coreboot July 2012

coreboot@coreboot.org

35 participants
639 discussions

seeking AMD 990FX / SB950 documentation
by David Griffith 21 Jul '12

21 Jul '12

Would someone please point out where I can get documentation on the AMD 990FX / SB950 north and south bridges? The 800 series stuff is at support.amd.com, but not these. -- David Griffith dave(a)661.org

3 2

New patch to review for coreboot: e63d25f msrtool: Add new "-lf" option to decode all MSRs
by Anton Kochkov 21 Jul '12

21 Jul '12

Anton Kochkov (anton.kochkov(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1260 -gerrit commit e63d25feacf674b9e07bc9b71bba8f03a09d5fe7 Author: Anton Kochkov <anton.kochkov(a)gmail.com> Date: Sat Jul 21 11:14:50 2012 +0400 msrtool: Add new "-lf" option to decode all MSRs Added new -lf option - list all read only MSRs and force decoding them for detected or selected platform. Change-Id: I237583618d0af72512b6084bd3486b67c9af54ba Signed-off-by: Anton Kochkov <anton.kochkov(a)gmail.com> --- util/msrtool/linux.c | 1 + util/msrtool/msrtool.c | 17 +++++++++++++++-- util/msrtool/msrtool.h | 1 + util/msrtool/msrutils.c | 33 +++++++++++++++++++++++++++++++++ 4 files changed, 50 insertions(+), 2 deletions(-) diff --git a/util/msrtool/linux.c b/util/msrtool/linux.c index ac94d80..e6df1b8 100644 --- a/util/msrtool/linux.c +++ b/util/msrtool/linux.c @@ -78,6 +78,7 @@ int linux_close(uint8_t cpu) { int linux_rdmsr(uint8_t cpu, uint32_t addr, struct msr *val) { struct msr tmp; if (lseek(msr_fd[cpu], addr, SEEK_SET) == -1) { + printf("linux_rdmsr(): cpu = %d\n", cpu); SYSERROR(lseek, addr); return 0; } diff --git a/util/msrtool/msrtool.c b/util/msrtool/msrtool.c index 433fc32..0a4c998 100644 --- a/util/msrtool/msrtool.c +++ b/util/msrtool/msrtool.c @@ -71,6 +71,7 @@ static void syntax(char *argv[]) { printf(" -r\t include [Reserved] values\n"); printf(" -k\t list all known systems and targets\n"); printf(" -l\t list MSRs and bit fields for current target(s) (-kl for ALL targets!)\n"); + printf(" -lf\t list MSRs and enforce decoding for current target\n"); printf(" -c\t access MSRs on the specified CPU, default=%d\n", DEFAULT_CPU); printf(" -m\t force a system, e.g: -m linux\n"); printf(" -t\t force a target, can be used multiple times, e.g: -t geodelx -t cs5536\n"); @@ -270,11 +271,11 @@ int main(int argc, char *argv[]) { int ret = 1; const struct sysdef *s; const struct targetdef *t; - uint8_t tn, listmsrs = 0, listknown = 0, input = 0; + uint8_t tn, listmsrs = 0, listknown = 0, input = 0, forcedecode = 0; uint32_t addr = 0; const char *streamfn = NULL, *difffn = NULL; struct msr msrval = MSR2(-1, -1); - while ((c = getopt(argc, argv, "hqvrklc:m:t:a:i:s:d:")) != -1) + while ((c = getopt(argc, argv, "hqvrklfc:m:t:a:i:s:d:")) != -1) switch (c) { case 'h': syntax(argv); @@ -294,6 +295,9 @@ int main(int argc, char *argv[]) { case 'l': listmsrs = 1; break; + case 'f': + forcedecode = 1; + break; case 'c': cpu = atoi(optarg); break; @@ -395,6 +399,15 @@ int main(int argc, char *argv[]) { } if (listmsrs) { + if (forcedecode) { + for (tn = 0; tn < targets_found; tn++) { + if (tn) + printf("\n"); + dumpmsrs(targets[tn], cpu); + } + printf("\n"); + return 0; + } if (streamfn) return do_stream(streamfn, 1); for (tn = 0; tn < targets_found; tn++) { diff --git a/util/msrtool/msrtool.h b/util/msrtool/msrtool.h index 73671e5..25ddc6d 100644 --- a/util/msrtool/msrtool.h +++ b/util/msrtool/msrtool.h @@ -172,6 +172,7 @@ const struct msrdef *findmsrdef(const uint32_t addr); uint32_t msraddrbyname(const char *name); void dumpmsrdefs(const struct targetdef *t); int dumpmsrdefsvals(FILE *f, const struct targetdef *t, const uint8_t cpu); +int dumpmsrs(const struct targetdef *t, const uint8_t cpu); uint8_t str2msr(char *str, struct msr *msr, char **endptr); void decodemsr(const uint8_t cpu, const uint32_t addr, const struct msr val); uint8_t diff_msr(FILE *fout, const uint32_t addr, const struct msr a, const struct msr b); diff --git a/util/msrtool/msrutils.c b/util/msrtool/msrutils.c index 2ceb60c..922df14 100644 --- a/util/msrtool/msrutils.c +++ b/util/msrtool/msrutils.c @@ -211,6 +211,39 @@ int dumpmsrdefsvals(FILE *f, const struct targetdef *t, const uint8_t cpu) { return 0; } +int dumpmsrs(const struct targetdef *t, const uint8_t cpu) { + struct msr bitval, mask; + struct msr val = MSR1(0); + const struct msrdef *m; + const struct msrbits *mb; + if (NULL == t) + return 1; + if (!sys->open(cpu, SYS_RDONLY)) + return 1; + printf("# %s MSRs:\n", t->name); + for (m = t->msrs; !MSR_ISEOT(*m); m++) { + if (t->msrs != m) + printf("\n"); + if (m->type != MSRTYPE_WRONLY) { + if (!sys->rdmsr(cpu, m->addr, &val)) + return 1; + printf("# %s\n", m->symbol); + for (mb = m->bits; mb->size; mb++) { + if (!reserved && 0 == strcmp(mb->name, "RSVD")) + continue; + print_bitdef(stdout, mb, " = "); + mask.hi = mask.lo = 0xffffffff; + mask = msr_shr(mask, 64 - mb->size); + bitval = msr_shr(val, mb->start - mb->size + 1); + msr_and(&bitval, mask); + print_bitval(stdout, mb, bitval); + } + } + } + sys->close(cpu); + return 0; +} + /** * Parse a hexadecimal string into an MSR value. *

1 0

New patch to review for coreboot: 23a3206 msrtool: CPU probe functions call cpuid only once
by Anton Kochkov 21 Jul '12

21 Jul '12

Anton Kochkov (anton.kochkov(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1259 -gerrit commit 23a32066e98c3e90651e51ccc5adf7c34b16558f Author: Anton Kochkov <anton.kochkov(a)gmail.com> Date: Sat Jul 21 07:29:48 2012 +0400 msrtool: CPU probe functions call cpuid only once Fixed CPU probing by calling cpuid only once and then using result as argument for all probe functions. Change-Id: Icd615636207499cfa46b8b99bf819ef8ca2d97c0 Signed-off-by: Anton Kochkov <anton.kochkov(a)gmail.com> --- util/msrtool/cs5536.c | 2 +- util/msrtool/geodegx2.c | 3 +- util/msrtool/geodelx.c | 3 +- util/msrtool/intel_core1.c | 3 +- util/msrtool/intel_core2_early.c | 3 +- util/msrtool/intel_core2_later.c | 3 +- util/msrtool/intel_nehalem.c | 3 +- util/msrtool/intel_pentium3.c | 3 +- util/msrtool/intel_pentium3_early.c | 3 +- util/msrtool/intel_pentium4_early.c | 3 +- util/msrtool/intel_pentium4_later.c | 3 +- util/msrtool/k8.c | 3 +- util/msrtool/msrtool.c | 7 +++- util/msrtool/msrtool.h | 49 +++++++++++++++++------------------ 14 files changed, 41 insertions(+), 50 deletions(-) diff --git a/util/msrtool/cs5536.c b/util/msrtool/cs5536.c index 666a93a..aa3a0e8 100644 --- a/util/msrtool/cs5536.c +++ b/util/msrtool/cs5536.c @@ -19,7 +19,7 @@ #include "msrtool.h" -int cs5536_probe(const struct targetdef *target) { +int cs5536_probe(const struct cpuid_t *id, const struct targetdef *target) { return (NULL != pci_dev_find(0x1022, 0x2090)); } diff --git a/util/msrtool/geodegx2.c b/util/msrtool/geodegx2.c index ae5d887..b617c29 100644 --- a/util/msrtool/geodegx2.c +++ b/util/msrtool/geodegx2.c @@ -20,8 +20,7 @@ #include "msrtool.h" -int geodegx2_probe(const struct targetdef *target) { - struct cpuid_t *id = cpuid(); +int geodegx2_probe(const struct cpuid_t *id, const struct targetdef *target) { return 5 == id->family && 5 == id->model; } diff --git a/util/msrtool/geodelx.c b/util/msrtool/geodelx.c index 063e031..1d644f3 100644 --- a/util/msrtool/geodelx.c +++ b/util/msrtool/geodelx.c @@ -19,8 +19,7 @@ #include "msrtool.h" -int geodelx_probe(const struct targetdef *target) { - struct cpuid_t *id = cpuid(); +int geodelx_probe(const struct cpuid_t *id, const struct targetdef *target) { return 5 == id->family && 10 == id->model; } diff --git a/util/msrtool/intel_core1.c b/util/msrtool/intel_core1.c index 1ebc7df..07c9de6 100644 --- a/util/msrtool/intel_core1.c +++ b/util/msrtool/intel_core1.c @@ -19,8 +19,7 @@ #include "msrtool.h" -int intel_core1_probe(const struct targetdef *target) { - struct cpuid_t *id = cpuid(); +int intel_core1_probe(const struct cpuid_t *id, const struct targetdef *target) { return ((0x6 == id->family) && (0xe == id->model)); } diff --git a/util/msrtool/intel_core2_early.c b/util/msrtool/intel_core2_early.c index 674d7db..ed02198 100644 --- a/util/msrtool/intel_core2_early.c +++ b/util/msrtool/intel_core2_early.c @@ -19,8 +19,7 @@ #include "msrtool.h" -int intel_core2_early_probe(const struct targetdef *target) { - struct cpuid_t *id = cpuid(); +int intel_core2_early_probe(const struct cpuid_t *id, const struct targetdef *target) { return ((0x6 == id->family) && (0xf == id->model)); } diff --git a/util/msrtool/intel_core2_later.c b/util/msrtool/intel_core2_later.c index 1c06c43..40f6723 100644 --- a/util/msrtool/intel_core2_later.c +++ b/util/msrtool/intel_core2_later.c @@ -19,8 +19,7 @@ #include "msrtool.h" -int intel_core2_later_probe(const struct targetdef *target) { - struct cpuid_t *id = cpuid(); +int intel_core2_later_probe(const struct cpuid_t *id, const struct targetdef *target) { return ((0x6 == id->family)&(0x17 == id->model)); } diff --git a/util/msrtool/intel_nehalem.c b/util/msrtool/intel_nehalem.c index e69fe57..f1afa17 100644 --- a/util/msrtool/intel_nehalem.c +++ b/util/msrtool/intel_nehalem.c @@ -19,8 +19,7 @@ #include "msrtool.h" -int intel_nehalem_probe(const struct targetdef *target) { - struct cpuid_t *id = cpuid(); +int intel_nehalem_probe(const struct cpuid_t *id, const struct targetdef *target) { return ((0x6 == id->family) && ( (0x1a == id->model) || (0x1e == id->model) || diff --git a/util/msrtool/intel_pentium3.c b/util/msrtool/intel_pentium3.c index 442ae3d..b39ca99 100644 --- a/util/msrtool/intel_pentium3.c +++ b/util/msrtool/intel_pentium3.c @@ -19,8 +19,7 @@ #include "msrtool.h" -int intel_pentium3_probe(const struct targetdef *target) { - struct cpuid_t *id = cpuid(); +int intel_pentium3_probe(const struct cpuid_t *id, const struct targetdef *target) { return ((0x6 == id->family) && ( (0xa == id->model) || (0xb == id->model) diff --git a/util/msrtool/intel_pentium3_early.c b/util/msrtool/intel_pentium3_early.c index ced3037..edd294b 100644 --- a/util/msrtool/intel_pentium3_early.c +++ b/util/msrtool/intel_pentium3_early.c @@ -19,8 +19,7 @@ #include "msrtool.h" -int intel_pentium3_early_probe(const struct targetdef *target) { - struct cpuid_t *id = cpuid(); +int intel_pentium3_early_probe(const struct cpuid_t *id, const struct targetdef *target) { return ((0x6 == id->family) && ( (0x7 == id->model) || (0x8 == id->model) diff --git a/util/msrtool/intel_pentium4_early.c b/util/msrtool/intel_pentium4_early.c index cb6c53e..087c42b 100644 --- a/util/msrtool/intel_pentium4_early.c +++ b/util/msrtool/intel_pentium4_early.c @@ -19,8 +19,7 @@ #include "msrtool.h" -int intel_pentium4_early_probe(const struct targetdef *target) { - struct cpuid_t *id = cpuid(); +int intel_pentium4_early_probe(const struct cpuid_t *id, const struct targetdef *target) { return ((0xf == id->family) && (0x2 == id->model)); } diff --git a/util/msrtool/intel_pentium4_later.c b/util/msrtool/intel_pentium4_later.c index 7c077ee..d8d592e 100644 --- a/util/msrtool/intel_pentium4_later.c +++ b/util/msrtool/intel_pentium4_later.c @@ -19,8 +19,7 @@ #include "msrtool.h" -int intel_pentium4_later_probe(const struct targetdef *target) { - struct cpuid_t *id = cpuid(); +int intel_pentium4_later_probe(const struct cpuid_t *id, const struct targetdef *target) { return ((0xf == id->family) && ( (0x3 == id->model) || (0x4 == id->model) diff --git a/util/msrtool/k8.c b/util/msrtool/k8.c index 6d2500d..66114db 100644 --- a/util/msrtool/k8.c +++ b/util/msrtool/k8.c @@ -19,8 +19,7 @@ #include "msrtool.h" -int k8_probe(const struct targetdef *target) { - struct cpuid_t *id = cpuid(); +int k8_probe(const struct cpuid_t *id, const struct targetdef *target) { return 0xF == id->family; } diff --git a/util/msrtool/msrtool.c b/util/msrtool/msrtool.c index 433fc32..6f66234 100644 --- a/util/msrtool/msrtool.c +++ b/util/msrtool/msrtool.c @@ -270,6 +270,7 @@ int main(int argc, char *argv[]) { int ret = 1; const struct sysdef *s; const struct targetdef *t; + const struct cpuid_t *id; uint8_t tn, listmsrs = 0, listknown = 0, input = 0; uint32_t addr = 0; const char *streamfn = NULL, *difffn = NULL; @@ -354,14 +355,16 @@ int main(int argc, char *argv[]) { if (targets) for (tn = 0; tn < targets_found; tn++) printf_quiet("Forced target %s: %s\n", targets[tn]->name, targets[tn]->prettyname); - else + else { + id = cpuid(); for (t = alltargets; !TARGET_ISEOT(*t); t++) { printf_verbose("Probing for target %s: %s\n", t->name, t->prettyname); - if (!t->probe(t)) + if (!t->probe(id, t)) continue; printf_quiet("Detected target %s: %s\n", t->name, t->prettyname); add_target(t); } + } printf_quiet("\n"); fflush(stdout); diff --git a/util/msrtool/msrtool.h b/util/msrtool/msrtool.h index 73671e5..7bee97d 100644 --- a/util/msrtool/msrtool.h +++ b/util/msrtool/msrtool.h @@ -97,10 +97,21 @@ struct msrdef { #define MAX_CORES 8 +typedef enum { VENDOR_INTEL = 1, VENDOR_AMD = 2 } vendor_t; + +struct cpuid_t { + uint8_t family; + uint8_t model; + uint8_t stepping; + uint8_t ext_family; + uint8_t ext_model; + vendor_t vendor; +}; + struct targetdef { const char *name; const char *prettyname; - int (*probe)(const struct targetdef *target); + int (*probe)(const struct cpuid_t *id, const struct targetdef *target); const struct msrdef *msrs; }; @@ -126,18 +137,6 @@ struct sysdef { #define SYSTEM_EOT .name = NULL #define SYSTEM_ISEOT(s) (NULL == (s).name) -typedef enum { VENDOR_INTEL = 1, VENDOR_AMD = 2 } vendor_t; - -struct cpuid_t { - uint8_t family; - uint8_t model; - uint8_t stepping; - uint8_t ext_family; - uint8_t ext_model; - vendor_t vendor; -}; - - extern const struct sysdef *sys; extern uint8_t targets_found; @@ -201,51 +200,51 @@ extern int freebsd_rdmsr(uint8_t cpu, uint32_t addr, struct msr *val); /** target externs **/ /* geodegx2.c */ -extern int geodegx2_probe(const struct targetdef *t); +extern int geodegx2_probe(const struct cpuid_t *id, const struct targetdef *t); extern const struct msrdef geodegx2_msrs[]; /* geodelx.c */ -extern int geodelx_probe(const struct targetdef *t); +extern int geodelx_probe(const struct cpuid_t *id, const struct targetdef *t); extern const struct msrdef geodelx_msrs[]; /* cs5536.c */ -extern int cs5536_probe(const struct targetdef *t); +extern int cs5536_probe(const struct cpuid_t *id, const struct targetdef *t); extern const struct msrdef cs5536_msrs[]; /* k8.c */ -extern int k8_probe(const struct targetdef *t); +extern int k8_probe(const struct cpuid_t *id, const struct targetdef *t); extern const struct msrdef k8_msrs[]; /* intel_pentium3_early.c */ -extern int intel_pentium3_early_probe(const struct targetdef *t); +extern int intel_pentium3_early_probe(const struct cpuid_t *id, const struct targetdef *t); extern const struct msrdef intel_pentium3_early_msrs[]; /* intel_pentium3.c */ -extern int intel_pentium3_probe(const struct targetdef *t); +extern int intel_pentium3_probe(const struct cpuid_t *id, const struct targetdef *t); extern const struct msrdef intel_pentium3_msrs[]; /* intel_core1.c */ -extern int intel_core1_probe(const struct targetdef *t); +extern int intel_core1_probe(const struct cpuid_t *id, const struct targetdef *t); extern const struct msrdef intel_core1_msrs[]; /* intel_core2_early.c */ -extern int intel_core2_early_probe(const struct targetdef *t); +extern int intel_core2_early_probe(const struct cpuid_t *id, const struct targetdef *t); extern const struct msrdef intel_core2_early_msrs[]; /* intel_core2_later.c */ -extern int intel_core2_later_probe(const struct targetdef *t); +extern int intel_core2_later_probe(const struct cpuid_t *id, const struct targetdef *t); extern const struct msrdef intel_core2_later_msrs[]; /* intel_pentium4_early.c */ -extern int intel_pentium4_early_probe(const struct targetdef *t); +extern int intel_pentium4_early_probe(const struct cpuid_t *id, const struct targetdef *t); extern const struct msrdef intel_pentium4_early_msrs[]; /* intel_pentium4_later.c */ -extern int intel_pentium4_later_probe(const struct targetdef *t); +extern int intel_pentium4_later_probe(const struct cpuid_t *id, const struct targetdef *t); extern const struct msrdef intel_pentium4_later_msrs[]; /* intel_nehalem.c */ -extern int intel_nehalem_probe(const struct targetdef *t); +extern int intel_nehalem_probe(const struct cpuid_t *id, const struct targetdef *t); extern const struct msrdef intel_nehalem_msrs[]; #endif /* MSRTOOL_H */

1 0

New patch to review for coreboot: 997a8ea inteltool: Add support for H65 Express chipset
by Anton Kochkov 21 Jul '12

21 Jul '12

Anton Kochkov (anton.kochkov(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1258 -gerrit commit 997a8ea9bcf8352871f380665798a424ef0f60f4 Author: Anton Kochkov <anton.kochkov(a)gmail.com> Date: Sat Jul 21 06:36:47 2012 +0400 inteltool: Add support for H65 Express chipset Added few MCH and DMI registers for H65E. Description of them can be found at "2nd Generation Intel Core Processors Family datasheet" Change-Id: If4fee35bb5a09b04ea0684be9cbd3c1e9084b934 Signed-off-by: Anton Kochkov <anton.kochkov(a)gmail.com> --- util/inteltool/inteltool.c | 1 + util/inteltool/inteltool.h | 2 + util/inteltool/memory.c | 84 +++++++++++++++++++++++++++++++++++++++- util/inteltool/pcie.c | 90 ++++++++++++++++++++++++++++++++++++++++++- 4 files changed, 171 insertions(+), 6 deletions(-) diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index ef354f2..56bbc4a 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -54,6 +54,7 @@ static const struct { { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82G33, "P35/G33/G31/P31" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82Q33, "Q33" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X58, "X58" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM65E, "HM65 Express" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GS45, "GS45ME" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ATOM_DXXX, "Atom D400/500 Series" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ATOM_NXXX, "Atom N400 Series" }, diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index 22ebc3d..aa8a292 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -102,6 +102,8 @@ /* 82371AB/EB/MB use the same device ID value. */ #define PCI_DEVICE_ID_INTEL_82371XX 0x7110 +#define PCI_DEVICE_ID_INTEL_HM65E 0x0104 + #define ARRAY_SIZE(a) ((int)(sizeof(a) / sizeof((a)[0]))) #if !defined(__DARWIN__) && !defined(__FreeBSD__) diff --git a/util/inteltool/memory.c b/util/inteltool/memory.c index 18300ac..d66ee48 100644 --- a/util/inteltool/memory.c +++ b/util/inteltool/memory.c @@ -23,6 +23,47 @@ #include <inttypes.h> #include "inteltool.h" +static const io_register_t sandybridge_mch_registers[] = { +/* Channel 0 */ + { 0x4000, 4, "TC_DBP_C0" }, // Timing of DDR Bin Parameters + { 0x4004, 4, "TC_RAP_C0" }, // Timing of DDR Regular Access Parameters + { 0x4028, 4, "SC_IO_LATENCY_C0" }, // IO Latency Configuration + { 0x42A4, 4, "TC_SRFTP_C0" }, // Self-Refresh Timing Parameters + { 0x40B0, 4, "PM_PDWN_config_C0" }, // Power-down Configuration + { 0x4294, 4, "TC_RFP_C0" }, // Refresh Parameters + { 0x4298, 4, "TC_RFTP_C0" }, // Refresh Timing Parameters +/* Channel 1 */ + { 0x4400, 4, "TC_DBP_C1" }, // Timing of DDR Bin Parameters + { 0x4404, 4, "TC_RAP_C1" }, // Timing of DDR Regular Access Parameters + { 0x4428, 4, "SC_IO_LATENCY_C1" }, // IO Latency Configuration + { 0x46A4, 4, "TC_SRFTP_C1" }, // Self-Refresh Timing Parameters + { 0x44B0, 4, "PM_PDWN_config_C1" }, // Power-down Configuration + { 0x4694, 4, "TC_RFP_C1" }, // Refresh Parameters + { 0x4698, 4, "TC_RFTP_C1" }, // Refresh Timing Parameters +/* Integrated Memory Peripheral Hub (IMPH) */ + { 0x740C, 4, "CRDTCTL3" }, // Credit Control 3 +/* Common Registers */ + { 0x5000, 4, "MAD_CHNL" }, // Address decoder Channel Configuration + { 0x5004, 4, "MAD_DIMM_ch0" }, // Address Decode Channel 0 + { 0x5008, 4, "MAD_DIMM_ch1" }, // Address Decode Channel 1 + { 0x5060, 4, "PM_SREF_config" }, // Self Refresh Configuration +/* MMIO Registers Broadcast Group */ + { 0x4CB0, 4, "PM_PDWN_config" }, // Power-down Configuration + { 0x4F84, 4, "PM_CMD_PWR" }, // Power Management Command Power + { 0x4F88, 4, "PM_BW_LIMIT_config" }, // BW Limit Configuration + { 0x4F8C, 4, "RESERVED" }, // Reserved, default value - 0xFF1D1519 +/* PCU MCHBAR Registers */ + { 0x5880, 4, "MEM_TRML_ESTIMATION_CONFIG" }, // Memory Thermal Estimation Configuration + { 0x5884, 4, "RESERVED" }, // Reserved + { 0x5888, 4, "MEM_TRML_THRESHOLDS_CONFIG" }, // Memory Thermal Thresholds Configuration + { 0x58A0, 4, "MEM_TRML_STATUS_REPORT" }, // Memory Thermal Status Report + { 0x58A4, 4, "MEM_TRML_TEMPERATURE_REPORT" }, // Memory Thermal Temperature Report + { 0x58A8, 4, "MEM_TRML_INTERRUPT" }, // Memory Thermal Interrupt + { 0x5948, 4, "GT_PERF_STATUS" }, // GT Performance Status + { 0x5998, 4, "RP_STATE_CAP" }, // RP State Capability + { 0x5D10, 8, "SSKPD" }, // Sticky Scratchpad Data +}; + /* * (G)MCH MMIO Config Space */ @@ -31,6 +72,7 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc) int i, size = (16 * 1024); volatile uint8_t *mchbar; uint64_t mchbar_phys; + const io_register_t *mch_registers = NULL; struct pci_dev *nb_device6; /* "overflow device" on i865 */ uint16_t pcicmd6; @@ -115,6 +157,11 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc) mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe; mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32; break; + case PCI_DEVICE_ID_INTEL_HM65E: + mchbar_phys = pci_read_long(nb, 0x48) & 0xffff8000; + mch_registers = sandybridge_mch_registers; + size = ARRAY_SIZE(sandybridge_mch_registers); + break; default: printf("Error: Dumping MCHBAR on this northbridge is not (yet) supported.\n"); return 1; @@ -135,9 +182,40 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc) else printf("MCHBAR = 0x%08" PRIx64 " (MEM)\n\n", mchbar_phys); - for (i = 0; i < size; i += 4) { - if (*(uint32_t *)(mchbar + i)) - printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(mchbar+i)); + if (mch_registers != NULL) { + for (i = 0; i < size; i++) { + switch (mch_registers[i].size) { + case 8: + printf("mchbase+0x%04x: 0x%08lx (%s)\n", + mch_registers[i].addr, + *(uint64_t *)(mchbar+mch_registers[i].addr), + mch_registers[i].name); + break; + case 4: + printf("mchbase+0x%04x: 0x%08x (%s)\n", + mch_registers[i].addr, + *(uint32_t *)(mchbar+mch_registers[i].addr), + mch_registers[i].name); + break; + case 2: + printf("mchbase+0x%04x: 0x%04x (%s)\n", + mch_registers[i].addr, + *(uint16_t *)(mchbar+mch_registers[i].addr), + mch_registers[i].name); + break; + case 1: + printf("mchbase+0x%04x: 0x%02x (%s)\n", + mch_registers[i].addr, + *(uint8_t *)(mchbar+mch_registers[i].addr), + mch_registers[i].name); + break; + } + } + } else { + for (i = 0; i < size; i += 4) { + if (*(uint32_t *)(mchbar + i)) + printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(mchbar+i)); + } } unmap_physical((void *)mchbar, size); diff --git a/util/inteltool/pcie.c b/util/inteltool/pcie.c index ea23835..a7429a0 100644 --- a/util/inteltool/pcie.c +++ b/util/inteltool/pcie.c @@ -2,6 +2,7 @@ * inteltool - dump all registers on an Intel CPU + chipset based system. * * Copyright (C) 2008-2010 by coresystems GmbH + * Copyright (C) 2012 Anton Kochkov * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -22,6 +23,58 @@ #include <inttypes.h> #include "inteltool.h" +static const io_register_t sandybridge_dmi_registers[] = { + { 0x00, 4, "DMI VCECH" }, // DMI Virtual Channel Enhanced Capability + { 0x04, 4, "DMI PVCCAP1" }, // DMI Port VC Capability Register 1 + { 0x08, 4, "DMI PVVAP2" }, // DMI Port VC Capability Register 2 + { 0x0C, 2, "DMI PVCCTL" }, // DMI Port VC Control +/* { 0x0E, 2, "RSVD" }, // Reserved */ + { 0x10, 4, "DMI VC0RCAP" }, // DMI VC0 Resource Capability + { 0x14, 4, "DMI VC0RCTL" }, // DMI VC0 Resource Control +/* { 0x18, 2, "RSVD" }, // Reserved */ + { 0x1A, 2, "DMI VC0RSTS" }, // DMI VC0 Resource Status + { 0x1C, 4, "DMI VC1RCAP" }, // DMI VC1 Resource Capability + { 0x20, 4, "DMI VC1RCTL" }, // DMI VC1 Resource Control +/* { 0x24, 2, "RSVD" }, // Reserved */ + { 0x26, 2, "DMI VC1RSTS" }, // DMI VC1 Resource Status + { 0x28, 4, "DMI VCPRCAP" }, // DMI VCp Resource Capability + { 0x2C, 4, "DMI VCPRCTL" }, // DMI VCp Resource Control +/* { 0x30, 2, "RSVD" }, // Reserved */ + { 0x32, 2, "DMI VCPRSTS" }, // DMI VCp Resource Status + { 0x34, 4, "DMI VCMRCAP" }, // DMI VCm Resource Capability + { 0x38, 4, "DMI VCMRCTL" }, // DMI VCm Resource Control +/* { 0x3C, 2, "RSVD" }, // Reserved */ + { 0x3E, 2, "DMI VCMRSTS" }, // DMI VCm Resource Status +/* { 0x40, 4, "RSVD" }, // Reserved */ + { 0x44, 4, "DMI ESC" }, // DMI Element Self Description +/* { 0x48, 8, "RSVD" }, // Reserved */ + { 0x50, 4, "DMI LE1D" }, // DMI Link Entry 1 Description +/* { 0x54, 4, "RSVD" }, // Reserved */ + { 0x58, 4, "DMI LE1A" }, // DMI Link Entry 1 Address + { 0x5C, 4, "DMI LUE1A" }, // DMI Link Upper Entry 1 Address + { 0x60, 4, "DMI LE2D" }, // DMI Link Entry 2 Description +/* { 0x64, 4, "RSVD" }, // Reserved */ + { 0x68, 4, "DMI LE2A" }, // DMI Link Entry 2 Address +/* { 0x6C, 4, "RSVD" }, // Reserved + { 0x70, 8, "RSVD" }, // Reserved + { 0x78, 8, "RSVD" }, // Reserved + { 0x80, 4, "RSVD" }, // Reserved */ + { 0x84, 4, "LCAP" }, // Link Capabilities + { 0x88, 2, "LCTL" }, // Link Control + { 0x8A, 2, "LSTS" }, // Link Status +/* { 0x8C, 4, "RSVD" }, // Reserved + { 0x90, 4, "RSVD" }, // Reserved + { 0x94, 4, "RSVD" }, // Reserved */ + { 0x98, 2, "LCTL2" }, // Link Control 2 + { 0x9A, 2, "LSTS2" }, // Link Status 2 +/* ... - Reserved */ + { 0xBC0, 4, "AFE_BMUF0" }, // AFE BMU Configuration Function 0 + { 0xBC4, 4, "RSVD" }, // Reserved + { 0xBC8, 4, "RSVD" }, // Reserved + { 0xBCC, 4, "AFE_BMUT0" }, // AFE BMU Configuration Test 0 +/* ... - Reserved */ +}; + /* * Egress Port Root Complex MMIO configuration space */ @@ -91,6 +144,7 @@ int print_dmibar(struct pci_dev *nb) int i, size = (4 * 1024); volatile uint8_t *dmibar; uint64_t dmibar_phys; + const io_register_t *dmi_registers = NULL; printf("\n============= DMIBAR ============\n\n"); @@ -124,6 +178,11 @@ int print_dmibar(struct pci_dev *nb) case PCI_DEVICE_ID_INTEL_X58: dmibar_phys = pci_read_long(nb, 0x50) & 0xfffff000; break; + case PCI_DEVICE_ID_INTEL_HM65E: + dmibar_phys = pci_read_long(nb, 0x68) & 0xfffff000; + dmi_registers = sandybridge_dmi_registers; + size = ARRAY_SIZE(sandybridge_dmi_registers); + break; default: printf("Error: Dumping DMIBAR on this northbridge is not (yet) supported.\n"); return 1; @@ -137,9 +196,34 @@ int print_dmibar(struct pci_dev *nb) } printf("DMIBAR = 0x%08" PRIx64 " (MEM)\n\n", dmibar_phys); - for (i = 0; i < size; i += 4) { - if (*(uint32_t *)(dmibar + i)) - printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(dmibar+i)); + if (dmi_registers != NULL) { + for (i = 0; i < size; i++) { + switch (dmi_registers[i].size) { + case 4: + printf("dmibase+0x%04x: 0x%08x (%s)\n", + dmi_registers[i].addr, + *(uint32_t *)(dmibar+dmi_registers[i].addr), + dmi_registers[i].name); + break; + case 2: + printf("dmibase+0x%04x: 0x%04x (%s)\n", + dmi_registers[i].addr, + *(uint16_t *)(dmibar+dmi_registers[i].addr), + dmi_registers[i].name); + break; + case 1: + printf("dmibase+0x%04x: 0x%02x (%s)\n", + dmi_registers[i].addr, + *(uint8_t *)(dmibar+dmi_registers[i].addr), + dmi_registers[i].name); + break; + } + } + } else { + for (i = 0; i < size; i += 4) { + if (*(uint32_t *)(dmibar + i)) + printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(dmibar+i)); + } } unmap_physical((void *)dmibar, size);

1 0

Patch set updated for coreboot: 6517d04 VIA Nano: Add support for VIA Nano CPUs
by Alexandru Gagniuc 21 Jul '12

21 Jul '12

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1257 -gerrit commit 6517d04e47fa7ed5673ab79d640b3f317773a832 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Fri Jul 20 18:17:01 2012 -0500 VIA Nano: Add support for VIA Nano CPUs Add code to do the following for the VIA Nano CPUs - Update microcode - Set maximum frequency - Initialize power states - Set up cache Attempting to change the voltage or frequency of the CPU without applying the microcode update will hang the CPU, so we only do transitions if we can verify the microcode has been updated. The microcode is updated directly from CBFS. No microcode is included in ramstage. The microcode is not included in this commit. To get the microcode, run bios_extract on the manufacturer supplied BIOS, and look for the file marked "P6 Microcode". Include this file in CBFS. You can have the build system include this file automatically by selecting Expert Mode, then look under 'Chipset' -> 'Include CPU microcode in CBFS' -> Include external microcode file (check) 'Path and filename of CPU microcode' should contain the location of the microcode file previously extracted. Change-Id: I586aaca5715e047b42ef901d66772ace0e6b655e Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/cpu/via/Kconfig | 1 + src/cpu/via/Makefile.inc | 6 +- src/cpu/via/nano/Kconfig | 41 ++++++++ src/cpu/via/nano/Makefile.inc | 29 ++++++ src/cpu/via/nano/nano_init.c | 205 +++++++++++++++++++++++++++++++++++++++ src/cpu/via/nano/update_ucode.c | 150 ++++++++++++++++++++++++++++ src/cpu/via/nano/update_ucode.h | 72 ++++++++++++++ 7 files changed, 501 insertions(+), 3 deletions(-) diff --git a/src/cpu/via/Kconfig b/src/cpu/via/Kconfig index 570d408..5c38c91 100644 --- a/src/cpu/via/Kconfig +++ b/src/cpu/via/Kconfig @@ -1,2 +1,3 @@ source src/cpu/via/c3/Kconfig source src/cpu/via/c7/Kconfig +source src/cpu/via/nano/Kconfig diff --git a/src/cpu/via/Makefile.inc b/src/cpu/via/Makefile.inc index 2616111..f1e198d 100644 --- a/src/cpu/via/Makefile.inc +++ b/src/cpu/via/Makefile.inc @@ -1,3 +1,3 @@ -subdirs-$(CONFIG_CPU_VIA_C7) += c7 -subdirs-$(CONFIG_CPU_VIA_C3) += c3 - +subdirs-$(CONFIG_CPU_VIA_C7) += c7 +subdirs-$(CONFIG_CPU_VIA_C3) += c3 +subdirs-$(CONFIG_CPU_VIA_NANO) += nano diff --git a/src/cpu/via/nano/Kconfig b/src/cpu/via/nano/Kconfig new file mode 100644 index 0000000..4df3ab4 --- /dev/null +++ b/src/cpu/via/nano/Kconfig @@ -0,0 +1,41 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see <http://www.gnu.org/licenses/>. +## + +config CPU_VIA_NANO + bool + +if CPU_VIA_NANO + +config CPU_SPECIFIC_OPTIONS + def_bool y + select UDELAY_TSC + select MMX + select SSE2 + select CACHE_AS_RAM + select CPU_MICROCODE_FROM_CBFS + +config DCACHE_RAM_BASE + hex + default 0xffef0000 + +config DCACHE_RAM_SIZE + hex + default 0x8000 + +endif # CPU_VIA_NANO diff --git a/src/cpu/via/nano/Makefile.inc b/src/cpu/via/nano/Makefile.inc new file mode 100644 index 0000000..1a03620 --- /dev/null +++ b/src/cpu/via/nano/Makefile.inc @@ -0,0 +1,29 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see <http://www.gnu.org/licenses/>. +## + +subdirs-y += ../../x86/tsc +subdirs-y += ../../x86/mtrr +subdirs-y += ../../x86/lapic +subdirs-y += ../../x86/cache +subdirs-y += ../../x86/smm + +driver-y += nano_init.c +ramstage-y += update_ucode.c + +cpu_incs += $(src)/cpu/via/car/cache_as_ram.inc diff --git a/src/cpu/via/nano/nano_init.c b/src/cpu/via/nano/nano_init.c new file mode 100644 index 0000000..80f8813 --- /dev/null +++ b/src/cpu/via/nano/nano_init.c @@ -0,0 +1,205 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include "update_ucode.h" +#include <console/console.h> +#include <device/device.h> +#include <cpu/cpu.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/lapic.h> +#include <cpu/x86/cache.h> +#include <delay.h> + +#define MODEL_NANO 0x2 +#define MODEL_NANO_3000_B0 0x8 +#define MODEL_NANO_3000_B2 0xa + +#define MSR_IA32_PERF_STATUS 0x00000198 +#define MSR_IA32_PERF_CTL 0x00000199 +#define MSR_IA32_MISC_ENABLE 0x000001a0 +#define NANO_MYSTERIOUS_MSR 0x120e + +static void nano_finish_fid_vid_transition(void) +{ + + msr_t msr; + /* Wait until the power transition ends */ + int cnt = 0; + do { + udelay(16); + msr = rdmsr(MSR_IA32_PERF_STATUS); + cnt++; + if (cnt > 128) { + printk(BIOS_WARNING, + "Error while updating multiplier and voltage\n"); + break; + } + } while (msr.lo & ((1 << 16) | (1 << 17))); + + /* Print the new FID and Voltage */ + u8 cur_vid = (msr.lo >> 0) & 0xff; + u8 cur_fid = (msr.lo >> 8) & 0xff; + printk(BIOS_INFO, "New CPU multiplier: %dx\n", cur_fid); + printk(BIOS_INFO, "New Voltage ID : %dx\n", cur_vid); +} + +static void nano_set_max_fid_vid(void) +{ + msr_t msr; + /* Get voltage and frequency info */ + msr = rdmsr(MSR_IA32_PERF_STATUS); + u8 min_fid = (msr.hi >> 24); + u8 max_fid = (msr.hi >> 8) & 0xff; + u8 min_vid = (msr.hi >> 16) & 0xff; + u8 max_vid = (msr.hi >> 0) & 0xff; + u8 cur_vid = (msr.lo >> 0) & 0xff; + u8 cur_fid = (msr.lo >> 8) & 0xff; + + printk(BIOS_INFO, "CPU multiplier: %dx (min %dx; max %dx)\n", + cur_fid, min_fid, max_fid); + printk(BIOS_INFO, "Voltage ID : %dx (min %dx; max %dx)\n", + cur_vid, min_vid, max_vid); + + if( (cur_fid != max_fid) || (cur_vid != max_vid) ) { + /* Set highest frequency and VID */ + msr.lo = msr.hi; + msr.hi = 0; + wrmsr(MSR_IA32_PERF_CTL, msr); + /* Wait for the transition to complete, otherwise, the CPU + * might reset itself repeatedly */ + nano_finish_fid_vid_transition(); + } + /* As a side note, if we didn't update the microcode by this point, the + * second PLL will not lock correctly. The clock will still be provided + * by the first PLL, and execution will continue normally, ___until___ + * the CPU switches PLL. Once that happens we will no longer have a + * working clock source, and the CPU will hang + * Moral of the story: update the microcode, or don't change FID + * This check is handled before calling nano_power() */ +} + +static void nano_power(void) +{ + msr_t msr; + /* Enable Powersaver */ + msr = rdmsr(MSR_IA32_MISC_ENABLE); + msr.lo |= (1 << 16); + wrmsr(MSR_IA32_MISC_ENABLE, msr); + + /* Enable 6 bit or 7-bit VRM support + * This MSR is not documented by VIA docs, other than setting these + * bits */ + msr = rdmsr(NANO_MYSTERIOUS_MSR); + msr.lo |= ( (1<<7) | (1<<4) ); + /* FIXME: Do we have a 6-bit or 7-bit VRM? + * set bit [5] for 7-bit, or don't set it for 6 bit VRM + * This will probably require a Kconfig option + * My board has a 7-bit VRM, so I can't test the 6-bit VRM stuff */ + msr.lo |= (1<<5); + wrmsr(NANO_MYSTERIOUS_MSR, msr); + + /* Set the maximum frequency and voltage */ + nano_set_max_fid_vid(); + + /* Enable TM3 */ + msr = rdmsr(MSR_IA32_MISC_ENABLE); + msr.lo |= ( (1<<3) | (1<<13) ); + wrmsr(MSR_IA32_MISC_ENABLE, msr); + + u8 stepping = ( cpuid_eax(0x1) ) &0xf; + if(stepping >= MODEL_NANO_3000_B0) { + /* Hello Nano 3000. The Terminator needs a CPU upgrade */ + /* Enable C1e, C2e, C3e, and C4e states */ + msr = rdmsr(MSR_IA32_MISC_ENABLE); + msr.lo |= ( (1<<25) | (1<<26) | (1<<31)); /* C1e, C2e, C3e */ + msr.hi |= (1<<0); /* C4e */ + wrmsr(MSR_IA32_MISC_ENABLE, msr); + } + + /* Lock on Powersaver */ + msr = rdmsr(MSR_IA32_MISC_ENABLE); + msr.lo |= (1<<20); + wrmsr(MSR_IA32_MISC_ENABLE, msr); +} + +static void nano_init(device_t dev) +{ + print_debug(" Nano POWER:\n"); + struct cpuinfo_x86 c; + + get_fms(&c, dev->device); + + /* We didn't test this on the Nano 1000/2000 series, so warn the user */ + if(c.x86_mask < MODEL_NANO_3000_B0) { + printk(BIOS_EMERG, "WARNING: This CPU has not been tested. " + "Please report any issues encountered. \n"); + } + switch (c.x86_mask) { + case MODEL_NANO: + printk(BIOS_INFO, "VIA Nano"); + break; + case MODEL_NANO_3000_B0: + printk(BIOS_INFO, "VIA Nano 3000 rev B0"); + break; + case MODEL_NANO_3000_B2: + printk(BIOS_INFO, "VIA Nano 3000 rev B2"); + break; + default: + printk(BIOS_EMERG, "Stepping not recognized: %x\n", c.x86_mask); + } + printk(BIOS_INFO, "\n"); + + /* We only read microcode from CBFS. If we don't have any microcode in + * CBFS, we'll just get back with 0 updates. User choice FTW. */ + unsigned int n_updates = nano_update_ucode(); + + if(n_updates != 0){ + nano_power(); + } else { + /* Changing the frequency or voltage without first updating the + * microcode will hang the CPU, so just don't do it */ + printk(BIOS_EMERG, "WARNING: CPU Microcode not updated.\n" + " Will not change frequency, as this may hang the CPU.\n"); + } + + /* Turn on cache */ + x86_enable_cache(); + /* Set up Memory Type Range Registers */ + x86_setup_mtrrs(); + x86_mtrr_check(); + /* Enable the local cpu apics */ + setup_lapic(); +} + +static struct device_operations cpu_dev_ops = { + .init = nano_init, +}; + +static struct cpu_device_id cpu_table[] = { + {X86_VENDOR_CENTAUR, 0x06f2}, // VIA NANO 1000/2000 Series + {X86_VENDOR_CENTAUR, 0x06f8}, // VIA NANO 3000 rev B0 + {X86_VENDOR_CENTAUR, 0x06fa}, // VIA NANO 3000 rev B2 + {0, 0}, +}; + +static const struct cpu_driver driver __cpu_driver = { + .ops = &cpu_dev_ops, + .id_table = cpu_table, +}; diff --git a/src/cpu/via/nano/update_ucode.c b/src/cpu/via/nano/update_ucode.c new file mode 100644 index 0000000..9ade518 --- /dev/null +++ b/src/cpu/via/nano/update_ucode.c @@ -0,0 +1,150 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include "update_ucode.h" +#include <cpu/x86/msr.h> +#include <console/console.h> +#include <stddef.h> +#include <cpu/cpu.h> +#include <arch/cpu.h> +#include <cbfs.h> + +static ucode_update_status nano_apply_ucode(const nano_ucode_header *ucode) +{ + printk(BIOS_SPEW, "Attempting to apply microcode update\n"); + + msr_t msr; + /* Address of ucode block goes in msr.lo for 32-bit mode + * Now remember, we need to pass the address of the actual microcode, + * not the header. The header is just there to help us. */ + msr.lo = (unsigned int)(&(ucode->ucode_start)); + msr.hi = 0; + wrmsr(MSR_IA32_BIOS_UPDT_TRIG, msr); + + /* Let's see if we updated succesfully */ + msr = rdmsr(MSR_UCODE_UPDATE_STATUS); + + return msr.lo & 0x07; +} + +static void nano_print_ucode_info(const nano_ucode_header *ucode) +{ + printk(BIOS_SPEW, "Microcode update information:\n"); + printk(BIOS_SPEW, "Name: %8s\n", ucode->name ); + printk(BIOS_SPEW, "Date: %u/%u/%u\n", ucode->month, + ucode->day, ucode->year ); +} + +static ucode_validity nano_ucode_is_valid(const nano_ucode_header *ucode) +{ + /* We must have a valid signature */ + if(ucode->signature != NANO_UCODE_SIGNATURE) + return NANO_UCODE_SIGNATURE_ERROR; + /* The size of the head must be exactly 12 double words */ + if( (ucode->total_size - ucode->payload_size) != NANO_UCODE_HEADER_SIZE) + return NANO_UCODE_WRONG_SIZE; + + /* How about a checksum ? Checksum must be 0 + * Two's complement done over the entire file, including the header */ + int i; + u32 check = 0; + u32 *raw = (void*) ucode; + for(i = 0 ; i < ((ucode->total_size) >> 2); i++) { + check += raw[i]; + } + if(check != 0) + return NANO_UCODE_CHECKSUM_FAIL; + /* Made it here huh? Then it looks valid to us. + * If there's anything else wrong, the CPU will reject the update */ + return NANO_UCODE_VALID; +} + +static void nano_print_ucode_status(ucode_update_status stat) +{ + switch(stat) + { + case UCODE_UPDATE_SUCCESS: + printk(BIOS_INFO, "Microcode update succesful.\n"); + break; + case UCODE_UPDATE_FAIL: + printk(BIOS_ALERT, "Microcode update failed, bad environment." + "Update was not applied.\n"); + break; + case UCODE_UPDATE_WRONG_CPU: + printk(BIOS_ALERT, "Update not applicable to this CPU.\n"); + break; + case UCODE_INVALID_UPDATE_BLOCK: + printk(BIOS_ALERT, "Microcode block invalid." + "Update was not applied.\n"); + break; + default: + printk(BIOS_ALERT, "Unknown status. No update applied.\n"); + } +} + +unsigned int nano_update_ucode(void) +{ + size_t i; + unsigned int n_updates = 0; + const struct cbfs_file *cbfs_ucode; + u32 fms = cpuid_eax(0x1); + + cbfs_ucode = cbfs_find("cpu_microcode"); + /* Oops, did you forget to include the microcode ? */ + if(cbfs_ucode == NULL) { + printk(BIOS_ALERT, "WARNING: No microcode file found in CBFS. " + "Aborting microcode updates\n"); + return 0; + } + + /* Considering we are running with eXecute-In-Place (XIP), there's no + * need to worry that accessing data from ROM will slow us down. + * Microcode data should be aligned to a 4-byte boundary, but CBFS + * already does that for us (Do you, CBFS?) */ + const u32 *ucode_data = CBFS_SUBHEADER(cbfs_ucode); + const u32 ucode_len = ntohl(cbfs_ucode->len); + + /* We might do a lot of loops searching for the microcode updates, but + * keep in mind, nano_ucode_is_valid searches for the signature before + * doing anything else. */ + for( i = 0; i < (ucode_len >> 2); /* don't increment i here */ ) + { + ucode_update_status stat; + const nano_ucode_header * ucode = (void *)(&ucode_data[i]); + if(nano_ucode_is_valid(ucode) != NANO_UCODE_VALID) { + i++; + continue; + } + /* Since we have a valid microcode, there's no need to search + * in this region, so we restart our search at the end of this + * microcode */ + i += (ucode->total_size >> 2); + /* Is the microcode compatible with our CPU? */ + if(ucode->applicable_fms != fms) continue; + /* For our most curious users */ + nano_print_ucode_info(ucode); + /* The meat of the pie */ + stat = nano_apply_ucode(ucode); + /* The user might want to know how the update went */ + nano_print_ucode_status(stat); + if(stat == UCODE_UPDATE_SUCCESS) n_updates++; + } + + return n_updates; +} diff --git a/src/cpu/via/nano/update_ucode.h b/src/cpu/via/nano/update_ucode.h new file mode 100644 index 0000000..e014b1e --- /dev/null +++ b/src/cpu/via/nano/update_ucode.h @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ +#ifndef __UPDATE_UCODE_C +#define __UPDATE_UCODE_C + +#include <console/console.h> +#include <cpu/cpu.h> + +#define MSR_IA32_BIOS_UPDT_TRIG 0x00000079 +#define MSR_IA32_BIOS_SIGN_ID 0x0000008b +#define MSR_UCODE_UPDATE_STATUS 0x00001205 + +#define NANO_UCODE_SIGNATURE 0x53415252 +#define NANO_UCODE_HEADER_SIZE 0x30 + +/* We care what these values are exactly, so we define them to be sure */ +typedef enum ucode_update_status_enum { + UCODE_UPDATE_NOT_ATTEMPTED = 0x0, + UCODE_UPDATE_SUCCESS = 0x1, + UCODE_UPDATE_FAIL = 0x2, + UCODE_UPDATE_WRONG_CPU = 0x3, + UCODE_INVALID_UPDATE_BLOCK = 0x4, +} ucode_update_status; + + +typedef enum ucode_validity_enum { + NANO_UCODE_VALID = 0, /* We only care that valid == 0 */ + NANO_UCODE_SIGNATURE_ERROR, + NANO_UCODE_WRONG_SIZE, + NANO_UCODE_CHECKSUM_FAIL, +} ucode_validity; + +typedef struct nano_ucode_header_st { + u32 signature; /* NANO_UCODE_SIGNATURE */ + u32 update_revision; /* Revision of the update header */ + u16 year; /* Year of patch release */ + u8 day; /* Day of patch release */ + u8 month; /* Month of patch release */ + u32 applicable_fms; /* Fam/model/stepping to which ucode applies */ + u32 checksum; /* Two's complement checksum of ucode+header */ + u32 loader_revision; /* Revision of hardware ucode update loader*/ + u32 rfu_1; /* Reservod for future use */ + u32 payload_size; /* Size of the ucode payload only */ + u32 total_size; /* Size of the ucode, including header */ + char name[8]; /* ASCII string of ucode filename */ + u32 rfu_2; /* Reservod for future use */ + /* First double-word of the ucode payload + * Its address represents the beginning of the ucode update we need to + * send to the CPU */ + u32 ucode_start; + +}nano_ucode_header; + +unsigned int nano_update_ucode(void); + +#endif /* __UPDATE_UCODE_C */

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Patch set updated for coreboot: b521a4d VIA Nano: Add support for VIA Nano CPUs
by Alexandru Gagniuc 20 Jul '12

20 Jul '12

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1257 -gerrit commit b521a4dcbdf85b78e3301d2d8dfcdd1698730794 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Fri Jul 20 18:17:01 2012 -0500 VIA Nano: Add support for VIA Nano CPUs Add code to do the following for the VIA Nano CPUs - Update microcode - Set maximum frequency - Initialize power states - Set up cache Attempting to change the voltage or frequency of the CPU without applying the microcode update will hang the CPU, so we only do transitions if we can verify the microcode has been updated. The microcode is updated directly from CBFS. No microcode is included in ramstage. The microcode is not included in this commit. To get the microcode, run bios_extract on the manufacturer supplied BIOS, and look for the file marked "P6 Microcode". Include this file in CBFS. You can have the build system include this file automatically by selecting Expert Mode, then look under 'Chipset' -> 'Include CPU microcode in CBFS' -> Include external microcode file (check) 'Path and filename of CPU microcode' should contain the location of the microcode file previously extracted. Change-Id: I586aaca5715e047b42ef901d66772ace0e6b655e Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/cpu/via/Kconfig | 1 + src/cpu/via/Makefile.inc | 5 +- src/cpu/via/nano/Kconfig | 41 ++++++++ src/cpu/via/nano/Makefile.inc | 30 ++++++ src/cpu/via/nano/nano_init.c | 205 +++++++++++++++++++++++++++++++++++++++ src/cpu/via/nano/update_ucode.c | 151 ++++++++++++++++++++++++++++ src/cpu/via/nano/update_ucode.h | 72 ++++++++++++++ 7 files changed, 503 insertions(+), 2 deletions(-) diff --git a/src/cpu/via/Kconfig b/src/cpu/via/Kconfig index 570d408..5c38c91 100644 --- a/src/cpu/via/Kconfig +++ b/src/cpu/via/Kconfig @@ -1,2 +1,3 @@ source src/cpu/via/c3/Kconfig source src/cpu/via/c7/Kconfig +source src/cpu/via/nano/Kconfig diff --git a/src/cpu/via/Makefile.inc b/src/cpu/via/Makefile.inc index 2616111..bdfef0e 100644 --- a/src/cpu/via/Makefile.inc +++ b/src/cpu/via/Makefile.inc @@ -1,3 +1,4 @@ -subdirs-$(CONFIG_CPU_VIA_C7) += c7 -subdirs-$(CONFIG_CPU_VIA_C3) += c3 +subdirs-$(CONFIG_CPU_VIA_C7) += c7 +subdirs-$(CONFIG_CPU_VIA_C3) += c3 +subdirs-$(CONFIG_CPU_VIA_NANO) += nano diff --git a/src/cpu/via/nano/Kconfig b/src/cpu/via/nano/Kconfig new file mode 100644 index 0000000..ee7c3e0 --- /dev/null +++ b/src/cpu/via/nano/Kconfig @@ -0,0 +1,41 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see <http://www.gnu.org/licenses/>. +## + +config CPU_VIA_NANO + bool + +if CPU_VIA_NANO + +config CPU_SPECIFIC_OPTIONS + def_bool y + select UDELAY_TSC + select MMX + select SSE2 + select CACHE_AS_RAM + select CPU_MICROCODE_FROM_CBFS + +config DCACHE_RAM_BASE + hex + default 0xffef0000 + +config DCACHE_RAM_SIZE + hex + default 0x8000 + +endif # CPU_VIA_NAN diff --git a/src/cpu/via/nano/Makefile.inc b/src/cpu/via/nano/Makefile.inc new file mode 100644 index 0000000..b936444 --- /dev/null +++ b/src/cpu/via/nano/Makefile.inc @@ -0,0 +1,30 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see <http://www.gnu.org/licenses/>. +## + +subdirs-y += ../../x86/tsc +subdirs-y += ../../x86/mtrr +subdirs-y += ../../x86/lapic +subdirs-y += ../../x86/cache +subdirs-y += ../../x86/smm +subdirs-y += ../../intel/microcode + +driver-y += nano_init.c +ramstage-y += update_ucode.c + +cpu_incs += $(src)/cpu/via/car/cache_as_ram.inc diff --git a/src/cpu/via/nano/nano_init.c b/src/cpu/via/nano/nano_init.c new file mode 100644 index 0000000..80f8813 --- /dev/null +++ b/src/cpu/via/nano/nano_init.c @@ -0,0 +1,205 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include "update_ucode.h" +#include <console/console.h> +#include <device/device.h> +#include <cpu/cpu.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/lapic.h> +#include <cpu/x86/cache.h> +#include <delay.h> + +#define MODEL_NANO 0x2 +#define MODEL_NANO_3000_B0 0x8 +#define MODEL_NANO_3000_B2 0xa + +#define MSR_IA32_PERF_STATUS 0x00000198 +#define MSR_IA32_PERF_CTL 0x00000199 +#define MSR_IA32_MISC_ENABLE 0x000001a0 +#define NANO_MYSTERIOUS_MSR 0x120e + +static void nano_finish_fid_vid_transition(void) +{ + + msr_t msr; + /* Wait until the power transition ends */ + int cnt = 0; + do { + udelay(16); + msr = rdmsr(MSR_IA32_PERF_STATUS); + cnt++; + if (cnt > 128) { + printk(BIOS_WARNING, + "Error while updating multiplier and voltage\n"); + break; + } + } while (msr.lo & ((1 << 16) | (1 << 17))); + + /* Print the new FID and Voltage */ + u8 cur_vid = (msr.lo >> 0) & 0xff; + u8 cur_fid = (msr.lo >> 8) & 0xff; + printk(BIOS_INFO, "New CPU multiplier: %dx\n", cur_fid); + printk(BIOS_INFO, "New Voltage ID : %dx\n", cur_vid); +} + +static void nano_set_max_fid_vid(void) +{ + msr_t msr; + /* Get voltage and frequency info */ + msr = rdmsr(MSR_IA32_PERF_STATUS); + u8 min_fid = (msr.hi >> 24); + u8 max_fid = (msr.hi >> 8) & 0xff; + u8 min_vid = (msr.hi >> 16) & 0xff; + u8 max_vid = (msr.hi >> 0) & 0xff; + u8 cur_vid = (msr.lo >> 0) & 0xff; + u8 cur_fid = (msr.lo >> 8) & 0xff; + + printk(BIOS_INFO, "CPU multiplier: %dx (min %dx; max %dx)\n", + cur_fid, min_fid, max_fid); + printk(BIOS_INFO, "Voltage ID : %dx (min %dx; max %dx)\n", + cur_vid, min_vid, max_vid); + + if( (cur_fid != max_fid) || (cur_vid != max_vid) ) { + /* Set highest frequency and VID */ + msr.lo = msr.hi; + msr.hi = 0; + wrmsr(MSR_IA32_PERF_CTL, msr); + /* Wait for the transition to complete, otherwise, the CPU + * might reset itself repeatedly */ + nano_finish_fid_vid_transition(); + } + /* As a side note, if we didn't update the microcode by this point, the + * second PLL will not lock correctly. The clock will still be provided + * by the first PLL, and execution will continue normally, ___until___ + * the CPU switches PLL. Once that happens we will no longer have a + * working clock source, and the CPU will hang + * Moral of the story: update the microcode, or don't change FID + * This check is handled before calling nano_power() */ +} + +static void nano_power(void) +{ + msr_t msr; + /* Enable Powersaver */ + msr = rdmsr(MSR_IA32_MISC_ENABLE); + msr.lo |= (1 << 16); + wrmsr(MSR_IA32_MISC_ENABLE, msr); + + /* Enable 6 bit or 7-bit VRM support + * This MSR is not documented by VIA docs, other than setting these + * bits */ + msr = rdmsr(NANO_MYSTERIOUS_MSR); + msr.lo |= ( (1<<7) | (1<<4) ); + /* FIXME: Do we have a 6-bit or 7-bit VRM? + * set bit [5] for 7-bit, or don't set it for 6 bit VRM + * This will probably require a Kconfig option + * My board has a 7-bit VRM, so I can't test the 6-bit VRM stuff */ + msr.lo |= (1<<5); + wrmsr(NANO_MYSTERIOUS_MSR, msr); + + /* Set the maximum frequency and voltage */ + nano_set_max_fid_vid(); + + /* Enable TM3 */ + msr = rdmsr(MSR_IA32_MISC_ENABLE); + msr.lo |= ( (1<<3) | (1<<13) ); + wrmsr(MSR_IA32_MISC_ENABLE, msr); + + u8 stepping = ( cpuid_eax(0x1) ) &0xf; + if(stepping >= MODEL_NANO_3000_B0) { + /* Hello Nano 3000. The Terminator needs a CPU upgrade */ + /* Enable C1e, C2e, C3e, and C4e states */ + msr = rdmsr(MSR_IA32_MISC_ENABLE); + msr.lo |= ( (1<<25) | (1<<26) | (1<<31)); /* C1e, C2e, C3e */ + msr.hi |= (1<<0); /* C4e */ + wrmsr(MSR_IA32_MISC_ENABLE, msr); + } + + /* Lock on Powersaver */ + msr = rdmsr(MSR_IA32_MISC_ENABLE); + msr.lo |= (1<<20); + wrmsr(MSR_IA32_MISC_ENABLE, msr); +} + +static void nano_init(device_t dev) +{ + print_debug(" Nano POWER:\n"); + struct cpuinfo_x86 c; + + get_fms(&c, dev->device); + + /* We didn't test this on the Nano 1000/2000 series, so warn the user */ + if(c.x86_mask < MODEL_NANO_3000_B0) { + printk(BIOS_EMERG, "WARNING: This CPU has not been tested. " + "Please report any issues encountered. \n"); + } + switch (c.x86_mask) { + case MODEL_NANO: + printk(BIOS_INFO, "VIA Nano"); + break; + case MODEL_NANO_3000_B0: + printk(BIOS_INFO, "VIA Nano 3000 rev B0"); + break; + case MODEL_NANO_3000_B2: + printk(BIOS_INFO, "VIA Nano 3000 rev B2"); + break; + default: + printk(BIOS_EMERG, "Stepping not recognized: %x\n", c.x86_mask); + } + printk(BIOS_INFO, "\n"); + + /* We only read microcode from CBFS. If we don't have any microcode in + * CBFS, we'll just get back with 0 updates. User choice FTW. */ + unsigned int n_updates = nano_update_ucode(); + + if(n_updates != 0){ + nano_power(); + } else { + /* Changing the frequency or voltage without first updating the + * microcode will hang the CPU, so just don't do it */ + printk(BIOS_EMERG, "WARNING: CPU Microcode not updated.\n" + " Will not change frequency, as this may hang the CPU.\n"); + } + + /* Turn on cache */ + x86_enable_cache(); + /* Set up Memory Type Range Registers */ + x86_setup_mtrrs(); + x86_mtrr_check(); + /* Enable the local cpu apics */ + setup_lapic(); +} + +static struct device_operations cpu_dev_ops = { + .init = nano_init, +}; + +static struct cpu_device_id cpu_table[] = { + {X86_VENDOR_CENTAUR, 0x06f2}, // VIA NANO 1000/2000 Series + {X86_VENDOR_CENTAUR, 0x06f8}, // VIA NANO 3000 rev B0 + {X86_VENDOR_CENTAUR, 0x06fa}, // VIA NANO 3000 rev B2 + {0, 0}, +}; + +static const struct cpu_driver driver __cpu_driver = { + .ops = &cpu_dev_ops, + .id_table = cpu_table, +}; diff --git a/src/cpu/via/nano/update_ucode.c b/src/cpu/via/nano/update_ucode.c new file mode 100644 index 0000000..6a61338 --- /dev/null +++ b/src/cpu/via/nano/update_ucode.c @@ -0,0 +1,151 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include "update_ucode.h" +#include <cpu/x86/msr.h> +#include <console/console.h> +#include <stddef.h> +#include <cpu/cpu.h> +#include <arch/cpu.h> +#include <cbfs.h> + +static ucode_update_status nano_apply_ucode(const nano_ucode_header *ucode) +{ + printk(BIOS_SPEW, "Attempting to apply microcode update\n"); + + msr_t msr; + /* Address of ucode block goes in msr.lo for 32-bit mode + * Now remember, we need to pass the address of the actual microcode, + * not the header. The header is just there to help us. */ + msr.lo = (unsigned int)(&(ucode->ucode_start)); + msr.hi = 0; + wrmsr(MSR_IA32_BIOS_UPDT_TRIG, msr); + + /* Let's see if we updated succesfully */ + msr = rdmsr(MSR_UCODE_UPDATE_STATUS); + + return msr.lo & 0x07; +} + +static void nano_print_ucode_info(const nano_ucode_header *ucode) +{ + printk(BIOS_SPEW, "Microcode update information:\n"); + printk(BIOS_SPEW, "Name: %8s\n", ucode->name ); + printk(BIOS_SPEW, "Date: %u/%u/%u\n", ucode->month, + ucode->day, ucode->year ); +} + +static ucode_validity nano_ucode_is_valid(const nano_ucode_header *ucode) +{ + /* We must have a valid signature */ + if(ucode->signature != NANO_UCODE_SIGNATURE) + return NANO_UCODE_SIGNATURE_ERROR; + /* The size of the head must be exactly 12 double words */ + if( (ucode->total_size - ucode->payload_size) != NANO_UCODE_HEADER_SIZE) + return NANO_UCODE_WRONG_SIZE; + + /* How about a checksum ? Checksum must be 0 + * Two's complement done over the entire file, including the header */ + int i; + u32 check = 0; + u32 *raw = (void*) ucode; + for(i = 0 ; i < ((ucode->total_size) >> 2); i++) { + check += raw[i]; + } + if(check != 0) + return NANO_UCODE_CHECKSUM_FAIL; + /* Made it here huh? Then it looks valid to us. + * If there's anything else wrong, the CPU will reject the update */ + return NANO_UCODE_VALID; +} + +static void nano_print_ucode_status(ucode_update_status stat) +{ + switch(stat) + { + case UCODE_UPDATE_SUCCESS: + printk(BIOS_INFO, "Microcode update succesful.\n"); + break; + case UCODE_UPDATE_FAIL: + printk(BIOS_ALERT, "Microcode update failed, bad environment." + "Update was not applied.\n"); + break; + case UCODE_UPDATE_WRONG_CPU: + printk(BIOS_ALERT, "Update not applicable to this CPU.\n"); + break; + case UCODE_INVALID_UPDATE_BLOCK: + printk(BIOS_ALERT, "Microcode block invalid." + "Update was not applied.\n"); + break; + default: + printk(BIOS_ALERT, "Unknown status. No update applied.\n"); + } +} + +unsigned int nano_update_ucode(void) +{ + size_t i; + unsigned int n_updates = 0; + const struct cbfs_file *cbfs_ucode; + u32 fms = cpuid_eax(0x1); + + cbfs_ucode = cbfs_find("cpu_microcode"); + /* Oops, did you forget to include the microcode ? */ + if(cbfs_ucode == NULL) { + printk(BIOS_ALERT, "WARNING: No microcode file found in CBFS. " + "Aborting microcode updates\n"); + return 0; + } + + /* Considering we are running with eXecute-In-Place (XIP), there's no + * need to worry that accessing data from ROM will slow us down. + * Microcode data should be aligned to a 4-byte boundary, but CBFS + * already does that for us (Do you, CBFS?) */ + const u32 *ucode_data = CBFS_SUBHEADER(cbfs_ucode); + const u32 ucode_len = ntohl(cbfs_ucode->len); + + /* We might do a lot of loops searching for the microcode updates, but + * keep in mind, nano_ucode_is_valid searches for the signature before + * doing anything else. */ + for( i = 0; i < (ucode_len >> 2); /* don't increment i here */) + { + ucode_update_status stat; + const nano_ucode_header * ucode = (void *)(&ucode_data[i]); + if(nano_ucode_is_valid(ucode) != NANO_UCODE_VALID) { + i++; + continue; + } + /* Since we have a valid microcode, there's no need to search + * in this region, so we restart our search at the end of this + * microcode */ + i+= (ucode->total_size >> 2); + /* Is the microcode compatible with our CPU? */ + if(ucode->applicable_fms != fms) continue; + /* For our most curious users */ + nano_print_ucode_info(ucode); + /* The meat of the pie */ + stat = nano_apply_ucode(ucode); + /* The user might want to know how the update went */ + nano_print_ucode_status(stat); + if(stat == UCODE_UPDATE_SUCCESS) n_updates++; + } + + return n_updates; + +} diff --git a/src/cpu/via/nano/update_ucode.h b/src/cpu/via/nano/update_ucode.h new file mode 100644 index 0000000..05b6f1e --- /dev/null +++ b/src/cpu/via/nano/update_ucode.h @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ +#ifndef __UPDATE_UCODE_C +#define __UPDATE_UCODE_C + +#include <console/console.h> +#include <cpu/cpu.h> + +#define MSR_IA32_BIOS_UPDT_TRIG 0x00000079 +#define MSR_IA32_BIOS_SIGN_ID 0x0000008b +#define MSR_UCODE_UPDATE_STATUS 0x00001205 + +#define NANO_UCODE_SIGNATURE 0x53415252 +#define NANO_UCODE_HEADER_SIZE 0x30 + +/* We care what these values are exactly, so we define them to be sure */ +typedef enum ucode_update_status_enum { + UCODE_UPDATE_NOT_ATTEMPTED = 0x0, + UCODE_UPDATE_SUCCESS = 0x1, + UCODE_UPDATE_FAIL = 0x2, + UCODE_UPDATE_WRONG_CPU = 0x3, + UCODE_INVALID_UPDATE_BLOCK = 0x4, +} ucode_update_status; + + +typedef enum ucode_validity_enum { + NANO_UCODE_VALID = 0, /* We only care that valid == 0 */ + NANO_UCODE_SIGNATURE_ERROR, + NANO_UCODE_WRONG_SIZE, + NANO_UCODE_CHECKSUM_FAIL, +} ucode_validity; + +typedef struct nano_ucode_header_st { + u32 signature; /* NANO_UCODE_SIGNATURE */ + u32 update_revision; /* Revision of the update header */ + u16 year; /* Year of patch release */ + u8 day; /* Day of patch release */ + u8 month; /* Month of patch release */ + u32 applicable_fms; /* Fam/model/stepping to which ucode applies */ + u32 checksum; /* Two's complement checksum of ucode+header */ + u32 loader_revision; /* Revision of hardware ucode update loader*/ + u32 rfu_1; /* Reservod for future use */ + u32 payload_size; /* Size of the ucode payload only */ + u32 total_size; /* Size of the ucode, including header */ + char name[8]; /* ASCII string of ucode filename */ + u32 rfu_2; /* Reservod for future use */ + /* First double-word of the ucode payload + * Its address represents the beginning of the ucode update we need to + * send to the CPU */ + u32 ucode_start; + +}nano_ucode_header; + +unsigned int nano_update_ucode(void); + +#endif /* __UPDATE_UCODE_C */ \ No newline at end of file

1 0

Patch set updated for coreboot: f6d0693 VIA Nano: Add support for VIA Nano CPUs
by Alexandru Gagniuc 20 Jul '12

20 Jul '12

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1257 -gerrit commit f6d069350ae1dd7fd2ef94784b6466524f78746d Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Fri Jul 20 18:17:01 2012 -0500 VIA Nano: Add support for VIA Nano CPUs Add code to do the following for the VIA Nano CPUs - Update microcode - Set maximum frequency - Initialize power states - Set up cache Attempting to change the voltage or frequency of the CPU without applying the microcode update will hang the CPU, so we only do transitions if we can verify the microcode has been updated. The microcode is updated directly from CBFS. No microcode is included in ramstage. The microcode is not included in this commit. To get the microcode, run bios_extract on the manufacturer supplied BIOS, and look for the file marked "P6 Microcode". Include this file in CBFS. You can have the build system include this file automatically by selecting Expert Mode, then look under 'Chipset' -> 'Include CPU microcode in CBFS' -> Include external microcode file (check) 'Path and filename of CPU microcode' should contain the location of the microcode file previously extracted. Change-Id: I586aaca5715e047b42ef901d66772ace0e6b655e Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/cpu/via/Kconfig | 1 + src/cpu/via/Makefile.inc | 5 +- src/cpu/via/nano/Kconfig | 41 ++++++++ src/cpu/via/nano/Makefile.inc | 30 ++++++ src/cpu/via/nano/nano_init.c | 205 +++++++++++++++++++++++++++++++++++++++ src/cpu/via/nano/update_ucode.c | 151 ++++++++++++++++++++++++++++ src/cpu/via/nano/update_ucode.h | 72 ++++++++++++++ 7 files changed, 503 insertions(+), 2 deletions(-) diff --git a/src/cpu/via/Kconfig b/src/cpu/via/Kconfig index 570d408..5c38c91 100644 --- a/src/cpu/via/Kconfig +++ b/src/cpu/via/Kconfig @@ -1,2 +1,3 @@ source src/cpu/via/c3/Kconfig source src/cpu/via/c7/Kconfig +source src/cpu/via/nano/Kconfig diff --git a/src/cpu/via/Makefile.inc b/src/cpu/via/Makefile.inc index 2616111..bdfef0e 100644 --- a/src/cpu/via/Makefile.inc +++ b/src/cpu/via/Makefile.inc @@ -1,3 +1,4 @@ -subdirs-$(CONFIG_CPU_VIA_C7) += c7 -subdirs-$(CONFIG_CPU_VIA_C3) += c3 +subdirs-$(CONFIG_CPU_VIA_C7) += c7 +subdirs-$(CONFIG_CPU_VIA_C3) += c3 +subdirs-$(CONFIG_CPU_VIA_NANO) += nano diff --git a/src/cpu/via/nano/Kconfig b/src/cpu/via/nano/Kconfig new file mode 100644 index 0000000..75aa425 --- /dev/null +++ b/src/cpu/via/nano/Kconfig @@ -0,0 +1,41 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see <http://www.gnu.org/licenses/>. +## + +config CPU_VIA_NANO + bool + +if CPU_VIA_NANO + +config CPU_SPECIFIC_OPTIONS + def_bool y + select UDELAY_TSC + select MMX + select SSE2 + select CACHE_AS_RAM + select CPU_MICROCODE_FROM_CBFS + +config DCACHE_RAM_BASE + hex + default 0xffef0000 + +config DCACHE_RAM_SIZE + hex + default 0x8000 + +endif # CPU_VIA_C7 diff --git a/src/cpu/via/nano/Makefile.inc b/src/cpu/via/nano/Makefile.inc new file mode 100644 index 0000000..b936444 --- /dev/null +++ b/src/cpu/via/nano/Makefile.inc @@ -0,0 +1,30 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see <http://www.gnu.org/licenses/>. +## + +subdirs-y += ../../x86/tsc +subdirs-y += ../../x86/mtrr +subdirs-y += ../../x86/lapic +subdirs-y += ../../x86/cache +subdirs-y += ../../x86/smm +subdirs-y += ../../intel/microcode + +driver-y += nano_init.c +ramstage-y += update_ucode.c + +cpu_incs += $(src)/cpu/via/car/cache_as_ram.inc diff --git a/src/cpu/via/nano/nano_init.c b/src/cpu/via/nano/nano_init.c new file mode 100644 index 0000000..0496748 --- /dev/null +++ b/src/cpu/via/nano/nano_init.c @@ -0,0 +1,205 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include "update_ucode.h" +#include <console/console.h> +#include <device/device.h> +#include <cpu/cpu.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/lapic.h> +#include <cpu/x86/cache.h> +#include <delay.h> + +#define MODEL_NANO 0x3 +#define MODEL_NANO_3000_B0 0x8 +#define MODEL_NANO_3000_B2 0xa + +#define MSR_IA32_PERF_STATUS 0x00000198 +#define MSR_IA32_PERF_CTL 0x00000199 +#define MSR_IA32_MISC_ENABLE 0x000001a0 +#define NANO_MYSTERIOUS_MSR 0x120e + +static void nano_finish_fid_vid_transition(void) +{ + + msr_t msr; + /* Wait until the power transition ends */ + int cnt = 0; + do { + udelay(16); + msr = rdmsr(MSR_IA32_PERF_STATUS); + cnt++; + if (cnt > 128) { + printk(BIOS_WARNING, + "Error while updating multiplier and voltage\n"); + break; + } + } while (msr.lo & ((1 << 16) | (1 << 17))); + + /* Print the new FID and Voltage */ + u8 cur_vid = (msr.lo >> 0) & 0xff; + u8 cur_fid = (msr.lo >> 8) & 0xff; + printk(BIOS_INFO, "New CPU multiplier: %dx\n", cur_fid); + printk(BIOS_INFO, "New Voltage ID : %dx\n", cur_vid); +} + +static void nano_set_max_fid_vid(void) +{ + msr_t msr; + /* Get voltage and frequency info */ + msr = rdmsr(MSR_IA32_PERF_STATUS); + u8 min_fid = (msr.hi >> 24); + u8 max_fid = (msr.hi >> 8) & 0xff; + u8 min_vid = (msr.hi >> 16) & 0xff; + u8 max_vid = (msr.hi >> 0) & 0xff; + u8 cur_vid = (msr.lo >> 0) & 0xff; + u8 cur_fid = (msr.lo >> 8) & 0xff; + + printk(BIOS_INFO, "CPU multiplier: %dx (min %dx; max %dx)\n", + cur_fid, min_fid, max_fid); + printk(BIOS_INFO, "Voltage ID : %dx (min %dx; max %dx)\n", + cur_vid, min_vid, max_vid); + + if( (cur_fid != max_fid) || (cur_vid != max_vid) ) { + /* Set highest frequency and VID */ + msr.lo = msr.hi; + msr.hi = 0; + wrmsr(MSR_IA32_PERF_CTL, msr); + /* Wait for the transition to complete, otherwise, the CPU + * might reset itself repeatedly */ + nano_finish_fid_vid_transition(); + } + /* As a side note, if we didn't update the microcode by this point, the + * second PLL will not lock correctly. The clock will still be provided + * by the first PLL, and execution will continue normally, ___until___ + * the CPU switches PLL. Once that happens we will no longer have a + * working clock source, and the CPU will hang + * Moral of the story: update the microcode, or don't change FID + * This check is handled before calling nano_power() */ +} + +static void nano_power(void) +{ + msr_t msr; + /* Enable Powersaver */ + msr = rdmsr(MSR_IA32_MISC_ENABLE); + msr.lo |= (1 << 16); + wrmsr(MSR_IA32_MISC_ENABLE, msr); + + /* Enable 6 bit or 7-bit VRM support + * This MSR is not documented by VIA docs, other than setting these + * bits */ + msr = rdmsr(NANO_MYSTERIOUS_MSR); + msr.lo |= ( (1<<7) | (1<<4) ); + /* FIXME: Do we have a 6-bit or 7-bit VRM? + * set bit [5] for 7-bit, or don't set it for 6 bit VRM + * This will probably require a Kconfig option + * My board has a 7-bit VRM, so I can't test the 6-bit VRM stuff */ + msr.lo |= (1<<5); + wrmsr(NANO_MYSTERIOUS_MSR, msr); + + /* Set the maximum frequency and voltage */ + nano_set_max_fid_vid(); + + /* Enable TM3 */ + msr = rdmsr(MSR_IA32_MISC_ENABLE); + msr.lo |= ( (1<<3) | (1<<13) ); + wrmsr(MSR_IA32_MISC_ENABLE, msr); + + u8 stepping = ( cpuid_eax(0x1) ) &0xf; + if(stepping >= MODEL_NANO_3000_B0) { + /* Hello Nano 3000. The Terminator needs a CPU upgrade */ + /* Enable C1e, C2e, C3e, and C4e states */ + msr = rdmsr(MSR_IA32_MISC_ENABLE); + msr.lo |= ( (1<<25) | (1<<26) | (1<<31)); /* C1e, C2e, C3e */ + msr.hi |= (1<<0); /* C4e */ + wrmsr(MSR_IA32_MISC_ENABLE, msr); + } + + /* Lock on Powersaver */ + msr = rdmsr(MSR_IA32_MISC_ENABLE); + msr.lo |= (1<<20); + wrmsr(MSR_IA32_MISC_ENABLE, msr); +} + +static void nano_init(device_t dev) +{ + print_debug(" Nano POWER:\n"); + struct cpuinfo_x86 c; + + get_fms(&c, dev->device); + + /* We didn't test this on the Nano 1000/2000 series, so warn the user */ + if(c.x86_mask < MODEL_NANO_3000_B0) { + printk(BIOS_EMERG, "WARNING: This CPU has not been tested. " + "Please report any issues encountered. \n"); + } + switch (c.x86_mask) { + case MODEL_NANO: + printk(BIOS_INFO, "VIA Nano"); + break; + case MODEL_NANO_3000_B0: + printk(BIOS_INFO, "VIA Nano 3000 rev B0"); + break; + case MODEL_NANO_3000_B2: + printk(BIOS_INFO, "VIA Nano 3000 rev B2"); + break; + default: + printk(BIOS_EMERG, "Stepping not recognized: %x\n", c.x86_mask); + } + printk(BIOS_INFO, "\n"); + + /* We only read microcode from CBFS. If we don't have any microcode in + * CBFS, we'll just get back with 0 updates. User choice FTW. */ + unsigned int n_updates = nano_update_ucode(); + + if(n_updates != 0){ + nano_power(); + } else { + /* Changing the frequency or voltage without first updating the + * microcode will hang the CPU, so just don't do it */ + printk(BIOS_EMERG, "WARNING: CPU Microcode not updated.\n" + " Will not change frequency, as this may hang the CPU.\n"); + } + + /* Turn on cache */ + x86_enable_cache(); + /* Set up Memory Type Range Registers */ + x86_setup_mtrrs(); + x86_mtrr_check(); + /* Enable the local cpu apics */ + setup_lapic(); +} + +static struct device_operations cpu_dev_ops = { + .init = nano_init, +}; + +static struct cpu_device_id cpu_table[] = { + {X86_VENDOR_CENTAUR, 0x06f2}, // VIA NANO 1000/2000 Series + {X86_VENDOR_CENTAUR, 0x06f8}, // VIA NANO 3000 rev B0 + {X86_VENDOR_CENTAUR, 0x06fa}, // VIA NANO 3000 rev B2 + {0, 0}, +}; + +static const struct cpu_driver driver __cpu_driver = { + .ops = &cpu_dev_ops, + .id_table = cpu_table, +}; diff --git a/src/cpu/via/nano/update_ucode.c b/src/cpu/via/nano/update_ucode.c new file mode 100644 index 0000000..6a61338 --- /dev/null +++ b/src/cpu/via/nano/update_ucode.c @@ -0,0 +1,151 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include "update_ucode.h" +#include <cpu/x86/msr.h> +#include <console/console.h> +#include <stddef.h> +#include <cpu/cpu.h> +#include <arch/cpu.h> +#include <cbfs.h> + +static ucode_update_status nano_apply_ucode(const nano_ucode_header *ucode) +{ + printk(BIOS_SPEW, "Attempting to apply microcode update\n"); + + msr_t msr; + /* Address of ucode block goes in msr.lo for 32-bit mode + * Now remember, we need to pass the address of the actual microcode, + * not the header. The header is just there to help us. */ + msr.lo = (unsigned int)(&(ucode->ucode_start)); + msr.hi = 0; + wrmsr(MSR_IA32_BIOS_UPDT_TRIG, msr); + + /* Let's see if we updated succesfully */ + msr = rdmsr(MSR_UCODE_UPDATE_STATUS); + + return msr.lo & 0x07; +} + +static void nano_print_ucode_info(const nano_ucode_header *ucode) +{ + printk(BIOS_SPEW, "Microcode update information:\n"); + printk(BIOS_SPEW, "Name: %8s\n", ucode->name ); + printk(BIOS_SPEW, "Date: %u/%u/%u\n", ucode->month, + ucode->day, ucode->year ); +} + +static ucode_validity nano_ucode_is_valid(const nano_ucode_header *ucode) +{ + /* We must have a valid signature */ + if(ucode->signature != NANO_UCODE_SIGNATURE) + return NANO_UCODE_SIGNATURE_ERROR; + /* The size of the head must be exactly 12 double words */ + if( (ucode->total_size - ucode->payload_size) != NANO_UCODE_HEADER_SIZE) + return NANO_UCODE_WRONG_SIZE; + + /* How about a checksum ? Checksum must be 0 + * Two's complement done over the entire file, including the header */ + int i; + u32 check = 0; + u32 *raw = (void*) ucode; + for(i = 0 ; i < ((ucode->total_size) >> 2); i++) { + check += raw[i]; + } + if(check != 0) + return NANO_UCODE_CHECKSUM_FAIL; + /* Made it here huh? Then it looks valid to us. + * If there's anything else wrong, the CPU will reject the update */ + return NANO_UCODE_VALID; +} + +static void nano_print_ucode_status(ucode_update_status stat) +{ + switch(stat) + { + case UCODE_UPDATE_SUCCESS: + printk(BIOS_INFO, "Microcode update succesful.\n"); + break; + case UCODE_UPDATE_FAIL: + printk(BIOS_ALERT, "Microcode update failed, bad environment." + "Update was not applied.\n"); + break; + case UCODE_UPDATE_WRONG_CPU: + printk(BIOS_ALERT, "Update not applicable to this CPU.\n"); + break; + case UCODE_INVALID_UPDATE_BLOCK: + printk(BIOS_ALERT, "Microcode block invalid." + "Update was not applied.\n"); + break; + default: + printk(BIOS_ALERT, "Unknown status. No update applied.\n"); + } +} + +unsigned int nano_update_ucode(void) +{ + size_t i; + unsigned int n_updates = 0; + const struct cbfs_file *cbfs_ucode; + u32 fms = cpuid_eax(0x1); + + cbfs_ucode = cbfs_find("cpu_microcode"); + /* Oops, did you forget to include the microcode ? */ + if(cbfs_ucode == NULL) { + printk(BIOS_ALERT, "WARNING: No microcode file found in CBFS. " + "Aborting microcode updates\n"); + return 0; + } + + /* Considering we are running with eXecute-In-Place (XIP), there's no + * need to worry that accessing data from ROM will slow us down. + * Microcode data should be aligned to a 4-byte boundary, but CBFS + * already does that for us (Do you, CBFS?) */ + const u32 *ucode_data = CBFS_SUBHEADER(cbfs_ucode); + const u32 ucode_len = ntohl(cbfs_ucode->len); + + /* We might do a lot of loops searching for the microcode updates, but + * keep in mind, nano_ucode_is_valid searches for the signature before + * doing anything else. */ + for( i = 0; i < (ucode_len >> 2); /* don't increment i here */) + { + ucode_update_status stat; + const nano_ucode_header * ucode = (void *)(&ucode_data[i]); + if(nano_ucode_is_valid(ucode) != NANO_UCODE_VALID) { + i++; + continue; + } + /* Since we have a valid microcode, there's no need to search + * in this region, so we restart our search at the end of this + * microcode */ + i+= (ucode->total_size >> 2); + /* Is the microcode compatible with our CPU? */ + if(ucode->applicable_fms != fms) continue; + /* For our most curious users */ + nano_print_ucode_info(ucode); + /* The meat of the pie */ + stat = nano_apply_ucode(ucode); + /* The user might want to know how the update went */ + nano_print_ucode_status(stat); + if(stat == UCODE_UPDATE_SUCCESS) n_updates++; + } + + return n_updates; + +} diff --git a/src/cpu/via/nano/update_ucode.h b/src/cpu/via/nano/update_ucode.h new file mode 100644 index 0000000..05b6f1e --- /dev/null +++ b/src/cpu/via/nano/update_ucode.h @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ +#ifndef __UPDATE_UCODE_C +#define __UPDATE_UCODE_C + +#include <console/console.h> +#include <cpu/cpu.h> + +#define MSR_IA32_BIOS_UPDT_TRIG 0x00000079 +#define MSR_IA32_BIOS_SIGN_ID 0x0000008b +#define MSR_UCODE_UPDATE_STATUS 0x00001205 + +#define NANO_UCODE_SIGNATURE 0x53415252 +#define NANO_UCODE_HEADER_SIZE 0x30 + +/* We care what these values are exactly, so we define them to be sure */ +typedef enum ucode_update_status_enum { + UCODE_UPDATE_NOT_ATTEMPTED = 0x0, + UCODE_UPDATE_SUCCESS = 0x1, + UCODE_UPDATE_FAIL = 0x2, + UCODE_UPDATE_WRONG_CPU = 0x3, + UCODE_INVALID_UPDATE_BLOCK = 0x4, +} ucode_update_status; + + +typedef enum ucode_validity_enum { + NANO_UCODE_VALID = 0, /* We only care that valid == 0 */ + NANO_UCODE_SIGNATURE_ERROR, + NANO_UCODE_WRONG_SIZE, + NANO_UCODE_CHECKSUM_FAIL, +} ucode_validity; + +typedef struct nano_ucode_header_st { + u32 signature; /* NANO_UCODE_SIGNATURE */ + u32 update_revision; /* Revision of the update header */ + u16 year; /* Year of patch release */ + u8 day; /* Day of patch release */ + u8 month; /* Month of patch release */ + u32 applicable_fms; /* Fam/model/stepping to which ucode applies */ + u32 checksum; /* Two's complement checksum of ucode+header */ + u32 loader_revision; /* Revision of hardware ucode update loader*/ + u32 rfu_1; /* Reservod for future use */ + u32 payload_size; /* Size of the ucode payload only */ + u32 total_size; /* Size of the ucode, including header */ + char name[8]; /* ASCII string of ucode filename */ + u32 rfu_2; /* Reservod for future use */ + /* First double-word of the ucode payload + * Its address represents the beginning of the ucode update we need to + * send to the CPU */ + u32 ucode_start; + +}nano_ucode_header; + +unsigned int nano_update_ucode(void); + +#endif /* __UPDATE_UCODE_C */ \ No newline at end of file

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New patch to review for coreboot: b775d07 VIA Nano: Add support for VIA Nano CPUs
by Alexandru Gagniuc 20 Jul '12

20 Jul '12

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1257 -gerrit commit b775d07b8a75dd5d6a992c649617466b35cd3a98 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Fri Jul 20 18:17:01 2012 -0500 VIA Nano: Add support for VIA Nano CPUs Add code to do the following for the VIA Nano CPUs - Update microcode - Set maximum frequency - Initialize power states - Set up cache Attempting to change the voltage or frequency of the CPU without applying the microcode update will hang the CPU, so we only do transitions if we can verify the microcode has been updated. The microcode is updated directly from CBFS. No microcode is included in ramstage. The microcode is not included in this commit. To get the microcode, run bios_extract on the manufacturer supplied BIOS, and look for the file marked "P6 Microcode". Include this file in CBFS. You can have the build system include this file automatically by selecting Expert Mode, then look under 'Chipset' -> 'Include CPU microcode in CBFS' -> Include external microcode file (check) 'Path and filename of CPU microcode' should contain the location of the microcode file previously extracted. Change-Id: I586aaca5715e047b42ef901d66772ace0e6b655e Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/cpu/via/Kconfig | 1 + src/cpu/via/Makefile.inc | 5 +- src/cpu/via/nano/Kconfig | 41 ++++++++ src/cpu/via/nano/Makefile.inc | 32 ++++++ src/cpu/via/nano/nano_init.c | 205 +++++++++++++++++++++++++++++++++++++++ src/cpu/via/nano/update_ucode.c | 151 ++++++++++++++++++++++++++++ src/cpu/via/nano/update_ucode.h | 72 ++++++++++++++ 7 files changed, 505 insertions(+), 2 deletions(-) diff --git a/src/cpu/via/Kconfig b/src/cpu/via/Kconfig index 570d408..5c38c91 100644 --- a/src/cpu/via/Kconfig +++ b/src/cpu/via/Kconfig @@ -1,2 +1,3 @@ source src/cpu/via/c3/Kconfig source src/cpu/via/c7/Kconfig +source src/cpu/via/nano/Kconfig diff --git a/src/cpu/via/Makefile.inc b/src/cpu/via/Makefile.inc index 2616111..bdfef0e 100644 --- a/src/cpu/via/Makefile.inc +++ b/src/cpu/via/Makefile.inc @@ -1,3 +1,4 @@ -subdirs-$(CONFIG_CPU_VIA_C7) += c7 -subdirs-$(CONFIG_CPU_VIA_C3) += c3 +subdirs-$(CONFIG_CPU_VIA_C7) += c7 +subdirs-$(CONFIG_CPU_VIA_C3) += c3 +subdirs-$(CONFIG_CPU_VIA_NANO) += nano diff --git a/src/cpu/via/nano/Kconfig b/src/cpu/via/nano/Kconfig new file mode 100644 index 0000000..75aa425 --- /dev/null +++ b/src/cpu/via/nano/Kconfig @@ -0,0 +1,41 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see <http://www.gnu.org/licenses/>. +## + +config CPU_VIA_NANO + bool + +if CPU_VIA_NANO + +config CPU_SPECIFIC_OPTIONS + def_bool y + select UDELAY_TSC + select MMX + select SSE2 + select CACHE_AS_RAM + select CPU_MICROCODE_FROM_CBFS + +config DCACHE_RAM_BASE + hex + default 0xffef0000 + +config DCACHE_RAM_SIZE + hex + default 0x8000 + +endif # CPU_VIA_C7 diff --git a/src/cpu/via/nano/Makefile.inc b/src/cpu/via/nano/Makefile.inc new file mode 100644 index 0000000..e3d85e6 --- /dev/null +++ b/src/cpu/via/nano/Makefile.inc @@ -0,0 +1,32 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program. If not, see <http://www.gnu.org/licenses/>. +## + +subdirs-y += ../../x86/tsc +subdirs-y += ../../x86/mtrr +subdirs-y += ../../x86/lapic +subdirs-y += ../../x86/cache +subdirs-y += ../../x86/smm +subdirs-y += ../../intel/microcode + +driver-y += nano_init.c +ramstage-y += update_ucode.c + +cpu_microcode-y += nano_ucode_pula.h + +cpu_incs += $(src)/cpu/via/car/cache_as_ram.inc diff --git a/src/cpu/via/nano/nano_init.c b/src/cpu/via/nano/nano_init.c new file mode 100644 index 0000000..0496748 --- /dev/null +++ b/src/cpu/via/nano/nano_init.c @@ -0,0 +1,205 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include "update_ucode.h" +#include <console/console.h> +#include <device/device.h> +#include <cpu/cpu.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/lapic.h> +#include <cpu/x86/cache.h> +#include <delay.h> + +#define MODEL_NANO 0x3 +#define MODEL_NANO_3000_B0 0x8 +#define MODEL_NANO_3000_B2 0xa + +#define MSR_IA32_PERF_STATUS 0x00000198 +#define MSR_IA32_PERF_CTL 0x00000199 +#define MSR_IA32_MISC_ENABLE 0x000001a0 +#define NANO_MYSTERIOUS_MSR 0x120e + +static void nano_finish_fid_vid_transition(void) +{ + + msr_t msr; + /* Wait until the power transition ends */ + int cnt = 0; + do { + udelay(16); + msr = rdmsr(MSR_IA32_PERF_STATUS); + cnt++; + if (cnt > 128) { + printk(BIOS_WARNING, + "Error while updating multiplier and voltage\n"); + break; + } + } while (msr.lo & ((1 << 16) | (1 << 17))); + + /* Print the new FID and Voltage */ + u8 cur_vid = (msr.lo >> 0) & 0xff; + u8 cur_fid = (msr.lo >> 8) & 0xff; + printk(BIOS_INFO, "New CPU multiplier: %dx\n", cur_fid); + printk(BIOS_INFO, "New Voltage ID : %dx\n", cur_vid); +} + +static void nano_set_max_fid_vid(void) +{ + msr_t msr; + /* Get voltage and frequency info */ + msr = rdmsr(MSR_IA32_PERF_STATUS); + u8 min_fid = (msr.hi >> 24); + u8 max_fid = (msr.hi >> 8) & 0xff; + u8 min_vid = (msr.hi >> 16) & 0xff; + u8 max_vid = (msr.hi >> 0) & 0xff; + u8 cur_vid = (msr.lo >> 0) & 0xff; + u8 cur_fid = (msr.lo >> 8) & 0xff; + + printk(BIOS_INFO, "CPU multiplier: %dx (min %dx; max %dx)\n", + cur_fid, min_fid, max_fid); + printk(BIOS_INFO, "Voltage ID : %dx (min %dx; max %dx)\n", + cur_vid, min_vid, max_vid); + + if( (cur_fid != max_fid) || (cur_vid != max_vid) ) { + /* Set highest frequency and VID */ + msr.lo = msr.hi; + msr.hi = 0; + wrmsr(MSR_IA32_PERF_CTL, msr); + /* Wait for the transition to complete, otherwise, the CPU + * might reset itself repeatedly */ + nano_finish_fid_vid_transition(); + } + /* As a side note, if we didn't update the microcode by this point, the + * second PLL will not lock correctly. The clock will still be provided + * by the first PLL, and execution will continue normally, ___until___ + * the CPU switches PLL. Once that happens we will no longer have a + * working clock source, and the CPU will hang + * Moral of the story: update the microcode, or don't change FID + * This check is handled before calling nano_power() */ +} + +static void nano_power(void) +{ + msr_t msr; + /* Enable Powersaver */ + msr = rdmsr(MSR_IA32_MISC_ENABLE); + msr.lo |= (1 << 16); + wrmsr(MSR_IA32_MISC_ENABLE, msr); + + /* Enable 6 bit or 7-bit VRM support + * This MSR is not documented by VIA docs, other than setting these + * bits */ + msr = rdmsr(NANO_MYSTERIOUS_MSR); + msr.lo |= ( (1<<7) | (1<<4) ); + /* FIXME: Do we have a 6-bit or 7-bit VRM? + * set bit [5] for 7-bit, or don't set it for 6 bit VRM + * This will probably require a Kconfig option + * My board has a 7-bit VRM, so I can't test the 6-bit VRM stuff */ + msr.lo |= (1<<5); + wrmsr(NANO_MYSTERIOUS_MSR, msr); + + /* Set the maximum frequency and voltage */ + nano_set_max_fid_vid(); + + /* Enable TM3 */ + msr = rdmsr(MSR_IA32_MISC_ENABLE); + msr.lo |= ( (1<<3) | (1<<13) ); + wrmsr(MSR_IA32_MISC_ENABLE, msr); + + u8 stepping = ( cpuid_eax(0x1) ) &0xf; + if(stepping >= MODEL_NANO_3000_B0) { + /* Hello Nano 3000. The Terminator needs a CPU upgrade */ + /* Enable C1e, C2e, C3e, and C4e states */ + msr = rdmsr(MSR_IA32_MISC_ENABLE); + msr.lo |= ( (1<<25) | (1<<26) | (1<<31)); /* C1e, C2e, C3e */ + msr.hi |= (1<<0); /* C4e */ + wrmsr(MSR_IA32_MISC_ENABLE, msr); + } + + /* Lock on Powersaver */ + msr = rdmsr(MSR_IA32_MISC_ENABLE); + msr.lo |= (1<<20); + wrmsr(MSR_IA32_MISC_ENABLE, msr); +} + +static void nano_init(device_t dev) +{ + print_debug(" Nano POWER:\n"); + struct cpuinfo_x86 c; + + get_fms(&c, dev->device); + + /* We didn't test this on the Nano 1000/2000 series, so warn the user */ + if(c.x86_mask < MODEL_NANO_3000_B0) { + printk(BIOS_EMERG, "WARNING: This CPU has not been tested. " + "Please report any issues encountered. \n"); + } + switch (c.x86_mask) { + case MODEL_NANO: + printk(BIOS_INFO, "VIA Nano"); + break; + case MODEL_NANO_3000_B0: + printk(BIOS_INFO, "VIA Nano 3000 rev B0"); + break; + case MODEL_NANO_3000_B2: + printk(BIOS_INFO, "VIA Nano 3000 rev B2"); + break; + default: + printk(BIOS_EMERG, "Stepping not recognized: %x\n", c.x86_mask); + } + printk(BIOS_INFO, "\n"); + + /* We only read microcode from CBFS. If we don't have any microcode in + * CBFS, we'll just get back with 0 updates. User choice FTW. */ + unsigned int n_updates = nano_update_ucode(); + + if(n_updates != 0){ + nano_power(); + } else { + /* Changing the frequency or voltage without first updating the + * microcode will hang the CPU, so just don't do it */ + printk(BIOS_EMERG, "WARNING: CPU Microcode not updated.\n" + " Will not change frequency, as this may hang the CPU.\n"); + } + + /* Turn on cache */ + x86_enable_cache(); + /* Set up Memory Type Range Registers */ + x86_setup_mtrrs(); + x86_mtrr_check(); + /* Enable the local cpu apics */ + setup_lapic(); +} + +static struct device_operations cpu_dev_ops = { + .init = nano_init, +}; + +static struct cpu_device_id cpu_table[] = { + {X86_VENDOR_CENTAUR, 0x06f2}, // VIA NANO 1000/2000 Series + {X86_VENDOR_CENTAUR, 0x06f8}, // VIA NANO 3000 rev B0 + {X86_VENDOR_CENTAUR, 0x06fa}, // VIA NANO 3000 rev B2 + {0, 0}, +}; + +static const struct cpu_driver driver __cpu_driver = { + .ops = &cpu_dev_ops, + .id_table = cpu_table, +}; diff --git a/src/cpu/via/nano/update_ucode.c b/src/cpu/via/nano/update_ucode.c new file mode 100644 index 0000000..6a61338 --- /dev/null +++ b/src/cpu/via/nano/update_ucode.c @@ -0,0 +1,151 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include "update_ucode.h" +#include <cpu/x86/msr.h> +#include <console/console.h> +#include <stddef.h> +#include <cpu/cpu.h> +#include <arch/cpu.h> +#include <cbfs.h> + +static ucode_update_status nano_apply_ucode(const nano_ucode_header *ucode) +{ + printk(BIOS_SPEW, "Attempting to apply microcode update\n"); + + msr_t msr; + /* Address of ucode block goes in msr.lo for 32-bit mode + * Now remember, we need to pass the address of the actual microcode, + * not the header. The header is just there to help us. */ + msr.lo = (unsigned int)(&(ucode->ucode_start)); + msr.hi = 0; + wrmsr(MSR_IA32_BIOS_UPDT_TRIG, msr); + + /* Let's see if we updated succesfully */ + msr = rdmsr(MSR_UCODE_UPDATE_STATUS); + + return msr.lo & 0x07; +} + +static void nano_print_ucode_info(const nano_ucode_header *ucode) +{ + printk(BIOS_SPEW, "Microcode update information:\n"); + printk(BIOS_SPEW, "Name: %8s\n", ucode->name ); + printk(BIOS_SPEW, "Date: %u/%u/%u\n", ucode->month, + ucode->day, ucode->year ); +} + +static ucode_validity nano_ucode_is_valid(const nano_ucode_header *ucode) +{ + /* We must have a valid signature */ + if(ucode->signature != NANO_UCODE_SIGNATURE) + return NANO_UCODE_SIGNATURE_ERROR; + /* The size of the head must be exactly 12 double words */ + if( (ucode->total_size - ucode->payload_size) != NANO_UCODE_HEADER_SIZE) + return NANO_UCODE_WRONG_SIZE; + + /* How about a checksum ? Checksum must be 0 + * Two's complement done over the entire file, including the header */ + int i; + u32 check = 0; + u32 *raw = (void*) ucode; + for(i = 0 ; i < ((ucode->total_size) >> 2); i++) { + check += raw[i]; + } + if(check != 0) + return NANO_UCODE_CHECKSUM_FAIL; + /* Made it here huh? Then it looks valid to us. + * If there's anything else wrong, the CPU will reject the update */ + return NANO_UCODE_VALID; +} + +static void nano_print_ucode_status(ucode_update_status stat) +{ + switch(stat) + { + case UCODE_UPDATE_SUCCESS: + printk(BIOS_INFO, "Microcode update succesful.\n"); + break; + case UCODE_UPDATE_FAIL: + printk(BIOS_ALERT, "Microcode update failed, bad environment." + "Update was not applied.\n"); + break; + case UCODE_UPDATE_WRONG_CPU: + printk(BIOS_ALERT, "Update not applicable to this CPU.\n"); + break; + case UCODE_INVALID_UPDATE_BLOCK: + printk(BIOS_ALERT, "Microcode block invalid." + "Update was not applied.\n"); + break; + default: + printk(BIOS_ALERT, "Unknown status. No update applied.\n"); + } +} + +unsigned int nano_update_ucode(void) +{ + size_t i; + unsigned int n_updates = 0; + const struct cbfs_file *cbfs_ucode; + u32 fms = cpuid_eax(0x1); + + cbfs_ucode = cbfs_find("cpu_microcode"); + /* Oops, did you forget to include the microcode ? */ + if(cbfs_ucode == NULL) { + printk(BIOS_ALERT, "WARNING: No microcode file found in CBFS. " + "Aborting microcode updates\n"); + return 0; + } + + /* Considering we are running with eXecute-In-Place (XIP), there's no + * need to worry that accessing data from ROM will slow us down. + * Microcode data should be aligned to a 4-byte boundary, but CBFS + * already does that for us (Do you, CBFS?) */ + const u32 *ucode_data = CBFS_SUBHEADER(cbfs_ucode); + const u32 ucode_len = ntohl(cbfs_ucode->len); + + /* We might do a lot of loops searching for the microcode updates, but + * keep in mind, nano_ucode_is_valid searches for the signature before + * doing anything else. */ + for( i = 0; i < (ucode_len >> 2); /* don't increment i here */) + { + ucode_update_status stat; + const nano_ucode_header * ucode = (void *)(&ucode_data[i]); + if(nano_ucode_is_valid(ucode) != NANO_UCODE_VALID) { + i++; + continue; + } + /* Since we have a valid microcode, there's no need to search + * in this region, so we restart our search at the end of this + * microcode */ + i+= (ucode->total_size >> 2); + /* Is the microcode compatible with our CPU? */ + if(ucode->applicable_fms != fms) continue; + /* For our most curious users */ + nano_print_ucode_info(ucode); + /* The meat of the pie */ + stat = nano_apply_ucode(ucode); + /* The user might want to know how the update went */ + nano_print_ucode_status(stat); + if(stat == UCODE_UPDATE_SUCCESS) n_updates++; + } + + return n_updates; + +} diff --git a/src/cpu/via/nano/update_ucode.h b/src/cpu/via/nano/update_ucode.h new file mode 100644 index 0000000..05b6f1e --- /dev/null +++ b/src/cpu/via/nano/update_ucode.h @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ +#ifndef __UPDATE_UCODE_C +#define __UPDATE_UCODE_C + +#include <console/console.h> +#include <cpu/cpu.h> + +#define MSR_IA32_BIOS_UPDT_TRIG 0x00000079 +#define MSR_IA32_BIOS_SIGN_ID 0x0000008b +#define MSR_UCODE_UPDATE_STATUS 0x00001205 + +#define NANO_UCODE_SIGNATURE 0x53415252 +#define NANO_UCODE_HEADER_SIZE 0x30 + +/* We care what these values are exactly, so we define them to be sure */ +typedef enum ucode_update_status_enum { + UCODE_UPDATE_NOT_ATTEMPTED = 0x0, + UCODE_UPDATE_SUCCESS = 0x1, + UCODE_UPDATE_FAIL = 0x2, + UCODE_UPDATE_WRONG_CPU = 0x3, + UCODE_INVALID_UPDATE_BLOCK = 0x4, +} ucode_update_status; + + +typedef enum ucode_validity_enum { + NANO_UCODE_VALID = 0, /* We only care that valid == 0 */ + NANO_UCODE_SIGNATURE_ERROR, + NANO_UCODE_WRONG_SIZE, + NANO_UCODE_CHECKSUM_FAIL, +} ucode_validity; + +typedef struct nano_ucode_header_st { + u32 signature; /* NANO_UCODE_SIGNATURE */ + u32 update_revision; /* Revision of the update header */ + u16 year; /* Year of patch release */ + u8 day; /* Day of patch release */ + u8 month; /* Month of patch release */ + u32 applicable_fms; /* Fam/model/stepping to which ucode applies */ + u32 checksum; /* Two's complement checksum of ucode+header */ + u32 loader_revision; /* Revision of hardware ucode update loader*/ + u32 rfu_1; /* Reservod for future use */ + u32 payload_size; /* Size of the ucode payload only */ + u32 total_size; /* Size of the ucode, including header */ + char name[8]; /* ASCII string of ucode filename */ + u32 rfu_2; /* Reservod for future use */ + /* First double-word of the ucode payload + * Its address represents the beginning of the ucode update we need to + * send to the CPU */ + u32 ucode_start; + +}nano_ucode_header; + +unsigned int nano_update_ucode(void); + +#endif /* __UPDATE_UCODE_C */ \ No newline at end of file

1 0

Patch set updated for coreboot: 35c23b5 Make broadcast SIPI optional.
by Ronald G. Minnich 20 Jul '12

20 Jul '12

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1256 -gerrit commit 35c23b5727d17cb4e56a51c1d0dfbef203cfc018 Author: Ronald G. Minnich <rminnich(a)google.com> Date: Fri Jul 20 11:13:51 2012 -0700 Make broadcast SIPI optional. Broadcast SIPI breaks some platforms. This change introduces a new configuration variable, BROADCAST_SIPI, that controls how SIPI is managed. The default is off, since we know that works. You can turn it on but be aware that even if your platform boots it may get very odd crashes. We need to finish up the broadcast SIPI code and that will take some work. Change-Id: Icf0bd0357353ab7ac4b217939152aa67e8255fa2 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/arch/x86/Kconfig | 18 ++- src/arch/x86/include/arch/cpu.h | 27 +++ src/arch/x86/lib/cpu.c | 40 ++++- src/cpu/intel/hyperthreading/intel_sibling.c | 46 ++++- src/cpu/intel/model_1067x/model_1067x_init.c | 10 + src/cpu/intel/model_106cx/Kconfig | 1 - src/cpu/intel/model_106cx/model_106cx_init.c | 9 + src/cpu/intel/model_206ax/acpi.c | 16 ++ src/cpu/intel/model_206ax/model_206ax_init.c | 64 ++++++ src/cpu/intel/model_6ex/model_6ex_init.c | 5 + src/cpu/intel/model_6fx/model_6fx_init.c | 6 + src/cpu/intel/model_f2x/model_f2x_init.c | 6 + src/cpu/intel/model_f3x/model_f3x_init.c | 7 + src/cpu/intel/model_f4x/model_f4x_init.c | 7 + src/cpu/x86/lapic/lapic_cpu_init.c | 286 ++++++++++++++++++++++++-- src/cpu/x86/lapic/secondary.S | 29 ++- src/cpu/x86/pae/pgtbl.c | 11 + src/drivers/i2c/w83795/w83795.c | 9 +- src/include/cpu/cpu.h | 12 +- 19 files changed, 574 insertions(+), 35 deletions(-) diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 4dfbe70..f679fa0 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -2,7 +2,23 @@ menu "Architecture (x86)" # This is an SMP option. It relates to starting up APs. # It is usually set in mainboard/*/Kconfig. -# TODO: Improve description. +# If set, startup uses a BROADCAST to start all cores at once +# It is wrong for some HT cores, e.g. those in chromebooks. +# Because it is breaks some platforms, and the old code works on +# all platforms, we leave it off. +config BROADCAST_SIPI + bool + default n + depends on ARCH_X86 + +# This is another SMP option. On some HT platforms the AP +# must not try to halt, but rather must wait in the +# secondary start code for another SIPI so it can stop +# correctly. +config AP_IN_SIPI_WAIT + bool + default n + depends on ARCH_X86 && ! BROADCAST_SIPI # Aligns 16bit entry code in bootblock so that hyper-threading CPUs # can boot AP CPUs to enable their shared caches. diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 0fe5ea5..29215fd 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -158,6 +158,33 @@ struct cpu_driver { struct device; struct cpu_driver *find_cpu_driver(struct device *cpu); +#if CONFIG_BROADCAST_SIPI == 0 +struct cpu_info { + device_t cpu; + unsigned int index; +}; + +static inline struct cpu_info *cpu_info(void) +{ + struct cpu_info *ci; + __asm__("andl %%esp,%0; " + "orl %2, %0 " + :"=r" (ci) + : "0" (~(CONFIG_STACK_SIZE - 1)), + "r" (CONFIG_STACK_SIZE - sizeof(struct cpu_info)) + ); + return ci; +} + +static inline unsigned long cpu_index(void) +{ + struct cpu_info *ci; + ci = cpu_info(); + return ci->index; +} + +#endif /* ! CONFIG_BROADCAST_SIPI */ + struct cpuinfo_x86 { uint8_t x86; /* CPU family */ uint8_t x86_vendor; /* CPU vendor */ diff --git a/src/arch/x86/lib/cpu.c b/src/arch/x86/lib/cpu.c index 7cd955e..65f8a22 100644 --- a/src/arch/x86/lib/cpu.c +++ b/src/arch/x86/lib/cpu.c @@ -9,7 +9,9 @@ #include <device/path.h> #include <device/device.h> #include <smp/spinlock.h> +#if CONFIG_BROADCAST_SIPI == 1 #include <cpu/x86/lapic.h> +#endif /* CONFIG_BROADCAST_SIPI */ /* Standard macro to see if a specific flag is changeable */ static inline int flag_is_changeable_p(uint32_t flag) @@ -235,7 +237,15 @@ static void set_cpu_ops(struct device *cpu) cpu->ops = driver ? driver->ops : NULL; } +#if CONFIG_BROADCAST_SIPI == 0 +void cpu_initialize(unsigned int index) +#else /* CONFIG_BROADCAST_SIPI */ +#if CONFIG_SMP +static spinlock_t start_cpu_lock = SPIN_LOCK_UNLOCKED; +#endif + void cpu_initialize(struct bus *cpu_bus, int index) +#endif /* CONFIG_BROADCAST_SIPI */ { /* Because we busy wait at the printk spinlock. * It is important to keep the number of printed messages @@ -244,16 +254,41 @@ void cpu_initialize(struct bus *cpu_bus, int index) */ struct device *cpu; struct cpuinfo_x86 c; - struct device_path cpu_path; unsigned char id = lapicid(); +#if CONFIG_BROADCAST_SIPI == 1 + struct device_path cpu_path; cpu_path.type = DEVICE_PATH_APIC; cpu_path.apic.apic_id = id; + cpu_path.type = DEVICE_PATH_APIC; + cpu_path.apic.apic_id = id; + cpu_path.apic.index = index; +#if CONFIG_SMP + spin_lock(&start_cpu_lock); +#endif cpu = alloc_find_dev(cpu_bus, &cpu_path); +#if CONFIG_SMP + spin_unlock(&start_cpu_lock); +#endif + printk(BIOS_DEBUG, "Initializing CPU #%d\n", id); +#else /* ! CONFIG_BROADCAST_SIPI */ + struct cpu_info *info; + info = cpu_info(); + + cpu = info->cpu; + if (!cpu) { + die("CPU: missing cpu device structure"); + } + cpu->path.apic.index = index; printk(BIOS_DEBUG, "Initializing CPU #%d\n", id); + cpu = info->cpu; + if (!cpu) { + die("CPU: missing cpu device structure"); + } +#endif /* CONFIG_BROADCAST_SIPI */ /* Find what type of cpu we are dealing with */ identify_cpu(cpu); @@ -284,8 +319,7 @@ void cpu_initialize(struct bus *cpu_bus, int index) cpu->ops->init(cpu); } - printk(BIOS_INFO, "CPU #%d initialized\n", id); + printk(BIOS_INFO, "CPU #%d ,lapic id %d, initialized\n", index, id); - return; } diff --git a/src/cpu/intel/hyperthreading/intel_sibling.c b/src/cpu/intel/hyperthreading/intel_sibling.c index 8377cd0..cabd3cc 100644 --- a/src/cpu/intel/hyperthreading/intel_sibling.c +++ b/src/cpu/intel/hyperthreading/intel_sibling.c @@ -7,13 +7,55 @@ #include <smp/spinlock.h> #include <assert.h> +#if CONFIG_BROADCAST_SIPI == 0 +#if !CONFIG_SERIAL_CPU_INIT +#error Intel hyper-threading requires serialized cpu init +#endif + +static int first_time = 1; +static int disable_siblings = !CONFIG_LOGICAL_CPUS; + +void intel_sibling_init(device_t cpu) +{ + unsigned int core_ids, apic_ids, threads; + + /* See if I am a sibling cpu */ + if (cpu->path.apic.apic_id & (siblings -1)) { + if (disable_siblings) { + cpu->enabled = 0; + } + return; + } + /* I am the primary cpu start up my siblings */ + for(i = 1; i < siblings; i++) { + struct device_path cpu_path; + device_t new; + /* Build the cpu device path */ + cpu_path.type = DEVICE_PATH_APIC; + cpu_path.apic.apic_id = cpu->path.apic.apic_id + i; + + /* Allocate new cpu device structure iff sibling CPU + * was not in static device tree. + */ + new = alloc_find_dev(cpu->bus, &cpu_path); + + if (!new) { + continue; + } + + printk(BIOS_DEBUG, "CPU: %u has sibling %u\n", + cpu->path.apic.apic_id, + new->path.apic.apic_id); + } +} + +#else /* CONFIG_BROADCAST_SIPI */ /* Return true if running thread does not have the smallest lapic ID * within a CPU core. */ int intel_ht_sibling(void) { unsigned int core_ids, apic_ids, threads; - apic_ids = 1; if (cpuid_eax(0) >= 1) apic_ids = (cpuid_ebx(1) >> 16) & 0xff; @@ -27,3 +69,5 @@ int intel_ht_sibling(void) threads = (apic_ids / core_ids); return !!(lapicid() & (threads-1)); } +#endif /* CONFIG_BROADCAST_SIPI */ + diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c index ddd1381..4a91b04 100644 --- a/src/cpu/intel/model_1067x/model_1067x_init.c +++ b/src/cpu/intel/model_1067x/model_1067x_init.c @@ -29,6 +29,10 @@ #include <cpu/x86/lapic.h> #include <cpu/intel/microcode.h> #include <cpu/intel/speedstep.h> + +#if CONFIG_BROADCAST_SIPI == 0 +#include <cpu/intel/hyperthreading.h> +#endif /* ! CONFIG_BROADCAST_SIPI */ #include <cpu/x86/cache.h> #include <cpu/x86/name.h> @@ -220,6 +224,12 @@ static void model_1067x_init(device_t cpu) /* PIC thermal sensor control */ configure_pic_thermal_sensors(); +#if CONFIG_BROADCAST_SIPI == 0 + + /* Start up my cpu siblings */ + intel_sibling_init(cpu); +#endif /* ! CONFIG_BROADCAST_SIPI */ + } static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_106cx/Kconfig b/src/cpu/intel/model_106cx/Kconfig index 2ef7392..00abf6b 100644 --- a/src/cpu/intel/model_106cx/Kconfig +++ b/src/cpu/intel/model_106cx/Kconfig @@ -11,4 +11,3 @@ config CPU_ADDR_BITS default 32 endif - diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c index 8d2ef3d..16660ac 100644 --- a/src/cpu/intel/model_106cx/model_106cx_init.c +++ b/src/cpu/intel/model_106cx/model_106cx_init.c @@ -27,6 +27,10 @@ #include <cpu/x86/lapic.h> #include <cpu/intel/microcode.h> #include <cpu/intel/speedstep.h> + +#if CONFIG_BROADCAST_SIPI == 0 +#include <cpu/intel/hyperthreading.h> +#endif /* ! CONFIG_BROADCAST_SIPI */ #include <cpu/x86/cache.h> #include <cpu/x86/name.h> #include <usbdebug.h> @@ -177,6 +181,11 @@ static void model_106cx_init(device_t cpu) configure_misc(); /* TODO: PIC thermal sensor control */ +#if CONFIG_BROADCAST_SIPI == 0 + + /* Start up my cpu siblings */ + intel_sibling_init(cpu); +#endif /* ! CONFIG_BROADCAST_SIPI */ } static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_206ax/acpi.c b/src/cpu/intel/model_206ax/acpi.c index dea23e7..1b5fa0a 100644 --- a/src/cpu/intel/model_206ax/acpi.c +++ b/src/cpu/intel/model_206ax/acpi.c @@ -26,7 +26,9 @@ #include <arch/acpigen.h> #include <arch/cpu.h> #include <cpu/x86/msr.h> +#if CONFIG_BROADCAST_SIPI == 1 #include <cpu/x86/lapic.h> +#endif /* CONFIG_BROADCAST_SIPI */ #include <cpu/intel/acpi.h> #include <cpu/intel/speedstep.h> #include <cpu/intel/turbo.h> @@ -89,8 +91,14 @@ static int generate_cstate_entries(acpi_cstate_t *cstates, static int generate_C_state_entries(void) { +#if CONFIG_BROADCAST_SIPI == 0 + struct cpu_info *info; +#endif /* ! CONFIG_BROADCAST_SIPI */ + struct cpu_driver *cpu; +#if CONFIG_BROADCAST_SIPI == 1 struct cpu_driver *cpu; struct device *cpu_dev; +#endif /* CONFIG_BROADCAST_SIPI */ int len, lenif; device_t lapic; struct cpu_intel_model_206ax_config *conf = NULL; @@ -104,10 +112,18 @@ static int generate_C_state_entries(void) return 0; /* Find CPU map of supported C-states */ +#if CONFIG_BROADCAST_SIPI == 0 + info = cpu_info(); + if (!info) + return 0; + cpu = find_cpu_driver(info->cpu); +#else /* CONFIG_BROADCAST_SIPI */ cpu_dev = dev_find_lapic(lapicid()); if (!cpu_dev) return 0; cpu = find_cpu_driver(cpu_dev); +#endif /* CONFIG_BROADCAST_SIPI */ + if (!cpu || !cpu->cstates) return 0; diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index d60c237..6e76d7f 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -414,6 +414,63 @@ static void configure_mca(void) static unsigned ehci_debug_addr; #endif +#if CONFIG_BROADCAST_SIPI == 0 +/* + * Initialize any extra cores/threads in this package. + */ +static void intel_cores_init(device_t cpu) +{ + struct cpuid_result result; + unsigned cores, threads, i; + + result = cpuid_ext(0xb, 0); /* Threads per core */ + threads = result.ebx & 0xff; + + result = cpuid_ext(0xb, 1); /* Cores per package */ + cores = result.ebx & 0xff; + + /* Only initialize extra cores from BSP */ + if (cpu->path.apic.apic_id) + return; + + printk(BIOS_DEBUG, "CPU: %u has %u cores %u threads\n", + cpu->path.apic.apic_id, cores, threads); + + for (i = 1; i < cores; ++i) { + struct device_path cpu_path; + device_t new; + + /* Build the cpu device path */ + cpu_path.type = DEVICE_PATH_APIC; + cpu_path.apic.apic_id = + cpu->path.apic.apic_id + i; + + /* Update APIC ID if no hyperthreading */ + if (threads == 1) + cpu_path.apic.apic_id <<= 1; + + /* Allocate the new cpu device structure */ + new = alloc_dev(cpu->bus, &cpu_path); + if (!new) + continue; + + printk(BIOS_DEBUG, "CPU: %u has core %u\n", + cpu->path.apic.apic_id, + new->path.apic.apic_id); + +#if CONFIG_SMP && CONFIG_MAX_CPUS > 1 + /* Start the new cpu */ + if (!start_cpu(new)) { + /* Record the error in cpu? */ + printk(BIOS_ERR, "CPU %u would not start!\n", + new->path.apic.apic_id); + } +#endif + } +} + +#endif /* ! CONFIG_BROADCAST_SIPI */ + static void model_206ax_init(device_t cpu) { char processor_name[49]; @@ -476,6 +533,13 @@ static void model_206ax_init(device_t cpu) /* Enable Turbo */ enable_turbo(); + +#if CONFIG_BROADCAST_SIPI == 0 + + /* Start up extra cores */ + intel_cores_init(cpu); +#endif /* ! CONFIG_BROADCAST_SIPI */ + } static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c index a0afd2e..989ca27 100644 --- a/src/cpu/intel/model_6ex/model_6ex_init.c +++ b/src/cpu/intel/model_6ex/model_6ex_init.c @@ -205,6 +205,11 @@ static void model_6ex_init(device_t cpu) /* PIC thermal sensor control */ configure_pic_thermal_sensors(); +#if CONFIG_BROADCAST_SIPI == 0 + + /* Start up my cpu siblings */ + intel_sibling_init(cpu); +#endif /* ! CONFIG_BROADCAST_SIPI */ } static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c index c5d7a6b..171059a 100644 --- a/src/cpu/intel/model_6fx/model_6fx_init.c +++ b/src/cpu/intel/model_6fx/model_6fx_init.c @@ -243,6 +243,12 @@ static void model_6fx_init(device_t cpu) /* PIC thermal sensor control */ configure_pic_thermal_sensors(); + +#if CONFIG_BROADCAST_SIPI == 0 + + /* Start up my cpu siblings */ + intel_sibling_init(cpu); +#endif /* ! CONFIG_BROADCAST_SIPI */ } static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_f2x/model_f2x_init.c b/src/cpu/intel/model_f2x/model_f2x_init.c index fa9e05f..87c3157 100644 --- a/src/cpu/intel/model_f2x/model_f2x_init.c +++ b/src/cpu/intel/model_f2x/model_f2x_init.c @@ -60,6 +60,12 @@ static void model_f2x_init(device_t cpu) /* Enable the local cpu apics */ setup_lapic(); + +#if CONFIG_BROADCAST_SIPI == 0 + + /* Start up my cpu siblings */ + intel_sibling_init(cpu); +#endif /* ! CONFIG_BROADCAST_SIPI */ }; static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_f3x/model_f3x_init.c b/src/cpu/intel/model_f3x/model_f3x_init.c index dd2a45f..96c38cd 100644 --- a/src/cpu/intel/model_f3x/model_f3x_init.c +++ b/src/cpu/intel/model_f3x/model_f3x_init.c @@ -43,6 +43,13 @@ static void model_f3x_init(device_t cpu) /* Enable the local cpu apics */ setup_lapic(); + +#if CONFIG_BROADCAST_SIPI == 0 + + /* Start up my cpu siblings */ + intel_sibling_init(cpu); +#endif /* ! CONFIG_BROADCAST_SIPI */ + }; static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_f4x/model_f4x_init.c b/src/cpu/intel/model_f4x/model_f4x_init.c index af7d9d2..cade95f 100644 --- a/src/cpu/intel/model_f4x/model_f4x_init.c +++ b/src/cpu/intel/model_f4x/model_f4x_init.c @@ -51,6 +51,13 @@ static void model_f4x_init(device_t cpu) /* Enable the local cpu apics */ setup_lapic(); + +#if CONFIG_BROADCAST_SIPI == 0 + + /* Start up my cpu siblings */ + intel_sibling_init(cpu); +#endif /* ! CONFIG_BROADCAST_SIPI */ + }; static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index b6dc560..b29340d 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -60,9 +60,27 @@ static void copy_secondary_start_to_1m_below(void) printk(BIOS_DEBUG, "start_eip=0x%08lx, code_size=0x%08lx\n", (long unsigned int)AP_SIPI_VECTOR, code_size); } -static struct bus *current_cpu_bus; +#ifdef __SSE3__ +static __inline__ __attribute__((always_inline)) unsigned long readcr4(void) +{ + unsigned long value; + __asm__ __volatile__ ( + "mov %%cr4, %[value]" + : [value] "=a" (value)); + return value; +} -static int lapic_start_cpus(struct bus *cpu_bus) +static __inline__ __attribute__((always_inline)) void + writecr4(unsigned long Data) +{ + __asm__ __volatile__ ( + "mov %%eax, %%cr4" + : + : "a" (Data) + ); +} +#if CONFIG_BROADCAST_SIPI == 0 +static int lapic_start_cpu(unsigned long apicid) { int timeout; unsigned long send_status, accept_status; @@ -187,26 +205,239 @@ static void stop_all_ap_cpus(void) mdelay(10); } -#ifdef __SSE3__ -static __inline__ __attribute__((always_inline)) unsigned long readcr4(void) + +/* C entry point of secondary cpus */ +void secondary_cpu_init(int index) { - unsigned long value; - __asm__ __volatile__ ( - "mov %%cr4, %[value]" - : [value] "=a" (value)); - return value; +#ifdef __SSE3__ + /* + * Seems that CR4 was cleared when AP start via lapic_start_cpu() + * Turn on CR4.OSFXSR and CR4.OSXMMEXCPT when SSE options enabled + */ + u32 cr4_val; + cr4_val = readcr4(); + cr4_val |= (1 << 9 | 1 << 10); + writecr4(cr4_val); +#endif + atomic_inc(&active_cpus); + cpu_initialize(current_cpu_bus, index); + atomic_dec(&active_cpus); } -static __inline__ __attribute__((always_inline)) void writecr4(unsigned long Data) +static void wait_other_cpus_stop(struct bus *cpu_bus) { - __asm__ __volatile__ ( - "mov %%eax, %%cr4" - : - : "a" (Data) - ); + device_t cpu; + int old_active_count, active_count; + long loopcount = 0; + + /* Now loop until the other cpus have finished initializing */ + old_active_count = 1; + active_count = atomic_read(&active_cpus); + while(active_count > 1) { + if (active_count != old_active_count) { + printk(BIOS_INFO, "Waiting for %d CPUS to stop\n", active_count - 1); + old_active_count = active_count; + } + udelay(10); + active_count = atomic_read(&active_cpus); + loopcount++; + } + for(cpu = cpu_bus->children; cpu; cpu = cpu->sibling) { + if (cpu->path.type != DEVICE_PATH_APIC) { + continue; + } + if (cpu->path.apic.apic_id == SPEEDSTEP_APIC_MAGIC) { + continue; + } + if (!cpu->initialized) { + printk(BIOS_ERR, "CPU 0x%02x did not initialize!\n", + cpu->path.apic.apic_id); + } + } + stop_all_ap_cpus(); + printk(BIOS_DEBUG, "All AP CPUs stopped (%ld loops)\n", loopcount); } + +#endif /* CONFIG_SMP */ + +void initialize_cpus(struct bus *cpu_bus) +{ + struct device_path cpu_path; + +#if NEED_LAPIC == 1 + /* Ensure the local apic is enabled */ + enable_lapic(); + + /* Get the device path of the boot cpu */ + cpu_path.type = DEVICE_PATH_APIC; + cpu_path.apic.apic_id = lapicid(); +#else + /* Get the device path of the boot cpu */ + cpu_path.type = DEVICE_PATH_CPU; + cpu_path.cpu.id = 0; +#endif + +#if CONFIG_SMP + copy_secondary_start_to_1m_below(); // why here? In case some day we can start core1 in amd_sibling_init +#endif + +#if CONFIG_HAVE_SMI_HANDLER + smm_init(); #endif + cpus_ready_for_init(); + + /* Initialize the bootstrap processor */ + cpu_initialize(cpu_bus, 0); + +#if CONFIG_SMP + lapic_start_cpus(cpu_bus); + /* Now wait the rest of the cpus stop*/ + wait_other_cpus_stop(cpu_bus); +#endif +} + +#else + +static struct bus *current_cpu_bus; + +static int lapic_start_cpus(struct bus *cpu_bus) +#if CONFIG_SMP && CONFIG_MAX_CPUS > 1 + +static struct bus *current_cpu_bus; + +static int lapic_start_cpus(struct bus *cpu_bus) +{ + int timeout; + unsigned long send_status, accept_status, start_eip; + int maxlvt; + + /* + * Starting actual IPI sequence... + */ + + current_cpu_bus = cpu_bus; + + printk(BIOS_SPEW, "Asserting INIT.\n"); + + /* Send INIT SIPI to target chip */ + lapic_write_around(LAPIC_ICR2, 0); + lapic_write_around(LAPIC_ICR, LAPIC_INT_ASSERT + | LAPIC_DM_INIT | LAPIC_DEST_ALLBUT); + + printk(BIOS_DEBUG, "Waiting for send to finish...\n"); + timeout = 0; + do { + printk(BIOS_SPEW, "+"); + udelay(100); + send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY; + } while (send_status && (timeout++ < 1000)); + if (timeout >= 1000) { + printk(BIOS_DEBUG, "First apic write timed out. Disabling\n"); + // too bad. + printk(BIOS_DEBUG, "ESR is 0x%lx\n", lapic_read(LAPIC_ESR)); + if (lapic_read(LAPIC_ESR)) { + printk(BIOS_DEBUG, "Try to reset ESR\n"); + lapic_write_around(LAPIC_ESR, 0); + printk(BIOS_DEBUG, "ESR is 0x%lx\n", lapic_read(LAPIC_ESR)); + } + return 0; + } + start_eip = get_valid_start_eip((unsigned long)_secondary_start); + + maxlvt = 4; + + printk(BIOS_SPEW, "Sending STARTUP.\n"); + lapic_read_around(LAPIC_SPIV); + lapic_write(LAPIC_ESR, 0); + lapic_read(LAPIC_ESR); + printk(BIOS_SPEW, "After apic_write.\n"); + + /* + * STARTUP IPI + */ + + /* Target chip */ + lapic_write_around(LAPIC_ICR2, 0); + printk(BIOS_SPEW, "After apic_write_around(LAPIC_ICR2, 0);\n"); + + /* Boot on the stack */ + /* Kick the second */ + lapic_write_around(LAPIC_ICR, + LAPIC_INT_ASSERT | LAPIC_DM_STARTUP | LAPIC_DEST_ALLBUT + | (start_eip >> 12)); + printk(BIOS_SPEW, "After apic_write_around allbut starteip %p.\n", + (void *)start_eip); + + /* + * Give the other CPU some time to accept the IPI. + */ + udelay(300); + + printk(BIOS_DEBUG, "Startup point 1.\n"); + + printk(BIOS_DEBUG, "Waiting for send to finish...\n"); + timeout = 0; + do { + printk(BIOS_DEBUG, "+"); + udelay(100); + send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY; + } while (send_status && (timeout++ < 1000)); + + /* + * Give the other CPU some time to accept the IPI. + */ + udelay(200); + /* + * Due to the Pentium erratum 3AP. + */ + if (maxlvt > 3) { + lapic_read_around(LAPIC_SPIV); + lapic_write(LAPIC_ESR, 0); + } + accept_status = (lapic_read(LAPIC_ESR) & 0xEF); + + printk(BIOS_DEBUG, "After Startup.\n"); + if (send_status) + printk(BIOS_WARNING, "APIC never delivered???\n"); + if (accept_status) + printk(BIOS_WARNING, "APIC delivery error (%lx).\n", + accept_status); + if (send_status || accept_status) + return 0; + return 1; +} + + +/* Number of cpus that are currently running in coreboot */ +static atomic_t active_cpus = ATOMIC_INIT(1); + +volatile unsigned long secondary_stack; +extern unsigned char _estack[]; + +static void stop_all_ap_cpus(void) +{ + unsigned long send_status; + int timeout; + /* send an LAPIC INIT to all but myself */ + lapic_write_around(LAPIC_ICR2, 0); + lapic_write_around(LAPIC_ICR, + LAPIC_INT_ASSERT | LAPIC_DM_INIT | LAPIC_DEST_ALLBUT); + + /* wait for the ipi send to finish */ + printk(BIOS_SPEW, "Waiting for send to finish...\n"); + timeout = 0; + do { + printk(BIOS_SPEW, "+"); + udelay(100); + send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY; + } while (send_status && (timeout++ < 1000)); + if (timeout >= 1000) { + printk(BIOS_ERR, "timed out\n"); + } + mdelay(10); +} + /* C entry point of secondary cpus */ void secondary_cpu_init(int index) { @@ -236,7 +467,8 @@ static void wait_other_cpus_stop(struct bus *cpu_bus) active_count = atomic_read(&active_cpus); while(active_count > 1) { if (active_count != old_active_count) { - printk(BIOS_INFO, "Waiting for %d CPUS to stop\n", active_count - 1); + printk(BIOS_INFO, "Waiting for %d CPUS to stop\n", + active_count - 1); old_active_count = active_count; } udelay(10); @@ -257,6 +489,23 @@ static void wait_other_cpus_stop(struct bus *cpu_bus) } stop_all_ap_cpus(); printk(BIOS_DEBUG, "All AP CPUs stopped (%ld loops)\n", loopcount); +#if 0 + for(i = 1; i <= last_cpu_index; i++){ + unsigned long *stack = stacks[i]; + int lowest; + int maxstack = (CONFIG_STACK_SIZE - sizeof(struct cpu_info)) + /sizeof(*stack) - 1; + if (stack[0] != 0xDEADBEEF) + printk(BIOS_ERR, "CPU%d overran its stack\n", i); + for(lowest = 0; lowest < maxstack; lowest++) + if (stack[lowest] != 0xDEADBEEF) + break; + printk(BIOS_SPEW, "CPU%d: stack allocated from %p to %p:", i, + stack, &stack[maxstack]); + printk(BIOS_SPEW, "lowest stack address was %p\n", + &stack[lowest]); + } +#endif } #endif /* CONFIG_SMP */ @@ -279,7 +528,8 @@ void initialize_cpus(struct bus *cpu_bus) #endif #if CONFIG_SMP - copy_secondary_start_to_1m_below(); // why here? In case some day we can start core1 in amd_sibling_init + // why here? In case some day we can start core1 in amd_sibling_init + copy_secondary_start_to_lowest_1M(); #endif #if CONFIG_HAVE_SMI_HANDLER @@ -297,4 +547,4 @@ void initialize_cpus(struct bus *cpu_bus) wait_other_cpus_stop(cpu_bus); #endif } - +#endif \ No newline at end of file diff --git a/src/cpu/x86/lapic/secondary.S b/src/cpu/x86/lapic/secondary.S index e6650ec..a6d5ea3 100644 --- a/src/cpu/x86/lapic/secondary.S +++ b/src/cpu/x86/lapic/secondary.S @@ -2,7 +2,11 @@ #include <cpu/x86/lapic_def.h> .text - .globl _secondary_start, _secondary_start_end, cpucount, ap_protected_start + .globl _secondary_start, _secondary_start_end, ap_protected_start +#if CONFIG_BROADCAST_SIPI == 1 + .globl cpucount +#endif + .balign 4096 _secondary_start: .code16 cli @@ -26,12 +30,6 @@ _secondary_start: ljmpl $0x10, $__ap_protected_start -gdtaddr: - .word gdt_limit /* the table limit */ - .long gdt /* we know the offset */ - -_secondary_start_end: - ap_protected_start: .code32 lgdt gdtaddr @@ -49,6 +47,14 @@ __ap_protected_start: /* Load the Interrupt descriptor table */ lidt idtarg +#if CONFIG_BROADCAST_SIPI == 0 + /* Set the stack pointer, and flag that we are done */ + xorl %eax, %eax + movl secondary_stack, %esp + movl secondary_cpu_index, %edi + pushl %edi + movl %eax, secondary_stack +#else /* CONFIG_BROADCAST_SIPI */ /* increment our cpu index */ movl $1, %eax lock xadd %eax, cpucount @@ -61,10 +67,19 @@ __ap_protected_start: add %eax, %esp pushl %ecx +#endif /* CONFIG_BROADCAST_SIPI */ + call secondary_cpu_init 1: hlt jmp 1b +#if CONFIG_BROADCAST_SIPI == 1 cpucount: .long 1 +#endif /* CONFIG_BROADCAST_SIPI */ +gdtaddr: + .word gdt_limit /* the table limit */ + .long gdt /* we know the offset */ + +_secondary_start_end: .code32 diff --git a/src/cpu/x86/pae/pgtbl.c b/src/cpu/x86/pae/pgtbl.c index 7aa17c2..f84ec6e 100644 --- a/src/cpu/x86/pae/pgtbl.c +++ b/src/cpu/x86/pae/pgtbl.c @@ -7,6 +7,15 @@ #include <cpu/cpu.h> #include <cpu/x86/pae.h> #include <cpu/x86/lapic.h> + +#if CONFIG_BROADCAST_SIPI == 1 +#include <device/device.h> +#endif /* CONFIG_BROADCAST_SIPI */ +#include <cpu/cpu.h> +#include <cpu/x86/pae.h> +#if CONFIG_BROADCAST_SIPI == 1 +#include <cpu/x86/lapic.h> +#endif /* CONFIG_BROADCAST_SIPI */ #include <string.h> static void paging_off(void) @@ -45,6 +54,7 @@ static void paging_on(void *pdp) ); } +#if CONFIG_BROADCAST_SIPI == 1 static int cpu_index(void) { device_t dev = dev_find_lapic(lapicid()); @@ -53,6 +63,7 @@ static int cpu_index(void) return dev->path.apic.index; } +#endif /* CONFIG_BROADCAST_SIPI */ void *map_2M_page(unsigned long page) { struct pde { diff --git a/src/drivers/i2c/w83795/w83795.c b/src/drivers/i2c/w83795/w83795.c index 12be4da..14b12b3 100644 --- a/src/drivers/i2c/w83795/w83795.c +++ b/src/drivers/i2c/w83795/w83795.c @@ -22,7 +22,9 @@ #include <console/console.h> #include <device/device.h> #include "southbridge/amd/cimx/sb700/smbus.h" /*SMBUS_IO_BASE*/ +#if CONFIG_BROADCAST_SIPI == 1 #include <cpu/x86/lapic.h> +#endif /* CONFIG_BROADCAST_SIPI */ #include "w83795.h" static u32 w83795_set_bank(u8 bank) @@ -225,8 +227,13 @@ static void w83795_init(w83795_fan_mode_t mode, u8 dts_src) static void w83795_hwm_init(device_t dev) { struct device *cpu; - +#if CONFIG_BROADCAST_SIPI == 0 + struct cpu_info *info; + info = cpu_info(); + cpu = info->cpu; +#else /* CONFIG_BROADCAST_SIPI */ cpu = dev_find_lapic(lapicid()); +#endif /* CONFIG_BROADCAST_SIPI */ if (!cpu) die("CPU: missing cpu device structure"); diff --git a/src/include/cpu/cpu.h b/src/include/cpu/cpu.h index 9765dfd..0bf85d6 100644 --- a/src/include/cpu/cpu.h +++ b/src/include/cpu/cpu.h @@ -4,12 +4,18 @@ #include <arch/cpu.h> #if !defined(__ROMCC__) + +#if CONFIG_BROADCAST_SIPI == 0 +void secondary_cpu_init(unsigned int cpu_index)__attribute__((regparm(0))); +void cpu_initialize(unsigned int cpu_index); +#else /* CONFIG_BROADCAST_SIPI */ +void secondary_cpu_init(int index); +extern unsigned int cpucount; void cpu_initialize(struct bus *cpu_bus, int index); +#endif /* CONFIG_BROADCAST_SIPI */ + struct bus; void initialize_cpus(struct bus *cpu_bus); -void secondary_cpu_init(int index); - -extern unsigned int cpucount; #if !CONFIG_WAIT_BEFORE_CPUS_INIT #define cpus_ready_for_init() do {} while(0)

1 0

Patch set updated for coreboot: 2c1b2df Make broadcast SIPI optional.
by Ronald G. Minnich 20 Jul '12

20 Jul '12

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1256 -gerrit commit 2c1b2df79630f12339625b6a2636716093fbbaed Author: Ronald G. Minnich <rminnich(a)google.com> Date: Fri Jul 20 11:13:51 2012 -0700 Make broadcast SIPI optional. Broadcast SIPI breaks some platforms. This change introduces a new configuration variable, BROADCAST_SIPI, that controls how SIPI is managed. The default is off, since we know that works. You can turn it on but be aware that even if your platform boots it may get very odd crashes. We need to finish up the broadcast SIPI code and that will take some work. Change-Id: Icf0bd0357353ab7ac4b217939152aa67e8255fa2 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/arch/x86/Kconfig | 18 ++- src/arch/x86/include/arch/cpu.h | 27 +++ src/arch/x86/lib/cpu.c | 40 ++++- src/cpu/intel/hyperthreading/intel_sibling.c | 46 ++++- src/cpu/intel/model_1067x/model_1067x_init.c | 10 + src/cpu/intel/model_106cx/Kconfig | 1 - src/cpu/intel/model_106cx/model_106cx_init.c | 9 + src/cpu/intel/model_206ax/acpi.c | 16 ++ src/cpu/intel/model_206ax/model_206ax_init.c | 64 ++++++ src/cpu/intel/model_6ex/model_6ex_init.c | 5 + src/cpu/intel/model_6fx/model_6fx_init.c | 6 + src/cpu/intel/model_f2x/model_f2x_init.c | 6 + src/cpu/intel/model_f3x/model_f3x_init.c | 7 + src/cpu/intel/model_f4x/model_f4x_init.c | 7 + src/cpu/x86/lapic/lapic_cpu_init.c | 286 ++++++++++++++++++++++++-- src/cpu/x86/lapic/secondary.S | 23 ++- src/cpu/x86/pae/pgtbl.c | 11 + src/drivers/i2c/w83795/w83795.c | 9 +- src/include/cpu/cpu.h | 12 +- 19 files changed, 574 insertions(+), 29 deletions(-) diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 4dfbe70..f679fa0 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -2,7 +2,23 @@ menu "Architecture (x86)" # This is an SMP option. It relates to starting up APs. # It is usually set in mainboard/*/Kconfig. -# TODO: Improve description. +# If set, startup uses a BROADCAST to start all cores at once +# It is wrong for some HT cores, e.g. those in chromebooks. +# Because it is breaks some platforms, and the old code works on +# all platforms, we leave it off. +config BROADCAST_SIPI + bool + default n + depends on ARCH_X86 + +# This is another SMP option. On some HT platforms the AP +# must not try to halt, but rather must wait in the +# secondary start code for another SIPI so it can stop +# correctly. +config AP_IN_SIPI_WAIT + bool + default n + depends on ARCH_X86 && ! BROADCAST_SIPI # Aligns 16bit entry code in bootblock so that hyper-threading CPUs # can boot AP CPUs to enable their shared caches. diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 0fe5ea5..29215fd 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -158,6 +158,33 @@ struct cpu_driver { struct device; struct cpu_driver *find_cpu_driver(struct device *cpu); +#if CONFIG_BROADCAST_SIPI == 0 +struct cpu_info { + device_t cpu; + unsigned int index; +}; + +static inline struct cpu_info *cpu_info(void) +{ + struct cpu_info *ci; + __asm__("andl %%esp,%0; " + "orl %2, %0 " + :"=r" (ci) + : "0" (~(CONFIG_STACK_SIZE - 1)), + "r" (CONFIG_STACK_SIZE - sizeof(struct cpu_info)) + ); + return ci; +} + +static inline unsigned long cpu_index(void) +{ + struct cpu_info *ci; + ci = cpu_info(); + return ci->index; +} + +#endif /* ! CONFIG_BROADCAST_SIPI */ + struct cpuinfo_x86 { uint8_t x86; /* CPU family */ uint8_t x86_vendor; /* CPU vendor */ diff --git a/src/arch/x86/lib/cpu.c b/src/arch/x86/lib/cpu.c index 7cd955e..65f8a22 100644 --- a/src/arch/x86/lib/cpu.c +++ b/src/arch/x86/lib/cpu.c @@ -9,7 +9,9 @@ #include <device/path.h> #include <device/device.h> #include <smp/spinlock.h> +#if CONFIG_BROADCAST_SIPI == 1 #include <cpu/x86/lapic.h> +#endif /* CONFIG_BROADCAST_SIPI */ /* Standard macro to see if a specific flag is changeable */ static inline int flag_is_changeable_p(uint32_t flag) @@ -235,7 +237,15 @@ static void set_cpu_ops(struct device *cpu) cpu->ops = driver ? driver->ops : NULL; } +#if CONFIG_BROADCAST_SIPI == 0 +void cpu_initialize(unsigned int index) +#else /* CONFIG_BROADCAST_SIPI */ +#if CONFIG_SMP +static spinlock_t start_cpu_lock = SPIN_LOCK_UNLOCKED; +#endif + void cpu_initialize(struct bus *cpu_bus, int index) +#endif /* CONFIG_BROADCAST_SIPI */ { /* Because we busy wait at the printk spinlock. * It is important to keep the number of printed messages @@ -244,16 +254,41 @@ void cpu_initialize(struct bus *cpu_bus, int index) */ struct device *cpu; struct cpuinfo_x86 c; - struct device_path cpu_path; unsigned char id = lapicid(); +#if CONFIG_BROADCAST_SIPI == 1 + struct device_path cpu_path; cpu_path.type = DEVICE_PATH_APIC; cpu_path.apic.apic_id = id; + cpu_path.type = DEVICE_PATH_APIC; + cpu_path.apic.apic_id = id; + cpu_path.apic.index = index; +#if CONFIG_SMP + spin_lock(&start_cpu_lock); +#endif cpu = alloc_find_dev(cpu_bus, &cpu_path); +#if CONFIG_SMP + spin_unlock(&start_cpu_lock); +#endif + printk(BIOS_DEBUG, "Initializing CPU #%d\n", id); +#else /* ! CONFIG_BROADCAST_SIPI */ + struct cpu_info *info; + info = cpu_info(); + + cpu = info->cpu; + if (!cpu) { + die("CPU: missing cpu device structure"); + } + cpu->path.apic.index = index; printk(BIOS_DEBUG, "Initializing CPU #%d\n", id); + cpu = info->cpu; + if (!cpu) { + die("CPU: missing cpu device structure"); + } +#endif /* CONFIG_BROADCAST_SIPI */ /* Find what type of cpu we are dealing with */ identify_cpu(cpu); @@ -284,8 +319,7 @@ void cpu_initialize(struct bus *cpu_bus, int index) cpu->ops->init(cpu); } - printk(BIOS_INFO, "CPU #%d initialized\n", id); + printk(BIOS_INFO, "CPU #%d ,lapic id %d, initialized\n", index, id); - return; } diff --git a/src/cpu/intel/hyperthreading/intel_sibling.c b/src/cpu/intel/hyperthreading/intel_sibling.c index 8377cd0..cabd3cc 100644 --- a/src/cpu/intel/hyperthreading/intel_sibling.c +++ b/src/cpu/intel/hyperthreading/intel_sibling.c @@ -7,13 +7,55 @@ #include <smp/spinlock.h> #include <assert.h> +#if CONFIG_BROADCAST_SIPI == 0 +#if !CONFIG_SERIAL_CPU_INIT +#error Intel hyper-threading requires serialized cpu init +#endif + +static int first_time = 1; +static int disable_siblings = !CONFIG_LOGICAL_CPUS; + +void intel_sibling_init(device_t cpu) +{ + unsigned int core_ids, apic_ids, threads; + + /* See if I am a sibling cpu */ + if (cpu->path.apic.apic_id & (siblings -1)) { + if (disable_siblings) { + cpu->enabled = 0; + } + return; + } + /* I am the primary cpu start up my siblings */ + for(i = 1; i < siblings; i++) { + struct device_path cpu_path; + device_t new; + /* Build the cpu device path */ + cpu_path.type = DEVICE_PATH_APIC; + cpu_path.apic.apic_id = cpu->path.apic.apic_id + i; + + /* Allocate new cpu device structure iff sibling CPU + * was not in static device tree. + */ + new = alloc_find_dev(cpu->bus, &cpu_path); + + if (!new) { + continue; + } + + printk(BIOS_DEBUG, "CPU: %u has sibling %u\n", + cpu->path.apic.apic_id, + new->path.apic.apic_id); + } +} + +#else /* CONFIG_BROADCAST_SIPI */ /* Return true if running thread does not have the smallest lapic ID * within a CPU core. */ int intel_ht_sibling(void) { unsigned int core_ids, apic_ids, threads; - apic_ids = 1; if (cpuid_eax(0) >= 1) apic_ids = (cpuid_ebx(1) >> 16) & 0xff; @@ -27,3 +69,5 @@ int intel_ht_sibling(void) threads = (apic_ids / core_ids); return !!(lapicid() & (threads-1)); } +#endif /* CONFIG_BROADCAST_SIPI */ + diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c index ddd1381..4a91b04 100644 --- a/src/cpu/intel/model_1067x/model_1067x_init.c +++ b/src/cpu/intel/model_1067x/model_1067x_init.c @@ -29,6 +29,10 @@ #include <cpu/x86/lapic.h> #include <cpu/intel/microcode.h> #include <cpu/intel/speedstep.h> + +#if CONFIG_BROADCAST_SIPI == 0 +#include <cpu/intel/hyperthreading.h> +#endif /* ! CONFIG_BROADCAST_SIPI */ #include <cpu/x86/cache.h> #include <cpu/x86/name.h> @@ -220,6 +224,12 @@ static void model_1067x_init(device_t cpu) /* PIC thermal sensor control */ configure_pic_thermal_sensors(); +#if CONFIG_BROADCAST_SIPI == 0 + + /* Start up my cpu siblings */ + intel_sibling_init(cpu); +#endif /* ! CONFIG_BROADCAST_SIPI */ + } static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_106cx/Kconfig b/src/cpu/intel/model_106cx/Kconfig index 2ef7392..00abf6b 100644 --- a/src/cpu/intel/model_106cx/Kconfig +++ b/src/cpu/intel/model_106cx/Kconfig @@ -11,4 +11,3 @@ config CPU_ADDR_BITS default 32 endif - diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c index 8d2ef3d..16660ac 100644 --- a/src/cpu/intel/model_106cx/model_106cx_init.c +++ b/src/cpu/intel/model_106cx/model_106cx_init.c @@ -27,6 +27,10 @@ #include <cpu/x86/lapic.h> #include <cpu/intel/microcode.h> #include <cpu/intel/speedstep.h> + +#if CONFIG_BROADCAST_SIPI == 0 +#include <cpu/intel/hyperthreading.h> +#endif /* ! CONFIG_BROADCAST_SIPI */ #include <cpu/x86/cache.h> #include <cpu/x86/name.h> #include <usbdebug.h> @@ -177,6 +181,11 @@ static void model_106cx_init(device_t cpu) configure_misc(); /* TODO: PIC thermal sensor control */ +#if CONFIG_BROADCAST_SIPI == 0 + + /* Start up my cpu siblings */ + intel_sibling_init(cpu); +#endif /* ! CONFIG_BROADCAST_SIPI */ } static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_206ax/acpi.c b/src/cpu/intel/model_206ax/acpi.c index dea23e7..1b5fa0a 100644 --- a/src/cpu/intel/model_206ax/acpi.c +++ b/src/cpu/intel/model_206ax/acpi.c @@ -26,7 +26,9 @@ #include <arch/acpigen.h> #include <arch/cpu.h> #include <cpu/x86/msr.h> +#if CONFIG_BROADCAST_SIPI == 1 #include <cpu/x86/lapic.h> +#endif /* CONFIG_BROADCAST_SIPI */ #include <cpu/intel/acpi.h> #include <cpu/intel/speedstep.h> #include <cpu/intel/turbo.h> @@ -89,8 +91,14 @@ static int generate_cstate_entries(acpi_cstate_t *cstates, static int generate_C_state_entries(void) { +#if CONFIG_BROADCAST_SIPI == 0 + struct cpu_info *info; +#endif /* ! CONFIG_BROADCAST_SIPI */ + struct cpu_driver *cpu; +#if CONFIG_BROADCAST_SIPI == 1 struct cpu_driver *cpu; struct device *cpu_dev; +#endif /* CONFIG_BROADCAST_SIPI */ int len, lenif; device_t lapic; struct cpu_intel_model_206ax_config *conf = NULL; @@ -104,10 +112,18 @@ static int generate_C_state_entries(void) return 0; /* Find CPU map of supported C-states */ +#if CONFIG_BROADCAST_SIPI == 0 + info = cpu_info(); + if (!info) + return 0; + cpu = find_cpu_driver(info->cpu); +#else /* CONFIG_BROADCAST_SIPI */ cpu_dev = dev_find_lapic(lapicid()); if (!cpu_dev) return 0; cpu = find_cpu_driver(cpu_dev); +#endif /* CONFIG_BROADCAST_SIPI */ + if (!cpu || !cpu->cstates) return 0; diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index d60c237..6e76d7f 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -414,6 +414,63 @@ static void configure_mca(void) static unsigned ehci_debug_addr; #endif +#if CONFIG_BROADCAST_SIPI == 0 +/* + * Initialize any extra cores/threads in this package. + */ +static void intel_cores_init(device_t cpu) +{ + struct cpuid_result result; + unsigned cores, threads, i; + + result = cpuid_ext(0xb, 0); /* Threads per core */ + threads = result.ebx & 0xff; + + result = cpuid_ext(0xb, 1); /* Cores per package */ + cores = result.ebx & 0xff; + + /* Only initialize extra cores from BSP */ + if (cpu->path.apic.apic_id) + return; + + printk(BIOS_DEBUG, "CPU: %u has %u cores %u threads\n", + cpu->path.apic.apic_id, cores, threads); + + for (i = 1; i < cores; ++i) { + struct device_path cpu_path; + device_t new; + + /* Build the cpu device path */ + cpu_path.type = DEVICE_PATH_APIC; + cpu_path.apic.apic_id = + cpu->path.apic.apic_id + i; + + /* Update APIC ID if no hyperthreading */ + if (threads == 1) + cpu_path.apic.apic_id <<= 1; + + /* Allocate the new cpu device structure */ + new = alloc_dev(cpu->bus, &cpu_path); + if (!new) + continue; + + printk(BIOS_DEBUG, "CPU: %u has core %u\n", + cpu->path.apic.apic_id, + new->path.apic.apic_id); + +#if CONFIG_SMP && CONFIG_MAX_CPUS > 1 + /* Start the new cpu */ + if (!start_cpu(new)) { + /* Record the error in cpu? */ + printk(BIOS_ERR, "CPU %u would not start!\n", + new->path.apic.apic_id); + } +#endif + } +} + +#endif /* ! CONFIG_BROADCAST_SIPI */ + static void model_206ax_init(device_t cpu) { char processor_name[49]; @@ -476,6 +533,13 @@ static void model_206ax_init(device_t cpu) /* Enable Turbo */ enable_turbo(); + +#if CONFIG_BROADCAST_SIPI == 0 + + /* Start up extra cores */ + intel_cores_init(cpu); +#endif /* ! CONFIG_BROADCAST_SIPI */ + } static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c index a0afd2e..989ca27 100644 --- a/src/cpu/intel/model_6ex/model_6ex_init.c +++ b/src/cpu/intel/model_6ex/model_6ex_init.c @@ -205,6 +205,11 @@ static void model_6ex_init(device_t cpu) /* PIC thermal sensor control */ configure_pic_thermal_sensors(); +#if CONFIG_BROADCAST_SIPI == 0 + + /* Start up my cpu siblings */ + intel_sibling_init(cpu); +#endif /* ! CONFIG_BROADCAST_SIPI */ } static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c index c5d7a6b..171059a 100644 --- a/src/cpu/intel/model_6fx/model_6fx_init.c +++ b/src/cpu/intel/model_6fx/model_6fx_init.c @@ -243,6 +243,12 @@ static void model_6fx_init(device_t cpu) /* PIC thermal sensor control */ configure_pic_thermal_sensors(); + +#if CONFIG_BROADCAST_SIPI == 0 + + /* Start up my cpu siblings */ + intel_sibling_init(cpu); +#endif /* ! CONFIG_BROADCAST_SIPI */ } static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_f2x/model_f2x_init.c b/src/cpu/intel/model_f2x/model_f2x_init.c index fa9e05f..87c3157 100644 --- a/src/cpu/intel/model_f2x/model_f2x_init.c +++ b/src/cpu/intel/model_f2x/model_f2x_init.c @@ -60,6 +60,12 @@ static void model_f2x_init(device_t cpu) /* Enable the local cpu apics */ setup_lapic(); + +#if CONFIG_BROADCAST_SIPI == 0 + + /* Start up my cpu siblings */ + intel_sibling_init(cpu); +#endif /* ! CONFIG_BROADCAST_SIPI */ }; static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_f3x/model_f3x_init.c b/src/cpu/intel/model_f3x/model_f3x_init.c index dd2a45f..96c38cd 100644 --- a/src/cpu/intel/model_f3x/model_f3x_init.c +++ b/src/cpu/intel/model_f3x/model_f3x_init.c @@ -43,6 +43,13 @@ static void model_f3x_init(device_t cpu) /* Enable the local cpu apics */ setup_lapic(); + +#if CONFIG_BROADCAST_SIPI == 0 + + /* Start up my cpu siblings */ + intel_sibling_init(cpu); +#endif /* ! CONFIG_BROADCAST_SIPI */ + }; static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_f4x/model_f4x_init.c b/src/cpu/intel/model_f4x/model_f4x_init.c index af7d9d2..cade95f 100644 --- a/src/cpu/intel/model_f4x/model_f4x_init.c +++ b/src/cpu/intel/model_f4x/model_f4x_init.c @@ -51,6 +51,13 @@ static void model_f4x_init(device_t cpu) /* Enable the local cpu apics */ setup_lapic(); + +#if CONFIG_BROADCAST_SIPI == 0 + + /* Start up my cpu siblings */ + intel_sibling_init(cpu); +#endif /* ! CONFIG_BROADCAST_SIPI */ + }; static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index b6dc560..b29340d 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -60,9 +60,27 @@ static void copy_secondary_start_to_1m_below(void) printk(BIOS_DEBUG, "start_eip=0x%08lx, code_size=0x%08lx\n", (long unsigned int)AP_SIPI_VECTOR, code_size); } -static struct bus *current_cpu_bus; +#ifdef __SSE3__ +static __inline__ __attribute__((always_inline)) unsigned long readcr4(void) +{ + unsigned long value; + __asm__ __volatile__ ( + "mov %%cr4, %[value]" + : [value] "=a" (value)); + return value; +} -static int lapic_start_cpus(struct bus *cpu_bus) +static __inline__ __attribute__((always_inline)) void + writecr4(unsigned long Data) +{ + __asm__ __volatile__ ( + "mov %%eax, %%cr4" + : + : "a" (Data) + ); +} +#if CONFIG_BROADCAST_SIPI == 0 +static int lapic_start_cpu(unsigned long apicid) { int timeout; unsigned long send_status, accept_status; @@ -187,26 +205,239 @@ static void stop_all_ap_cpus(void) mdelay(10); } -#ifdef __SSE3__ -static __inline__ __attribute__((always_inline)) unsigned long readcr4(void) + +/* C entry point of secondary cpus */ +void secondary_cpu_init(int index) { - unsigned long value; - __asm__ __volatile__ ( - "mov %%cr4, %[value]" - : [value] "=a" (value)); - return value; +#ifdef __SSE3__ + /* + * Seems that CR4 was cleared when AP start via lapic_start_cpu() + * Turn on CR4.OSFXSR and CR4.OSXMMEXCPT when SSE options enabled + */ + u32 cr4_val; + cr4_val = readcr4(); + cr4_val |= (1 << 9 | 1 << 10); + writecr4(cr4_val); +#endif + atomic_inc(&active_cpus); + cpu_initialize(current_cpu_bus, index); + atomic_dec(&active_cpus); } -static __inline__ __attribute__((always_inline)) void writecr4(unsigned long Data) +static void wait_other_cpus_stop(struct bus *cpu_bus) { - __asm__ __volatile__ ( - "mov %%eax, %%cr4" - : - : "a" (Data) - ); + device_t cpu; + int old_active_count, active_count; + long loopcount = 0; + + /* Now loop until the other cpus have finished initializing */ + old_active_count = 1; + active_count = atomic_read(&active_cpus); + while(active_count > 1) { + if (active_count != old_active_count) { + printk(BIOS_INFO, "Waiting for %d CPUS to stop\n", active_count - 1); + old_active_count = active_count; + } + udelay(10); + active_count = atomic_read(&active_cpus); + loopcount++; + } + for(cpu = cpu_bus->children; cpu; cpu = cpu->sibling) { + if (cpu->path.type != DEVICE_PATH_APIC) { + continue; + } + if (cpu->path.apic.apic_id == SPEEDSTEP_APIC_MAGIC) { + continue; + } + if (!cpu->initialized) { + printk(BIOS_ERR, "CPU 0x%02x did not initialize!\n", + cpu->path.apic.apic_id); + } + } + stop_all_ap_cpus(); + printk(BIOS_DEBUG, "All AP CPUs stopped (%ld loops)\n", loopcount); } + +#endif /* CONFIG_SMP */ + +void initialize_cpus(struct bus *cpu_bus) +{ + struct device_path cpu_path; + +#if NEED_LAPIC == 1 + /* Ensure the local apic is enabled */ + enable_lapic(); + + /* Get the device path of the boot cpu */ + cpu_path.type = DEVICE_PATH_APIC; + cpu_path.apic.apic_id = lapicid(); +#else + /* Get the device path of the boot cpu */ + cpu_path.type = DEVICE_PATH_CPU; + cpu_path.cpu.id = 0; +#endif + +#if CONFIG_SMP + copy_secondary_start_to_1m_below(); // why here? In case some day we can start core1 in amd_sibling_init +#endif + +#if CONFIG_HAVE_SMI_HANDLER + smm_init(); #endif + cpus_ready_for_init(); + + /* Initialize the bootstrap processor */ + cpu_initialize(cpu_bus, 0); + +#if CONFIG_SMP + lapic_start_cpus(cpu_bus); + /* Now wait the rest of the cpus stop*/ + wait_other_cpus_stop(cpu_bus); +#endif +} + +#else + +static struct bus *current_cpu_bus; + +static int lapic_start_cpus(struct bus *cpu_bus) +#if CONFIG_SMP && CONFIG_MAX_CPUS > 1 + +static struct bus *current_cpu_bus; + +static int lapic_start_cpus(struct bus *cpu_bus) +{ + int timeout; + unsigned long send_status, accept_status, start_eip; + int maxlvt; + + /* + * Starting actual IPI sequence... + */ + + current_cpu_bus = cpu_bus; + + printk(BIOS_SPEW, "Asserting INIT.\n"); + + /* Send INIT SIPI to target chip */ + lapic_write_around(LAPIC_ICR2, 0); + lapic_write_around(LAPIC_ICR, LAPIC_INT_ASSERT + | LAPIC_DM_INIT | LAPIC_DEST_ALLBUT); + + printk(BIOS_DEBUG, "Waiting for send to finish...\n"); + timeout = 0; + do { + printk(BIOS_SPEW, "+"); + udelay(100); + send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY; + } while (send_status && (timeout++ < 1000)); + if (timeout >= 1000) { + printk(BIOS_DEBUG, "First apic write timed out. Disabling\n"); + // too bad. + printk(BIOS_DEBUG, "ESR is 0x%lx\n", lapic_read(LAPIC_ESR)); + if (lapic_read(LAPIC_ESR)) { + printk(BIOS_DEBUG, "Try to reset ESR\n"); + lapic_write_around(LAPIC_ESR, 0); + printk(BIOS_DEBUG, "ESR is 0x%lx\n", lapic_read(LAPIC_ESR)); + } + return 0; + } + start_eip = get_valid_start_eip((unsigned long)_secondary_start); + + maxlvt = 4; + + printk(BIOS_SPEW, "Sending STARTUP.\n"); + lapic_read_around(LAPIC_SPIV); + lapic_write(LAPIC_ESR, 0); + lapic_read(LAPIC_ESR); + printk(BIOS_SPEW, "After apic_write.\n"); + + /* + * STARTUP IPI + */ + + /* Target chip */ + lapic_write_around(LAPIC_ICR2, 0); + printk(BIOS_SPEW, "After apic_write_around(LAPIC_ICR2, 0);\n"); + + /* Boot on the stack */ + /* Kick the second */ + lapic_write_around(LAPIC_ICR, + LAPIC_INT_ASSERT | LAPIC_DM_STARTUP | LAPIC_DEST_ALLBUT + | (start_eip >> 12)); + printk(BIOS_SPEW, "After apic_write_around allbut starteip %p.\n", + (void *)start_eip); + + /* + * Give the other CPU some time to accept the IPI. + */ + udelay(300); + + printk(BIOS_DEBUG, "Startup point 1.\n"); + + printk(BIOS_DEBUG, "Waiting for send to finish...\n"); + timeout = 0; + do { + printk(BIOS_DEBUG, "+"); + udelay(100); + send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY; + } while (send_status && (timeout++ < 1000)); + + /* + * Give the other CPU some time to accept the IPI. + */ + udelay(200); + /* + * Due to the Pentium erratum 3AP. + */ + if (maxlvt > 3) { + lapic_read_around(LAPIC_SPIV); + lapic_write(LAPIC_ESR, 0); + } + accept_status = (lapic_read(LAPIC_ESR) & 0xEF); + + printk(BIOS_DEBUG, "After Startup.\n"); + if (send_status) + printk(BIOS_WARNING, "APIC never delivered???\n"); + if (accept_status) + printk(BIOS_WARNING, "APIC delivery error (%lx).\n", + accept_status); + if (send_status || accept_status) + return 0; + return 1; +} + + +/* Number of cpus that are currently running in coreboot */ +static atomic_t active_cpus = ATOMIC_INIT(1); + +volatile unsigned long secondary_stack; +extern unsigned char _estack[]; + +static void stop_all_ap_cpus(void) +{ + unsigned long send_status; + int timeout; + /* send an LAPIC INIT to all but myself */ + lapic_write_around(LAPIC_ICR2, 0); + lapic_write_around(LAPIC_ICR, + LAPIC_INT_ASSERT | LAPIC_DM_INIT | LAPIC_DEST_ALLBUT); + + /* wait for the ipi send to finish */ + printk(BIOS_SPEW, "Waiting for send to finish...\n"); + timeout = 0; + do { + printk(BIOS_SPEW, "+"); + udelay(100); + send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY; + } while (send_status && (timeout++ < 1000)); + if (timeout >= 1000) { + printk(BIOS_ERR, "timed out\n"); + } + mdelay(10); +} + /* C entry point of secondary cpus */ void secondary_cpu_init(int index) { @@ -236,7 +467,8 @@ static void wait_other_cpus_stop(struct bus *cpu_bus) active_count = atomic_read(&active_cpus); while(active_count > 1) { if (active_count != old_active_count) { - printk(BIOS_INFO, "Waiting for %d CPUS to stop\n", active_count - 1); + printk(BIOS_INFO, "Waiting for %d CPUS to stop\n", + active_count - 1); old_active_count = active_count; } udelay(10); @@ -257,6 +489,23 @@ static void wait_other_cpus_stop(struct bus *cpu_bus) } stop_all_ap_cpus(); printk(BIOS_DEBUG, "All AP CPUs stopped (%ld loops)\n", loopcount); +#if 0 + for(i = 1; i <= last_cpu_index; i++){ + unsigned long *stack = stacks[i]; + int lowest; + int maxstack = (CONFIG_STACK_SIZE - sizeof(struct cpu_info)) + /sizeof(*stack) - 1; + if (stack[0] != 0xDEADBEEF) + printk(BIOS_ERR, "CPU%d overran its stack\n", i); + for(lowest = 0; lowest < maxstack; lowest++) + if (stack[lowest] != 0xDEADBEEF) + break; + printk(BIOS_SPEW, "CPU%d: stack allocated from %p to %p:", i, + stack, &stack[maxstack]); + printk(BIOS_SPEW, "lowest stack address was %p\n", + &stack[lowest]); + } +#endif } #endif /* CONFIG_SMP */ @@ -279,7 +528,8 @@ void initialize_cpus(struct bus *cpu_bus) #endif #if CONFIG_SMP - copy_secondary_start_to_1m_below(); // why here? In case some day we can start core1 in amd_sibling_init + // why here? In case some day we can start core1 in amd_sibling_init + copy_secondary_start_to_lowest_1M(); #endif #if CONFIG_HAVE_SMI_HANDLER @@ -297,4 +547,4 @@ void initialize_cpus(struct bus *cpu_bus) wait_other_cpus_stop(cpu_bus); #endif } - +#endif \ No newline at end of file diff --git a/src/cpu/x86/lapic/secondary.S b/src/cpu/x86/lapic/secondary.S index e6650ec..b56e378 100644 --- a/src/cpu/x86/lapic/secondary.S +++ b/src/cpu/x86/lapic/secondary.S @@ -2,7 +2,11 @@ #include <cpu/x86/lapic_def.h> .text - .globl _secondary_start, _secondary_start_end, cpucount, ap_protected_start + .globl _secondary_start, _secondary_start_end, ap_protected_start +#if CONFIG_BROADCAST_SIPI == 1 + .globl cpucount +#endif + .balign 4096 _secondary_start: .code16 cli @@ -49,6 +53,14 @@ __ap_protected_start: /* Load the Interrupt descriptor table */ lidt idtarg +#if CONFIG_BROADCAST_SIPI == 0 + /* Set the stack pointer, and flag that we are done */ + xorl %eax, %eax + movl secondary_stack, %esp + movl secondary_cpu_index, %edi + pushl %edi + movl %eax, secondary_stack +#else /* CONFIG_BROADCAST_SIPI */ /* increment our cpu index */ movl $1, %eax lock xadd %eax, cpucount @@ -61,10 +73,19 @@ __ap_protected_start: add %eax, %esp pushl %ecx +#endif /* CONFIG_BROADCAST_SIPI */ + call secondary_cpu_init 1: hlt jmp 1b +#if CONFIG_BROADCAST_SIPI == 1 cpucount: .long 1 +#endif /* CONFIG_BROADCAST_SIPI */ +gdtaddr: + .word gdt_limit /* the table limit */ + .long gdt /* we know the offset */ + +_secondary_start_end: .code32 diff --git a/src/cpu/x86/pae/pgtbl.c b/src/cpu/x86/pae/pgtbl.c index 7aa17c2..f84ec6e 100644 --- a/src/cpu/x86/pae/pgtbl.c +++ b/src/cpu/x86/pae/pgtbl.c @@ -7,6 +7,15 @@ #include <cpu/cpu.h> #include <cpu/x86/pae.h> #include <cpu/x86/lapic.h> + +#if CONFIG_BROADCAST_SIPI == 1 +#include <device/device.h> +#endif /* CONFIG_BROADCAST_SIPI */ +#include <cpu/cpu.h> +#include <cpu/x86/pae.h> +#if CONFIG_BROADCAST_SIPI == 1 +#include <cpu/x86/lapic.h> +#endif /* CONFIG_BROADCAST_SIPI */ #include <string.h> static void paging_off(void) @@ -45,6 +54,7 @@ static void paging_on(void *pdp) ); } +#if CONFIG_BROADCAST_SIPI == 1 static int cpu_index(void) { device_t dev = dev_find_lapic(lapicid()); @@ -53,6 +63,7 @@ static int cpu_index(void) return dev->path.apic.index; } +#endif /* CONFIG_BROADCAST_SIPI */ void *map_2M_page(unsigned long page) { struct pde { diff --git a/src/drivers/i2c/w83795/w83795.c b/src/drivers/i2c/w83795/w83795.c index 12be4da..14b12b3 100644 --- a/src/drivers/i2c/w83795/w83795.c +++ b/src/drivers/i2c/w83795/w83795.c @@ -22,7 +22,9 @@ #include <console/console.h> #include <device/device.h> #include "southbridge/amd/cimx/sb700/smbus.h" /*SMBUS_IO_BASE*/ +#if CONFIG_BROADCAST_SIPI == 1 #include <cpu/x86/lapic.h> +#endif /* CONFIG_BROADCAST_SIPI */ #include "w83795.h" static u32 w83795_set_bank(u8 bank) @@ -225,8 +227,13 @@ static void w83795_init(w83795_fan_mode_t mode, u8 dts_src) static void w83795_hwm_init(device_t dev) { struct device *cpu; - +#if CONFIG_BROADCAST_SIPI == 0 + struct cpu_info *info; + info = cpu_info(); + cpu = info->cpu; +#else /* CONFIG_BROADCAST_SIPI */ cpu = dev_find_lapic(lapicid()); +#endif /* CONFIG_BROADCAST_SIPI */ if (!cpu) die("CPU: missing cpu device structure"); diff --git a/src/include/cpu/cpu.h b/src/include/cpu/cpu.h index 9765dfd..0bf85d6 100644 --- a/src/include/cpu/cpu.h +++ b/src/include/cpu/cpu.h @@ -4,12 +4,18 @@ #include <arch/cpu.h> #if !defined(__ROMCC__) + +#if CONFIG_BROADCAST_SIPI == 0 +void secondary_cpu_init(unsigned int cpu_index)__attribute__((regparm(0))); +void cpu_initialize(unsigned int cpu_index); +#else /* CONFIG_BROADCAST_SIPI */ +void secondary_cpu_init(int index); +extern unsigned int cpucount; void cpu_initialize(struct bus *cpu_bus, int index); +#endif /* CONFIG_BROADCAST_SIPI */ + struct bus; void initialize_cpus(struct bus *cpu_bus); -void secondary_cpu_init(int index); - -extern unsigned int cpucount; #if !CONFIG_WAIT_BEFORE_CPUS_INIT #define cpus_ready_for_init() do {} while(0)

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coreboot July 2012