Patch set updated for coreboot: d9c108e cs5536: add smbus support in ramstage
by Christian Gmeiner 20 Jul '12
by Christian Gmeiner 20 Jul '12
20 Jul '12
Christian Gmeiner (christian.gmeiner(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1243
-gerrit
commit d9c108eef717bc1de1b86b8120267b4c3a00f06d
Author: Christian Gmeiner <christian.gmeiner(a)gmail.com>
Date: Fri Jul 20 10:21:29 2012 +0200
cs5536: add smbus support in ramstage
With this patch it is possible to use the smbus in ramstage. The
biggest part of the patch is a simple code split into a general
part (smbus.h) and the concrete users (early_smbus.c and cs5536.c).
After the switch from romstage to ramstage the smb base address
has changed, but that is no problem as the new base address is
stored in bar0 of the ISA bridge. It could also be read via msr,
but via PCI it is simpler. I used the following patch as
reference on how to readout the new base address:
http://lists.laptop.org/pipermail/commits-kernel/2006-November/000178.html
Change-Id: I9f86a1e474368c62f9ed3a95edfb3e63117aa156
Signed-off-by: Christian Gmeiner <christian.gmeiner(a)gmail.com>
---
src/southbridge/amd/cs5536/Makefile.inc | 2 +
src/southbridge/amd/cs5536/cs5536.c | 20 +++
src/southbridge/amd/cs5536/early_smbus.c | 176 +--------------------------
src/southbridge/amd/cs5536/smbus.c | 199 ++++++++++++++++++++++++++++++
src/southbridge/amd/cs5536/smbus.h | 34 +++++
5 files changed, 256 insertions(+), 175 deletions(-)
diff --git a/src/southbridge/amd/cs5536/Makefile.inc b/src/southbridge/amd/cs5536/Makefile.inc
index 75c6e5c..3d2613b 100644
--- a/src/southbridge/amd/cs5536/Makefile.inc
+++ b/src/southbridge/amd/cs5536/Makefile.inc
@@ -20,3 +20,5 @@
driver-y += cs5536.c
driver-y += ide.c
driver-y += pirq.c
+driver-y += smbus.c
+romstage-y += smbus.c
\ No newline at end of file
diff --git a/src/southbridge/amd/cs5536/cs5536.c b/src/southbridge/amd/cs5536/cs5536.c
index 872de36..0c0368f 100644
--- a/src/southbridge/amd/cs5536/cs5536.c
+++ b/src/southbridge/amd/cs5536/cs5536.c
@@ -23,6 +23,7 @@
#include <device/pci.h>
#include <device/pci_ops.h>
#include <device/pci_ids.h>
+#include <device/smbus.h>
#include <console/console.h>
#include <stdint.h>
#include <pc80/isa-dma.h>
@@ -33,6 +34,7 @@
#include <stdlib.h>
#include "chip.h"
#include "cs5536.h"
+#include "smbus.h"
struct msrinit {
u32 msrnum;
@@ -667,6 +669,23 @@ static void southbridge_enable(struct device *dev)
}
+static int lsmbus_read_byte(device_t dev, u8 address)
+{
+ u16 device;
+ struct resource *res;
+ struct bus *pbus;
+
+ device = dev->path.i2c.device;
+ pbus = get_pbus_smbus(dev);
+ res = find_resource(pbus->dev, 0x10);
+
+ return do_smbus_read_byte(res->base, device, address);
+}
+
+static struct smbus_bus_operations lops_smbus_bus = {
+ .read_byte = lsmbus_read_byte,
+};
+
static struct device_operations southbridge_ops = {
.read_resources = cs5536_read_resources,
.set_resources = pci_dev_set_resources,
@@ -674,6 +693,7 @@ static struct device_operations southbridge_ops = {
.init = southbridge_init,
// .enable = southbridge_enable,
.scan_bus = scan_static_bus,
+ .ops_smbus_bus = &lops_smbus_bus,
};
static const struct pci_driver cs5536_pci_driver __pci_driver = {
diff --git a/src/southbridge/amd/cs5536/early_smbus.c b/src/southbridge/amd/cs5536/early_smbus.c
index 814bc5a..c3f6817 100644
--- a/src/southbridge/amd/cs5536/early_smbus.c
+++ b/src/southbridge/amd/cs5536/early_smbus.c
@@ -18,11 +18,7 @@
*/
#include "cs5536.h"
-
-#define SMBUS_ERROR -1
-#define SMBUS_WAIT_UNTIL_READY_TIMEOUT -2
-#define SMBUS_WAIT_UNTIL_DONE_TIMEOUT -3
-#define SMBUS_TIMEOUT (1000)
+#include "smbus.h"
/* initialization for SMBus Controller */
static void cs5536_enable_smbus(void)
@@ -37,176 +33,6 @@ static void cs5536_enable_smbus(void)
}
-static void smbus_delay(void)
-{
- /* inb(0x80); */
-}
-
-static int smbus_wait(unsigned smbus_io_base)
-{
- unsigned long loops = SMBUS_TIMEOUT;
- unsigned char val;
-
- do {
- smbus_delay();
- val = inb(smbus_io_base + SMB_STS);
- if ((val & SMB_STS_SDAST) != 0)
- break;
- if (val & (SMB_STS_BER | SMB_STS_NEGACK)) {
- /*printk(BIOS_DEBUG, "SMBUS WAIT ERROR %x\n", val); */
- return SMBUS_ERROR;
- }
- } while (--loops);
- return loops ? 0 : SMBUS_WAIT_UNTIL_READY_TIMEOUT;
-}
-
-/* generate a smbus start condition */
-static int smbus_start_condition(unsigned smbus_io_base)
-{
- unsigned char val;
-
- /* issue a START condition */
- val = inb(smbus_io_base + SMB_CTRL1);
- outb(val | SMB_CTRL1_START, smbus_io_base + SMB_CTRL1);
-
- /* check for bus conflict */
- val = inb(smbus_io_base + SMB_STS);
- if ((val & SMB_STS_BER) != 0)
- return SMBUS_ERROR;
-
- return smbus_wait(smbus_io_base);
-}
-
-static int smbus_check_stop_condition(unsigned smbus_io_base)
-{
- unsigned char val;
- unsigned long loops;
- loops = SMBUS_TIMEOUT;
- /* check for SDA status */
- do {
- smbus_delay();
- val = inb(smbus_io_base + SMB_CTRL1);
- if ((val & SMB_CTRL1_STOP) == 0) {
- break;
- }
- outb((0x7F << 1) | SMB_CTRL2_ENABLE, smbus_io_base + SMB_CTRL2);
- } while (--loops);
- return loops ? 0 : SMBUS_WAIT_UNTIL_READY_TIMEOUT;
-}
-
-static int smbus_stop_condition(unsigned smbus_io_base)
-{
- outb(SMB_CTRL1_STOP, smbus_io_base + SMB_CTRL1);
- return smbus_wait(smbus_io_base);
-}
-
-static int smbus_ack(unsigned smbus_io_base, int state)
-{
- unsigned char val = inb(smbus_io_base + SMB_CTRL1);
-
-/* if (state) */
- outb(val | SMB_CTRL1_ACK, smbus_io_base + SMB_CTRL1);
-/* else
- outb(val & ~SMB_CTRL1_ACK, smbus_io_base + SMB_CTRL1);
-*/
- return 0;
-}
-
-static int smbus_send_slave_address(unsigned smbus_io_base,
- unsigned char device)
-{
- unsigned char val;
-
- /* send the slave address */
- outb(device, smbus_io_base + SMB_SDA);
-
- /* check for bus conflict and NACK */
- val = inb(smbus_io_base + SMB_STS);
- if (((val & SMB_STS_BER) != 0) || ((val & SMB_STS_NEGACK) != 0)) {
- /* printk(BIOS_DEBUG, "SEND SLAVE ERROR (%x)\n", val); */
- return SMBUS_ERROR;
- }
- return smbus_wait(smbus_io_base);
-}
-
-static int smbus_send_command(unsigned smbus_io_base, unsigned char command)
-{
- unsigned char val;
-
- /* send the command */
- outb(command, smbus_io_base + SMB_SDA);
-
- /* check for bus conflict and NACK */
- val = inb(smbus_io_base + SMB_STS);
- if (((val & SMB_STS_BER) != 0) || ((val & SMB_STS_NEGACK) != 0))
- return SMBUS_ERROR;
-
- return smbus_wait(smbus_io_base);
-}
-
-static unsigned char smbus_get_result(unsigned smbus_io_base)
-{
- return inb(smbus_io_base + SMB_SDA);
-}
-
-static unsigned char do_smbus_read_byte(unsigned smbus_io_base,
- unsigned char device,
- unsigned char address)
-{
- unsigned char error = 0;
-
- if ((smbus_check_stop_condition(smbus_io_base))) {
- error = 1;
- goto err;
- }
-
- if ((smbus_start_condition(smbus_io_base))) {
- error = 2;
- goto err;
- }
-
- if ((smbus_send_slave_address(smbus_io_base, device << 1))) {
- error = 3;
- goto err;
- }
-
- smbus_ack(smbus_io_base, 1);
-
- if ((smbus_send_command(smbus_io_base, address))) {
- error = 4;
- goto err;
- }
-
- if ((smbus_start_condition(smbus_io_base))) {
- error = 5;
- goto err;
- }
-
- if ((smbus_send_slave_address(smbus_io_base, (device << 1) | 0x01))) {
- error = 6;
- goto err;
- }
-
- if ((smbus_stop_condition(smbus_io_base))) {
- error = 7;
- goto err;
- }
-
- return smbus_get_result(smbus_io_base);
-
-err:
- print_debug("SMBUS READ ERROR:");
- print_debug_hex8(error);
- print_debug(" device:");
- print_debug_hex8(device);
- print_debug("\n");
- /* stop, clean up the error, and leave */
- smbus_stop_condition(smbus_io_base);
- outb(inb(smbus_io_base + SMB_STS), smbus_io_base + SMB_STS);
- outb(0x0, smbus_io_base + SMB_STS);
- return 0xFF;
-}
-
static inline int smbus_read_byte(unsigned device, unsigned address)
{
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
diff --git a/src/southbridge/amd/cs5536/smbus.c b/src/southbridge/amd/cs5536/smbus.c
new file mode 100644
index 0000000..3b948c4
--- /dev/null
+++ b/src/southbridge/amd/cs5536/smbus.c
@@ -0,0 +1,199 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <arch/io.h>
+#include "cs5536.h"
+#include "smbus.h"
+
+#define SMBUS_ERROR -1
+#define SMBUS_WAIT_UNTIL_READY_TIMEOUT -2
+#define SMBUS_WAIT_UNTIL_DONE_TIMEOUT -3
+#define SMBUS_TIMEOUT (1000)
+
+static void smbus_delay(void)
+{
+ /* inb(0x80); */
+}
+
+static int smbus_wait(unsigned smbus_io_base)
+{
+ unsigned long loops = SMBUS_TIMEOUT;
+ unsigned char val;
+
+ do {
+ smbus_delay();
+ val = inb(smbus_io_base + SMB_STS);
+ if ((val & SMB_STS_SDAST) != 0)
+ break;
+ if (val & (SMB_STS_BER | SMB_STS_NEGACK)) {
+ /*printk(BIOS_DEBUG, "SMBUS WAIT ERROR %x\n", val); */
+ return SMBUS_ERROR;
+ }
+ } while (--loops);
+ return loops ? 0 : SMBUS_WAIT_UNTIL_READY_TIMEOUT;
+}
+
+/* generate a smbus start condition */
+int smbus_start_condition(unsigned smbus_io_base)
+{
+ unsigned char val;
+
+ /* issue a START condition */
+ val = inb(smbus_io_base + SMB_CTRL1);
+ outb(val | SMB_CTRL1_START, smbus_io_base + SMB_CTRL1);
+
+ /* check for bus conflict */
+ val = inb(smbus_io_base + SMB_STS);
+ if ((val & SMB_STS_BER) != 0)
+ return SMBUS_ERROR;
+
+ return smbus_wait(smbus_io_base);
+}
+
+int smbus_check_stop_condition(unsigned smbus_io_base)
+{
+ unsigned char val;
+ unsigned long loops;
+ loops = SMBUS_TIMEOUT;
+ /* check for SDA status */
+ do {
+ smbus_delay();
+ val = inb(smbus_io_base + SMB_CTRL1);
+ if ((val & SMB_CTRL1_STOP) == 0) {
+ break;
+ }
+ outb((0x7F << 1) | SMB_CTRL2_ENABLE, smbus_io_base + SMB_CTRL2);
+ } while (--loops);
+ return loops ? 0 : SMBUS_WAIT_UNTIL_READY_TIMEOUT;
+}
+
+int smbus_stop_condition(unsigned smbus_io_base)
+{
+ outb(SMB_CTRL1_STOP, smbus_io_base + SMB_CTRL1);
+ return smbus_wait(smbus_io_base);
+}
+
+static int smbus_ack(unsigned smbus_io_base, int state)
+{
+ unsigned char val = inb(smbus_io_base + SMB_CTRL1);
+
+/* if (state) */
+ outb(val | SMB_CTRL1_ACK, smbus_io_base + SMB_CTRL1);
+/* else
+ outb(val & ~SMB_CTRL1_ACK, smbus_io_base + SMB_CTRL1);
+*/
+ return 0;
+}
+
+int smbus_send_slave_address(unsigned smbus_io_base,
+ unsigned char device)
+{
+ unsigned char val;
+
+ /* send the slave address */
+ outb(device, smbus_io_base + SMB_SDA);
+
+ /* check for bus conflict and NACK */
+ val = inb(smbus_io_base + SMB_STS);
+ if (((val & SMB_STS_BER) != 0) || ((val & SMB_STS_NEGACK) != 0)) {
+ /* printk(BIOS_DEBUG, "SEND SLAVE ERROR (%x)\n", val); */
+ return SMBUS_ERROR;
+ }
+ return smbus_wait(smbus_io_base);
+}
+
+int smbus_send_command(unsigned smbus_io_base, unsigned char command)
+{
+ unsigned char val;
+
+ /* send the command */
+ outb(command, smbus_io_base + SMB_SDA);
+
+ /* check for bus conflict and NACK */
+ val = inb(smbus_io_base + SMB_STS);
+ if (((val & SMB_STS_BER) != 0) || ((val & SMB_STS_NEGACK) != 0))
+ return SMBUS_ERROR;
+
+ return smbus_wait(smbus_io_base);
+}
+
+static unsigned char smbus_get_result(unsigned smbus_io_base)
+{
+ return inb(smbus_io_base + SMB_SDA);
+}
+
+unsigned char do_smbus_read_byte(unsigned smbus_io_base,
+ unsigned char device,
+ unsigned char address)
+{
+ unsigned char error = 0;
+
+ if ((smbus_check_stop_condition(smbus_io_base))) {
+ error = 1;
+ goto err;
+ }
+
+ if ((smbus_start_condition(smbus_io_base))) {
+ error = 2;
+ goto err;
+ }
+
+ if ((smbus_send_slave_address(smbus_io_base, device << 1))) {
+ error = 3;
+ goto err;
+ }
+
+ smbus_ack(smbus_io_base, 1);
+
+ if ((smbus_send_command(smbus_io_base, address))) {
+ error = 4;
+ goto err;
+ }
+
+ if ((smbus_start_condition(smbus_io_base))) {
+ error = 5;
+ goto err;
+ }
+
+ if ((smbus_send_slave_address(smbus_io_base, (device << 1) | 0x01))) {
+ error = 6;
+ goto err;
+ }
+
+ if ((smbus_stop_condition(smbus_io_base))) {
+ error = 7;
+ goto err;
+ }
+
+ return smbus_get_result(smbus_io_base);
+
+err:
+ print_debug("SMBUS READ ERROR:");
+ print_debug_hex8(error);
+ print_debug(" device:");
+ print_debug_hex8(device);
+ print_debug("\n");
+ /* stop, clean up the error, and leave */
+ smbus_stop_condition(smbus_io_base);
+ outb(inb(smbus_io_base + SMB_STS), smbus_io_base + SMB_STS);
+ outb(0x0, smbus_io_base + SMB_STS);
+ return 0xFF;
+}
+
diff --git a/src/southbridge/amd/cs5536/smbus.h b/src/southbridge/amd/cs5536/smbus.h
new file mode 100644
index 0000000..318a727
--- /dev/null
+++ b/src/southbridge/amd/cs5536/smbus.h
@@ -0,0 +1,34 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _CS5536_SMBUS_H
+#define _CS5536_SMBUS_H
+
+int smbus_start_condition(unsigned smbus_io_base);
+int smbus_stop_condition(unsigned smbus_io_base);
+int smbus_check_stop_condition(unsigned smbus_io_base);
+int smbus_send_slave_address(unsigned smbus_io_base,
+ unsigned char device);
+int smbus_send_command(unsigned smbus_io_base, unsigned char command);
+
+unsigned char do_smbus_read_byte(unsigned smbus_io_base,
+ unsigned char device,
+ unsigned char address);
+
+#endif /* _CS5536_SMBUS_H */
1
0
Good day (or any other time)!
While working with/on libpayload for EHCI USB driver, i've found strange
error, when device is found (port status = 0x1803)
and sending first control transaction. (usb_attach_device/get_free_address).
Mainboard - Foxconn N15235
wait_for_tds(): ERROR with packet
========= EHCI TD at [0x0004d000] =========
__EHCI_TD cerr: 0, total_len: 8
__EHCI_TD: next_qtd [0x0004d120]
__EHCI_TD: alt_next_qtd [0x00000001]
__EHCI_TD: token [0x00080248]
__EHCI_TD: Bytes to Transfer [8]
__EHCI_TD: PID CODE: [2]
__EHCI_TD: Interrupt On Complete (IOC) [0]
__EHCI_TD: Status Active [0]
__EHCI_TD: Status Halted [1]
__EHCI_TD: Status Data Buffer Error [0]
__EHCI_TD: Status Babble detected [0]
__EHCI_TD: Status Transaction Error [1]
__EHCI_TD: Status Missed Micro Frame [0]
__EHCI_TD: Status Split Transaction State [0]
__EHCI_TD: Status Ping State [0]
wait_for_tds(): -----------------
Attaching full log, where dumping registers/packets on every step.
Hope someone know the reason.
Best regards,
Anton Kochkov.
1
0
Patch set updated for coreboot: f1de1ed cs5536: add smbus support in ramstage
by Christian Gmeiner 20 Jul '12
by Christian Gmeiner 20 Jul '12
20 Jul '12
Christian Gmeiner (christian.gmeiner(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1243
-gerrit
commit f1de1ed50ceecca3aa31687b341f09d704b927c7
Author: Christian Gmeiner <christian.gmeiner(a)gmail.com>
Date: Fri Jul 20 09:59:28 2012 +0200
cs5536: add smbus support in ramstage
With this patch it is possible to use the smbus in ramstage. The
biggest part of the patch is a simple code split into a general
part (smbus.h) and the concrete users (early_smbus.c and cs5536.c).
After the switch from romstage to ramstage the smb base address
has changed, but that is no problem as the new base address is
stored in bar0 of the ISA bridge. It could also be read via msr,
but via PCI it is simpler. I used the following patch as
reference on how to readout the new base address:
http://lists.laptop.org/pipermail/commits-kernel/2006-November/000178.html
Change-Id: I9f86a1e474368c62f9ed3a95edfb3e63117aa156
Signed-off-by: Christian Gmeiner <christian.gmeiner(a)gmail.com>
---
src/southbridge/amd/cs5536/Makefile.inc | 2 +
src/southbridge/amd/cs5536/cs5536.c | 20 +++
src/southbridge/amd/cs5536/early_smbus.c | 176 +--------------------------
src/southbridge/amd/cs5536/smbus.c | 199 ++++++++++++++++++++++++++++++
src/southbridge/amd/cs5536/smbus.h | 34 +++++
5 files changed, 256 insertions(+), 175 deletions(-)
diff --git a/src/southbridge/amd/cs5536/Makefile.inc b/src/southbridge/amd/cs5536/Makefile.inc
index 75c6e5c..3d2613b 100644
--- a/src/southbridge/amd/cs5536/Makefile.inc
+++ b/src/southbridge/amd/cs5536/Makefile.inc
@@ -20,3 +20,5 @@
driver-y += cs5536.c
driver-y += ide.c
driver-y += pirq.c
+driver-y += smbus.c
+romstage-y += smbus.c
\ No newline at end of file
diff --git a/src/southbridge/amd/cs5536/cs5536.c b/src/southbridge/amd/cs5536/cs5536.c
index 872de36..0c0368f 100644
--- a/src/southbridge/amd/cs5536/cs5536.c
+++ b/src/southbridge/amd/cs5536/cs5536.c
@@ -23,6 +23,7 @@
#include <device/pci.h>
#include <device/pci_ops.h>
#include <device/pci_ids.h>
+#include <device/smbus.h>
#include <console/console.h>
#include <stdint.h>
#include <pc80/isa-dma.h>
@@ -33,6 +34,7 @@
#include <stdlib.h>
#include "chip.h"
#include "cs5536.h"
+#include "smbus.h"
struct msrinit {
u32 msrnum;
@@ -667,6 +669,23 @@ static void southbridge_enable(struct device *dev)
}
+static int lsmbus_read_byte(device_t dev, u8 address)
+{
+ u16 device;
+ struct resource *res;
+ struct bus *pbus;
+
+ device = dev->path.i2c.device;
+ pbus = get_pbus_smbus(dev);
+ res = find_resource(pbus->dev, 0x10);
+
+ return do_smbus_read_byte(res->base, device, address);
+}
+
+static struct smbus_bus_operations lops_smbus_bus = {
+ .read_byte = lsmbus_read_byte,
+};
+
static struct device_operations southbridge_ops = {
.read_resources = cs5536_read_resources,
.set_resources = pci_dev_set_resources,
@@ -674,6 +693,7 @@ static struct device_operations southbridge_ops = {
.init = southbridge_init,
// .enable = southbridge_enable,
.scan_bus = scan_static_bus,
+ .ops_smbus_bus = &lops_smbus_bus,
};
static const struct pci_driver cs5536_pci_driver __pci_driver = {
diff --git a/src/southbridge/amd/cs5536/early_smbus.c b/src/southbridge/amd/cs5536/early_smbus.c
index 814bc5a..c3f6817 100644
--- a/src/southbridge/amd/cs5536/early_smbus.c
+++ b/src/southbridge/amd/cs5536/early_smbus.c
@@ -18,11 +18,7 @@
*/
#include "cs5536.h"
-
-#define SMBUS_ERROR -1
-#define SMBUS_WAIT_UNTIL_READY_TIMEOUT -2
-#define SMBUS_WAIT_UNTIL_DONE_TIMEOUT -3
-#define SMBUS_TIMEOUT (1000)
+#include "smbus.h"
/* initialization for SMBus Controller */
static void cs5536_enable_smbus(void)
@@ -37,176 +33,6 @@ static void cs5536_enable_smbus(void)
}
-static void smbus_delay(void)
-{
- /* inb(0x80); */
-}
-
-static int smbus_wait(unsigned smbus_io_base)
-{
- unsigned long loops = SMBUS_TIMEOUT;
- unsigned char val;
-
- do {
- smbus_delay();
- val = inb(smbus_io_base + SMB_STS);
- if ((val & SMB_STS_SDAST) != 0)
- break;
- if (val & (SMB_STS_BER | SMB_STS_NEGACK)) {
- /*printk(BIOS_DEBUG, "SMBUS WAIT ERROR %x\n", val); */
- return SMBUS_ERROR;
- }
- } while (--loops);
- return loops ? 0 : SMBUS_WAIT_UNTIL_READY_TIMEOUT;
-}
-
-/* generate a smbus start condition */
-static int smbus_start_condition(unsigned smbus_io_base)
-{
- unsigned char val;
-
- /* issue a START condition */
- val = inb(smbus_io_base + SMB_CTRL1);
- outb(val | SMB_CTRL1_START, smbus_io_base + SMB_CTRL1);
-
- /* check for bus conflict */
- val = inb(smbus_io_base + SMB_STS);
- if ((val & SMB_STS_BER) != 0)
- return SMBUS_ERROR;
-
- return smbus_wait(smbus_io_base);
-}
-
-static int smbus_check_stop_condition(unsigned smbus_io_base)
-{
- unsigned char val;
- unsigned long loops;
- loops = SMBUS_TIMEOUT;
- /* check for SDA status */
- do {
- smbus_delay();
- val = inb(smbus_io_base + SMB_CTRL1);
- if ((val & SMB_CTRL1_STOP) == 0) {
- break;
- }
- outb((0x7F << 1) | SMB_CTRL2_ENABLE, smbus_io_base + SMB_CTRL2);
- } while (--loops);
- return loops ? 0 : SMBUS_WAIT_UNTIL_READY_TIMEOUT;
-}
-
-static int smbus_stop_condition(unsigned smbus_io_base)
-{
- outb(SMB_CTRL1_STOP, smbus_io_base + SMB_CTRL1);
- return smbus_wait(smbus_io_base);
-}
-
-static int smbus_ack(unsigned smbus_io_base, int state)
-{
- unsigned char val = inb(smbus_io_base + SMB_CTRL1);
-
-/* if (state) */
- outb(val | SMB_CTRL1_ACK, smbus_io_base + SMB_CTRL1);
-/* else
- outb(val & ~SMB_CTRL1_ACK, smbus_io_base + SMB_CTRL1);
-*/
- return 0;
-}
-
-static int smbus_send_slave_address(unsigned smbus_io_base,
- unsigned char device)
-{
- unsigned char val;
-
- /* send the slave address */
- outb(device, smbus_io_base + SMB_SDA);
-
- /* check for bus conflict and NACK */
- val = inb(smbus_io_base + SMB_STS);
- if (((val & SMB_STS_BER) != 0) || ((val & SMB_STS_NEGACK) != 0)) {
- /* printk(BIOS_DEBUG, "SEND SLAVE ERROR (%x)\n", val); */
- return SMBUS_ERROR;
- }
- return smbus_wait(smbus_io_base);
-}
-
-static int smbus_send_command(unsigned smbus_io_base, unsigned char command)
-{
- unsigned char val;
-
- /* send the command */
- outb(command, smbus_io_base + SMB_SDA);
-
- /* check for bus conflict and NACK */
- val = inb(smbus_io_base + SMB_STS);
- if (((val & SMB_STS_BER) != 0) || ((val & SMB_STS_NEGACK) != 0))
- return SMBUS_ERROR;
-
- return smbus_wait(smbus_io_base);
-}
-
-static unsigned char smbus_get_result(unsigned smbus_io_base)
-{
- return inb(smbus_io_base + SMB_SDA);
-}
-
-static unsigned char do_smbus_read_byte(unsigned smbus_io_base,
- unsigned char device,
- unsigned char address)
-{
- unsigned char error = 0;
-
- if ((smbus_check_stop_condition(smbus_io_base))) {
- error = 1;
- goto err;
- }
-
- if ((smbus_start_condition(smbus_io_base))) {
- error = 2;
- goto err;
- }
-
- if ((smbus_send_slave_address(smbus_io_base, device << 1))) {
- error = 3;
- goto err;
- }
-
- smbus_ack(smbus_io_base, 1);
-
- if ((smbus_send_command(smbus_io_base, address))) {
- error = 4;
- goto err;
- }
-
- if ((smbus_start_condition(smbus_io_base))) {
- error = 5;
- goto err;
- }
-
- if ((smbus_send_slave_address(smbus_io_base, (device << 1) | 0x01))) {
- error = 6;
- goto err;
- }
-
- if ((smbus_stop_condition(smbus_io_base))) {
- error = 7;
- goto err;
- }
-
- return smbus_get_result(smbus_io_base);
-
-err:
- print_debug("SMBUS READ ERROR:");
- print_debug_hex8(error);
- print_debug(" device:");
- print_debug_hex8(device);
- print_debug("\n");
- /* stop, clean up the error, and leave */
- smbus_stop_condition(smbus_io_base);
- outb(inb(smbus_io_base + SMB_STS), smbus_io_base + SMB_STS);
- outb(0x0, smbus_io_base + SMB_STS);
- return 0xFF;
-}
-
static inline int smbus_read_byte(unsigned device, unsigned address)
{
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
diff --git a/src/southbridge/amd/cs5536/smbus.c b/src/southbridge/amd/cs5536/smbus.c
new file mode 100644
index 0000000..3b948c4
--- /dev/null
+++ b/src/southbridge/amd/cs5536/smbus.c
@@ -0,0 +1,199 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <arch/io.h>
+#include "cs5536.h"
+#include "smbus.h"
+
+#define SMBUS_ERROR -1
+#define SMBUS_WAIT_UNTIL_READY_TIMEOUT -2
+#define SMBUS_WAIT_UNTIL_DONE_TIMEOUT -3
+#define SMBUS_TIMEOUT (1000)
+
+static void smbus_delay(void)
+{
+ /* inb(0x80); */
+}
+
+static int smbus_wait(unsigned smbus_io_base)
+{
+ unsigned long loops = SMBUS_TIMEOUT;
+ unsigned char val;
+
+ do {
+ smbus_delay();
+ val = inb(smbus_io_base + SMB_STS);
+ if ((val & SMB_STS_SDAST) != 0)
+ break;
+ if (val & (SMB_STS_BER | SMB_STS_NEGACK)) {
+ /*printk(BIOS_DEBUG, "SMBUS WAIT ERROR %x\n", val); */
+ return SMBUS_ERROR;
+ }
+ } while (--loops);
+ return loops ? 0 : SMBUS_WAIT_UNTIL_READY_TIMEOUT;
+}
+
+/* generate a smbus start condition */
+int smbus_start_condition(unsigned smbus_io_base)
+{
+ unsigned char val;
+
+ /* issue a START condition */
+ val = inb(smbus_io_base + SMB_CTRL1);
+ outb(val | SMB_CTRL1_START, smbus_io_base + SMB_CTRL1);
+
+ /* check for bus conflict */
+ val = inb(smbus_io_base + SMB_STS);
+ if ((val & SMB_STS_BER) != 0)
+ return SMBUS_ERROR;
+
+ return smbus_wait(smbus_io_base);
+}
+
+int smbus_check_stop_condition(unsigned smbus_io_base)
+{
+ unsigned char val;
+ unsigned long loops;
+ loops = SMBUS_TIMEOUT;
+ /* check for SDA status */
+ do {
+ smbus_delay();
+ val = inb(smbus_io_base + SMB_CTRL1);
+ if ((val & SMB_CTRL1_STOP) == 0) {
+ break;
+ }
+ outb((0x7F << 1) | SMB_CTRL2_ENABLE, smbus_io_base + SMB_CTRL2);
+ } while (--loops);
+ return loops ? 0 : SMBUS_WAIT_UNTIL_READY_TIMEOUT;
+}
+
+int smbus_stop_condition(unsigned smbus_io_base)
+{
+ outb(SMB_CTRL1_STOP, smbus_io_base + SMB_CTRL1);
+ return smbus_wait(smbus_io_base);
+}
+
+static int smbus_ack(unsigned smbus_io_base, int state)
+{
+ unsigned char val = inb(smbus_io_base + SMB_CTRL1);
+
+/* if (state) */
+ outb(val | SMB_CTRL1_ACK, smbus_io_base + SMB_CTRL1);
+/* else
+ outb(val & ~SMB_CTRL1_ACK, smbus_io_base + SMB_CTRL1);
+*/
+ return 0;
+}
+
+int smbus_send_slave_address(unsigned smbus_io_base,
+ unsigned char device)
+{
+ unsigned char val;
+
+ /* send the slave address */
+ outb(device, smbus_io_base + SMB_SDA);
+
+ /* check for bus conflict and NACK */
+ val = inb(smbus_io_base + SMB_STS);
+ if (((val & SMB_STS_BER) != 0) || ((val & SMB_STS_NEGACK) != 0)) {
+ /* printk(BIOS_DEBUG, "SEND SLAVE ERROR (%x)\n", val); */
+ return SMBUS_ERROR;
+ }
+ return smbus_wait(smbus_io_base);
+}
+
+int smbus_send_command(unsigned smbus_io_base, unsigned char command)
+{
+ unsigned char val;
+
+ /* send the command */
+ outb(command, smbus_io_base + SMB_SDA);
+
+ /* check for bus conflict and NACK */
+ val = inb(smbus_io_base + SMB_STS);
+ if (((val & SMB_STS_BER) != 0) || ((val & SMB_STS_NEGACK) != 0))
+ return SMBUS_ERROR;
+
+ return smbus_wait(smbus_io_base);
+}
+
+static unsigned char smbus_get_result(unsigned smbus_io_base)
+{
+ return inb(smbus_io_base + SMB_SDA);
+}
+
+unsigned char do_smbus_read_byte(unsigned smbus_io_base,
+ unsigned char device,
+ unsigned char address)
+{
+ unsigned char error = 0;
+
+ if ((smbus_check_stop_condition(smbus_io_base))) {
+ error = 1;
+ goto err;
+ }
+
+ if ((smbus_start_condition(smbus_io_base))) {
+ error = 2;
+ goto err;
+ }
+
+ if ((smbus_send_slave_address(smbus_io_base, device << 1))) {
+ error = 3;
+ goto err;
+ }
+
+ smbus_ack(smbus_io_base, 1);
+
+ if ((smbus_send_command(smbus_io_base, address))) {
+ error = 4;
+ goto err;
+ }
+
+ if ((smbus_start_condition(smbus_io_base))) {
+ error = 5;
+ goto err;
+ }
+
+ if ((smbus_send_slave_address(smbus_io_base, (device << 1) | 0x01))) {
+ error = 6;
+ goto err;
+ }
+
+ if ((smbus_stop_condition(smbus_io_base))) {
+ error = 7;
+ goto err;
+ }
+
+ return smbus_get_result(smbus_io_base);
+
+err:
+ print_debug("SMBUS READ ERROR:");
+ print_debug_hex8(error);
+ print_debug(" device:");
+ print_debug_hex8(device);
+ print_debug("\n");
+ /* stop, clean up the error, and leave */
+ smbus_stop_condition(smbus_io_base);
+ outb(inb(smbus_io_base + SMB_STS), smbus_io_base + SMB_STS);
+ outb(0x0, smbus_io_base + SMB_STS);
+ return 0xFF;
+}
+
diff --git a/src/southbridge/amd/cs5536/smbus.h b/src/southbridge/amd/cs5536/smbus.h
new file mode 100644
index 0000000..8f82d38
--- /dev/null
+++ b/src/southbridge/amd/cs5536/smbus.h
@@ -0,0 +1,34 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _CS5536_SMBUS_H
+#define _CS5536_SMBUS_H
+
+int smbus_start_condition(unsigned smbus_io_base);
+int smbus_stop_condition(unsigned smbus_io_base);
+int smbus_check_stop_condition(unsigned smbus_io_base);
+int smbus_send_slave_address(unsigned smbus_io_base,
+ unsigned char device);
+static int smbus_send_command(unsigned smbus_io_base, unsigned char command);
+
+unsigned char do_smbus_read_byte(unsigned smbus_io_base,
+ unsigned char device,
+ unsigned char address);
+
+#endif /* _CS5536_SMBUS_H */
1
0
Patch set updated for coreboot: 85fd89c buildsystem: Make CPU microcode updating more configurable
by Alexandru Gagniuc 20 Jul '12
by Alexandru Gagniuc 20 Jul '12
20 Jul '12
Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1245
-gerrit
commit 85fd89c0747298d1dc3bdea0ee6f22f215762610
Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
Date: Fri Jul 20 00:11:21 2012 -0500
buildsystem: Make CPU microcode updating more configurable
This commit has two main parts:
1) Move UPDATE_CPU_MICROCODE to src/cpu/Kconfig to make it a more
"global" option, and make it depend on
RESPECT_UPDATE_CPU_MICROCODE_OPTION
Having this option hidded in AMD Fam 10h Kconfig made it virtually
invisible to devs working on other CPUs. Having this as a global
option, should provide an incentive for people to work on
configurable microcode updates.
2) Added option to the build system to include a microcode file in CBFS.
The option will only be visible if the CPU's Kconfig selects
CPU_MICROCODE_FROM_CBFS, basically telling the build system that the
CPU initialization routines are capable of finding and applying
microcode updates from CBFS.
If CPU_MICROCODE_FROM_CBFS is selected, the user is presented with two
options:
- Include microcode in CBFS from an external file
- Don't include any microcode in CBFS
You might also have noticed a commented-out option in Kconfig:
CPU_MICROCODE_CBFS_GENERATE
The idea behind this is to take a C array, compile it, and generate a
microcode file automatically. This means the user won't have to fiddle
with microcode files, which might be next to impossible to obtain.
Since this option requires more intricate modifications to the build
system, it is better to implement it in a future patch.
I am leaving this commented-out option to communicate intent and provide
an incentive to implement it.
Change-Id: I38d0c9851691aa112e93031860e94895857ebb76
Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
---
src/arch/x86/Makefile.inc | 7 ++++
src/cpu/Kconfig | 76 +++++++++++++++++++++++++++++++++++++++
src/cpu/amd/model_10xxx/Kconfig | 33 +----------------
3 files changed, 84 insertions(+), 32 deletions(-)
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index f498831..a215a7b 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -49,6 +49,9 @@ endif
ifeq ($(CONFIG_AP_CODE_IN_CAR),y)
COREBOOT_ROM_DEPENDENCIES+=$(objcbfs)/coreboot_ap.elf
endif
+ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL),y)
+COREBOOT_ROM_DEPENDENCIES+=$(CONFIG_CPU_MICROCODE_FILE)
+endif
extract_nth=$(word $(1), $(subst |, ,$(2)))
@@ -100,6 +103,10 @@ ifeq ($(CONFIG_INCLUDE_CONFIG_FILE),y)
sed -e '/^#/d' -e '/^ *$$/d' $(DOTCONFIG) >> $(obj)/config.tmp ; \
$(CBFSTOOL) $@.tmp add $(obj)/config.tmp config raw; rm -f $(obj)/config.tmp ; fi
endif
+ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL),y)
+ @printf " CPU uCode cpu_microcode\n"
+ $(CBFSTOOL) $@.tmp add $(CONFIG_CPU_MICROCODE_FILE) cpu_microcode microcode
+endif
mv $@.tmp $@
@printf " CBFSPRINT $(subst $(obj)/,,$(@))\n\n"
$(CBFSTOOL) $@ print
diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig
index 85e83d4..849b6f3 100644
--- a/src/cpu/Kconfig
+++ b/src/cpu/Kconfig
@@ -62,3 +62,79 @@ config SSE2
with more efficient code if SSE2 instructions are available.
endif # ARCH_X86
+
+config CPU_MICROCODE_FROM_CBFS
+ bool
+ default n
+
+choice
+ prompt "Include CPU microcode in CBFS"
+ default CPU_MICROCODE_CBFS_NONE
+ depends on EXPERT && CPU_MICROCODE_FROM_CBFS
+
+#config CPU_MICROCODE_CBFS_GENERATE
+# bool "Generate from tree"
+
+config CPU_MICROCODE_CBFS_EXTERNAL
+ depends on CPU_MICROCODE_FROM_CBFS
+ bool "Include external microcode file"
+ help
+ Select this option if you want to include an external file containing
+ the CPU microcode. This will be included as a separate file in CBFS.
+ This option is only available for CPUs where loading microcode from
+ CBFS is implemented.
+
+config CPU_MICROCODE_CBFS_NONE
+ bool "None"
+ help
+ Select this option if you do not want CPU microcode included in CBFS.
+ Note that for some CPUs, the microcode is hard-coded into the source
+ tree and is not loaded from CBFS. In this case, microcode will still
+ be updated.
+
+endchoice
+
+config CPU_MICROCODE_FILE
+ string "Path and filename of CPU microcode"
+ depends on CPU_MICROCODE_CBFS_EXTERNAL
+ default "microcode.bin"
+ help
+ The path and filename of the file containing the CPU microcode.
+
+
+# The following option lets us know that the CPU initialization code will check
+# for UPDATE_CPU_MICROCODE, and will not include any microcode updates in the
+# image if it detects this option.
+# This must only be selected by CPUs whose microcode update has been adjusted
+# to respect UPDATE_CPU_MICROCODE option.
+config RESPECTS_UPDATE_CPU_MICROCODE_OPTION
+ bool
+ default n
+
+config UPDATE_CPU_MICROCODE
+ bool "Update CPU microcode"
+ default y
+ depends on EXPERT && RESPECTS_UPDATE_CPU_MICROCODE_OPTION
+ help
+ Select this to apply patches to the CPU microcode provided by the
+ vendor (without source), and distributed with coreboot, to address
+ issues in the CPU post production.
+
+ Microcode updates distributed with coreboot are not necessarily the
+ latest version available. Updates are only applied if they are newer
+ than the microcode already in the CPU.
+
+ Unselect this to let CPUs run with microcode as shipped from factory.
+ No binary microcode patches will be included in the coreboot image in
+ that case, which can help with creating an image for which complete
+ source code is available, which in turn might simplify license
+ compliance.
+
+ Microcode updates intend to solve issues that have been discovered
+ after CPU production. The common case is that systems work as intended
+ with updated microcode, but we have also seen cases where issues were
+ solved by not applying the microcode updates.
+
+ Note that some operating system include these same microcode patches,
+ so you may need to also disable microcode updates in your operating
+ system in order for this option to matter.
diff --git a/src/cpu/amd/model_10xxx/Kconfig b/src/cpu/amd/model_10xxx/Kconfig
index 221d044..64ac850 100644
--- a/src/cpu/amd/model_10xxx/Kconfig
+++ b/src/cpu/amd/model_10xxx/Kconfig
@@ -3,6 +3,7 @@ config CPU_AMD_MODEL_10XXX
select SSE
select SSE2
select MMCONF_SUPPORT_DEFAULT
+ select RESPECTS_UPDATE_CPU_MICROCODE_OPTION
if CPU_AMD_MODEL_10XXX
config CPU_ADDR_BITS
@@ -51,36 +52,4 @@ config SET_FIDVID_CORE_RANGE
endif # SET_FIDVID
-config UPDATE_CPU_MICROCODE
- bool
- default y
-
-config UPDATE_CPU_MICROCODE
- bool "Update CPU microcode"
- default y
- depends on EXPERT && CPU_AMD_MODEL_10XXX
- help
- Select this to apply patches to the CPU microcode provided by
- AMD without source, and distributed with coreboot, to address
- issues in the CPU post production.
-
- Microcode updates distributed with coreboot are not necessarily
- the latest version available from AMD. Updates are only applied
- if they are newer than the microcode already in your CPU.
-
- Unselect this to let Fam10h CPUs run with microcode as shipped
- from factory. No binary microcode patches will be included in the
- coreboot image in that case, which can help with creating an image
- for which complete source code is available, which in turn might
- simplify license compliance.
-
- Microcode updates intend to solve issues that have been discovered
- after CPU production. The common case is that systems work as
- intended with updated microcode, but we have also seen cases where
- issues were solved by not applying the microcode updates.
-
- Note that some operating system include these same microcode
- patches, so you may need to also disable microcode updates in
- your operating system in order for this option to matter.
-
endif # CPU_AMD_MODEL_10XXX
1
0
New patch to review for coreboot: d490264 buildsystem: Make CPU microcode updating more configurable
by Alexandru Gagniuc 20 Jul '12
by Alexandru Gagniuc 20 Jul '12
20 Jul '12
Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1245
-gerrit
commit d490264bd70cc6e5c8052cd8dc4ca880ed78d67e
Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
Date: Fri Jul 20 00:11:21 2012 -0500
buildsystem: Make CPU microcode updating more configurable
This commit has two main parts:
1) Move UPDATE_CPU_MICROCODE to src/cpu/Kconfig to make it a more
"global" option, and make it depend on
RESPECT_UPDATE_CPU_MICROCODE_OPTION
Having this option hidded in AMD Fam 10h Kconfig made it virtually
invisible to devs working on other CPUs. Having this as a global
option, should provide an incentive for people to work on
configurable microcode updates.
2) Added option to the build system to include a microcode file in CBFS.
The option will only be visible if the CPU's Kconfig selects
CPU_MICROCODE_FROM_CBFS, basically telling the build system that the
CPU initialization routines are capable of finding and applying
microcode updates from CBFS.
If CPU_MICROCODE_FROM_CBFS is selected, the user is presented with two
options:
- Include microcode in CBFS from an external file
- Don't include any microcode in CBFS
You might also have noticed a commented-out option in Kconfig:
CPU_MICROCODE_CBFS_GENERATE
The idea behind this is to take a C array, compile it, and generate a
microcode file automatically. This means the user won't have to fiddle
with microcode files, which might be next to impossible to obtain.
Since this option requires more intricate modifications to the build
system, it is better to implement it in a future patch.
I am leaving this commented-out option to communicate intent and provide
an incentive to implement it.
Change-Id: I38d0c9851691aa112e93031860e94895857ebb76
Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
---
src/arch/x86/Makefile.inc | 7 ++++
src/cpu/Kconfig | 76 +++++++++++++++++++++++++++++++++++++++
src/cpu/amd/model_10xxx/Kconfig | 33 +----------------
3 files changed, 84 insertions(+), 32 deletions(-)
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index f498831..c67ee39 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -49,6 +49,9 @@ endif
ifeq ($(CONFIG_AP_CODE_IN_CAR),y)
COREBOOT_ROM_DEPENDENCIES+=$(objcbfs)/coreboot_ap.elf
endif
+ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL),y)
+COREBOOT_ROM_DEPENDENCIES+=$(CONFIG_CPU_MICROCODE_FILE)
+endif
extract_nth=$(word $(1), $(subst |, ,$(2)))
@@ -100,6 +103,10 @@ ifeq ($(CONFIG_INCLUDE_CONFIG_FILE),y)
sed -e '/^#/d' -e '/^ *$$/d' $(DOTCONFIG) >> $(obj)/config.tmp ; \
$(CBFSTOOL) $@.tmp add $(obj)/config.tmp config raw; rm -f $(obj)/config.tmp ; fi
endif
+ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL),y)
+ @printf " CPU uCode ( compression: $(CBFS_PAYLOAD_COMPRESS_NAME))\n"
+ $(CBFSTOOL) $@.tmp add $(CONFIG_CPU_MICROCODE_FILE) cpu_microcode microcode
+endif
mv $@.tmp $@
@printf " CBFSPRINT $(subst $(obj)/,,$(@))\n\n"
$(CBFSTOOL) $@ print
diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig
index 85e83d4..849b6f3 100644
--- a/src/cpu/Kconfig
+++ b/src/cpu/Kconfig
@@ -62,3 +62,79 @@ config SSE2
with more efficient code if SSE2 instructions are available.
endif # ARCH_X86
+
+config CPU_MICROCODE_FROM_CBFS
+ bool
+ default n
+
+choice
+ prompt "Include CPU microcode in CBFS"
+ default CPU_MICROCODE_CBFS_NONE
+ depends on EXPERT && CPU_MICROCODE_FROM_CBFS
+
+#config CPU_MICROCODE_CBFS_GENERATE
+# bool "Generate from tree"
+
+config CPU_MICROCODE_CBFS_EXTERNAL
+ depends on CPU_MICROCODE_FROM_CBFS
+ bool "Include external microcode file"
+ help
+ Select this option if you want to include an external file containing
+ the CPU microcode. This will be included as a separate file in CBFS.
+ This option is only available for CPUs where loading microcode from
+ CBFS is implemented.
+
+config CPU_MICROCODE_CBFS_NONE
+ bool "None"
+ help
+ Select this option if you do not want CPU microcode included in CBFS.
+ Note that for some CPUs, the microcode is hard-coded into the source
+ tree and is not loaded from CBFS. In this case, microcode will still
+ be updated.
+
+endchoice
+
+config CPU_MICROCODE_FILE
+ string "Path and filename of CPU microcode"
+ depends on CPU_MICROCODE_CBFS_EXTERNAL
+ default "microcode.bin"
+ help
+ The path and filename of the file containing the CPU microcode.
+
+
+# The following option lets us know that the CPU initialization code will check
+# for UPDATE_CPU_MICROCODE, and will not include any microcode updates in the
+# image if it detects this option.
+# This must only be selected by CPUs whose microcode update has been adjusted
+# to respect UPDATE_CPU_MICROCODE option.
+config RESPECTS_UPDATE_CPU_MICROCODE_OPTION
+ bool
+ default n
+
+config UPDATE_CPU_MICROCODE
+ bool "Update CPU microcode"
+ default y
+ depends on EXPERT && RESPECTS_UPDATE_CPU_MICROCODE_OPTION
+ help
+ Select this to apply patches to the CPU microcode provided by the
+ vendor (without source), and distributed with coreboot, to address
+ issues in the CPU post production.
+
+ Microcode updates distributed with coreboot are not necessarily the
+ latest version available. Updates are only applied if they are newer
+ than the microcode already in the CPU.
+
+ Unselect this to let CPUs run with microcode as shipped from factory.
+ No binary microcode patches will be included in the coreboot image in
+ that case, which can help with creating an image for which complete
+ source code is available, which in turn might simplify license
+ compliance.
+
+ Microcode updates intend to solve issues that have been discovered
+ after CPU production. The common case is that systems work as intended
+ with updated microcode, but we have also seen cases where issues were
+ solved by not applying the microcode updates.
+
+ Note that some operating system include these same microcode patches,
+ so you may need to also disable microcode updates in your operating
+ system in order for this option to matter.
diff --git a/src/cpu/amd/model_10xxx/Kconfig b/src/cpu/amd/model_10xxx/Kconfig
index 221d044..64ac850 100644
--- a/src/cpu/amd/model_10xxx/Kconfig
+++ b/src/cpu/amd/model_10xxx/Kconfig
@@ -3,6 +3,7 @@ config CPU_AMD_MODEL_10XXX
select SSE
select SSE2
select MMCONF_SUPPORT_DEFAULT
+ select RESPECTS_UPDATE_CPU_MICROCODE_OPTION
if CPU_AMD_MODEL_10XXX
config CPU_ADDR_BITS
@@ -51,36 +52,4 @@ config SET_FIDVID_CORE_RANGE
endif # SET_FIDVID
-config UPDATE_CPU_MICROCODE
- bool
- default y
-
-config UPDATE_CPU_MICROCODE
- bool "Update CPU microcode"
- default y
- depends on EXPERT && CPU_AMD_MODEL_10XXX
- help
- Select this to apply patches to the CPU microcode provided by
- AMD without source, and distributed with coreboot, to address
- issues in the CPU post production.
-
- Microcode updates distributed with coreboot are not necessarily
- the latest version available from AMD. Updates are only applied
- if they are newer than the microcode already in your CPU.
-
- Unselect this to let Fam10h CPUs run with microcode as shipped
- from factory. No binary microcode patches will be included in the
- coreboot image in that case, which can help with creating an image
- for which complete source code is available, which in turn might
- simplify license compliance.
-
- Microcode updates intend to solve issues that have been discovered
- after CPU production. The common case is that systems work as
- intended with updated microcode, but we have also seen cases where
- issues were solved by not applying the microcode updates.
-
- Note that some operating system include these same microcode
- patches, so you may need to also disable microcode updates in
- your operating system in order for this option to matter.
-
endif # CPU_AMD_MODEL_10XXX
1
0
Patch set updated for coreboot: 6a9fd9d NOTFORMERGE: VX900 early init, Nano CPU init, and EPIA M850 board
by Alexandru Gagniuc 20 Jul '12
by Alexandru Gagniuc 20 Jul '12
20 Jul '12
Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1228
-gerrit
commit 6a9fd9d6bb89ecdf3b49fb057182200a5cd9ee0f
Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
Date: Mon Aug 1 05:16:20 2011 -0500
NOTFORMERGE: VX900 early init, Nano CPU init, and EPIA M850 board
Early initialization for VIA VX900:
SMBUS is functional.
Raminit works with 1 rank, but untested with several ranks.
DRAM calibration when more than one DIMM is present is not fully
implemented. Correct MRS command mapping not implemented for DIMMS
which swap address pins.
The delay calibration strategy is to put some predefined delays for
the MD input delays, and run hardware calibration on the other
three delays (DQS input, DQ/DQS output).
For the future, we could change this strategy to one that uses the
hardware calibration of MD input. Unfortunately, according to my
testing, the MD input delay calibration does not work reliably.
VIA nano CPU init:
Microcode updating works. Attempting to change the voltage or
frequency of the CPU without applying the microcode update will
hang the CPU, so we only do transitions if we can verify the
microcode has been updated.
The microcode is updated directly from CBFS. A few residual pieces of
code remain from the time microcode was loaded from an array.
VX900 + VX800 related changes:
Added LPC driver struct in VX800 code. The LPCs seem to be similar
enough that the VX800 LPC code works on the VX900
VIA EPIA M850 board:
Minimum infrastructure to compile a coreboot image for this board is
added; most PCI devices are switched off in devicetree.cb
========== Other Changes: ==========
UPDATE_CPU_MICROCODE:
Moved UPDATE_CPU_MICROCODE to src/cpu/Kconfig to make it a more
"global" option, and made it depend on
RESPECT_UPDATE_CPU_MICROCODE_OPTION
I will submit this as a separate patch once I figure out how to only
push this part of my branch
Include microcode in CBFS:
Added option to the build system to include a microcode file in CBFS.
The option will only be visible if the CPU's Kconfig selects
CPU_MICROCODE_FROM_CBFS
This option tells the build system that the CPU code is capable of
finding and applying microcode updates from CBFS.
I can turn this into a separate patch if there is enough interest
You might also have noticed a commented-out option in Kconfig:
CPU_MICROCODE_CBFS_GENERATE
The idea behind this is to take a C array, compile it, and generate a
microcode file automatically. This means the user won't have to fiddle
with microcode files, which might be next to impossible to obtain.
Since this option requires more intricate modifications to the build
system, I have put it off for now.
Change-Id: I7624944dbc05fbf3019897a116954d71dfda0031
Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
---
src/arch/x86/Makefile.inc | 7 +
src/arch/x86/include/arch/romcc_io.h | 28 +
src/cpu/Kconfig | 76 ++
src/cpu/amd/model_10xxx/Kconfig | 33 +-
src/cpu/via/Kconfig | 1 +
src/cpu/via/Makefile.inc | 5 +-
src/cpu/via/nano/Kconfig | 42 ++
src/cpu/via/nano/Makefile.inc | 30 +
src/cpu/via/nano/nano_init.c | 168 +++++
src/cpu/via/nano/nano_ucode_010f07d9.h | 963 ++++++++++++++++++++++++++
src/cpu/via/nano/update_ucode.c | 209 ++++++
src/cpu/via/nano/update_ucode.h | 79 +++
src/devices/dram/dram.h | 154 +++++
src/devices/dram/dram_util.c | 297 ++++++++
src/devices/smbus/early_smbus.c | 141 ++++
src/devices/smbus/smbus.h | 99 +++
src/include/device/pci_ids.h | 22 +
src/lib/.cbfs.c.kate-swp | Bin 0 -> 3998 bytes
src/mainboard/asus/Kconfig | 2 +-
src/mainboard/via/Kconfig | 3 +
src/mainboard/via/epia-m850/Kconfig | 47 ++
src/mainboard/via/epia-m850/Makefile.inc | 21 +
src/mainboard/via/epia-m850/chip.h | 21 +
src/mainboard/via/epia-m850/devicetree.cb | 63 ++
src/mainboard/via/epia-m850/mainboard.c | 25 +
src/mainboard/via/epia-m850/romstage.c | 78 +++
src/northbridge/via/Kconfig | 1 +
src/northbridge/via/Makefile.inc | 1 +
src/northbridge/via/vx800/lpc.c | 6 +
src/northbridge/via/vx900/Kconfig | 23 +
src/northbridge/via/vx900/Makefile.inc | 34 +
src/northbridge/via/vx900/chip.h | 23 +
src/northbridge/via/vx900/early_smbus.c | 191 ++++++
src/northbridge/via/vx900/early_vx900.h | 35 +
src/northbridge/via/vx900/forgotten.c | 192 ++++++
src/northbridge/via/vx900/forgotten.h | 78 +++
src/northbridge/via/vx900/northbridge.c | 91 +++
src/northbridge/via/vx900/raminit.h | 77 +++
src/northbridge/via/vx900/raminit_ddr3.c | 1053 +++++++++++++++++++++++++++++
src/northbridge/via/vx900/romstrap.inc | 50 ++
src/northbridge/via/vx900/romstrap.lds | 27 +
src/northbridge/via/vx900/vx900.h | 26 +
42 files changed, 4487 insertions(+), 35 deletions(-)
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index f498831..f9ca1de 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -49,6 +49,9 @@ endif
ifeq ($(CONFIG_AP_CODE_IN_CAR),y)
COREBOOT_ROM_DEPENDENCIES+=$(objcbfs)/coreboot_ap.elf
endif
+ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL),y)
+COREBOOT_ROM_DEPENDENCIES+=$(CONFIG_CPU_MICROCODE_FILE)
+endif
extract_nth=$(word $(1), $(subst |, ,$(2)))
@@ -100,6 +103,10 @@ ifeq ($(CONFIG_INCLUDE_CONFIG_FILE),y)
sed -e '/^#/d' -e '/^ *$$/d' $(DOTCONFIG) >> $(obj)/config.tmp ; \
$(CBFSTOOL) $@.tmp add $(obj)/config.tmp config raw; rm -f $(obj)/config.tmp ; fi
endif
+ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL),y)
+ @printf " CPU uCode ( compression: $(CBFS_PAYLOAD_COMPRESS_NAME))\n"
+ $(CBFSTOOL) $@.tmp add $(CONFIG_CPU_MICROCODE_FILE) cpu_microcode microcode #$(CBFS_PAYLOAD_COMPRESS_FLAG)
+endif
mv $@.tmp $@
@printf " CBFSPRINT $(subst $(obj)/,,$(@))\n\n"
$(CBFSTOOL) $@ print
diff --git a/src/arch/x86/include/arch/romcc_io.h b/src/arch/x86/include/arch/romcc_io.h
index 37fb7ab..8876b28 100644
--- a/src/arch/x86/include/arch/romcc_io.h
+++ b/src/arch/x86/include/arch/romcc_io.h
@@ -244,6 +244,34 @@ static inline __attribute__((always_inline)) void pci_write_config32(device_t de
#endif
}
+static inline __attribute__((always_inline))
+void pci_mod_config8(device_t dev, unsigned int where,
+ uint8_t clr_mask, uint8_t set_mask)
+{
+ uint8_t reg8 = pci_read_config8(dev, where);
+ reg8 &= ~clr_mask;
+ reg8 |= set_mask;
+ pci_write_config8(dev, where, reg8);
+}
+static inline __attribute__((always_inline))
+void pci_mod_config16(device_t dev, unsigned int where,
+ uint16_t clr_mask, uint16_t set_mask)
+{
+ uint16_t reg16 = pci_read_config16(dev, where);
+ reg16 &= ~clr_mask;
+ reg16 |= set_mask;
+ pci_write_config16(dev, where, reg16);
+}
+static inline __attribute__((always_inline))
+void pci_mod_config32(device_t dev, unsigned int where,
+ uint32_t clr_mask, uint32_t set_mask)
+{
+ uint32_t reg32 = pci_read_config32(dev, where);
+ reg32 &= ~clr_mask;
+ reg32 |= set_mask;
+ pci_write_config32(dev, where, reg32);
+}
+
#define PCI_DEV_INVALID (0xffffffffU)
static inline device_t pci_io_locate_device(unsigned pci_id, device_t dev)
{
diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig
index 85e83d4..849b6f3 100644
--- a/src/cpu/Kconfig
+++ b/src/cpu/Kconfig
@@ -62,3 +62,79 @@ config SSE2
with more efficient code if SSE2 instructions are available.
endif # ARCH_X86
+
+config CPU_MICROCODE_FROM_CBFS
+ bool
+ default n
+
+choice
+ prompt "Include CPU microcode in CBFS"
+ default CPU_MICROCODE_CBFS_NONE
+ depends on EXPERT && CPU_MICROCODE_FROM_CBFS
+
+#config CPU_MICROCODE_CBFS_GENERATE
+# bool "Generate from tree"
+
+config CPU_MICROCODE_CBFS_EXTERNAL
+ depends on CPU_MICROCODE_FROM_CBFS
+ bool "Include external microcode file"
+ help
+ Select this option if you want to include an external file containing
+ the CPU microcode. This will be included as a separate file in CBFS.
+ This option is only available for CPUs where loading microcode from
+ CBFS is implemented.
+
+config CPU_MICROCODE_CBFS_NONE
+ bool "None"
+ help
+ Select this option if you do not want CPU microcode included in CBFS.
+ Note that for some CPUs, the microcode is hard-coded into the source
+ tree and is not loaded from CBFS. In this case, microcode will still
+ be updated.
+
+endchoice
+
+config CPU_MICROCODE_FILE
+ string "Path and filename of CPU microcode"
+ depends on CPU_MICROCODE_CBFS_EXTERNAL
+ default "microcode.bin"
+ help
+ The path and filename of the file containing the CPU microcode.
+
+
+# The following option lets us know that the CPU initialization code will check
+# for UPDATE_CPU_MICROCODE, and will not include any microcode updates in the
+# image if it detects this option.
+# This must only be selected by CPUs whose microcode update has been adjusted
+# to respect UPDATE_CPU_MICROCODE option.
+config RESPECTS_UPDATE_CPU_MICROCODE_OPTION
+ bool
+ default n
+
+config UPDATE_CPU_MICROCODE
+ bool "Update CPU microcode"
+ default y
+ depends on EXPERT && RESPECTS_UPDATE_CPU_MICROCODE_OPTION
+ help
+ Select this to apply patches to the CPU microcode provided by the
+ vendor (without source), and distributed with coreboot, to address
+ issues in the CPU post production.
+
+ Microcode updates distributed with coreboot are not necessarily the
+ latest version available. Updates are only applied if they are newer
+ than the microcode already in the CPU.
+
+ Unselect this to let CPUs run with microcode as shipped from factory.
+ No binary microcode patches will be included in the coreboot image in
+ that case, which can help with creating an image for which complete
+ source code is available, which in turn might simplify license
+ compliance.
+
+ Microcode updates intend to solve issues that have been discovered
+ after CPU production. The common case is that systems work as intended
+ with updated microcode, but we have also seen cases where issues were
+ solved by not applying the microcode updates.
+
+ Note that some operating system include these same microcode patches,
+ so you may need to also disable microcode updates in your operating
+ system in order for this option to matter.
diff --git a/src/cpu/amd/model_10xxx/Kconfig b/src/cpu/amd/model_10xxx/Kconfig
index 221d044..64ac850 100644
--- a/src/cpu/amd/model_10xxx/Kconfig
+++ b/src/cpu/amd/model_10xxx/Kconfig
@@ -3,6 +3,7 @@ config CPU_AMD_MODEL_10XXX
select SSE
select SSE2
select MMCONF_SUPPORT_DEFAULT
+ select RESPECTS_UPDATE_CPU_MICROCODE_OPTION
if CPU_AMD_MODEL_10XXX
config CPU_ADDR_BITS
@@ -51,36 +52,4 @@ config SET_FIDVID_CORE_RANGE
endif # SET_FIDVID
-config UPDATE_CPU_MICROCODE
- bool
- default y
-
-config UPDATE_CPU_MICROCODE
- bool "Update CPU microcode"
- default y
- depends on EXPERT && CPU_AMD_MODEL_10XXX
- help
- Select this to apply patches to the CPU microcode provided by
- AMD without source, and distributed with coreboot, to address
- issues in the CPU post production.
-
- Microcode updates distributed with coreboot are not necessarily
- the latest version available from AMD. Updates are only applied
- if they are newer than the microcode already in your CPU.
-
- Unselect this to let Fam10h CPUs run with microcode as shipped
- from factory. No binary microcode patches will be included in the
- coreboot image in that case, which can help with creating an image
- for which complete source code is available, which in turn might
- simplify license compliance.
-
- Microcode updates intend to solve issues that have been discovered
- after CPU production. The common case is that systems work as
- intended with updated microcode, but we have also seen cases where
- issues were solved by not applying the microcode updates.
-
- Note that some operating system include these same microcode
- patches, so you may need to also disable microcode updates in
- your operating system in order for this option to matter.
-
endif # CPU_AMD_MODEL_10XXX
diff --git a/src/cpu/via/Kconfig b/src/cpu/via/Kconfig
index 570d408..5c38c91 100644
--- a/src/cpu/via/Kconfig
+++ b/src/cpu/via/Kconfig
@@ -1,2 +1,3 @@
source src/cpu/via/c3/Kconfig
source src/cpu/via/c7/Kconfig
+source src/cpu/via/nano/Kconfig
diff --git a/src/cpu/via/Makefile.inc b/src/cpu/via/Makefile.inc
index 2616111..bdfef0e 100644
--- a/src/cpu/via/Makefile.inc
+++ b/src/cpu/via/Makefile.inc
@@ -1,3 +1,4 @@
-subdirs-$(CONFIG_CPU_VIA_C7) += c7
-subdirs-$(CONFIG_CPU_VIA_C3) += c3
+subdirs-$(CONFIG_CPU_VIA_C7) += c7
+subdirs-$(CONFIG_CPU_VIA_C3) += c3
+subdirs-$(CONFIG_CPU_VIA_NANO) += nano
diff --git a/src/cpu/via/nano/Kconfig b/src/cpu/via/nano/Kconfig
new file mode 100644
index 0000000..3ebd1c4
--- /dev/null
+++ b/src/cpu/via/nano/Kconfig
@@ -0,0 +1,42 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
+##
+## This program is free software: you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation, either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program. If not, see <http://www.gnu.org/licenses/>.
+##
+
+config CPU_VIA_NANO
+ bool
+
+if CPU_VIA_NANO
+
+config CPU_SPECIFIC_OPTIONS
+ def_bool y
+ select UDELAY_TSC
+ select MMX
+ select SSE2
+ select CACHE_AS_RAM
+ select RESPECTS_UPDATE_CPU_MICROCODE_OPTION
+ select CPU_MICROCODE_FROM_CBFS
+
+config DCACHE_RAM_BASE
+ hex
+ default 0xffef0000
+
+config DCACHE_RAM_SIZE
+ hex
+ default 0x8000
+
+endif # CPU_VIA_C7
diff --git a/src/cpu/via/nano/Makefile.inc b/src/cpu/via/nano/Makefile.inc
new file mode 100644
index 0000000..d167eac
--- /dev/null
+++ b/src/cpu/via/nano/Makefile.inc
@@ -0,0 +1,30 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
+##
+## This program is free software: you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation, either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program. If not, see <http://www.gnu.org/licenses/>.
+##
+
+subdirs-y += ../../x86/tsc
+subdirs-y += ../../x86/mtrr
+subdirs-y += ../../x86/lapic
+subdirs-y += ../../x86/cache
+subdirs-y += ../../x86/smm
+subdirs-y += ../../intel/microcode
+
+driver-y += nano_init.c
+ramstage-$(CONFIG_UPDATE_CPU_MICROCODE) += update_ucode.c
+
+cpu_incs += $(src)/cpu/via/car/cache_as_ram.inc
diff --git a/src/cpu/via/nano/nano_init.c b/src/cpu/via/nano/nano_init.c
new file mode 100644
index 0000000..96ae599
--- /dev/null
+++ b/src/cpu/via/nano/nano_init.c
@@ -0,0 +1,168 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "update_ucode.h"
+#include <console/console.h>
+#include <device/device.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/lapic.h>
+#include <cpu/x86/cache.h>
+#include <delay.h>
+
+#define MODEL_NANO 0x3
+#define MODEL_NANO_3000_B0 0x8
+#define MODEL_NANO_3000_B2 0xa
+
+#define MSR_IA32_PERF_STATUS 0x00000198
+#define MSR_IA32_PERF_CTL 0x00000199
+#define MSR_IA32_MISC_ENABLE 0x000001a0
+
+
+static u16 nano_vid_to_mv(u8 vid)
+{
+ return (15000 - 125 * vid) / 10;
+}
+
+static void nano_power(void)
+{
+ msr_t msr;
+ /* Enable Powersaver */
+ msr = rdmsr(MSR_IA32_MISC_ENABLE);
+ msr.lo |= (1 << 16);
+ wrmsr(MSR_IA32_MISC_ENABLE, msr);
+
+ /* Enable 6 bit or 7-bit VRM support
+ * If we don't do this, then trying to change the VID or FID will hang
+ * the CPU. This MSR is not documented in VIA docs*/
+ msr = rdmsr(0x120e);
+ msr.lo |= ( (1<<7) | (1<<4) );
+ /* FIXME: set bit 5 for 7-bit, or don't set for 6 bit
+ * This will probably require a config option */
+ msr.lo |= (1<<5);
+ wrmsr(0x120e, msr);
+
+ /* Get voltage and frequency info */
+ msr = rdmsr(MSR_IA32_PERF_STATUS);
+ u8 min_fid = (msr.hi >> 24);
+ u8 max_fid = (msr.hi >> 8) & 0xff;
+ u8 min_vid = (msr.hi >> 16) & 0xff;
+ u8 max_vid = (msr.hi >> 0) & 0xff;
+ u8 cur_vid = (msr.lo >> 0) & 0xff;
+ u8 cur_fid = (msr.lo >> 8) & 0xff;
+
+ printk(BIOS_DEBUG, "MSR %.8x:%.8x\n", msr.hi, msr.lo);
+ printk(BIOS_INFO, "FID: %dx (min %dx; max %dx)\n",
+ cur_fid, min_fid, max_fid);
+ printk(BIOS_INFO, "VID: %dx (min %dx; max %dx)\n",
+ cur_vid, min_vid, max_vid);
+
+ printk(BIOS_INFO, "Voltage: %dmV (min %dmV; max %dmV)\n",
+ nano_vid_to_mv(cur_vid),
+ nano_vid_to_mv(min_vid),
+ nano_vid_to_mv(max_vid));
+
+ printk(BIOS_INFO, "CPU multiplier: %dx (min %dx; max %dx)\n",
+ (int)((msr.lo >> 8) & 0xff),
+ (int)((msr.hi >> 24) & 0xff), (int)((msr.hi >> 8) & 0xff));
+
+ /* Set highest frequency and VID*/
+ msr.lo = msr.hi;
+ msr.hi = 0;
+ wrmsr(MSR_IA32_PERF_CTL, msr);
+
+ /* We could wait while CPU is executing the frequency transition, but
+ * the Nano has 2 PLLs, and will instantly switch once the second PLL
+ * is locked and ready.
+ * As a side note, if we didn't update the microcode by this point, the
+ * second PLL will not lock correctly. The clock will still be provided
+ * by the first PLL, and execution will continue normally, ___until___
+ * the CPU switches PLL. Once that happens we will no longer have a
+ * working clock source, and the CPU will hang
+ * Moral of the story: update the microcode, or don't change FID */
+
+ printk(BIOS_DEBUG, "MSR 01a0 hi: 0x%.8x lo: 0x%.8x\n", msr.hi, msr.lo);
+
+ msr = rdmsr(0x120e);
+ printk(BIOS_DEBUG, "MSR 120e hi: 0x%.8x lo: 0x%.8x\n", msr.hi, msr.lo);
+}
+
+static void nano_init(device_t dev)
+{
+ print_debug(" Nano POWER:\n");
+ struct cpuinfo_x86 c;
+
+ get_fms(&c, dev->device);
+
+ switch (c.x86_mask) {
+ case MODEL_NANO:
+ printk(BIOS_INFO, "VIA Nano");
+ break;
+ case MODEL_NANO_3000_B0:
+ printk(BIOS_INFO, "VIA Nano 3000 rev B0");
+ break;
+ case MODEL_NANO_3000_B2:
+ printk(BIOS_INFO, "VIA Nano 3000 rev B2");
+ break;
+ default:
+ printk(BIOS_EMERG, "CPU not recognized: %x\n", c.x86_mask);
+ }
+ printk(BIOS_INFO, "\n");
+
+ /* This will have been defined as an empty function if microcode
+ * updates were disabled in Kconfig, and no ucode binary will have
+ * been included in the ROM */
+ unsigned int n_updates = nano_update_ucode();
+
+ if(n_updates != 0){
+ nano_power();
+ } else {
+ /* Changing the frequency or voltage without first updating the
+ * microcode will hang the CPU, so just don't do it */
+ printk(BIOS_EMERG, "WARNING: CPU Microcode not updated.\n"
+ " Will not change frequency, as this may hang the CPU.\n");
+ }
+
+ /* Turn on cache */
+ x86_enable_cache();
+
+ /* Set up Memory Type Range Registers */
+ x86_setup_mtrrs();
+ x86_mtrr_check();
+
+ /* Enable the local cpu apics */
+ setup_lapic();
+}
+
+static struct device_operations cpu_dev_ops = {
+ .init = nano_init,
+};
+
+static struct cpu_device_id cpu_table[] = {
+ {X86_VENDOR_CENTAUR, 0x06f2}, // VIA NANO 1000/2000 Series
+ {X86_VENDOR_CENTAUR, 0x06f8}, // VIA NANO 3000 rev B0
+ {X86_VENDOR_CENTAUR, 0x06fa}, // VIA NANO 3000 rev B2
+ {0, 0},
+};
+
+static const struct cpu_driver driver __cpu_driver = {
+ .ops = &cpu_dev_ops,
+ .id_table = cpu_table,
+};
\ No newline at end of file
diff --git a/src/cpu/via/nano/nano_ucode_010f07d9.h b/src/cpu/via/nano/nano_ucode_010f07d9.h
new file mode 100644
index 0000000..41bb394
--- /dev/null
+++ b/src/cpu/via/nano/nano_ucode_010f07d9.h
@@ -0,0 +1,963 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#if defined(CONFIG_UPDATE_CPU_MICROCODE) && (CONFIG_UPDATE_CPU_MICROCODE != 0)
+
+static const unsigned int ucode_6f2_0[] __attribute__ ((aligned(32))) =
+{
+ 0x53415252, 0x00000000, 0x010f07d9, 0x000006f2,
+ 0x04bb1af1, 0x00000001, 0xffffffff, 0x00000ca0,
+ 0x00000cd0, 0x46363030, 0x45325032, 0x00000000,
+ 0xcb93e3bb, 0x191b8d4a, 0x1863851e, 0x5073b90e,
+ 0x637e23a3, 0xfb2b5429, 0x04714c6c, 0xc15656b7,
+ 0x1a338d28, 0x1b182ec1, 0x3c52af0a, 0x6d370976,
+ 0x969bc177, 0x64487a31, 0xcc081129, 0x5e1eab09,
+ 0x60510c3c, 0x8a8056df, 0xd63b03a9, 0xa44b1274,
+ 0x0debc269, 0x8b0345ed, 0x4970a2f6, 0x207d49ea,
+ 0x204d200f, 0x382f15c8, 0xa036eb02, 0xb4a7bc00,
+ 0xdb71ba56, 0x94b7c995, 0x9a62daf2, 0x1121f430,
+ 0x3e4a5be0, 0x3c7161fc, 0x871cf176, 0x401b4152,
+ 0x7666d9e6, 0xa7d0a300, 0xba2badc0, 0xb76c09d7,
+ 0x20188e4c, 0x790a4683, 0xc9e67da8, 0x0e06ac83,
+ 0x61a20460, 0xff613e2b, 0x75987149, 0x1f377798,
+ 0x0d2d0a03, 0x80770351, 0xfdd1521a, 0x9e0c3559,
+ 0x615cff3f, 0x4b52bf4f, 0x7f147ef1, 0x8710413d,
+ 0xa1f56c83, 0x82b4e353, 0x41059fd8, 0x0ba3cee2,
+ 0xec086b55, 0x30884385, 0x8de9db16, 0x5b43fe34,
+ 0x181d9769, 0xaf85ba70, 0xc1e0339d, 0x57543307,
+ 0x6a9f4dae, 0xc311f618, 0xb517af2e, 0xf1dee71b,
+ 0x055b82d4, 0x2c87f018, 0x855e566e, 0x62902b91,
+ 0x81add936, 0x369c1e10, 0x580b5188, 0x72884066,
+ 0x60451175, 0x33f8c435, 0xeb7a0000, 0x403bb343,
+ 0xa7af4cee, 0x52dc1a70, 0x0f14769b, 0xc3322154,
+ 0xbe2d133c, 0x18631717, 0x4dd84315, 0x004885c0,
+ 0xeb301a26, 0xff84832c, 0xcba0da4a, 0xa62d6358,
+ 0x63f014e7, 0xfd11a7cd, 0xe4caac35, 0xee8eac91,
+ 0xf46f29e6, 0x98b09104, 0xf3e95a8d, 0x66b0a414,
+ 0xd8fc6cd4, 0x5ffd91e9, 0x59df2432, 0x5a76aba5,
+ 0x39564d85, 0x05743921, 0x0f8c6cc2, 0xc75205b0,
+ 0x69ebf3a1, 0xbd742cf5, 0x75b4904f, 0xb6757441,
+ 0x0019eb84, 0x65186919, 0x5cda5257, 0x9abec161,
+ 0x2703a74d, 0xb8e17040, 0xcee1b384, 0x13e81aed,
+ 0x5f1accea, 0x61593e03, 0x1e3a816e, 0xddd02632,
+ 0x489c55c3, 0x999ee852, 0x6f1fc127, 0xb8a3dda1,
+ 0x88218af7, 0xafd4a7c1, 0x8a9cd570, 0x525b63d8,
+ 0x39ca4752, 0x18cda626, 0xc6871457, 0x53606f5f,
+ 0x57e6bc19, 0xe7fca134, 0x5b554854, 0xa92ca963,
+ 0x9fefd3ff, 0x208c2169, 0x585520fa, 0x1661b36e,
+ 0x47ab65ee, 0xdfebfbf9, 0x9c66a187, 0x17dad804,
+ 0x2c78cadc, 0xd5e76482, 0xc5325e9f, 0x75f4e6a3,
+ 0x5bf89d31, 0xe3b8343b, 0x66ae81c0, 0xb08e79bd,
+ 0x7c14f7d3, 0x77c55a1c, 0xb9564471, 0x7fbf729a,
+ 0x80b59bd8, 0xa11c09fd, 0x07e3ca4c, 0xbab01bcd,
+ 0x3789f6bc, 0x9818d37d, 0xe6d32289, 0x0f6a4bf6,
+ 0xcd25812f, 0xb77d2cdb, 0xfc2d2824, 0xb86998dd,
+ 0x66de552c, 0x063f6eba, 0xd65591a3, 0x59ade6b7,
+ 0x5dfa16eb, 0x8c5b0b17, 0xc5b92112, 0x2f5a48b8,
+ 0x81ad574a, 0x42259f3e, 0x79403f4b, 0x0924fc75,
+ 0x108fe221, 0xa251e85f, 0x4e8c16ec, 0x365c9527,
+ 0x2abbb52f, 0x118c79a7, 0xb05ba6c0, 0x0eb2b3ed,
+ 0x8b011c88, 0x79175adb, 0xcbafe02c, 0x9307c24f,
+ 0xd15209ca, 0x23e569fd, 0x26815346, 0x425bd748,
+ 0x504217c2, 0x64e9d2c0, 0x400ba29a, 0x632e3858,
+ 0x7ab4e2d5, 0x6e868452, 0x85bd8005, 0x189cd3c0,
+ 0xd3cbe3f7, 0x820a90aa, 0x4f68b900, 0x65c53860,
+ 0x9a86de7f, 0x4c836b6b, 0x73841092, 0x78590b4a,
+ 0xcd4afc02, 0x73e79113, 0xafefe0f9, 0x30bec385,
+ 0x1fc9252f, 0x6ee8ce4d, 0x3cfa91bb, 0xf493ad13,
+ 0xf02593e0, 0xa63b96da, 0xa7a9c5cb, 0xdcf34661,
+ 0xdabcc8c9, 0x1f330aa8, 0x288df4de, 0xffc2462a,
+ 0xba825a78, 0x6a12478b, 0xda32e0a9, 0xb832887e,
+ 0x5fe63cc3, 0x26cc1f1b, 0x4c7015be, 0x52b54080,
+ 0xb025f5f1, 0x8f8d5ede, 0xbfd6ce2f, 0x924891c3,
+ 0xbe57187d, 0x46e5774f, 0x60a835a3, 0x55a976d3,
+ 0xe30f0595, 0xca07e54a, 0x8231e320, 0x8f977146,
+ 0x475d7c82, 0x10d413c6, 0xc052b913, 0x4c837bc3,
+ 0xbb18ba72, 0x504e64d8, 0x6981f723, 0xda361a85,
+ 0x93443179, 0x74ee16a6, 0xe69a40a5, 0xc117916c,
+ 0xef2f94ac, 0xa06b1e43, 0xdc6e01f9, 0x738e45d0,
+ 0x6b691cca, 0xd3aee7a7, 0x4fe6ee6c, 0xaf2c3419,
+ 0x936e5354, 0xaa757d6d, 0xd01d94fc, 0x47472d81,
+ 0x59489f6d, 0x05cc8f75, 0xeaf2c914, 0xde038603,
+ 0x421e1d5d, 0x45130e4f, 0x8567c50a, 0x240a6fe6,
+ 0x2d270151, 0xeebc219e, 0x0c144950, 0x7d720b18,
+ 0xe6fcf50f, 0x0cda08b2, 0x9241fad6, 0x93152f2d,
+ 0x168b85b9, 0x6eeaeacd, 0xd260c66e, 0x98722b57,
+ 0xe7fcce71, 0x8cf65088, 0x7c218a64, 0x9e957b44,
+ 0xb2f65850, 0x077e049f, 0x2e53ea65, 0x7bf3cb90,
+ 0xca9a4364, 0xddacedc2, 0x1d14f350, 0x3bde8346,
+ 0xf7e5d1ee, 0x7328349d, 0xd665e46f, 0xeffc771b,
+ 0xb8e40217, 0xaf1ffddb, 0xacef49f0, 0x7a4767e1,
+ 0x29659ac1, 0x8fdfee86, 0x2652e871, 0x32ef6440,
+ 0x23981fef, 0xd6956341, 0x44996531, 0xc6dac529,
+ 0xdb49a5c1, 0xb49e0268, 0x03b9a628, 0x859a9cb5,
+ 0x2324f6de, 0x8e09a640, 0x73111b32, 0x209d2265,
+ 0xf8ce7adf, 0x1fee2336, 0x91be0cc2, 0xa6231b34,
+ 0x2ee23a48, 0x1f9f0f02, 0xcef888d5, 0x54928d45,
+ 0x84a864f8, 0xdffdc2ac, 0xedead650, 0x895781ca,
+ 0x2c1ae5c7, 0x7cd560f0, 0xf346ad96, 0x2a919ca3,
+ 0xe845fb6a, 0x5d571861, 0xa28f98f7, 0x0625128f,
+ 0xb3032eea, 0x5e737938, 0xab4e2758, 0x30da5a1a,
+ 0x0700091c, 0x49e24af7, 0xb8739db8, 0x7071cb8d,
+ 0xe8b664cf, 0x5fd996ac, 0x69949200, 0x7e8e89ed,
+ 0xb534a7bc, 0x79fcab56, 0xf7c922c0, 0x260db9df,
+ 0x044a7415, 0x771bf7c6, 0x43c80438, 0xa68f9d6e,
+ 0x26866efd, 0x069dbef7, 0x5ec95f89, 0x118a6f4e,
+ 0x04f307c8, 0xd2442831, 0xc3a4055d, 0x38dd57bb,
+ 0x5a2bf99e, 0x943c8216, 0x8a8a8d67, 0x06d8933d,
+ 0x36d8c238, 0x52892351, 0x233fca34, 0x8f37f14a,
+ 0x03da33bb, 0x5403344c, 0x89abc6db, 0x0c615ee4,
+ 0x841c70f6, 0x2eb7465a, 0xbe04d7f2, 0x58d30b98,
+ 0x684f579c, 0x04968042, 0xa1288066, 0xa02d7561,
+ 0xef31130a, 0x7af7c497, 0xd06ac0f2, 0xd7d213f3,
+ 0xc7151981, 0x6f62d944, 0xfa29cd6e, 0xcc39d1c6,
+ 0x1ac2747b, 0x3c15dd86, 0x9c0c31eb, 0x81297dc2,
+ 0x1da797fc, 0x7eede51d, 0xb7acaba4, 0x3fe2d1af,
+ 0x72255af0, 0x99649635, 0x993f7868, 0x400d58f5,
+ 0x6d606432, 0xb3a02790, 0xbc8b9346, 0x001c3213,
+ 0xf0521676, 0x8fed58a2, 0x91a13447, 0x2a2e3fe3,
+ 0x3d961ac1, 0xee9f3e1a, 0xdb1e5cc0, 0x91170710,
+ 0x3bb17cd9, 0xa87cc42a, 0x29fb31dd, 0x540fa9c9,
+ 0xe74c97ef, 0x08e2ac05, 0xee5255cb, 0x8ccb8dad,
+ 0x14508794, 0x75702112, 0x05ecb30b, 0x5b68f36f,
+ 0xdd90f0f0, 0x4c60e9fe, 0x1152b8b2, 0x1598fe5e,
+ 0x10f1a26d, 0x95b63950, 0x4360fd96, 0x65c82329,
+ 0x2a4b6080, 0x9ff2d6aa, 0x8ff3c3af, 0x2ebdbdec,
+ 0xc42c46d9, 0x1af653ee, 0x5fbf4d3a, 0xa9936322,
+ 0xdc317ab0, 0x7671bdbd, 0xc971f3aa, 0x07978288,
+ 0x7c47615b, 0x0db52c1b, 0x3d0eda0b, 0xe63c6102,
+ 0xd56ef998, 0xaa755081, 0x0a749833, 0xcf4ec8ed,
+ 0x34a92cff, 0xee1bf9a1, 0xb59b0b64, 0x96354086,
+ 0x9d7d5a3c, 0x8144a9ad, 0x96830ca9, 0x90703b77,
+ 0x44db18c2, 0x0932960c, 0xc89dbf7b, 0x3ca76c1c,
+ 0xe6cc836b, 0x368eede3, 0x55c18caf, 0x00cbafd5,
+ 0xc3078024, 0x7d15441c, 0xd23ad62c, 0xf7661a68,
+ 0x98847057, 0xd6767a16, 0x196501b6, 0x68396b86,
+ 0xef4af71b, 0xa81367c2, 0xa4d13e7d, 0xbb8eebeb,
+ 0x4db5f47a, 0x731be642, 0xc2a15f27, 0x3324a7ea,
+ 0x0db10f7b, 0xaba8fe35, 0x225eb533, 0x9f188e3d,
+ 0xa5da4ad3, 0x3464c397, 0xc7572bc2, 0x43bc38e5,
+ 0x3a79ff7f, 0x3021c8f4, 0x822d257e, 0x295f9ee3,
+ 0xa62aa886, 0xeedfdbd0, 0x10ba9b9b, 0x6304cbca,
+ 0x03bbb766, 0x5fccc253, 0x6434c05e, 0xabd80cac,
+ 0x036ea64a, 0xc7babe5a, 0xde7b2fbe, 0xbcd2d22a,
+ 0x5f8219a6, 0xfc75fedf, 0x4f17ce1c, 0x6e670ca9,
+ 0x625b6ae6, 0xee8e9f95, 0x3b3eaae1, 0x9b3ca894,
+ 0x0b0ba78b, 0xfad8065d, 0xa1006779, 0xad9dc956,
+ 0x9f1d8e3d, 0x92f57a18, 0x9bc9e111, 0xc318ae8f,
+ 0xb6862269, 0x3d06fb0d, 0x861c740b, 0xb95e8053,
+ 0x419e7fd2, 0xc360dc82, 0x26d99c21, 0x4336524b,
+ 0x8a9414e5, 0xef9e020e, 0x57e81247, 0xa32a3cab,
+ 0x568e0a11, 0x4daf23bd, 0x1b5d7277, 0x212b7332,
+ 0xdb34afb5, 0xf3d0c01d, 0x5ca627df, 0xaa39c230,
+ 0x4192aa29, 0xed166fa9, 0x071922a6, 0x61074f39,
+ 0xfa700b5a, 0x4a60ed83, 0x1d1d9850, 0x5fe6c671,
+ 0x17730867, 0x6b2c5bfc, 0x0e0dd897, 0xa5c82db3,
+ 0xffcd57cb, 0x962ec9fb, 0x1ac2bdfc, 0x8b85b190,
+ 0x7a4b5a35, 0xd1224522, 0x900462c7, 0x32805daa,
+ 0xa1a8b29b, 0x4720559b, 0x1d846a68, 0x08edd510,
+ 0x02ca010f, 0xeadce4c4, 0x038cde06, 0xbdbfadac,
+ 0x9144d599, 0x670e6072, 0xc14d3857, 0x61f2de60,
+ 0x003d684f, 0xc1ddece7, 0x66c453b6, 0xaf66d81a,
+ 0xe15a2f94, 0xbb3c1f59, 0xab6f1f7d, 0x3b24d812,
+ 0xd629cd94, 0x09d51c81, 0x45cc0259, 0x8eaa8b98,
+ 0xbd945c62, 0x4e74d9ba, 0x449372d0, 0x59bbc106,
+ 0xaa2e4bda, 0xeb24fd0b, 0xc461db59, 0x89fb5031,
+ 0xd51d68bd, 0xe43f615f, 0x0cda1656, 0xe5d77e7a,
+ 0x8136b5c1, 0x13b0c9fd, 0x424adc1c, 0x62797556,
+ 0x450ac473, 0x7f1a6b9d, 0xf678b474, 0x56bd0f0e,
+ 0xe0d75f60, 0x29fc1192, 0xed79a7de, 0x331ffd62,
+ 0xacdac9e9, 0x59de2860, 0x81765718, 0x288c9049,
+ 0x5aa21365, 0x1d8c1119, 0x1f69f6aa, 0x9d5fecc7,
+ 0xccab7d03, 0x611dd66d, 0x88cff2c3, 0xa32df329,
+ 0xfb79f49c, 0xa5673b94, 0x01ca3e4a, 0x4a3c4a3a,
+ 0x79e381ee, 0xfdccd33a, 0xdfffe03c, 0x71785391,
+ 0xd35dc0a3, 0x90c514d7, 0x7f272154, 0x2fbade0b,
+ 0x7e7a40f7, 0x81225389, 0xbc7959fe, 0xfc11b819,
+ 0xb35a6494, 0xf2536a6f, 0x08797aa8, 0x448cd990,
+ 0x9444e16e, 0x03e145ae, 0xd5df6c1b, 0xbf11e6bf,
+ 0xa4cfa985, 0xa22bfbfe, 0x0a51c5c8, 0xdc037e99,
+ 0x22433d50, 0x734d2ba1, 0x8462dcd9, 0x93c0eaca,
+ 0xef87a4bd, 0x7ddfcd1e, 0x73e7d2c6, 0x55c6a86c,
+ 0xc1d99aae, 0xe88fa687, 0xbeadd303, 0x91af28c0,
+ 0x38e178a0, 0x903911b9, 0x804982e8, 0x4e28b42c,
+ 0x50d16e74, 0x5cf89c55, 0xa5e4a723, 0x69647877,
+ 0xb9e426a6, 0x5f0b5419, 0x4c810a84, 0x99c0bc0b,
+ 0x1c66db66, 0x9d664e5c, 0x97c517f4, 0xcd7bf742,
+ 0x284a6299, 0x29a414f6, 0x266b30bf, 0x341a3c0f,
+ 0x03649f3c, 0x3baaff4f, 0x150626e4, 0xcc705cac,
+ 0x97f93343, 0x5c667935, 0x796e0213, 0x87339a47,
+ 0xb67e7c0b, 0x19d36387, 0xfdebd50f, 0x2ccbb93a,
+ 0x53418f96, 0xb9913750, 0x474e557d, 0x39066bfe,
+ 0xc132ed2f, 0x969eef68, 0xeea46a2b, 0xf38d3ac8,
+ 0x94fa4b4a, 0x0f3d5a39, 0x663681bb, 0x052d913d,
+ 0x0ed760d8, 0x6a86a5e6, 0x3b4f8215, 0x45e1703e,
+ 0x7b6da797, 0x2f417ce8, 0x370805fb, 0x10d71f7d,
+ 0x939e57b1, 0x660658bf, 0xb0578eff, 0x83c92004,
+ 0x82d2e830, 0x6a069ede, 0x37bff328, 0xcfc11964,
+ 0xc1551e3b, 0x43f5f81d, 0x993a4c70, 0xb5368f5c,
+ 0xcdfd6ab1, 0x33fb820b, 0x8982c211, 0x658c9d3d,
+ 0x03d94fea, 0x9d14461e, 0xf6054c0b, 0x23505ea9,
+ 0x767bc220, 0x2ae3ca31, 0xf3994369, 0x60c3f27e,
+ 0x4b9b0489, 0x44cc2326, 0x8c6f6753, 0x92905384,
+ 0x4aa90362, 0x5fb075a6, 0x2e61e8bb, 0x46cd1270,
+ 0xe72c6c9d, 0x83111ee4, 0xccd8f5c5, 0x5103ec2f,
+ 0x6e851815, 0x947f246e, 0xde86ad18, 0x9760a987,
+ 0x059e48e2, 0x58a79e93, 0x6aa5b31a, 0x35aabcd5,
+ 0x71f4d3e7, 0x1ae1f425, 0xecce2950, 0x6253dc95,
+ 0xd91f8ddc, 0x214a4a07, 0xb4d299ad, 0x13ef8d8e,
+ 0xbed7b47f, 0x4a12a7eb, 0xeb0963ab, 0xdf0f3b8f,
+ 0x2aa6845d, 0x80881430, 0xd615c63d, 0x4d244696,
+ 0xf627cc27, 0xe03210af, 0x2bc55248, 0xf16867e9,
+ 0x1e065d75, 0xc2b362cd, 0xd9751d64, 0xc2949adf,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+};
+
+static const unsigned int ucode_6f3_0[] __attribute__ ((aligned(32))) =
+{
+ 0x53415252, 0x00000000, 0x061a07d9, 0x000006f3,
+ 0x08074e5a, 0x00000001, 0xffffffff, 0x00000390,
+ 0x000003c0, 0x46363030, 0x32315033, 0x00000000,
+ 0xb07f7392, 0x535a690e, 0xb60295df, 0xfaff25b9,
+ 0x4f4609e6, 0x9fe6ac72, 0x879663b0, 0xab25c96a,
+ 0x65e5e671, 0x5cd611f8, 0xf39e82bd, 0x931d23de,
+ 0x4504a04c, 0x2ba455fb, 0x2fc1034c, 0xbd47d87e,
+ 0xdeb4d91c, 0x33e88111, 0xf1521b6d, 0xa0f8cb0f,
+ 0x013166c3, 0xa784e786, 0xb564c335, 0x826dca49,
+ 0xda84b5e5, 0x63b0da88, 0xd15fd3b3, 0x501590bf,
+ 0x9efa91a7, 0x5f8b7591, 0x97710227, 0xf162ab61,
+ 0x76ec62b9, 0xa8bbba48, 0x5be51483, 0xb84fdb38,
+ 0x933f9758, 0x8616b6b7, 0xc0b405c4, 0xcdbd4e00,
+ 0x254c6488, 0x907dc541, 0x90edf61d, 0x5beef31e,
+ 0x782de3cf, 0x158500d4, 0x9cee8612, 0xdebe1f64,
+ 0xce9d7aa3, 0x0b968a79, 0x520ae716, 0x3dc74a69,
+ 0xb2393da8, 0x6a9f4ec0, 0x7e609890, 0x07121f6b,
+ 0xb318c3f8, 0x52db78bd, 0x2530e9fe, 0xae1a1b72,
+ 0xef55426d, 0x462b9823, 0x9b5fcc9f, 0x46b525ee,
+ 0x5284a388, 0xc1ce0d78, 0xf9e86226, 0xaad31a00,
+ 0xb183aeb0, 0xa75f6593, 0xffa6705a, 0x1d43b713,
+ 0x644424eb, 0x1f9cc20e, 0xa096550f, 0x3497cebd,
+ 0x1941af1f, 0xcf205da8, 0xb3996a90, 0xa08cd793,
+ 0xe1021d21, 0xaa80086e, 0x30e29788, 0xd35458e5,
+ 0x6d5b50cf, 0xc5aaa0f0, 0xd8dceac7, 0x096d6e2a,
+ 0x10b245dc, 0xba5c77c1, 0x2970e03b, 0x4b742ff2,
+ 0x6a2ffbf5, 0x42d4cdbc, 0xeb2744c1, 0xf49eb6f5,
+ 0x806e288c, 0x608e6ad8, 0x9fa0d47f, 0xb40e1ae4,
+ 0x0e63b495, 0x6b1b1fbd, 0x8f1dcda5, 0xff0f7888,
+ 0xeb425a16, 0x1eee7e0a, 0x69c202bc, 0x04020726,
+ 0xbbc62de3, 0x6ebbd54b, 0x22be95c7, 0xe37298e9,
+ 0x309bd861, 0xb04b8d33, 0x63b1e9dd, 0xa27459a1,
+ 0x1f7f69eb, 0xb4cfda0b, 0x226d81a3, 0xaef54cc2,
+ 0xfdb2af55, 0x8f40bd55, 0x7c75fc1b, 0x1ea27f79,
+ 0x7d4775a3, 0x49b65d08, 0xbd9afb11, 0x9c54c786,
+ 0x01fe71ea, 0x9bfc7e9a, 0xe8dca094, 0x416dd13c,
+ 0xc160dfe5, 0x737538f7, 0x6e4a1a3b, 0x3e6dafc7,
+ 0x6d72e2ce, 0x12e54b8a, 0x7035f549, 0xb072e1d4,
+ 0x3b38588f, 0xe026e230, 0xeb224bf0, 0xe37f21c9,
+ 0x9a36fef9, 0x5d82682d, 0x11e5edc2, 0x3442a202,
+ 0x5072abc3, 0xe544eb7e, 0x578bde22, 0x295f8584,
+ 0x02c23076, 0x35476376, 0x9f135eb8, 0x0613fe0f,
+ 0x5ff04afc, 0xd3e1053f, 0x23b58392, 0xc4a0f77a,
+ 0xb87814d6, 0x3a8c17f4, 0xb5efab44, 0x3fe2c21e,
+ 0xcbe0efb6, 0x12997b25, 0x5b18b44e, 0x6b849d21,
+ 0x580f84e4, 0x99a964d0, 0x3fa892a9, 0xd4b01144,
+ 0x6d54c83b, 0x31659593, 0xd7596e21, 0x642c0e11,
+ 0x7403ea9c, 0x47719512, 0x33a86634, 0x8ae60597,
+ 0xb94e5df6, 0x5cf4e917, 0xe438f361, 0x8f5d4d13,
+ 0x00f3d7b7, 0xb9b15305, 0x8e9e1537, 0x350c32f9,
+ 0x31d5f77f, 0xdb7ae793, 0x70094efd, 0xca83ff65,
+ 0xa7f487dc, 0xb15ddccc, 0x99609635, 0xf06787f3,
+ 0x8bc4b4e1, 0x6ebc77e2, 0xf55f780b, 0x4a3b9c96,
+ 0x91860f8a, 0x75827196, 0xb5948530, 0xc7152cb7,
+ 0xec776fea, 0x55c73d21, 0xc4b036c5, 0x69af8697,
+ 0x1d80bc77, 0x91eea8a8, 0xd1ba9808, 0x5a0a812f,
+ 0xc2a14b33, 0x351a2801, 0xc0b41870, 0x3241a4f9,
+ 0xa09fe4b5, 0x407aae2b, 0x394b6e00, 0x323a0b88,
+ 0xa01681d5, 0xda56a382, 0x216d8f3d, 0x7b8e0b61,
+ 0xfb4aa26e, 0x6e5c4623, 0xdc082e4c, 0xe9ea397c,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+};
+
+static const unsigned int ucode_6f8_0[] __attribute__ ((aligned(32))) =
+{
+ 0x53415252, 0x00000000, 0x061907da, 0x000006f8,
+ 0xd4f1b587, 0x00000001, 0xffffffff, 0x00000220,
+ 0x00000250, 0x46363030, 0x46325438, 0x00000000,
+ 0x3299b452, 0x689711fa, 0xee4c84d4, 0xba1598f3,
+ 0x1b403653, 0x2798a70b, 0x224e13ad, 0xc328665d,
+ 0x19f33bc3, 0x54e1be26, 0xe8128c3f, 0x06f9f27f,
+ 0x6fb344ff, 0x36bd410e, 0x229793f2, 0x4d5bc18d,
+ 0xc4f03970, 0xfc7234d0, 0x1856eb5d, 0xcb3a0ed7,
+ 0x524e9de9, 0x1f6cde76, 0x1affdd49, 0xadd2bab5,
+ 0x9c472670, 0x84553d4e, 0x7c8124e1, 0xaddd4ac0,
+ 0xf3588d7c, 0x4642a4be, 0xb1eaa4e5, 0x9069602a,
+ 0x44118af3, 0x3c4c0dbc, 0xacfafeca, 0xa6c708be,
+ 0x4610f501, 0x91f4aabe, 0x0fa3cddf, 0xc64761a7,
+ 0x22022ece, 0xa4d589bc, 0x237de460, 0x60067a6c,
+ 0xf4cff750, 0xd7f5f8c5, 0x9ce2a52a, 0x5653e820,
+ 0x139344a8, 0xc1203a30, 0x4e7f9226, 0xf562836d,
+ 0x0280a4f9, 0x6f23eb5e, 0x3a0e7684, 0x23281e3e,
+ 0xb3c7c258, 0x216d2392, 0xba5f0c35, 0x4e82b0fc,
+ 0xf4e4b3ab, 0x1cd124b7, 0xe1a3261c, 0x5972c999,
+ 0x9575d310, 0x58c81253, 0xc24d1f17, 0xd224c5f7,
+ 0x1205ac8a, 0x2a0fccee, 0x3017b59b, 0x8caf9c22,
+ 0x9e2a470c, 0x3a217bfb, 0xafc9c401, 0x8f278be9,
+ 0xedcc7fce, 0x293cfb52, 0x2fbcf8f5, 0x2470a1df,
+ 0xc8fa046e, 0x58315fcb, 0xfc7c7834, 0xcab53bdd,
+ 0xf3615edf, 0x65f5df91, 0xb145ec86, 0x246bb495,
+ 0x6a71f1e8, 0xc01d50cf, 0x6768cb06, 0x835912be,
+ 0x884a8f0b, 0xafa8c8c0, 0xfa37d361, 0x8026f64e,
+ 0x8c755c89, 0x4c412800, 0x94f8c215, 0xcee50ecd,
+ 0xe4098f72, 0xe932bccd, 0xf0d2a3b0, 0xe3cbfd25,
+ 0xecc7ce41, 0x501b9db9, 0x160ef756, 0x35e97342,
+ 0xc1de34a6, 0xb9f30ca2, 0x1e5018a7, 0xcc6ed6c3,
+ 0x84698919, 0x8e1337e2, 0x299b3d65, 0x401339a2,
+ 0x437d0911, 0xa0baf2cc, 0xe23713b1, 0x814cde1a,
+ 0x18977d01, 0x22a6a5fd, 0x75eba689, 0x586ecb90,
+ 0x9a5b37e3, 0x3d3da0f1, 0xed63599a, 0x40dba6cc,
+ 0xa8a920a7, 0x9b548faf, 0x7562d2ca, 0xd69ac4e0,
+ 0x59ef1bfc, 0x08787853, 0x82844a28, 0x2cd823e5,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+};
+
+static const unsigned int ucode_6f8_1[] __attribute__ ((aligned(32))) =
+{
+ 0x53415252, 0x00000000, 0x051a07da, 0x000006f8,
+ 0x5d1a2de5, 0x00000001, 0xffffffff, 0x00000c20,
+ 0x00000c50, 0x46363030, 0x64325038, 0x00000000,
+ 0x1239d07e, 0x691e32e0, 0xd205e5c0, 0xdfc570de,
+ 0x278e4479, 0x4bca3390, 0x6e7e9b71, 0xd4a85a32,
+ 0x99af2c5e, 0xb452d0a5, 0x4bec4f39, 0x045a8308,
+ 0x09639159, 0xe5ee7bd3, 0x1f49d8ef, 0x3a72c6ce,
+ 0x9a299074, 0xf7a294c2, 0xf88ad4e9, 0x99a46faf,
+ 0xd106a8e9, 0x1c1c978b, 0x22c43cc1, 0x4af01738,
+ 0x1f0d51e1, 0x43976497, 0xd59b7f7c, 0x77879a05,
+ 0xe8e89fed, 0x93e1b538, 0x9d3855ef, 0x7ea23c17,
+ 0xe550e1f6, 0x17613f73, 0x0783fc18, 0x81980e9d,
+ 0x107dc8df, 0xe620b143, 0x48236b44, 0xabf1efb9,
+ 0x7100c5c7, 0xd2245ace, 0x8c859d0b, 0x563a71b7,
+ 0x697dc982, 0xc34a7399, 0x84fea92f, 0xfe6fae64,
+ 0x5e053930, 0xf3de4ab5, 0xc9924782, 0xa4509166,
+ 0x96780cbb, 0xf9008bb1, 0x4d9f7e1b, 0x0e117f75,
+ 0x01c28c4a, 0xe4321ae6, 0xfb340eab, 0x666247a1,
+ 0xa8a5a4a8, 0xe47a3486, 0x94b71bff, 0xeb6d4841,
+ 0x51b7dbbf, 0xcf6bdc3e, 0xae0c68a0, 0xd28c8e55,
+ 0x170435d7, 0x9ee8dcb5, 0xcd2de33e, 0xd13ac2de,
+ 0xa15478d6, 0x226485e7, 0xff7ab105, 0xa0c4ae78,
+ 0x4a8c6cd6, 0xbe4008ab, 0x1037e1e5, 0x5eeb7789,
+ 0x9811fe9c, 0xde44c9ed, 0xa2ffd6d1, 0xecc9f0da,
+ 0x00a460e2, 0x44767b1a, 0xe854e585, 0xc70d0131,
+ 0x3f519a63, 0x468d4386, 0xbbd9c826, 0xa8de428a,
+ 0x0015b96d, 0x17221e10, 0x514e719e, 0x62398cee,
+ 0xb67bb642, 0x0b552de8, 0xe2b2d2f6, 0x22be5083,
+ 0x5ab773ae, 0x46cf2603, 0x86d62320, 0xa0748945,
+ 0x5493221a, 0xa783c1ba, 0x622660e8, 0xb6dc2449,
+ 0xc1897743, 0xfd20c8b4, 0xe14c135f, 0x4e811706,
+ 0xdfdd2b7d, 0x3c16ffa5, 0xd0905f28, 0xc823bef5,
+ 0xd862aa3b, 0x31365fb9, 0x7bd9c7ab, 0xbcf2d6c4,
+ 0xbfc18909, 0xe26312ca, 0x5a68d937, 0x6d250f9b,
+ 0x0781914d, 0xabe54ba9, 0x85d894e6, 0x8c825963,
+ 0xc6e50f72, 0x538ea5a1, 0x861a4623, 0x2bffc2de,
+ 0xe28ae4a2, 0x397d6007, 0xa861f13d, 0xdba785be,
+ 0xc11c37e5, 0xc41a74d7, 0x0f1485c5, 0x1e477a67,
+ 0x8c3d8f46, 0xf7ed4dc8, 0xe99bc25a, 0x1900b0b0,
+ 0xe5cb1b0e, 0x86d18bbf, 0x06ce255c, 0xa762a311,
+ 0x721137c7, 0x26770edd, 0x41839b2c, 0x4bd33366,
+ 0x53836b63, 0xfdc9ed92, 0x5a5145cd, 0xb389fb44,
+ 0x2314ff6d, 0x3b6f0c95, 0x3b201e62, 0xbc5c0994,
+ 0xc620809b, 0x2d9cfacb, 0xe7ed2028, 0x43ecd1c1,
+ 0x13586475, 0x4a720fd7, 0x402f351d, 0xb9781bf9,
+ 0x730e46b4, 0x6810e052, 0xf1dd1b73, 0x8c93e152,
+ 0xb668f9a8, 0x387ee173, 0x41b84b1a, 0xfccfcd68,
+ 0x6047f011, 0xaec6155a, 0x29e0273b, 0x3c9d935e,
+ 0xcb98f03e, 0x4fb51e6f, 0x3ad9b929, 0x6569a278,
+ 0x09b3f6a5, 0x722e9d27, 0x3d4e7da7, 0x11eb3728,
+ 0x076d703d, 0xdca1cf88, 0x2bfad541, 0xcb82293b,
+ 0x99c39f16, 0x6bcb6cbb, 0x1ed41582, 0xcc9be6f0,
+ 0x11f00eb4, 0x1ba055d1, 0xe9a43853, 0x5c055bbe,
+ 0x1ba8500c, 0x70430fd4, 0x45583d82, 0xfc41ef87,
+ 0x3e513205, 0xfd65386c, 0x8a814402, 0x14117437,
+ 0x8a486978, 0xb49cc14d, 0x9c22a9e9, 0x746c15ae,
+ 0xcab3486f, 0x3989de53, 0xd7e237cb, 0x5feb4d98,
+ 0x5c56cbc2, 0x841b5e44, 0x09c9a118, 0xf1f2d529,
+ 0x4fb098fc, 0x1cb3e1ea, 0x9f25bb78, 0xd56f9469,
+ 0x38b08d7a, 0x19b0e914, 0x86311f65, 0x7069459d,
+ 0x711daf17, 0x09738673, 0x53e9bedb, 0x043032e5,
+ 0x32058bd4, 0x22b1a50f, 0xc66b2642, 0x2a7c553c,
+ 0xe7da476d, 0xdfbcc19a, 0x538b5822, 0x3bca007f,
+ 0x082d45fc, 0x78bfcdcb, 0x98e554c4, 0x9ec8e392,
+ 0xebf5ed7c, 0x3b154db7, 0xacf59ef8, 0x8443d4a5,
+ 0xd90a6e4d, 0x486d9807, 0xfd4bab17, 0x76628450,
+ 0xc73b007e, 0x9397abc5, 0x63f035c8, 0x92c4603b,
+ 0xe5807fd2, 0xd305a2ae, 0x65d2c231, 0xdf35bd23,
+ 0xaae754fe, 0x46b9de20, 0x699fd249, 0xa38ddaf0,
+ 0xb3dbf2df, 0x151c7094, 0x7bf864b9, 0x65aff002,
+ 0x7d8d621b, 0xce073aa8, 0x6086f5b5, 0xfd4d8243,
+ 0x791482c3, 0x0df0d01d, 0x6ad8e4ba, 0x6ad0d3f7,
+ 0x2b77d92b, 0x6d68d02d, 0x4a43d822, 0xfef3b1a1,
+ 0x54e96282, 0xdb7ab5b3, 0x72aac1d9, 0xfb4f83ad,
+ 0x1e51747c, 0x36fea058, 0x1e715a12, 0xf3aa6639,
+ 0xfd1a3a64, 0xf173bee2, 0x6a382ad0, 0x48435821,
+ 0x31b90284, 0x3b9ba0c1, 0xf2329444, 0x323f7d8d,
+ 0x8c72dc74, 0xce9301e1, 0x8cb5cd91, 0x124f7dcd,
+ 0xcac6a0f6, 0xe487f261, 0x88e05297, 0x49074df2,
+ 0x1c4c72ea, 0xbf37e900, 0x09103656, 0x723f13f7,
+ 0x454b06c2, 0xe35eaf5f, 0x8879aaa4, 0x78c5ef10,
+ 0xe5895238, 0x749df405, 0x0ce57fec, 0x6da90247,
+ 0xea013e94, 0x6c907d03, 0x1b2f69b5, 0xb2744c73,
+ 0xad1fa97c, 0xca641bb7, 0x10af012e, 0x0c922243,
+ 0xa35519c2, 0xcc3067e7, 0x1064d47d, 0x087e9aa6,
+ 0x803b5642, 0x9936d3c1, 0x3336db24, 0x2c3ccdec,
+ 0xe5b6be8a, 0xe69dea99, 0x4a6f9632, 0xa9a945ca,
+ 0xe7ba26df, 0xb2dae8a0, 0xde770e47, 0x91138e00,
+ 0x3895be22, 0xd0b5f9b5, 0x834c3f69, 0xf75d5f75,
+ 0x90468761, 0x009f6475, 0x73fe55e6, 0x73a00e1c,
+ 0xddaaa0c5, 0xeb3ab712, 0x15d4c070, 0x1cdafd9f,
+ 0x67831b13, 0xef666e8c, 0xc28c36a6, 0x42e5e1f4,
+ 0xd5eb66b7, 0x388f50b3, 0x048c56ed, 0x2f4f9415,
+ 0x435785a6, 0x9d42dc6f, 0x4273b34e, 0x3c3595e8,
+ 0x15f938b4, 0xe2dd91ca, 0x83336b59, 0x4fd6fb7c,
+ 0xbb696bdf, 0x27ce9bd3, 0xdbb85616, 0xf9d9fb6a,
+ 0xb2f0eff5, 0x9216697f, 0x8f51ff6c, 0x99aa370b,
+ 0x2acda31f, 0xd6a36d34, 0xd8475f8d, 0x00c6db0e,
+ 0xfb5db914, 0xeccd35a5, 0x9de84e78, 0x11c242a3,
+ 0xae3788e1, 0xc3f11ed6, 0xdb7da54d, 0xf9c24298,
+ 0x2d1ddec5, 0x180df86c, 0x32fd5b37, 0x82e762ba,
+ 0x19c464f9, 0x0b746141, 0x7069dd69, 0xd509970c,
+ 0xdd325119, 0xe6195b0d, 0xf56796e7, 0xa0d7b2c9,
+ 0xe392698d, 0x3d72adeb, 0x40e9eff3, 0xdf27aa62,
+ 0xfbe9b1bb, 0x3eaf1333, 0x32d9cba9, 0xa90704aa,
+ 0x2de9b422, 0x50f4c07c, 0xb63b4b7e, 0xa34313ca,
+ 0x981dedfd, 0xeab79e01, 0x8900d971, 0x54ecd36d,
+ 0x09146d31, 0x232c3d8b, 0x724b0f3f, 0x27beaf1b,
+ 0x6380dce1, 0xf345f0c1, 0xa6cd4fb7, 0x5412699f,
+ 0x0ebceac3, 0x92a5d843, 0x6c47d876, 0x34db9582,
+ 0xf0159db3, 0x1e08b349, 0x8858102d, 0x24109519,
+ 0xbcb7cae4, 0x84cf5852, 0x9e052e13, 0xb81c27bf,
+ 0xd2750406, 0x5a35b818, 0xfb2c4908, 0xa4972bf0,
+ 0x89296d16, 0xa7d13b99, 0xd74fa892, 0x1a9de940,
+ 0xf2f439d9, 0x81eae6cd, 0x964f0918, 0x20c1f8bc,
+ 0x415977f4, 0x85a775dd, 0xac52244e, 0x8fcc423c,
+ 0x2d29104d, 0xbc61c01a, 0xf9675ac5, 0x90b773d2,
+ 0x54d53eea, 0x1a9f081c, 0xa052d353, 0x9813df28,
+ 0x3b2f5310, 0x0e771c09, 0xf4fedb01, 0x3e8efd60,
+ 0x278d845d, 0xde7f42ba, 0x2345f3ac, 0xbebef98c,
+ 0xe8adcba5, 0xdcd1e4ad, 0xf83bc609, 0x9a2fa38f,
+ 0x2ac6482f, 0xa20cf438, 0x1a56ccc9, 0x79f1ed26,
+ 0xd16c090c, 0x3c4d43ba, 0x3b2face9, 0x8f2a121a,
+ 0x23bff2f3, 0xc05f634e, 0x7abcaff3, 0x8f640674,
+ 0x91c1718a, 0xafed69e8, 0x5045ac4a, 0x1305672c,
+ 0x50d9e2e3, 0xcc009820, 0xcf623411, 0x383811a7,
+ 0xc1803f0f, 0x20cee852, 0xa5954ac9, 0x930e486f,
+ 0xb6381088, 0x8c5f599b, 0x7c36f62d, 0x603132d6,
+ 0xe79e0289, 0x23e6bbcb, 0xf36d61c5, 0xa188ccb4,
+ 0x8138aea8, 0xa93c9f62, 0x68450a57, 0xedf82eca,
+ 0x7e930a05, 0xc368bf51, 0xb92feb10, 0x17f95ccf,
+ 0x6f15cfea, 0x0c6734c4, 0x7c86850d, 0x01ed6dbd,
+ 0x1db961a7, 0x50d369c2, 0x81fe1af0, 0x598b6b2a,
+ 0x42a3a9cf, 0x6e05e662, 0xf5b6a456, 0x2748aeb0,
+ 0xc4645796, 0x5d9c489b, 0xbd6c830e, 0x1c161f9c,
+ 0x476deedd, 0x269b3eec, 0xc602402d, 0x4b6fc409,
+ 0x9f068add, 0xda7e60b9, 0xd8348fcb, 0x73d2b0d1,
+ 0xa5959497, 0xeef9eca7, 0x4e32cb40, 0xec36b3ec,
+ 0x4f1b132a, 0x662d5a69, 0xa6a019d6, 0x5c463ceb,
+ 0x7d41e303, 0x59014126, 0x00fa882c, 0x4b1364b2,
+ 0xcf0fabda, 0x2b1c9268, 0xb43c1b3f, 0xa684737b,
+ 0x47f06aac, 0xcb04b166, 0x2af950ee, 0x216d324e,
+ 0x9a9fbbbe, 0x33a47d17, 0x76f86457, 0xd93c3cd2,
+ 0x20db26d9, 0xd49946dc, 0x6d95f662, 0x937c535a,
+ 0x096e0a00, 0x62c05258, 0xe21c3f63, 0xbd267ef9,
+ 0xc8c98b92, 0xb3e7880a, 0x528d53d3, 0x1d33fd8a,
+ 0xf94c986f, 0xa8e57165, 0xac413d88, 0x34f19e3b,
+ 0x50a3d8b7, 0x58fb8676, 0x54769514, 0xbde066cb,
+ 0x2f764378, 0xea725550, 0x0a8da2f2, 0xca2eb43e,
+ 0xdb390910, 0x99912ba4, 0x684a13a0, 0xf9dfce0c,
+ 0x892a9f9a, 0xae224458, 0x18711cf0, 0x65c356ec,
+ 0x381439ef, 0xd464bd27, 0x35de3dff, 0xaaa4df24,
+ 0x10d24190, 0x3928a9cc, 0x0c825daa, 0x478c90a3,
+ 0x5e6e78ca, 0x74f376d9, 0xd956af27, 0x063de8ca,
+ 0x2f01ee2a, 0x6bc4cf28, 0x3e34901c, 0xd32a57ee,
+ 0x213685b6, 0x75d5440a, 0x10695179, 0xded4b2b0,
+ 0x7061436d, 0xbf4ea54e, 0xbd2ddcd5, 0xcfcc7995,
+ 0xbc811e36, 0xcf6b17a3, 0x2bb295b6, 0xd3c0e8f2,
+ 0xf8d0f7d6, 0x185a221b, 0x25006d43, 0xffbb6a42,
+ 0x519c1a07, 0xe1e1024e, 0x5061c863, 0x4b0ba1ea,
+ 0x5f86a8cb, 0x9a141d40, 0x65ed1bbb, 0x59aaccdc,
+ 0xc301f198, 0xfc80d362, 0x5a837e5a, 0xe0cfb2e5,
+ 0xc260a4dd, 0x31eff844, 0xfa7a0250, 0xff916b6a,
+ 0x532e7112, 0xec3d9fb3, 0x67eadd71, 0x5d035008,
+ 0x1031f03e, 0x10bc1eb0, 0xa4ffda78, 0x3fc90618,
+ 0x069d00fd, 0x55e1a1a2, 0x0a989734, 0x5e710bde,
+ 0x014971ee, 0x4da810b6, 0x81bc117d, 0x4c1ef7ce,
+ 0x3b1700d3, 0x71384ebd, 0xdd61e7e8, 0x289950f1,
+ 0xd07180c8, 0xb2e515cc, 0x997acc95, 0x5be0c088,
+ 0x1d8158dc, 0xf0a69511, 0xb956f917, 0x9b5d5862,
+ 0x0d6465b6, 0xce06697f, 0xfe1c0e62, 0xa4580f33,
+ 0x2eeb88b5, 0x681dac6a, 0x9cfc3e9b, 0xa6ac8962,
+ 0xf3881c23, 0x20e2f490, 0xc2537859, 0xed893623,
+ 0xf425531f, 0x318333b7, 0x3256ae11, 0xd7a21e7a,
+ 0x878f5dea, 0x863f99d8, 0x6a0aff4b, 0xad9ef05f,
+ 0x2e0b2622, 0x328ee279, 0x9d78deba, 0x098fb6b4,
+ 0xfd55c005, 0x09f38311, 0xaf043a10, 0x5beef91b,
+ 0x49003cd2, 0x9131085f, 0x6fa720d9, 0x478eba08,
+ 0x1ebd8a6c, 0x70a5de24, 0xf3381bd1, 0x0cd7e36e,
+ 0xb8a700a0, 0x2e9c5742, 0x9b09100e, 0x57c7e936,
+ 0xf9505650, 0x3e0aeb75, 0x48bb9648, 0xdafe191a,
+ 0x0dcfc0eb, 0x99959593, 0x23215288, 0xd094cb50,
+ 0xd5e7fbb2, 0xc891856d, 0x9e5939fd, 0xd394ea44,
+ 0xf9657de6, 0xa2a2775b, 0x9926805d, 0xd8ac5f16,
+ 0x5c86f714, 0x00d46245, 0x1303e8ea, 0xc98bb0e2,
+ 0x3417f3ee, 0xe75bfce0, 0xeadd8c71, 0xc17a4930,
+ 0x5f29da29, 0xe807c6d0, 0xbed5247f, 0xbf731759,
+ 0xf9787556, 0x3a476c20, 0xd85972b5, 0x1ec03708,
+ 0xa0690f12, 0x2fc6ed76, 0x014aa07c, 0x3725e608,
+ 0x31adaeb9, 0x2d1a12bf, 0xc97eed8c, 0xe55bb6f0,
+ 0xc6e2c259, 0xa09811a2, 0x8dae432c, 0x969602b5,
+ 0xf389d691, 0x32d9dc61, 0x43758e7b, 0x7c4b2cf6,
+ 0x97945f6c, 0x59c54e8a, 0x6262fbb0, 0x677b4c79,
+ 0x7a1f6899, 0x17298ee9, 0x6b0cd48f, 0xe38037cc,
+ 0x3c210d43, 0xe5239986, 0x15140d7f, 0x6be997b4,
+ 0x34e54608, 0x896736ef, 0x6f719086, 0x1c946889,
+ 0x8c02a0a5, 0x530d2d15, 0x76afe26b, 0xbec240c8,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+};
+
+static const unsigned int ucode_6fa_0[] __attribute__ ((aligned(32))) =
+{
+ 0x53415252, 0x00000000, 0x0a0507da, 0x000006fa,
+ 0xc28eb1c2, 0x00000001, 0xffffffff, 0x00000300,
+ 0x00000330, 0x46363030, 0x37335441, 0x00000000,
+ 0x0d31346a, 0xeb2ca8ec, 0xc65a3981, 0x28ddcdcc,
+ 0xf3a8fae5, 0x19d731f5, 0xdf863966, 0x7635b5f2,
+ 0x36d4f0b2, 0xbe24024e, 0x51f57cda, 0x9241c870,
+ 0x68895578, 0x74f59766, 0x5fbda11c, 0xb818f7d7,
+ 0xf35d31b8, 0xe4e576ee, 0xbe1a8a54, 0xe6c59c9c,
+ 0x54d5b539, 0xdca35f5b, 0x19eba0ec, 0x4fba2f04,
+ 0x0df76dfc, 0x05d5b057, 0x36784885, 0x5b43e337,
+ 0x14285276, 0x4561194e, 0x103a82ae, 0x9c7b625a,
+ 0x9d96b6f3, 0xa4fd5883, 0x20585c48, 0x94c67d0d,
+ 0x9ce050d2, 0xd0b5165e, 0x63a0bd8e, 0xf9cd1ece,
+ 0x1584115a, 0x5a662320, 0x63e96e07, 0x7818aac2,
+ 0x6e71233d, 0x1fd178d4, 0x79f16ec9, 0x82f84202,
+ 0x39d8be98, 0x15723245, 0x48ce0075, 0x801ead46,
+ 0x69e8dd35, 0xe5d94c2a, 0x6abb1b97, 0x20762ad6,
+ 0x5e0df657, 0xf7f9a887, 0x20ffb759, 0xbb52002c,
+ 0xa488ebeb, 0xac4eb608, 0x2dd6fc64, 0x67763775,
+ 0x31961884, 0xcd2edeb2, 0x275aed6f, 0x90d87287,
+ 0x2e0f651a, 0xf14b5cac, 0x6bc86e79, 0xcd5ea86c,
+ 0x322ae237, 0x7ece1ef2, 0x45abb79e, 0x5a1b6a68,
+ 0xe3aa633f, 0x9f471388, 0x73ac0258, 0x32ef97ee,
+ 0xe7a98b7a, 0x3feb205f, 0x5466aca4, 0xbf65921c,
+ 0x977da54a, 0xeb27e06f, 0x44bd2376, 0x78e9dd9b,
+ 0x0c426ef0, 0x6ba253ff, 0x1ea0144d, 0x6099a85b,
+ 0x1f0de3db, 0x15e925f7, 0x1e172b91, 0x8a9d83ab,
+ 0x0948df11, 0xc4338ceb, 0x3d13d77b, 0xc4ba859e,
+ 0x601c45a4, 0x2b7a4cfd, 0xd6f42cb0, 0x03827c56,
+ 0xcbe180ef, 0x8ac33028, 0xdd3a5aea, 0x772c2d5d,
+ 0x44884fa7, 0xb37de9c0, 0x9e7fba9d, 0x761f99f1,
+ 0x118f7fcc, 0x7bd6346d, 0xa5c85359, 0xe09d8dae,
+ 0x6034a867, 0x4af20a35, 0xe213d5b5, 0x83678e65,
+ 0x7fa12f26, 0x881bf834, 0xd7a898f9, 0x2e00d34d,
+ 0xadfd0f9f, 0x64f62e57, 0xeb94a4e6, 0x2741735d,
+ 0xfdd7bf3d, 0x0bb5d428, 0x04c6cf8e, 0x7c91f2e2,
+ 0x862dafe0, 0xe2bc5ef5, 0x1cf8983f, 0x48fb28fb,
+ 0xf3725287, 0xfceacf3c, 0x9c97d1b6, 0x244aa0f2,
+ 0x74cd0c3d, 0x62def4c1, 0x5389a927, 0x9213a193,
+ 0xfbccaf62, 0xe0c52a28, 0x2f960d1e, 0x261fdc3a,
+ 0xa4011e50, 0x8cba98a3, 0xc1ee67fd, 0x8bdc9bd1,
+ 0xd2ba1d9a, 0x2ff19168, 0x2c893f34, 0x465b9763,
+ 0xac4a2241, 0xdabab40a, 0x848d8ed7, 0x32e0c7db,
+ 0xe037749b, 0xa806fe6d, 0xfd392283, 0x54c23f8b,
+ 0xddff2a30, 0xbc3cf4b2, 0xfa60ba33, 0xa9bba869,
+ 0x0ab138e4, 0xd0a75765, 0x83a03739, 0xed1e0b96,
+ 0x7b2a9c07, 0x21d68bd2, 0x1c74b719, 0x63eaac88,
+ 0xea824a44, 0x3f1e946d, 0xaa660153, 0x30d73746,
+ 0x25019ec8, 0x93a60137, 0xebd12222, 0x2a97f7a8,
+ 0xca0d18f0, 0x60a7b913, 0xe208502f, 0xf7f99b2e,
+ 0xa111ffab, 0x17977781, 0xa1d5ac7b, 0xdeb44610,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+};
+
+static const unsigned int ucode_6fa_1[] __attribute__ ((aligned(32))) =
+{
+ 0x53415252, 0x00000000, 0x091807da, 0x000006fa,
+ 0x0bd03d37, 0x00000001, 0xffffffff, 0x00000c10,
+ 0x00000c40, 0x46363030, 0x36335041, 0x00000000,
+ 0xa8502cf0, 0x6b8ae36f, 0xcc201a00, 0xf99bd698,
+ 0xbaa54ce5, 0xd26c6c64, 0x6586a335, 0xdf114ce6,
+ 0x65768732, 0x0c9fff59, 0xf0c87c99, 0x3cb93d44,
+ 0x776f6f6a, 0x4cd46553, 0x3b5548de, 0xba94bd6d,
+ 0xacfdae04, 0x01d0ed9a, 0x2b51dcbb, 0x0e88b2c0,
+ 0x0a87b9bd, 0x7fdafd01, 0x2b2114a4, 0x094f0a66,
+ 0xa19ef4ff, 0xf00fc22f, 0x0a791589, 0x14b0605b,
+ 0x65c880ce, 0x98a25bd3, 0xc46bcf0f, 0x23b28754,
+ 0x9d5b0d0a, 0xc7b95ff1, 0x4b559af5, 0x2c972fb7,
+ 0x24c7393a, 0x50953092, 0xcdfbb400, 0xd8b74e66,
+ 0x167c8540, 0xe5f33cf3, 0x6f06bece, 0x67853c91,
+ 0xec256024, 0x4321a8d7, 0xdf8db159, 0xb3c4ea19,
+ 0x49c55dbb, 0x6cd0893f, 0x24926b88, 0x8b6d8c1e,
+ 0xcbc1ca74, 0x0d97abf7, 0xbd0683e5, 0xfbd070ae,
+ 0x2d86f2ba, 0xdf2d5df1, 0x1c94ac1d, 0xce105cc6,
+ 0x707d966a, 0x425adf11, 0xd5437db4, 0x9439e46c,
+ 0xf491c327, 0xa264301e, 0x74f59c4c, 0x4fd8cd7d,
+ 0x4d2ee13b, 0xeedc9b07, 0xb48c496e, 0x0a9a158b,
+ 0xe2aa1f80, 0xe56e1be4, 0x601147a5, 0x9e8e1a67,
+ 0xe311dea5, 0x0e787f57, 0xe6d48d91, 0xfc5efa36,
+ 0x8d740ced, 0x626aa6ec, 0xfa47f6c6, 0x78236dbc,
+ 0xac414eda, 0xbe9b7c3f, 0x922aa24c, 0xe824c36b,
+ 0x4bf0a6ea, 0x4650f510, 0xe14ea433, 0x8a863587,
+ 0x99f2e00c, 0xace2241e, 0x673a6a21, 0xeacd0611,
+ 0x1d5d9f26, 0x63542bdc, 0x19769443, 0x83fb04f6,
+ 0xd2dba174, 0x41fc8e8e, 0xb753a248, 0xbe7f5d53,
+ 0x97bd16c8, 0xb6e3ea74, 0x10a04714, 0x678ba0fe,
+ 0x41903bb6, 0xdc3f69f5, 0x69c0e20e, 0xa3857a0e,
+ 0xa66aec62, 0x4f1129d4, 0x39bf5e5c, 0x6566814d,
+ 0x6ebc5d8d, 0x74fab02e, 0x6ce9ff42, 0x20dd4b0d,
+ 0x89a915bc, 0xdb86b288, 0xe6a2f5c0, 0xd26fa8d8,
+ 0x8ce2b6ef, 0xb38cb16c, 0x7e187321, 0xe9057cf7,
+ 0xfeff6963, 0xafcbd93d, 0x1ac7600e, 0xf953ad97,
+ 0xdd8daaa5, 0x24ffd3a3, 0x6a87f2e0, 0xa5a876ae,
+ 0xbe7ec94d, 0x630e9bdd, 0x14cf97ff, 0x0ad023f8,
+ 0xafc7d6b6, 0x01d9c914, 0xcaa89ce8, 0xb87471ee,
+ 0xf7a6722f, 0x37e1c449, 0x16efc69c, 0x6b5fd873,
+ 0x0cb4dbf5, 0xd7e3e2fc, 0x1b980086, 0x3fcc2b9b,
+ 0xef724017, 0x6ab5078a, 0x9c469135, 0xda49a6d8,
+ 0x94bd4cd4, 0x5ee98e66, 0x4bb9cd31, 0x96bb17de,
+ 0x3796eef6, 0x0a0cdc6f, 0x5855dd79, 0x21f4df2a,
+ 0x70fcf480, 0x1e408673, 0x2c9a1e7c, 0xd8281ab2,
+ 0xd2251523, 0xc207118f, 0xb520e691, 0xf7be5cd0,
+ 0xae7af3ad, 0xd8bd2853, 0xed06f5e7, 0x70e4318d,
+ 0xd949fff5, 0x84a7dca6, 0x54116bcb, 0xe38fab7c,
+ 0x41f88f1a, 0x148f2a61, 0x6598203c, 0xf3df679c,
+ 0xa47d2d48, 0x6ebd84aa, 0xca409338, 0x5ea735c7,
+ 0x8f5902a3, 0x486b9a72, 0x2a6c9f7a, 0x4f58af16,
+ 0x8e589cbd, 0x847b026e, 0xeb883553, 0x9bd04361,
+ 0xdf75294b, 0x5701b848, 0x8e4c290e, 0x84ae09a2,
+ 0x7c2e5310, 0x1f1e3351, 0x57464eba, 0x2f2bd882,
+ 0x55312151, 0xd699d4a8, 0x86c0cb2a, 0xc18625d5,
+ 0x01e34f5f, 0xdd71a9b5, 0x00d1404c, 0x478a8fdd,
+ 0xaca315cd, 0x08c2bb61, 0xe1e95f74, 0x5c0f2e74,
+ 0xc5b86ecd, 0x5efba52e, 0x27162c32, 0x2cd364e0,
+ 0x7c2ff4dd, 0x20afee39, 0x01f06c32, 0x5705321c,
+ 0x721e9a19, 0x0406919f, 0x793ddfdb, 0x34ad2684,
+ 0xb870a1c0, 0x12723655, 0x8f3a0553, 0x1eb77d55,
+ 0x31777ded, 0x80d06c75, 0x9e0f8431, 0x289bd541,
+ 0x742e6c03, 0xd9d32028, 0xb7891977, 0xaddc8f96,
+ 0x1815c705, 0x7c50fb3f, 0x72e1a6d5, 0x58a49102,
+ 0x94734a5a, 0xf1431853, 0xcb403be0, 0x80ff034c,
+ 0x1cca1d4c, 0xa451b20a, 0xcfff97a1, 0x6897d11a,
+ 0x153fe0f9, 0x6747b5df, 0x3a88bcef, 0x6648176b,
+ 0x7986c1d7, 0x3f2d7a08, 0x8ea0db0e, 0xf0f57877,
+ 0x0ed1edbf, 0x95158803, 0x0425f867, 0x79237bc3,
+ 0x28ce7bcc, 0x60f311a5, 0xc7ba09fb, 0x55596285,
+ 0xc724ebe4, 0xeac78d31, 0x3e6c778e, 0x05252503,
+ 0x3dcdcb51, 0x78c59d5c, 0xa3dee354, 0x52b19d1a,
+ 0xfca398b0, 0x63f65f9d, 0xc9fc4fa4, 0xd35ebec9,
+ 0xa3698241, 0x05d0e962, 0xf7526d10, 0x7777b4e4,
+ 0x72482300, 0x96d42113, 0xce18adb9, 0x0f6fae9b,
+ 0xbd737b23, 0x2f327586, 0x456e2db2, 0xe8bacf5c,
+ 0xa3333916, 0xb1045776, 0xe831b66b, 0x28c002f1,
+ 0x6907e87b, 0xd44c8009, 0xb8bfbd22, 0x5f11a712,
+ 0xb99ed38c, 0xf14ef1bf, 0xa50cffec, 0x3ac7cc61,
+ 0x967864d6, 0x0f4dd3f2, 0x9a52c6e0, 0x4622af4c,
+ 0x8c5fe79d, 0x1f5aaf51, 0xb379d3fc, 0x06f5485c,
+ 0xb46f53fc, 0xfb7b867e, 0x4fd79268, 0xb426ba21,
+ 0x3bd32579, 0xeccf15e1, 0xdbf2585f, 0x38dc054a,
+ 0xf66e29ce, 0x93d218ef, 0x38a61bee, 0x5d764b3b,
+ 0x698c1bee, 0xd1f1dcca, 0xcb4d774f, 0x7ae6113e,
+ 0xbc46ab5d, 0x7cea59f7, 0xef726f3c, 0x86e552c8,
+ 0x54b5c263, 0xbb9f213c, 0xb0ec7aee, 0xae412550,
+ 0x7d672e4c, 0x479482d1, 0xbe984fd4, 0xbb40b4e9,
+ 0xce460f5b, 0xc25d2d8e, 0x14d43871, 0xc622459e,
+ 0xd25cdf24, 0x4cfc08fe, 0x6e66c76d, 0x6163f5e5,
+ 0x590ef352, 0x38dd5eee, 0x5b56b3c0, 0xbf7a708f,
+ 0xd11ce5b9, 0x46fe1639, 0x87e53fae, 0x52b6d358,
+ 0x32d6eb0b, 0x2c8d0693, 0x7b823fba, 0x1743a83d,
+ 0x89ec17f7, 0x74679c91, 0x14768344, 0xf27ab26f,
+ 0xcafbebd7, 0xb996128f, 0xef5940d8, 0xf3d2817c,
+ 0xbfa77515, 0x223a22a1, 0xc301ff17, 0xfb63edb7,
+ 0x4d0b235a, 0x9dbd7318, 0xf165ef57, 0x872805e4,
+ 0x78fbcb1b, 0x8715e546, 0x909b519b, 0x073ebe68,
+ 0x520c18f5, 0x75d543ef, 0xfffd247f, 0xc51faa72,
+ 0xc3ff9c28, 0x05d95767, 0xf8a8ce29, 0x6c3100df,
+ 0x9602b7b5, 0xf1df9514, 0xdfbde49a, 0x63f347c3,
+ 0xa3fedee4, 0x5ab74220, 0x9e3ab0fb, 0x6024aa18,
+ 0x941b54f2, 0xaf740c6b, 0x07278738, 0xdc9f9f70,
+ 0x528d7eb4, 0xb78b4da4, 0x7e0859ca, 0x4d7f2f34,
+ 0x4cce084c, 0x1e1eaa38, 0xe237324d, 0x096f11bc,
+ 0x8b040823, 0x2a1c921a, 0x13df560f, 0x8d6f9621,
+ 0x34ed0c9c, 0x8f52c968, 0x8c079396, 0x5c2d78c5,
+ 0xba61f0ba, 0x0d6737a7, 0xc7ac90b5, 0x40711497,
+ 0xc610777e, 0x1baf3ab6, 0x2a509778, 0xb64267ae,
+ 0xf0292472, 0x316c99d9, 0x2773d52f, 0x31de412b,
+ 0x7d7c33d9, 0x5418cbd7, 0x779a60f5, 0x2b6635a1,
+ 0x4a7480ad, 0xa91700ed, 0xdd719d72, 0xf4ef7bfa,
+ 0xf292f4a7, 0xe20a154c, 0x6980673e, 0xd087d272,
+ 0x3f62947c, 0xcf82e629, 0x998f72d1, 0x181537ec,
+ 0xec99111e, 0x9ff94a7e, 0x5838ed56, 0x652e00ad,
+ 0x63d2e127, 0x291b39ed, 0xe8874f1f, 0x9fcea857,
+ 0x4b44e4d7, 0x79facf6b, 0xfa97248d, 0xabf1b436,
+ 0x44bf8ca3, 0xa2342483, 0x27b39aae, 0x54ad61e8,
+ 0x62aaf9c8, 0xcf1f0e5f, 0x57727cb9, 0x2bbe1a27,
+ 0xad813e18, 0xade7e54a, 0x6d9ae354, 0x7dda6e41,
+ 0x6b503615, 0xe539a489, 0xacd4cf0c, 0x50b5ee9b,
+ 0xe12cd634, 0xdaa2358a, 0xf3ed5c3c, 0xd7bf1749,
+ 0xc8953072, 0x8e5cebe6, 0xa89070ea, 0xb8978ab1,
+ 0x9bb10556, 0x14552e00, 0x5e3254e6, 0x3749eeca,
+ 0xdafe140d, 0xe7ed3e04, 0x5bed7ee9, 0xf9f2b6d0,
+ 0x78958f75, 0xe5e5677a, 0x6bd77819, 0x802ca29a,
+ 0x90bbda35, 0x1ed94bcc, 0x04d5fd91, 0xb23898df,
+ 0xef508485, 0xc2db56db, 0x335a3555, 0xafd667b7,
+ 0x2e41b466, 0xd17eb896, 0x98ba5a85, 0x7205a0cd,
+ 0xa89f5fe5, 0xbc8082bf, 0x0ea9336d, 0xd5f7695f,
+ 0x3df7ae79, 0x0c16a95b, 0x872eca3f, 0x6565c3c6,
+ 0xa7c70d84, 0x5a9cfc9d, 0xf9d365e1, 0x83b41c41,
+ 0xa361972f, 0xcedd50d9, 0x0dd0ffaf, 0x33beb660,
+ 0x6e5f8aae, 0x39d89272, 0x59a2dd37, 0x46b32dd6,
+ 0x23d1b438, 0xaed8f126, 0xf56c2494, 0x1be3e72a,
+ 0x49559bde, 0x651f3b68, 0xa77ee774, 0xf6ee86d2,
+ 0xd6958a8b, 0x12ba080f, 0xce76bd3b, 0xafad53b0,
+ 0xe5fb067a, 0x4f4b6149, 0x54215017, 0xad0378e2,
+ 0x482d9f3f, 0xfb953d72, 0xd078f21d, 0x8b91bcd0,
+ 0xd5eff898, 0x2d47c13a, 0xfc918304, 0x6569bbdd,
+ 0xdfccdc07, 0x3f6c1171, 0x0aa3e691, 0x22b945c6,
+ 0x123c08b9, 0x3c61ad47, 0xf3684a46, 0x6ddf05df,
+ 0x45587657, 0x65d93c69, 0x3028c52a, 0x0f0bc6f9,
+ 0x9686fdc6, 0x50c758fe, 0x4fb30ed1, 0xfbc1e704,
+ 0xfdb31f63, 0x593a7512, 0x316393b2, 0xc9f4832b,
+ 0x4f1a5a37, 0xb1b47d4d, 0x5fcc8ccd, 0xe8069867,
+ 0x0e3709c9, 0x09e4cb6d, 0x7a5db9a9, 0x64a714d4,
+ 0xbec5c79a, 0x16bea0a5, 0x81666c3d, 0x35f96dea,
+ 0x9b6405f0, 0x3ad8a387, 0x8672e95e, 0xf6b43b37,
+ 0x8c2a03e8, 0x454073e1, 0x2dcec42d, 0xf78c7e73,
+ 0x082676e2, 0x0350e3fb, 0xd8221bde, 0x825a4d19,
+ 0xb9fa4b07, 0xb107ffac, 0x2a4b6eea, 0x3e642e4b,
+ 0xa7585a91, 0x84610e89, 0x63238347, 0xbbc51fd3,
+ 0xfe022393, 0x5ca78d29, 0x817b9406, 0x4e56ceb6,
+ 0x41675640, 0x2e7ce351, 0x97409f25, 0xf723c6ec,
+ 0x0392c2de, 0xd6a28f3a, 0x78de0130, 0xae0a3790,
+ 0xee61980d, 0x7f1bb7b8, 0x1e09abde, 0x978c8936,
+ 0x3f389b96, 0xec790b39, 0xf822a35b, 0x8a1d3592,
+ 0xdebdb41d, 0x133b9d1a, 0x5883447b, 0xbcf8bb09,
+ 0x8fe79675, 0xaa8f1d7b, 0xd017c7b7, 0xcd06e94f,
+ 0x8755fc1a, 0xffaa89fa, 0x29be8e81, 0x6fcf52a5,
+ 0x55725694, 0x02573e0b, 0x233e87cc, 0x4ef6c107,
+ 0x6f903aec, 0xe71d60d1, 0xa043f83c, 0xe5899344,
+ 0x40d5ea27, 0xde3a6bd4, 0x22cffa9b, 0xb70a3a9d,
+ 0xee1e1fc1, 0x9f304bcf, 0x9a00125e, 0x4fdce973,
+ 0x81cfc376, 0xba14685c, 0x1307212d, 0x9d3cb67c,
+ 0xcf5174a2, 0xce2df038, 0x3d98a9bb, 0x1e4e0289,
+ 0x70370e7a, 0xab7f5a12, 0xd9a73509, 0x84073ecd,
+ 0x1640aed1, 0xb129a7e9, 0xfd8d50b7, 0xaa97ef05,
+ 0xa398d289, 0x3d0445b0, 0x2a063516, 0x0ac49d0e,
+ 0x273b8e5e, 0xad1c3b0a, 0x59c61b56, 0xdf16f4b2,
+ 0x55710d7c, 0x4f8a9a78, 0xe9a3e9cc, 0x96c33642,
+ 0xc1711c0b, 0x453e85a7, 0x36cb0791, 0xd052b65f,
+ 0xd9745f46, 0x720f96c6, 0x112e753a, 0x8e487589,
+ 0x040c3d65, 0x1c642c49, 0x59cebaef, 0x3c44c71d,
+ 0x416fe930, 0xa2092f52, 0x8b89f343, 0xf44f9656,
+ 0x2fe20f9e, 0xbc5acf24, 0x43238ee6, 0x247a5997,
+ 0x2f0e3771, 0xc03e76d9, 0xdef328ee, 0xed802543,
+ 0x2a32c194, 0x4cd92940, 0x3d9eccbc, 0x9fb7ac0e,
+ 0x23e4acff, 0x0f6ef7cd, 0xdfb588d0, 0x2aa0b794,
+ 0x7a5d022a, 0x4356c9b3, 0x97281179, 0x41337e53,
+ 0x76790819, 0xb9a5ca77, 0xaf1a9b2a, 0x1a655dfb,
+ 0x6b106bc8, 0xee6fcab5, 0xe16c7aac, 0x45cb5be6,
+ 0x280d9a95, 0xf2ddc81b, 0x9e1f01e0, 0x1148cf1d,
+ 0xf483fc39, 0x3a66021c, 0x1057a22c, 0xa0685244,
+ 0x1e8a55bc, 0x0390fe02, 0x76c29392, 0x53c53e08,
+ 0xa733d7a2, 0xcb877f82, 0x4fd82ea5, 0x53cb96f3,
+ 0x4547075d, 0x41c477e8, 0xb0912c69, 0x57ed6e48,
+ 0x3e743d6c, 0x882451c7, 0xc868cedd, 0xb3fae605,
+ 0xd81848cb, 0xf3b16ab0, 0x5f3c7494, 0x4fca84d3,
+ 0x621cafcb, 0xa7225d72, 0x83596120, 0xc8f57258,
+ 0x5b443741, 0x0858ebb9, 0xa7392619, 0x26c71263,
+ 0xdfac85c7, 0x95929d75, 0x2a082fe4, 0xb91c4054,
+ 0x2b1a13b2, 0x717e3a2c, 0xfe2165ed, 0x1c5b1653,
+ 0x9ab498cd, 0x3b3d437a, 0xe9c737d3, 0xfd071595,
+ 0x638c4625, 0x997ec96b, 0xa4b0d070, 0xe459568c,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+};
+
+static const unsigned int ucode_6fa_2[] __attribute__ ((aligned(32))) =
+{
+ 0x53415252, 0x00000000, 0x091807da, 0x000006fa,
+ 0xd43a9824, 0x00000001, 0xffffffff, 0x00000940,
+ 0x00000970, 0x46363030, 0x36335041, 0x00000000,
+ 0x302b7fb9, 0x51c322f3, 0x1481e6b5, 0x9950f1a5,
+ 0x27048310, 0xb3895c51, 0x5a93c4a9, 0xeb6c4601,
+ 0x95b0f2ff, 0x99ff6dc9, 0x83843695, 0xb687e255,
+ 0xa3efa9f1, 0x23d98810, 0x846ac2d3, 0x1c9d6010,
+ 0x6715bfdc, 0xa789fab9, 0xe56a1d09, 0x0eeb0427,
+ 0x9ed0a3a7, 0x45ec7559, 0x0c2eb033, 0x17f146dc,
+ 0x30c35795, 0x37a56765, 0x66b11205, 0x5471a208,
+ 0x5a0049b8, 0xc008aca5, 0x29ee84fb, 0x66e3303d,
+ 0x101656d6, 0x2e7de920, 0x673cabfd, 0xf05d1c06,
+ 0x64c507f6, 0xd823cbe0, 0x7e7f4183, 0x04cad122,
+ 0x747e3ba9, 0x3226c602, 0x7dc01760, 0xce634320,
+ 0x84f55355, 0x1c411f23, 0x6972e335, 0x06f74042,
+ 0xa8006f71, 0xfeed7d7e, 0x3f09abbf, 0x6a1a8c7f,
+ 0x0d1b730c, 0x5c73a586, 0x9d73ed26, 0xe43c786a,
+ 0x1da597e3, 0x34c8f323, 0x447d5fb3, 0x9976957d,
+ 0x2c5df47b, 0xf19a1bc3, 0xe53b3cbe, 0xf0a8e170,
+ 0x11f0f112, 0x60e00900, 0xc4014477, 0xcbbda9cf,
+ 0x478c7d43, 0x0c76da66, 0x54f59535, 0x3a310af5,
+ 0x81a2e87b, 0xae577790, 0xc610b904, 0xaa7afec7,
+ 0x0ba491df, 0xc44ac7ea, 0x055551b0, 0x967834ff,
+ 0x46075ceb, 0x3f0d8a90, 0x6336f1f4, 0x638e85be,
+ 0xdbc8df61, 0x0112c46c, 0x94aa12ed, 0xe1814406,
+ 0xcb48defa, 0x4c5543ca, 0x756f2306, 0xd7a66dd7,
+ 0x48262543, 0xece84d6d, 0x6addde77, 0x8e5045a5,
+ 0x94761706, 0x2a8f98ff, 0x14898b09, 0xc5111544,
+ 0x60c93fc7, 0x6bea5ad2, 0x81282ca0, 0xe34f2730,
+ 0x9013ce09, 0xebe061d9, 0x975eb536, 0xadcd9034,
+ 0x257fc5a9, 0xffc3bd52, 0x1eadf9ba, 0x0bd81a5c,
+ 0xea0c52f9, 0x8347a620, 0x78663976, 0xccaa6aec,
+ 0x2bd641d4, 0xc3dcc4dc, 0x55e5296d, 0x9e94bfe1,
+ 0x746c3a01, 0x99f0dcea, 0xf52657aa, 0x3622ceb3,
+ 0xa95f8c65, 0x8eaaee04, 0xd71aea04, 0xfcfd6e78,
+ 0x7984686c, 0xe40a8dbf, 0xf50ee2e9, 0x93eb96c1,
+ 0xe834ee5b, 0x5d05b60b, 0x20c10cea, 0x0a8c2645,
+ 0x155a6187, 0xde1aedae, 0x7204cf15, 0xe85373e4,
+ 0xe9f93d4a, 0xc7531d3a, 0x5c535875, 0x46ec1ae6,
+ 0x6aeea9bd, 0x871bb354, 0x1ab2be63, 0xf8dad26c,
+ 0x7b04e772, 0x48564a81, 0x742d28ba, 0x6e698de4,
+ 0xa0779db3, 0x1ce0c3d7, 0x237cb6b0, 0xf286fe37,
+ 0x781af9aa, 0xf4d61b0b, 0xe26b7572, 0x51f38cb3,
+ 0x604873cb, 0x693a158f, 0xb2a0b427, 0xa6cf762b,
+ 0xe91831d4, 0x0376bf4b, 0x0ea5b667, 0x830b103e,
+ 0x25a8dd84, 0x21e82db9, 0x6d4c0e5e, 0xfb767d16,
+ 0x4b883e4b, 0x3de33b14, 0xc9490454, 0x33d61eb4,
+ 0xd0197448, 0x940e34a4, 0x8c48a3b1, 0x3456c76f,
+ 0x92535ef7, 0x95328e66, 0x8882cce2, 0xce2b761b,
+ 0x729cf0e7, 0xa892dd65, 0x804de33d, 0x1549715e,
+ 0x8c819f7a, 0x982d9d26, 0x05314c31, 0x2ea19906,
+ 0xf48db2da, 0xd1b20b93, 0x2bbaea99, 0x4289b538,
+ 0x1352afb3, 0x15aa3a0a, 0x3b80f3f5, 0xc1a1719c,
+ 0x132c9711, 0x46fd6ca8, 0x771b91c5, 0x09414702,
+ 0x9a9fb8d6, 0xff2bc606, 0xb6214f8a, 0x74dacacf,
+ 0x513c4dd5, 0x137fa66c, 0x503d5d37, 0xe024c0da,
+ 0x793e186f, 0x31c2bf95, 0x320c616a, 0x83719c1d,
+ 0xde0d6e00, 0x9409b2a0, 0xe213fae2, 0x21731821,
+ 0x83f51eb3, 0x3cb2eab5, 0xd9c401d3, 0x8d5379ac,
+ 0x624189bb, 0x5233e883, 0x1f3d0c02, 0x3b46edc3,
+ 0xb47d4661, 0xff867384, 0xf4daa252, 0xfc55fa25,
+ 0xb465352e, 0xe1ff2a20, 0x438427df, 0x8cd561f1,
+ 0x8c2debb1, 0xf89d5e68, 0x74015f75, 0xa5ea69fa,
+ 0x0197a406, 0xbc60439a, 0x32244a3c, 0x4c0b5007,
+ 0x61d1138d, 0x024a59f1, 0x305fe9cc, 0x724833dc,
+ 0xcbae0bea, 0x8de58519, 0x62968adc, 0xadd0011c,
+ 0xc5b23595, 0x5b3990c9, 0xd3c64ecc, 0xb5d33759,
+ 0x054c797b, 0xc172220c, 0xda29fe07, 0x7f450ebf,
+ 0xec12a33e, 0x86d9bbb3, 0x78bffba7, 0x6a183c16,
+ 0x3cdb717b, 0x601e0c7f, 0xcf945c26, 0x073e7331,
+ 0xdebd7ad0, 0x62879d5c, 0xe0273347, 0xa2ff18e4,
+ 0x78a14f44, 0x20728f07, 0x25cfa3d5, 0xd699e2a7,
+ 0xc729bf4e, 0x9250bd92, 0xbabf3a88, 0xf69d91ac,
+ 0x0de005b2, 0xee6c6551, 0xf3ec51af, 0x0d4ab84f,
+ 0x85b7f548, 0xa0dcf7ae, 0x55efb6a5, 0xbcc9fdb5,
+ 0xe789546e, 0x8a209948, 0xb49fc3dd, 0x945fd8f7,
+ 0x9c2ab04e, 0x17625832, 0x18253aab, 0x26e3b5fe,
+ 0xd03ebf0d, 0xe5f8b8e4, 0xcdf3ef2f, 0x4024ca62,
+ 0xd3436616, 0xd19b1010, 0x7e53746c, 0xbaea2597,
+ 0xdd72726c, 0xb5a6a4c4, 0x348efd94, 0xba4d3a94,
+ 0x3d736b7c, 0xd32fd9e8, 0x98624886, 0xeaab1e7d,
+ 0xeec8edc6, 0x51dacdff, 0xf7359960, 0x221caa31,
+ 0x34fb3350, 0x794d034c, 0x6aef3d76, 0xc925c505,
+ 0xf752c1ad, 0x04b61fde, 0x7b42ef68, 0x1a119091,
+ 0xe21077a2, 0xc0c21dfb, 0x480cee09, 0x70144e31,
+ 0x49d345b9, 0xb3fe6f47, 0x11d12867, 0xe99898c6,
+ 0x6e54b4fd, 0x5f8d169c, 0x93e707b9, 0x1a90974c,
+ 0xd6a685e4, 0x6c20c321, 0x29f12f73, 0x12e54190,
+ 0x04de2470, 0x6dbb24bb, 0x7f0fd71c, 0xd5e2c954,
+ 0x7d93c73a, 0xd2a2c48d, 0x61e2db8d, 0x1a192d47,
+ 0xc2d8d438, 0x5e779066, 0xc4bcc619, 0x06f872ef,
+ 0xf3401439, 0x573ebd1b, 0x61896e22, 0xde431aef,
+ 0xbad386d8, 0xf54ca23b, 0x57d8016f, 0xd98e33ac,
+ 0xc5f29f61, 0x85217cb1, 0x250a23ef, 0x16c2d7ce,
+ 0x8b8b0207, 0xaeaf1661, 0x8c645ab3, 0x10692f9a,
+ 0x84845cb2, 0x3809ed87, 0x958b72cf, 0xfdc465f9,
+ 0x167924f4, 0x79b72fd3, 0xd53e01b8, 0x878c0bc7,
+ 0x444d821d, 0xb2329171, 0x68dae31b, 0x6dd25eb0,
+ 0x876262cc, 0x600fcaf3, 0xa26397e5, 0xab3b5cd5,
+ 0x11f6df26, 0x3b503f54, 0xfd28517b, 0xac2c6723,
+ 0xf189feec, 0x6c0eabe7, 0xc3b57dd3, 0x9383ffbc,
+ 0xaff39d18, 0x4dae936e, 0x8806e540, 0xd956dfe9,
+ 0x7726c523, 0xe20d141f, 0x75249f0c, 0x641c7ecf,
+ 0x4d75cad2, 0x5e2097c6, 0xffdba551, 0xf97adab1,
+ 0x8d86a099, 0x4ce7dafa, 0xc4bf244c, 0xbd5ab78b,
+ 0x9060c834, 0x4f0533da, 0xeee0c724, 0x39963d31,
+ 0xcde4a77c, 0xf2222170, 0x00675c98, 0x72b6807a,
+ 0xfceec299, 0xb4bfd75f, 0x82385beb, 0x8a4fa5e6,
+ 0x1f4d790b, 0x8cb998f6, 0x5e41077c, 0xbdb77edc,
+ 0x5b885781, 0xdcd539a0, 0x50f70de2, 0xf72c206e,
+ 0xd47a8c39, 0xc8c84742, 0x4f5e1cde, 0x8ec26342,
+ 0x45add698, 0xc0bd2b6d, 0x10096f65, 0xc7e30310,
+ 0x1c951782, 0x37b5edea, 0xe10aea7f, 0xf40d763c,
+ 0x01a93a40, 0x197d0a4b, 0x3d41eed5, 0xe9beb9d6,
+ 0x1d9247a4, 0xeafe224c, 0x2f2578d5, 0x45eb10a4,
+ 0xb6b22e2b, 0xef55f252, 0xb4e224e4, 0x067dcb26,
+ 0xb6d0b2a3, 0xfd8a0221, 0x049bbf33, 0x70752994,
+ 0xf75fd79b, 0x34fcb9d9, 0x90ca2832, 0xf1c767ca,
+ 0x387d06cd, 0x9d5bfdfc, 0x45fb1391, 0xffbf1a8f,
+ 0xa7713b73, 0x04b45260, 0x41f7aadf, 0x4e9ab87d,
+ 0x26cfd8fc, 0x4ae2842a, 0x00b21491, 0x8e41fff9,
+ 0x931d987b, 0x1780ad94, 0x74d9d450, 0x6b4e7b86,
+ 0xd290203b, 0x2677caa9, 0x962f8e81, 0x2ed26089,
+ 0x14e26f42, 0xeb70b144, 0xa095d8c1, 0x6b572c29,
+ 0x78fbacf2, 0x5cdc5cfb, 0xfae86706, 0xddda5706,
+ 0xaa767744, 0x7493a4a2, 0x0e9f6b3f, 0x9806a4df,
+ 0x10e4c5d5, 0x9b49682a, 0xcb1d045c, 0x0b93aa0f,
+ 0x9204696b, 0x82d18f87, 0x1551957c, 0x5410f2ed,
+ 0xb937ab2e, 0xaaf40b54, 0x2b9d4857, 0x50231070,
+ 0x49ee3994, 0xceaa9dbb, 0x9bd8c899, 0xe9605a77,
+ 0xfd88758b, 0x6464201d, 0xa0605f2c, 0xc54d1473,
+ 0x30f678bd, 0xe07ade92, 0x315e83b4, 0x9f0e9866,
+ 0x6861b81f, 0xe3dbc8c2, 0xd67d8c2d, 0x27ffa228,
+ 0x25727f2b, 0xc6637d9b, 0x455637b4, 0x5aabdb00,
+ 0xb74a792c, 0x5bc1a7a8, 0xcbb106d8, 0xd7088b31,
+ 0xefec63ed, 0x5fcb7619, 0x79b5006e, 0x46de8644,
+ 0xdc61db98, 0x7701dca1, 0x1a9622f6, 0x6d192615,
+ 0xc380d47a, 0x10685fa3, 0x1f7fc304, 0x06d3796a,
+ 0x345013f3, 0x4c2db462, 0xddab6807, 0xf2525b65,
+ 0x086d312b, 0x62df52a6, 0x0903ce35, 0xf526c030,
+ 0x58ad7ac0, 0xf188c61f, 0x09869aa0, 0x76ae266b,
+ 0xe352afc2, 0xa5f2f582, 0x5ec4d829, 0x78fbae90,
+ 0xfb64e6ea, 0x96f43d96, 0x735098d0, 0x45006937,
+ 0xb8c64d9d, 0xdc1eacc8, 0x48674e13, 0x809f1e57,
+ 0x3481a112, 0xe97aa223, 0xd9609801, 0x120265b2,
+ 0x12211b6f, 0x7a930f99, 0x10d1fa9b, 0x69413983,
+ 0x72c88496, 0xf6bd37de, 0x397c05bf, 0x69cf3d17,
+ 0x2472b3e5, 0x6534bde0, 0x175c0e03, 0xfd31a289,
+ 0xe4d5d467, 0x933c0637, 0x14547ff0, 0x63dddc17,
+ 0x734f0426, 0x1b7d4414, 0x1d61e181, 0xa9bb645b,
+ 0xe33daddd, 0x0f3fd487, 0xb36f4aef, 0x042e3609,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+};
+
+
+const u32* microcode_updates[] =
+{
+ ucode_6f2_0,
+ ucode_6f3_0,
+ ucode_6f8_0, ucode_6f8_1,
+ ucode_6fa_0, ucode_6fa_1, ucode_6fa_2,
+ 0x00000000
+};
+#endif
diff --git a/src/cpu/via/nano/update_ucode.c b/src/cpu/via/nano/update_ucode.c
new file mode 100644
index 0000000..6cb64b1
--- /dev/null
+++ b/src/cpu/via/nano/update_ucode.c
@@ -0,0 +1,209 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "update_ucode.h"
+#include "nano_ucode_010f07d9.h"
+#include <cpu/x86/msr.h>
+#include <console/console.h>
+#include <stddef.h>
+#include <cpu/cpu.h>
+#include <arch/cpu.h>
+#include <cbfs.h>
+#include <stdlib.h>
+
+static ucode_update_status nano_apply_ucode(const nano_ucode_header *ucode)
+{
+ printk(BIOS_INFO, "Attempting to apply microcode update\n");
+
+ msr_t msr;
+
+ /* FIXME: We are not sure this is needed, but we are doing it anyway */
+ //msr.hi = msr.lo = 0;
+ //wrmsr(MSR_IA32_BIOS_SIGN_ID, msr);
+
+ /* Address of ucode block goes in msr.lo for 32-bit mode
+ * Now remember, we need to pass the address of the actual microcode,
+ * not the header. The header is just there to help us.
+ */
+ msr.lo = (unsigned int)(&(ucode->ucode_start));
+ msr.hi = 0;
+ wrmsr(MSR_IA32_BIOS_UPDT_TRIG, msr);
+
+ /* Let's see if we updated succesfully */
+ msr = rdmsr(MSR_UCODE_UPDATE_STATUS);
+
+ return msr.lo & 0x07;
+}
+
+static void nano_print_ucode_info(const nano_ucode_header *ucode)
+{
+ printk(BIOS_SPEW, "Microcode update information:\n");
+ printk(BIOS_SPEW, "Name: %8s\n",
+ ucode->name
+ );
+ printk(BIOS_SPEW, "Date: %u/%u/%u\n", ucode->month,
+ ucode->day, ucode->year );
+}
+
+static ucode_validity nano_ucode_is_valid(const nano_ucode_header *ucode)
+{
+ /* We must have a valid signature */
+ if(ucode->signature != NANO_UCODE_SIGNATURE)
+ return NANO_UCODE_SIGNATURE_ERROR;
+ /* The size of the head must be exactly 12 double words */
+ if(( ucode->total_size - ucode->payload_size) != NANO_UCODE_HEADER_SIZE)
+ return NANO_UCODE_WRONG_SIZE;
+
+ /* How about a checksum ? Checksum must be 0
+ * Two's complement done over the entire file, including the header */
+ int i;
+ u32 check = 0;
+ u32 *raw = (void*) ucode;
+ for(i = 0 ; i < ((ucode->total_size) >> 2); i++) {
+ check += raw[i];
+ }
+ if(check != 0)
+ return NANO_UCODE_CHECKSUM_FAIL;
+ /* Made it here huh?
+ * If there's anything else wrong, the CPU will reject the update */
+ return NANO_UCODE_VALID;
+}
+#if 0
+static void nano_print_ucode_invalid_reason(ucode_validity why)
+{
+ switch(why) {
+ case NANO_UCODE_VALID:
+ break; /* No error */
+ case NANO_UCODE_SIGNATURE_ERROR:
+ printk(BIOS_SPEW, "Microcode signature is invalid.\n");
+ break;
+ case NANO_UCODE_WRONG_SIZE:
+ printk(BIOS_SPEW, "Microcode header has wrong size.\n");
+ break;
+ case NANO_UCODE_CHECKSUM_FAIL:
+ printk(BIOS_SPEW, "Microcode checksum verification failed.\n");
+ break;
+ default:
+ /* We should _never get this */
+ printk(BIOS_SPEW, "Microcode check failed with unknown code."
+ "Please report this issue.\n" );
+ }
+}
+#endif
+static void nano_print_ucode_status(ucode_update_status stat)
+{
+ switch(stat)
+ {
+ case UCODE_UPDATE_SUCCESS:
+ printk(BIOS_INFO, "Microcode update succesful.\n");
+ break;
+ case UCODE_UPDATE_FAIL:
+ printk(BIOS_ALERT, "Microcode update failed, bad environment."
+ "Update was not applied.\n");
+ break;
+ case UCODE_UPDATE_WRONG_CPU:
+ printk(BIOS_ALERT, "Update not applicable to this CPU.\n");
+ break;
+ case UCODE_INVALID_UPDATE_BLOCK:
+ printk(BIOS_ALERT, "Microcode block invalid."
+ "Update was not applied.\n");
+ break;
+ default:
+ printk(BIOS_ALERT, "Unknown status. No update applied.\n");
+ }
+}
+
+unsigned int nano_update_ucode(void)
+{
+ size_t i;
+ unsigned int n_updates = 0;
+ const struct cbfs_file *cbfs_ucode;
+ u32 fms = cpuid_eax(0x1);
+
+ cbfs_ucode = cbfs_find("cpu_microcode");
+ /* Oops, did you forget to include the microcode ? */
+ if(cbfs_ucode == NULL) {
+ printk(BIOS_ALERT, "WARNING: No microcode file found in CBFS. "
+ "Aborting microcode updates\n");
+ return 0;
+ }
+
+ /* Considering we are running with eXecute-In-Place (XIP), there's no
+ * need to worry that accessing data from ROM will slow us down
+ * Microcode data should be aligned to a 4-byte boundary, but CBFS
+ * already does that for us (Do you, CBFS?) */
+ const u32* ucode_data = CBFS_SUBHEADER(cbfs_ucode);
+ const u32 ucode_len = ntohl(cbfs_ucode->len);
+
+ /* We might do a lot of loops searching for the microcode updates, but
+ * keep in mind, nano_ucode_is_valid searches for the signature before
+ * doing anything else */
+ for( i = 0; i < (ucode_len >> 2); /* don't increment i here */)
+ {
+ ucode_update_status stat;
+ const nano_ucode_header * ucode = (void *)(&ucode_data[i]);
+ if(nano_ucode_is_valid(ucode) != NANO_UCODE_VALID) {
+ i++;
+ continue;
+ }
+ /* Since we have a valid microcode, there's no need to serach
+ * in this region, so we restart our search at the end of this
+ * microcode */
+ i+= (ucode->total_size >> 2);
+ /* Is the microcode compatible with our CPU? */
+ if(ucode->applicable_fms != fms) continue;
+ /* For our most curious users */
+ nano_print_ucode_info(ucode);
+ /* The meat of the pie */
+ stat = nano_apply_ucode(ucode);
+ /* The user might want to know how the update went */
+ nano_print_ucode_status(stat);
+ if(stat == UCODE_UPDATE_SUCCESS) n_updates++;
+ }
+
+#if 0
+ /* FIXME: This loop will most likely go away, but I will save it for a
+ * while. It won't be in the final patch, I promise. */
+ //const nano_ucode_header * head;
+ /* Nano CPUs are able to combine multiple concurrent microcode updates,
+ * Thus, we may have more than one update to apply */
+ size_t i;
+ for(i = 0; microcode_updates[i] != 0; i++)
+ {
+ ucode_update_status stat;
+ const u32* current = microcode_updates[i];
+ head = (void *)current;
+ /* Check if update matches our CPU */
+ if(head->applicable_fms != fms) continue;
+ /* HA!!!! Update found, but is it valid */
+ ucode_validity is_valid = nano_ucode_is_valid(current);
+ if(is_valid != NANO_UCODE_VALID) {
+ nano_print_ucode_invalid_reason(is_valid);
+ continue;
+ }
+ nano_print_ucode_info(current);
+ stat = nano_apply_ucode(current);
+ /* The user might want to know how the update went */
+ nano_print_ucode_status(stat);
+ if(stat == UCODE_UPDATE_SUCCESS) n_updates++;
+ }
+#endif
+ return n_updates;
+
+}
\ No newline at end of file
diff --git a/src/cpu/via/nano/update_ucode.h b/src/cpu/via/nano/update_ucode.h
new file mode 100644
index 0000000..b9c6a00
--- /dev/null
+++ b/src/cpu/via/nano/update_ucode.h
@@ -0,0 +1,79 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __UPDATE_UCODE_C
+#define __UPDATE_UCODE_C
+
+#include <console/console.h>
+#include <cpu/cpu.h>
+
+#define MSR_IA32_BIOS_UPDT_TRIG 0x00000079
+#define MSR_IA32_BIOS_SIGN_ID 0x0000008b
+#define MSR_UCODE_UPDATE_STATUS 0x00001205
+
+#define NANO_UCODE_SIGNATURE 0x53415252
+#define NANO_UCODE_HEADER_SIZE 0x30
+
+/* We care what these values are exactly, so we define them to be sure */
+typedef enum ucode_update_status_enum {
+ UCODE_UPDATE_NOT_ATTEMPTED = 0x0,
+ UCODE_UPDATE_SUCCESS = 0x1,
+ UCODE_UPDATE_FAIL = 0x2,
+ UCODE_UPDATE_WRONG_CPU = 0x3,
+ UCODE_INVALID_UPDATE_BLOCK = 0x4,
+} ucode_update_status;
+
+
+typedef enum ucode_validity_enum {
+ NANO_UCODE_VALID = 0, /* We only care that valid == 0 */
+ NANO_UCODE_SIGNATURE_ERROR,
+ NANO_UCODE_WRONG_SIZE,
+ NANO_UCODE_CHECKSUM_FAIL,
+} ucode_validity;
+
+typedef struct nano_ucode_header_st {
+ u32 signature; /* NANO_UCODE_SIGNATURE */
+ u32 update_revision; /* Revision of the update header */
+ u16 year; /* Year of patch release */
+ u8 day; /* Day of patch release */
+ u8 month; /* Month of patch release */
+ u32 applicable_fms; /* Fam/model/stepping to which ucode applies */
+ u32 checksum; /* Two's complement checksum of ucode+header */
+ u32 loader_revision; /* Revision of hardware ucode update loader*/
+ u32 rfu_1; /* Reservod for future use */
+ u32 payload_size; /* Size of the ucode payload only */
+ u32 total_size; /* Size of the ucode, including header */
+ char name[8]; /* ASCII string of ucode filename */
+ u32 rfu_2; /* Reservod for future use */
+ /* First double-word of the ucode payload
+ * Its address represents the beginning of the ucode update we need to
+ * send to the CPU */
+ u32 ucode_start;
+
+}nano_ucode_header;
+
+#if defined(CONFIG_UPDATE_CPU_MICROCODE) && CONFIG_UPDATE_CPU_MICROCODE != 0
+unsigned int nano_update_ucode(void);
+#else
+static unsigned int nano_update_ucode(void)
+{
+ printk(BIOS_INFO, "CPU Microcode updating disabled.\n");
+ return 0;
+}
+#endif
+#endif /* __UPDATE_UCODE_C */
\ No newline at end of file
diff --git a/src/devices/dram/dram.h b/src/devices/dram/dram.h
new file mode 100644
index 0000000..d79cc52
--- /dev/null
+++ b/src/devices/dram/dram.h
@@ -0,0 +1,154 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef DRAM_H
+#define DRAM_H
+
+#include <stdint.h>
+
+/* DRAM type, byte 2 of spd */
+#define DRAM_TYPE_UNDEFINED 0x00
+#define DRAM_TYPE_FPM_DRAM 0x01
+#define DRAM_TYPE_EDO 0x02
+#define DRAM_TYPE_PIPELINED_NIBBLE 0x03
+#define DRAM_TYPE_SDRAM 0x04
+#define DRAM_TYPE_ROM 0x05
+#define DRAM_TYPE_DDR_SGRAM 0x06
+#define DRAM_TYPE_DDR 0x07
+#define DRAM_TYPE_DDR2 0x08
+#define DRAM_TYPE_DDR2_FBDIMM 0x09
+#define DRAM_TYPE_DDR2_FB_PROBE 0x0a
+#define DRAM_TYPE_DDR3 0x0b
+
+/* Module type (byte 3, bits 3:0) of SPD */
+#define DIMM_TYPE_UNDEFINED 0
+#define DIMM_TYPE_RDIMM 1
+#define DIMM_TYPE_UDIMM 2
+#define DIMM_TYPE_SO_DIMM 3
+#define DIMM_TYPE_MICRO_DIMM 4
+#define DIMM_TYPE_MINI_RDIMM 5
+#define DIMM_TYPE_MINI_UDIMM 6
+#define DIMM_TYPE_MINI_CDIMM 7
+#define DIMM_TYPE_72B_SO_UDIMM 8
+#define DIMM_TYPE_72B_SO_RDIMM 9
+#define DIMM_TYPE_72B_SO_CDIMM 10
+
+#if defined(CONFIG_DEBUG_RAM_SETUP) && (CONFIG_DEBUG_RAM_SETUP)
+#define printram(x, ...) printk(BIOS_DEBUG, x, ##__VA_ARGS__)
+#else
+#define printram(x, ...)
+#endif
+
+/* Different values for tCK, representing standard DDR3 frequencies
+ * As always, these values are in 1/256 ns units */
+#define TCK_1066MHZ 240
+#define TCK_800MHZ 320
+#define TCK_666MHZ 384
+#define TCK_533MHZ 480
+#define TCK_400MHZ 640
+#define TCK_333MHZ 768
+#define TCK_266MHZ 960
+#define TCK_200MHZ 1280
+
+#define RAM_UNIT (1<<24)
+
+#include <stdint.h>
+
+/**
+ *\brief DIMM characteristics
+ *
+ * The characteristics of each DIMM, as presented by the SPD
+ */
+typedef struct dimm_attr_st {
+ u8 dram_type;
+ u16 cas_supported;
+ /* Number of ranks */
+ u8 ranks;
+ /* Number or row address bits */
+ u8 row_bits;
+ /* Number or column address bits */
+ u8 col_bits;
+ /* Size of module in (1 << 24) bytes (16MB) */
+ u16 size;
+ /* Latencies are in units of ns, scaled by x256 */
+ u32 tCK;
+ u32 tAA;
+ u32 tWR;
+ u32 tRCD;
+ u32 tRRD;
+ u32 tRP;
+ u32 tRAS;
+ u32 tRC;
+ u32 tRFC;
+ u32 tWTR;
+ u32 tRTP;
+ u32 tFAW;
+
+} dimm_attr;
+
+typedef struct ramctr_timing_st {
+ u8 dram_type;
+ u16 cas_supported;
+ /* tLatencies are in units of ns, scaled by x256 */
+ u32 tCK;
+ u32 tAA;
+ u32 tWR;
+ u32 tRCD;
+ u32 tRRD;
+ u32 tRP;
+ u32 tRAS;
+ u32 tRC;
+ u32 tRFC;
+ u32 tWTR;
+ u32 tRTP;
+ u32 tFAW;
+ /* Latencies in terms of clock cycles
+ * They are saved separately as they are needed for DRAM MRS commands*/
+ u8 CAS; /* CAS read latency */
+ u8 CWL; /* CAS write latency */
+ u8 WR; /* write recovery time */
+
+} ramctr_timing;
+
+
+typedef u8 spd_raw_data[256];
+
+/**
+ * \brief Decode the raw spd data
+ */
+void spd_decode_ddr3(dimm_attr *dimm, spd_raw_data spd_data);
+
+/**
+ * \brief Checks if the DIMM is Registered based on byte[3] of the spd
+ */
+int dimm_is_registered(u8 spd_byte3);
+
+/**
+ * \brief Print the info in dimm
+ */
+void dram_print_spd_ddr3(const dimm_attr *dimm);
+
+/**
+ * \brief Read double word from specified address
+ *
+ * Should be useful when doing an MRS to the DIMM
+ */
+u32 volatile_read(u32 addr);
+
+#endif /* DRAM_H */
diff --git a/src/devices/dram/dram_util.c b/src/devices/dram/dram_util.c
new file mode 100644
index 0000000..75913e4
--- /dev/null
+++ b/src/devices/dram/dram_util.c
@@ -0,0 +1,297 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "dram.h"
+#include <console/console.h>
+#include <device/device.h>
+
+u32 volatile_read(volatile u32 addr)
+{
+ volatile u32 result;
+ result = *(volatile u32*)addr;
+ return result;
+}
+
+int dimm_is_registered(u8 spd_byte3)
+{
+ spd_byte3 &= 0x0f;
+ if( (spd_byte3 == DIMM_TYPE_RDIMM)
+ | (spd_byte3 == DIMM_TYPE_MINI_RDIMM)
+ | (spd_byte3 == DIMM_TYPE_72B_SO_RDIMM) )
+ return 1;
+
+ return 0;
+}
+
+void spd_decode_ddr3(dimm_attr *dimm, spd_raw_data spd)
+{
+ int nCRC, i;
+ u16 crc, spd_crc;
+ u8 * ptr = spd;
+ u8 ftb_divisor;
+ u8 ftb_dividend;
+ u8 capacity_shift, bus_width, sdram_width;
+ u32 mtb; /* medium time base */
+ /* Make sure that the spd dump is indeed from a DDR3 module */
+ if(spd[2] != DRAM_TYPE_DDR3)
+ {
+ printram("Not a DDR3 SPD!\n");
+ dimm->dram_type = DRAM_TYPE_UNDEFINED;
+ return;
+ }
+ dimm->dram_type = DRAM_TYPE_DDR3;
+
+ /* Find the number of bytes covered by CRC */
+ if(spd[0] & 0x80) {
+ nCRC = 117;
+ } else {
+ nCRC =126;
+ }
+
+ /* Compute the CRC */
+ crc = 0;
+ while (--nCRC >= 0) {
+ crc = crc ^ (int)*ptr++ << 8;
+ for (i = 0; i < 8; ++i)
+ if (crc & 0x8000) {
+ crc = crc << 1 ^ 0x1021;
+ } else {
+ crc = crc << 1;
+ }
+ }
+ /* Compare with the CRC in the SPD */
+ spd_crc = (spd[127] << 8) + spd[126];
+ /* Verify the CRC is correct */
+ if(crc != spd_crc)
+ printram("SPD CRC failed!!!");
+
+
+ unsigned int reg, val, param;
+ printram(" Revision: %x \n", spd[1] );
+ printram(" Type : %x \n", spd[2] );
+ printram(" Key : %x \n", spd[3] );
+
+ reg = spd[4];
+ /* Number of memory banks */
+ val = (reg >> 4) & 0x07;
+ if (val > 0x03) printram(" Invalid number of memory banks\n");
+ param = 1 << (val + 3);
+ printram(" Banks : %u \n", param );
+ /* SDRAM capacity */
+ capacity_shift = reg & 0x0f;
+ if (capacity_shift > 0x06) printram(" Invalid module capacity\n");
+ if (capacity_shift < 0x02) {
+ printram(" Capacity: %u Mb\n", 256 << capacity_shift);
+ } else {
+ printram(" Capacity: %u Gb\n", 1 << (capacity_shift - 2));
+ }
+
+ reg = spd[5];
+ /* Row address bits */
+ val = (reg >> 4) & 0x07;
+ if(val > 0x04) printram(" Invalid row address bits\n");
+ dimm->row_bits = val + 12;
+ /* Column address bits */
+ val = reg & 0x07;
+ if(val > 0x03) printram(" Invalid column address bits\n");
+ dimm->col_bits = val + 9;
+
+ /* Module nominal voltage */
+ reg = spd[6];
+ print_debug(" Supported voltages: ");
+ if(reg & (1<<2) ) print_debug("1.2V ");
+ if(reg & (1<<1) ) print_debug("1.35V ");
+ if( !(reg & (1<<0)) ) print_debug("1.5V ");
+ print_debug("\n");
+
+ /* Module organization */
+ reg = spd[7];
+ /* Number of ranks*/
+ val = (reg >> 3) & 0x07;
+ if(val > 3) printram(" Invalid number of ranks\n");
+ dimm->ranks = val + 1;
+ /* SDRAM device width */
+ val = (reg & 0x07);
+ if(val > 3) printram(" Invalid SDRAM width\n");
+ sdram_width = (4 << val);
+ printram(" SDRAM width : %u \n", sdram_width);
+
+ /* Memory bus width */
+ reg = spd[8];
+ /* Bus extension */
+ val = (reg >> 3) & 0x03;
+ if(val > 1) printram(" Invalid bus extension\n");
+ printram(" Bus extension : %u bits\n", val?8:0);
+ /* Bus width */
+ val = reg & 0x07;
+ if(val > 3) printram(" Invalid bus width\n");
+ bus_width = 8 << val;
+ printram(" Bus width : %u \n", bus_width);
+
+ /* We have all the info we need to compute the dimm size */
+ /* Capacity is 256Mbit multiplied by the power of 2 specified in
+ * capacity_shift
+ * The rest is the JEDEC formula */
+ /* I am certain it will fit in 16 bits
+ * Remember, It's in units of 2^24 bytes*/
+ dimm->size = ( (1 << (capacity_shift + (25-24)) ) * bus_width
+ * dimm->ranks ) / sdram_width;
+
+ /* Fine Timebase (FTB) Dividend/Divisor */
+ /* Dividend */
+ ftb_dividend = (spd[9] >> 4) & 0x0f;
+ /* Divisor */
+ ftb_divisor = spd[9] & 0x0f;
+
+ /* Medium Timebase =
+ * Medium Timebase (MTB) Dividend /
+ * Medium Timebase (MTB) Divisor */
+ mtb = (((u32)spd[10]) << 8) / spd [11];
+
+ /* SDRAM Minimum Cycle Time (tCKmin) */
+ dimm->tCK = spd[12] * mtb;
+
+ /* CAS Latencies Supported */
+ dimm->cas_supported = (spd[15] << 8) + spd[14];
+
+ /* Minimum CAS Latency Time (tAAmin) */
+ dimm->tAA = spd[16] * mtb;
+
+ /* Minimum Write Recovery Time (tWRmin) */
+ dimm->tWR = spd[17] * mtb;
+
+ /* Minimum RAS# to CAS# Delay Time (tRCDmin) */
+ dimm->tRCD = spd[18] * mtb;
+
+ /* Minimum Row Active to Row Active Delay Time (tRRDmin) */
+ dimm->tRRD = spd[19] * mtb;
+
+ /* Minimum Row Precharge Delay Time (tRPmin)*/
+ dimm->tRP = spd[20] * mtb;
+
+ /* Minimum Active to Precharge Delay Time (tRASmin) */
+ dimm->tRAS = (((spd[21] & 0x0f) << 8) + spd[22]) * mtb;
+
+ /* Minimum Active to Active/Refresh Delay Time (tRCmin) */
+ dimm->tRC = (((spd[21] & 0xf0) << 4) + spd[23]) * mtb;
+
+ /* Minimum Refresh Recovery Delay Time (tRFCmin) */
+ dimm->tRFC = ((spd[25] << 8) + spd[24]) * mtb;
+
+ /* Minimum Internal Write to Read Command Delay Time (tWTRmin) */
+ dimm->tWTR = spd[26] * mtb;
+
+ /* Minimum Internal Read to Precharge Command Delay Time (tRTPmin) */
+ dimm->tRTP = spd[27] * mtb;
+
+ /* Minimum Four Activate Window Delay Time (tFAWmin) */
+ dimm->tFAW = (((spd[28] & 0x0f) << 8) + spd[29]) * mtb;
+
+ /* SDRAM Optional Features */
+ reg = spd[30];
+ print_debug(" Optional features :");
+ if(reg & 0x80) print_debug(" DLL-Off_mode");
+ if(reg & 0x02) print_debug(" RZQ/7");
+ if(reg & 0x01) print_debug(" RZQ/6");
+ print_debug("\n");
+
+ /* SDRAM Thermal and Refresh Options */
+ reg = spd[31];
+ print_debug(" Thermal features :");
+ if(reg & 0x80) print_debug(" PASR");
+ if(reg & 0x08) print_debug(" ODTS");
+ if(reg & 0x04) print_debug(" ASR");
+ if(reg & 0x02) print_debug(" ext_temp_refresh");
+ if(reg & 0x01) print_debug(" ext_temp_range");
+ print_debug("\n");
+
+ /* Module Thermal Sensor */
+ reg = spd[32];
+ print_debug(" Thermal sensor : ");
+ if(reg & 0x80) print_debug("yes");
+ else print_debug("no");
+ print_debug("\n");
+
+ /* SDRAM Device Type */
+ reg = spd[33];
+ print_debug(" Standard SDRAM : ");
+ if(reg & 0x80) print_debug("no");
+ else print_debug("yes");
+ print_debug("\n");
+
+ /* Fine Offset for SDRAM Minimum Cycle Time (tCKmin) */
+ //printram(" tCKmin FTB : %i \n", spd[34]);
+ /* Fine Offset for Minimum CAS Latency Time (tAAmin) */
+ //printram(" tAAmin FTB : %i \n", spd[35]);
+ /* Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin) */
+ //printram(" tRCDmin FTB : %i \n", spd[36]);
+ /* Fine Offset for Minimum Row Precharge Delay Time (tRPmin) */
+ //printram(" tRPmin FTB : %i \n", spd[37]);
+ /* Fine Offset for Minimum Active to Active/Refresh Delay Time (tRCmin) */
+ //printram(" tRCmin FTB : %i \n", spd[38]);
+
+ if(spd[60] & 0x01)
+ printram(" DIMM Address bits mirrorred!!!\n");
+
+}
+
+static void print_ns(const char * msg, u32 val)
+{
+ u32 mant, fp;
+ mant = val/256;
+ fp = (val % 256) * 1000/256;
+
+ printram("%s%3u.%.3u ns\n", msg, mant, fp);
+}
+
+void dram_print_spd_ddr3(const dimm_attr *dimm)
+{
+ u16 val16;
+ int i;
+
+ printram(" Row addr bits : %u \n", dimm->row_bits);
+ printram(" Column addr bits : %u \n", dimm->col_bits);
+ printram(" Number of ranks : %u \n", dimm->ranks);
+ printram(" DIMM Capacity : %u MB\n", dimm->size << 4);
+
+ /* CAS Latencies Supported */
+ val16 = dimm->cas_supported;
+ print_debug(" CAS latencies :");
+ i = 0;
+ do{
+ if(val16 & 1) printram(" %u", i + 4);
+ i++;
+ val16 >>= 1;
+ } while(val16);
+ print_debug("\n");
+
+ print_ns(" tCKmin : ", dimm->tCK);
+ print_ns(" tAAmin : ", dimm->tAA);
+ print_ns(" tWRmin : ", dimm->tWR);
+ print_ns(" tRCDmin : ", dimm->tRCD);
+ print_ns(" tRRDmin : ", dimm->tRRD);
+ print_ns(" tRPmin : ", dimm->tRP);
+ print_ns(" tRASmin : ", dimm->tRAS);
+ print_ns(" tRCmin : ", dimm->tRC);
+ print_ns(" tRFCmin : ", dimm->tRFC);
+ print_ns(" tWTRmin : ", dimm->tWTR);
+ print_ns(" tRTPmin : ", dimm->tRTP);
+ print_ns(" tFAWmin : ", dimm->tFAW);
+
+}
diff --git a/src/devices/smbus/early_smbus.c b/src/devices/smbus/early_smbus.c
new file mode 100644
index 0000000..4583aca
--- /dev/null
+++ b/src/devices/smbus/early_smbus.c
@@ -0,0 +1,141 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+/**
+ * @file post_codes.h
+ *
+ * This file defines the implementations for the functions defined in smbus.h
+ * These are a generic SMBUS implementation, which should work with a majority
+ * of chipsets.
+ * They are marked weak so that they can be overridden by the chipset code if
+ * necessary.
+ */
+
+#include "smbus.h"
+
+/**
+ * \brief Brief delay for SMBUS transactions
+ */
+__attribute__((weak))
+void __smbus_delay(void)
+{
+ inb(0x80);
+}
+
+/**
+ * \brief Clear the SMBUS host status register
+ */
+__attribute__((weak))
+void __smbus_reset(u16 __smbus_io_base)
+{
+ outb(0xdf, SMBHSTSTAT);
+}
+
+/**
+ * \brief Print an error, should it occur. If no error, just exit.
+ *
+ * @param host_status The data returned on the host status register after
+ * a transaction is processed.
+ * @param loops The number of times a transaction was attempted.
+ * @return 0 if no error occurred
+ * 1 if an error was detected
+ */
+__attribute__((weak))
+int __smbus_print_error(u8 host_status, int loops, u16 __smbus_io_base)
+{
+ /* Check if there actually was an error. */
+ if ((host_status == 0x00 || host_status == 0x40 ||
+ host_status == 0x42) && (loops < SMBUS_TIMEOUT))
+ return 0;
+
+ if (loops >= SMBUS_TIMEOUT)
+ printsmbus("SMBus timeout\n");
+ if (host_status & (1 << 4))
+ printsmbus("Interrupt/SMI# was Failed Bus Transaction\n");
+ if (host_status & (1 << 3))
+ printsmbus("Bus error\n");
+ if (host_status & (1 << 2))
+ printsmbus("Device error\n");
+ if (host_status & (1 << 1))
+ printsmbus("Interrupt/SMI# completed successfully\n");
+ if (host_status & (1 << 0))
+ printsmbus("Host busy\n");
+ return 1;
+}
+
+/**
+ * \brief Checks if the SMBUS is currently busy with a transaction
+ */
+__attribute__((weak))
+int __smbus_is_busy(u16 __smbus_io_base)
+{
+ /* Check if bit 0 of the status register is 1 (busy) or 0 (ready) */
+ return ( (inb(SMBHSTSTAT) & (1 << 0)) == 1);
+}
+
+/**
+ * \brief Wait for the SMBUS to become ready to process a new transaction.
+ */
+__attribute__((weak))
+int __smbus_wait_until_ready(u16 __smbus_io_base)
+{
+ int loops;
+
+ printsmbus("Waiting until SMBus ready\n");
+
+ /* Loop up to SMBUS_TIMEOUT times, waiting for bit 0 of the
+ * SMBus Host Status register to go to 0, indicating the operation
+ * was completed successfully. I don't remember why I did it this way,
+ * but I think it was because ROMCC was running low on registers */
+ loops = 0;
+ while (__smbus_is_busy(__smbus_io_base) && loops < SMBUS_TIMEOUT)
+ ++loops;
+
+ return __smbus_print_error(inb(SMBHSTSTAT), loops, __smbus_io_base);
+}
+
+/**
+ * \brief Read a byte from the SMBUS.
+ *
+ * @param dimm The address location of the DIMM on the SMBus.
+ * @param offset The offset the data is located at.
+ */
+__attribute__((weak))
+u8 __smbus_read_byte(u8 dimm, u8 offset, u16 __smbus_io_base)
+{
+ u8 val;
+
+ /* Initialize SMBUS sequence */
+ __smbus_reset(__smbus_io_base);
+ /* Clear host data port. */
+ outb(0x00, SMBHSTDAT0);
+
+ __smbus_wait_until_ready(__smbus_io_base);
+
+ /* Actual addr to reg format. */
+ dimm = (dimm << 1);
+ dimm |= 1; /* read command */
+ outb(dimm, SMBXMITADD);
+ outb(offset, SMBHSTCMD);
+ /* Start transaction, byte data read. */
+ outb(0x48, SMBHSTCTL);
+ __smbus_wait_until_ready(__smbus_io_base);
+
+ val = inb(SMBHSTDAT0);
+ return val;
+}
\ No newline at end of file
diff --git a/src/devices/smbus/smbus.h b/src/devices/smbus/smbus.h
new file mode 100644
index 0000000..820a0dd
--- /dev/null
+++ b/src/devices/smbus/smbus.h
@@ -0,0 +1,99 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/**
+ * @file post_codes.h
+ *
+ * This file defines the prototypes for several common SMBUS functions
+ * These functions are prefixed with __smbus_ so that they do not conflict with
+ * the dozens of similar (duplicated) implementations in many southbridges.
+ *
+ * As a last parameter, the SMBUS functions take a u16 value __smbus_io_base,
+ * which represents the base IO port for smbus transactions
+ */
+
+#include <arch/io.h>
+
+/**
+ * \brief SMBUS IO ports in relation to the base IO port
+ */
+#define SMBHSTSTAT __smbus_io_base + 0x0
+#define SMBSLVSTAT __smbus_io_base + 0x1
+#define SMBHSTCTL __smbus_io_base + 0x2
+#define SMBHSTCMD __smbus_io_base + 0x3
+#define SMBXMITADD __smbus_io_base + 0x4
+#define SMBHSTDAT0 __smbus_io_base + 0x5
+#define SMBHSTDAT1 __smbus_io_base + 0x6
+#define SMBBLKDAT __smbus_io_base + 0x7
+#define SMBSLVCTL __smbus_io_base + 0x8
+#define SMBTRNSADD __smbus_io_base + 0x9
+#define SMBSLVDATA __smbus_io_base + 0xa
+
+#define SMBUS_TIMEOUT (100*1000*10)
+
+/**
+ * \brief printk macro for SMBUS debugging
+ */
+#if defined(CONFIG_DEBUG_SMBUS_SETUP) && (CONFIG_DEBUG_SMBUS_SETUP)
+#define printsmbus(x, ...) printk(BIOS_DEBUG, x, ##__VA_ARGS__)
+#else
+#define printsmbus(x, ...)
+#endif
+
+void __smbus_reset(u16 __smbus_io_base);
+int __smbus_print_error(u8 host_status, int loops, u16 __smbus_io_base);
+int __smbus_is_busy(u16 __smbus_io_base);
+int __smbus_wait_until_ready(u16 __smbus_io_base);
+u8 __smbus_read_byte(u8 dimm, u8 offset, u16 __smbus_io_base);
+
+void __smbus_delay(void);
+
+#if defined(SMBUS_IO_BASE) && (SMBUS_IO_BASE != 0)
+
+__attribute__((always_inline, unused))
+static void smbus_reset(void)
+{
+ __smbus_reset(SMBUS_IO_BASE);
+}
+
+__attribute__((always_inline, unused))
+static int smbus_is_busy(void)
+{
+ return __smbus_is_busy(SMBUS_IO_BASE);
+}
+
+__attribute__((always_inline, unused))
+static int smbus_wait_until_ready(void)
+{
+ return __smbus_wait_until_ready(SMBUS_IO_BASE);
+}
+
+__attribute__((always_inline, unused))
+static int smbus_print_error(u8 host_status, int loops)
+{
+ return __smbus_print_error(host_status, loops, SMBUS_IO_BASE);
+}
+
+__attribute__((always_inline, unused))
+static u8 smbus_read_byte(u8 dimm, u8 offset)
+{
+ return __smbus_read_byte(dimm, offset, SMBUS_IO_BASE);
+}
+
+#endif
\ No newline at end of file
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index fd886da..ff70fa3 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -1337,6 +1337,28 @@
#define PCI_DEVICE_ID_VIA_VX855_VGA 0x5122
#define PCI_DEVICE_ID_VIA_VX855_VLINK 0x7409
#define PCI_DEVICE_ID_VIA_VX855_MEMCTRL 0x3409
+/* VIA VX900 PCI IDs */
+#define PCI_DEVICE_ID_VIA_VX900_HOST_BR 0x0410
+#define PCI_DEVICE_ID_VIA_VX900_ERR 0x1410
+#define PCI_DEVICE_ID_VIA_VX900_CPU_CTR 0x2410
+#define PCI_DEVICE_ID_VIA_VX900_MEMCTRL 0x3410
+#define PCI_DEVICE_ID_VIA_VX900_PM 0x4410
+#define PCI_DEVICE_ID_VIA_VX900_APIC 0x5410
+#define PCI_DEVICE_ID_VIA_VX900_SCRATCH 0x6410
+#define PCI_DEVICE_ID_VIA_VX900_NBRIDGE 0x7410
+#define PCI_DEVICE_ID_VIA_VX900_LPC 0x8410
+#define PCI_DEVICE_ID_VIA_VX900_PEX1 0xa410
+#define PCI_DEVICE_ID_VIA_VX900_PEX2 0xb410
+#define PCI_DEVICE_ID_VIA_VX900_PEX3 0xc410
+#define PCI_DEVICE_ID_VIA_VX900_PEX4 0xd410
+#define PCI_DEVICE_ID_VIA_VX900_PEX_CTR 0xe410
+#define PCI_DEVICE_ID_VIA_VX900_SBRIDGE 0xa535
+#define PCI_DEVICE_ID_VIA_VX900_PCI_BR 0xb535
+#define PCI_DEVICE_ID_VIA_VX900_VGA 0x7122
+#define PCI_DEVICE_ID_VIA_VX900_VID_DEC 0x9170
+#define PCI_DEVICE_ID_VIA_VX900_HDAC 0x3288
+#define PCI_DEVICE_ID_VIA_VX900_ETH 0x3119
+/* VIA CN700 */
#define PCI_DEVICE_ID_VIA_CN700_AGP 0x0314
#define PCI_DEVICE_ID_VIA_CN700_ERR 0x1314
#define PCI_DEVICE_ID_VIA_CN700_HOST 0x2314
diff --git a/src/lib/.cbfs.c.kate-swp b/src/lib/.cbfs.c.kate-swp
new file mode 100644
index 0000000..574cd2f
Binary files /dev/null and b/src/lib/.cbfs.c.kate-swp differ
diff --git a/src/mainboard/asus/Kconfig b/src/mainboard/asus/Kconfig
index 1ca1278..318761d 100644
--- a/src/mainboard/asus/Kconfig
+++ b/src/mainboard/asus/Kconfig
@@ -82,7 +82,7 @@ source "src/mainboard/asus/p2b-ds/Kconfig"
source "src/mainboard/asus/p2b-f/Kconfig"
source "src/mainboard/asus/p2b-ls/Kconfig"
source "src/mainboard/asus/p3b-f/Kconfig"
-source "src/mainboard/asus/dsbf/Kconfig
+source "src/mainboard/asus/dsbf/Kconfig"
config MAINBOARD_VENDOR
string
diff --git a/src/mainboard/via/Kconfig b/src/mainboard/via/Kconfig
index 6980548..48f4055 100644
--- a/src/mainboard/via/Kconfig
+++ b/src/mainboard/via/Kconfig
@@ -9,6 +9,8 @@ config BOARD_VIA_EPIA_CN
bool "EPIA-CN"
config BOARD_VIA_EPIA_M700
bool "EPIA-M700"
+config BOARD_VIA_EPIA_M850
+ bool "EPIA-M850"
config BOARD_VIA_EPIA_M
bool "EPIA-M"
config BOARD_VIA_EPIA_N
@@ -23,6 +25,7 @@ endchoice
source "src/mainboard/via/epia/Kconfig"
source "src/mainboard/via/epia-cn/Kconfig"
source "src/mainboard/via/epia-m700/Kconfig"
+source "src/mainboard/via/epia-m850/Kconfig"
source "src/mainboard/via/epia-m/Kconfig"
source "src/mainboard/via/epia-n/Kconfig"
source "src/mainboard/via/pc2500e/Kconfig"
diff --git a/src/mainboard/via/epia-m850/Kconfig b/src/mainboard/via/epia-m850/Kconfig
new file mode 100644
index 0000000..1309e87
--- /dev/null
+++ b/src/mainboard/via/epia-m850/Kconfig
@@ -0,0 +1,47 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2011-2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
+##
+## This program is free software: you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation, either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program. If not, see <http://www.gnu.org/licenses/>.
+##
+
+if BOARD_VIA_EPIA_M850
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select ARCH_X86
+ select CPU_VIA_NANO
+ select NORTHBRIDGE_VIA_VX900
+ select SUPERIO_FINTEK_F81865F
+ #select BOARD_HAS_FADT
+ #select HAVE_PIRQ_TABLE
+ #select HAVE_ACPI_TABLES
+ #select HAVE_OPTION_TABLE
+ select BOARD_ROMSIZE_KB_512
+ select RAMINIT_SYSINFO
+
+config MAINBOARD_DIR
+ string
+ default via/epia-m850
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "EPIA-M850"
+
+config IRQ_SLOT_COUNT
+ int
+ default 13
+
+endif # BOARD_VIA_EPIA_M850
diff --git a/src/mainboard/via/epia-m850/Makefile.inc b/src/mainboard/via/epia-m850/Makefile.inc
new file mode 100644
index 0000000..9c6d31f
--- /dev/null
+++ b/src/mainboard/via/epia-m850/Makefile.inc
@@ -0,0 +1,21 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
+##
+## This program is free software: you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation, either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program. If not, see <http://www.gnu.org/licenses/>.
+##
+
+#romstage-y += ./../../../superio/fintek/f81865f/f81865f_early_serial.c
+
diff --git a/src/mainboard/via/epia-m850/chip.h b/src/mainboard/via/epia-m850/chip.h
new file mode 100644
index 0000000..7872fde
--- /dev/null
+++ b/src/mainboard/via/epia-m850/chip.h
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+extern struct chip_operations mainboard_ops;
+
+struct mainboard_config {};
diff --git a/src/mainboard/via/epia-m850/devicetree.cb b/src/mainboard/via/epia-m850/devicetree.cb
new file mode 100644
index 0000000..b3418a2
--- /dev/null
+++ b/src/mainboard/via/epia-m850/devicetree.cb
@@ -0,0 +1,63 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
+##
+## This program is free software: you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation, either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program. If not, see <http://www.gnu.org/licenses/>.
+##
+
+chip northbridge/via/vx900 # Northbridge
+ device lapic_cluster 0 on # APIC cluster
+ chip cpu/via/nano # VIA NANO
+ device lapic 0 on end # APIC
+ end
+ end
+ device pci_domain 0 on
+ device pci 0.0 off end # AGP Bridge
+ device pci 0.1 off end # Error Reporting
+ device pci 0.2 off end # Host Bus Control
+ device pci 0.3 off end # Memory Controller
+ device pci 0.4 off end # Power Management
+ device pci 0.5 off end # Power Management
+ device pci 0.6 off end # Power Management
+ device pci 0.7 off end # V-Link Controller
+ device pci 1.0 off end # PCI Bridge
+ device pci 1.1 off end # Audio
+ device pci 3.0 off end # PCIE control
+ device pci 3.1 off end # PEX1
+ device pci 3.2 off end # PEX2
+ device pci 3.3 off end # PEX3
+ device pci 3.4 off end # PEX4
+ device pci c.0 off end
+ device pci d.0 off end
+ device pci f.0 off end # IDE/SATA
+ device pci 10.0 off end # USB 1.1
+ device pci 10.1 off end # USB 1.1
+ device pci 10.2 off end # USB 1.1
+ device pci 10.3 off end # USB 1.1
+ device pci 10.4 off end # USB 2.0
+ device pci 11.0 on end # LPC
+# chip drivers/generic/generic # DIMM 0 channel 1
+# device i2c 50 off end
+# end
+# chip drivers/generic/generic # DIMM 1 channel 1
+# device i2c 51 off end
+# end
+ chip superio/fintek/f81865f # Super duper IO
+ end
+ device pci 11.7 off end # NB/SB control
+ device pci 13.0 off end # PCI Bridge
+ device pci 14.0 off end # HD Audio
+ end
+end
diff --git a/src/mainboard/via/epia-m850/mainboard.c b/src/mainboard/via/epia-m850/mainboard.c
new file mode 100644
index 0000000..df72a0c
--- /dev/null
+++ b/src/mainboard/via/epia-m850/mainboard.c
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <device/device.h>
+#include "chip.h"
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("VIA EPIA-M850 Mainboard")
+};
diff --git a/src/mainboard/via/epia-m850/romstage.c b/src/mainboard/via/epia-m850/romstage.c
new file mode 100644
index 0000000..043afc3
--- /dev/null
+++ b/src/mainboard/via/epia-m850/romstage.c
@@ -0,0 +1,78 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011-2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/*
+ * Inspired from the EPIA-M700
+ */
+
+#include <stdint.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <arch/hlt.h>
+#include <console/console.h>
+#include <lib.h>
+#include "cpu/x86/bist.h"
+#include <string.h>
+
+#include "northbridge/via/vx900/early_vx900.h"
+#include "northbridge/via/vx900/raminit.h"
+#include "superio/fintek/f81865f/f81865f_early_serial.c"
+
+#define SERIAL_DEV PNP_DEV(0x4e, 0x10)
+
+/* cache_as_ram.inc jumps to here. */
+void main(unsigned long bist)
+{
+ /* Enable multifunction bit for northbridge.
+ * This enables the PCI configuration spaces of D0F1 to D0F7 to be
+ * accessed */
+ pci_write_config8(PCI_DEV(0, 0, 0), 0x4f, 0x01);
+
+ f81865f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ console_init();
+ print_debug("Console initialized. \n");
+
+ /* Halt if there was a built-in self test failure. */
+ report_bist_failure(bist);
+
+ /* x86 cold boot I/O cmd. */
+ enable_smbus();
+
+ /* If this works, then SMBUS is up and running */
+ //dump_spd_data();
+
+ /* Now we can worry about raminit.
+ * This board only has DDR3, so no need to worry about which DRAM type
+ * to use */
+ dimm_layout dimms = {{0x50, 0x51, SPD_END_LIST}};
+ vx900_init_dram_ddr3(&dimms);
+
+ //ram_check(0, 0x80);
+ ram_check((1<<20), 0x80);
+ ram_check((1<<26), 0x80);
+
+
+ print_debug("We passed RAM verify\n");
+
+ return;
+
+}
diff --git a/src/northbridge/via/Kconfig b/src/northbridge/via/Kconfig
index 2c38acf..8a747b9 100644
--- a/src/northbridge/via/Kconfig
+++ b/src/northbridge/via/Kconfig
@@ -4,3 +4,4 @@ source src/northbridge/via/cn400/Kconfig
source src/northbridge/via/vt8601/Kconfig
source src/northbridge/via/vt8623/Kconfig
source src/northbridge/via/vx800/Kconfig
+source src/northbridge/via/vx900/Kconfig
diff --git a/src/northbridge/via/Makefile.inc b/src/northbridge/via/Makefile.inc
index 75cb15b..2e74b61 100644
--- a/src/northbridge/via/Makefile.inc
+++ b/src/northbridge/via/Makefile.inc
@@ -4,4 +4,5 @@ subdirs-$(CONFIG_NORTHBRIDGE_VIA_CN700) += cn700
subdirs-$(CONFIG_NORTHBRIDGE_VIA_CX700) += cx700
subdirs-$(CONFIG_NORTHBRIDGE_VIA_CN400) += cn400
subdirs-$(CONFIG_NORTHBRIDGE_VIA_VX800) += vx800
+subdirs-$(CONFIG_NORTHBRIDGE_VIA_VX900) += vx900
diff --git a/src/northbridge/via/vx800/lpc.c b/src/northbridge/via/vx800/lpc.c
index b9941d1..144ede0 100644
--- a/src/northbridge/via/vx800/lpc.c
+++ b/src/northbridge/via/vx800/lpc.c
@@ -375,3 +375,9 @@ static const struct pci_driver lpc_driver __pci_driver = {
.vendor = PCI_VENDOR_ID_VIA,
.device = PCI_DEVICE_ID_VIA_VX855_LPC,
};
+
+static const struct pci_driver lpc_driver_900 __pci_driver = {
+ .ops = &vx800_lpc_ops,
+ .vendor = PCI_VENDOR_ID_VIA,
+ .device = PCI_DEVICE_ID_VIA_VX900_LPC,
+};
\ No newline at end of file
diff --git a/src/northbridge/via/vx900/Kconfig b/src/northbridge/via/vx900/Kconfig
new file mode 100644
index 0000000..d1c7a48
--- /dev/null
+++ b/src/northbridge/via/vx900/Kconfig
@@ -0,0 +1,23 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
+##
+## This program is free software: you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation, either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program. If not, see <http://www.gnu.org/licenses/>.
+##
+
+config NORTHBRIDGE_VIA_VX900
+ bool
+ select HAVE_DEBUG_RAM_SETUP
+ select HAVE_DEBUG_SMBUS
\ No newline at end of file
diff --git a/src/northbridge/via/vx900/Makefile.inc b/src/northbridge/via/vx900/Makefile.inc
new file mode 100644
index 0000000..614c663
--- /dev/null
+++ b/src/northbridge/via/vx900/Makefile.inc
@@ -0,0 +1,34 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
+##
+## This program is free software: you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation, either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program. If not, see <http://www.gnu.org/licenses/>.
+##
+
+romstage-y += early_smbus.c
+romstage-y += raminit_ddr3.c
+romstage-y += ./../../../devices/dram/dram_util.c
+romstage-y += ./../../../devices/smbus/early_smbus.c
+#romstage-y += ./../../../cpu/x86/lapic/apic_timer.c
+
+
+driver-y += northbridge.c
+# Drivers for these devices already exist with the vx800
+# Use those instead of duplicating code
+#driver-y += ./../vx800/vga.c
+driver-y += ./../vx800/lpc.c
+
+chipset_bootblock_inc += $(src)/northbridge/via/vx900/romstrap.inc
+chipset_bootblock_lds += $(src)/northbridge/via/vx900/romstrap.lds
diff --git a/src/northbridge/via/vx900/chip.h b/src/northbridge/via/vx900/chip.h
new file mode 100644
index 0000000..15c9744
--- /dev/null
+++ b/src/northbridge/via/vx900/chip.h
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+struct northbridge_via_vx900_config {
+};
+
+extern struct chip_operations northbridge_via_vx900_ops;
diff --git a/src/northbridge/via/vx900/early_smbus.c b/src/northbridge/via/vx900/early_smbus.c
new file mode 100644
index 0000000..aa6cec0
--- /dev/null
+++ b/src/northbridge/via/vx900/early_smbus.c
@@ -0,0 +1,191 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <device/pci_ids.h>
+#include "early_vx900.h"
+
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <console/console.h>
+#include <devices/dram/dram.h>
+
+__attribute__((unused))
+static void smbus_delays(int delays)
+{
+ while(delays--) __smbus_delay();
+}
+
+
+/**
+ * Read a byte from the SMBus.
+ *
+ * @param dimm The address location of the DIMM on the SMBus.
+ * @param offset The offset the data is located at.
+ */
+u8 __smbus_read_byte(u8 dimm, u8 offset, u16 __smbus_io_base)
+{
+ u8 val;
+
+ /* Initialize SMBUS sequence */
+ smbus_reset();
+ /* Clear host data port. */
+ outb(0x00, SMBHSTDAT0);
+
+ smbus_wait_until_ready();
+ smbus_delays(50);
+
+ /* Actual addr to reg format. */
+ dimm = (dimm << 1);
+ dimm |= 1; /* read command */
+ outb(dimm, SMBXMITADD);
+ outb(offset, SMBHSTCMD);
+ /* Start transaction, byte data read. */
+ outb(0x48, SMBHSTCTL);
+ smbus_wait_until_ready();
+
+ val = inb(SMBHSTDAT0);
+ return val;
+}
+
+void enable_smbus(void)
+{
+ device_t dev;
+ u8 reg8;
+ u16 __smbus_io_base = SMBUS_IO_BASE;
+
+ /* Locate the Power Management control */
+ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_VX900_LPC), 0);
+
+ if (dev == PCI_DEV_INVALID) {
+ die("Power Managment Controller not found\n");
+ }
+
+ /*
+ * To use SMBus to manage devices on the system board, it is a must to
+ * enable SMBus function by setting
+ * PMU_RXD2[0] (SMBus Controller Enable) to 1.
+ * And set PMU_RXD0 and PMU_RXD1 (SMBus I/O Base) to an appropriate
+ * I/O port address, so that all registers in SMBus I/O port can be
+ * accessed.
+ */
+
+ reg8 = pci_read_config8(dev, 0xd2);
+ /* Enable SMBus controller */
+ reg8 |= 1;
+ /* Set SMBUS clock from 128k source */
+ reg8 |= 1<<2;
+ pci_write_config8(dev, 0xd2, reg8);
+
+ reg8 = pci_read_config8(dev, 0x94);
+ /* SMBUS clock from divider of 14.318 MHz */
+ reg8 &= ~(1<<7);
+ pci_write_config8(dev, 0x94, reg8);
+
+ /* Set SMBus IO base */
+ pci_write_config16(dev, 0xd0, SMBUS_IO_BASE);
+
+ /*
+ * Initialize the SMBus sequence:
+ */
+ /* Clear SMBus host status register */
+ smbus_reset();
+ /* Clear SMBus host data 0 register */
+ outb(0x00, SMBHSTDAT0);
+
+ /* Wait for SMBUS */
+ smbus_wait_until_ready();
+
+}
+
+void spd_read(u8 addr, spd_raw_data spd)
+{
+ u8 reg;
+ int i, regs;
+ reg = smbus_read_byte(addr, 2);
+ if(reg != 0x0b)
+ {
+ printk(BIOS_DEBUG, "SMBUS device %x not a DDR3 module\n", addr);
+ spd[2] = 0;
+ return;
+ }
+
+ reg = smbus_read_byte(addr, 0);
+ reg &= 0xf;
+ if (reg == 0x3) {
+ regs = 256;
+ } else if (reg == 0x2) {
+ regs = 176;
+ } else if (reg == 0x1) {
+ regs = 128;
+ } else {
+ printk(BIOS_INFO, "No DIMM present at %x\n", addr);
+ spd[2] = 0;
+ return;
+ }
+ printk(BIOS_DEBUG, "SPD Data for DIMM %x \n", addr);
+ for (i = 0; i < regs; i++) {
+ reg = smbus_read_byte(addr, i);
+ //printk(BIOS_DEBUG, " Offset %u = 0x%x \n", i, reg );
+ spd[i] = reg;
+ }
+}
+
+void dump_spd_data(void)
+{
+ int dimm, offset, regs;
+ unsigned int reg;
+ spd_raw_data spd;
+ dimm_attr dimmx;
+
+ for (dimm = 0x50; dimm < 0x52; dimm++) {
+ reg = smbus_read_byte(dimm, 2);
+ if(reg != 0x0b)
+ {
+ printk(BIOS_DEBUG,
+ "SMBUS device %x not a DDR3 module\n", dimm);
+ continue;
+ }
+
+ reg = smbus_read_byte(dimm, 0);
+ reg &= 0xf;
+ if (reg == 0x3) {
+ regs = 256;
+ } else if (reg == 0x2) {
+ regs = 176;
+ } else if (reg == 0x1) {
+ regs = 128;
+ } else {
+ printk(BIOS_INFO, "No DIMM present at %x\n", dimm);
+ regs = 0;
+ continue;
+ }
+ printk(BIOS_DEBUG, "SPD Data for DIMM %x \n", dimm);
+ for (offset = 0; offset < regs; offset++) {
+ reg = smbus_read_byte(dimm, offset);
+ //printk(BIOS_DEBUG, " Offset %u = 0x%x \n", offset, reg );
+ spd[offset] = reg;
+ }
+
+ spd_decode_ddr3(&dimmx, spd);
+ dram_print_spd_ddr3(&dimmx);
+
+ }
+}
+
diff --git a/src/northbridge/via/vx900/early_vx900.h b/src/northbridge/via/vx900/early_vx900.h
new file mode 100644
index 0000000..6b33077
--- /dev/null
+++ b/src/northbridge/via/vx900/early_vx900.h
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef EARLY_VX900_H
+#define EARLY_VX900_H
+
+#include <stdint.h>
+
+#define SMBUS_IO_BASE 0x500
+#include <devices/smbus/smbus.h>
+
+
+#include "raminit.h"
+
+void enable_smbus(void);
+void dump_spd_data(void);
+void spd_read(u8 addr, spd_raw_data spd);
+
+#endif /* EARLY_VX900_H */
diff --git a/src/northbridge/via/vx900/forgotten.c b/src/northbridge/via/vx900/forgotten.c
new file mode 100644
index 0000000..37aae81
--- /dev/null
+++ b/src/northbridge/via/vx900/forgotten.c
@@ -0,0 +1,192 @@
+#include "forgotten.h"
+#include <../../dram/dram.h>
+
+u16 ddr3_get_mr0(
+ char precharge_pd,
+ u8 write_recovery,
+ char dll_reset,
+ char mode,
+ u8 cas,
+ char interleaved_burst,
+ u8 burst_lenght
+){
+ u32 cmd = 0;
+ if(precharge_pd) cmd |= (1 << 12);
+ /* Write recovery */
+ cmd |= ( ((write_recovery - 4) & 0x7) << 9);
+ if(dll_reset) cmd |= (1 << 8);
+ if(mode) cmd |= (1<<7);
+ /* CAS latency) */
+ cmd |= ( ((cas - 4) & 0x7) << 4);
+ if(interleaved_burst) cmd |= (1 << 3);
+ /* Burst lenght */
+ cmd |= (burst_lenght & 0x3);
+ return cmd;
+}
+
+u16 ddr3_get_mr1(
+ char q_off_disable,
+ char tdqs,
+ u8 rtt_nom,
+ char write_leveling,
+ u8 output_drive_strenght,
+ u8 additive_latency,
+ u8 dll_disable
+){
+ u32 cmd = 0;
+ if(q_off_disable) cmd |= (1 << 12);
+ if(tdqs) cmd |= (1 << 11);
+ /* rtt_nom */
+ cmd |= ( ((rtt_nom & 4) << (9-2)) | ((rtt_nom & 2) << (6-1))
+ | ((rtt_nom & 1) << 2));
+ if(write_leveling) cmd |= (1 << 7);
+ /* output drive strenght */
+ cmd |= ( ((output_drive_strenght & 2) << (5-1))
+ | ((output_drive_strenght & 1) << 1) );
+ /* Additive latency */
+ cmd |= ((additive_latency & 0x3) << 3);
+ if(dll_disable) cmd |= (1 << 0);
+ return cmd;
+}
+
+u16 ddr3_get_mr2(
+ u8 rtt_wr,
+ char extended_temp,
+ char auto_self_refresh,
+ u8 cas_write
+){
+ u32 cmd = 0;
+ /* Rtt_wr */
+ cmd |= ( (rtt_wr & 0x3) << 9);
+ if(extended_temp) cmd |= (1 << 7);
+ if(auto_self_refresh) cmd |= (1 << 6);
+ /* CAS write latency */
+ cmd |= ( ((cas_write - 5) & 0x7) << 3);
+ return cmd;
+}
+
+u16 ddr3_get_mr3(char dataflow_from_mpr)
+{
+ u32 cmd = 0;
+ if(dataflow_from_mpr) cmd |= (1<<2);
+ return cmd;
+}
+
+/*
+ * Translate the MRS command into the memory address corresponding to the
+ * command. This is based on the CPU address to memory address mapping described
+ * by the initial values of registers 0x52 and 0x53, so do not fuck with them
+ * until after the MRS commands have been sent to all ranks
+ */
+
+u32 vx900_get_mrs_addr(u8 mrs_type, u16 cmd);
+
+u32 vx900_get_mrs_addr(u8 mrs_type, u16 cmd)
+{
+ u32 addr = 0;
+ /* A3 <-> MA0, A4 <-> MA1, ... A12 <-> MA9 */
+ addr |= ((cmd &0x3ff)<< 3);
+ /* A20 <-> MA10 */
+ addr |= (((cmd >> 10) & 0x1) << 20);
+ /* A13 <-> MA11, A14 <-> MA12 */
+ addr |= (((cmd >> 11) & 0x3) << 13);
+
+ /* Do not fuck with registers 0x52 and 0x53 if you want the following
+ * mappings to work for you:
+ * A17 <-> BA0, A18 <-> BA1, A19 <-> BA2 */
+ addr |= ((mrs_type & 0x7) << 17);
+ return addr;
+}
+void vx900_dram_ddr3_init_rank(device_t mcu, const ramctr_timing *ctrl,
+ int rank);
+void vx900_dram_ddr3_init_rank(device_t mcu, const ramctr_timing *ctrl,
+ int rank)
+{
+ u8 reg8;
+ u32 reg32, cmd, res, addr;
+ int i;
+
+ printram("Initializing rank %u\n", rank);
+
+ /* Step 06 - Set Fun3_RX6B[2:0] to 001b (NOP Command Enable). */
+ reg8 = pci_read_config8(mcu, 0x6b);
+ reg8 &= ~(0x07);
+ reg8 |= (1<<0);
+ pci_write_config8(mcu, 0x6b, reg8);
+ /* Step 07 - Read a double word from any address of the DIMM. */
+ reg32 = volatile_read(0x0);
+ udelay(10);
+ printram("We just read 0x%x\n", reg32);
+ /* Step 08 - Set Fun3_RX6B[2:0] to 011b (MSR Enable). */
+ reg8 = pci_read_config8(mcu, 0x6b);
+ reg8 &= ~(0x07);
+ reg8 |= (3<<0);
+ pci_write_config8(mcu, 0x6b, reg8);
+
+ /* Step 09 – Issue MR2 cycle. Read a double word from the address depended
+ * on DRAM’s Rtt_WR and CWL settings.
+ * (Check the byte 63 of SPD. If memory address lines of target physical
+ * rank is mirrored, MA3~MA8 and BA0~BA1 should be swapped.) */
+ cmd = ddr3_get_mr2(DDR3_MR2_RTT_WR_OFF,0,0,ctrl->CWL);
+ addr = vx900_get_mrs_addr(2, cmd);
+ if(addr != 0x00040040){
+ printram("MR2 needed at addr 0x%.8x, but done at 0x%.8x\n", 0x00040040, addr);
+ }
+ res = volatile_read(addr);
+ udelay(10);
+ printram("MR2 cycle 0x%.4x @ addr 0x%.8x read 0x%.8x\n", cmd, addr, res);
+
+ /* Step 10 – Issue MR3 cycle - set DRAM to normal operation mode.
+ */
+ cmd = ddr3_get_mr3(0);
+ addr = vx900_get_mrs_addr(3, cmd);
+ res = volatile_read(addr);
+ udelay(10);
+ printram("MR3 cycle 0x%.4x @ addr 0x%.8x read 0x%.8x\n", cmd, addr, res);
+
+ /* Step 11 –Issue MR1 cycle
+ * Set DRAM’s output driver impedance, and Rtt_Nom settings.
+ * * The DLL enable field, TDQS field, write leveling enable field,
+ * additive latency field, and Qoff field should be set to 0.
+ */
+ cmd = ddr3_get_mr1(DDR3_MR1_QOFF_ENABLE, DDR3_MR1_TQDS_DISABLE,
+ DDR3_MR1_RTT_NOM_RZQ2,
+ DDR3_MR1_WRITE_LEVELING_DISABLE, DDR3_MR1_ODS_RZQ7,
+ DDR3_MR1_AL_DISABLE, DDR3_MR1_DLL_ENABLE);
+ addr = vx900_get_mrs_addr(1, cmd);
+ res = volatile_read(addr);
+ udelay(10);
+ printram("MR1 cycle 0x%.4x @ addr 0x%.8x read 0x%.8x\n", cmd, addr, res);
+
+ /* Step 12 - Issue MR0 cycle.
+ * Set DRAM’s burst length, CAS latency and write recovery settings.
+ * * The read burst type field should be set to interleave.
+ * * The mode field should be set to normal mode.
+ * * The DLL reset field should be set to No.
+ * * The DLL control for precharge PD field should be set to Fast exit.
+ */
+ cmd = ddr3_get_mr0(DDR3_MR0_PRECHARGE_FAST, ctrl->WR,
+ DDR3_MR0_DLL_RESET_NO, DDR3_MR0_MODE_NORMAL,
+ ctrl->CAS, DDR3_MR0_BURST_TYPE_INTERLEAVED,
+ DDR3_MR0_BURST_LENGTH_CHOP);
+ addr = vx900_get_mrs_addr(0, cmd);
+ if(addr != 0x000069c8){
+ printram("MR0 needed at addr 0x%.8x, but done at 0x%.8x\n", 0x000069c8, addr);
+ addr = 0x000069c8;
+ }
+ res = volatile_read(addr);
+ printram("MR0 cycle 0x%.4x @ addr 0x%.8x read 0x%.8x\n", cmd, addr, res);
+
+ /* Step 13 - Set Rx6B[2:0] to 110b (Long ZQ calibration command). */
+ reg8 = pci_read_config8(mcu, 0x6b);
+ reg8 &= ~(0x07);
+ reg8 |= (3<<1);
+ pci_write_config8(mcu, 0x6b, reg8);
+ for(i = 0; i < 1000; i++) inb(0x80);
+
+
+ /* Step 14 - Read a double word from any address of the DIMM. */
+ reg32 = volatile_read(0x0);
+ printram("We just read 0x%x\n", reg32);
+}
+
diff --git a/src/northbridge/via/vx900/forgotten.h b/src/northbridge/via/vx900/forgotten.h
new file mode 100644
index 0000000..43641f7
--- /dev/null
+++ b/src/northbridge/via/vx900/forgotten.h
@@ -0,0 +1,78 @@
+#ifndef REDUNDANT_H
+#define REDUNDANT_H
+
+#define DDR3_MR0_PRECHARGE_SLOW 0
+#define DDR3_MR0_PRECHARGE_FAST 1
+#define DDR3_MR0_MODE_NORMAL 0
+#define DDR3_MR0_MODE_TEST 1
+#define DDR3_MR0_DLL_RESET_NO 0
+#define DDR3_MR0_DLL_RESET_YES 1
+#define DDR3_MR0_BURST_TYPE_SEQUENTIAL 0
+#define DDR3_MR0_BURST_TYPE_INTERLEAVED 1
+#define DDR3_MR0_BURST_LENGTH_FIXED_8 0
+#define DDR3_MR0_BURST_LENGTH_CHOP 1
+#define DDR3_MR0_BURST_LENGTH_FIXED_4 2
+/**
+ * \brief Get command address for a DDR3 MR0 command
+ */
+u16 ddr3_get_mr0(
+ char precharge_pd,
+ u8 write_recovery,
+ char dll_reset,
+ char mode,
+ u8 cas,
+ char interleaved_burst,
+ u8 burst_lenght
+);
+
+#define DDR3_MR1_TQDS_DISABLE 0
+#define DDR3_MR1_TQDS_ENABLE 1
+#define DDR3_MR1_QOFF_ENABLE 0
+#define DDR3_MR1_QOFF_DISABLE 1
+#define DDR3_MR1_WRITE_LEVELING_DISABLE 0
+#define DDR3_MR1_WRITE_LEVELING_ENABLE 1
+#define DDR3_MR1_RTT_NOM_OFF 0
+#define DDR3_MR1_RTT_NOM_RZQ4 1
+#define DDR3_MR1_RTT_NOM_RZQ2 2
+#define DDR3_MR1_RTT_NOM_RZQ6 3
+#define DDR3_MR1_RTT_NOM_RZQ12 4
+#define DDR3_MR1_RTT_NOM_RZQ8 5
+#define DDR3_MR1_AL_DISABLE 0
+#define DDR3_MR1_AL_CL_MINUS_1 1
+#define DDR3_MR1_AL_CL_MINUS_2 2
+#define DDR3_MR1_ODS_RZQ6 0
+#define DDR3_MR1_ODS_RZQ7 1
+#define DDR3_MR1_DLL_ENABLE 0
+#define DDR3_MR1_DLL_DISABLE 1
+/**
+ * \brief Get command address for a DDR3 MR1 command
+ */
+u16 ddr3_get_mr1(
+ char q_off,
+ char tdqs,
+ u8 rtt_nom,
+ char write_leveling,
+ u8 output_drive_strenght,
+ u8 additive_latency,
+ u8 dll_disable
+);
+
+#define DDR3_MR2_RTT_WR_OFF 0
+#define DDR3_MR2_RTT_WR_RZQ4 1
+#define DDR3_MR2_RTT_WR_RZQ2 2
+/**
+ * \brief Get command address for a DDR3 MR2 command
+ */
+u16 ddr3_get_mr2(
+ u8 rtt_wr,
+ char extended_temp,
+ char auto_self_refresh,
+ u8 cas_write
+);
+
+/**
+ * \brief Get command address for a DDR3 MR3 command
+ */
+u16 ddr3_get_mr3(char dataflow_from_mpr);
+
+#endif /* REDUNDANT_H */
\ No newline at end of file
diff --git a/src/northbridge/via/vx900/northbridge.c b/src/northbridge/via/vx900/northbridge.c
new file mode 100644
index 0000000..afdd208
--- /dev/null
+++ b/src/northbridge/via/vx900/northbridge.c
@@ -0,0 +1,91 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "vx900.h"
+#include "chip.h"
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <cpu/cpu.h>
+#include <cbmem.h>
+
+static void vx900_read_resources(device_t dev)
+{
+ print_debug("========= VX900 memory sizing & Co. ==========\n");
+ int idx = 0;
+ /* FIXME: just a quick memory sizing. fix me later */
+ unsigned long tolm = (1<<29);
+ ram_resource(dev, idx++, 0, 640);
+ /* Leave a hole for vga, 0xa0000 - 0xc0000 */
+ ram_resource(dev, idx++, 768, ((tolm >> 10) - 768));
+ #if CONFIG_WRITE_HIGH_TABLES
+ /* Leave some space for ACPI, PIRQ and MP tables */
+ high_tables_base = tolm - HIGH_MEMORY_SIZE;
+ high_tables_size = HIGH_MEMORY_SIZE;
+ printk(BIOS_DEBUG, "high_tables_base: %08llx, size %lld\n",
+ high_tables_base, high_tables_size);
+ #endif
+}
+
+static void pci_domain_set_resources(device_t dev)
+{
+ assign_resources(dev->link_list);
+}
+
+static void cpu_bus_init(device_t dev)
+{
+ initialize_cpus(dev->link_list);
+}
+
+static void cpu_bus_noop(device_t dev)
+{
+}
+static struct device_operations cpu_bus_ops = {
+ .read_resources = cpu_bus_noop,
+ .set_resources = cpu_bus_noop,
+ .enable_resources = cpu_bus_noop,
+ .init = cpu_bus_init,
+ .scan_bus = 0,
+};
+
+static struct device_operations pci_domain_ops = {
+ .read_resources = vx900_read_resources,
+ .set_resources = pci_domain_set_resources,
+ .enable_resources = NULL,
+ .init = NULL,
+ .scan_bus = pci_domain_scan_bus,
+};
+
+static void enable_dev(device_t dev)
+{
+ /* Set the operations if it is a special bus type */
+ if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
+ dev->ops = &pci_domain_ops;
+ } else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
+ dev->ops = &cpu_bus_ops;
+ }
+}
+
+struct chip_operations northbridge_via_vx900_ops = {
+ CHIP_NAME("VIA VX900 Chipset")
+ .enable_dev = enable_dev,
+};
+
diff --git a/src/northbridge/via/vx900/raminit.h b/src/northbridge/via/vx900/raminit.h
new file mode 100644
index 0000000..6268070
--- /dev/null
+++ b/src/northbridge/via/vx900/raminit.h
@@ -0,0 +1,77 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef RAMINIT_VX900_H
+#define RAMINIT_VX900_H
+
+#include <devices/dram/dram.h>
+
+/* The maximum number of DIMM slots that the VX900 supports */
+#define VX900_MAX_DIMM_SLOTS 2
+
+#define VX900_MAX_MEM_RANKS 4
+
+
+#define SPD_END_LIST 0xff
+
+typedef struct dimm_layout_st
+{
+ /* The address of the DIMM on the SMBUS *
+ * 0xFF to terminate the array*/
+ u8 spd_addr[VX900_MAX_DIMM_SLOTS + 1];
+} dimm_layout;
+
+typedef struct dimm_info_st
+{
+ dimm_attr dimm[VX900_MAX_DIMM_SLOTS];
+} dimm_info;
+
+typedef struct mem_rank_st {
+ u16 start_addr;
+ u16 end_addr;
+}mem_rank;
+
+typedef struct rank_layout_st {
+ u32 phys_rank_size[VX900_MAX_MEM_RANKS];
+ mem_rank virt[VX900_MAX_MEM_RANKS];
+} rank_layout;
+
+typedef struct pci_reg8_st {
+ u8 addr;
+ u8 val;
+} pci_reg8;
+
+typedef u8 timing_dly[8];
+
+typedef struct delay_range_st {
+ timing_dly low;
+ timing_dly avg;
+ timing_dly high;
+} delay_range;
+
+typedef struct vx900_delay_calib_st {
+ delay_range rx_dq_cr;
+ delay_range rx_dqs;
+ delay_range tx_dq;
+ delay_range tx_dqs;
+} vx900_delay_calib;
+
+void vx900_init_dram_ddr3(const dimm_layout *dimms);
+
+#endif /* RAMINIT_VX900_H */
diff --git a/src/northbridge/via/vx900/raminit_ddr3.c b/src/northbridge/via/vx900/raminit_ddr3.c
new file mode 100644
index 0000000..fb1618f
--- /dev/null
+++ b/src/northbridge/via/vx900/raminit_ddr3.c
@@ -0,0 +1,1053 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011-2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+
+#include "early_vx900.h"
+#include "raminit.h"
+
+#include <string.h>
+#include <console/console.h>
+#include <device/pci_ids.h>
+
+#include <delay.h>
+
+#define min(a,b) a<b?a:b
+#define max(a,b) a>b?a:b
+
+#define MCU PCI_DEV(0, 0, 3)
+
+
+/* FIXME: Really Alex, is this all you can come up with? */
+void udelay(unsigned usecs)
+{
+ int i;
+ for(i = 0; i < usecs; i++)
+ inb(0x80);
+}
+
+/* Registers 0x78 -> 0x7f contain calibration the settings for DRAM IO timing
+ * The dataset in these registers is selected from 0x70.
+ * Once the correct dataset is selected the delays can be altered.
+ * mode refers to TxDQS, TxDQ, RxDQS, or RxCR
+ * setting refers to either manual, average, upper bound, or lower bound
+ */
+#define VX900_CALIB_TxDQS 0
+#define VX900_CALIB_TxDQ 1
+#define VX900_CALIB_RxDQS 2
+#define VX900_CALIB_RxDQ_CR 3
+
+#define VX900_CALIB_AVERAGE 0
+#define VX900_CALIB_LOWER 1
+#define VX900_CALIB_UPPER 2
+#define VX900_CALIB_MANUAL 4
+
+static void vx900_delay_calib_mode_select(u8 delay_type, u8 bound)
+{
+ /* Which calibration setting */
+ u8 reg8 = (delay_type & 0x03) << 2;
+ /* Upper, lower, average, or manual setting */
+ reg8 |= (bound & 0x03);
+ pci_write_config8(MCU, 0x70, reg8);
+}
+
+static void vx900_read_0x78_0x7f(timing_dly dly)
+{
+ *((u32*) (&(dly[0]))) = pci_read_config32(MCU, 0x78);
+ *((u32*) (&(dly[4]))) = pci_read_config32(MCU, 0x7c);
+}
+
+static void vx900_write_0x78_0x7f(const timing_dly dly)
+{
+ pci_write_config32(MCU, 0x78, *((u32*) (&(dly[0]))) );
+ pci_write_config32(MCU, 0x7c, *((u32*) (&(dly[4]))) );
+}
+
+static void vx900_read_delay_range(delay_range *d_range, u8 mode)
+{
+ vx900_delay_calib_mode_select(mode, VX900_CALIB_LOWER);
+ vx900_read_0x78_0x7f(d_range->low);
+ vx900_delay_calib_mode_select(mode, VX900_CALIB_AVERAGE);
+ vx900_read_0x78_0x7f(d_range->avg);
+ vx900_delay_calib_mode_select(mode, VX900_CALIB_UPPER);
+ vx900_read_0x78_0x7f(d_range->high);
+}
+
+static void dump_delay(const timing_dly dly)
+{
+ u8 i;
+ for(i = 0; i < 8; i ++)
+ {
+ printram(" %.2x", dly[i]);
+ }
+ printram("\n");
+}
+
+static void dump_delay_range(const delay_range d_range)
+{
+ printram("Lower limit: ");
+ dump_delay(d_range.low);
+ printram("Average: ");
+ dump_delay(d_range.avg);
+ printram("Upper limit: ");
+ dump_delay(d_range.high);
+}
+
+/* These are some "safe" values that can be used for memory initialization.
+ * Some will stay untouched, and others will be overwritten later on
+ * YOU REALLY NEED THE DATASHEET TO UNDERSTAND THESE !!! */
+static pci_reg8 mcu_init_config[] = {
+ {0x40, 0x01}, /* Virtual rank 0 ending address = 64M - 1 */
+ {0x41, 0x00}, {0x42, 0x00}, {0x43, 0x00}, /* Virtual Ranks ending */
+ {0x48, 0x00}, /* Virtual rank 0 starting address = 0 */
+ {0x49, 0x00}, {0x4a, 0x00}, {0x4b, 0x00}, /* Virtual Ranks beginning */
+ {0x50, 0xd8}, /* Set ranks 0-3 to 11 col bits, 16 row bits */
+ {0x52, 0x33}, /* Map BA0 to A17, BA1 to A18 */
+ {0x53, 0x5b}, /* Map BA2 to A19, FIXME: check RA0/RA1 */
+ /* Disable all virtual ranks */
+ {0x54, 0x00}, {0x55, 0x00}, {0x56, 0x00}, {0x57, 0x00},
+ /* Disable rank interleaving in ranks 0-3 */
+ {0x58, 0x00}, {0x59, 0x00}, {0x5a, 0x00}, {0x5b, 0x00},
+ {0x6c, 0xA0}, /* Memory type: DDR3, VDIMM: 1.5V, 64-bit DRAM */
+ {0xc4, 0x80}, /* Enable 8 memory banks */
+ {0xc6, 0x80}, /* Minimum latency from self-refresh. Bit [7] must be 1 */
+ //{0xc8, 0x80}, /* Enable automatic triggering of short ZQ calibration */
+ {0x99, 0xf0}, /* Power Management and Bypass Reorder Queue */
+ /* Enable differential DQS; MODT assertion values suggested in DS */
+ {0x9e, 0xa1}, {0x9f, 0x51},
+ /* DQ/DQM Duty Control - Do not put any extra delays*/
+ {0xe9, 0x00}, {0xea, 0x00}, {0xeb, 0x00}, {0xec, 0x00},
+ {0xed, 0x00}, {0xee, 0x00}, {0xef, 0x00},
+ {0xfc, 0x00}, {0xfd, 0x00}, {0xfe, 0x00}, {0xff, 0x00},
+ /* The following parameters we may or may not change */
+ {0x61, 0x2e}, /* DRAMC Pipeline Control */
+ {0x77, 0x10}, /* MDQS Output Control */
+
+ /* The following are parameters we'll most likely never change again */
+ {0x60, 0xf4}, /* DRAM Pipeline Turn-Around Setting */
+ {0x65, 0x49}, /* DRAM Arbitration Bandwidth Timer - I */
+ {0x66, 0x80}, /* DRAM Queue / Arbitration */
+ {0x69, 0xc6}, /* Bank Interleave Control */
+ {0x6a, 0xfc}, /* DRAMC Request Reorder Control */
+ {0x6e, 0x38}, /* Burst lenght: 8, burst-chop: enable */
+ {0x73, 0x04}, /* Close All Pages Threshold */
+
+ /* The following need to be dynamically asserted */
+ /* See: check_special_registers.c */
+ {0x74, 0xa0}, /* Yes, same 0x74; add one more T */
+ {0x76, 0x60}, /* Write Data Phase Control */
+
+};
+
+/* This table keeps the driving strength control setting that we can safely use
+ * doring initialization. */
+static pci_reg8 mcu_drv_ctrl_config[] = {
+ {0xd3, 0x03}, /* Enable auto-compensation circuit for ODT strength */
+ {0xd4, 0x80}, /* Set internal ODT to dynamically turn on or off */
+ {0xd6, 0x20}, /* Enable strong driving for MA and DRAM commands*/
+ {0xd0, 0x88}, /* (ODT) Strength ?has effect? */
+ {0xe0, 0x88}, /* DRAM Driving – Group DQS (MDQS) */
+ {0xe1, 0x00}, /* Disable offset mode for driving strength control */
+ {0xe2, 0x88}, /* DRAM Driving – Group DQ (MD, MDQM) */
+ {0xe4, 0xcc}, /* DRAM Driving – Group CSA (MCS, MCKE, MODT) */
+ {0xe8, 0x88}, /* DRAM Driving – Group MA (MA, MBA, MSRAS, MSCAS, MSWE)*/
+ {0xe6, 0xff}, /* DRAM Driving – Group DCLK0 (DCLK[2:0] for DIMM0) */
+ {0xe7, 0xff}, /* DRAM Driving – Group DCLK1 (DCLK[5:3] for DIMM1) */
+ {0xe4, 0xcc}, /* DRAM Driving – Group CSA (MCS, MCKE, MODT)*/
+ {0x91, 0x08}, /* MCLKO Output Phase Delay - I */
+ {0x92, 0x08}, /* MCLKO Output Phase Delay - II */
+ {0x93, 0x16}, /* CS/CKE Output Phase Delay */
+ {0x95, 0x16}, /* SCMD/MA Output Phase Delay */
+ {0x9b, 0x3f}, /* Memory Clock Output Enable */
+};
+
+static void vx900_dram_write_init_config(void)
+{
+ size_t i;
+ for(i = 0; i < (sizeof(mcu_init_config)/sizeof(pci_reg8)); i++)
+ {
+ pci_write_config8(MCU, mcu_init_config[i].addr,
+ mcu_init_config[i].val);
+ }
+}
+
+static void dram_find_spds_ddr3(const dimm_layout *addr, dimm_info *dimm)
+{
+ size_t i = 0;
+ int dimms = 0;
+ do {
+ spd_raw_data spd;
+ spd_read(addr->spd_addr[i], spd);
+ spd_decode_ddr3(&dimm->dimm[i], spd);
+ if(dimm->dimm[i].dram_type != DRAM_TYPE_DDR3) continue;
+ dimms++;
+ dram_print_spd_ddr3(&dimm->dimm[i]);
+ } while(addr->spd_addr[++i] != SPD_END_LIST
+ && i < VX900_MAX_DIMM_SLOTS);
+
+ if(!dimms)
+ die("No DIMMs were found");
+}
+
+static void dram_find_common_params(const dimm_info *dimms, ramctr_timing *ctrl)
+{
+ size_t i, valid_dimms;
+ memset(ctrl, 0, sizeof(ramctr_timing));
+ ctrl->cas_supported = 0xff;
+ valid_dimms = 0;
+ for(i = 0; i < VX900_MAX_DIMM_SLOTS; i++)
+ {
+ const dimm_attr *dimm = &dimms->dimm[i];
+ if(dimm->dram_type == DRAM_TYPE_UNDEFINED) continue;
+ valid_dimms++;
+
+ if(valid_dimms == 1) {
+ /* First DIMM defines the type of DIMM */
+ ctrl->dram_type = dimm->dram_type;
+ } else {
+ /* Check if we have mismatched DIMMs */
+ if(ctrl->dram_type != dimm->dram_type)
+ die("Mismatched DIMM Types");
+ }
+ /* Find all possible CAS combinations */
+ ctrl->cas_supported &= dimm->cas_supported;
+
+ /* Find the smallest common latencies supported by all DIMMs */
+ ctrl->tCK = max(ctrl->tCK, dimm->tCK );
+ ctrl->tAA = max(ctrl->tAA, dimm->tAA );
+ ctrl->tWR = max(ctrl->tWR, dimm->tWR );
+ ctrl->tRCD = max(ctrl->tRCD, dimm->tRCD);
+ ctrl->tRRD = max(ctrl->tRRD, dimm->tRRD);
+ ctrl->tRP = max(ctrl->tRP, dimm->tRP );
+ ctrl->tRAS = max(ctrl->tRAS, dimm->tRAS);
+ ctrl->tRC = max(ctrl->tRC, dimm->tRC );
+ ctrl->tRFC = max(ctrl->tRFC, dimm->tRFC);
+ ctrl->tWTR = max(ctrl->tWTR, dimm->tWTR);
+ ctrl->tRTP = max(ctrl->tRTP, dimm->tRTP);
+ ctrl->tFAW = max(ctrl->tFAW, dimm->tFAW);
+
+ }
+
+ if(!ctrl->cas_supported) die("Unsupported DIMM combination. "
+ "DIMMS do not support common CAS latency");
+ if(!valid_dimms) die("No valid DIMMs found");
+}
+
+static void vx900_dram_phys_bank_range(const dimm_info *dimms,
+ rank_layout *ranks)
+{
+ size_t i;
+ //u8 reg8;
+ for(i = 0; i < VX900_MAX_DIMM_SLOTS; i ++)
+ {
+ if(dimms->dimm[i].dram_type == DRAM_TYPE_UNDEFINED)
+ continue;
+ u8 nranks = dimms->dimm[i].ranks;
+ if(nranks > 2)
+ die("Found DIMM with more than two ranks, which is not "
+ "supported by this chipset");
+ u32 size = dimms->dimm[i].size;
+ if(nranks == 2) {
+ /* Each rank holds half the capacity of the DIMM */
+ size >>= 1;
+ ranks->phys_rank_size[i<<1] = size;
+ ranks->phys_rank_size[(i<<1) | 1] = size;
+ } else {
+ /* Otherwise, everything is held in the first bank */
+ ranks->phys_rank_size[i<<1] = size;
+ ranks->phys_rank_size[(i<<1) | 1] = 0;;
+ }
+ }
+}
+
+static void vx900_dram_driving_ctrl(const dimm_info *dimm)
+{
+ size_t i, ndimms;
+ u8 val;
+
+ /* For ODT range selection, datasheet recommends
+ * when 1 DIMM present: 60 Ohm
+ * when 2 DIMMs present: 120 Ohm */
+ ndimms = 0;
+ for(i = 0; i < VX900_MAX_DIMM_SLOTS; i++) {
+ if(dimm->dimm[i].dram_type == DRAM_TYPE_DDR3) ndimms++;
+ }
+ val = (ndimms > 1) ? 0x0 : 0x1;
+ pci_write_config8(MCU, 0xd5, val << 2);
+
+
+ /* FIXME: Assert dynamically based on dimm config */
+ /* DRAM ODT Lookup Table*/
+ pci_write_config8(MCU, 0x9c, 0xe4);
+
+ for(i = 0; i < (sizeof(mcu_drv_ctrl_config)/sizeof(pci_reg8)); i++)
+ {
+ pci_write_config8(MCU, mcu_drv_ctrl_config[i].addr,
+ mcu_drv_ctrl_config[i].val);
+ }
+}
+
+static void vx900_clear_vr_map(void)
+{
+ /* Disable all ranks */
+ pci_write_config16(MCU, 0x54, 0x0000);
+}
+
+static void vx900_pr_map_all_vr3(void)
+{
+ /* Enable all ranks and set them to VR3 */
+ pci_write_config16(MCU, 0x54, 0xbbbb);
+}
+/* Map physical rank pr to virtual rank vr */
+static void vx900_map_pr_vr(u8 pr, u8 vr)
+{
+ pr &= 0x3; vr &= 0x3;
+ /* Enable rank (bit [3], and set the VR number bits [1:0] */
+ u16 val = 0x8 | vr;
+ /* Now move the value to the appropriate PR */
+ val <<= (pr * 4);
+ pci_mod_config16(MCU, 0x54, 0xf << (pr * 4), val);
+ printram("Mapping PR %u to VR %u\n", pr, vr);
+}
+
+static u8 vx900_get_CWL(u8 CAS)
+{
+ /* Get CWL based on CAS using the following rule:
+ * _________________________________________
+ * CAS: | 4T | 5T | 6T | 7T | 8T | 9T | 10T | 11T |
+ * CWL: | 5T | 5T | 5T | 6T | 6T | 7T | 7T | 8T |
+ */
+ static const u8 cas_cwl_map[] = {5, 5, 5, 6, 6, 7, 7, 8};
+ if(CAS > 11) return 8;
+ return cas_cwl_map[CAS - 4];
+}
+
+static void vx900_dram_timing(ramctr_timing *ctrl)
+{
+ /* Here we are calculating latencies, and writing them to the appropiate
+ * registers. Some registers do not take latencies from 0T, for example:
+ * CAS: 000 = 4T, 001 = 5T, 010 = 6T, etc
+ * In this example we subtract 4T from the result for CAS: (val - 4)
+ * The & 0x07 after (val - T0) just makes sure that, no matter what
+ * crazy thing may happen, we do not write outside the bits allocated
+ * in the register */
+ u8 reg8, val, tFAW, tRRD;
+ u32 val32;
+
+ /* Maximum supported DDR3 frequency is 533MHz (DDR3 1066)
+ * so make sure we cap it if we have faster DIMMs */
+ if(ctrl->tCK < TCK_533MHZ) ctrl->tCK = TCK_533MHZ;
+ val32 = (1000 << 8) / ctrl->tCK;
+ printram("Selected DRAM frequency: %u MHz\n", val32);
+
+ /* Now find the right DRAM frequency setting,
+ * and align it to the closest JEDEC standard frequency */
+ if(ctrl->tCK <= TCK_533MHZ) {val = 0x07; ctrl->tCK = TCK_533MHZ;}
+ else if(ctrl->tCK <= TCK_400MHZ) {val = 0x06; ctrl->tCK = TCK_400MHZ;}
+ else if(ctrl->tCK <= TCK_333MHZ) {val = 0x05; ctrl->tCK = TCK_333MHZ;}
+ else if(ctrl->tCK <= TCK_266MHZ) {val = 0x04; ctrl->tCK = TCK_266MHZ;}
+
+ /* Find CAS and CWL latencies */
+ val = (ctrl->tAA + ctrl->tCK -1) / ctrl->tCK;
+ printram("Minimum CAS latency : %uT\n", val);
+ /* Find lowest supported CAS latency that satisfies the minimum value */
+ while( !((ctrl->cas_supported >> (val-4))&1)
+ && (ctrl->cas_supported >> (val-4))) {
+ val++;
+ }
+ /* Is CAS supported */
+ if(!(ctrl->cas_supported & (1 << (val-4))) )
+ printram("CAS not supported\n");
+ printram("Selected CAS latency : %uT\n", val);
+ ctrl->CAS = val;
+ ctrl->CWL = vx900_get_CWL(ctrl->CAS);
+ printram("Selected CWL latency : %uT\n", ctrl->CWL);
+ /* Write CAS and CWL */
+ reg8 = ( ((ctrl->CWL - 4) &0x07) << 4 ) | ((ctrl->CAS - 4) & 0x07);
+ pci_write_config8(MCU, 0xc0, reg8);
+
+ /* Find tRCD */
+ val = (ctrl->tRCD + ctrl->tCK -1) / ctrl->tCK;
+ printram("Selected tRCD : %uT\n", val);
+ reg8 = ((val-4) & 0x7) << 4;
+ /* Find tRP */
+ val = (ctrl->tRP + ctrl->tCK -1) / ctrl->tCK;
+ printram("Selected tRP : %uT\n", val);
+ reg8 |= ((val-4) & 0x7);
+ pci_write_config8(MCU, 0xc1, reg8);
+
+ /* Find tRAS */
+ val = (ctrl->tRAS + ctrl->tCK -1) / ctrl->tCK;
+ printram("Selected tRAS : %uT\n", val);
+ reg8 = ((val-15) & 0x7) << 4;
+ /* Find tWR */
+ ctrl->WR = (ctrl->tWR + ctrl->tCK -1) / ctrl->tCK;
+ printram("Selected tWR : %uT\n", ctrl->WR);
+ reg8 |= ((ctrl->WR-4) & 0x7);
+ pci_write_config8(MCU, 0xc2, reg8);
+
+ /* Find tFAW */
+ tFAW = (ctrl->tFAW + ctrl->tCK -1) / ctrl->tCK;
+ printram("Selected tFAW : %uT\n", tFAW);
+ /* Find tRRD */
+ tRRD = (ctrl->tRRD + ctrl->tCK -1) / ctrl->tCK;
+ printram("Selected tRRD : %uT\n", tRRD);
+ val = tFAW - 4*tRRD; /* number of cycles above 4*tRRD */
+ reg8 = ((val-0) & 0x7) << 4;
+ reg8 |= ((tRRD-2) & 0x7);
+ pci_write_config8(MCU, 0xc3, reg8);
+
+ /* Find tRTP */
+ val = (ctrl->tRTP + ctrl->tCK -1) / ctrl->tCK;
+ printram("Selected tRTP : %uT\n", val);
+ reg8 = ((val & 0x3) << 4);
+ /* Find tWTR */
+ val = (ctrl->tWTR + ctrl->tCK -1) / ctrl->tCK;
+ printram("Selected tWTR : %uT\n", val);
+ reg8 |= ((val - 2) & 0x7);
+ pci_mod_config8(MCU, 0xc4, 0x3f, reg8);
+
+ /* DRAM Timing for All Ranks - VI
+ * [7:6] CKE Assertion Minimum Pulse Width
+ * We probably don't want to mess with this just yet.
+ * [5:0] Refresh-to-Active or Refresh-to-Refresh (tRFC)
+ * tRFC = (30 + 2 * [5:0])T
+ * Since we previously set RxC4[7]
+ */
+ reg8 = pci_read_config8(MCU, 0xc5);
+ val = (ctrl->tRFC + ctrl->tCK -1) / ctrl->tCK;
+ printram("Minimum tRFC : %uT\n", val);
+ if(val < 30) {
+ val = 0;
+ } else {
+ val = (val -30 + 1 ) / 2;
+ }
+ ;
+ printram("Selected tRFC : %uT\n", 30 + 2 * val);
+ reg8 |= (val & 0x3f);
+ pci_write_config8(MCU, 0xc5, reg8);
+
+ /* Where does this go??? */
+ val = (ctrl->tRC + ctrl->tCK -1) / ctrl->tCK;
+ printram("Required tRC : %uT\n", val);
+}
+
+static void vx900_dram_freq(ramctr_timing *ctrl)
+{
+ u8 val;
+
+ /* Program the DRAM frequency */
+
+ /* Step 1 - Reset the PLL */
+ pci_mod_config8(MCU, 0x90, 0x00, 0x0f);
+ /* Wait at least 10 ns; VIA code delays by 640us */
+ udelay(640);
+
+ /* Step 2 - Set target frequency */
+ if(ctrl->tCK <= TCK_533MHZ) {val = 0x07; ctrl->tCK = TCK_533MHZ;}
+ else if(ctrl->tCK <= TCK_400MHZ) {val = 0x06; ctrl->tCK = TCK_400MHZ;}
+ else if(ctrl->tCK <= TCK_333MHZ) {val = 0x05; ctrl->tCK = TCK_333MHZ;}
+ else /*ctrl->tCK <= TCK_266MHZ*/ {val = 0x04; ctrl->tCK = TCK_266MHZ;}
+ /* Restart the PLL with the desired frequency */
+ pci_mod_config8(MCU, 0x90, 0x0f, val);
+
+ /* Step 3 - Wait for PLL to stabilize */
+ udelay(2000);
+
+ /* Step 4 - Reset the DLL - Clear [7,4]*/
+ pci_mod_config8(MCU, 0x6b, 0x90, 0x00);
+ udelay(2000);
+
+ /* Step 5 - Enable the DLL - Set bits [7,4] to 01b*/
+ pci_mod_config8(MCU, 0x6b, 0x00, 0x10);
+ udelay(2000);
+
+ /* Step 6 - Start DLL Calibration - Set bit [7] */
+ pci_mod_config8(MCU, 0x6b, 0x00, 0x80);
+ udelay(5);
+
+ /* Step 7 - Finish DLL Calibration - Clear bit [7]*/
+ pci_mod_config8(MCU, 0x6b, 0x80, 0x00);
+
+ /* Step 8 - If we have registered DIMMs, we need to set bit[0] */
+ if(dimm_is_registered(ctrl->dram_type)){
+ printram("Enabling RDIMM support in memory controller\n");
+ pci_mod_config8(MCU, 0x6c, 0x00, 0x01);
+ }
+}
+
+/* The VX900 can send the MRS commands directly through hardware */
+void vx900_dram_ddr3_do_hw_mrs(u8 ma_swap, u8 rtt_nom,
+ u8 ods, u8 rtt_wr, u8 srt, u8 asr);
+/*static*/ void vx900_dram_ddr3_do_hw_mrs(u8 ma_swap, u8 rtt_nom,
+ u8 ods, u8 rtt_wr, u8 srt, u8 asr)
+{
+ u8 reg8 = 0;
+ u32 reg32;
+ if(asr) reg8 |= (1 << 0);
+ if(srt) reg8 |= (1 << 1);
+ reg8 |= ((rtt_wr & 0x03) << 4);
+ pci_write_config8(MCU, 0xcd, reg8);
+ reg8 = 1;
+ if(ma_swap) reg8 |= (1 << 1);
+ reg8 |= ((ods & 0x03) << 2);
+ reg8 |= ((rtt_nom & 0x7) << 4);
+ pci_write_config8(MCU, 0xcc, reg8);
+ reg32=0;
+ while(pci_read_config8(MCU, 0xcc) & 1) reg32++;
+ printram(" Waited %u PCI cycles for HW MRS\n", reg32);
+}
+#include "forgotten.h"
+#include "forgotten.c"
+
+static void vx900_dram_send_soft_mrs(u8 type, u16 cmd)
+{
+ u32 addr;
+ /* Set Fun3_RX6B[2:0] to 011b (MSR Enable). */
+ pci_mod_config8(MCU, 0x6b, 0x07, (3<<0));
+ /* Find the address corresponding to the MRS */
+ addr = vx900_get_mrs_addr(type, cmd);
+ //printram("MRS CPU addr: %.8x\n", addr);
+ /* Execute the MRS */
+ volatile_read(addr);
+ /* Set Fun3_Rx6B[2:0] to 000b (Normal SDRAM Mode). */
+ pci_mod_config8(MCU, 0x6b, 0x07, 0x00);
+}
+
+static void vx900_dram_ddr3_dimm_init(const ramctr_timing *ctrl,
+ const rank_layout *ranks)
+{
+ size_t i;
+
+ /* Set BA[0/1/2] to [A17/18/19] */
+ pci_write_config16(MCU, 0x52, 0x5b33);
+
+ /* Step 01 - Set Fun3_Rx6E[5] to 1b to support burst length. */
+ pci_mod_config8(MCU, 0x6e, 0, 1<<5);
+ /* Step 02 - Set Fun3_RX69[0] to 0b (Disable Multiple Page Mode). */
+ pci_mod_config8(MCU, 0x69, (1<<0), 0x00);
+ /* And set [7:6] to 10b ?*/
+ pci_write_config8(MCU, 0x69, 0x87);
+
+ /* Step 03 - Set the target physical rank to virtual rank0 and other
+ * ranks to virtual rank3. */
+ vx900_pr_map_all_vr3();
+
+ /* Step 04 - Set Fun3_Rx50 to D8h. */
+ pci_write_config8(MCU, 0x50, 0xd8);
+ /* Step 05 - Set Fun3_RX6B[5] to 1b to de-assert RESET# and wait for at
+ * least 500 us. */
+ pci_mod_config8(MCU, 0x6b, 0x00, (1<<5) );
+ udelay(500);
+
+ /* Step 6 -> 15 - Set the target physical rank to virtual rank 0 and
+ * other ranks to virtual rank 3.
+ * Repeat Step 6 to 14 for every rank present, then jump to Step 16. */
+ for(i = 0; i < VX900_MAX_MEM_RANKS; i++)
+ {
+ if(ranks->phys_rank_size[i] == 0) continue;
+ printram("Initializing rank %lu\n", i);
+
+ /* Set target physical rank to virtual rank 0
+ * other ranks to virtual rank 3*/
+ vx900_map_pr_vr(i, 0);
+
+#define USE_HW_INIT_SEQUENCE 1
+#if USE_HW_INIT_SEQUENCE
+
+ /* FIXME: Is this needed on HW init? */
+ pci_mod_config8(MCU, 0x6b, 0x07, 0x01); /* Enable NOP */
+ volatile_read(0x0); /* Do NOP */
+ pci_mod_config8(MCU, 0x6b, 0x07, 0x03); /* MSR Enable */
+
+ /* FIXME: Values dependent on DIMM setup
+ * This works for 1 DIMM
+ * See init_dram_by_rank.c and get_basic_information.c
+ * in the VIA provided code */
+ const u8 rtt_nom = DDR3_MR1_RTT_NOM_RZQ2;
+ const u8 ods = DDR3_MR1_ODS_RZQ6;
+ const u8 rtt_wr = DDR3_MR2_RTT_WR_OFF;
+
+ printram("Using Hardware method\n");
+ /* FIXME: MA swap dependent on module */
+ vx900_dram_ddr3_do_hw_mrs(0, rtt_nom, ods, rtt_wr, 0, 0);
+
+ /* Normal SDRAM Mode */
+ pci_mod_config8(MCU, 0x6b, 0x07, 0x00);
+
+#else /* USE_HW_INIT_SEQUENCE */
+ printram("Using software method\n");
+ vx900_dram_ddr3_init_rank(MCU, ctrl, i);
+#endif /* USE_HW_INIT_SEQUENCE */
+ /* Step 15, set the rank to virtual rank 3*/
+ vx900_map_pr_vr(i, 3);
+ }
+
+ /* Step 16 – Set Fun3_Rx6B[2:0] to 000b (Normal SDRAM Mode). */
+ pci_mod_config8(MCU, 0x6b, 0x07, 0x00);
+
+ /* Set BA[0/1/2] to [A13/14/15] */
+ pci_mod_config16(MCU, 0x52, 0x0fff, 0x0911);
+
+ /* Step 17 – Set Fun3_Rx69[0] to 1b (Enable Multiple Page Mode). */
+ pci_mod_config8(MCU, 0x69, 0x00, (1<<0) );
+
+ printram("DIMM initialization sequence complete\n");
+}
+
+
+static void vx900_rx_capture_range_calib(void)
+{
+ u8 reg8;
+ u16 cmd;
+ const u32 cal_addr = 0x20;
+
+ /* Set IO calibration address */
+ pci_mod_config16(MCU, 0x8c , 0xfff0, cal_addr&(0xfff0));
+ /* Data pattern must be 0x00 for this calibration
+ * See paragraph describing Rx8e */
+ pci_write_config8(MCU, 0x8e, 0x00);
+
+ /* Precharge all */
+ pci_mod_config8(MCU, 0x06b, 0x07, 0x02);
+ volatile_read(0x0);
+ udelay(1000);
+
+ /* Enable read leveling: Set D0F3Rx71[7]=1
+ * Set return data format: Clear D0F3Rx71[6]=0 */
+ pci_mod_config8(MCU, 0x71, 0x40, 0x80);
+
+ /* Put DRAM in read leveling mode */
+ cmd = ddr3_get_mr3(1);
+ vx900_dram_send_soft_mrs(3, cmd);
+
+ /* Data pattern must be 0x00 for this calibration
+ * See paragraph describing Rx8e */
+ pci_write_config8(MCU, 0x8e, 0x00);
+ /* Trigger calibration */
+ reg8 = 0xa0;
+ pci_write_config8(MCU, 0x71, reg8);
+
+ /* Wait for it */
+ while(pci_read_config8(MCU, 0x71) & 0x10) cmd++;
+ printram("RX capture range calibration took %u PCI cycles\n", cmd);
+
+ /* Disable read leveling, and put dram in normal operation mode */
+ cmd = ddr3_get_mr3(0);
+ vx900_dram_send_soft_mrs(3, cmd);
+
+ /* Disable read leveling: Set D0F3Rx71[7]=0 */
+ pci_mod_config8(MCU, 0x71, 1<<7, 0);
+}
+
+static void vx900_rx_dqs_delay_calib(void)
+{
+ u16 cmd;
+ const u32 cal_addr = 0x30;
+
+ /* We need to disable refresh commands so that they don't interfere */
+ const u8 ref_cnt = pci_read_config8(MCU, 0xc7);
+ pci_write_config8(MCU, 0xc7, 0);
+ /* Set IO calibration address */
+ pci_mod_config16(MCU, 0x8c , 0xfff0, cal_addr&(0xfff0));
+ /* Data pattern must be 0x00 for this calibration
+ * See paragraph describing Rx8e */
+ pci_write_config8(MCU, 0x8e, 0x00);
+
+ /* Precharge all */
+ pci_mod_config8(MCU, 0x06b, 0x07, 0x02);
+ volatile_read(0x0);
+ udelay(1000);
+
+ /* Enable read leveling: Set D0F3Rx71[7]=1
+ * Set return data format: Clear D0F3Rx71[6]=0
+ * Set RxDQS to use calibration setting - Clear Rx71[2] and Rx71[0] */
+ pci_mod_config8(MCU, 0x71, 0x45, 0x80);
+
+ /* Put DRAM in read leveling mode (enable MPR flow) */
+ cmd = ddr3_get_mr3(1);
+ vx900_dram_send_soft_mrs(3, cmd);
+
+ /* From VIA code; Undocumented
+ * In theory this enables MODT[3:0] to be asserted*/
+ pci_mod_config8(MCU, 0x9e, 0, 0x80);
+
+ /* Trigger calibration: Set D0F3Rx71[1:0]=10b */
+ pci_mod_config8(MCU, 0x71, 0x03, 0x02);
+
+ /* Wait for calibration to complete */
+ while( pci_read_config8(MCU, 0x71) & 0x02 );
+
+ /* Put DRAM in normal mode (disable MPR flow) */
+ cmd = ddr3_get_mr3(0);
+ vx900_dram_send_soft_mrs(3, cmd);
+
+ /* Disable read leveling: Set D0F3Rx71[7]=0 */
+ pci_mod_config8(MCU, 0x71, 1<<7, 0);
+
+ /* Restore the refresh counter*/
+ //pci_write_config8(MCU, 0xc7, ref_cnt);
+ if(ref_cnt);
+
+ /* FIXME: should we save it before, or should we just set it as is */
+ pci_write_config16(MCU, 0x52, 0x5911);
+}
+
+static void vx900_tx_dqs_trigger_calib(u8 pattern)
+{
+ u32 i;
+ /* Data pattern for calibration */
+ pci_write_config8(MCU, 0x8e, pattern);
+ /* Trigger calibration */
+ pci_mod_config8(MCU, 0x75, 0, 0x20);
+ /* Wait for calibration */
+ i = 0;
+ while(pci_read_config8(MCU, 0x75) & 0x20) i++;
+ printram(" Tx DQS calib took %u PCI cycles\n", i);
+}
+static void vx900_tx_dqs_delay_calib(void)
+{
+ const u32 cal_addr = 0x00;
+ /* Set IO calibration address */
+ pci_mod_config16(MCU, 0x8c , 0xfff0, cal_addr&(0xfff0));
+ /* Set circuit to use calibration results - Clear Rx75[0]*/
+ pci_mod_config8(MCU, 0x75, 0x01, 0);
+ /* Run calibration with first data pattern*/
+ vx900_tx_dqs_trigger_calib(0x5a);
+ /* Run again with different pattern */
+ vx900_tx_dqs_trigger_calib(0xa5);
+}
+
+static void vx900_tx_dq_delay_calib(void)
+{
+ int i = 0;
+ /* Data pattern for calibration */
+ pci_write_config8(MCU, 0x8e, 0x5a);
+ /* Trigger calibration */
+ pci_mod_config8(MCU, 0x75, 0, 0x02);
+ /* Wait for calibration */
+ while(pci_read_config8(MCU, 0x75) & 0x02) i++;
+ printram("TX DQ calibration took %u PCI cycles\n", i);
+}
+
+static void vx900_rxdqs_adjust(delay_range *dly)
+{
+ /* Adjust Rx DQS delay after calibration has been run. This is
+ * recommended by VIA, but no explanation was provided as to why */
+ size_t i;
+ for(i = 0; i < 8; i++)
+ {
+ if(dly->low[i] < 3)
+ {
+ if(i == 2 || i== 4) dly->low[i] += 4;
+ else dly->avg[i] += 3;
+
+ }
+
+ if(dly->high[i] > 0x38) dly->avg[i] -= 6;
+ else if(dly->high[i] > 0x30) dly->avg[i] -= 4;
+
+ if(dly->avg[i] > 0x20) dly->avg[i] = 0x20;
+ }
+
+ /* Put Rx DQS delay into manual mode (Set Rx[2,0] to 01) */
+ pci_mod_config8(MCU, 0x71, 0x05, 0x01);
+ /* Now write the new settings */
+ vx900_write_0x78_0x7f(dly->avg);
+}
+
+static void vx900_dram_calibrate_delays(const ramctr_timing *ctrl,
+ const rank_layout *ranks)
+{
+ timing_dly dly;
+ size_t i;
+ u8 val;
+ vx900_delay_calib delay_cal;
+ memset(&delay_cal, 0, sizeof(delay_cal));
+ printram("Starting delay calibration\n");
+
+ /**** Read delay control ****/
+ /* MD Input Data Push Timing Control;
+ * use values recommended in datasheet
+ * Setting this too low causes the Rx window to move below the range we
+ * need it so we can capture it with Rx_78_7f
+ * This causes Rx calibrations to be too close to 0, and Tx
+ * calibrations will fail.
+ * Setting this too high causes the window to move above the range.
+ */
+ if (ctrl->tCK <= TCK_533MHZ) val = 2;
+ else if (ctrl->tCK <= TCK_333MHZ) val = 1;
+ else val = 0;
+ val ++; /* FIXME: vendor BIOS sets this to 3 */
+ pci_mod_config8(MCU, 0x74, (0x03 << 1), ((val & 0x03) << 1) );
+
+ /* FIXME: The vendor BIOS increases the MD input delay - WHY ? */
+ pci_mod_config8(MCU, 0xef, (3<<4), 3<<4);
+
+
+ /**** Write delay control ****/
+ /* FIXME: The vendor BIOS does this, but WHY?
+ * Early DQ/DQS for write cycles */
+ pci_mod_config8(MCU, 0x76, (3<<2), 2<<2);
+ /* FIXME: The vendor BIOS does this - Output preamble ?*/
+ pci_write_config8(MCU, 0x77, 0x10);
+
+ /* FIXME: Vendor BIOS goes in with
+ * 8 page registers
+ * multiple page mode
+ * High Priority Refresh request
+ * -- WHY?*/
+ pci_write_config8(MCU, 0x69, 0xc7);
+
+ /* Set BA[0/1/2] to [A17/18/19] */
+ pci_write_config16(MCU, 0x52, 0x5b33);
+ /* Disable Multiple Page Mode - Set Rx69[0] to 0 */
+ pci_mod_config8(MCU, 0x69, (1<<0), 0x00);
+
+ /* It's very important that we keep all ranks which are not calibrated
+ * mapped to VR3. Even if we disable them, if they are mapped to VR0
+ * (the rank we use for calibrations), the calibrations may fail in
+ * unexpected ways. */
+ vx900_pr_map_all_vr3();
+
+ for(i = 0; i < VX900_MAX_DIMM_SLOTS; i++)
+ {
+ /* Do we have a valid DIMM? */
+ if(ranks->phys_rank_size[i] + ranks->phys_rank_size[i+1] == 0 )
+ continue;
+
+ /* Map the first rank of the DIMM to VR0 */
+ vx900_map_pr_vr(2*i, 0);
+
+ /* Run calibrations */if(1){
+ vx900_rx_capture_range_calib();
+ vx900_read_delay_range(&(delay_cal.rx_dq_cr),
+ VX900_CALIB_RxDQ_CR);
+ dump_delay_range(delay_cal.rx_dq_cr);}
+
+ /*FIXME: Cheating with Rx CR setting
+ * We need to either use Rx CR calibration
+ * or set up a table for the calibration */
+ dly[0] = 0x28; dly[1] = 0x1c; dly[2] = 0x28; dly[3] = 0x28;
+ dly[4] = 0x2c; dly[5] = 0x30; dly[6] = 0x30; dly[7] = 0x34;
+ printram("Bypassing RxCR 78-7f calibration with:\n");
+ dump_delay(dly);
+ /* We need to put the setting on manual mode */
+ pci_mod_config8(MCU, 0x71, 0, 0x10);
+ vx900_delay_calib_mode_select(VX900_CALIB_RxDQ_CR, VX900_CALIB_MANUAL);
+ vx900_write_0x78_0x7f(dly);
+
+ /************* RxDQS *************/
+ vx900_rx_dqs_delay_calib();
+ vx900_read_delay_range(&(delay_cal.rx_dqs), VX900_CALIB_RxDQS);
+ printram("RX DQS calibration results\n");
+ dump_delay_range(delay_cal.rx_dqs);
+
+ vx900_rxdqs_adjust(&(delay_cal.rx_dqs));
+
+ vx900_read_delay_range(&(delay_cal.rx_dqs), VX900_CALIB_RxDQS);
+ printram("RX DQS calibration results after adjustment\n");
+ dump_delay_range(delay_cal.rx_dqs);
+
+ /* FIXME: Vendor BIOS does it again (enable auto-precharge) - WHY? */
+ pci_write_config8(MCU, 0x69, 0xce);
+
+ /* FIXME: this is done by vendor BIOS, and recommended by VIA
+ * However, datasheet says that bit[7] is reserved, and
+ * calibration works just as well if we don't set this to 1b .
+ * Should we really do this, or can we drop it ? */
+ if(ctrl->tCK <= TCK_533MHZ){
+ for( i = 0; i< 8; i++) dly[i] = 0x80;
+ pci_mod_config8(MCU, 0x75, 0x00, 0x01); /* manual Tx DQ DQS */
+ vx900_delay_calib_mode_select(VX900_CALIB_TxDQ, VX900_CALIB_MANUAL);
+ vx900_write_0x78_0x7f(dly);
+ vx900_delay_calib_mode_select(VX900_CALIB_TxDQS, VX900_CALIB_MANUAL);
+ vx900_write_0x78_0x7f(dly);
+ }
+
+ /************* TxDQS *************/
+ vx900_tx_dqs_delay_calib();
+
+ vx900_read_delay_range(&(delay_cal.tx_dqs), VX900_CALIB_TxDQS);
+ printram("Tx DQS calibration results\n");
+ dump_delay_range(delay_cal.tx_dqs);
+ /************* TxDQ *************/
+ /* FIXME: not sure if multiple page mode should be enabled here
+ * Vendor BIOS does it */
+ pci_mod_config8(MCU, 0x69, 0 , 0x01);
+
+ vx900_tx_dq_delay_calib();
+ vx900_read_delay_range(&(delay_cal.tx_dq), VX900_CALIB_TxDQ);
+ printram("TX DQ delay calibration results:\n");
+ dump_delay_range(delay_cal.tx_dq);
+
+ /* write manual settings */
+ pci_mod_config8(MCU, 0x75, 0, 0x01);
+ vx900_delay_calib_mode_select(VX900_CALIB_TxDQS, VX900_CALIB_MANUAL);
+ vx900_write_0x78_0x7f(delay_cal.tx_dqs.avg);
+ vx900_delay_calib_mode_select(VX900_CALIB_TxDQ, VX900_CALIB_MANUAL);
+ vx900_write_0x78_0x7f(delay_cal.tx_dq.avg);
+ }
+}
+
+static void vx900_dram_set_refresh_counter(ramctr_timing *ctrl)
+{
+ u8 reg8;
+ /* Set DRAM refresh counter
+ * Based on a refresh counter of 0x61 at 400MHz */
+ reg8 = (TCK_400MHZ * 0x61) / ctrl->tCK;
+ pci_write_config8(MCU, 0xc7, reg8);
+}
+
+static void vx900_dram_range(ramctr_timing *ctrl, rank_layout *ranks)
+{
+ size_t i, vrank = 0;
+ u8 reg8;
+ u32 ramsize = 0;
+ vx900_clear_vr_map();
+ for(i = 0; i < VX900_MAX_MEM_RANKS; i++)
+ {
+ u32 rank_size = ranks->phys_rank_size[i];
+ if(!rank_size) continue;
+ ranks->virt[vrank].start_addr = ramsize;
+ ramsize += rank_size;
+ ranks->virt[vrank].end_addr = ramsize;
+
+ /* Rank memory range */
+ reg8 = (ranks->virt[vrank].start_addr >> 2);
+ pci_write_config8(MCU, 0x48 + vrank, reg8);
+ reg8 = (ranks->virt[vrank].end_addr >> 2);
+ pci_write_config8(MCU, 0x40 + vrank, reg8);
+
+ vx900_map_pr_vr(i, vrank);
+
+ printram("Mapped Physical rank %u, to virtual rank %u\n"
+ " Start address: 0x%.8x000000\n"
+ " End address: 0x%.8x000000\n",
+ (int) i, (int) vrank,
+ ranks->virt[vrank].start_addr,
+ ranks->virt[vrank].end_addr);
+
+ /* Move on to next virtual rank */
+ vrank++;
+ }
+
+ printram("Initialized %u virtual ranks, with a total size of %u MB\n",
+ (int) vrank, ramsize << 4);
+}
+
+static void vx900_dram_write_final_config(ramctr_timing *ctrl)
+{
+
+ /* FIXME: These are quick cheats */
+ pci_write_config8(MCU, 0x50, 0xa0); /* DRAM MA map */
+ pci_write_config16(MCU, 0x52, 0x5911); /* Rank interleave */
+
+ //pci_write_config8(MCU, 0x69, 0xe7);
+ //pci_write_config8(MCU, 0x72, 0x0f);
+
+ //pci_write_config8(MCU, 0x97, 0xa4); /* self-refresh */
+
+ /* Enable automatic triggering of short ZQ calibration */
+ pci_write_config8(MCU, 0xc8, 0x80);
+
+}
+
+static void print_debug_pci_dev(device_t dev)
+{
+ print_debug("PCI: ");
+ print_debug_hex8((dev >> 20) & 0xff);
+ print_debug_char(':');
+ print_debug_hex8((dev >> 15) & 0x1f);
+ print_debug_char('.');
+ print_debug_hex8((dev >> 12) & 7);
+}
+
+static void dump_pci_device(device_t dev)
+{
+ int i;
+ print_debug_pci_dev(dev);
+ print_debug("\n");
+
+ for (i = 0; i <= 0xff; i++) {
+ unsigned char val;
+ if ((i & 0x0f) == 0) {
+ print_debug_hex8(i);
+ print_debug_char(':');
+ }
+
+ if ((i & 0x0f) == 0x08) {
+ print_debug(" |");
+ }
+
+ val = pci_read_config8(dev, i);
+ print_debug_char(' ');
+ print_debug_hex8(val);
+
+ if ((i & 0x0f) == 0x0f) {
+ print_debug("\n");
+ }
+ }
+}
+
+void vx900_init_dram_ddr3(const dimm_layout *dimm_addr)
+{
+ dimm_info dimm_prop;
+ ramctr_timing ctrl_prop;
+ rank_layout ranks;
+ device_t mcu;
+
+ /* Locate the Memory controller */
+ mcu = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_VX900_MEMCTRL), 0);
+
+ if (mcu == PCI_DEV_INVALID) {
+ die("Memory Controller not found\n");
+ }
+ dump_pci_device(mcu);
+ memset(&ranks, 0, sizeof(ranks));
+ /* 1) Write some initial "safe" parameters */
+ vx900_dram_write_init_config();
+ /* 2) Get timing information from SPDs */
+ dram_find_spds_ddr3(dimm_addr, &dimm_prop);
+ /* 3) Find lowest common denominator for all modules */
+ dram_find_common_params(&dimm_prop, &ctrl_prop);
+ /* 4) Find the size of each memory rank */
+ vx900_dram_phys_bank_range(&dimm_prop, &ranks);
+ /* 5) Set DRAM driving strength */
+ vx900_dram_driving_ctrl(&dimm_prop);
+ /* 6) Set DRAM frequency and latencies */
+ vx900_dram_timing(&ctrl_prop);
+ vx900_dram_freq(&ctrl_prop);
+ /* 7) Initialize the modules themselves */
+ vx900_dram_ddr3_dimm_init(&ctrl_prop, &ranks);
+ /* 8) Set refresh counter based on DRAM frequency */
+ vx900_dram_set_refresh_counter(&ctrl_prop);
+ /* 9) Calibrate receive and transmit delays */
+ vx900_dram_calibrate_delays(&ctrl_prop, &ranks);
+ /* 10) Enable Physical to Virtual Rank mapping */
+ vx900_dram_range(&ctrl_prop, &ranks);
+ /* 99) Some final adjustments */
+ vx900_dram_write_final_config(&ctrl_prop);
+ /* Take a dump */
+ dump_pci_device(mcu);
+
+}
+
diff --git a/src/northbridge/via/vx900/romstrap.inc b/src/northbridge/via/vx900/romstrap.inc
new file mode 100644
index 0000000..2eb2de5
--- /dev/null
+++ b/src/northbridge/via/vx900/romstrap.inc
@@ -0,0 +1,50 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2004 Tyan Computer
+ * (Written by Yinghai Lu <yhlu(a)tyan.com> for Tyan Computer)
+ * Copyright (C) 2007 Rudolf Marek <r.marek(a)assembler.cz>
+ * Copyright (C) 2009 One Laptop per Child, Association, Inc.
+ * Copyright (C) 2011-2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* This file constructs the ROM strap table for VX900 */
+
+ .section ".romstrap", "a", @progbits
+
+ .globl __romstrap_start
+__romstrap_start:
+tblpointer:
+ .long 0x77886047
+ .long 0x00777777
+ .long 0x00000000
+ .long 0x00000000
+ .long 0x00888888
+ .long 0x00AA1111
+ .long 0x00000000
+ .long 0x00000000
+
+/*
+ * The pointer to above table should be at 0xffffffd0,
+ * the table itself MUST be aligned to 128B it seems!
+ */
+rspointers:
+ .long tblpointer // It will be 0xffffffd0
+
+ .globl __romstrap_end
+
+__romstrap_end:
+.previous
diff --git a/src/northbridge/via/vx900/romstrap.lds b/src/northbridge/via/vx900/romstrap.lds
new file mode 100644
index 0000000..fc63c05
--- /dev/null
+++ b/src/northbridge/via/vx900/romstrap.lds
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 AMD
+ * (Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD)
+ * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>
+ */
+
+SECTIONS {
+ . = (0x100000000 - 0x2c) - (__romstrap_end - __romstrap_start);
+ .romstrap (.): {
+ *(.romstrap)
+ }
+}
diff --git a/src/northbridge/via/vx900/vx900.h b/src/northbridge/via/vx900/vx900.h
new file mode 100644
index 0000000..2137daf
--- /dev/null
+++ b/src/northbridge/via/vx900/vx900.h
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#define VX800_ACPI_IO_BASE 0x0400
+
+#define VX900_NB_IOAPIC_ID 0x2
+#define VX900_NB_IOAPIC_BASE 0xfecc000
+
+#define VX900_SB_IOAPIC_ID 0x1
+#define VX900_SB_IOAPIC_BASE 0xfec0000
\ No newline at end of file
1
0
20 Jul '12
Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1241
-gerrit
commit fda6a3cf882adecf8ffc56dfeafd7b28ef215eda
Author: zbao <fishbaozi(a)gmail.com>
Date: Thu Jul 19 16:38:12 2012 +0800
Trinity wrapper code improvement.
Set the default location of hudson firmware to 3rdparty.
Move UMA code from mainboard to northbridge.
Change-Id: I11afea0c7fd04aa84a629dc762704c42baf002df
Signed-off-by: Zheng Bao <zheng.bao(a)amd.com>
Signed-off-by: zbao <fishbaozi(a)gmail.com>
---
src/northbridge/amd/agesa/family15tn/northbridge.c | 48 ++++++++++++++++++++
src/southbridge/amd/agesa/hudson/Kconfig | 6 +-
2 files changed, 51 insertions(+), 3 deletions(-)
diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c
index 1e14e8e..dc04afd 100644
--- a/src/northbridge/amd/agesa/family15tn/northbridge.c
+++ b/src/northbridge/amd/agesa/family15tn/northbridge.c
@@ -613,6 +613,54 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void)
}
#endif
+#define ONE_MB 0x100000
+
+void setup_uma_memory(void)
+{
+#if CONFIG_GFXUMA
+ msr_t msr, msr2;
+ uint32_t sys_mem;
+
+ /* TOP_MEM: the top of DRAM below 4G */
+ msr = rdmsr(TOP_MEM);
+ printk
+ (BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
+ __func__, msr.lo, msr.hi);
+
+ /* TOP_MEM2: the top of DRAM above 4G */
+ msr2 = rdmsr(TOP_MEM2);
+ printk (BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n",
+ __func__, msr2.lo, msr2.hi);
+
+ /* refer to UMA Size Consideration in Family15h BKDG. */
+ /* Please reference MemNGetUmaSizeOR () */
+ /*
+ * Total system memory UMASize
+ * >= 2G 512M
+ * >=1G 256M
+ * <1G 64M
+ */
+ sys_mem = msr.lo + 16 * ONE_MB; // Ignore 16MB allocated for C6 when finding UMA size
+ if ((msr2.hi & 0x0000000F) || (sys_mem >= 2048 * ONE_MB)) {
+ uma_memory_size = 512 * ONE_MB;
+ } else if (sys_mem >= 1024 * ONE_MB) {
+ uma_memory_size = 256 * ONE_MB;
+ } else {
+ uma_memory_size = 64 * ONE_MB;
+ }
+ uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */
+
+ printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n",
+ __func__, uma_memory_size, uma_memory_base);
+
+ /* TODO: TOP_MEM2 */
+#else
+ uma_memory_size = 256 * ONE_MB; /* 256M recommended UMA */
+ uma_memory_base = 768 * ONE_MB; /* 1GB system memory supported */
+#endif
+}
+
+
static void domain_set_resources(device_t dev)
{
#if CONFIG_PCI_64BIT_PREF_MEM == 1
diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig
index 5b29042..e3fc8c7 100644
--- a/src/southbridge/amd/agesa/hudson/Kconfig
+++ b/src/southbridge/amd/agesa/hudson/Kconfig
@@ -67,17 +67,17 @@ config HUDSON_GEC_FWM
config HUDSON_XHCI_FWM_FILE
string "XHCI firmware path and filename"
- default "3rdparty/amd/hudson/xhci.bin"
+ default "3rdparty/southbridge/amd/hudson/xhci.bin"
depends on HUDSON_XHCI_FWM
config HUDSON_IMC_FWM_FILE
string "IMC firmware path and filename"
- default "3rdparty/amd/hudson/imc.bin"
+ default "3rdparty/southbridge/amd/hudson/imc.bin"
depends on HUDSON_IMC_FWM
config HUDSON_GEC_FWM_FILE
string "GEC firmware path and filename"
- default "src/southbridge/amd/agesa/hudson/gec.bin"
+ default "3rdparty/southbridge/amd/hudson/gec.bin"
depends on HUDSON_GEC_FWM
config HUDSON_FWM
1
0
20 Jul '12
Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1158
-gerrit
commit 99aa8442610e80c70ec6004dcde26179b03fcf24
Author: zbao <fishbaozi(a)gmail.com>
Date: Thu Jul 19 16:39:01 2012 +0800
Mainboard Parmer based on Trinity
Parmer has.
1. Trinity, Socket FS1R2.
2. Hudson A75.
Ubuntu has been validated on Parmer. S3 is supported.
Change-Id: I1a6932d0ca9f7abe78dc24d3bc238a4b5a48281b
Signed-off-by: Zheng Bao <zheng.bao(a)amd.com>
Signed-off-by: zbao <fishbaozi(a)gmail.com>
---
src/mainboard/amd/Kconfig | 3 +
src/mainboard/amd/parmer/BiosCallOuts.c | 735 +++++++++++
src/mainboard/amd/parmer/BiosCallOuts.h | 82 ++
src/mainboard/amd/parmer/Kconfig | 114 ++
src/mainboard/amd/parmer/Makefile.inc | 33 +
src/mainboard/amd/parmer/OptionsIds.h | 67 +
src/mainboard/amd/parmer/PlatformGnbPcie.c | 203 +++
src/mainboard/amd/parmer/PlatformGnbPcieComplex.h | 72 ++
src/mainboard/amd/parmer/acpi/AmdImc.asl | 95 ++
src/mainboard/amd/parmer/acpi/ide.asl | 244 ++++
src/mainboard/amd/parmer/acpi/routing.asl | 356 ++++++
src/mainboard/amd/parmer/acpi/sata.asl | 148 +++
src/mainboard/amd/parmer/acpi/usb.asl | 114 ++
src/mainboard/amd/parmer/acpi_tables.c | 329 +++++
src/mainboard/amd/parmer/agesawrapper.c | 768 +++++++++++
src/mainboard/amd/parmer/agesawrapper.h | 97 ++
src/mainboard/amd/parmer/buildOpts.c | 499 ++++++++
src/mainboard/amd/parmer/chip.h | 22 +
src/mainboard/amd/parmer/cmos.layout | 114 ++
src/mainboard/amd/parmer/devicetree.cb | 86 ++
src/mainboard/amd/parmer/dimmSpd.c | 164 +++
src/mainboard/amd/parmer/dimmSpd.h | 59 +
src/mainboard/amd/parmer/dsdt.asl | 1421 +++++++++++++++++++++
src/mainboard/amd/parmer/get_bus_conf.c | 140 ++
src/mainboard/amd/parmer/irq_tables.c | 112 ++
src/mainboard/amd/parmer/mainboard.c | 70 +
src/mainboard/amd/parmer/mptable.c | 212 +++
src/mainboard/amd/parmer/pmio.c | 53 +
src/mainboard/amd/parmer/pmio.h | 33 +
src/mainboard/amd/parmer/reset.c | 64 +
src/mainboard/amd/parmer/romstage.c | 162 +++
31 files changed, 6671 insertions(+), 0 deletions(-)
diff --git a/src/mainboard/amd/Kconfig b/src/mainboard/amd/Kconfig
index c6de048..eaaf877 100644
--- a/src/mainboard/amd/Kconfig
+++ b/src/mainboard/amd/Kconfig
@@ -37,6 +37,8 @@ config BOARD_AMD_TORPEDO
bool "Torpedo"
config BOARD_AMD_UNIONSTATION
bool "Unionstation"
+config BOARD_AMD_PARMER
+ bool "Parmer"
endchoice
source "src/mainboard/amd/db800/Kconfig"
@@ -56,6 +58,7 @@ source "src/mainboard/amd/persimmon/Kconfig"
source "src/mainboard/amd/south_station/Kconfig"
source "src/mainboard/amd/torpedo/Kconfig"
source "src/mainboard/amd/union_station/Kconfig"
+source "src/mainboard/amd/parmer/Kconfig"
config MAINBOARD_VENDOR
string
diff --git a/src/mainboard/amd/parmer/BiosCallOuts.c b/src/mainboard/amd/parmer/BiosCallOuts.c
new file mode 100644
index 0000000..a50e532
--- /dev/null
+++ b/src/mainboard/amd/parmer/BiosCallOuts.c
@@ -0,0 +1,735 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include "agesawrapper.h"
+#include "amdlib.h"
+#include "dimmSpd.h"
+#include "BiosCallOuts.h"
+#include "Ids.h"
+#include "OptionsIds.h"
+#include "heapManager.h"
+#include "FchPlatform.h"
+
+STATIC CONST BIOS_CALLOUT_STRUCT BiosCallouts[] =
+{
+ {AGESA_ALLOCATE_BUFFER,
+ BiosAllocateBuffer
+ },
+
+ {AGESA_DEALLOCATE_BUFFER,
+ BiosDeallocateBuffer
+ },
+
+ {AGESA_DO_RESET,
+ BiosReset
+ },
+
+ {AGESA_LOCATE_BUFFER,
+ BiosLocateBuffer
+ },
+
+ {AGESA_READ_SPD,
+ BiosReadSpd
+ },
+
+ {AGESA_READ_SPD_RECOVERY,
+ BiosDefaultRet
+ },
+
+ {AGESA_RUNFUNC_ONAP,
+ BiosRunFuncOnAp
+ },
+
+ {AGESA_GET_IDS_INIT_DATA,
+ BiosGetIdsInitData
+ },
+
+ {AGESA_HOOKBEFORE_DQS_TRAINING,
+ BiosHookBeforeDQSTraining
+ },
+
+ {AGESA_HOOKBEFORE_EXIT_SELF_REF,
+ BiosHookBeforeExitSelfRefresh
+ },
+
+ {AGESA_FCH_OEM_CALLOUT,
+ Fch_Oem_config
+ },
+};
+
+AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+ UINTN i;
+ AGESA_STATUS CalloutStatus;
+ UINTN CallOutCount = sizeof (BiosCallouts) / sizeof (BiosCallouts [0]);
+
+ for (i = 0; i < CallOutCount; i++)
+ {
+ if (BiosCallouts[i].CalloutName == Func)
+ {
+ break;
+ }
+ }
+
+ if(i >= CallOutCount)
+ {
+ return AGESA_UNSUPPORTED;
+ }
+
+ CalloutStatus = BiosCallouts[i].CalloutPtr (Func, Data, ConfigPtr);
+
+ return CalloutStatus;
+}
+
+CONST IDS_NV_ITEM IdsData[] =
+{
+ /*{
+ AGESA_IDS_NV_MAIN_PLL_CON,
+ 0x1
+ },
+ {
+ AGESA_IDS_NV_MAIN_PLL_FID_EN,
+ 0x1
+ },
+ {
+ AGESA_IDS_NV_MAIN_PLL_FID,
+ 0x8
+ },
+
+ {
+ AGESA_IDS_NV_CUSTOM_NB_PSTATE,
+ },
+ {
+ AGESA_IDS_NV_CUSTOM_NB_P0_DIV_CTRL,
+ },
+ {
+ AGESA_IDS_NV_CUSTOM_NB_P1_DIV_CTRL,
+ },
+ {
+ AGESA_IDS_NV_FORCE_NB_PSTATE,
+ },
+ */
+ {
+ 0xFFFF,
+ 0xFFFF
+ }
+};
+
+#define NUM_IDS_ENTRIES (sizeof (IdsData) / sizeof (IDS_NV_ITEM))
+
+AGESA_STATUS BiosGetIdsInitData (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+ UINTN i;
+ IDS_NV_ITEM *IdsPtr;
+
+ IdsPtr = ((IDS_CALLOUT_STRUCT *) ConfigPtr)->IdsNvPtr;
+
+ if (Data == IDS_CALLOUT_INIT) {
+ for (i = 0; i < NUM_IDS_ENTRIES; i++) {
+ IdsPtr[i].IdsNvValue = IdsData[i].IdsNvValue;
+ IdsPtr[i].IdsNvId = IdsData[i].IdsNvId;
+ }
+ }
+ return AGESA_SUCCESS;
+}
+
+AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+ UINT32 AvailableHeapSize;
+ UINT8 *BiosHeapBaseAddr;
+ UINT32 CurrNodeOffset;
+ UINT32 PrevNodeOffset;
+ UINT32 FreedNodeOffset;
+ UINT32 BestFitNodeOffset;
+ UINT32 BestFitPrevNodeOffset;
+ UINT32 NextFreeOffset;
+ BIOS_BUFFER_NODE *CurrNodePtr;
+ BIOS_BUFFER_NODE *FreedNodePtr;
+ BIOS_BUFFER_NODE *BestFitNodePtr;
+ BIOS_BUFFER_NODE *BestFitPrevNodePtr;
+ BIOS_BUFFER_NODE *NextFreePtr;
+ BIOS_HEAP_MANAGER *BiosHeapBasePtr;
+ AGESA_BUFFER_PARAMS *AllocParams;
+
+ AllocParams = ((AGESA_BUFFER_PARAMS *) ConfigPtr);
+ AllocParams->BufferPointer = NULL;
+
+ AvailableHeapSize = BIOS_HEAP_SIZE - sizeof (BIOS_HEAP_MANAGER);
+ BiosHeapBaseAddr = (UINT8 *) GetHeapBase(&(AllocParams->StdHeader));
+ BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BiosHeapBaseAddr;
+
+ if (BiosHeapBasePtr->StartOfAllocatedNodes == 0) {
+ /* First allocation */
+ CurrNodeOffset = sizeof (BIOS_HEAP_MANAGER);
+ CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset);
+ CurrNodePtr->BufferHandle = AllocParams->BufferHandle;
+ CurrNodePtr->BufferSize = AllocParams->BufferLength;
+ CurrNodePtr->NextNodeOffset = 0;
+ AllocParams->BufferPointer = (UINT8 *) CurrNodePtr + sizeof (BIOS_BUFFER_NODE);
+
+ /* Update the remaining free space */
+ FreedNodeOffset = CurrNodeOffset + CurrNodePtr->BufferSize + sizeof (BIOS_BUFFER_NODE);
+ FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset);
+ FreedNodePtr->BufferSize = AvailableHeapSize - sizeof (BIOS_BUFFER_NODE) - CurrNodePtr->BufferSize;
+ FreedNodePtr->NextNodeOffset = 0;
+
+ /* Update the offsets for Allocated and Freed nodes */
+ BiosHeapBasePtr->StartOfAllocatedNodes = CurrNodeOffset;
+ BiosHeapBasePtr->StartOfFreedNodes = FreedNodeOffset;
+ } else {
+ /* Find out whether BufferHandle has been allocated on the heap. */
+ /* If it has, return AGESA_BOUNDS_CHK */
+ CurrNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes;
+ CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset);
+
+ while (CurrNodeOffset != 0) {
+ CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset);
+ if (CurrNodePtr->BufferHandle == AllocParams->BufferHandle) {
+ return AGESA_BOUNDS_CHK;
+ }
+ CurrNodeOffset = CurrNodePtr->NextNodeOffset;
+ /* If BufferHandle has not been allocated on the heap, CurrNodePtr here points
+ to the end of the allocated nodes list.
+ */
+
+ }
+ /* Find the node that best fits the requested buffer size */
+ FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes;
+ PrevNodeOffset = FreedNodeOffset;
+ BestFitNodeOffset = 0;
+ BestFitPrevNodeOffset = 0;
+ while (FreedNodeOffset != 0) {
+ FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset);
+ if (FreedNodePtr->BufferSize >= (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE))) {
+ if (BestFitNodeOffset == 0) {
+ /* First node that fits the requested buffer size */
+ BestFitNodeOffset = FreedNodeOffset;
+ BestFitPrevNodeOffset = PrevNodeOffset;
+ } else {
+ /* Find out whether current node is a better fit than the previous nodes */
+ BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset);
+ if (BestFitNodePtr->BufferSize > FreedNodePtr->BufferSize) {
+ BestFitNodeOffset = FreedNodeOffset;
+ BestFitPrevNodeOffset = PrevNodeOffset;
+ }
+ }
+ }
+ PrevNodeOffset = FreedNodeOffset;
+ FreedNodeOffset = FreedNodePtr->NextNodeOffset;
+ } /* end of while loop */
+
+ if (BestFitNodeOffset == 0) {
+ /* If we could not find a node that fits the requested buffer */
+ /* size, return AGESA_BOUNDS_CHK */
+ return AGESA_BOUNDS_CHK;
+ } else {
+ BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset);
+ BestFitPrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitPrevNodeOffset);
+
+ /* If BestFitNode is larger than the requested buffer, fragment the node further */
+ if (BestFitNodePtr->BufferSize > (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE))) {
+ NextFreeOffset = BestFitNodeOffset + AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE);
+
+ NextFreePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextFreeOffset);
+ NextFreePtr->BufferSize = BestFitNodePtr->BufferSize - (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE));
+ NextFreePtr->NextNodeOffset = BestFitNodePtr->NextNodeOffset;
+ } else {
+ /* Otherwise, next free node is NextNodeOffset of BestFitNode */
+ NextFreeOffset = BestFitNodePtr->NextNodeOffset;
+ }
+
+ /* If BestFitNode is the first buffer in the list, then update
+ StartOfFreedNodes to reflect the new free node
+ */
+ if (BestFitNodeOffset == BiosHeapBasePtr->StartOfFreedNodes) {
+ BiosHeapBasePtr->StartOfFreedNodes = NextFreeOffset;
+ } else {
+ BestFitPrevNodePtr->NextNodeOffset = NextFreeOffset;
+ }
+
+ /* Add BestFitNode to the list of Allocated nodes */
+ CurrNodePtr->NextNodeOffset = BestFitNodeOffset;
+ BestFitNodePtr->BufferSize = AllocParams->BufferLength;
+ BestFitNodePtr->BufferHandle = AllocParams->BufferHandle;
+ BestFitNodePtr->NextNodeOffset = 0;
+
+ /* Remove BestFitNode from list of Freed nodes */
+ AllocParams->BufferPointer = (UINT8 *) BestFitNodePtr + sizeof (BIOS_BUFFER_NODE);
+ }
+ }
+
+ return AGESA_SUCCESS;
+}
+
+AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+
+ UINT8 *BiosHeapBaseAddr;
+ UINT32 AllocNodeOffset;
+ UINT32 PrevNodeOffset;
+ UINT32 NextNodeOffset;
+ UINT32 FreedNodeOffset;
+ UINT32 EndNodeOffset;
+ BIOS_BUFFER_NODE *AllocNodePtr;
+ BIOS_BUFFER_NODE *PrevNodePtr;
+ BIOS_BUFFER_NODE *FreedNodePtr;
+ BIOS_BUFFER_NODE *NextNodePtr;
+ BIOS_HEAP_MANAGER *BiosHeapBasePtr;
+ AGESA_BUFFER_PARAMS *AllocParams;
+
+ BiosHeapBaseAddr = (UINT8 *) GetHeapBase(&(AllocParams->StdHeader));
+ BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BiosHeapBaseAddr;
+
+ AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr;
+
+ /* Find target node to deallocate in list of allocated nodes.
+ Return AGESA_BOUNDS_CHK if the BufferHandle is not found
+ */
+ AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes;
+ AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset);
+ PrevNodeOffset = AllocNodeOffset;
+
+ while (AllocNodePtr->BufferHandle != AllocParams->BufferHandle) {
+ if (AllocNodePtr->NextNodeOffset == 0) {
+ return AGESA_BOUNDS_CHK;
+ }
+ PrevNodeOffset = AllocNodeOffset;
+ AllocNodeOffset = AllocNodePtr->NextNodeOffset;
+ AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset);
+ }
+
+ /* Remove target node from list of allocated nodes */
+ PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset);
+ PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset;
+
+ /* Zero out the buffer, and clear the BufferHandle */
+ LibAmdMemFill ((UINT8 *)AllocNodePtr + sizeof (BIOS_BUFFER_NODE), 0, AllocNodePtr->BufferSize, &(AllocParams->StdHeader));
+ AllocNodePtr->BufferHandle = 0;
+ AllocNodePtr->BufferSize += sizeof (BIOS_BUFFER_NODE);
+
+ /* Add deallocated node in order to the list of freed nodes */
+ FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes;
+ FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset);
+
+ EndNodeOffset = AllocNodeOffset + AllocNodePtr->BufferSize;
+
+ if (AllocNodeOffset < FreedNodeOffset) {
+ /* Add to the start of the freed list */
+ if (EndNodeOffset == FreedNodeOffset) {
+ /* If the freed node is adjacent to the first node in the list, concatenate both nodes */
+ AllocNodePtr->BufferSize += FreedNodePtr->BufferSize;
+ AllocNodePtr->NextNodeOffset = FreedNodePtr->NextNodeOffset;
+
+ /* Clear the BufferSize and NextNodeOffset of the previous first node */
+ FreedNodePtr->BufferSize = 0;
+ FreedNodePtr->NextNodeOffset = 0;
+
+ } else {
+ /* Otherwise, add freed node to the start of the list
+ Update NextNodeOffset and BufferSize to include the
+ size of BIOS_BUFFER_NODE
+ */
+ AllocNodePtr->NextNodeOffset = FreedNodeOffset;
+ }
+ /* Update StartOfFreedNodes to the new first node */
+ BiosHeapBasePtr->StartOfFreedNodes = AllocNodeOffset;
+ } else {
+ /* Traverse list of freed nodes to find where the deallocated node
+ should be place
+ */
+ NextNodeOffset = FreedNodeOffset;
+ NextNodePtr = FreedNodePtr;
+ while (AllocNodeOffset > NextNodeOffset) {
+ PrevNodeOffset = NextNodeOffset;
+ if (NextNodePtr->NextNodeOffset == 0) {
+ break;
+ }
+ NextNodeOffset = NextNodePtr->NextNodeOffset;
+ NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset);
+ }
+
+ /* If deallocated node is adjacent to the next node,
+ concatenate both nodes
+ */
+ if (NextNodeOffset == EndNodeOffset) {
+ NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset);
+ AllocNodePtr->BufferSize += NextNodePtr->BufferSize;
+ AllocNodePtr->NextNodeOffset = NextNodePtr->NextNodeOffset;
+
+ NextNodePtr->BufferSize = 0;
+ NextNodePtr->NextNodeOffset = 0;
+ } else {
+ /*AllocNodePtr->NextNodeOffset = FreedNodePtr->NextNodeOffset; */
+ AllocNodePtr->NextNodeOffset = NextNodeOffset;
+ }
+ /* If deallocated node is adjacent to the previous node,
+ concatenate both nodes
+ */
+ PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset);
+ EndNodeOffset = PrevNodeOffset + PrevNodePtr->BufferSize;
+ if (AllocNodeOffset == EndNodeOffset) {
+ PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset;
+ PrevNodePtr->BufferSize += AllocNodePtr->BufferSize;
+
+ AllocNodePtr->BufferSize = 0;
+ AllocNodePtr->NextNodeOffset = 0;
+ } else {
+ PrevNodePtr->NextNodeOffset = AllocNodeOffset;
+ }
+ }
+ return AGESA_SUCCESS;
+}
+
+AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+ UINT32 AllocNodeOffset;
+ UINT8 *BiosHeapBaseAddr;
+ BIOS_BUFFER_NODE *AllocNodePtr;
+ BIOS_HEAP_MANAGER *BiosHeapBasePtr;
+ AGESA_BUFFER_PARAMS *AllocParams;
+
+ AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr;
+
+ BiosHeapBaseAddr = (UINT8 *) GetHeapBase(&(AllocParams->StdHeader));
+ BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BiosHeapBaseAddr;
+
+ AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes;
+ AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset);
+
+ while (AllocParams->BufferHandle != AllocNodePtr->BufferHandle) {
+ if (AllocNodePtr->NextNodeOffset == 0) {
+ AllocParams->BufferPointer = NULL;
+ AllocParams->BufferLength = 0;
+ return AGESA_BOUNDS_CHK;
+ } else {
+ AllocNodeOffset = AllocNodePtr->NextNodeOffset;
+ AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset);
+ }
+ }
+
+ AllocParams->BufferPointer = (UINT8 *) ((UINT8 *) AllocNodePtr + sizeof (BIOS_BUFFER_NODE));
+ AllocParams->BufferLength = AllocNodePtr->BufferSize;
+
+ return AGESA_SUCCESS;
+
+}
+
+AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+ AGESA_STATUS Status;
+
+ Status = agesawrapper_amdlaterunaptask (Func, Data, ConfigPtr);
+ return Status;
+}
+
+AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+ AGESA_STATUS Status;
+ UINT8 Value;
+ UINTN ResetType;
+ AMD_CONFIG_PARAMS *StdHeader;
+
+ ResetType = Data;
+ StdHeader = ConfigPtr;
+
+ //
+ // Perform the RESET based upon the ResetType. In case of
+ // WARM_RESET_WHENVER and COLD_RESET_WHENEVER, the request will go to
+ // AmdResetManager. During the critical condition, where reset is required
+ // immediately, the reset will be invoked directly by writing 0x04 to port
+ // 0xCF9 (Reset Port).
+ //
+ switch (ResetType) {
+ case WARM_RESET_WHENEVER:
+ case COLD_RESET_WHENEVER:
+ break;
+
+ case WARM_RESET_IMMEDIATELY:
+ case COLD_RESET_IMMEDIATELY:
+ Value = 0x06;
+ LibAmdIoWrite (AccessWidth8, 0xCf9, &Value, StdHeader);
+ break;
+
+ default:
+ break;
+ }
+
+ Status = 0;
+ return Status;
+}
+
+AGESA_STATUS BiosReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+ AGESA_STATUS Status;
+ Status = AmdMemoryReadSPD (Func, Data, ConfigPtr);
+
+ return Status;
+}
+
+AGESA_STATUS BiosDefaultRet (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+ return AGESA_UNSUPPORTED;
+}
+
+/* Call the host environment interface to provide a user hook opportunity. */
+AGESA_STATUS BiosHookBeforeDQSTraining (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+ return AGESA_SUCCESS;
+}
+
+/* Call the host environment interface to provide a user hook opportunity. */
+AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+ return AGESA_SUCCESS;
+}
+
+/**
+ * AMD Parmer Platform ALC272 Verb Table
+ */
+const CODEC_ENTRY Pumori_Alc272_VerbTbl[] = {
+ {0x11, 0x411111F0},
+ {0x12, 0x411111F0},
+ {0x13, 0x411111F0},
+ {0x14, 0x411111F0},
+ {0x15, 0x411111F0},
+ {0x16, 0x411111F0},
+ {0x17, 0x411111F0},
+ {0x18, 0x01a19830},
+ {0x19, 0x411111F0},
+ {0x1a, 0x01813020},
+ {0x1b, 0x411111F0},
+ {0x1d, 0x40151e05},
+ {0x1e, 0x411111F0},
+ {0x21, 0x01214010},
+ {0xff, 0xffffffff}
+};
+
+const CODEC_TBL_LIST PumoriCodecTableList[] =
+{
+ {0x10ec0272, (CODEC_ENTRY*)&Pumori_Alc272_VerbTbl[0]},
+ {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL}
+};
+
+#define FAN_INPUT_INTERNAL_DIODE 0
+#define FAN_INPUT_TEMP0 1
+#define FAN_INPUT_TEMP1 2
+#define FAN_INPUT_TEMP2 3
+#define FAN_INPUT_TEMP3 4
+#define FAN_INPUT_TEMP0_FILTER 5
+#define FAN_INPUT_ZERO 6
+#define FAN_INPUT_DISABLED 7
+
+#define FAN_AUTOMODE (1 << 0)
+#define FAN_LINEARMODE (1 << 1)
+#define FAN_STEPMODE ~(1 << 1)
+#define FAN_POLARITY_HIGH (1 << 2)
+#define FAN_POLARITY_LOW ~(1 << 2)
+
+/* Normally, 4-wire fan runs at 25KHz and 3-wire fan runs at 100Hz */
+#define FREQ_28KHZ 0x0
+#define FREQ_25KHZ 0x1
+#define FREQ_23KHZ 0x2
+#define FREQ_21KHZ 0x3
+#define FREQ_29KHZ 0x4
+#define FREQ_18KHZ 0x5
+#define FREQ_100HZ 0xF7
+#define FREQ_87HZ 0xF8
+#define FREQ_58HZ 0xF9
+#define FREQ_44HZ 0xFA
+#define FREQ_35HZ 0xFB
+#define FREQ_29HZ 0xFC
+#define FREQ_22HZ 0xFD
+#define FREQ_14HZ 0xFE
+#define FREQ_11HZ 0xFF
+
+/* Parmer Hardware Monitor Fan Control
+ * Hardware limitation:
+ * HWM failed to read the input temperture vi I2C,
+ * if other software switch the I2C switch by mistake or intention.
+ * We recommend to using IMC to control Fans, instead of HWM.
+ */
+static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
+{
+ FCH_HWM_FAN_CTR oem_factl[5] = {
+ /*temperatuer input, fan mode, frequency, low_duty, med_duty, multiplier, lowtemp, medtemp, hightemp, LinearRange, LinearHoldCount */
+ /* Parmer FanOUT0 Fan header J32 */
+ {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0},
+ /* Parmer FanOUT1 Fan header J31*/
+ {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0},
+ {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0},
+ {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0},
+ {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0},
+ };
+ LibAmdMemCopy ((VOID *)(FchParams->Hwm.HwmFanControl), &oem_factl, (sizeof (FCH_HWM_FAN_CTR) * 5), FchParams->StdHeader);
+
+ /* Enable IMC fan control. the recommand way */
+#if defined CONFIG_HUDSON_IMC_FWM && (CONFIG_HUDSON_IMC_FWM == 1)
+ /* HwMonitorEnable = TRUE && HwmFchtsiAutoOpll ==FALSE to call FchECfancontrolservice */
+ FchParams->Hwm.HwMonitorEnable = TRUE;
+ FchParams->Hwm.HwmFchtsiAutoPoll = FALSE;/* 0 disable, 1 enable TSI Auto Polling */
+
+ FchParams->Imc.ImcEnable = TRUE;
+ FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */
+ FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC , 1 enable IMC, 0 following hw strap setting */
+
+ LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader);
+
+ /* Thermal Zone Parameter */
+ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00;
+ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */
+ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x00; //BIT0 | BIT2 | BIT5;
+ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x00;//6 | BIT3;
+ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00;
+ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x00;
+ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x98; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */
+ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg7 = 2;
+ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg8 = 0; /* PWM steping rate in unit of PWM level percentage */
+ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg9 = 0;
+
+ /* IMC Fan Policy temperature thresholds */
+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg0 = 0x00;
+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg1 = 0x00; /* Zone */
+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0;///80; /*AC0 threshold in Celsius */
+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg3 = 0; /*AC1 threshold in Celsius */
+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0; /*AC2 threshold in Celsius */
+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0; /*AC3 threshold in Celsius, 0xFF is not define */
+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg6 = 0; /*AC4 threshold in Celsius, 0xFF is not define */
+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg7 = 0; /*AC5 threshold in Celsius, 0xFF is not define */
+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg8 = 0; /*AC6 threshold in Celsius, 0xFF is not define */
+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg9 = 0; /*AC7 lowest threshold in Celsius, 0xFF is not define */
+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegA = 0; /*critical threshold* in Celsius, 0xFF is not define */
+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegB = 0x00;
+
+ /* IMC Fan Policy PWM Settings */
+ FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg0 = 0x00;
+ FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg1 = 0x00; /* Zone */
+ FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg2 = 0; /* AL0 percentage */
+ FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg3 = 0; /* AL1 percentage */
+ FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg4 = 0; /* AL2 percentage */
+ FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg5 = 0x00; /* AL3 percentage */
+ FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg6 = 0x00; /* AL4 percentage */
+ FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg7 = 0x00; /* AL5 percentage */
+ FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg8 = 0x00; /* AL6 percentage */
+ FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg9 = 0x00; /* AL7 percentage */
+
+ FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg0 = 0x00;
+ FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg1 = 0x01; /* Zone */
+ FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg2 = 0x55;//BIT0 | BIT2 | BIT5;
+ FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg3 = 0x17;
+ FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg4 = 0x00;
+ FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg5 = 0x00;
+ FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg6 = 0x90; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */
+ FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg7 = 0;
+ FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg8 = 0; /* PWM steping rate in unit of PWM level percentage */
+ FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg9 = 0;
+
+ FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg0 = 0x00;
+ FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg1 = 0x01; /* zone */
+ FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg2 = 60; /*AC0 threshold in Celsius */
+ FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg3 = 40; /*AC1 threshold in Celsius */
+ FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg4 = 0; /*AC2 threshold in Celsius */
+ FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg5 = 0; /*AC3 threshold in Celsius, 0xFF is not define */
+ FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg6 = 0; /*AC4 threshold in Celsius, 0xFF is not define */
+ FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg7 = 0; /*AC5 threshold in Celsius, 0xFF is not define */
+ FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg8 = 0; /*AC6 threshold in Celsius, 0xFF is not define */
+ FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg9 = 0; /*AC7 lowest threshold in Celsius, 0xFF is not define */
+ FchParams->Imc.EcStruct.MsgFun83Zone1MsgRegA = 0; /*critical threshold* in Celsius, 0xFF is not define */
+ FchParams->Imc.EcStruct.MsgFun83Zone1MsgRegB = 0x00;
+
+ FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg0 = 0x00;
+ FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg1 = 0x01; /*Zone */
+ FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg2 = 0; /* AL0 percentage */
+ FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg3 = 0; /* AL1 percentage */
+ FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg4 = 0; /* AL2 percentage */
+ FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg5 = 0x00; /* AL3 percentage */
+ FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg6 = 0x00; /* AL4 percentage */
+ FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg7 = 0x00; /* AL5 percentage */
+ FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg8 = 0x00; /* AL6 percentage */
+ FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg9 = 0x00; /* AL7 percentage */
+
+ FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg0 = 0x00;
+ FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg1 = 0x2; /* Zone */
+ FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg2 = 0x0;//BIT0 | BIT2 | BIT5;
+ FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg3 = 0x0;
+ FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg4 = 0x00;
+ FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg5 = 0x00;
+ FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg6 = 0x98; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */
+ FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg7 = 2;
+ FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg8 = 5; /* PWM steping rate in unit of PWM level percentage */
+ FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg9 = 0;
+
+ FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg0 = 0x00;
+ FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg1 = 0x3; /* Zone */
+ FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg2 = 0x0;//BIT0 | BIT2 | BIT5;
+ FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg3 = 0x0;
+ FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg4 = 0x00;
+ FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg5 = 0x00;
+ FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg6 = 0x0; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */
+ FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg7 = 0;
+ FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg8 = 0; /* PWM steping rate in unit of PWM level percentage */
+ FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg9 = 0;
+
+ /* IMC Function */
+ FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x333;//BIT0 | BIT4 |BIT8;
+
+ /* NOTE:
+ * FchInitLateHwm will overwrite the EcStruct with EcDefaultMassege,
+ * AGESA put EcDefaultMassege as global data in ROM, so we can't overwride it.
+ * so we remove it from AGESA code. Please Seee FchInitLateHwm.
+ */
+
+#else /* HWM fan control, the way not recommand */
+ FchParams->Imc.ImcEnable = FALSE;
+ FchParams->Hwm.HwMonitorEnable = TRUE;
+ FchParams->Hwm.HwmFchtsiAutoPoll = TRUE;/* 1 enable, 0 disable TSI Auto Polling */
+
+#endif /* CONFIG_HUDSON_IMC_FWM */
+}
+
+/**
+ * Fch Oem setting callback
+ *
+ * Configure platform specific Hudson device,
+ * such Azalia, SATA, GEC, IMC etc.
+ */
+AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr)
+{
+ FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *)FchData;
+
+ if (FchParams->StdHeader->Func == AMD_INIT_RESET) {
+ //FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *) FchData;
+ printk(BIOS_DEBUG, "Fch OEM config in INIT RESET ");
+ //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */
+ } else if (FchParams->StdHeader->Func == AMD_INIT_ENV) {
+ FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData;
+ printk(BIOS_DEBUG, "Fch OEM config in INIT ENV ");
+
+ /* Azalia Controller OEM Codec Table Pointer */
+ FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&PumoriCodecTableList[0]);
+ /* Azalia Controller Front Panel OEM Table Pointer */
+
+ /* Fan Control */
+ oem_fan_control(FchParams_env);
+
+ /* sata configuration */
+ }
+ printk(BIOS_DEBUG, "Done\n");
+
+ return AGESA_SUCCESS;
+}
diff --git a/src/mainboard/amd/parmer/BiosCallOuts.h b/src/mainboard/amd/parmer/BiosCallOuts.h
new file mode 100644
index 0000000..1993c64
--- /dev/null
+++ b/src/mainboard/amd/parmer/BiosCallOuts.h
@@ -0,0 +1,82 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _BIOS_CALLOUT_H_
+#define _BIOS_CALLOUT_H_
+
+#include "Porting.h"
+#include "AGESA.h"
+
+#define REQUIRED_CALLOUTS 12
+#define BIOS_HEAP_START_ADDRESS 0x010000000
+#define BIOS_HEAP_SIZE 0x30000
+#define BSP_STACK_BASE_ADDR 0x30000
+
+
+typedef struct _BIOS_HEAP_MANAGER {
+ //UINT32 AvailableSize;
+ UINT32 StartOfAllocatedNodes;
+ UINT32 StartOfFreedNodes;
+} BIOS_HEAP_MANAGER;
+
+typedef struct _BIOS_BUFFER_NODE {
+ UINT32 BufferHandle;
+ UINT32 BufferSize;
+ UINT32 NextNodeOffset;
+} BIOS_BUFFER_NODE;
+/*
+ * CALLOUTS
+ */
+AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+
+/* REQUIRED CALLOUTS
+ * AGESA ADVANCED CALLOUTS - CPU
+ */
+AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+AGESA_STATUS BiosGetIdsInitData (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+
+/* AGESA ADVANCED CALLOUTS - MEMORY */
+AGESA_STATUS BiosReadSpd (UINT32 Func,UINT32 Data,VOID *ConfigPtr);
+
+/* BIOS DEFAULT RET */
+AGESA_STATUS BiosDefaultRet (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+
+/* Call the host environment interface to provide a user hook opportunity. */
+AGESA_STATUS BiosHookBeforeDQSTraining (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+/* Call the host environment interface to provide a user hook opportunity. */
+AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+/* Call the host environment interface to provide a user hook opportunity. */
+AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+/* PCIE slot reset control */
+AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+/* FCH OEM Config*/
+AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr);
+#define SB_GPIO_REG02 2
+#define SB_GPIO_REG09 9
+#define SB_GPIO_REG10 10
+#define SB_GPIO_REG15 15
+#define SB_GPIO_REG17 17
+#define SB_GPIO_REG21 21
+#define SB_GPIO_REG25 25
+#define SB_GPIO_REG28 28
+#endif //_BIOS_CALLOUT_H_
diff --git a/src/mainboard/amd/parmer/Kconfig b/src/mainboard/amd/parmer/Kconfig
new file mode 100644
index 0000000..3212c44
--- /dev/null
+++ b/src/mainboard/amd/parmer/Kconfig
@@ -0,0 +1,114 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+#
+
+if BOARD_AMD_PARMER
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select ARCH_X86
+ select CPU_AMD_AGESA_FAMILY15_TN
+ select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN_ROOT_COMPLEX
+ select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN
+ select SOUTHBRIDGE_AMD_AGESA_HUDSON
+ select HAVE_BUS_CONFIG
+ select HAVE_OPTION_TABLE
+ select HAVE_PIRQ_TABLE
+ select HAVE_MP_TABLE
+ select HAVE_MAINBOARD_RESOURCES
+ select HAVE_ACPI_RESUME
+ select HAVE_HARD_RESET
+ select SB_HT_CHAIN_UNITID_OFFSET_ONLY
+ select LIFT_BSP_APIC_ID
+ select SERIAL_CPU_INIT
+ select AMDMCT
+ select HAVE_ACPI_TABLES
+ select BOARD_ROMSIZE_KB_4096
+ select TINY_BOOTBLOCK
+ select GFXUMA
+ select UDELAY_LAPIC
+
+config MAINBOARD_DIR
+ string
+ default amd/parmer
+
+config APIC_ID_OFFSET
+ hex
+ default 0x0
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "Parmer"
+
+config HW_MEM_HOLE_SIZEK
+ hex
+ default 0x200000
+
+config MAX_CPUS
+ int
+ default 4
+
+config MAX_PHYSICAL_CPUS
+ int
+ default 1
+
+config HW_MEM_HOLE_SIZE_AUTO_INC
+ bool
+ default n
+
+config MEM_TRAIN_SEQ
+ int
+ default 2
+
+config IRQ_SLOT_COUNT
+ int
+ default 11
+
+config RAMTOP
+ hex
+ default 0x1000000
+
+config HEAP_SIZE
+ hex
+ default 0xc0000
+
+config STACK_SIZE
+ hex
+ default 0x10000
+
+config ACPI_SSDTX_NUM
+ int
+ default 0
+
+config RAMBASE
+ hex
+ default 0x200000
+
+config ONBOARD_VGA_IS_PRIMARY
+ bool
+ default y
+
+config VGA_BIOS_ID
+ string
+ default "1002,9900"
+
+config WARNINGS_ARE_ERRORS
+ bool
+ default n
+
+endif # BOARD_AMD_PARMER
diff --git a/src/mainboard/amd/parmer/Makefile.inc b/src/mainboard/amd/parmer/Makefile.inc
new file mode 100644
index 0000000..e345243
--- /dev/null
+++ b/src/mainboard/amd/parmer/Makefile.inc
@@ -0,0 +1,33 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+#
+
+romstage-y += buildOpts.c
+romstage-y += agesawrapper.c
+romstage-y += dimmSpd.c
+romstage-y += BiosCallOuts.c
+romstage-y += PlatformGnbPcie.c
+
+ramstage-y += buildOpts.c
+ramstage-y += agesawrapper.c
+ramstage-y += dimmSpd.c
+ramstage-y += BiosCallOuts.c
+ramstage-y += PlatformGnbPcie.c
+
+ramstage-y += reset.c
+ramstage-y += pmio.c
diff --git a/src/mainboard/amd/parmer/OptionsIds.h b/src/mainboard/amd/parmer/OptionsIds.h
new file mode 100644
index 0000000..0a1d328
--- /dev/null
+++ b/src/mainboard/amd/parmer/OptionsIds.h
@@ -0,0 +1,67 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/**
+ * @file
+ *
+ * IDS Option File
+ *
+ * This file is used to switch on/off IDS features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: Core
+ * @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $
+ */
+#ifndef _OPTION_IDS_H_
+#define _OPTION_IDS_H_
+
+/**
+ *
+ * This file generates the defaults tables for the Integrated Debug Support
+ * Module. The documented build options are imported from a user controlled
+ * file for processing. The build options for the Integrated Debug Support
+ * Module are listed below:
+ *
+ * IDSOPT_IDS_ENABLED
+ * IDSOPT_ERROR_TRAP_ENABLED
+ * IDSOPT_CONTROL_ENABLED
+ * IDSOPT_TRACING_ENABLED
+ * IDSOPT_PERF_ANALYSIS
+ * IDSOPT_ASSERT_ENABLED
+ * IDS_DEBUG_PORT
+ * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
+ *
+ **/
+
+#define IDSOPT_IDS_ENABLED TRUE
+//#define IDSOPT_CONTROL_ENABLED TRUE
+//#define IDSOPT_TRACING_ENABLED TRUE
+#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE
+//#define IDSOPT_PERF_ANALYSIS TRUE
+#define IDSOPT_ASSERT_ENABLED TRUE
+//#undef IDSOPT_DEBUG_ENABLED
+//#define IDSOPT_DEBUG_ENABLED FALSE
+//#undef IDSOPT_HOST_SIMNOW
+//#define IDSOPT_HOST_SIMNOW FALSE
+//#undef IDSOPT_HOST_HDT
+//#define IDSOPT_HOST_HDT FALSE
+//#define IDS_DEBUG_PORT 0x80
+
+#endif
diff --git a/src/mainboard/amd/parmer/PlatformGnbPcie.c b/src/mainboard/amd/parmer/PlatformGnbPcie.c
new file mode 100644
index 0000000..791540c
--- /dev/null
+++ b/src/mainboard/amd/parmer/PlatformGnbPcie.c
@@ -0,0 +1,203 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "heapManager.h"
+#include "PlatformGnbPcieComplex.h"
+#include "Filecode.h"
+
+#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
+
+PCIe_PORT_DESCRIPTOR PortList [] = {
+ /* PCIe port, Lanes 8:23, PCI Device Number 2 */
+ {
+ 0, /* Descriptor flags */
+ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 23),
+ PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+ },
+ /* PCIe port, Lanes 16:23, PCI Device Number 3 */
+ {
+ 0, /* Descriptor flags */
+ PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 16, 23),
+ PCIE_PORT_DATA_INITIALIZER (PortDisabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+ },
+
+ /* PCIe port, Lanes 4, PCI Device Number 4, PCIE MINI0 */
+ {
+ 0, /* Descriptor flags */
+ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4),
+ PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+ },
+
+ /* PCIe port, Lanes 5, PCI Device Number 5, PCIE MINI1 */
+ {
+ 0, /* Descriptor flags */
+ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5),
+ PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+ },
+
+ /* PCIe port, Lanes 6, PCI Device Number 6, PCIE SLOT1 */
+ {
+ 0, /* Descriptor flags */
+ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6),
+ PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+ },
+
+ /* PCIe port, Lanes 7, PCI Device Number 7, LAN */
+ {
+ 0, /* Descriptor flags */
+ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7),
+ PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+ },
+
+ /* Initialize Port descriptor (PCIe port, Lanes ?, PCI Device Number 8, ...) */
+ {
+ DESCRIPTOR_TERMINATE_LIST, /* Descriptor flags !!!IMPORTANT!!! Terminate last element of array */
+ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3),
+ PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
+ },
+};
+
+PCIe_DDI_DESCRIPTOR DdiList [] = {
+ /* DP0 to HDMI0/DP */
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27),
+ PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux1, Hdp1)
+ },
+ /* DP1 to FCH */
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 28, 31),
+ PCIE_DDI_DATA_INITIALIZER (ConnectorTypeNutmegDpToVga, Aux2, Hdp2)
+ },
+ /* DP2 to HDMI1/DP */
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 32, 35),
+ /* PCIE_DDI_DATA_INITIALIZER (ConnectorTypeEDP, Aux3, Hdp3) */
+ PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux3, Hdp3)
+ },
+ /* GFX Lane 15-12 */
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 12, 15),
+ PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux4, Hdp4)
+ },
+ /* GFX Lane 11-8 */
+ {
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 16, 19),
+ PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux5, Hdp5)
+ },
+ /* GFX Lane 7-4 */
+ {
+ DESCRIPTOR_TERMINATE_LIST,
+ PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 20, 23),
+ PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux6, Hdp6)
+ }
+};
+
+PCIe_COMPLEX_DESCRIPTOR Trinity = {
+ DESCRIPTOR_TERMINATE_LIST,
+ 0,
+ &PortList[0],
+ &DdiList[0]
+};
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * OemCustomizeInitEarly
+ *
+ * Description:
+ * This is the stub function will call the host environment through the binary block
+ * interface (call-out port) to provide a user hook opportunity
+ *
+ * Parameters:
+ * @param[in] **PeiServices
+ * @param[in] *InitEarly
+ *
+ * @retval VOID
+ *
+ **/
+/*---------------------------------------------------------------------------------------*/
+VOID
+OemCustomizeInitEarly (
+ IN OUT AMD_EARLY_PARAMS *InitEarly
+ )
+{
+ AGESA_STATUS Status;
+ VOID *TrinityPcieComplexListPtr;
+ VOID *TrinityPciePortPtr;
+ VOID *TrinityPcieDdiPtr;
+
+ ALLOCATE_HEAP_PARAMS AllocHeapParams;
+
+ /* GNB PCIe topology Porting */
+
+ /* */
+ /* Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR */
+ /* */
+ AllocHeapParams.RequestedBufferSize = (sizeof (PCIe_COMPLEX_DESCRIPTOR) +
+ sizeof (PCIe_PORT_DESCRIPTOR) * 7 +
+ sizeof (PCIe_DDI_DESCRIPTOR)) * 6;
+
+ AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
+ AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
+ Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
+ if ( Status!= AGESA_SUCCESS) {
+ /* Could not allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR */
+ ASSERT(FALSE);
+ return;
+ }
+
+ TrinityPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
+
+ AllocHeapParams.BufferPtr += sizeof (PCIe_COMPLEX_DESCRIPTOR);
+ TrinityPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr;
+
+ AllocHeapParams.BufferPtr += sizeof (PCIe_PORT_DESCRIPTOR) * 7;
+ TrinityPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
+
+ LibAmdMemFill (TrinityPcieComplexListPtr,
+ 0,
+ sizeof (PCIe_COMPLEX_DESCRIPTOR),
+ &InitEarly->StdHeader);
+
+ LibAmdMemFill (TrinityPciePortPtr,
+ 0,
+ sizeof (PCIe_PORT_DESCRIPTOR) * 7,
+ &InitEarly->StdHeader);
+
+ LibAmdMemFill (TrinityPcieDdiPtr,
+ 0,
+ sizeof (PCIe_DDI_DESCRIPTOR) * 6,
+ &InitEarly->StdHeader);
+
+ LibAmdMemCopy (TrinityPcieComplexListPtr, &Trinity, sizeof (PCIe_COMPLEX_DESCRIPTOR), &InitEarly->StdHeader);
+ LibAmdMemCopy (TrinityPciePortPtr, &PortList[0], sizeof (PCIe_PORT_DESCRIPTOR) * 7, &InitEarly->StdHeader);
+ LibAmdMemCopy (TrinityPcieDdiPtr, &DdiList[0], sizeof (PCIe_DDI_DESCRIPTOR) * 6, &InitEarly->StdHeader);
+
+ ((PCIe_COMPLEX_DESCRIPTOR*)TrinityPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)TrinityPciePortPtr;
+ ((PCIe_COMPLEX_DESCRIPTOR*)TrinityPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)TrinityPcieDdiPtr;
+
+ InitEarly->GnbConfig.PcieComplexList = TrinityPcieComplexListPtr;
+}
diff --git a/src/mainboard/amd/parmer/PlatformGnbPcieComplex.h b/src/mainboard/amd/parmer/PlatformGnbPcieComplex.h
new file mode 100644
index 0000000..c10d251
--- /dev/null
+++ b/src/mainboard/amd/parmer/PlatformGnbPcieComplex.h
@@ -0,0 +1,72 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H
+#define _PLATFORM_GNB_PCIE_COMPLEX_H
+
+#include "Porting.h"
+#include "AGESA.h"
+#include "amdlib.h"
+
+//GNB GPP Port4
+#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable
+#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
+#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
+#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
+ //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
+#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
+
+//GNB GPP Port5
+#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable
+#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
+#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
+#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
+ //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
+#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
+
+//GNB GPP Port6
+#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable
+#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
+#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
+#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
+ //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
+#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
+
+//GNB GPP Port7
+#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable
+#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
+#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
+#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
+ //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
+#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
+
+//GNB GPP Port8
+#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable
+#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
+#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
+#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
+ //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
+#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
+
+VOID
+OemCustomizeInitEarly (
+ IN OUT AMD_EARLY_PARAMS *InitEarly
+ );
+
+#endif //_PLATFORM_GNB_PCIE_COMPLEX_H
diff --git a/src/mainboard/amd/parmer/acpi/AmdImc.asl b/src/mainboard/amd/parmer/acpi/AmdImc.asl
new file mode 100644
index 0000000..937c10a
--- /dev/null
+++ b/src/mainboard/amd/parmer/acpi/AmdImc.asl
@@ -0,0 +1,95 @@
+//BTDC Due to IMC Fan, ACPI control codes
+OperationRegion(IMIO, SystemIO, 0x3E, 0x02)
+Field(IMIO , ByteAcc, NoLock, Preserve) {
+ IMCX,8,
+ IMCA,8
+}
+
+IndexField(IMCX, IMCA, ByteAcc, NoLock, Preserve) {
+ Offset(0x80),
+ MSTI, 8,
+ MITS, 8,
+ MRG0, 8,
+ MRG1, 8,
+ MRG2, 8,
+ MRG3, 8,
+}
+
+Method(WACK, 0)
+{
+ Store(0, Local0)
+ While (LNotEqual(Local0, 0xFA)) {
+ Store(MRG0, Local0)
+ Sleep(10)
+ }
+}
+
+//Init
+Method (ITZE, 0)
+{
+ Store(0, MRG0)
+ Store(0xB5, MRG1)
+ Store(0, MRG2)
+ Store(0x96, MSTI)
+ WACK()
+
+ Store(0, MRG0)
+ Store(0, MRG1)
+ Store(0, MRG2)
+ Store(0x80, MSTI)
+ WACK()
+
+ Or(MRG2, 0x01, Local0)
+
+ Store(0, MRG0)
+ Store(0, MRG1)
+ Store(Local0, MRG2)
+ Store(0x81, MSTI)
+ WACK()
+}
+
+//Sleep
+Method (IMSP, 0)
+{
+ Store(0, MRG0)
+ Store(0xB5, MRG1)
+ Store(0, MRG2)
+ Store(0x96, MSTI)
+ WACK()
+
+ Store(0, MRG0)
+ Store(1, MRG1)
+ Store(0, MRG2)
+ Store(0x98, MSTI)
+ WACK()
+
+ Store(0, MRG0)
+ Store(0xB4, MRG1)
+ Store(0, MRG2)
+ Store(0x96, MSTI)
+ WACK()
+}
+
+//Wake
+Method (IMWK, 0)
+{
+ Store(0, MRG0)
+ Store(0xB5, MRG1)
+ Store(0, MRG2)
+ Store(0x96, MSTI)
+ WACK()
+
+ Store(0, MRG0)
+ Store(0, MRG1)
+ Store(0, MRG2)
+ Store(0x80, MSTI)
+ WACK()
+
+ Or(MRG2, 0x01, Local0)
+
+ Store(0, MRG0)
+ Store(0, MRG1)
+ Store(Local0, MRG2)
+ Store(0x81, MSTI)
+ WACK()
+}
diff --git a/src/mainboard/amd/parmer/acpi/ide.asl b/src/mainboard/amd/parmer/acpi/ide.asl
new file mode 100644
index 0000000..765a67e
--- /dev/null
+++ b/src/mainboard/amd/parmer/acpi/ide.asl
@@ -0,0 +1,244 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*
+Scope (_SB) {
+ Device(PCI0) {
+ Device(IDEC) {
+ Name(_ADR, 0x00140001)
+ #include "ide.asl"
+ }
+ }
+}
+*/
+
+/* Some timing tables */
+Name(UDTT, Package(){ /* Udma timing table */
+ 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */
+})
+
+Name(MDTT, Package(){ /* MWDma timing table */
+ 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */
+})
+
+Name(POTT, Package(){ /* Pio timing table */
+ 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */
+})
+
+/* Some timing register value tables */
+Name(MDRT, Package(){ /* MWDma timing register table */
+ 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */
+})
+
+Name(PORT, Package(){
+ 0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */
+})
+
+OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */
+ Field(ICRG, AnyAcc, NoLock, Preserve)
+{
+ PPTS, 8, /* Primary PIO Slave Timing */
+ PPTM, 8, /* Primary PIO Master Timing */
+ OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */
+ PMTM, 8, /* Primary MWDMA Master Timing */
+ OFFSET(0x08), PPCR, 8, /* Primary PIO Control */
+ OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */
+ PPSM, 4, /* Primary PIO slave Mode */
+ OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */
+ OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */
+ PDSM, 4, /* Primary UltraDMA Mode */
+}
+
+Method(GTTM, 1) /* get total time*/
+{
+ Store(And(Arg0, 0x0F), Local0) /* Recovery Width */
+ Increment(Local0)
+ Store(ShiftRight(Arg0, 4), Local1) /* Command Width */
+ Increment(Local1)
+ Return(Multiply(30, Add(Local0, Local1)))
+}
+
+Device(PRID)
+{
+ Name (_ADR, Zero)
+ Method(_GTM, 0)
+ {
+ NAME(OTBF, Buffer(20) { /* out buffer */
+ 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
+ })
+
+ CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */
+ CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */
+ CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */
+ CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */
+ CreateDwordField(OTBF, 16, BFFG) /* buffer flags */
+
+ /* Just return if the channel is disabled */
+ If(And(PPCR, 0x01)) { /* primary PIO control */
+ Return(OTBF)
+ }
+
+ /* Always tell them independent timing available and IOChannelReady used on both drives */
+ Or(BFFG, 0x1A, BFFG)
+
+ Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */
+ Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */
+
+ If(And(PDCR, 0x01)) { /* It's under UDMA mode */
+ Or(BFFG, 0x01, BFFG)
+ Store(DerefOf(Index(UDTT, PDMM)), DSD0)
+ }
+ Else {
+ Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */
+ }
+
+ If(And(PDCR, 0x02)) { /* It's under UDMA mode */
+ Or(BFFG, 0x04, BFFG)
+ Store(DerefOf(Index(UDTT, PDSM)), DSD1)
+ }
+ Else {
+ Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */
+ }
+
+ Return(OTBF) /* out buffer */
+ } /* End Method(_GTM) */
+
+ Method(_STM, 3, NotSerialized)
+ {
+ NAME(INBF, Buffer(20) { /* in buffer */
+ 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
+ })
+
+ CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */
+ CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */
+ CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */
+ CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */
+ CreateDwordField(INBF, 16, BFFG) /*buffer flag */
+
+ Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0)
+ Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */
+ Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1)
+ Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */
+
+ Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */
+ Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */
+
+ If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */
+ Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0)
+ Divide(Local0, 7, PDMM,)
+ Or(PDCR, 0x01, PDCR)
+ }
+ Else {
+ If(LNotEqual(DSD0, 0xFFFFFFFF)) {
+ Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0)
+ Store(DerefOf(Index(MDRT, Local0)), PMTM)
+ }
+ }
+
+ If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */
+ Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0)
+ Divide(Local0, 7, PDSM,)
+ Or(PDCR, 0x02, PDCR)
+ }
+ Else {
+ If(LNotEqual(DSD1, 0xFFFFFFFF)) {
+ Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0)
+ Store(DerefOf(Index(MDRT, Local0)), PMTS)
+ }
+ }
+ /* Return(INBF) */
+ } /*End Method(_STM) */
+ Device(MST)
+ {
+ Name(_ADR, 0)
+ Method(_GTF) {
+ Name(CMBF, Buffer(21) {
+ 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
+ 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
+ })
+ CreateByteField(CMBF, 1, POMD)
+ CreateByteField(CMBF, 8, DMMD)
+ CreateByteField(CMBF, 5, CMDA)
+ CreateByteField(CMBF, 12, CMDB)
+ CreateByteField(CMBF, 19, CMDC)
+
+ Store(0xA0, CMDA)
+ Store(0xA0, CMDB)
+ Store(0xA0, CMDC)
+
+ Or(PPMM, 0x08, POMD)
+
+ If(And(PDCR, 0x01)) {
+ Or(PDMM, 0x40, DMMD)
+ }
+ Else {
+ Store(Match
+ (MDTT, MLE, GTTM(PMTM),
+ MTR, 0, 0), Local0)
+ If(LLess(Local0, 3)) {
+ Or(0x20, Local0, DMMD)
+ }
+ }
+ Return(CMBF)
+ }
+ } /* End Device(MST) */
+
+ Device(SLAV)
+ {
+ Name(_ADR, 1)
+ Method(_GTF) {
+ Name(CMBF, Buffer(21) {
+ 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
+ 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
+ })
+ CreateByteField(CMBF, 1, POMD)
+ CreateByteField(CMBF, 8, DMMD)
+ CreateByteField(CMBF, 5, CMDA)
+ CreateByteField(CMBF, 12, CMDB)
+ CreateByteField(CMBF, 19, CMDC)
+
+ Store(0xB0, CMDA)
+ Store(0xB0, CMDB)
+ Store(0xB0, CMDC)
+
+ Or(PPSM, 0x08, POMD)
+
+ If(And(PDCR, 0x02)) {
+ Or(PDSM, 0x40, DMMD)
+ }
+ Else {
+ Store(Match
+ (MDTT, MLE, GTTM(PMTS),
+ MTR, 0, 0), Local0)
+ If(LLess(Local0, 3)) {
+ Or(0x20, Local0, DMMD)
+ }
+ }
+ Return(CMBF)
+ }
+ } /* End Device(SLAV) */
+}
diff --git a/src/mainboard/amd/parmer/acpi/routing.asl b/src/mainboard/amd/parmer/acpi/routing.asl
new file mode 100644
index 0000000..cc03701
--- /dev/null
+++ b/src/mainboard/amd/parmer/acpi/routing.asl
@@ -0,0 +1,356 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*
+DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
+ )
+ {
+ #include "routing.asl"
+ }
+*/
+
+/* Routing is in System Bus scope */
+Scope(\_SB) {
+ Name(PR0, Package(){
+ /* NB devices */
+ /* Bus 0, Dev 0 - F15 Host Controller */
+ /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
+ Package(){0x0001FFFF, 0, INTB, 0 },
+ Package(){0x0001FFFF, 1, INTC, 0 },
+
+ /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
+ Package(){0x0002FFFF, 0, INTC, 0 },
+ Package(){0x0002FFFF, 1, INTD, 0 },
+ Package(){0x0002FFFF, 2, INTA, 0 },
+ Package(){0x0002FFFF, 3, INTB, 0 },
+
+ /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
+ Package(){0x0003FFFF, 0, INTD, 0 },
+ Package(){0x0003FFFF, 1, INTA, 0 },
+ Package(){0x0003FFFF, 2, INTB, 0 },
+ Package(){0x0003FFFF, 3, INTC, 0 },
+
+ /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
+ Package(){0x0004FFFF, 0, INTA, 0 },
+ Package(){0x0004FFFF, 1, INTB, 0 },
+ Package(){0x0004FFFF, 2, INTC, 0 },
+ Package(){0x0004FFFF, 3, INTD, 0 },
+
+ /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
+ Package(){0x0005FFFF, 0, INTB, 0 },
+ Package(){0x0005FFFF, 1, INTC, 0 },
+ Package(){0x0005FFFF, 2, INTD, 0 },
+ Package(){0x0005FFFF, 3, INTA, 0 },
+
+ /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
+ Package(){0x0006FFFF, 0, INTC, 0 },
+ Package(){0x0006FFFF, 1, INTD, 0 },
+ Package(){0x0006FFFF, 2, INTA, 0 },
+ Package(){0x0006FFFF, 3, INTB, 0 },
+
+ /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
+ Package(){0x0007FFFF, 0, INTD, 0 },
+ Package(){0x0007FFFF, 1, INTA, 0 },
+ Package(){0x0007FFFF, 2, INTB, 0 },
+ Package(){0x0007FFFF, 3, INTC, 0 },
+
+ /* Bus 0, Funct 8 - Southbridge port (normally hidden) */
+
+ /* SB devices */
+ /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */
+ Package(){0x0014FFFF, 0, INTA, 0 },
+ Package(){0x0014FFFF, 1, INTB, 0 },
+ Package(){0x0014FFFF, 2, INTC, 0 },
+ Package(){0x0014FFFF, 3, INTD, 0 },
+
+ /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
+ * EHCI, dev 18, 19 func 2 */
+ Package(){0x0012FFFF, 0, INTC, 0 },
+ Package(){0x0012FFFF, 1, INTB, 0 },
+
+ Package(){0x0013FFFF, 0, INTC, 0 },
+ Package(){0x0013FFFF, 1, INTB, 0 },
+
+ Package(){0x0016FFFF, 0, INTC, 0 },
+ Package(){0x0016FFFF, 1, INTB, 0 },
+
+ /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */
+ Package(){0x0010FFFF, 0, INTC, 0 },
+ Package(){0x0010FFFF, 1, INTB, 0 },
+
+ /* Bus 0, Dev 17 - SATA controller */
+ Package(){0x0011FFFF, 0, INTD, 0 },
+
+ /* Bus 0, Dev 21 Pcie Bridge */
+ Package(){0x0015FFFF, 0, INTA, 0 },
+ Package(){0x0015FFFF, 1, INTB, 0 },
+ Package(){0x0015FFFF, 2, INTC, 0 },
+ Package(){0x0015FFFF, 3, INTD, 0 },
+ })
+
+ Name(APR0, Package(){
+ /* NB devices in APIC mode */
+ /* Bus 0, Dev 0 - F15 Host Controller */
+
+ /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
+ Package(){0x0001FFFF, 0, 0, 17 },
+ package(){0x0001FFFF, 1, 0, 18 },
+
+ /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
+ Package(){0x0002FFFF, 0, 0, 18 },
+ Package(){0x0002FFFF, 1, 0, 19 },
+ Package(){0x0002FFFF, 2, 0, 16 },
+ Package(){0x0002FFFF, 3, 0, 17 },
+
+ /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
+ Package(){0x0003FFFF, 0, 0, 19 },
+ Package(){0x0003FFFF, 1, 0, 16 },
+ Package(){0x0003FFFF, 2, 0, 17 },
+ Package(){0x0003FFFF, 3, 0, 18 },
+
+ /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
+ Package(){0x0004FFFF, 0, 0, 16 },
+ Package(){0x0004FFFF, 1, 0, 17 },
+ Package(){0x0004FFFF, 2, 0, 18 },
+ Package(){0x0004FFFF, 3, 0, 19 },
+
+ /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
+ Package(){0x0005FFFF, 0, 0, 17 },
+ Package(){0x0005FFFF, 1, 0, 18 },
+ Package(){0x0005FFFF, 2, 0, 19 },
+ Package(){0x0005FFFF, 3, 0, 16 },
+
+ /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
+ Package(){0x0006FFFF, 0, 0, 18 },
+ Package(){0x0006FFFF, 1, 0, 19 },
+ Package(){0x0006FFFF, 2, 0, 16 },
+ Package(){0x0006FFFF, 3, 0, 17 },
+
+ /* Bus 0, Dev 7 - PCIe Bridge for network card */
+ Package(){0x0007FFFF, 0, 0, 19 },
+ Package(){0x0007FFFF, 1, 0, 16 },
+ Package(){0x0007FFFF, 2, 0, 17 },
+ Package(){0x0007FFFF, 3, 0, 18 },
+
+ /* Bus 0, Funct 8 - Southbridge port (normally hidden) */
+
+ /* SB devices in APIC mode */
+ /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
+ Package(){0x0014FFFF, 0, 0, 16 },
+ Package(){0x0014FFFF, 1, 0, 17 },
+ Package(){0x0014FFFF, 2, 0, 18 },
+ Package(){0x0014FFFF, 3, 0, 19 },
+
+ /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
+ * EHCI, dev 18, 19 func 2 */
+ Package(){0x0012FFFF, 0, 0, 18 },
+ Package(){0x0012FFFF, 1, 0, 17 },
+
+ Package(){0x0013FFFF, 0, 0, 18 },
+ Package(){0x0013FFFF, 1, 0, 17 },
+
+ Package(){0x0016FFFF, 0, 0, 18 },
+ Package(){0x0016FFFF, 1, 0, 17 },
+
+ /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */
+ Package(){0x0010FFFF, 0, 0, 0x12},
+ Package(){0x0010FFFF, 1, 0, 0x11},
+
+ /* Bus 0, Dev 17 - SATA controller */
+ Package(){0x0011FFFF, 0, 0, 19 },
+
+ /* Bus0, Dev 21 PCIE Bridge */
+ Package(){0x0015FFFF, 0, 0, 16 },
+ Package(){0x0015FFFF, 1, 0, 17 },
+ Package(){0x0015FFFF, 2, 0, 18 },
+ Package(){0x0015FFFF, 3, 0, 19 },
+ })
+
+ Name(PS2, Package(){
+ /* The external GFX - Hooked to PCIe slot 2 */
+ Package(){0x0000FFFF, 0, INTC, 0 },
+ Package(){0x0000FFFF, 1, INTD, 0 },
+ Package(){0x0000FFFF, 2, INTA, 0 },
+ Package(){0x0000FFFF, 3, INTB, 0 },
+ })
+ Name(APS2, Package(){
+ /* The external GFX - Hooked to PCIe slot 2 */
+ Package(){0x0000FFFF, 0, 0, 18 },
+ Package(){0x0000FFFF, 1, 0, 19 },
+ Package(){0x0000FFFF, 2, 0, 16 },
+ Package(){0x0000FFFF, 3, 0, 17 },
+ })
+
+#if 0 //parmer not use
+ Name(PS3, Package(){
+ /* The external GFX - Hooked to PCIe slot 3 */
+ Package(){0x0000FFFF, 0, INTD, 0 },
+ Package(){0x0000FFFF, 1, INTA, 0 },
+ Package(){0x0000FFFF, 2, INTB, 0 },
+ Package(){0x0000FFFF, 3, INTC, 0 },
+ })
+ Name(APS3, Package(){
+ /* The external GFX - Hooked to PCIe slot 3 */
+ Package(){0x0000FFFF, 0, 0, 19 },
+ Package(){0x0000FFFF, 1, 0, 16 },
+ Package(){0x0000FFFF, 2, 0, 17 },
+ Package(){0x0000FFFF, 3, 0, 18 },
+ })
+#endif
+
+ Name(PS4, Package(){
+ /* PCIe slot - Hooked to PCIe slot 4 */
+ Package(){0x0000FFFF, 0, INTA, 0 },
+ Package(){0x0000FFFF, 1, INTB, 0 },
+ Package(){0x0000FFFF, 2, INTC, 0 },
+ Package(){0x0000FFFF, 3, INTD, 0 },
+ })
+ Name(APS4, Package(){
+ /* PCIe slot - Hooked to PCIe slot 4 */
+ Package(){0x0000FFFF, 0, 0, 16 },
+ Package(){0x0000FFFF, 1, 0, 17 },
+ Package(){0x0000FFFF, 2, 0, 18 },
+ Package(){0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name(PS5, Package(){
+ /* PCIe slot - Hooked to PCIe slot 5 */
+ Package(){0x0000FFFF, 0, INTB, 0 },
+ Package(){0x0000FFFF, 1, INTC, 0 },
+ Package(){0x0000FFFF, 2, INTD, 0 },
+ Package(){0x0000FFFF, 3, INTA, 0 },
+ })
+ Name(APS5, Package(){
+ /* PCIe slot - Hooked to PCIe slot 5 */
+ Package(){0x0000FFFF, 0, 0, 17 },
+ Package(){0x0000FFFF, 1, 0, 18 },
+ Package(){0x0000FFFF, 2, 0, 19 },
+ Package(){0x0000FFFF, 3, 0, 16 },
+ })
+
+ Name(PS6, Package(){
+ /* PCIe slot - Hooked to PCIe slot 6 */
+ Package(){0x0000FFFF, 0, INTC, 0 },
+ Package(){0x0000FFFF, 1, INTD, 0 },
+ Package(){0x0000FFFF, 2, INTA, 0 },
+ Package(){0x0000FFFF, 3, INTB, 0 },
+ })
+ Name(APS6, Package(){
+ /* PCIe slot - Hooked to PCIe slot 6 */
+ Package(){0x0000FFFF, 0, 0, 18 },
+ Package(){0x0000FFFF, 1, 0, 19 },
+ Package(){0x0000FFFF, 2, 0, 16 },
+ Package(){0x0000FFFF, 3, 0, 17 },
+ })
+
+ Name(PS7, Package(){
+ /* The onboard Ethernet chip - Dev 7 Parmer Hooked to RTK8111E Ethernet Card x1 Device7-GPP3 J16B*/
+ Package(){0x0000FFFF, 0, INTD, 0 },
+ Package(){0x0000FFFF, 1, INTA, 0 },
+ Package(){0x0000FFFF, 2, INTB, 0 },
+ Package(){0x0000FFFF, 3, INTC, 0 },
+ })
+ Name(APS7, Package(){
+ /* The onboard Ethernet chip - Dev 7 Parmer Hooked to RTK8111E Ethernet Card x1 Device7-GPP3 J16B*/
+ Package(){0x0000FFFF, 0, 0, 19 },
+ Package(){0x0000FFFF, 1, 0, 16 },
+ Package(){0x0000FFFF, 2, 0, 17 },
+ Package(){0x0000FFFF, 3, 0, 18 },
+ })
+
+ Name(PE0, Package(){
+ /* PCIe slot - Hooked to PCIe Bridge 0*/
+ Package(){0x0000FFFF, 0, INTA, 0 },
+ Package(){0x0000FFFF, 1, INTB, 0 },
+ Package(){0x0000FFFF, 2, INTC, 0 },
+ Package(){0x0000FFFF, 3, INTD, 0 },
+ })
+ Name(APE0, Package(){
+ /* PCIe slot - Hooked to PCIe Bridge 0*/
+ Package(){0x0000FFFF, 0, 0, 16 },
+ Package(){0x0000FFFF, 1, 0, 17 },
+ Package(){0x0000FFFF, 2, 0, 18 },
+ Package(){0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name(PE1, Package(){
+ /* PCIe slot - Hooked to PCIe Bridge 1*/
+ Package(){0x0000FFFF, 0, INTB, 0 },
+ Package(){0x0000FFFF, 1, INTC, 0 },
+ Package(){0x0000FFFF, 2, INTD, 0 },
+ Package(){0x0000FFFF, 3, INTA, 0 },
+ })
+ Name(APE1, Package(){
+ /* PCIe slot - Hooked to PCIe Bridge 1*/
+ Package(){0x0000FFFF, 0, 0, 17 },
+ Package(){0x0000FFFF, 1, 0, 18 },
+ Package(){0x0000FFFF, 2, 0, 19 },
+ Package(){0x0000FFFF, 3, 0, 16 },
+ })
+
+ Name(PE2, Package(){
+ /* PCIe slot - Hooked to PCIe Bridge 2*/
+ Package(){0x0000FFFF, 0, INTC, 0 },
+ Package(){0x0000FFFF, 1, INTD, 0 },
+ Package(){0x0000FFFF, 2, INTA, 0 },
+ Package(){0x0000FFFF, 3, INTB, 0 },
+ })
+ Name(APE2, Package(){
+ /* PCIe slot - Hooked to PCIe Bridge 2*/
+ Package(){0x0000FFFF, 0, 0, 18 },
+ Package(){0x0000FFFF, 1, 0, 19 },
+ Package(){0x0000FFFF, 2, 0, 16 },
+ Package(){0x0000FFFF, 3, 0, 17 },
+ })
+
+ Name(PE3, Package(){
+ /* PCIe slot - Hooked to PCIe Bridge 3 */
+ Package(){0x0000FFFF, 0, INTD, 0 },
+ Package(){0x0000FFFF, 1, INTA, 0 },
+ Package(){0x0000FFFF, 2, INTB, 0 },
+ Package(){0x0000FFFF, 3, INTC, 0 },
+ })
+ Name(APE3, Package(){
+ /* PCIe slot - Hooked to PCIe Bridge 3*/
+ Package(){0x0000FFFF, 0, 0, 19 },
+ Package(){0x0000FFFF, 1, 0, 16 },
+ Package(){0x0000FFFF, 2, 0, 17 },
+ Package(){0x0000FFFF, 3, 0, 18 },
+ })
+
+ /* SB PCI Bridge J21, J22 */
+ Name(PCIB, Package(){
+ /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */
+ Package(){0x0005FFFF, 0, 0, 0x14 },
+ Package(){0x0005FFFF, 1, 0, 0x15 },
+ Package(){0x0005FFFF, 2, 0, 0x16 },
+ Package(){0x0005FFFF, 3, 0, 0x17 },
+
+ Package(){0x0006FFFF, 0, 0, 0x15 },
+ Package(){0x0006FFFF, 1, 0, 0x16 },
+ Package(){0x0006FFFF, 2, 0, 0x17 },
+ Package(){0x0006FFFF, 3, 0, 0x14 },
+/*
+ Package(){0x0007FFFF, 0, 0, 0x16 },
+ Package(){0x0007FFFF, 1, 0, 0x17 },
+ Package(){0x0007FFFF, 2, 0, 0x14 },
+ Package(){0x0007FFFF, 3, 0, 0x15 },
+*/
+ })
+}
diff --git a/src/mainboard/amd/parmer/acpi/sata.asl b/src/mainboard/amd/parmer/acpi/sata.asl
new file mode 100644
index 0000000..8fd9e9b
--- /dev/null
+++ b/src/mainboard/amd/parmer/acpi/sata.asl
@@ -0,0 +1,148 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* simple name description */
+
+/*
+Scope (_SB) {
+ Device(PCI0) {
+ Device(SATA) {
+ Name(_ADR, 0x00110000)
+ #include "sata.asl"
+ }
+ }
+}
+*/
+
+Name(STTM, Buffer(20) {
+ 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
+ 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
+ 0x1f, 0x00, 0x00, 0x00
+})
+
+/* Start by clearing the PhyRdyChg bits */
+Method(_INI) {
+ \_GPE._L1F()
+}
+
+Device(PMRY)
+{
+ Name(_ADR, 0)
+ Method(_GTM, 0x0, NotSerialized) {
+ Return(STTM)
+ }
+ Method(_STM, 0x3, NotSerialized) {}
+
+ Device(PMST) {
+ Name(_ADR, 0)
+ Method(_STA,0) {
+ if (LGreater(P0IS,0)) {
+ return (0x0F) /* sata is visible */
+ }
+ else {
+ return (0x00) /* sata is missing */
+ }
+ }
+ }/* end of PMST */
+
+ Device(PSLA)
+ {
+ Name(_ADR, 1)
+ Method(_STA,0) {
+ if (LGreater(P1IS,0)) {
+ return (0x0F) /* sata is visible */
+ }
+ else {
+ return (0x00) /* sata is missing */
+ }
+ }
+ } /* end of PSLA */
+} /* end of PMRY */
+
+Device(SEDY)
+{
+ Name(_ADR, 1) /* IDE Scondary Channel */
+ Method(_GTM, 0x0, NotSerialized) {
+ Return(STTM)
+ }
+ Method(_STM, 0x3, NotSerialized) {}
+
+ Device(SMST)
+ {
+ Name(_ADR, 0)
+ Method(_STA,0) {
+ if (LGreater(P2IS,0)) {
+ return (0x0F) /* sata is visible */
+ }
+ else {
+ return (0x00) /* sata is missing */
+ }
+ }
+ } /* end of SMST */
+
+ Device(SSLA)
+ {
+ Name(_ADR, 1)
+ Method(_STA,0) {
+ if (LGreater(P3IS,0)) {
+ return (0x0F) /* sata is visible */
+ }
+ else {
+ return (0x00) /* sata is missing */
+ }
+ }
+ } /* end of SSLA */
+} /* end of SEDY */
+
+/* SATA Hot Plug Support */
+Scope(\_GPE) {
+ Method(_L1F,0x0,NotSerialized) {
+ if (\_SB.P0PR) {
+ if (LGreater(\_SB.P0IS,0)) {
+ sleep(32)
+ }
+ Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */
+ store(one, \_SB.P0PR)
+ }
+
+ if (\_SB.P1PR) {
+ if (LGreater(\_SB.P1IS,0)) {
+ sleep(32)
+ }
+ Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
+ store(one, \_SB.P1PR)
+ }
+
+ if (\_SB.P2PR) {
+ if (LGreater(\_SB.P2IS,0)) {
+ sleep(32)
+ }
+ Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */
+ store(one, \_SB.P2PR)
+ }
+
+ if (\_SB.P3PR) {
+ if (LGreater(\_SB.P3IS,0)) {
+ sleep(32)
+ }
+ Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
+ store(one, \_SB.P3PR)
+ }
+ }
+}
diff --git a/src/mainboard/amd/parmer/acpi/usb.asl b/src/mainboard/amd/parmer/acpi/usb.asl
new file mode 100644
index 0000000..7780a15
--- /dev/null
+++ b/src/mainboard/amd/parmer/acpi/usb.asl
@@ -0,0 +1,114 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* simple name description */
+/*
+DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
+ )
+ {
+ #include "usb.asl"
+ }
+*/
+Method(UCOC, 0) {
+ Sleep(20)
+ Store(0x13,CMTI)
+ Store(0,GPSL)
+}
+
+/* USB Port 0 overcurrent uses Gpm 0 */
+If(LLessEqual(UOM0,9)) {
+ Scope (\_GPE) {
+ Method (_L13) {
+ }
+ }
+}
+
+/* USB Port 1 overcurrent uses Gpm 1 */
+If (LLessEqual(UOM1,9)) {
+ Scope (\_GPE) {
+ Method (_L14) {
+ }
+ }
+}
+
+/* USB Port 2 overcurrent uses Gpm 2 */
+If (LLessEqual(UOM2,9)) {
+ Scope (\_GPE) {
+ Method (_L15) {
+ }
+ }
+}
+
+/* USB Port 3 overcurrent uses Gpm 3 */
+If (LLessEqual(UOM3,9)) {
+ Scope (\_GPE) {
+ Method (_L16) {
+ }
+ }
+}
+
+/* USB Port 4 overcurrent uses Gpm 4 */
+If (LLessEqual(UOM4,9)) {
+ Scope (\_GPE) {
+ Method (_L19) {
+ }
+ }
+}
+
+/* USB Port 5 overcurrent uses Gpm 5 */
+If (LLessEqual(UOM5,9)) {
+ Scope (\_GPE) {
+ Method (_L1A) {
+ }
+ }
+}
+
+/* USB Port 6 overcurrent uses Gpm 6 */
+If (LLessEqual(UOM6,9)) {
+ Scope (\_GPE) {
+ /* Method (_L1C) { */
+ Method (_L06) {
+ }
+ }
+}
+
+/* USB Port 7 overcurrent uses Gpm 7 */
+If (LLessEqual(UOM7,9)) {
+ Scope (\_GPE) {
+ /* Method (_L1D) { */
+ Method (_L07) {
+ }
+ }
+}
+
+/* USB Port 8 overcurrent uses Gpm 8 */
+If (LLessEqual(UOM8,9)) {
+ Scope (\_GPE) {
+ Method (_L17) {
+ }
+ }
+}
+
+/* USB Port 9 overcurrent uses Gpm 9 */
+If (LLessEqual(UOM9,9)) {
+ Scope (\_GPE) {
+ Method (_L0E) {
+ }
+ }
+}
diff --git a/src/mainboard/amd/parmer/acpi_tables.c b/src/mainboard/amd/parmer/acpi_tables.c
new file mode 100644
index 0000000..c699d5b
--- /dev/null
+++ b/src/mainboard/amd/parmer/acpi_tables.c
@@ -0,0 +1,329 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <string.h>
+#include <arch/acpi.h>
+#include <arch/acpigen.h>
+#include <arch/ioapic.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <cpu/x86/msr.h>
+#include "agesawrapper.h"
+#include <cpu/amd/mtrr.h>
+#include <cpu/amd/amdfam15.h>
+
+#include "agesawrapper.h"
+
+#define DUMP_ACPI_TABLES 0
+
+#if DUMP_ACPI_TABLES == 1
+
+static void dump_mem(u32 start, u32 end)
+{
+ u32 i;
+ print_debug("dump_mem:");
+ for (i = start; i < end; i++) {
+ if ((i & 0xf) == 0) {
+ printk(BIOS_DEBUG, "\n%08x:", i);
+ }
+ printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i));
+ }
+ print_debug("\n");
+}
+#endif
+
+extern const unsigned char AmlCode[];
+
+unsigned long acpi_fill_mcfg(unsigned long current)
+{
+ /* Just a dummy */
+ return current;
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+ /* create all subtables for processors */
+ current = acpi_create_madt_lapics(current);
+
+ /* Write SB800 IOAPIC, only one */
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS,
+ IO_APIC_ADDR, 0);
+
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 0, 2, 0);
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 9, 9, 0xF);
+ /* 0: mean bus 0--->ISA */
+ /* 0: PIC 0 */
+ /* 2: APIC 2 */
+ /* 5 mean: 0101 --> Edige-triggered, Active high */
+
+ /* create all subtables for processors */
+ current += acpi_create_madt_lapic_nmi(current, 0xff, 5, 1);
+ /* 1: LINT1 connect to NMI */
+
+ return current;
+}
+
+unsigned long acpi_fill_hest(acpi_hest_t *hest)
+{
+ void *addr, *current;
+
+ /* Skip the HEST header. */
+ current = (void *)(hest + 1);
+
+ addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE);
+ if (addr != NULL)
+ current += acpi_create_hest_error_source(hest, current, 0, (void *)((u32)addr + 2), *(UINT16 *)addr - 2);
+
+ addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC);
+ if (addr != NULL)
+ current += acpi_create_hest_error_source(hest, current, 1, (void *)((u32)addr + 2), *(UINT16 *)addr - 2);
+
+ return (unsigned long)current;
+}
+
+unsigned long acpi_fill_slit(unsigned long current)
+{
+ /* Not implemented */
+ return current;
+}
+
+unsigned long acpi_fill_srat(unsigned long current)
+{
+ /* No NUMA, no SRAT */
+ return current;
+}
+
+unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id)
+{
+ int lens;
+ msr_t msr;
+ char pscope[] = "\\_SB.PCI0";
+
+ lens = acpigen_write_scope(pscope);
+ msr = rdmsr(TOP_MEM);
+ lens += acpigen_write_name_dword("TOM1", msr.lo);
+ msr = rdmsr(TOP_MEM2);
+ /*
+ * Since XP only implements parts of ACPI 2.0, we can't use a qword
+ * here.
+ * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt
+ * slide 22ff.
+ * Shift value right by 20 bit to make it fit into 32bit,
+ * giving us 1MB granularity and a limit of almost 4Exabyte of memory.
+ */
+ lens += acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20);
+ acpigen_patch_len(lens - 1);
+ return (unsigned long) (acpigen_get_current());
+}
+
+unsigned long write_acpi_tables(unsigned long start)
+{
+ unsigned long current;
+ acpi_rsdp_t *rsdp;
+ acpi_rsdt_t *rsdt;
+ acpi_hpet_t *hpet;
+ acpi_madt_t *madt;
+ acpi_srat_t *srat;
+ acpi_slit_t *slit;
+ acpi_fadt_t *fadt;
+ acpi_facs_t *facs;
+ acpi_header_t *dsdt;
+ acpi_header_t *ssdt;
+ acpi_header_t *alib;
+ acpi_header_t *ivrs;
+ acpi_hest_t *hest;
+
+ get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */
+
+ /* Align ACPI tables to 16 bytes */
+ start = (start + 0x0f) & -0x10;
+ current = start;
+
+ printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
+
+ /* We need at least an RSDP and an RSDT Table */
+ rsdp = (acpi_rsdp_t *) current;
+ current += sizeof(acpi_rsdp_t);
+ rsdt = (acpi_rsdt_t *) current;
+ current += sizeof(acpi_rsdt_t);
+
+ /* clear all table memory */
+ memset((void *)start, 0, current - start);
+
+ acpi_write_rsdp(rsdp, rsdt, NULL);
+ acpi_write_rsdt(rsdt);
+
+ /* DSDT */
+ current = (current + 0x07) & -0x08;
+ printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current);
+ dsdt = (acpi_header_t *)current; /* it will used by fadt */
+ memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
+ current += dsdt->length;
+ memcpy(dsdt, &AmlCode, dsdt->length);
+ printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length);
+
+ /* FACS */ /* it needs 64 bit alignment */
+ current = (current + 0x07) & -0x08;
+ printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current);
+ facs = (acpi_facs_t *) current; /* it will be used by fadt */
+ current += sizeof(acpi_facs_t);
+ acpi_create_facs(facs);
+
+ /* FADT */
+ current = (current + 0x07) & -0x08;
+ printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current);
+ fadt = (acpi_fadt_t *) current;
+ current += sizeof(acpi_fadt_t);
+
+ acpi_create_fadt(fadt, facs, dsdt);
+ acpi_add_table(rsdp, fadt);
+
+ /*
+ * We explicitly add these tables later on:
+ */
+ current = (current + 0x07) & -0x08;
+ printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current);
+ hpet = (acpi_hpet_t *) current;
+ current += sizeof(acpi_hpet_t);
+ acpi_create_hpet(hpet);
+ acpi_add_table(rsdp, hpet);
+
+ /* If we want to use HPET Timers Linux wants an MADT */
+ current = (current + 0x07) & -0x08;
+ printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current);
+ madt = (acpi_madt_t *) current;
+ acpi_create_madt(madt);
+ current += madt->header.length;
+ acpi_add_table(rsdp, madt);
+
+ /* HEST */
+ current = (current + 0x07) & -0x08;
+ hest = (acpi_hest_t *)current;
+ acpi_write_hest((void *)current);
+ acpi_add_table(rsdp, (void *)current);
+ current += ((acpi_header_t *)current)->length;
+
+ current = (current + 0x07) & -0x08;
+ printk(BIOS_DEBUG, "ACPI: * IVRS at %lx\n", current);
+ ivrs = agesawrapper_getlateinitptr(PICK_IVRS);
+ if (ivrs != NULL) {
+ memcpy((void *)current, ivrs, ivrs->length);
+ ivrs = (acpi_header_t *) current;
+ current += ivrs->length;
+ acpi_add_table(rsdp, ivrs);
+ } else {
+ printk(BIOS_DEBUG, " AGESA IVRS table NULL. Skipping.\n");
+ }
+
+ /* SRAT */
+ current = (current + 0x07) & -0x08;
+ printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current);
+ srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT);
+ if (srat != NULL) {
+ memcpy((void *)current, srat, srat->header.length);
+ srat = (acpi_srat_t *) current;
+ current += srat->header.length;
+ acpi_add_table(rsdp, srat);
+ } else {
+ printk(BIOS_DEBUG, " AGESA SRAT table NULL. Skipping.\n");
+ }
+
+ /* SLIT */
+ current = (current + 0x07) & -0x08;
+ printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current);
+ slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT);
+ if (slit != NULL) {
+ memcpy((void *)current, slit, slit->header.length);
+ slit = (acpi_slit_t *) current;
+ current += slit->header.length;
+ acpi_add_table(rsdp, slit);
+ } else {
+ printk(BIOS_DEBUG, " AGESA SLIT table NULL. Skipping.\n");
+ }
+
+ /* ALIB */
+ current = (current + 0x0f) & -0x10;
+ printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current);
+ alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB);
+ if (alib != NULL) {
+ memcpy((void *)current, alib, alib->length);
+ alib = (acpi_header_t *) current;
+ current += alib->length;
+ acpi_add_table(rsdp, (void *)alib);
+ }
+ else {
+ printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n");
+ }
+
+ /* this pstate ssdt may cause Blue Screen: Fixed: Keep this comment for a while. */
+ /* SSDT */
+ current = ( current + 0x0f) & -0x10;
+ printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current);
+ ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE);
+ if (ssdt != NULL) {
+ memcpy((void *)current, ssdt, ssdt->length);
+ ssdt = (acpi_header_t *) current;
+ current += ssdt->length;
+ }
+ else {
+ printk(BIOS_DEBUG, " AGESA PState table NULL. Skipping.\n");
+ }
+ acpi_add_table(rsdp,ssdt);
+
+ printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current);
+
+ printk(BIOS_DEBUG, "ACPI: * SSDT\n");
+ ssdt = (acpi_header_t *)current;
+
+ acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR);
+ current += ssdt->length;
+ acpi_add_table(rsdp, ssdt);
+
+#if DUMP_ACPI_TABLES == 1
+ printk(BIOS_DEBUG, "rsdp\n");
+ dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t));
+
+ printk(BIOS_DEBUG, "rsdt\n");
+ dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t));
+
+ printk(BIOS_DEBUG, "madt\n");
+ dump_mem(madt, ((void *)madt) + madt->header.length);
+
+ printk(BIOS_DEBUG, "srat\n");
+ dump_mem(srat, ((void *)srat) + srat->header.length);
+
+ printk(BIOS_DEBUG, "slit\n");
+ dump_mem(slit, ((void *)slit) + slit->header.length);
+
+ printk(BIOS_DEBUG, "ssdt\n");
+ dump_mem(ssdt, ((void *)ssdt) + ssdt->length);
+
+ printk(BIOS_DEBUG, "fadt\n");
+ dump_mem(fadt, ((void *)fadt) + fadt->header.length);
+
+ printk(BIOS_DEBUG, "hest\n");
+ dump_mem(hest, ((void *)hest) + hest->header.length);
+#endif
+
+ printk(BIOS_INFO, "ACPI: done.\n");
+ return current;
+}
diff --git a/src/mainboard/amd/parmer/agesawrapper.c b/src/mainboard/amd/parmer/agesawrapper.c
new file mode 100644
index 0000000..ff36750
--- /dev/null
+++ b/src/mainboard/amd/parmer/agesawrapper.c
@@ -0,0 +1,768 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*----------------------------------------------------------------------------------------
+ * M O D U L E S U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include "agesawrapper.h"
+#include "BiosCallOuts.h"
+#include "cpuRegisters.h"
+#include "cpuCacheInit.h"
+#include "cpuApicUtilities.h"
+#include "cpuEarlyInit.h"
+#include "cpuLateInit.h"
+#include "Dispatcher.h"
+#include "cpuCacheInit.h"
+#include "amdlib.h"
+#include "PlatformGnbPcieComplex.h"
+#include "Filecode.h"
+#include "heapManager.h"
+#include "FchPlatform.h"
+#include "Fch.h"
+#include <cpu/amd/agesa/s3_resume.h>
+#include <cbmem.h>
+#include <arch/acpi.h>
+#include <arch/io.h>
+
+VOID FchInitS3LateRestore (IN FCH_DATA_BLOCK *FchDataPtr);
+VOID FchInitS3EarlyRestore (IN FCH_DATA_BLOCK *FchDataPtr);
+
+#define FILECODE UNASSIGNED_FILE_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ * D E F I N I T I O N S A N D M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/* ACPI table pointers returned by AmdInitLate */
+VOID *DmiTable = NULL;
+VOID *AcpiPstate = NULL;
+VOID *AcpiSrat = NULL;
+VOID *AcpiSlit = NULL;
+
+VOID *AcpiWheaMce = NULL;
+VOID *AcpiWheaCmc = NULL;
+VOID *AcpiAlib = NULL;
+VOID *AcpiIvrs = NULL;
+
+/*----------------------------------------------------------------------------------------
+ * T Y P E D E F S A N D S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ * P R O T O T Y P E S O F L O C A L F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ * E X P O R T E D F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------
+ * L O C A L F U N C T I O N S
+ *---------------------------------------------------------------------------------------
+ */
+UINT32
+agesawrapper_amdinitcpuio (
+ VOID
+ )
+{
+ AGESA_STATUS Status;
+ UINT64 MsrReg;
+ UINT32 PciData;
+ PCI_ADDR PciAddress;
+ AMD_CONFIG_PARAMS StdHeader;
+
+ /* Enable legacy video routing: D18F1xF4 VGA Enable */
+ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4);
+ PciData = 1;
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+
+ /* The platform BIOS needs to ensure the memory ranges of SB800 legacy
+ * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are
+ * set to non-posted regions.
+ */
+ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84);
+ PciData = 0x00FEDF00; /* last address before processor local APIC at FEE00000 */
+ PciData |= 1 << 7; /* set NP (non-posted) bit */
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80);
+ PciData = (0xFED00000 >> 8) | 3; /* lowest NP address is HPET at FED00000 */
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+
+ /* Map the remaining PCI hole as posted MMIO */
+ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C);
+ PciData = 0x00FECF00; /* last address before non-posted range */
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+ LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
+ MsrReg = (MsrReg >> 8) | 3;
+ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88);
+ PciData = (UINT32)MsrReg;
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+
+ /* Send all IO (0000-FFFF) to southbridge. */
+ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4);
+ PciData = 0x0000F000;
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0);
+ PciData = 0x00000003;
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+ Status = AGESA_SUCCESS;
+ return (UINT32)Status;
+}
+
+UINT32
+agesawrapper_amdinitmmio (
+ VOID
+ )
+{
+ AGESA_STATUS Status;
+ UINT64 MsrReg;
+ UINT32 PciData;
+ PCI_ADDR PciAddress;
+ AMD_CONFIG_PARAMS StdHeader;
+
+ /*
+ Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
+ Address MSR register.
+ */
+ MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
+ LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
+
+ /*
+ Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
+ */
+ LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader);
+ MsrReg = MsrReg | 0x0000400000000000;
+ LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
+
+ /* For serial port */
+ PciData = 0xFF03FFD5;
+ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0x3, 0x44);
+ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+
+ /* Set ROM cache onto WP to decrease post time */
+ MsrReg = (0x0100000000ull - CONFIG_ROM_SIZE) | 5ull;
+ LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
+ MsrReg = (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800ull;
+ LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader);
+
+ Status = AGESA_SUCCESS;
+ return (UINT32)Status;
+}
+
+UINT32
+agesawrapper_amdinitreset (
+ VOID
+ )
+{
+ AGESA_STATUS status;
+ AMD_INTERFACE_PARAMS AmdParamStruct;
+ AMD_RESET_PARAMS AmdResetParams;
+
+ LibAmdMemFill (&AmdParamStruct,
+ 0,
+ sizeof (AMD_INTERFACE_PARAMS),
+ &(AmdParamStruct.StdHeader));
+
+ LibAmdMemFill (&AmdResetParams,
+ 0,
+ sizeof (AMD_RESET_PARAMS),
+ &(AmdResetParams.StdHeader));
+
+ AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET;
+ AmdParamStruct.AllocationMethod = ByHost;
+ AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS);
+ AmdParamStruct.NewStructPtr = &AmdResetParams;
+ AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+ AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+ AmdParamStruct.StdHeader.Func = 0;
+ AmdParamStruct.StdHeader.ImageBasePtr = 0;
+ AmdCreateStruct (&AmdParamStruct);
+ AmdResetParams.HtConfig.Depth = 0;
+
+ status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr);
+ if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus);
+ AmdReleaseStruct (&AmdParamStruct);
+ return (UINT32)status;
+}
+
+UINT32
+agesawrapper_amdinitearly (
+ VOID
+ )
+{
+ AGESA_STATUS status;
+ AMD_INTERFACE_PARAMS AmdParamStruct;
+ AMD_EARLY_PARAMS *AmdEarlyParamsPtr;
+
+ LibAmdMemFill (&AmdParamStruct,
+ 0,
+ sizeof (AMD_INTERFACE_PARAMS),
+ &(AmdParamStruct.StdHeader));
+
+ AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY;
+ AmdParamStruct.AllocationMethod = PreMemHeap;
+ AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+ AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+ AmdParamStruct.StdHeader.Func = 0;
+ AmdParamStruct.StdHeader.ImageBasePtr = 0;
+ AmdCreateStruct (&AmdParamStruct);
+
+ AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr;
+ OemCustomizeInitEarly (AmdEarlyParamsPtr);
+
+ status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr);
+ if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus);
+ AmdReleaseStruct (&AmdParamStruct);
+
+ return (UINT32)status;
+}
+
+UINT32 GetHeapBase(
+ AMD_CONFIG_PARAMS *StdHeader
+ )
+{
+ UINT32 heap;
+
+#if CONFIG_HAVE_ACPI_RESUME
+ /* Both romstage and ramstage has this S3 detect. */
+ if (acpi_get_sleep_type() == 3)
+ heap = (UINT32)cbmem_find(CBMEM_ID_RESUME_SCRATCH) + (CONFIG_HIGH_SCRATCH_MEMORY_SIZE - BIOS_HEAP_SIZE); /* base + high_stack_size */
+ else
+#endif
+ heap = BIOS_HEAP_START_ADDRESS; /* Low mem */
+
+ return heap;
+}
+
+UINT32
+agesawrapper_amdinitpost (
+ VOID
+ )
+{
+ AGESA_STATUS status;
+ UINT16 i;
+ UINT32 *HeadPtr;
+ AMD_INTERFACE_PARAMS AmdParamStruct;
+ AMD_POST_PARAMS *PostParams;
+ BIOS_HEAP_MANAGER *BiosManagerPtr;
+
+ LibAmdMemFill (&AmdParamStruct,
+ 0,
+ sizeof (AMD_INTERFACE_PARAMS),
+ &(AmdParamStruct.StdHeader));
+
+ AmdParamStruct.AgesaFunctionName = AMD_INIT_POST;
+ AmdParamStruct.AllocationMethod = PreMemHeap;
+ AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+ AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+ AmdParamStruct.StdHeader.Func = 0;
+ AmdParamStruct.StdHeader.ImageBasePtr = 0;
+
+ AmdCreateStruct (&AmdParamStruct);
+ PostParams = (AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr;
+ status = AmdInitPost (PostParams);
+ if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(PostParams->StdHeader.HeapStatus);
+ AmdReleaseStruct (&AmdParamStruct);
+ /* Initialize heap space */
+ BiosManagerPtr = (BIOS_HEAP_MANAGER *)GetHeapBase(&AmdParamStruct.StdHeader);
+
+ HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof (BIOS_HEAP_MANAGER));
+ for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++)
+ {
+ *HeadPtr = 0x00000000;
+ HeadPtr++;
+ }
+ BiosManagerPtr->StartOfAllocatedNodes = 0;
+ BiosManagerPtr->StartOfFreedNodes = 0;
+
+ return (UINT32)status;
+}
+
+UINT32
+agesawrapper_amdinitenv (
+ VOID
+ )
+{
+ AGESA_STATUS status;
+ AMD_INTERFACE_PARAMS AmdParamStruct;
+ AMD_ENV_PARAMS *EnvParam;
+
+ LibAmdMemFill (&AmdParamStruct,
+ 0,
+ sizeof (AMD_INTERFACE_PARAMS),
+ &(AmdParamStruct.StdHeader));
+
+ AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV;
+ AmdParamStruct.AllocationMethod = PostMemDram;
+ AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+ AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+ AmdParamStruct.StdHeader.Func = 0;
+ AmdParamStruct.StdHeader.ImageBasePtr = 0;
+ status = AmdCreateStruct (&AmdParamStruct);
+ EnvParam = (AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr;
+
+ status = AmdInitEnv (EnvParam);
+ if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(EnvParam->StdHeader.HeapStatus);
+ /* Initialize Subordinate Bus Number and Secondary Bus Number
+ * In platform BIOS this address is allocated by PCI enumeration code
+ Modify D1F0x18
+ */
+
+ return (UINT32)status;
+}
+
+VOID *
+agesawrapper_getlateinitptr (
+ int pick
+ )
+{
+ switch (pick) {
+ case PICK_DMI:
+ return DmiTable;
+ case PICK_PSTATE:
+ return AcpiPstate;
+ case PICK_SRAT:
+ return AcpiSrat;
+ case PICK_SLIT:
+ return AcpiSlit;
+ case PICK_WHEA_MCE:
+ return AcpiWheaMce;
+ case PICK_WHEA_CMC:
+ return AcpiWheaCmc;
+ case PICK_ALIB:
+ return AcpiAlib;
+ case PICK_IVRS:
+ return AcpiIvrs;
+ default:
+ return NULL;
+ }
+}
+
+UINT32
+agesawrapper_amdinitmid (
+ VOID
+ )
+{
+ AGESA_STATUS status;
+ AMD_INTERFACE_PARAMS AmdParamStruct;
+
+ /* Enable MMIO on AMD CPU Address Map Controller */
+ agesawrapper_amdinitcpuio ();
+
+ LibAmdMemFill (&AmdParamStruct,
+ 0,
+ sizeof (AMD_INTERFACE_PARAMS),
+ &(AmdParamStruct.StdHeader));
+
+ AmdParamStruct.AgesaFunctionName = AMD_INIT_MID;
+ AmdParamStruct.AllocationMethod = PostMemDram;
+ AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+ AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+ AmdParamStruct.StdHeader.Func = 0;
+ AmdParamStruct.StdHeader.ImageBasePtr = 0;
+
+ AmdCreateStruct (&AmdParamStruct);
+
+ ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr)->GnbMidConfiguration.iGpuVgaMode = 0;/* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
+ status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr);
+ if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus);
+ AmdReleaseStruct (&AmdParamStruct);
+
+ return (UINT32)status;
+}
+
+UINT32
+agesawrapper_amdinitlate (
+ VOID
+ )
+{
+ AGESA_STATUS Status;
+ AMD_INTERFACE_PARAMS AmdParamStruct;
+ AMD_LATE_PARAMS *AmdLateParams;
+
+ LibAmdMemFill (&AmdParamStruct,
+ 0,
+ sizeof (AMD_INTERFACE_PARAMS),
+ &(AmdParamStruct.StdHeader));
+
+ AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE;
+ AmdParamStruct.AllocationMethod = PostMemDram;
+ AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+ AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+ AmdParamStruct.StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
+ AmdParamStruct.StdHeader.Func = 0;
+ AmdParamStruct.StdHeader.ImageBasePtr = 0;
+
+ /* NOTE: if not call amdcreatestruct, the initializer(AmdInitLateInitializer) would not be called */
+ AmdCreateStruct(&AmdParamStruct);
+ AmdLateParams = (AMD_LATE_PARAMS *)AmdParamStruct.NewStructPtr;
+ Status = AmdInitLate(AmdLateParams);
+ /* CDIT table is not created. */
+ if (Status != AGESA_SUCCESS) {
+ /* agesawrapper_amdreadeventlog(AmdLateParams->StdHeader.HeapStatus); */
+ ASSERT(Status == AGESA_SUCCESS);
+ }
+
+ DmiTable = AmdLateParams->DmiTable;
+ AcpiPstate = AmdLateParams->AcpiPState;
+ AcpiSrat = AmdLateParams->AcpiSrat;
+ AcpiSlit = AmdLateParams->AcpiSlit;
+
+ AcpiWheaMce = AmdLateParams->AcpiWheaMce;
+ AcpiWheaCmc = AmdLateParams->AcpiWheaCmc;
+ AcpiAlib = AmdLateParams->AcpiAlib;
+ AcpiIvrs = AmdLateParams->AcpiIvrs;
+
+ printk(BIOS_DEBUG, "DmiTable:%x, AcpiPstatein: %x, AcpiSrat:%x,"
+ "AcpiSlit:%x, Mce:%x, Cmc:%x,"
+ "Alib:%x, AcpiIvrs:%x in %s\n",
+ (unsigned int)DmiTable, (unsigned int)AcpiPstate, (unsigned int)AcpiSrat,
+ (unsigned int)AcpiSlit, (unsigned int)AcpiWheaMce, (unsigned int)AcpiWheaCmc,
+ (unsigned int)AcpiAlib, (unsigned int)AcpiIvrs, __func__);
+
+ /* AmdReleaseStruct (&AmdParamStruct); */
+ return (UINT32)Status;
+}
+
+UINT32
+agesawrapper_amdlaterunaptask (
+ UINT32 Func,
+ UINT32 Data,
+ VOID *ConfigPtr
+ )
+{
+ AGESA_STATUS Status;
+ AP_EXE_PARAMS ApExeParams;
+
+ LibAmdMemFill (&ApExeParams,
+ 0,
+ sizeof (AP_EXE_PARAMS),
+ &(ApExeParams.StdHeader));
+
+ ApExeParams.StdHeader.AltImageBasePtr = 0;
+ ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+ ApExeParams.StdHeader.Func = 0;
+ ApExeParams.StdHeader.ImageBasePtr = 0;
+ ApExeParams.FunctionNumber = Func;
+ ApExeParams.RelatedDataBlock = ConfigPtr;
+
+ Status = AmdLateRunApTask (&ApExeParams);
+ if (Status != AGESA_SUCCESS) {
+ /* agesawrapper_amdreadeventlog(); */
+ ASSERT(Status == AGESA_SUCCESS);
+ }
+
+ return (UINT32)Status;
+}
+
+#if CONFIG_HAVE_ACPI_RESUME == 1
+
+UINT32 agesawrapper_amdinitresume(VOID)
+{
+ AGESA_STATUS status;
+ AMD_INTERFACE_PARAMS AmdParamStruct;
+ AMD_RESUME_PARAMS *AmdResumeParamsPtr;
+ S3_DATA_TYPE S3DataType;
+
+ LibAmdMemFill (&AmdParamStruct,
+ 0,
+ sizeof (AMD_INTERFACE_PARAMS),
+ &(AmdParamStruct.StdHeader));
+
+ AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME;
+ AmdParamStruct.AllocationMethod = PreMemHeap;
+ AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+ AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+ AmdParamStruct.StdHeader.Func = 0;
+ AmdParamStruct.StdHeader.ImageBasePtr = 0;
+ AmdCreateStruct (&AmdParamStruct);
+
+ AmdResumeParamsPtr = (AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr;
+
+ AmdResumeParamsPtr->S3DataBlock.NvStorageSize = 0;
+ AmdResumeParamsPtr->S3DataBlock.VolatileStorageSize = 0;
+ S3DataType = S3DataTypeNonVolatile;
+ OemAgesaGetS3Info (S3DataType,
+ (u32 *) &AmdResumeParamsPtr->S3DataBlock.NvStorageSize,
+ (void **) &AmdResumeParamsPtr->S3DataBlock.NvStorage);
+
+ status = AmdInitResume ((AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr);
+
+ if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus);
+ AmdReleaseStruct (&AmdParamStruct);
+
+ return (UINT32)status;
+}
+
+#ifndef __PRE_RAM__
+
+extern FCH_DATA_BLOCK InitEnvCfgDefault;
+STATIC VOID s3_resume_init_data(FCH_DATA_BLOCK *FchParams)
+{
+ FchParams->Gpp.GppLinkConfig = UserOptions.FchBldCfg->CfgFchGppLinkConfig;
+ FchParams->Gpp.PortCfg[0].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort0Present;
+ FchParams->Gpp.PortCfg[1].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort1Present;
+ FchParams->Gpp.PortCfg[2].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort2Present;
+ FchParams->Gpp.PortCfg[3].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort3Present;
+ FchParams->Gpp.PortCfg[0].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort0HotPlug;
+ FchParams->Gpp.PortCfg[1].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort1HotPlug;
+ FchParams->Gpp.PortCfg[2].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort2HotPlug;
+ FchParams->Gpp.PortCfg[3].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort3HotPlug;
+ FchParams->Gpp.GppFunctionEnable = TRUE; /* GppEnable */
+ FchParams->Gpp.GppPhyPllPowerDown = TRUE;
+ FchParams->Gpp.GppDynamicPowerSaving = TRUE;
+ FchParams->Gpp.UmiPhyPllPowerDown = TRUE;
+ FchParams->Gpp.NewGppAlgorithm = TRUE;
+ FchParams->Gpp.GppPortMinPollingTime = 40;
+
+ FchParams->Spi.SpiSpeed = 2;
+ FchParams->Ir.IrConfig = 3;
+
+ FchParams->HwAcpi.Smbus0BaseAddress = UserOptions.FchBldCfg->CfgSmbus0BaseAddress;
+ FchParams->HwAcpi.Smbus1BaseAddress = UserOptions.FchBldCfg->CfgSmbus1BaseAddress;
+ FchParams->HwAcpi.SioPmeBaseAddress = UserOptions.FchBldCfg->CfgSioPmeBaseAddress;
+ FchParams->HwAcpi.AcpiPm1EvtBlkAddr = UserOptions.FchBldCfg->CfgAcpiPm1EvtBlkAddr;
+ FchParams->HwAcpi.AcpiPm1CntBlkAddr = UserOptions.FchBldCfg->CfgAcpiPm1CntBlkAddr;
+ FchParams->HwAcpi.AcpiPmTmrBlkAddr = UserOptions.FchBldCfg->CfgAcpiPmTmrBlkAddr;
+ FchParams->HwAcpi.CpuControlBlkAddr = UserOptions.FchBldCfg->CfgCpuControlBlkAddr;
+ FchParams->HwAcpi.AcpiGpe0BlkAddr = UserOptions.FchBldCfg->CfgAcpiGpe0BlkAddr;
+ FchParams->HwAcpi.SmiCmdPortAddr = UserOptions.FchBldCfg->CfgSmiCmdPortAddr;
+ FchParams->HwAcpi.AcpiPmaCntBlkAddr = UserOptions.FchBldCfg->CfgAcpiPmaCntBlkAddr;
+ FchParams->HwAcpi.WatchDogTimerBase = UserOptions.FchBldCfg->CfgWatchDogTimerBase;
+ FchParams->Sata.SataRaid5Ssid = UserOptions.FchBldCfg->CfgSataRaid5Ssid;
+ FchParams->Sata.SataRaidSsid = UserOptions.FchBldCfg->CfgSataRaidSsid;
+ FchParams->Sata.SataAhciSsid = UserOptions.FchBldCfg->CfgSataAhciSsid;
+ FchParams->Sata.SataIdeSsid = UserOptions.FchBldCfg->CfgSataIdeSsid;
+ FchParams->Gec.GecShadowRomBase = UserOptions.FchBldCfg->CfgGecShadowRomBase;
+ FchParams->Spi.RomBaseAddress = UserOptions.FchBldCfg->CfgSpiRomBaseAddress;
+ FchParams->Sd.SdSsid = UserOptions.FchBldCfg->CfgSdSsid;
+ FchParams->Spi.LpcSsid = UserOptions.FchBldCfg->CfgLpcSsid;
+ FchParams->Hpet.HpetBase = UserOptions.FchBldCfg->CfgHpetBaseAddress;
+ FchParams->Azalia.AzaliaSsid = UserOptions.FchBldCfg->CfgAzaliaSsid;
+ FchParams->Smbus.SmbusSsid = UserOptions.FchBldCfg->CfgSmbusSsid;
+ FchParams->Ide.IdeSsid = UserOptions.FchBldCfg->CfgIdeSsid;
+ FchParams->Usb.EhciSsid = UserOptions.FchBldCfg->CfgEhciSsid;
+ FchParams->Usb.OhciSsid = UserOptions.FchBldCfg->CfgOhciSsid;
+ FchParams->Usb.XhciSsid = UserOptions.FchBldCfg->CfgXhciSsid;
+ FchParams->Ir.IrPinControl = UserOptions.FchBldCfg->CfgFchIrPinControl;
+ FchParams->Sd.SdClockControl = UserOptions.FchBldCfg->CfgFchSdClockControl;
+}
+
+UINT32 agesawrapper_fchs3earlyrestore (VOID)
+{
+ AGESA_STATUS status = AGESA_SUCCESS;
+
+ FCH_DATA_BLOCK FchParams;
+ AMD_CONFIG_PARAMS StdHeader;
+
+ StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
+ StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10;
+ StdHeader.AltImageBasePtr = 0;
+ StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+ StdHeader.Func = 0;
+ StdHeader.ImageBasePtr = 0;
+
+ FchParams = InitEnvCfgDefault;
+ FchParams.StdHeader = &StdHeader;
+ s3_resume_init_data(&FchParams);
+
+ FchInitS3EarlyRestore(&FchParams);
+
+ return status;
+}
+#endif
+
+UINT32 agesawrapper_amds3laterestore (VOID)
+{
+ AGESA_STATUS Status;
+ AMD_INTERFACE_PARAMS AmdInterfaceParams;
+ AMD_S3LATE_PARAMS AmdS3LateParams;
+ AMD_S3LATE_PARAMS *AmdS3LateParamsPtr;
+ S3_DATA_TYPE S3DataType;
+
+ agesawrapper_amdinitcpuio();
+ LibAmdMemFill (&AmdS3LateParams,
+ 0,
+ sizeof (AMD_S3LATE_PARAMS),
+ &(AmdS3LateParams.StdHeader));
+ AmdInterfaceParams.StdHeader.ImageBasePtr = 0;
+ AmdInterfaceParams.AllocationMethod = ByHost;
+ AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE;
+ AmdInterfaceParams.NewStructPtr = &AmdS3LateParams;
+ AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+ AmdS3LateParamsPtr = &AmdS3LateParams;
+ AmdInterfaceParams.NewStructSize = sizeof (AMD_S3LATE_PARAMS);
+
+ AmdCreateStruct (&AmdInterfaceParams);
+
+ AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = 0;
+ S3DataType = S3DataTypeVolatile;
+
+ OemAgesaGetS3Info (S3DataType,
+ (u32 *) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize,
+ (void **) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorage);
+
+ Status = AmdS3LateRestore (AmdS3LateParamsPtr);
+ if (Status != AGESA_SUCCESS) {
+ agesawrapper_amdreadeventlog(AmdInterfaceParams.StdHeader.HeapStatus);
+ ASSERT(Status == AGESA_SUCCESS);
+ }
+
+ return (UINT32)Status;
+}
+
+#ifndef __PRE_RAM__
+
+extern UINT8 picr_data[0x54], intr_data[0x54];
+
+UINT32 agesawrapper_fchs3laterestore (VOID)
+{
+ AGESA_STATUS status = AGESA_SUCCESS;
+
+ FCH_DATA_BLOCK FchParams;
+ AMD_CONFIG_PARAMS StdHeader;
+ UINT8 byte;
+
+ StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
+ StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10;
+ StdHeader.AltImageBasePtr = 0;
+ StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+ StdHeader.Func = 0;
+ StdHeader.ImageBasePtr = 0;
+
+ FchParams = InitEnvCfgDefault;
+ FchParams.StdHeader = &StdHeader;
+ s3_resume_init_data(&FchParams);
+ FchInitS3LateRestore(&FchParams);
+ /* PIC IRQ routine */
+ for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
+ outb(byte, 0xC00);
+ outb(picr_data[byte], 0xC01);
+ }
+
+ /* APIC IRQ routine */
+ for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
+ outb(byte | 0x80, 0xC00);
+ outb(intr_data[byte], 0xC01);
+ }
+
+ return status;
+}
+#endif
+
+#ifndef __PRE_RAM__
+
+UINT32 agesawrapper_amdS3Save(VOID)
+{
+ AGESA_STATUS Status;
+ AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr;
+ AMD_INTERFACE_PARAMS AmdInterfaceParams;
+ S3_DATA_TYPE S3DataType;
+
+ LibAmdMemFill (&AmdInterfaceParams,
+ 0,
+ sizeof (AMD_INTERFACE_PARAMS),
+ &(AmdInterfaceParams.StdHeader));
+
+ AmdInterfaceParams.StdHeader.ImageBasePtr = 0;
+ AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
+ AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+ AmdInterfaceParams.AllocationMethod = PostMemDram;
+ AmdInterfaceParams.AgesaFunctionName = AMD_S3_SAVE;
+ AmdInterfaceParams.StdHeader.AltImageBasePtr = 0;
+ AmdInterfaceParams.StdHeader.Func = 0;
+
+ AmdCreateStruct(&AmdInterfaceParams);
+ AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *)AmdInterfaceParams.NewStructPtr;
+ AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader;
+
+ Status = AmdS3Save(AmdS3SaveParamsPtr);
+ if (Status != AGESA_SUCCESS) {
+ agesawrapper_amdreadeventlog(AmdInterfaceParams.StdHeader.HeapStatus);
+ ASSERT(Status == AGESA_SUCCESS);
+ }
+
+ S3DataType = S3DataTypeNonVolatile;
+ printk(BIOS_DEBUG, "NvStorageSize=%x, NvStorage=%x\n",
+ (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize,
+ (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorage);
+
+ Status = OemAgesaSaveS3Info (
+ S3DataType,
+ AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize,
+ AmdS3SaveParamsPtr->S3DataBlock.NvStorage);
+
+ printk(BIOS_DEBUG, "VolatileStorageSize=%x, VolatileStorage=%x\n",
+ (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize,
+ (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage);
+
+ if (AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize != 0) {
+ S3DataType = S3DataTypeVolatile;
+
+ Status = OemAgesaSaveS3Info (
+ S3DataType,
+ AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize,
+ AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage);
+ }
+ OemAgesaSaveMtrr();
+
+ AmdReleaseStruct (&AmdInterfaceParams);
+
+ return (UINT32)Status;
+}
+
+#endif /* #ifndef __PRE_RAM__ */
+#endif /* CONFIG_HAVE_ACPI_RESUME */
+
+UINT32
+agesawrapper_amdreadeventlog (
+ UINT8 HeapStatus
+ )
+{
+ AGESA_STATUS Status;
+ EVENT_PARAMS AmdEventParams;
+
+ LibAmdMemFill (&AmdEventParams,
+ 0,
+ sizeof (EVENT_PARAMS),
+ &(AmdEventParams.StdHeader));
+
+ AmdEventParams.StdHeader.AltImageBasePtr = 0;
+ AmdEventParams.StdHeader.CalloutPtr = NULL;
+ AmdEventParams.StdHeader.Func = 0;
+ AmdEventParams.StdHeader.ImageBasePtr = 0;
+ AmdEventParams.StdHeader.HeapStatus = HeapStatus;
+ Status = AmdReadEventLog (&AmdEventParams);
+ while (AmdEventParams.EventClass != 0) {
+ printk(BIOS_DEBUG,"\nEventLog: EventClass = %x, EventInfo = %x.\n", (unsigned int)AmdEventParams.EventClass,(unsigned int)AmdEventParams.EventInfo);
+ printk(BIOS_DEBUG," Param1 = %x, Param2 = %x.\n",(unsigned int)AmdEventParams.DataParam1, (unsigned int)AmdEventParams.DataParam2);
+ printk(BIOS_DEBUG," Param3 = %x, Param4 = %x.\n",(unsigned int)AmdEventParams.DataParam3, (unsigned int)AmdEventParams.DataParam4);
+ Status = AmdReadEventLog (&AmdEventParams);
+ }
+
+ return (UINT32)Status;
+}
diff --git a/src/mainboard/amd/parmer/agesawrapper.h b/src/mainboard/amd/parmer/agesawrapper.h
new file mode 100644
index 0000000..db893cd
--- /dev/null
+++ b/src/mainboard/amd/parmer/agesawrapper.h
@@ -0,0 +1,97 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*----------------------------------------------------------------------------------------
+ * M O D U L E S U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#ifndef _AGESAWRAPPER_H_
+#define _AGESAWRAPPER_H_
+
+#include <stdint.h>
+#include "Porting.h"
+#include "AGESA.h"
+
+/*----------------------------------------------------------------------------------------
+ * D E F I N I T I O N S A N D M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+/* Define AMD Ontario APPU SSID/SVID */
+#define AMD_APU_SVID 0x1022
+#define AMD_APU_SSID 0x1234
+#define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS
+
+enum {
+ PICK_DMI, /* DMI Interface */
+ PICK_PSTATE, /* Acpi Pstate SSDT Table */
+ PICK_SRAT, /* SRAT Table */
+ PICK_SLIT, /* SLIT Table */
+ PICK_WHEA_MCE, /* WHEA MCE table */
+ PICK_WHEA_CMC, /* WHEA CMV table */
+ PICK_ALIB, /* SACPI SSDT table with ALIB implementation */
+ PICK_IVRS, /* IOMMU ACPI IVRS(I/O Virtualization Reporting Structure) table */
+};
+
+/*----------------------------------------------------------------------------------------
+ * T Y P E D E F S A N D S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+typedef struct {
+ UINT32 CalloutName;
+ AGESA_STATUS (*CalloutPtr) (UINT32 Func, UINT32 Data, VOID* ConfigPtr);
+} BIOS_CALLOUT_STRUCT;
+
+/*----------------------------------------------------------------------------------------
+ * P R O T O T Y P E S O F L O C A L F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ * E X P O R T E D F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------
+ * L O C A L F U N C T I O N S
+ *---------------------------------------------------------------------------------------
+ */
+
+UINT32 agesawrapper_amdinitreset (void);
+UINT32 agesawrapper_amdinitearly (void);
+UINT32 agesawrapper_amdinitenv (void);
+UINT32 agesawrapper_amdinitlate (void);
+UINT32 agesawrapper_amdinitpost (void);
+UINT32 agesawrapper_amdinitmid (void);
+UINT32 agesawrapper_amdreadeventlog (UINT8 HeapStatus);
+UINT32 agesawrapper_amdinitmmio (void);
+UINT32 agesawrapper_amdinitcpuio (void);
+void *agesawrapper_getlateinitptr (int pick);
+UINT32 agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, void *ConfigPtr);
+UINT32 agesawrapper_amdS3Save(VOID);
+UINT32 agesawrapper_amdinitresume(VOID);
+UINT32 agesawrapper_amds3laterestore (VOID);
+
+UINT32 agesawrapper_fchs3earlyrestore (VOID);
+UINT32 agesawrapper_fchs3laterestore (VOID);
+
+UINT32 GetHeapBase(AMD_CONFIG_PARAMS *StdHeader);
+
+#endif
diff --git a/src/mainboard/amd/parmer/buildOpts.c b/src/mainboard/amd/parmer/buildOpts.c
new file mode 100644
index 0000000..01091da
--- /dev/null
+++ b/src/mainboard/amd/parmer/buildOpts.c
@@ -0,0 +1,499 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/**
+ * @file
+ *
+ * AMD User options selection for a Brazos platform solution system
+ *
+ * This file is placed in the user's platform directory and contains the
+ * build option selections desired for that platform.
+ *
+ * For Information about this file, see @ref platforminstall.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: Core
+ * @e \$Revision: 23714 $ @e \$Date: 2009-12-09 17:28:37 -0600 (Wed, 09 Dec 2009) $
+ */
+
+#include "AGESA.h"
+//#include "CommonReturns.h"
+#include "Filecode.h"
+#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
+
+/* Select the cpu family. */
+#define INSTALL_FAMILY_10_SUPPORT FALSE
+#define INSTALL_FAMILY_12_SUPPORT FALSE
+#define INSTALL_FAMILY_14_SUPPORT FALSE
+#define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE
+
+/* Select the cpu socket type. */
+#define INSTALL_G34_SOCKET_SUPPORT FALSE
+#define INSTALL_C32_SOCKET_SUPPORT FALSE
+#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
+#define INSTALL_S1G4_SOCKET_SUPPORT FALSE
+#define INSTALL_ASB2_SOCKET_SUPPORT FALSE
+#define INSTALL_FS1_SOCKET_SUPPORT TRUE
+#define INSTALL_FM1_SOCKET_SUPPORT FALSE
+#define INSTALL_FP2_SOCKET_SUPPORT TRUE
+#define INSTALL_FT1_SOCKET_SUPPORT FALSE
+#define INSTALL_AM3_SOCKET_SUPPORT FALSE
+
+#define INSTALL_FM2_SOCKET_SUPPORT FALSE
+
+//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE
+//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE
+#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE
+//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE
+//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE
+//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE
+#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE
+#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE
+#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE
+//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE
+#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE
+//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE
+#define BLDOPT_REMOVE_SRAT FALSE //TRUE
+#define BLDOPT_REMOVE_SLIT FALSE //TRUE
+#define BLDOPT_REMOVE_WHEA FALSE //TRUE
+#define BLDOPT_REMOVE_CRAT TRUE
+//#define BLDOPT_REMOVE_DMI FALSE //TRUE
+//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE
+//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE
+//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE
+//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE
+//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE
+//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE
+
+//This element selects whether P-States should be forced to be independent,
+// as reported by the ACPI _PSD object. For single-link processors,
+// setting TRUE for OS to support this feature.
+
+//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE
+
+#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS
+#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER
+/* Build configuration values here.
+ */
+#define BLDCFG_VRM_CURRENT_LIMIT 90000
+#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0
+#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT 0
+#define BLDCFG_PLAT_NUM_IO_APICS 3
+#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST
+#define BLDCFG_MEM_INIT_PSTATE 0
+
+#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE
+
+#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY
+#define BLDCFG_MEMORY_MODE_UNGANGED TRUE
+#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE
+#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
+#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE
+#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE
+#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE
+#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE
+#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE
+#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE
+#define BLDCFG_MEMORY_POWER_DOWN TRUE
+#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT
+#define BLDCFG_ONLINE_SPARE FALSE
+#define BLDCFG_BANK_SWIZZLE TRUE
+#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO
+#define BLDCFG_MEMORY_CLOCK_SELECT DDR1866_FREQUENCY
+#define BLDCFG_DQS_TRAINING_CONTROL TRUE
+#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE
+#define BLDCFG_USE_BURST_MODE FALSE
+#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE
+#define BLDCFG_ENABLE_ECC_FEATURE TRUE
+#define BLDCFG_ECC_REDIRECTION FALSE
+#define BLDCFG_SCRUB_DRAM_RATE 0
+#define BLDCFG_SCRUB_L2_RATE 0
+#define BLDCFG_SCRUB_L3_RATE 0
+#define BLDCFG_SCRUB_IC_RATE 0
+#define BLDCFG_SCRUB_DC_RATE 0
+#define BLDCFG_ECC_SYMBOL_SIZE 4
+#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000
+#define BLDCFG_ECC_SYNC_FLOOD FALSE
+#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE
+#define BLDCFG_1GB_ALIGN FALSE
+#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE
+#define BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM 36 // PCIE Spread Spectrum default value 0.36%
+#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770
+
+#define BLDOPT_REMOVE_ALIB FALSE
+#define BLDCFG_PLATFORM_CPB_MODE CpbModeDisabled
+#define BLDCFG_PROCESSOR_SCOPE_NAME0 'P'
+#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0'
+#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6
+
+#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 200
+#define BLDCFG_CFG_ABM_SUPPORT 0
+
+//#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770
+
+// Specify the default values for the VRM controlling the VDDNB plane.
+// If not specified, the values used for the core VRM will be applied
+//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 // Not currently used on Trinity
+//#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 // Zero - disable NBPSI_L, Non-zero - enable NBPSI_L
+//#define BLDCFG_VRM_NB_SLEW_RATE 5000 // Used in calculating the VSRampSlamTime
+//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 // Not currently used on Trinity
+//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE 0 // Not currently used on Trinity
+//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 // Not currently used on Trinity
+
+#define BLDCFG_VRM_NB_CURRENT_LIMIT 60000
+
+#define BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 3
+#define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 3
+
+#if CONFIG_GFXUMA
+#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED
+#define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED
+//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/
+#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000//512M
+#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE
+#endif
+
+#define BLDCFG_IOMMU_SUPPORT FALSE
+
+#define BLDCFG_CFG_GNB_HD_AUDIO TRUE
+//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID
+//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID
+//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID
+
+/* Process the options...
+ * This file include MUST occur AFTER the user option selection settings
+ */
+#define AGESA_ENTRY_INIT_RESET TRUE
+#define AGESA_ENTRY_INIT_RECOVERY FALSE
+#define AGESA_ENTRY_INIT_EARLY TRUE
+#define AGESA_ENTRY_INIT_POST TRUE
+#define AGESA_ENTRY_INIT_ENV TRUE
+#define AGESA_ENTRY_INIT_MID TRUE
+#define AGESA_ENTRY_INIT_LATE TRUE
+#define AGESA_ENTRY_INIT_S3SAVE TRUE
+#define AGESA_ENTRY_INIT_RESUME TRUE //TRUE
+#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE
+#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE
+/*
+ * Customized OEM build configurations for FCH component
+ */
+// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00
+// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20
+// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00
+// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400
+// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404
+// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408
+// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410
+// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420
+// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000
+// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000
+// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000
+// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0
+// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00
+// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000
+// #define BLDCFG_AZALIA_SSID 0x780D1022
+// #define BLDCFG_SMBUS_SSID 0x780B1022
+// #define BLDCFG_IDE_SSID 0x780C1022
+// #define BLDCFG_SATA_AHCI_SSID 0x78011022
+// #define BLDCFG_SATA_IDE_SSID 0x78001022
+// #define BLDCFG_SATA_RAID5_SSID 0x78031022
+// #define BLDCFG_SATA_RAID_SSID 0x78021022
+// #define BLDCFG_EHCI_SSID 0x78081022
+// #define BLDCFG_OHCI_SSID 0x78071022
+// #define BLDCFG_LPC_SSID 0x780E1022
+// #define BLDCFG_SD_SSID 0x78061022
+// #define BLDCFG_XHCI_SSID 0x78121022
+// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE
+// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE
+// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4
+// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE
+// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE
+// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE
+// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE
+// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE
+// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE
+// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE
+// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE
+
+CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
+{
+ { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E },
+ { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E },
+ { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 },
+ { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 },
+ { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 },
+ { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 },
+ { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 },
+ { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 },
+ { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 },
+ { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 },
+ { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 },
+ { CPU_LIST_TERMINAL }
+};
+
+#define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList
+
+//#include "VirgoInstall.h"
+
+/* Include the files that instantiate the configuration definitions. */
+#include "cpuRegisters.h"
+#include "cpuFamRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "AdvancedApi.h"
+#include "heapManager.h"
+#include "CreateStruct.h"
+#include "cpuFeatures.h"
+#include "Table.h"
+#include "CommonReturns.h"
+#include "cpuEarlyInit.h"
+#include "cpuLateInit.h"
+#include "GnbInterface.h"
+
+ // This is the delivery package title, "BrazosPI"
+ // This string MUST be exactly 8 characters long
+#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'}
+
+ // This is the release version number of the AGESA component
+ // This string MUST be exactly 12 characters long
+#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '}
+
+/* MEMORY_BUS_SPEED */
+#define DDR400_FREQUENCY 200 ///< DDR 400
+#define DDR533_FREQUENCY 266 ///< DDR 533
+#define DDR667_FREQUENCY 333 ///< DDR 667
+#define DDR800_FREQUENCY 400 ///< DDR 800
+#define DDR1066_FREQUENCY 533 ///< DDR 1066
+#define DDR1333_FREQUENCY 667 ///< DDR 1333
+#define DDR1600_FREQUENCY 800 ///< DDR 1600
+#define DDR1866_FREQUENCY 933 ///< DDR 1866
+#define DDR2100_FREQUENCY 1050 ///< DDR 2100
+#define DDR2133_FREQUENCY 1066 ///< DDR 2133
+#define DDR2400_FREQUENCY 1200 ///< DDR 2400
+#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency
+
+/* QUANDRANK_TYPE*/
+#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
+#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
+
+/* USER_MEMORY_TIMING_MODE */
+#define TIMING_MODE_AUTO 0 ///< Use best rate possible
+#define TIMING_MODE_LIMITED 1 ///< Set user top limit
+#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
+
+/* POWER_DOWN_MODE */
+#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
+#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
+
+/*
+ * Agesa optional capabilities selection.
+ * Uncomment and mark FALSE those features you wish to include in the build.
+ * Comment out or mark TRUE those features you want to REMOVE from the build.
+ */
+
+#define DFLT_SMBUS0_BASE_ADDRESS 0xB00
+#define DFLT_SMBUS1_BASE_ADDRESS 0xB20
+#define DFLT_SIO_PME_BASE_ADDRESS 0xE00
+#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x800
+#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x804
+#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x808
+#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x810
+#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x820
+#define DFLT_SPI_BASE_ADDRESS 0xFEC10000
+#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0
+#define DFLT_HPET_BASE_ADDRESS 0xFED00000
+#define DFLT_SMI_CMD_PORT 0xB0
+#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00
+#define DFLT_GEC_BASE_ADDRESS 0xFED61000
+#define DFLT_AZALIA_SSID 0x780D1022
+#define DFLT_SMBUS_SSID 0x780B1022
+#define DFLT_IDE_SSID 0x780C1022
+#define DFLT_SATA_AHCI_SSID 0x78011022
+#define DFLT_SATA_IDE_SSID 0x78001022
+#define DFLT_SATA_RAID5_SSID 0x78031022
+#define DFLT_SATA_RAID_SSID 0x78021022
+#define DFLT_EHCI_SSID 0x78081022
+#define DFLT_OHCI_SSID 0x78071022
+#define DFLT_LPC_SSID 0x780E1022
+#define DFLT_SD_SSID 0x78061022
+#define DFLT_XHCI_SSID 0x78121022
+#define DFLT_FCH_PORT80_BEHIND_PCIB FALSE
+#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE
+#define DFLT_FCH_GPP_LINK_CONFIG PortA4
+#define DFLT_FCH_GPP_PORT0_PRESENT FALSE
+#define DFLT_FCH_GPP_PORT1_PRESENT FALSE
+#define DFLT_FCH_GPP_PORT2_PRESENT FALSE
+#define DFLT_FCH_GPP_PORT3_PRESENT FALSE
+#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE
+#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE
+#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE
+#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE
+//#define BLDCFG_IR_PIN_CONTROL 0x33
+
+GPIO_CONTROL parmer_gpio[] = {
+ {183, Function1, GpioIn | GpioOutEnB | PullUpB},
+ {-1}
+};
+#define BLDCFG_FCH_GPIO_CONTROL_LIST (&parmer_gpio[0])
+
+// The following definitions specify the default values for various parameters in which there are
+// no clearly defined defaults to be used in the common file. The values below are based on product
+// and BKDG content, please consult the AGESA Memory team for consultation.
+#define DFLT_SCRUB_DRAM_RATE (0)
+#define DFLT_SCRUB_L2_RATE (0)
+#define DFLT_SCRUB_L3_RATE (0)
+#define DFLT_SCRUB_IC_RATE (0)
+#define DFLT_SCRUB_DC_RATE (0)
+#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
+#define DFLT_VRM_SLEW_RATE (5000)
+
+#include "PlatformInstall.h"
+
+/*----------------------------------------------------------------------------------------
+ * CUSTOMER OVERIDES MEMORY TABLE
+ *----------------------------------------------------------------------------------------
+ */
+
+/*
+ * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
+ * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
+ * is populated, AGESA will base its settings on the data from the table. Otherwise, it will
+ * use its default conservative settings.
+ */
+CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
+ //
+ // The following macros are supported (use comma to separate macros):
+ //
+ // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap)
+ // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap.
+ // AGESA will base on this value to disable unused MemClk to save power.
+ // Example:
+ // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below:
+ // Bit AM3/S1g3 pin name
+ // 0 M[B,A]_CLK_H/L[0]
+ // 1 M[B,A]_CLK_H/L[1]
+ // 2 M[B,A]_CLK_H/L[2]
+ // 3 M[B,A]_CLK_H/L[3]
+ // 4 M[B,A]_CLK_H/L[4]
+ // 5 M[B,A]_CLK_H/L[5]
+ // 6 M[B,A]_CLK_H/L[6]
+ // 7 M[B,A]_CLK_H/L[7]
+ // And platform has the following routing:
+ // CS0 M[B,A]_CLK_H/L[4]
+ // CS1 M[B,A]_CLK_H/L[2]
+ // CS2 M[B,A]_CLK_H/L[3]
+ // CS3 M[B,A]_CLK_H/L[5]
+ // Then platform can specify the following macro:
+ // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00)
+ //
+ // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap)
+ // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap.
+ // AGESA will base on this value to tristate unused CKE to save power.
+ //
+ // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap)
+ // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap.
+ // AGESA will base on this value to tristate unused ODT pins to save power.
+ //
+ // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap)
+ // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap.
+ // AGESA will base on this value to tristate unused Chip select to save power.
+ //
+ // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel)
+ // Specifies the number of DIMM slots per channel.
+ //
+ // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel)
+ // Specifies the number of Chip selects per channel.
+ //
+ // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket)
+ // Specifies the number of channels per socket.
+ //
+ // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED)
+ // Specifies DDR bus speed of channel ChannelID on socket SocketID.
+ //
+ // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE)
+ // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...)
+ //
+ // WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
+ // Byte6Seed, Byte7Seed, ByteEccSeed)
+ // Specifies the write leveling seed for a channel of a socket.
+ //
+ // HW_RXEN_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
+ // Byte6Seed, Byte7Seed, ByteEccSeed)
+ // Speicifes the HW RXEN training seed for a channel of a socket
+ //
+ NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1),
+ NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2),
+ MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
+ CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x05, 0x0A),
+ ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00),
+ CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
+
+ PSO_END
+};
+
+/*
+ * These tables are optional and may be used to adjust memory timing settings
+ */
+#include "mm.h"
+#include "mn.h"
+
+// Customer table
+UINT8 AGESA_MEM_TABLE_TN[][sizeof (MEM_TABLE_ALIAS)] =
+{
+ // Hardcoded Memory Training Values
+
+ // The following macro should be used to override training values for your platform
+ //
+ // DQSACCESS(MTAfterDqsRwPosTrn, MTNodes, MTDcts, MTDIMMs, BFRdDqsDly, MTOverride, 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x1c, 0x20),
+ //
+ // NOTE:
+ // The following training hardcode values are example values that were taken from a tilapia motherboard
+ // with a particular DIMM configuration. To hardcode your own values, uncomment the appropriate line in
+ // the table and replace the byte lane values with your own.
+ //
+ // ------------------ BYTE LANES ----------------------
+ // BL0 BL1 BL2 BL3 BL4 BL5 BL6 Bl7 ECC
+ // Write Data Timing
+ // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM0, BFWrDatDly, MTOverride, 0x1D, 0x20, 0x26, 0x2B, 0x37, 0x3A, 0x3e, 0x3F, 0x30),// DCT0, DIMM0
+ // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM1, BFWrDatDly, MTOverride, 0x1D, 0x00, 0x06, 0x0B, 0x17, 0x1A, 0x1E, 0x1F, 0x10),// DCT0, DIMM1
+ // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM0, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x27, 0x2B, 0x3B, 0x3B, 0x3E, 0x3E, 0x30),// DCT1, DIMM0
+ // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM1, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x1C, 0x0B, 0x17, 0x1A, 0x1D, 0x1C, 0x10),// DCT1, DIMM1
+
+ // DQS Receiver Enable
+ // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0
+ // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM1, BFRcvEnDly, MTOverride, 0x7C, 0x7D, 0x7E, 0x81, 0x88, 0x8F, 0x96, 0x9F, 0x84),// DCT0, DIMM1
+ // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT1, DIMM0
+ // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM1, BFRcvEnDly, MTOverride, 0x1C, 0x1D, 0x1E, 0x01, 0x08, 0x0F, 0x16, 0x1F, 0x04),// DCT1, DIMM1
+
+ // Write DQS Delays
+ // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFWrDqsDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0
+ // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFWrDqsDly, MTOverride, 0x06, 0x0D, 0x12, 0x1A, 0x25, 0x28, 0x2C, 0x2C, 0x44),// DCT0, DIMM1
+ // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFWrDqsDly, MTOverride, 0x07, 0x0E, 0x14, 0x1B, 0x24, 0x29, 0x2B, 0x2C, 0x1F),// DCT1, DIMM0
+ // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFWrDqsDly, MTOverride, 0x07, 0x0C, 0x14, 0x19, 0x25, 0x28, 0x2B, 0x2B, 0x1A),// DCT1, DIMM1
+
+ // Read DQS Delays
+ // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x0E, 0x10),// DCT0, DIMM0
+ // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT0, DIMM1
+ // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM0
+ // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM1
+ //--------------------------------------------------------------------------------------------------------------------------------------------------
+ // TABLE END
+ NBACCESS (MTEnd, 0, 0, 0, 0, 0), // End of Table
+};
+UINT8 SizeOfTableTN = sizeof (AGESA_MEM_TABLE_TN) / sizeof (AGESA_MEM_TABLE_TN[0]);
diff --git a/src/mainboard/amd/parmer/chip.h b/src/mainboard/amd/parmer/chip.h
new file mode 100644
index 0000000..352a6ff
--- /dev/null
+++ b/src/mainboard/amd/parmer/chip.h
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+extern struct chip_operations mainboard_ops;
+
+struct mainboard_config {};
diff --git a/src/mainboard/amd/parmer/cmos.layout b/src/mainboard/amd/parmer/cmos.layout
new file mode 100644
index 0000000..f6b5806
--- /dev/null
+++ b/src/mainboard/amd/parmer/cmos.layout
@@ -0,0 +1,114 @@
+#*****************************************************************************
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+#*****************************************************************************
+
+entries
+
+#start-bit length config config-ID name
+#0 8 r 0 seconds
+#8 8 r 0 alarm_seconds
+#16 8 r 0 minutes
+#24 8 r 0 alarm_minutes
+#32 8 r 0 hours
+#40 8 r 0 alarm_hours
+#48 8 r 0 day_of_week
+#56 8 r 0 day_of_month
+#64 8 r 0 month
+#72 8 r 0 year
+#80 4 r 0 rate_select
+#84 3 r 0 REF_Clock
+#87 1 r 0 UIP
+#88 1 r 0 auto_switch_DST
+#89 1 r 0 24_hour_mode
+#90 1 r 0 binary_values_enable
+#91 1 r 0 square-wave_out_enable
+#92 1 r 0 update_finished_enable
+#93 1 r 0 alarm_interrupt_enable
+#94 1 r 0 periodic_interrupt_enable
+#95 1 r 0 disable_clock_updates
+#96 288 r 0 temporary_filler
+0 384 r 0 reserved_memory
+384 1 e 4 boot_option
+385 1 e 4 last_boot
+386 1 e 1 ECC_memory
+388 4 r 0 reboot_bits
+392 3 e 5 baud_rate
+395 1 e 1 hw_scrubber
+396 1 e 1 interleave_chip_selects
+397 2 e 8 max_mem_clock
+399 1 e 2 multi_core
+400 1 e 1 power_on_after_fail
+412 4 e 6 debug_level
+416 4 e 7 boot_first
+420 4 e 7 boot_second
+424 4 e 7 boot_third
+428 4 h 0 boot_index
+432 8 h 0 boot_countdown
+440 4 e 9 slow_cpu
+444 1 e 1 nmi
+445 1 e 1 iommu
+728 256 h 0 user_data
+984 16 h 0 check_sum
+# Reserve the extended AMD configuration registers
+1000 24 r 0 amd_reserved
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+5 0 115200
+5 1 57600
+5 2 38400
+5 3 19200
+5 4 9600
+5 5 4800
+5 6 2400
+5 7 1200
+6 6 Notice
+6 7 Info
+6 8 Debug
+6 9 Spew
+7 0 Network
+7 1 HDD
+7 2 Floppy
+7 8 Fallback_Network
+7 9 Fallback_HDD
+7 10 Fallback_Floppy
+#7 3 ROM
+8 0 400Mhz
+8 1 333Mhz
+8 2 266Mhz
+8 3 200Mhz
+9 0 off
+9 1 87.5%
+9 2 75.0%
+9 3 62.5%
+9 4 50.0%
+9 5 37.5%
+9 6 25.0%
+9 7 12.5%
+
+checksums
+
+checksum 392 983 984
diff --git a/src/mainboard/amd/parmer/devicetree.cb b/src/mainboard/amd/parmer/devicetree.cb
new file mode 100644
index 0000000..376e017
--- /dev/null
+++ b/src/mainboard/amd/parmer/devicetree.cb
@@ -0,0 +1,86 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+#
+chip northbridge/amd/agesa/family15tn/root_complex
+ device lapic_cluster 0 on
+ chip cpu/amd/agesa/family15tn
+ device lapic 10 on end
+ end
+ end
+ device pci_domain 0 on
+ subsystemid 0x1022 0x1410 inherit
+ chip northbridge/amd/agesa/family15tn # CPU side of HT root complex
+# device pci 18.0 on # northbridge
+ chip northbridge/amd/agesa/family15tn # PCI side of HT root complex
+ device pci 0.0 on end # Root Complex
+ device pci 1.0 on end # Internal Graphics P2P bridge 0x9804
+ device pci 1.1 on end # Internal Multimedia
+ device pci 2.0 on end # PCIE SLOT0 x16
+ device pci 3.0 on end # PCIE SLOT0 x16
+ device pci 4.0 on end # PCIE MINI0
+ device pci 5.0 on end # PCIE MINI1
+ device pci 6.0 on end # PCIE Slot1 x1
+ device pci 7.0 on end # LAN
+ device pci 8.0 off end # NB/SB Link P2P bridge
+ end
+ chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus
+ device pci 10.0 on end # XHCI HC0
+ device pci 10.1 on end # XHCI HC1
+ device pci 11.0 on end # SATA
+ device pci 12.0 on end # USB
+ device pci 12.2 on end # USB
+ device pci 13.0 on end # USB
+ device pci 13.2 on end # USB
+ device pci 14.0 on # SM
+ chip drivers/generic/generic #dimm 0-0-0
+ device i2c 50 on end
+ end
+ chip drivers/generic/generic #dimm 0-0-1
+ device i2c 51 on end
+ end
+ chip drivers/generic/generic #dimm 0-1-0
+ device i2c 52 on end
+ end
+ chip drivers/generic/generic #dimm 0-1-1
+ device i2c 53 on end
+ end
+ end # SM
+ device pci 14.1 on end # IDE 0x439c
+ device pci 14.2 on end # HDA 0x4383
+ device pci 14.3 on end # LPC 0x439d
+ device pci 14.4 on end # PCI 0x4384 # PCI-b conflict with GPIO.
+ device pci 14.5 on end # USB 2
+# device pci 14.6 on end # Gec
+ device pci 14.7 on end
+ device pci 15.0 off end # PCIe 0
+ device pci 15.1 off end # PCIe 1
+ device pci 15.2 off end # PCIe 2
+ device pci 15.3 off end # PCIe 3
+ register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
+ register "gpp_configuration" = "4"
+ end #southbridge/amd/hudson
+ device pci 18.0 on end
+ #device pci 18.0 on end
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ device pci 18.4 on end
+ device pci 18.5 on end
+ end #chip northbridge/amd/agesa/family15tn # CPU side of HT root complex
+ end #pci_domain
+end #northbridge/amd/agesa/family15tn/root_complex
diff --git a/src/mainboard/amd/parmer/dimmSpd.c b/src/mainboard/amd/parmer/dimmSpd.c
new file mode 100644
index 0000000..576de7e
--- /dev/null
+++ b/src/mainboard/amd/parmer/dimmSpd.c
@@ -0,0 +1,164 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include "Porting.h"
+#include "AGESA.h"
+#include "amdlib.h"
+#include "dimmSpd.h"
+
+#define DIMENSION(array)(sizeof (array)/ sizeof (array [0]))
+
+/*#pragma optimize ("", off) // for source level debug
+ *---------------------------------------------------------------------------
+ *
+ * SPD address table - porting required
+ */
+
+static const UINT8 spdAddressLookup [2] [2] [4] = // socket, channel, dimm
+{
+ // socket 0
+ {
+ {0xA0, 0x00}, // channel 0 dimms
+ {0xA2, 0x00}, // channel 1 dimms
+ },
+ // socket 1
+ {
+ {0x00, 0x00}, // channel 0 dimms
+ {0x00, 0x00}, // channel 1 dimms
+ },
+};
+
+/*-----------------------------------------------------------------------------
+ *
+ * readSmbusByteData - read a single SPD byte from any offset
+ */
+
+static int readSmbusByteData (int iobase, int address, char *buffer, int offset)
+{
+ unsigned int status;
+ UINT64 limit;
+
+ address |= 1; // set read bit
+
+ __outbyte (iobase + 0, 0xFF); // clear error status
+ __outbyte (iobase + 1, 0x1F); // clear error status
+ __outbyte (iobase + 3, offset); // offset in eeprom
+ __outbyte (iobase + 4, address); // slave address and read bit
+ __outbyte (iobase + 2, 0x48); // read byte command
+
+ // time limit to avoid hanging for unexpected error status (should never happen)
+ limit = __rdtsc () + 2000000000 / 10;
+ for (;;)
+ {
+ status = __inbyte (iobase);
+ if (__rdtsc () > limit) break;
+ if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting
+ if ((status & 1) == 1) continue; // HostBusy set, keep waiting
+ break;
+ }
+
+ buffer [0] = __inbyte (iobase + 5);
+ if (status == 2) status = 0; // check for done with no errors
+ return status;
+}
+
+/*-----------------------------------------------------------------------------
+ *
+ * readSmbusByte - read a single SPD byte from the default offset
+ * this function is faster function readSmbusByteData
+ */
+
+static int readSmbusByte (int iobase, int address, char *buffer)
+{
+ unsigned int status;
+ UINT64 limit;
+
+ __outbyte (iobase + 0, 0xFF); // clear error status
+ __outbyte (iobase + 2, 0x44); // read command
+
+ // time limit to avoid hanging for unexpected error status
+ limit = __rdtsc () + 2000000000 / 10;
+ for (;;)
+ {
+ status = __inbyte (iobase);
+ if (__rdtsc () > limit) break;
+ if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting
+ if ((status & 1) == 1) continue; // HostBusy set, keep waiting
+ break;
+ }
+
+ buffer [0] = __inbyte (iobase + 5);
+ if (status == 2) status = 0; // check for done with no errors
+ return status;
+}
+
+/*---------------------------------------------------------------------------
+ *
+ * readspd - Read one or more SPD bytes from a DIMM.
+ * Start with offset zero and read sequentially.
+ * Optimization relies on autoincrement to avoid
+ * sending offset for every byte.
+ * Reads 128 bytes in 7-8 ms at 400 KHz.
+ */
+
+static int readspd (int iobase, int SmbusSlaveAddress, char *buffer, int count)
+{
+ int index, error;
+
+ /* read the first byte using offset zero */
+ error = readSmbusByteData (iobase, SmbusSlaveAddress, buffer, 0);
+ if (error) return error;
+
+ /* read the remaining bytes using auto-increment for speed */
+ for (index = 1; index < count; index++)
+ {
+ error = readSmbusByte (iobase, SmbusSlaveAddress, &buffer [index]);
+ if (error) return error;
+ }
+
+ return 0;
+}
+
+static void writePmReg (int reg, int data)
+{
+ __outbyte (0xCD6, reg);
+ __outbyte (0xCD7, data);
+}
+
+static void setupFch (int ioBase)
+{
+ writePmReg (0x2D, ioBase >> 8);
+ writePmReg (0x2C, ioBase | 1);
+ __outbyte (ioBase + 0x0E, 66000000 / 400000 / 4); // set SMBus clock to 400 KHz
+}
+
+AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info)
+{
+ int spdAddress, ioBase;
+
+ if (info->SocketId >= DIMENSION (spdAddressLookup )) return AGESA_ERROR;
+ if (info->MemChannelId >= DIMENSION (spdAddressLookup[0] )) return AGESA_ERROR;
+ if (info->DimmId >= DIMENSION (spdAddressLookup[0][0])) return AGESA_ERROR;
+
+ spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId];
+ if (spdAddress == 0) return AGESA_ERROR;
+ ioBase = 0xB00;
+ setupFch (ioBase);
+ return readspd (ioBase, spdAddress, (void *) info->Buffer, 128);
+}
diff --git a/src/mainboard/amd/parmer/dimmSpd.h b/src/mainboard/amd/parmer/dimmSpd.h
new file mode 100644
index 0000000..c19cecc
--- /dev/null
+++ b/src/mainboard/amd/parmer/dimmSpd.h
@@ -0,0 +1,59 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*----------------------------------------------------------------------------------------
+ * M O D U L E S U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#ifndef _DIMMSPD_H_
+#define _DIMMSPD_H_
+
+#include "Porting.h"
+#include "AGESA.h"
+
+/*----------------------------------------------------------------------------------------
+ * D E F I N I T I O N S A N D M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ * T Y P E D E F S A N D S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ * P R O T O T Y P E S O F L O C A L F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ * E X P O R T E D F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+AGESA_STATUS
+AmdMemoryReadSPD (IN UINT32 Func, IN UINT32 Data, IN OUT AGESA_READ_SPD_PARAMS *SpdData);
+
+/*---------------------------------------------------------------------------------------
+ * L O C A L F U N C T I O N S
+ *---------------------------------------------------------------------------------------
+ */
+
+#endif
diff --git a/src/mainboard/amd/parmer/dsdt.asl b/src/mainboard/amd/parmer/dsdt.asl
new file mode 100644
index 0000000..e0cc3fd
--- /dev/null
+++ b/src/mainboard/amd/parmer/dsdt.asl
@@ -0,0 +1,1421 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* DefinitionBlock Statement */
+DefinitionBlock (
+ "DSDT.AML", /* Output filename */
+ "DSDT", /* Signature */
+ 0x02, /* DSDT Revision, needs to be 2 for 64bit */
+ "AMD ", /* OEMID */
+ "PARMER ", /* TABLE ID */
+ 0x00010001 /* OEM Revision */
+ )
+{ /* Start of ASL file */
+ /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */
+
+ /* Data to be patched by the BIOS during POST */
+ /* FIXME the patching is not done yet! */
+ /* Memory related values */
+ Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
+ Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
+ Name(PBLN, 0x0) /* Length of BIOS area */
+
+ Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
+ Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
+ Name(HPBA, 0xFED00000) /* Base address of HPET table */
+
+ Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
+
+ /* USB overcurrent mapping pins. */
+ Name(UOM0, 0)
+ Name(UOM1, 2)
+ Name(UOM2, 0)
+ Name(UOM3, 7)
+ Name(UOM4, 2)
+ Name(UOM5, 2)
+ Name(UOM6, 6)
+ Name(UOM7, 2)
+ Name(UOM8, 6)
+ Name(UOM9, 6)
+
+ /* Some global data */
+ Name(OSTP, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
+ Name(OSV, Ones) /* Assume nothing */
+ Name(PMOD, One) /* Assume APIC */
+
+ /*
+ * Processor Object
+ *
+ */
+ Scope (\_PR) { /* define processor scope */
+ Processor(
+ P000, /* name space name */
+ 0, /* Unique number for this processor */
+ 0x810, /* PBLK system I/O address !hardcoded! */
+ 0x06 /* PBLKLEN for boot processor */
+ ) {
+ }
+
+ Processor(
+ P001, /* name space name */
+ 1, /* Unique number for this processor */
+ 0x0810, /* PBLK system I/O address !hardcoded! */
+ 0x06 /* PBLKLEN for boot processor */
+ ) {
+ }
+ Processor(
+ P002, /* name space name */
+ 2, /* Unique number for this processor */
+ 0x0810, /* PBLK system I/O address !hardcoded! */
+ 0x06 /* PBLKLEN for boot processor */
+ ) {
+ }
+ Processor(
+ P003, /* name space name */
+ 3, /* Unique number for this processor */
+ 0x0810, /* PBLK system I/O address !hardcoded! */
+ 0x06 /* PBLKLEN for boot processor */
+ ) {
+ }
+ Processor(
+ P004, /* name space name */
+ 4, /* Unique number for this processor */
+ 0x0810, /* PBLK system I/O address !hardcoded! */
+ 0x06 /* PBLKLEN for boot processor */
+ ) {
+ }
+ Processor(
+ P005, /* name space name */
+ 5, /* Unique number for this processor */
+ 0x0810, /* PBLK system I/O address !hardcoded! */
+ 0x06 /* PBLKLEN for boot processor */
+ ) {
+ }
+ Processor(
+ P006, /* name space name */
+ 6, /* Unique number for this processor */
+ 0x0810, /* PBLK system I/O address !hardcoded! */
+ 0x06 /* PBLKLEN for boot processor */
+ ) {
+ }
+ Processor(
+ P007, /* name space name */
+ 7, /* Unique number for this processor */
+ 0x0810, /* PBLK system I/O address !hardcoded! */
+ 0x06 /* PBLKLEN for boot processor */
+ ) {
+ }
+ } /* End _PR scope */
+
+ /* PIC IRQ mapping registers, C00h-C01h. */
+ OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
+ Field(PRQM, ByteAcc, NoLock, Preserve) {
+ PRQI, 0x00000008,
+ PRQD, 0x00000008, /* Offset: 1h */
+ }
+ IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
+ PIRA, 0x00000008, /* Index 0 */
+ PIRB, 0x00000008, /* Index 1 */
+ PIRC, 0x00000008, /* Index 2 */
+ PIRD, 0x00000008, /* Index 3 */
+ PIRE, 0x00000008, /* Index 4 */
+ PIRF, 0x00000008, /* Index 5 */
+ PIRG, 0x00000008, /* Index 6 */
+ PIRH, 0x00000008, /* Index 7 */
+ }
+
+ /* PCI Error control register */
+ OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001)
+ Field(PERC, ByteAcc, NoLock, Preserve) {
+ SENS, 0x00000001,
+ PENS, 0x00000001,
+ SENE, 0x00000001,
+ PENE, 0x00000001,
+ }
+
+ /* Client Management index/data registers */
+ OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002)
+ Field(CMT, ByteAcc, NoLock, Preserve) {
+ CMTI, 8,
+ /* Client Management Data register */
+ G64E, 1,
+ G64O, 1,
+ G32O, 2,
+ , 2,
+ GPSL, 2,
+ }
+
+ /* GPM Port register */
+ OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001)
+ Field(GPT, ByteAcc, NoLock, Preserve) {
+ GPB0,1,
+ GPB1,1,
+ GPB2,1,
+ GPB3,1,
+ GPB4,1,
+ GPB5,1,
+ GPB6,1,
+ GPB7,1,
+ }
+
+ /* Flash ROM program enable register */
+ OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001)
+ Field(FRE, ByteAcc, NoLock, Preserve) {
+ , 0x00000006,
+ FLRE, 0x00000001,
+ }
+
+ /* PM2 index/data registers */
+ OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002)
+ Field(PM2R, ByteAcc, NoLock, Preserve) {
+ PM2I, 0x00000008,
+ PM2D, 0x00000008,
+ }
+
+ /* Power Management I/O registers, TODO:PMIO is quite different in SB800. */
+ OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002)
+ Field(PIOR, ByteAcc, NoLock, Preserve) {
+ PIOI, 0x00000008,
+ PIOD, 0x00000008,
+ }
+ IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) {
+ Offset(0xEE),
+ UPWS, 3,
+ }
+
+ /* PM1 Event Block
+ * First word is PM1_Status, Second word is PM1_Enable
+ */
+ Scope(\_SB) {
+ /* PCIe Configuration Space for CONFIG_MMCONF_BUS_NUMBER busses */
+ OperationRegion(PCFG, SystemMemory, PCBA, PCLN)
+ Field(PCFG, ByteAcc, NoLock, Preserve) {
+ /* Byte offsets are computed using the following technique:
+ * ((bus number + 1) * ((device number * 8) * 4096)) + register offset
+ * The 8 comes from 8 functions per device, and 4096 bytes per function config space
+ */
+ Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */
+ STB5, 32,
+ Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */
+ PT0D, 1,
+ PT1D, 1,
+ PT2D, 1,
+ PT3D, 1,
+ PT4D, 1,
+ PT5D, 1,
+ PT6D, 1,
+ PT7D, 1,
+ PT8D, 1,
+ PT9D, 1,
+ Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */
+ SBIE, 1,
+ SBME, 1,
+ Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */
+ SBRI, 8,
+ Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */
+ SBB1, 32,
+ Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */
+ ,14,
+ P92E, 1, /* Port92 decode enable */
+ }
+
+ OperationRegion(SB5, SystemMemory, STB5, 0x1000)
+ Field(SB5, AnyAcc, NoLock, Preserve){
+ /* Port 0 */
+ Offset(0x120), /* Port 0 Task file status */
+ P0ER, 1,
+ , 2,
+ P0DQ, 1,
+ , 3,
+ P0BY, 1,
+ Offset(0x128), /* Port 0 Serial ATA status */
+ P0DD, 4,
+ , 4,
+ P0IS, 4,
+ Offset(0x12C), /* Port 0 Serial ATA control */
+ P0DI, 4,
+ Offset(0x130), /* Port 0 Serial ATA error */
+ , 16,
+ P0PR, 1,
+
+ /* Port 1 */
+ offset(0x1A0), /* Port 1 Task file status */
+ P1ER, 1,
+ , 2,
+ P1DQ, 1,
+ , 3,
+ P1BY, 1,
+ Offset(0x1A8), /* Port 1 Serial ATA status */
+ P1DD, 4,
+ , 4,
+ P1IS, 4,
+ Offset(0x1AC), /* Port 1 Serial ATA control */
+ P1DI, 4,
+ Offset(0x1B0), /* Port 1 Serial ATA error */
+ , 16,
+ P1PR, 1,
+
+ /* Port 2 */
+ Offset(0x220), /* Port 2 Task file status */
+ P2ER, 1,
+ , 2,
+ P2DQ, 1,
+ , 3,
+ P2BY, 1,
+ Offset(0x228), /* Port 2 Serial ATA status */
+ P2DD, 4,
+ , 4,
+ P2IS, 4,
+ Offset(0x22C), /* Port 2 Serial ATA control */
+ P2DI, 4,
+ Offset(0x230), /* Port 2 Serial ATA error */
+ , 16,
+ P2PR, 1,
+
+ /* Port 3 */
+ Offset(0x2A0), /* Port 3 Task file status */
+ P3ER, 1,
+ , 2,
+ P3DQ, 1,
+ , 3,
+ P3BY, 1,
+ Offset(0x2A8), /* Port 3 Serial ATA status */
+ P3DD, 4,
+ , 4,
+ P3IS, 4,
+ Offset(0x2AC), /* Port 3 Serial ATA control */
+ P3DI, 4,
+ Offset(0x2B0), /* Port 3 Serial ATA error */
+ , 16,
+ P3PR, 1,
+ }
+ }
+
+ #include "acpi/routing.asl"
+
+ Scope(\_SB) {
+
+ Method(CkOT, 0){
+
+ if(LNotEqual(OSTP, Ones)) {Return(OSTP)} /* OS version was already detected */
+
+ if(CondRefOf(\_OSI,Local1))
+ {
+ Store(1, OSTP) /* Assume some form of XP */
+ if (\_OSI("Windows 2006")) /* Vista */
+ {
+ Store(2, OSTP)
+ }
+ } else {
+ If(WCMP(\_OS,"Linux")) {
+ Store(3, OSTP) /* Linux */
+ } Else {
+ Store(4, OSTP) /* Gotta be WinCE */
+ }
+ }
+ Return(OSTP)
+ }
+
+ Method(_PIC, 0x01, NotSerialized)
+ {
+ If (Arg0)
+ {
+ \_SB.CIRQ()
+ }
+ Store(Arg0, PMOD)
+ }
+ Method(CIRQ, 0x00, NotSerialized){
+ //Store(0, PIRA)
+ //Store(0, PIRB)
+ //Store(0, PIRC)
+ //Store(0, PIRD)
+ //Store(0, PIRE)
+ //Store(0, PIRF)
+ //Store(0, PIRG)
+ //Store(0, PIRH)
+ }
+
+ Name(IRQB, ResourceTemplate(){
+ IRQ(Level,ActiveLow,Shared){15}
+ })
+
+ Name(IRQP, ResourceTemplate(){
+ IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15}
+ })
+
+ Name(PITF, ResourceTemplate(){
+ IRQ(Level,ActiveLow,Exclusive){9}
+ })
+
+ Device(INTA) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 1)
+
+ Method(_STA, 0) {
+ if (PIRA) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTA._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKA\\_DIS\n") */
+ //Store(0x1F, PIRA)
+ } /* End Method(_SB.INTA._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKA\\_PRS\n") */
+ Return(IRQP)
+ } /* Method(_SB.INTA._PRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKA\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PIRA, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTA._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKA\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ //Store(Local0, PIRA)
+ } /* End Method(_SB.INTA._SRS) */
+ } /* End Device(INTA) */
+
+ Device(INTB) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 2)
+
+ Method(_STA, 0) {
+ if (PIRB) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTB._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKB\\_DIS\n") */
+ //Store(0, PIRB)
+ } /* End Method(_SB.INTB._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKB\\_PRS\n") */
+ Return(IRQP)
+ } /* Method(_SB.INTB._PRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKB\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PIRB, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTB._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKB\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PIRB)
+ } /* End Method(_SB.INTB._SRS) */
+ } /* End Device(INTB) */
+
+ Device(INTC) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 3)
+
+ Method(_STA, 0) {
+ if (PIRC) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTC._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKC\\_DIS\n") */
+ //Store(0, PIRC)
+ } /* End Method(_SB.INTC._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKC\\_PRS\n") */
+ Return(IRQP)
+ } /* Method(_SB.INTC._PRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKC\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PIRC, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTC._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKC\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PIRC)
+ } /* End Method(_SB.INTC._SRS) */
+ } /* End Device(INTC) */
+
+ Device(INTD) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 4)
+
+ Method(_STA, 0) {
+ if (PIRD) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTD._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKD\\_DIS\n") */
+ //Store(0, PIRD)
+ } /* End Method(_SB.INTD._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKD\\_PRS\n") */
+ Return(IRQP)
+ } /* Method(_SB.INTD._PRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKD\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PIRD, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTD._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKD\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PIRD)
+ } /* End Method(_SB.INTD._SRS) */
+ } /* End Device(INTD) */
+
+ Device(INTE) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 5)
+
+ Method(_STA, 0) {
+ if (PIRE) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTE._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKE\\_DIS\n") */
+ //Store(0, PIRE)
+ } /* End Method(_SB.INTE._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKE\\_PRS\n") */
+ Return(IRQP)
+ } /* Method(_SB.INTE._PRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKE\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PIRE, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTE._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKE\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PIRE)
+ } /* End Method(_SB.INTE._SRS) */
+ } /* End Device(INTE) */
+
+ Device(INTF) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 6)
+
+ Method(_STA, 0) {
+ if (PIRF) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTF._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKF\\_DIS\n") */
+ //Store(0, PIRF)
+ } /* End Method(_SB.INTF._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKF\\_PRS\n") */
+ Return(PITF)
+ } /* Method(_SB.INTF._PRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKF\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PIRF, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTF._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKF\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PIRF)
+ } /* End Method(_SB.INTF._SRS) */
+ } /* End Device(INTF) */
+
+ Device(INTG) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 7)
+
+ Method(_STA, 0) {
+ if (PIRG) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTG._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKG\\_DIS\n") */
+ //Store(0, PIRG)
+ } /* End Method(_SB.INTG._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKG\\_PRS\n") */
+ Return(IRQP)
+ } /* Method(_SB.INTG._CRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKG\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PIRG, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTG._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKG\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ Store(Local0, PIRG)
+ } /* End Method(_SB.INTG._SRS) */
+ } /* End Device(INTG) */
+
+ Device(INTH) {
+ Name(_HID, EISAID("PNP0C0F"))
+ Name(_UID, 8)
+
+ Method(_STA, 0) {
+ if (PIRH) {
+ Return(0x0B) /* sata is invisible */
+ } else {
+ Return(0x09) /* sata is disabled */
+ }
+ } /* End Method(_SB.INTH._STA) */
+
+ Method(_DIS ,0) {
+ /* DBGO("\\_SB\\LNKH\\_DIS\n") */
+ //Store(0, PIRH)
+ } /* End Method(_SB.INTH._DIS) */
+
+ Method(_PRS ,0) {
+ /* DBGO("\\_SB\\LNKH\\_PRS\n") */
+ Return(IRQP)
+ } /* Method(_SB.INTH._CRS) */
+
+ Method(_CRS ,0) {
+ /* DBGO("\\_SB\\LNKH\\_CRS\n") */
+ CreateWordField(IRQB, 0x1, IRQN)
+ ShiftLeft(1, PIRH, IRQN)
+ Return(IRQB)
+ } /* Method(_SB.INTH._CRS) */
+
+ Method(_SRS, 1) {
+ /* DBGO("\\_SB\\LNKH\\_CRS\n") */
+ CreateWordField(ARG0, 1, IRQM)
+
+ /* Use lowest available IRQ */
+ FindSetRightBit(IRQM, Local0)
+ if (Local0) {
+ Decrement(Local0)
+ }
+ //Store(Local0, PIRH)
+ } /* End Method(_SB.INTH._SRS) */
+ } /* End Device(INTH) */
+
+ } /* End Scope(_SB) */
+
+ /* Supported sleep states: */
+ Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */
+
+ If (LAnd(SSFG, 0x01)) {
+ Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */
+ }
+ If (LAnd(SSFG, 0x02)) {
+ Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */
+ }
+ If (LAnd(SSFG, 0x04)) {
+ Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */
+ }
+ If (LAnd(SSFG, 0x08)) {
+ Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */
+ }
+
+ Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */
+
+ Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */
+ Name(CSMS, 0) /* Current System State */
+
+ /* Wake status package */
+ Name(WKST,Package(){Zero, Zero})
+
+ /*
+ * \_PTS - Prepare to Sleep method
+ *
+ * Entry:
+ * Arg0=The value of the sleeping state S1=1, S2=2, etc
+ *
+ * Exit:
+ * -none-
+ *
+ * The _PTS control method is executed at the beginning of the sleep process
+ * for S1-S5. The sleeping value is passed to the _PTS control method. This
+ * control method may be executed a relatively long time before entering the
+ * sleep state and the OS may abort the operation without notification to
+ * the ACPI driver. This method cannot modify the configuration or power
+ * state of any device in the system.
+ */
+ Method(_PTS, 1) {
+ /* DBGO("\\_PTS\n") */
+ /* DBGO("From S0 to S") */
+ /* DBGO(Arg0) */
+ /* DBGO("\n") */
+
+ /* Don't allow PCIRST# to reset USB */
+ //if (LEqual(Arg0,3)){
+ // Store(0,URRE)
+ //}
+
+ /* Clear sleep SMI status flag and enable sleep SMI trap. */
+ /*Store(One, CSSM)
+ Store(One, SSEN)*/
+
+ /* On older chips, clear PciExpWakeDisEn */
+ /*if (LLessEqual(\_SB.SBRI, 0x13)) {
+ * Store(0,\_SB.PWDE)
+ *}
+ */
+
+ /* Clear wake status structure. */
+ Store(0, Index(WKST,0))
+ Store(0, Index(WKST,1))
+ Store(7, UPWS)
+ } /* End Method(\_PTS) */
+
+ /*
+ * The following method results in a "not a valid reserved NameSeg"
+ * warning so I have commented it out for the duration. It isn't
+ * used, so it could be removed.
+ *
+ *
+ * \_GTS OEM Going To Sleep method
+ *
+ * Entry:
+ * Arg0=The value of the sleeping state S1=1, S2=2
+ *
+ * Exit:
+ * -none-
+ *
+ * Method(\_GTS, 1) {
+ * DBGO("\\_GTS\n")
+ * DBGO("From S0 to S")
+ * DBGO(Arg0)
+ * DBGO("\n")
+ * }
+ */
+
+ /*
+ * \_BFS OEM Back From Sleep method
+ *
+ * Entry:
+ * Arg0=The value of the sleeping state S1=1, S2=2
+ *
+ * Exit:
+ * -none-
+ */
+ Method(\_BFS, 1) {
+ /* DBGO("\\_BFS\n") */
+ /* DBGO("From S") */
+ /* DBGO(Arg0) */
+ /* DBGO(" to S0\n") */
+ }
+
+ /*
+ * \_WAK System Wake method
+ *
+ * Entry:
+ * Arg0=The value of the sleeping state S1=1, S2=2
+ *
+ * Exit:
+ * Return package of 2 DWords
+ * Dword 1 - Status
+ * 0x00000000 wake succeeded
+ * 0x00000001 Wake was signaled but failed due to lack of power
+ * 0x00000002 Wake was signaled but failed due to thermal condition
+ * Dword 2 - Power Supply state
+ * if non-zero the effective S-state the power supply entered
+ */
+ Method(\_WAK, 1) {
+ /* DBGO("\\_WAK\n") */
+ /* DBGO("From S") */
+ /* DBGO(Arg0) */
+ /* DBGO(" to S0\n") */
+
+ /* Re-enable HPET */
+ //Store(1,HPDE)
+
+ /* Restore PCIRST# so it resets USB */
+ //if (LEqual(Arg0,3)){
+ // Store(1,URRE)
+ //}
+
+ /* Arbitrarily clear PciExpWakeStatus */
+ //Store(PWST, PWST)
+
+ /* if(DeRefOf(Index(WKST,0))) {
+ * Store(0, Index(WKST,1))
+ * } else {
+ * Store(Arg0, Index(WKST,1))
+ * }
+ */
+ Return(WKST)
+ } /* End Method(\_WAK) */
+
+ Scope(\_GPE) { /* Start Scope GPE */
+ /* General event 0 */
+ /* Method(_L00) {
+ * DBGO("\\_GPE\\_L00\n")
+ * }
+ */
+
+ /* General event 1 */
+ /* Method(_L01) {
+ * DBGO("\\_GPE\\_L00\n")
+ * }
+ */
+
+ /* General event 2 */
+ /* Method(_L02) {
+ * DBGO("\\_GPE\\_L00\n")
+ * }
+ */
+
+ /* General event 3 */
+ Method(_L03) {
+ /* DBGO("\\_GPE\\_L00\n") */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+
+ /* General event 4 */
+ /* Method(_L04) {
+ * DBGO("\\_GPE\\_L00\n")
+ * }
+ */
+
+ /* General event 5 */
+ /* Method(_L05) {
+ * DBGO("\\_GPE\\_L00\n")
+ * }
+ */
+
+ /* General event 6 - Used for GPM6, moved to USB.asl */
+ /* Method(_L06) {
+ * DBGO("\\_GPE\\_L00\n")
+ * }
+ */
+
+ /* General event 7 - Used for GPM7, moved to USB.asl */
+ /* Method(_L07) {
+ * DBGO("\\_GPE\\_L07\n")
+ * }
+ */
+
+ /* Legacy PM event */
+ Method(_L08) {
+ /* DBGO("\\_GPE\\_L08\n") */
+ }
+
+ /* Temp warning (TWarn) event */
+ Method(_L09) {
+ /* DBGO("\\_GPE\\_L09\n") */
+ /* Notify (\_TZ.TZ00, 0x80) */
+ }
+
+ /* Reserved */
+ /* Method(_L0A) {
+ * DBGO("\\_GPE\\_L0A\n")
+ * }
+ */
+
+ /* USB controller PME# */
+ Method(_L0B) {
+ /* DBGO("\\_GPE\\_L0B\n") */
+ Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+
+ /* AC97 controller PME# */
+ /* Method(_L0C) {
+ * DBGO("\\_GPE\\_L0C\n")
+ * }
+ */
+
+ /* OtherTherm PME# */
+ /* Method(_L0D) {
+ * DBGO("\\_GPE\\_L0D\n")
+ * }
+ */
+
+ /* GPM9 SCI event - Moved to USB.asl */
+ /* Method(_L0E) {
+ * DBGO("\\_GPE\\_L0E\n")
+ * }
+ */
+
+ /* PCIe HotPlug event */
+ /* Method(_L0F) {
+ * DBGO("\\_GPE\\_L0F\n")
+ * }
+ */
+
+ /* ExtEvent0 SCI event */
+ Method(_L10) {
+ /* DBGO("\\_GPE\\_L10\n") */
+ }
+
+ /* ExtEvent1 SCI event */
+ Method(_L11) {
+ /* DBGO("\\_GPE\\_L11\n") */
+ }
+
+ /* PCIe PME# event */
+ /* Method(_L12) {
+ * DBGO("\\_GPE\\_L12\n")
+ * }
+ */
+
+ /* GPM0 SCI event - Moved to USB.asl */
+ /* Method(_L13) {
+ * DBGO("\\_GPE\\_L13\n")
+ * }
+ */
+
+ /* GPM1 SCI event - Moved to USB.asl */
+ /* Method(_L14) {
+ * DBGO("\\_GPE\\_L14\n")
+ * }
+ */
+
+ /* GPM2 SCI event - Moved to USB.asl */
+ /* Method(_L15) {
+ * DBGO("\\_GPE\\_L15\n")
+ * }
+ */
+
+ /* GPM3 SCI event - Moved to USB.asl */
+ /* Method(_L16) {
+ * DBGO("\\_GPE\\_L16\n")
+ * }
+ */
+
+ /* GPM8 SCI event - Moved to USB.asl */
+ /* Method(_L17) {
+ * DBGO("\\_GPE\\_L17\n")
+ * }
+ */
+
+ /* GPIO0 or GEvent8 event */
+ Method(_L18) {
+ /* DBGO("\\_GPE\\_L18\n") */
+ Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+
+ /* GPM4 SCI event - Moved to USB.asl */
+ /* Method(_L19) {
+ * DBGO("\\_GPE\\_L19\n")
+ * }
+ */
+
+ /* GPM5 SCI event - Moved to USB.asl */
+ /* Method(_L1A) {
+ * DBGO("\\_GPE\\_L1A\n")
+ * }
+ */
+
+ /* Azalia SCI event */
+ Method(_L1B) {
+ /* DBGO("\\_GPE\\_L1B\n") */
+ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+
+ /* GPM6 SCI event - Reassigned to _L06 */
+ /* Method(_L1C) {
+ * DBGO("\\_GPE\\_L1C\n")
+ * }
+ */
+
+ /* GPM7 SCI event - Reassigned to _L07 */
+ /* Method(_L1D) {
+ * DBGO("\\_GPE\\_L1D\n")
+ * }
+ */
+
+ /* GPIO2 or GPIO66 SCI event */
+ /* Method(_L1E) {
+ * DBGO("\\_GPE\\_L1E\n")
+ * }
+ */
+
+ /* SATA SCI event - Moved to sata.asl */
+ /* Method(_L1F) {
+ * DBGO("\\_GPE\\_L1F\n")
+ * }
+ */
+
+ } /* End Scope GPE */
+
+ //#include "acpi/usb.asl"
+
+ /* System Bus */
+ Scope(\_SB) { /* Start \_SB scope */
+ #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */
+
+ /* _SB.PCI0 */
+ /* Note: Only need HID on Primary Bus */
+ Device(PCI0) {
+ External (TOM1)
+ External (TOM2)
+ Name(_HID, EISAID("PNP0A03"))
+ Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
+ Method(_BBN, 0) { /* Bus number = 0 */
+ Return(0)
+ }
+ Method(_STA, 0) {
+ /* DBGO("\\_SB\\PCI0\\_STA\n") */
+ Return(0x0B) /* Status is visible */
+ }
+
+ Method(_PRT,0) {
+ If(PMOD){ Return(APR0) } /* APIC mode */
+ Return (PR0) /* PIC Mode */
+ } /* end _PRT */
+
+ /* Describe the Northbridge devices Dev0 ,Func0*/
+ Device(AMRT) {
+ Name(_ADR, 0x00000000)
+ } /* end AMRT */
+
+#if 0 //not used in Parmer
+ /* Dev3 is also an external GFX bridge */
+ Device(PBR3) {
+ Name(_ADR, 0x00030000)
+ Name(_PRW, Package() {0x18, 4})
+ Method(_PRT,0) {
+ If(PMOD){ Return(APS3) } /* APIC mode */
+ Return (PS3) /* PIC Mode */
+ } /* end _PRT */
+ } /* end PBR3 */
+#endif
+
+ Device(PBR4) {
+ Name(_ADR, 0x00040000)
+ Name(_PRW, Package() {0x18, 4})
+ Method(_PRT,0) {
+ If(PMOD){ Return(APS4) } /* APIC mode */
+ Return (PS4) /* PIC Mode */
+ } /* end _PRT */
+ } /* end PBR4 */
+
+ Device(PBR5) {
+ Name(_ADR, 0x00050000)
+ Name(_PRW, Package() {0x18, 4})
+ Method(_PRT,0) {
+ If(PMOD){ Return(APS5) } /* APIC mode */
+ Return (PS5) /* PIC Mode */
+ } /* end _PRT */
+ } /* end PBR5 */
+
+ Device(PBR6) {
+ Name(_ADR, 0x00060000)
+ Name(_PRW, Package() {0x18, 4})
+ Method(_PRT,0) {
+ If(PMOD){ Return(APS6) } /* APIC mode */
+ Return (PS6) /* PIC Mode */
+ } /* end _PRT */
+ } /* end PBR6 */
+
+ /* The onboard EtherNet chip */
+ Device(PBR7) {
+ Name(_ADR, 0x00070000)
+ Name(_PRW, Package() {0x18, 4})
+ Method(_PRT,0) {
+ If(PMOD){ Return(APS7) } /* APIC mode */
+ Return (PS7) /* PIC Mode */
+ } /* end _PRT */
+ } /* end PBR7 */
+
+ /* PCI slot 1, 2, 3 */
+ Device(PIBR) {
+ Name(_ADR, 0x00140004)
+ Name(_PRW, Package() {0x18, 4})
+
+ Method(_PRT, 0) {
+ Return (PCIB)
+ }
+ }
+
+ /* Describe the Southbridge devices */
+ Device(STCR) {
+ Name(_ADR, 0x00110000)
+ //#include "acpi/sata.asl"
+ } /* end STCR */
+
+ Device(UOH1) {
+ Name(_ADR, 0x00120000)
+ Name(_PRW, Package() {0x0B, 3})
+ } /* end UOH1 */
+
+ Device(UOH2) {
+ Name(_ADR, 0x00120002)
+ Name(_PRW, Package() {0x0B, 3})
+ } /* end UOH2 */
+
+ Device(UOH3) {
+ Name(_ADR, 0x00130000)
+ Name(_PRW, Package() {0x0B, 3})
+ } /* end UOH3 */
+
+ Device(UOH4) {
+ Name(_ADR, 0x00130002)
+ Name(_PRW, Package() {0x0B, 3})
+ } /* end UOH4 */
+
+ Device(UOH5) {
+ Name(_ADR, 0x00160000)
+ Name(_PRW, Package() {0x0B, 3})
+ } /* end UOH5 */
+
+ Device(UOH6) {
+ Name(_ADR, 0x00160002)
+ Name(_PRW, Package() {0x0B, 3})
+ } /* end UOH5 */
+
+ Device(UEH1) {
+ Name(_ADR, 0x00140005)
+ Name(_PRW, Package() {0x0B, 3})
+ } /* end UEH1 */
+
+ Device(XHC0) {
+ Name(_ADR, 0x00100000)
+ Name(_PRW, Package() {0x0B, 4})
+ } /* end XHC0 */
+ Device(XHC1) {
+ Name(_ADR, 0x00100001)
+ Name(_PRW, Package() {0x0B, 4})
+ } /* end XHC1 */
+
+ Device(SBUS) {
+ Name(_ADR, 0x00140000)
+ } /* end SBUS */
+
+ /* Primary (and only) IDE channel */
+ Device(IDEC) {
+ Name(_ADR, 0x00140001)
+ //#include "acpi/ide.asl"
+ } /* end IDEC */
+
+ Device(AZHD) {
+ Name(_ADR, 0x00140002)
+ OperationRegion(AZPD, PCI_Config, 0x00, 0x100)
+ Field(AZPD, AnyAcc, NoLock, Preserve) {
+ offset (0x42),
+ NSDI, 1,
+ NSDO, 1,
+ NSEN, 1,
+ offset (0x44),
+ IPCR, 4,
+ offset (0x54),
+ PWST, 2,
+ , 6,
+ PMEB, 1,
+ , 6,
+ PMST, 1,
+ offset (0x62),
+ MMCR, 1,
+ offset (0x64),
+ MMLA, 32,
+ offset (0x68),
+ MMHA, 32,
+ offset (0x6C),
+ MMDT, 16,
+ }
+
+ Method(_INI) {
+ If(LEqual(OSTP,3)){ /* If we are running Linux */
+ Store(zero, NSEN)
+ Store(one, NSDO)
+ Store(one, NSDI)
+ }
+ }
+ } /* end AZHD */
+
+ Device(LIBR) {
+ Name(_ADR, 0x00140003)
+ /* Method(_INI) {
+ * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")
+ } */ /* End Method(_SB.SBRDG._INI) */
+
+ /* Real Time Clock Device */
+ Device(RTC0) {
+ Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */
+ Name(_CRS, ResourceTemplate() {
+ IRQNoFlags(){8}
+ IO(Decode16,0x0070, 0x0070, 0, 2)
+ /* IO(Decode16,0x0070, 0x0070, 0, 4) */
+ })
+ } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */
+
+ Device(TMR) { /* Timer */
+ Name(_HID,EISAID("PNP0100")) /* System Timer */
+ Name(_CRS, ResourceTemplate() {
+ IRQNoFlags(){0}
+ IO(Decode16, 0x0040, 0x0040, 0, 4)
+ /* IO(Decode16, 0x0048, 0x0048, 0, 4) */
+ })
+ } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */
+
+ Device(SPKR) { /* Speaker */
+ Name(_HID,EISAID("PNP0800")) /* AT style speaker */
+ Name(_CRS, ResourceTemplate() {
+ IO(Decode16, 0x0061, 0x0061, 0, 1)
+ })
+ } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */
+
+ Device(PIC) {
+ Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */
+ Name(_CRS, ResourceTemplate() {
+ IRQNoFlags(){2}
+ IO(Decode16,0x0020, 0x0020, 0, 2)
+ IO(Decode16,0x00A0, 0x00A0, 0, 2)
+ /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */
+ /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */
+ })
+ } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */
+
+ Device(MAD) { /* 8257 DMA */
+ Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */
+ Name(_CRS, ResourceTemplate() {
+ DMA(Compatibility,BusMaster,Transfer8){4}
+ IO(Decode16, 0x0000, 0x0000, 0x10, 0x10)
+ IO(Decode16, 0x0081, 0x0081, 0x01, 0x03)
+ IO(Decode16, 0x0087, 0x0087, 0x01, 0x01)
+ IO(Decode16, 0x0089, 0x0089, 0x01, 0x03)
+ IO(Decode16, 0x008F, 0x008F, 0x01, 0x01)
+ IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20)
+ }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */
+ } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */
+
+ Device(COPR) {
+ Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */
+ Name(_CRS, ResourceTemplate() {
+ IO(Decode16, 0x00F0, 0x00F0, 0, 0x10)
+ IRQNoFlags(){13}
+ })
+ } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
+ } /* end LIBR */
+
+ Device(HPBR) {
+ Name(_ADR, 0x00140004)
+ } /* end HostPciBr */
+
+ Device(ACAD) {
+ Name(_ADR, 0x00140005)
+ } /* end Ac97audio */
+
+ Device(ACMD) {
+ Name(_ADR, 0x00140006)
+ } /* end Ac97modem */
+
+ Name(CRES, ResourceTemplate() {
+ IO(Decode16, 0x0CF8, 0x0CF8, 1, 8)
+
+ WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, /* address granularity */
+ 0x0000, /* range minimum */
+ 0x0CF7, /* range maximum */
+ 0x0000, /* translation */
+ 0x0CF8 /* length */
+ )
+ WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, /* address granularity */
+ 0x03B0, /* range minimum */
+ 0x03DF, /* range maximum */
+ 0x0000, /* translation */
+ 0x0030 /* length */
+ )
+
+ WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, /* address granularity */
+ 0x0D00, /* range minimum */
+ 0xFFFF, /* range maximum */
+ 0x0000, /* translation */
+ 0xF300 /* length */
+ )
+
+ Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */
+ Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */
+ /* memory space for PCI BARs below 4GB */
+ Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO)
+ }) /* End Name(_SB.PCI0.CRES) */
+
+ Method(_CRS, 0) {
+ /* DBGO("\\_SB\\PCI0\\_CRS\n") */
+ CreateDWordField(CRES, ^MMIO._BAS, MM1B)
+ CreateDWordField(CRES, ^MMIO._LEN, MM1L)
+ /*
+ * Declare memory between TOM1 and 4GB as available
+ * for PCI MMIO.
+ * Use ShiftLeft to avoid 64bit constant (for XP).
+ * This will work even if the OS does 32bit arithmetic, as
+ * 32bit (0x00000000 - TOM1) will wrap and give the same
+ * result as 64bit (0x100000000 - TOM1).
+ */
+ Store(TOM1, MM1B)
+ ShiftLeft(0x10000000, 4, Local0)
+ Subtract(Local0, TOM1, Local0)
+ Store(Local0, MM1L)
+
+ Return(CRES) /* note to change the Name buffer */
+ } /* end of Method(_SB.PCI0._CRS) */
+
+ /*
+ *
+ * FIRST METHOD CALLED UPON BOOT
+ *
+ * 1. If debugging, print current OS and ACPI interpreter.
+ * 2. Get PCI Interrupt routing from ACPI VSM, this
+ * value is based on user choice in BIOS setup.
+ */
+ Method(_INI, 0) {
+ /* DBGO("\\_SB\\_INI\n") */
+ /* DBGO(" DSDT.ASL code from ") */
+ /* DBGO(__DATE__) */
+ /* DBGO(" ") */
+ /* DBGO(__TIME__) */
+ /* DBGO("\n Sleep states supported: ") */
+ /* DBGO("\n") */
+ /* DBGO(" \\_OS=") */
+ /* DBGO(\_OS) */
+ /* DBGO("\n \\_REV=") */
+ /* DBGO(\_REV) */
+ /* DBGO("\n") */
+
+ /* Determine the OS we're running on */
+ CkOT()
+
+ /* On older chips, clear PciExpWakeDisEn */
+ /*if (LLessEqual(\SBRI, 0x13)) {
+ * Store(0,\PWDE)
+ * }
+ */
+ /* TODO: It is unstable. */
+ //#include "acpi/AmdImc.asl" /* Hudson IMC function */
+ //ITZE() /* enable IMC Fan Control*/
+ } /* End Method(_SB._INI) */
+ } /* End Device(PCI0) */
+
+ Device(PWRB) { /* Start Power button device */
+ Name(_HID, EISAID("PNP0C0C"))
+ Name(_UID, 0xAA)
+ Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */
+ Name(_STA, 0x0B) /* sata is invisible */
+ }
+ } /* End \_SB scope */
+
+ Scope(\_SI) {
+ Method(_SST, 1) {
+ /* DBGO("\\_SI\\_SST\n") */
+ /* DBGO(" New Indicator state: ") */
+ /* DBGO(Arg0) */
+ /* DBGO("\n") */
+ }
+ } /* End Scope SI */
+}
+/* End of ASL file */
diff --git a/src/mainboard/amd/parmer/get_bus_conf.c b/src/mainboard/amd/parmer/get_bus_conf.c
new file mode 100644
index 0000000..ad5e1d7
--- /dev/null
+++ b/src/mainboard/amd/parmer/get_bus_conf.c
@@ -0,0 +1,140 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <string.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include <cpu/amd/amdfam14.h>
+#include "agesawrapper.h"
+
+/* Global variables for MB layouts and these will be shared by irqtable mptable
+ * and acpi_tables busnum is default.
+ */
+u8 bus_isa;
+u8 bus_sb800[3];
+u32 apicid_sb800;
+
+/*
+ * Here you only need to set value in pci1234 for HT-IO that could be installed or not
+ * You may need to preset pci1234 for HTIO board,
+ * please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
+ */
+u32 pci1234x[] = {
+ 0x0000ff0,
+};
+
+u32 bus_type[256];
+u32 sbdn_sb800;
+
+static u32 get_bus_conf_done = 0;
+
+#if CONFIG_HAVE_ACPI_RESUME == 1
+extern u8 acpi_slp_type;
+#endif
+void get_bus_conf(void)
+{
+ u32 apicid_base;
+ u32 status;
+
+ device_t dev;
+ int i, j;
+
+ if (get_bus_conf_done == 1)
+ return; /* do it only once */
+
+ get_bus_conf_done = 1;
+
+ /*
+ * This is the call to AmdInitLate. It is really in the wrong place, conceptually,
+ * but functionally within the coreboot model, this is the best place to make the
+ * call. The logically correct place to call AmdInitLate is after PCI scan is done,
+ * after the decision about S3 resume is made, and before the system tables are
+ * written into RAM. The routine that is responsible for writing the tables is
+ * "write_tables", called near the end of "hardwaremain". There is no platform
+ * specific entry point between the S3 resume decision point and the call to
+ * "write_tables", and the next platform specific entry points are the calls to
+ * the ACPI table write functions. The first of ose would seem to be the right
+ * place, but other table write functions, e.g. the PIRQ table write function, are
+ * called before the ACPI tables are written. This routine is called at the beginning
+ * of each of the write functions called prior to the ACPI write functions, so this
+ * becomes the best place for this call.
+ */
+#if CONFIG_HAVE_ACPI_RESUME == 1
+ if (acpi_slp_type != 3) {
+ status = agesawrapper_amdinitlate();
+ if(status) {
+ printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status);
+ }
+ status = agesawrapper_amdS3Save();
+ if (status) {
+ printk(BIOS_DEBUG, "agesawrapper_amds3save failed: %x \n", status);
+ }
+ }
+#else
+ status = agesawrapper_amdinitlate();
+ if (status)
+ printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status);
+#endif
+
+ sbdn_sb800 = 0;
+
+ for (i = 0; i < 3; i++) {
+ bus_sb800[i] = 0;
+ }
+
+ for (i = 0; i < 256; i++) {
+ bus_type[i] = 0; /* default ISA bus. */
+ }
+
+ bus_type[0] = 1; /* pci */
+
+ // bus_sb800[0] = (sysconf.pci1234[0] >> 16) & 0xff;
+ bus_sb800[0] = (pci1234x[0] >> 16) & 0xff;
+
+ /* sb800 */
+ dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, 4));
+
+ if (dev) {
+ bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+
+ bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+ bus_isa++;
+ for (j = bus_sb800[1]; j < bus_isa; j++)
+ bus_type[j] = 1;
+ }
+
+ for (i = 0; i < 4; i++) {
+ dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, i));
+ if (dev) {
+ bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+ bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+ bus_isa++;
+ }
+ }
+ for (j = bus_sb800[2]; j < bus_isa; j++)
+ bus_type[j] = 1;
+
+ /* I/O APICs: APIC ID Version State Address */
+ bus_isa = 10;
+ apicid_base = CONFIG_MAX_CPUS;
+ apicid_sb800 = apicid_base;
+}
diff --git a/src/mainboard/amd/parmer/irq_tables.c b/src/mainboard/amd/parmer/irq_tables.c
new file mode 100644
index 0000000..3bcd3fb
--- /dev/null
+++ b/src/mainboard/amd/parmer/irq_tables.c
@@ -0,0 +1,112 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/pci.h>
+#include <string.h>
+#include <stdint.h>
+#include <arch/pirq_routing.h>
+#include <cpu/amd/amdfam15.h>
+
+static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
+ u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
+ u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
+ u8 slot, u8 rfu)
+{
+ pirq_info->bus = bus;
+ pirq_info->devfn = devfn;
+ pirq_info->irq[0].link = link0;
+ pirq_info->irq[0].bitmap = bitmap0;
+ pirq_info->irq[1].link = link1;
+ pirq_info->irq[1].bitmap = bitmap1;
+ pirq_info->irq[2].link = link2;
+ pirq_info->irq[2].bitmap = bitmap2;
+ pirq_info->irq[3].link = link3;
+ pirq_info->irq[3].bitmap = bitmap3;
+ pirq_info->slot = slot;
+ pirq_info->rfu = rfu;
+}
+
+extern u8 bus_isa;
+extern u8 bus_sb800[2];
+extern unsigned long sbdn_sb800;
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+ struct irq_routing_table *pirq;
+ struct irq_info *pirq_info;
+ u32 slot_num;
+ u8 *v;
+
+ u8 sum = 0;
+ int i;
+
+ get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */
+
+ /* Align the table to be 16 byte aligned. */
+ addr += 15;
+ addr &= ~15;
+
+ /* This table must be betweeen 0xf0000 & 0x100000 */
+ printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
+
+ pirq = (void *)(addr);
+ v = (u8 *) (addr);
+
+ pirq->signature = PIRQ_SIGNATURE;
+ pirq->version = PIRQ_VERSION;
+
+ pirq->rtr_bus = bus_sb800[0];
+ pirq->rtr_devfn = ((sbdn_sb800 + 0x14) << 3) | 4;
+
+ pirq->exclusive_irqs = 0;
+
+ pirq->rtr_vendor = 0x1002;
+ pirq->rtr_device = 0x4384;
+
+ pirq->miniport_data = 0;
+
+ memset(pirq->rfu, 0, sizeof(pirq->rfu));
+
+ pirq_info = (void *)(&pirq->checksum + 1);
+ slot_num = 0;
+
+ /* pci bridge */
+ write_pirq_info(pirq_info, bus_sb800[0], ((sbdn_sb800 + 0x14) << 3) | 4,
+ 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
+ 0);
+ pirq_info++;
+
+ slot_num++;
+
+ pirq->size = 32 + 16 * slot_num;
+
+ for (i = 0; i < pirq->size; i++)
+ sum += v[i];
+
+ sum = pirq->checksum - sum;
+
+ if (sum != pirq->checksum) {
+ pirq->checksum = sum;
+ }
+
+ printk(BIOS_INFO, "write_pirq_routing_table done.\n");
+
+ return (unsigned long)pirq_info;
+}
diff --git a/src/mainboard/amd/parmer/mainboard.c b/src/mainboard/amd/parmer/mainboard.c
new file mode 100644
index 0000000..b16be36
--- /dev/null
+++ b/src/mainboard/amd/parmer/mainboard.c
@@ -0,0 +1,70 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <boot/tables.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <device/pci_def.h>
+#include <arch/acpi.h>
+#include "BiosCallOuts.h"
+#include <cpu/amd/agesa/s3_resume.h>
+#include "chip.h"
+#include "agesawrapper.h"
+
+/*************************************************
+ * enable the dedicated function in parmer board.
+ *************************************************/
+static void parmer_enable(device_t dev)
+{
+ printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
+ /*
+ * The mainboard is the first place that we get control in ramstage. Check
+ * for S3 resume and call the approriate AGESA/CIMx resume functions.
+ */
+#if CONFIG_HAVE_ACPI_RESUME == 1
+ acpi_slp_type = acpi_get_sleep_type();
+ if (acpi_slp_type == 3)
+ agesawrapper_fchs3earlyrestore();
+
+#endif
+ setup_uma_memory();
+}
+
+int add_mainboard_resources(struct lb_memory *mem)
+{
+ /* UMA is removed from system memory in the northbridge code, but
+ * in some circumstances we want the memory mentioned as reserved.
+ */
+ /* TODO: Check out why it is commented. */
+#if 0 /* (CONFIG_GFXUMA == 1) */
+ printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n",
+ uma_memory_base, uma_memory_size);
+ lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base,
+ uma_memory_size);
+#endif
+ return 0;
+}
+struct chip_operations mainboard_ops = {
+ CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard")
+ .enable_dev = parmer_enable,
+};
diff --git a/src/mainboard/amd/parmer/mptable.c b/src/mainboard/amd/parmer/mptable.c
new file mode 100644
index 0000000..143920e
--- /dev/null
+++ b/src/mainboard/amd/parmer/mptable.c
@@ -0,0 +1,212 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <arch/smp/mpspec.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <string.h>
+#include <stdint.h>
+#include <cpu/amd/amdfam15.h>
+#include "pmio.h"
+#include <arch/cpu.h>
+#include <cpu/x86/lapic.h>
+
+//-#define IO_APIC_ID CONFIG_MAX_PHYSICAL_CPUS + 1
+#define IO_APIC_ID CONFIG_MAX_CPUS
+extern u8 bus_sb800[3];
+
+extern u32 bus_type[256];
+extern u32 sbdn_sb800;
+extern u32 apicid_sb800;
+
+u8 picr_data[0x54] = {
+ 0x1F,0x1f,0x1f,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
+ 0x09,0x1F,0x1F,0x0B,0x1F,0x0B,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x1F,0x1F,0x1F,0x1F
+};
+u8 intr_data[0x54] = {
+ 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
+ 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x10,0x11,0x12,0x13
+};
+
+static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length)
+{
+ mc->mpc_length += length;
+ mc->mpc_entry_count++;
+}
+
+static void my_smp_write_bus(struct mp_config_table *mc,
+ unsigned char id, const char *bustype)
+{
+ struct mpc_config_bus *mpc;
+ mpc = smp_next_mpc_entry(mc);
+ memset(mpc, '\0', sizeof(*mpc));
+ mpc->mpc_type = MP_BUS;
+ mpc->mpc_busid = id;
+ memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
+ smp_add_mpc_entry(mc, sizeof(*mpc));
+}
+
+static void *smp_write_config_table(void *v)
+{
+ struct mp_config_table *mc;
+ int bus_isa;
+ int boot_apic_id;
+ unsigned apic_version;
+ unsigned cpu_features;
+ unsigned cpu_feature_flags;
+ struct cpuid_result result;
+ unsigned long cpu_flag;
+ u32 dword;
+ u8 byte;
+
+ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+
+ mptable_init(mc, LOCAL_APIC_ADDR);
+ memcpy(mc->mpc_oem, "AMD ", 8);
+
+ smp_write_processors(mc);
+
+ get_bus_conf();
+
+ //mptable_write_buses(mc, NULL, &bus_isa);
+ my_smp_write_bus(mc, 0, "PCI ");
+ my_smp_write_bus(mc, 1, "PCI ");
+ bus_isa = 0x02;
+ my_smp_write_bus(mc, bus_isa, "ISA ");
+
+ /* I/O APICs: APIC ID Version State Address */
+
+ dword = 0;
+ dword = pm_ioread(0x34) & 0xF0;
+ dword |= (pm_ioread(0x35) & 0xFF) << 8;
+ dword |= (pm_ioread(0x36) & 0xFF) << 16;
+ dword |= (pm_ioread(0x37) & 0xFF) << 24;
+ /* Set IO APIC ID onto IO_APIC_ID */
+ write32 (dword, 0x00);
+ write32 (dword + 0x10, IO_APIC_ID << 24);
+ apicid_sb800 = IO_APIC_ID;
+ smp_write_ioapic(mc, apicid_sb800, 0x21, dword);
+
+ /* PIC IRQ routine */
+ for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
+ outb(byte, 0xC00);
+ outb(picr_data[byte], 0xC01);
+ }
+
+ /* APIC IRQ routine */
+ for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
+ outb(byte | 0x80, 0xC00);
+ outb(intr_data[byte], 0xC01);
+ }
+
+ /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
+#define IO_LOCAL_INT(type, intr, apicid, pin) \
+ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
+ mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0);
+
+ /* PCI interrupts are level triggered, and are
+ * associated with a specific bus/device/function tuple.
+ */
+#define PCI_INT(bus, dev, int_sign, pin) \
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_sb800, (pin))
+
+ /* Internal VGA */
+ PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
+ PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
+
+ /* SMBUS */
+ PCI_INT(0x0, 0x14, 0x0, 0x10);
+
+ /* HD Audio */
+ PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]);
+
+ /* USB */
+ PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]);
+ PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
+ PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
+ PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
+ PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
+ PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
+ PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]);
+
+ /* sata */
+ PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]);
+ PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
+
+ /* on board NIC & Slot PCIE. */
+
+ /* PCI slots */
+ /* PCI_SLOT 0. */
+ PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14);
+ PCI_INT(bus_sb800[1], 0x5, 0x1, 0x15);
+ PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16);
+ PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17);
+
+ /* PCI_SLOT 1. */
+ PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15);
+ PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16);
+ PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17);
+ PCI_INT(bus_sb800[1], 0x6, 0x3, 0x14);
+
+ /* PCI_SLOT 2. */
+ PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16);
+ PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17);
+ PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14);
+ PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15);
+
+ PCI_INT(bus_sb800[2], 0x0, 0x0, 0x12);
+ PCI_INT(bus_sb800[2], 0x0, 0x1, 0x13);
+ PCI_INT(bus_sb800[2], 0x0, 0x2, 0x14);
+
+ /* PCIe Lan*/
+ PCI_INT(0x0, 0x06, 0x0, 0x13);
+
+ /* FCH PCIe PortA */
+ PCI_INT(0x0, 0x15, 0x0, 0x10);
+ /* FCH PCIe PortB */
+ PCI_INT(0x0, 0x15, 0x1, 0x11);
+ /* FCH PCIe PortC */
+ PCI_INT(0x0, 0x15, 0x2, 0x12);
+ /* FCH PCIe PortD */
+ PCI_INT(0x0, 0x15, 0x3, 0x13);
+
+ /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
+ IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
+ IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
+ /* There is no extension information... */
+
+ /* Compute the checksums */
+ return mptable_finalize(mc);
+}
+
+unsigned long write_smp_table(unsigned long addr)
+{
+ void *v;
+ v = smp_write_floating_table(addr, 0);
+ return (unsigned long)smp_write_config_table(v);
+}
diff --git a/src/mainboard/amd/parmer/pmio.c b/src/mainboard/amd/parmer/pmio.c
new file mode 100644
index 0000000..a8f1d3d
--- /dev/null
+++ b/src/mainboard/amd/parmer/pmio.c
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h> /*inb, outb*/
+#include "pmio.h"
+
+static void pmio_write_index(u16 port_base, u8 reg, u8 value)
+{
+ outb(reg, port_base);
+ outb(value, port_base + 1);
+}
+
+static u8 pmio_read_index(u16 port_base, u8 reg)
+{
+ outb(reg, port_base);
+ return inb(port_base + 1);
+}
+
+void pm_iowrite(u8 reg, u8 value)
+{
+ pmio_write_index(PM_INDEX, reg, value);
+}
+
+u8 pm_ioread(u8 reg)
+{
+ return pmio_read_index(PM_INDEX, reg);
+}
+
+void pm2_iowrite(u8 reg, u8 value)
+{
+ pmio_write_index(PM2_INDEX, reg, value);
+}
+
+u8 pm2_ioread(u8 reg)
+{
+ return pmio_read_index(PM2_INDEX, reg);
+}
diff --git a/src/mainboard/amd/parmer/pmio.h b/src/mainboard/amd/parmer/pmio.h
new file mode 100644
index 0000000..bc15fd9
--- /dev/null
+++ b/src/mainboard/amd/parmer/pmio.h
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _PMIO_H_
+#define _PMIO_H_
+
+#define PM_INDEX 0xCD6
+#define PM_DATA 0xCD7
+#define PM2_INDEX 0xCD0
+#define PM2_DATA 0xCD1
+
+void pm_iowrite(u8 reg, u8 value);
+u8 pm_ioread(u8 reg);
+void pm2_iowrite(u8 reg, u8 value);
+u8 pm2_ioread(u8 reg);
+
+#endif
diff --git a/src/mainboard/amd/parmer/reset.c b/src/mainboard/amd/parmer/reset.c
new file mode 100644
index 0000000..5735fa2
--- /dev/null
+++ b/src/mainboard/amd/parmer/reset.c
@@ -0,0 +1,64 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <reset.h>
+#include <arch/io.h> /*inb, outb*/
+#include <arch/romcc_io.h> /*pci_read_config32, device_t, PCI_DEV*/
+
+#define HT_INIT_CONTROL 0x6C
+#define HTIC_BIOSR_Detect (1<<5)
+
+#if CONFIG_MAX_PHYSICAL_CPUS > 32
+#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn)))
+#else
+#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)
+#endif
+
+static inline void set_bios_reset(void)
+{
+ u32 nodes;
+ u32 htic;
+ device_t dev;
+ int i;
+
+ nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1;
+ for(i = 0; i < nodes; i++) {
+ dev = NODE_PCI(i, 0);
+ htic = pci_read_config32(dev, HT_INIT_CONTROL);
+ htic &= ~HTIC_BIOSR_Detect;
+ pci_write_config32(dev, HT_INIT_CONTROL, htic);
+ }
+}
+
+void hard_reset(void)
+{
+ set_bios_reset();
+ /* Try rebooting through port 0xcf9 */
+ /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */
+ outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9);
+ outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9);
+}
+
+//SbReset();
+void soft_reset(void)
+{
+ set_bios_reset();
+ /* link reset */
+ outb(0x06, 0x0cf9);
+}
diff --git a/src/mainboard/amd/parmer/romstage.c b/src/mainboard/amd/parmer/romstage.c
new file mode 100644
index 0000000..028d6ae
--- /dev/null
+++ b/src/mainboard/amd/parmer/romstage.c
@@ -0,0 +1,162 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <arch/io.h>
+#include <arch/stages.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <arch/cpu.h>
+#include <cpu/x86/lapic.h>
+#include <cpu/x86/cache.h>
+#include <console/console.h>
+#include <console/loglevel.h>
+#include "agesawrapper.h"
+#include "cpu/x86/bist.h"
+#include "cpu/x86/lapic/boot_cpu.c"
+#include "southbridge/amd/agesa/hudson/hudson.h"
+#include "cpu/amd/agesa/s3_resume.h"
+#include "src/drivers/pc80/i8254.c"
+#include "src/drivers/pc80/i8259.c"
+#include "cbmem.h"
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
+void disable_cache_as_ram(void);
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+ u32 val;
+#if CONFIG_HAVE_ACPI_RESUME == 1
+ void *resume_backup_memory;
+#endif
+ val = agesawrapper_amdinitmmio();
+
+ hudson_lpc_port80();
+
+ if (!cpu_init_detectedx && boot_cpu()) {
+ post_code(0x30);
+
+ post_code(0x31);
+ console_init();
+ }
+
+ /* Halt if there was a built in self test failure */
+ post_code(0x34);
+ report_bist_failure(bist);
+
+ /* Load MPB */
+ val = cpuid_eax(1);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
+
+ post_code(0x37);
+ val = agesawrapper_amdinitreset();
+ if(val) {
+ printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val);
+ }
+
+ post_code(0x38);
+ printk(BIOS_DEBUG, "Got past sb800_early_setup\n");
+
+ post_code(0x39);
+
+ val = agesawrapper_amdinitearly ();
+ if(val) {
+ printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val);
+ }
+ printk(BIOS_DEBUG, "Got past agesawrapper_amdinitearly\n");
+
+#if CONFIG_HAVE_ACPI_RESUME
+ if (!acpi_is_wakeup_early()) { /* Check for S3 resume */
+#endif
+ post_code(0x40);
+ val = agesawrapper_amdinitpost ();
+ if(val) {
+ printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val);
+ }
+ printk(BIOS_DEBUG, "Got past agesawrapper_amdinitpost\n");
+
+ post_code(0x41);
+ val = agesawrapper_amdinitenv ();
+ if(val) {
+ printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", val);
+ }
+ printk(BIOS_DEBUG, "Got past agesawrapper_amdinitenv\n");
+ disable_cache_as_ram();
+ enable_cache();
+#if CONFIG_HAVE_ACPI_RESUME
+ } else { /* S3 detect */
+ printk(BIOS_INFO, "S3 detected\n");
+
+ post_code(0x60);
+ printk(BIOS_DEBUG, "agesawrapper_amdinitresume ");
+ val = agesawrapper_amdinitresume();
+ if (val)
+ printk(BIOS_DEBUG, "error level: %x \n", val);
+ else
+ printk(BIOS_DEBUG, "passed.\n");
+
+ printk(BIOS_DEBUG, "agesawrapper_amds3laterestore ");
+ val = agesawrapper_amds3laterestore ();
+ if (val)
+ printk(BIOS_DEBUG, "error level: %x \n", val);
+ else
+ printk(BIOS_DEBUG, "passed.\n");
+
+ post_code(0x61);
+ printk(BIOS_DEBUG, "Find resume memory location\n");
+ resume_backup_memory = (void *)backup_resume();
+
+ post_code(0x62);
+ printk(BIOS_DEBUG, "Move CAR stack.\n");
+ move_stack_high_mem();
+ printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE));
+
+ post_code(0x63);
+ disable_cache_as_ram();
+ printk(BIOS_DEBUG, "CAR disabled.\n");
+ set_resume_cache();
+
+ /*
+ * Copy the system memory that is in the ramstage area to the
+ * reserved area.
+ */
+ if (resume_backup_memory)
+ memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE);
+
+ printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n");
+ }
+#endif
+
+ /* Initialize i8259 pic */
+ post_code(0x41);
+ setup_i8259 ();
+
+ /* Initialize i8254 timers */
+ post_code(0x42);
+ setup_i8254 ();
+
+ post_code(0x50);
+ copy_and_run(0);
+
+ post_code(0x54); /* Should never see this post code. */
+}
1
0
Patch merged into coreboot/master: f17a005 Intel SCH northbridge: fix resource index
by gerrit＠coreboot.org 19 Jul '12
by gerrit＠coreboot.org 19 Jul '12
19 Jul '12
the following patch was just integrated into master:
commit f17a005cbca5878154f986d7b95fcc146968a93e
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Wed Jul 18 10:05:01 2012 +0300
Intel SCH northbridge: fix resource index
Change-Id: If131ac9df89080faccd8ed952d6fc019483b5b2e
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Build-Tested: build bot (Jenkins) at Wed Jul 18 15:28:26 2012, giving +1
Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Fri Jul 20 01:53:04 2012, giving +2
See http://review.coreboot.org/1237 for details.
-gerrit
1
0
New patch to review for coreboot: 664126b AMD CPUs: Updated CPU list in powernow_acpi.c
by Jukka Rantala 19 Jul '12
by Jukka Rantala 19 Jul '12
19 Jul '12
Jukka Rantala (jukka.rantala(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1244
-gerrit
commit 664126bafe7da55c2279db4b674dbabeab4a8359
Author: Jukka Rantala <jukka.rantala(a)gmail.com>
Date: Fri Jul 20 02:10:16 2012 +0300
AMD CPUs: Updated CPU list in powernow_acpi.c
Updated P state table to make frequency scaling work.
Added these CPUs: http://support.amd.com/us/Processor_TechDocs/30430.pdf
Also wrote a Python script for parsing AMD docs,
but not sure where to put it: http://pastebin.com/1dSvkXwc
Change-Id: I8f08111b73b9be551f3f59d2acb15051ccf36c1e
Signed-off-by: Jukka Rantala <jukka.rantala(a)gmail.com>
---
src/cpu/amd/model_fxx/powernow_acpi.c | 182 +++++++++++++++++++++++++++++++--
1 files changed, 174 insertions(+), 8 deletions(-)
diff --git a/src/cpu/amd/model_fxx/powernow_acpi.c b/src/cpu/amd/model_fxx/powernow_acpi.c
index 81b1067..dec790c 100644
--- a/src/cpu/amd/model_fxx/powernow_acpi.c
+++ b/src/cpu/amd/model_fxx/powernow_acpi.c
@@ -561,23 +561,189 @@ struct cpuentry entr[] = {
{180, 0x2c, 0x20f32, 0x10, 0x10, 1100,
{{2200, 1300, 1056}, {2000, 1250, 891},
{1800, 1200, 748}, {1000, 1100, 466}}},
- {3000, 0x4, 0x10ff0, 0xa, 0xa, 670,
- {{1000, 1100, 210}}},
/* AMA3000BEX5AR */
{3000, 0x4, 0xf4a, 0xa, 0x0, 815,
{{1600, 1400, 570}, {800, 1100, 190}}},
/* TMDML34BKX5LD, needs real TDP info */
{34, 0xa, 0x20f42, 0xa, 0x0, 350,
{{1600, 1400, 340}, {800, 1000, 330}}},
- /* SDA3100AIO3BX */
- {3100, 0x26, 0x20fc2, 0xa, 0xa, 590,
- {{1000, 1100, 217}}},
- /* SDA3400AIO3BX */
- {3400, 0x26, 0x20fc2, 0xc, 0xc, 590,
- {{1800, 1350, 496}, {1000, 1100, 207}}},
/* ADA3200AIO4BX */
{3200, 0x4, 0x20fc2, 0xe, 0xe, 670,
{{2000, 1350, 647}, {1800, 1300, 548}, {1000, 1100, 275}}},
+ /* ADA2800AEP4AP */
+ {2800, 0x4, 0xf48, 0xa, 0xa, 890,
+ {{800, 1300, 350}}},
+ /* ADA3000AEP4AP */
+ {3000, 0x4, 0xf48, 0xc, 0xc, 890,
+ {{1800, 1400, 660}, {800, 1300, 350}}},
+ /* ADA3200AEP5AP */
+ {3200, 0x4, 0xf48, 0xc, 0xc, 890,
+ {{1800, 1400, 660}, {800, 1300, 350}}},
+ /* ADA3400AEP5AP */
+ {3400, 0x4, 0xf48, 0xe, 0xe, 890,
+ {{2000, 1400, 700}, {800, 1300, 350}}},
+ /* ADA2800AEP4AR */
+ {2800, 0x4, 0xf4a, 0xa, 0xa, 890,
+ {{1000, 1100, 220}}},
+ /* ADA3000AEP4AR */
+ {3000, 0x4, 0xf4a, 0xc, 0xc, 890,
+ {{1800, 1400, 660}, {1000, 1100, 220}}},
+ /* ADA3700AEP5AR */
+ {3700, 0x4, 0xf4a, 0x10, 0x10, 890,
+ {{2200, 1400, 720}, {2000, 1300, 530}, {1800, 1200, 390}, {1000, 1100, 220}}},
+ /* ADA2800AEP4AX */
+ {2800, 0x4, 0xfc0, 0xa, 0xa, 890,
+ {{1000, 1100, 220}}},
+ /* ADA3000AEP4AX */
+ {3000, 0x4, 0xfc0, 0xc, 0xc, 890,
+ {{1800, 1400, 670}, {1000, 1100, 220}}},
+ /* ADA3200AEP4AX */
+ {3200, 0x4, 0xfc0, 0xe, 0xe, 890,
+ {{2000, 1400, 690}, {1800, 1300, 500}, {1000, 1100, 220}}},
+ /* ADA3400AEP4AX */
+ {3400, 0x4, 0xfc0, 0x10, 0x10, 890,
+ {{2200, 1400, 720}, {2000, 1300, 530}, {1800, 1200, 390}, {1000, 1100, 220}}},
+ /* ADA3500DEP4AS */
+ {3500, 0x4, 0xf7a, 0xe, 0xe, 890,
+ {{2000, 1400, 690}, {1800, 1300, 500}, {1000, 1100, 220}}},
+ /* ADA3500DEP4AW */
+ {3500, 0x4, 0xff0, 0xe, 0xe, 890,
+ {{2000, 1400, 690}, {1800, 1300, 500}, {1000, 1100, 220}}},
+ /* ADA3800DEP4AW */
+ {3800, 0x4, 0xff0, 0x10, 0x10, 890,
+ {{2200, 1400, 720}, {2000, 1300, 530}, {1800, 1200, 390}, {1000, 1100, 220}}},
+ /* ADA4000DEP5AS */
+ {4000, 0x4, 0xf7a, 0x10, 0x10, 890,
+ {{2200, 1400, 720}, {2000, 1300, 530}, {1800, 1200, 390}, {1000, 1100, 220}}},
+ /* ADA3500DAA4BN */
+ {3500, 0x4, 0x20f71, 0xe, 0xe, 670,
+ {{2000, 1350, 647}, {1800, 1300, 548}, {1000, 1100, 275}}},
+ /* ADA3700DAA5BN */
+ {3700, 0x4, 0x20f71, 0xe, 0xe, 853,
+ {{2000, 1350, 830}, {1800, 1300, 704}, {1000, 1100, 361}}},
+ /* ADA4000DAA5BN */
+ {4000, 0x4, 0x20f71, 0x10, 0x10, 853,
+ {{2200, 1350, 830}, {2000, 1300, 706}, {1800, 1250, 596}, {1000, 1100, 350}}},
+ /* ADA3700DKA5CF */
+ {3700, 0x4, 0x30f72, 0xe, 0xe, 853,
+ {{2000, 1350, 830}, {1800, 1300, 704}, {1000, 1100, 361}}},
+ /* ADA4000DKA5CF */
+ {4000, 0x4, 0x30f72, 0x10, 0x10, 853,
+ {{2200, 1350, 830}, {2000, 1300, 706}, {1800, 1250, 596}, {1000, 1100, 350}}},
+ /* ADA3800DAA4BP */
+ {3800, 0x4, 0x20ff0, 0x10, 0x10, 853,
+ {{2200, 1350, 830}, {2000, 1300, 706}, {1800, 1250, 596}, {1000, 1100, 350}}},
+ /* ADA3000DIK4BI */
+ {3000, 0x4, 0x10ff0, 0xa, 0xa, 670,
+ {{1000, 1100, 210}}},
+ /* ADA3200DIK4BI */
+ {3200, 0x4, 0x10ff0, 0xc, 0xc, 670,
+ {{1800, 1350, 560}, {1000, 1100, 210}}},
+ /* ADA3500DIK4BI */
+ {3500, 0x4, 0x10ff0, 0xe, 0xe, 670,
+ {{2000, 1350, 560}, {1800, 1300, 460}, {1000, 1100, 200}}},
+ /* ADA3000DAA4BP */
+ {3000, 0x4, 0x20ff0, 0xa, 0xa, 670,
+ {{1000, 1100, 296}}},
+ /* ADA3200DAA4BP */
+ {3200, 0x4, 0x20ff0, 0xc, 0xc, 670,
+ {{1800, 1350, 647}, {1000, 1100, 286}}},
+ /* ADA3500DAA4BP */
+ {3500, 0x4, 0x20ff0, 0xe, 0xe, 670,
+ {{2000, 1350, 647}, {1800, 1300, 548}, {1000, 1100, 275}}},
+ /* ADA3000DAA4BW */
+ {3000, 0x4, 0x20ff2, 0xa, 0xa, 670,
+ {{1000, 1100, 296}}},
+ /* ADA3200DAA4BW */
+ {3200, 0x4, 0x20ff2, 0xc, 0xc, 670,
+ {{1800, 1350, 647}, {1000, 1100, 286}}},
+ /* ADA3500DAA4BW */
+ {3500, 0x4, 0x20ff2, 0xe, 0xe, 670,
+ {{2000, 1350, 647}, {1800, 1300, 548}, {1000, 1100, 275}}},
+ /* ADA3200DKA4CG */
+ {3200, 0x4, 0x30ff2, 0xc, 0xc, 670,
+ {{1800, 1350, 647}, {1000, 1100, 286}}},
+ /* ADA3800DAA4BW */
+ {3800, 0x4, 0x20ff2, 0x10, 0x10, 853,
+ {{2200, 1350, 830}, {2000, 1300, 706}, {1800, 1250, 596}, {1000, 1100, 350}}},
+ /* ADA3000AIK4BX */
+ {3000, 0x4, 0x20fc2, 0xc, 0xc, 510,
+ {{1800, 1350, 428}, {1000, 1100, 189}}},
+ /* ADAFX53DEP5AS */
+ {53, 0x24, 0xf7a, 0x2a, 0x10, 890,
+ {{1200, 1100, 250}}},
+ /* ADAFX55DEI5AS */
+ {55, 0x24, 0xf7a, 0x2a, 0x12, 1040,
+ {{1200, 1100, 250}}},
+ /* ADAFX55DAA5BN */
+ {55, 0x24, 0x20f71, 0x2a, 0x12, 1040,
+ {{1200, 1100, 422}}},
+ /* ADAFX57DAA5BN */
+ {57, 0x24, 0x20f71, 0x2a, 0x14, 1040,
+ {{1200, 1100, 434}}},
+ /* SDA3100AIP3AX */
+ {3100, 0x22, 0xfc0, 0xa, 0xa, 620,
+ {{1000, 1100, 200}}},
+ /* SDA2600AIO2BA */
+ {2600, 0x22, 0x10fc0, 0x8, 0x8, 590,
+ {}},
+ /* SDA2800AIO3BA */
+ {2800, 0x22, 0x10fc0, 0x8, 0x8, 590,
+ {}},
+ /* SDA3000AIO2BA */
+ {3000, 0x22, 0x10fc0, 0xa, 0xa, 590,
+ {{1000, 1100, 190}}},
+ /* SDA3100AIO3BA */
+ {3100, 0x22, 0x10fc0, 0xa, 0xa, 590,
+ {{1000, 1100, 190}}},
+ /* SDA3300AIO2BA */
+ {3300, 0x22, 0x10fc0, 0xc, 0xc, 590,
+ {{1800, 1350, 488}, {1000, 1100, 180}}},
+ /* SDA2500AIO3BX */
+ {2500, 0x26, 0x20fc2, 0x6, 0x6, 590,
+ {}},
+ /* SDA2600AIO2BX */
+ {2600, 0x26, 0x20fc2, 0x8, 0x8, 590,
+ {}},
+ /* SDA2800AIO3BX */
+ {2800, 0x26, 0x20fc2, 0x8, 0x8, 590,
+ {}},
+ /* SDA3000AIO2BX */
+ {3000, 0x26, 0x20fc2, 0xa, 0xa, 590,
+ {{1000, 1100, 217}}},
+ /* SDA3100AIO3BX */
+ {3100, 0x26, 0x20fc2, 0xa, 0xa, 590,
+ {{1000, 1100, 217}}},
+ /* SDA3300AIO2BX */
+ {3300, 0x26, 0x20fc2, 0xc, 0xc, 590,
+ {{1800, 1350, 496}, {1000, 1100, 207}}},
+ /* SDA3400AIO3BX */
+ {3400, 0x26, 0x20fc2, 0xc, 0xc, 590,
+ {{1800, 1350, 496}, {1000, 1100, 207}}},
+ /* TMSMT32BQX4LD */
+ {32, 0xb, 0x20f42, 0xa, 0x0, 240,
+ {{1600, 1150, 199}, {800, 900, 77}}},
+ /* TMSMT34BQX5LD */
+ {34, 0xb, 0x20f42, 0xa, 0x0, 240,
+ {{1600, 1150, 199}, {800, 900, 79}}},
+ /* TMSMT37BQX5LD */
+ {37, 0xb, 0x20f42, 0xc, 0x0, 250,
+ {{1800, 1150, 209}, {1600, 1100, 175}, {800, 900, 79}}},
+ /* ADA4400DAA6CD */
+ {4400, 0x5, 0x20f32, 0xe, 0xe, 1100,
+ {{2000, 1300, 1056}, {1800, 1250, 891}, {1000, 1100, 490}}},
+ /* ADA4800DAA6CD */
+ {4800, 0x5, 0x20f32, 0x10, 0x10, 1100,
+ {{2200, 1300, 1056}, {2000, 1250, 891}, {1800, 1200, 748}, {1000, 1100, 466}}},
+ /* ADA3800DAA5BV */
+ {3800, 0x5, 0x20fb1, 0xc, 0xc, 890,
+ {{1800, 1300, 846}, {1000, 1100, 401}}},
+ /* ADA4200DAA5BV */
+ {4200, 0x5, 0x20fb1, 0xe, 0xe, 890,
+ {{2000, 1300, 846}, {1800, 1250, 709}, {1000, 1100, 376}}},
+ /* ADA4600DAA5BV */
+ {4600, 0x5, 0x20fb1, 0x10, 0x10, 1100,
+ {{2200, 1300, 1056}, {2000, 1250, 891}, {1800, 1200, 748}, {1000, 1100, 466}}},
};
static int pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
1
0