coreboot July 2012

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639 discussions

New patch to review for coreboot: db5db28 i945: Disable IGD if plugin VGA is preferred
by Patrick Georgi 20 Jul '12

20 Jul '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1252 -gerrit commit db5db2847ffb26c4e8181166498ae6353c65ec9c Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Fri Jul 20 12:37:06 2012 +0200 i945: Disable IGD if plugin VGA is preferred It's shut down, but UMA memory is not reclaimed. A later extension could optionally do the magic register dance that allows initialization of IGD as secondary graphics device. Change-Id: I2a92bb71755005b886a8e1825325c678a9991bf2 Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> --- src/northbridge/intel/i945/gma.c | 18 ++++++++++++++++++ 1 files changed, 18 insertions(+), 0 deletions(-) diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index b703a80..bf381b8 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -23,6 +23,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <pc80/mc146818rtc.h> +#include "i945.h" #define GDRST 0xc0 @@ -44,6 +45,22 @@ static void gma_func0_init(struct device *dev) pci_dev_init(dev); } +/* This doesn't reclaim stolen UMA memory, but IGD could still + be reenabled later. */ +static void gma_func0_disable(struct device *dev) +{ + struct device *dev_host = dev_find_slot(0, PCI_DEVFN(0x0, 0)); + + pci_write_config16(dev, GCFC, 0xa00); + pci_write_config16(dev_host, GGC, (1 << 1)); + + unsigned int reg32 = pci_read_config32(dev_host, DEVEN); + reg32 &= ~(DEVEN_D2F0 | DEVEN_D2F1); + pci_write_config32(dev_host, DEVEN, reg32); + + dev->enabled = 0; +} + static void gma_func1_init(struct device *dev) { u32 reg32; @@ -82,6 +99,7 @@ static struct device_operations gma_func0_ops = { .init = gma_func0_init, .scan_bus = 0, .enable = 0, + .disable = gma_func0_disable, .ops_pci = &gma_pci_ops, };

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New patch to review for coreboot: ce2a44e Allow shutting down internal graphics if plugin graphics are preferred
by Patrick Georgi 20 Jul '12

20 Jul '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1251 -gerrit commit ce2a44e3cbb5766261da8f1893b64e030edd0070 Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Fri Jul 20 12:29:33 2012 +0200 Allow shutting down internal graphics if plugin graphics are preferred VGA is this part-legacy thing that can cause trouble... For this, introduce device_t->disable(dev) method, in which a driver can take care to deregister the device if necessary. Change-Id: I3fecec07f402e530458b79eda30b2c274101fefa Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> --- src/devices/device.c | 8 ++++++++ src/include/device/device.h | 1 + 2 files changed, 9 insertions(+), 0 deletions(-) diff --git a/src/devices/device.c b/src/devices/device.c index d3f9b52..de27e88 100644 --- a/src/devices/device.c +++ b/src/devices/device.c @@ -762,6 +762,14 @@ static void set_vga_bridge_bits(void) vga = vga_onboard; } + /* If we prefer plugin VGA over chipset VGA, the chipset might + want to know. */ + if (!CONFIG_ONBOARD_VGA_IS_PRIMARY && (vga != vga_onboard) && + vga_onboard && vga_onboard->ops && vga_onboard->ops->disable) { + printk(BIOS_DEBUG, "Use plugin graphics over integrated.\n"); + vga_onboard->ops->disable(vga_onboard); + } + if (vga) { /* VGA is first add-on card or the only onboard VGA. */ printk(BIOS_DEBUG, "Setting up VGA for %s\n", dev_path(vga)); diff --git a/src/include/device/device.h b/src/include/device/device.h index 819b789..8cc937f 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -32,6 +32,7 @@ struct device_operations { void (*init)(device_t dev); unsigned int (*scan_bus)(device_t bus, unsigned int max); void (*enable)(device_t dev); + void (*disable)(device_t dev); void (*set_link)(device_t dev, unsigned int link); void (*reset_bus)(struct bus *bus); #if CONFIG_GENERATE_SMBIOS_TABLES

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New patch to review for coreboot: 05ca672 Drop VGA_BRIDGE_SETUP config option
by Patrick Georgi 20 Jul '12

20 Jul '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1250 -gerrit commit 05ca672a0521ce81886e1bd4bfecfc81970507e6 Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Fri Jul 20 11:55:19 2012 +0200 Drop VGA_BRIDGE_SETUP config option It defaults to true, and isn't disabled anywhere in the tree. I also couldn't think of a case where it's actually useful. Change-Id: I126a47625d5294f3cfff225629f2a948a83c9b7e Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> --- src/devices/Kconfig | 7 ------- src/devices/device.c | 5 ----- src/northbridge/amd/gx2/Kconfig | 2 +- 3 files changed, 1 insertions(+), 13 deletions(-) diff --git a/src/devices/Kconfig b/src/devices/Kconfig index 5168819..cec2048 100644 --- a/src/devices/Kconfig +++ b/src/devices/Kconfig @@ -18,13 +18,6 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -config VGA_BRIDGE_SETUP - bool "Setup bridges on path to VGA adapter" - default y - help - Allow bridges to set up legacy decoding ranges for VGA. Don't disable - this unless you're sure you don't want the briges setup for VGA. - # TODO: Explain differences (if any) for onboard cards. config VGA_ROM_RUN bool "Run VGA Option ROMs" diff --git a/src/devices/device.c b/src/devices/device.c index c378078..d3f9b52 100644 --- a/src/devices/device.c +++ b/src/devices/device.c @@ -705,7 +705,6 @@ static void avoid_fixed_resources(struct device *dev) } } -#if CONFIG_VGA_BRIDGE_SETUP device_t vga_pri = 0; static void set_vga_bridge_bits(void) { @@ -781,8 +780,6 @@ static void set_vga_bridge_bits(void) } } -#endif - /** * Assign the computed resources to the devices on the bus. * @@ -964,9 +961,7 @@ void dev_configure(void) struct device *root; struct device *child; -#if CONFIG_VGA_BRIDGE_SETUP set_vga_bridge_bits(); -#endif printk(BIOS_INFO, "Allocating resources...\n"); diff --git a/src/northbridge/amd/gx2/Kconfig b/src/northbridge/amd/gx2/Kconfig index ae532bd..5140409 100644 --- a/src/northbridge/amd/gx2/Kconfig +++ b/src/northbridge/amd/gx2/Kconfig @@ -24,7 +24,7 @@ config NORTHBRIDGE_AMD_GX2 choice prompt "Framebuffer size" default GX2_VIDEO_MB_8MB - depends on NORTHBRIDGE_AMD_GX2 && VGA_BRIDGE_SETUP + depends on NORTHBRIDGE_AMD_GX2 config GX2_VIDEO_MB_4MB bool "4MB"

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New patch to review for coreboot: 3bb096d Allow YABEL to fake write accesses to config space
by Patrick Georgi 20 Jul '12

20 Jul '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1249 -gerrit commit 3bb096d434e40819c882e841efc93c4b5d68f20a Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Fri Jul 20 13:44:50 2012 +0200 Allow YABEL to fake write accesses to config space A new Kconfig option tells YABEL to succeed on write accesses on other devices' config space without performing the actual write. This is enough for some basic bus modification done by some Option ROMs. Change-Id: Iab04f3a5c350b96654da4ba26858037f4c4b5c0a Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> --- src/devices/Kconfig | 12 ++++++++++++ src/devices/oprom/yabel/io.c | 2 ++ 2 files changed, 14 insertions(+), 0 deletions(-) diff --git a/src/devices/Kconfig b/src/devices/Kconfig index 5168819..87be8c0 100644 --- a/src/devices/Kconfig +++ b/src/devices/Kconfig @@ -105,6 +105,18 @@ config YABEL_PCI_ACCESS_OTHER_DEVICES onboard graphics chips whose Option ROM needs to reconfigure the north bridge. +config YABEL_PCI_FAKE_WRITING_OTHER_DEVICES_CONFIG + prompt "Fake success on writing other device's config space" + bool + depends on YABEL_PCI_ACCESS_OTHER_DEVICES + help + By default, YABEL aborts when the Option ROM tries to write to other + devices' config spaces. With this option enabled, the write doesn't + follow through, but the Option ROM is allowed to go on. + This can create issues such as hanging Option ROMs (if it depends on + that other register changing to the written value), so test for + impact before using this option. + config YABEL_VIRTMEM_LOCATION prompt "Location of YABEL's virtual memory" hex diff --git a/src/devices/oprom/yabel/io.c b/src/devices/oprom/yabel/io.c index 00bb1a0..5c19b51 100644 --- a/src/devices/oprom/yabel/io.c +++ b/src/devices/oprom/yabel/io.c @@ -524,7 +524,9 @@ pci_cfg_write(X86EMU_pioAddr addr, u32 val, u8 size) printf ("Config write access invalid! PCI device %x:%x.%x, offs: %x\n", bus, devfn >> 3, devfn & 7, offs); +#if !CONFIG_YABEL_PCI_FAKE_WRITING_OTHER_DEVICES_CONFIG HALT_SYS(); +#endif } else { #if CONFIG_PCI_OPTION_ROM_RUN_YABEL switch (size) {

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Re: [coreboot] [libpayload] EHCI USB driver transaction error
by Антон Кочков 20 Jul '12

20 Jul '12

Problem solved - was error in memory align - so, EHCI go to NULL pointer, which cause PCI error. Best regards, Anton Kochkov. On Fri, Jul 20, 2012 at 12:22 PM, Антон Кочков <anton.kochkov(a)gmail.com>wrote: > Sorry, valid mainboard name - Foxconn H61MXV > http://www.foxconnchannel.com/ProductDetail.aspx?T=motherboard&U=en-us00005… > > Best regards, > Anton Kochkov. > > > > > On Fri, Jul 20, 2012 at 12:10 PM, Антон Кочков <anton.kochkov(a)gmail.com>wrote: > >> Good day (or any other time)! >> While working with/on libpayload for EHCI USB driver, i've found strange >> error, when device is found (port status = 0x1803) >> and sending first control transaction. >> (usb_attach_device/get_free_address). >> Mainboard - Foxconn N15235 >> >> wait_for_tds(): ERROR with packet >> ========= EHCI TD at [0x0004d000] ========= >> __EHCI_TD cerr: 0, total_len: 8 >> __EHCI_TD: next_qtd [0x0004d120] >> __EHCI_TD: alt_next_qtd [0x00000001] >> __EHCI_TD: token [0x00080248] >> __EHCI_TD: Bytes to Transfer [8] >> __EHCI_TD: PID CODE: [2] >> __EHCI_TD: Interrupt On Complete (IOC) [0] >> __EHCI_TD: Status Active [0] >> __EHCI_TD: Status Halted [1] >> __EHCI_TD: Status Data Buffer Error [0] >> __EHCI_TD: Status Babble detected [0] >> __EHCI_TD: Status Transaction Error [1] >> __EHCI_TD: Status Missed Micro Frame [0] >> __EHCI_TD: Status Split Transaction State [0] >> __EHCI_TD: Status Ping State [0] >> wait_for_tds(): ----------------- >> >> Attaching full log, where dumping registers/packets on every step. >> Hope someone know the reason. >> >> Best regards, >> Anton Kochkov. >> >> >

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Patch merged into coreboot/master: 999c6c4 sconfig: typo fix
by gerrit＠coreboot.org 20 Jul '12

20 Jul '12

the following patch was just integrated into master: commit 999c6c4141e41032126f932594aede28baa71645 Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Fri Jul 20 12:47:06 2012 +0200 sconfig: typo fix eliminate printf format warning. Change-Id: I51f75a259d28c5de788f57c3d720b76ca638e330 Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> Build-Tested: build bot (Jenkins) at Fri Jul 20 13:07:55 2012, giving +1 Reviewed-By: Peter Stuge <peter(a)stuge.se> at Fri Jul 20 13:11:46 2012, giving +2 See http://review.coreboot.org/1248 for details. -gerrit

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New patch to review for coreboot: 999c6c4 sconfig: typo fix
by Patrick Georgi 20 Jul '12

20 Jul '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1248 -gerrit commit 999c6c4141e41032126f932594aede28baa71645 Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Fri Jul 20 12:47:06 2012 +0200 sconfig: typo fix eliminate printf format warning. Change-Id: I51f75a259d28c5de788f57c3d720b76ca638e330 Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> --- util/sconfig/main.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/util/sconfig/main.c b/util/sconfig/main.c index ca8c3c5..989f747 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -353,7 +353,7 @@ void add_ioapic_info(struct device *dev, int apicid, const char *_srcpin, int ir } if (srcpin > 3) { - printf("ERROR: srcpin '%d' invalid\n"); + printf("ERROR: srcpin '%d' invalid\n", srcpin); exit(1); } dev->pci_irq_info[srcpin].ioapic_irq_pin = irqpin;

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New patch to review for coreboot: e6fe83c AMD Agesa and GFXUMA: drop use of uma_memory_base
by Kyösti Mälkki 20 Jul '12

20 Jul '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1247 -gerrit commit e6fe83cf469724481f35c9ae05bf94a23d5d7ae0 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Jul 20 08:31:37 2012 +0300 AMD Agesa and GFXUMA: drop use of uma_memory_base Without GFXUMA, variables were not referenced anywhere. Fail builds on Family10 if GFXUMA is selected, because the northbridge code does not set UMA base or size. Change-Id: I15b91cf6241e9a890398eed03824b753828a0a51 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/amd/agesa/family10/northbridge.c | 4 ++++ src/northbridge/amd/agesa/family12/northbridge.c | 3 --- src/northbridge/amd/agesa/family14/northbridge.c | 3 --- src/northbridge/amd/agesa/family15/northbridge.c | 3 --- 4 files changed, 4 insertions(+), 9 deletions(-) diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index c4acedf..831aec0 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -923,6 +923,10 @@ static void amdfam10_domain_set_resources(device_t dev) u32 reset_memhole = 1; #endif +#if CONFIG_GFXUMA +#error Northbridge does not set uma_memory_base or uma_memory_size. +#endif + #if CONFIG_PCI_64BIT_PREF_MEM for (link = dev->link_list; link; link = link->next) { diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index d7458ff..7ac8996 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -508,9 +508,6 @@ void setup_uma_memory(void) __func__, uma_memory_size, uma_memory_base); /* TODO: TOP_MEM2 */ -#else - uma_memory_size = 0x10000000; /* 256M recommended UMA */ - uma_memory_base = 0x30000000; /* 1GB system memory supported */ #endif } diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index dbc432a..6cdff27 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -553,9 +553,6 @@ void setup_uma_memory(void) __func__, uma_memory_size, uma_memory_base); /* TODO: TOP_MEM2 */ -#else - uma_memory_size = 0x10000000; /* 256M recommended UMA */ - uma_memory_base = 0x30000000; /* 1GB system memory supported */ #endif } diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index 2036dbf..be86fda 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -668,9 +668,6 @@ void setup_uma_memory(void) __func__, uma_memory_size, uma_memory_base); /* TODO: TOP_MEM2 */ -#else - uma_memory_size = 256 * ONE_MB; /* 256M recommended UMA */ - uma_memory_base = 768 * ONE_MB; /* 1GB system memory supported */ #endif }

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New patch to review for coreboot: 1d673fc AMD K8 and AMDFAM10, GFXUMA: drop use of uma_memory_base
by Kyösti Mälkki 20 Jul '12

20 Jul '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1246 -gerrit commit 1d673fcaac64270f96dc9ffc886b2bd3fc9c9b98 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Jul 20 08:24:49 2012 +0300 AMD K8 and AMDFAM10, GFXUMA: drop use of uma_memory_base The code in rs690 or rs780 is always used with K8 or AMDFAM10 northbridge. Without GFXUMA, both of these set the same static value indirectly using the variable uma_memory_base. Make the register setting with immediate value, to remove the obscure use of variable uma_memory_base. Change-Id: I5354684457a76e73013b4e34a4538a6d122eee8d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/amd/amdfam10/northbridge.c | 3 --- src/northbridge/amd/amdk8/northbridge.c | 3 --- src/southbridge/amd/rs690/cmn.c | 6 ++++++ src/southbridge/amd/rs780/cmn.c | 6 ++++++ 4 files changed, 12 insertions(+), 6 deletions(-) diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index c53da22..68e79ad 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -885,9 +885,6 @@ void setup_uma_memory(void) __func__, uma_memory_size, uma_memory_base); /* TODO: TOP_MEM2 */ -#else - uma_memory_size = 0x8000000; /* 128M recommended UMA */ - uma_memory_base = 0x38000000; /* 1GB system memory supposed */ #endif } diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index c4a8acd..21f2808 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -879,9 +879,6 @@ void setup_uma_memory(void) __func__, uma_memory_size, uma_memory_base); /* TODO: TOP_MEM2 */ -#else - uma_memory_size = 0x8000000; /* 128M recommended UMA */ - uma_memory_base = 0x38000000; /* 1GB system memory supposed */ #endif } diff --git a/src/southbridge/amd/rs690/cmn.c b/src/southbridge/amd/rs690/cmn.c index 68c46e9..004cf78 100644 --- a/src/southbridge/amd/rs690/cmn.c +++ b/src/southbridge/amd/rs690/cmn.c @@ -316,7 +316,13 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) void rs690_set_tom(device_t nb_dev) { /* set TOM */ +#if CONFIG_GFXUMA pci_write_config32(nb_dev, 0x90, uma_memory_base); nbmc_write_index(nb_dev, 0x1e, uma_memory_base); +#else + /* 1GB system memory supposed */ + pci_write_config32(nb_dev, 0x90, 0x38000000); + nbmc_write_index(nb_dev, 0x1e, 0x38000000); +#endif } diff --git a/src/southbridge/amd/rs780/cmn.c b/src/southbridge/amd/rs780/cmn.c index 5c72a04..30da675 100644 --- a/src/southbridge/amd/rs780/cmn.c +++ b/src/southbridge/amd/rs780/cmn.c @@ -357,8 +357,14 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) void rs780_set_tom(device_t nb_dev) { /* set TOM */ +#if CONFIG_GFXUMA pci_write_config32(nb_dev, 0x90, uma_memory_base); //nbmc_write_index(nb_dev, 0x1e, uma_memory_base); +#else + /* 1GB system memory supposed */ + pci_write_config32(nb_dev, 0x90, 0x38000000); + //nbmc_write_index(nb_dev, 0x1e, 0x38000000); +#endif } // extract single bit

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Re: [coreboot] [libpayload] EHCI USB driver transaction error
by Антон Кочков 20 Jul '12

20 Jul '12

Sorry, valid mainboard name - Foxconn H61MXV http://www.foxconnchannel.com/ProductDetail.aspx?T=motherboard&U=en-us00005… Best regards, Anton Kochkov. On Fri, Jul 20, 2012 at 12:10 PM, Антон Кочков <anton.kochkov(a)gmail.com>wrote: > Good day (or any other time)! > While working with/on libpayload for EHCI USB driver, i've found strange > error, when device is found (port status = 0x1803) > and sending first control transaction. > (usb_attach_device/get_free_address). > Mainboard - Foxconn N15235 > > wait_for_tds(): ERROR with packet > ========= EHCI TD at [0x0004d000] ========= > __EHCI_TD cerr: 0, total_len: 8 > __EHCI_TD: next_qtd [0x0004d120] > __EHCI_TD: alt_next_qtd [0x00000001] > __EHCI_TD: token [0x00080248] > __EHCI_TD: Bytes to Transfer [8] > __EHCI_TD: PID CODE: [2] > __EHCI_TD: Interrupt On Complete (IOC) [0] > __EHCI_TD: Status Active [0] > __EHCI_TD: Status Halted [1] > __EHCI_TD: Status Data Buffer Error [0] > __EHCI_TD: Status Babble detected [0] > __EHCI_TD: Status Transaction Error [1] > __EHCI_TD: Status Missed Micro Frame [0] > __EHCI_TD: Status Split Transaction State [0] > __EHCI_TD: Status Ping State [0] > wait_for_tds(): ----------------- > > Attaching full log, where dumping registers/packets on every step. > Hope someone know the reason. > > Best regards, > Anton Kochkov. > >

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coreboot July 2012