coreboot July 2012

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Patch merged into coreboot/master: 11d98bb Fix udelay() implementation for i945 romstage
by gerrit＠coreboot.org 20 Jul '12

20 Jul '12

the following patch was just integrated into master: commit 11d98bbd78ba811d961b11033240521a6f9ffb68 Author: Nico Huber <nico.huber(a)secunet.com> Date: Thu Jul 19 16:16:59 2012 +0200 Fix udelay() implementation for i945 romstage Work around 32-bit overflow with 64-bit multiplication. Calculate correct CPU frequency. Change-Id: I86d78f2d70b9f9c62fd4e1e0d765e92e4de83f67 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Build-Tested: build bot (Jenkins) at Fri Jul 20 15:37:47 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Fri Jul 20 23:41:38 2012, giving +2 See http://review.coreboot.org/1254 for details. -gerrit

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Patch merged into coreboot/master: ce2a44e Allow shutting down internal graphics if plugin graphics are preferred
by gerrit＠coreboot.org 20 Jul '12

20 Jul '12

the following patch was just integrated into master: commit ce2a44e3cbb5766261da8f1893b64e030edd0070 Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Fri Jul 20 12:29:33 2012 +0200 Allow shutting down internal graphics if plugin graphics are preferred VGA is this part-legacy thing that can cause trouble... For this, introduce device_t->disable(dev) method, in which a driver can take care to deregister the device if necessary. Change-Id: I3fecec07f402e530458b79eda30b2c274101fefa Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> Build-Tested: build bot (Jenkins) at Fri Jul 20 14:57:34 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Fri Jul 20 23:38:50 2012, giving +2 See http://review.coreboot.org/1251 for details. -gerrit

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Patch merged into coreboot/master: 3bb096d Allow YABEL to fake write accesses to config space
by gerrit＠coreboot.org 20 Jul '12

20 Jul '12

the following patch was just integrated into master: commit 3bb096d434e40819c882e841efc93c4b5d68f20a Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Fri Jul 20 13:44:50 2012 +0200 Allow YABEL to fake write accesses to config space A new Kconfig option tells YABEL to succeed on write accesses on other devices' config space without performing the actual write. This is enough for some basic bus modification done by some Option ROMs. Change-Id: Iab04f3a5c350b96654da4ba26858037f4c4b5c0a Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> Build-Tested: build bot (Jenkins) at Fri Jul 20 14:15:36 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Fri Jul 20 23:37:55 2012, giving +2 See http://review.coreboot.org/1249 for details. -gerrit

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Patch merged into coreboot/master: 05ca672 Drop VGA_BRIDGE_SETUP config option
by gerrit＠coreboot.org 20 Jul '12

20 Jul '12

the following patch was just integrated into master: commit 05ca672a0521ce81886e1bd4bfecfc81970507e6 Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Fri Jul 20 11:55:19 2012 +0200 Drop VGA_BRIDGE_SETUP config option It defaults to true, and isn't disabled anywhere in the tree. I also couldn't think of a case where it's actually useful. Change-Id: I126a47625d5294f3cfff225629f2a948a83c9b7e Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> Build-Tested: build bot (Jenkins) at Fri Jul 20 14:37:51 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Fri Jul 20 23:36:22 2012, giving +2 See http://review.coreboot.org/1250 for details. -gerrit

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Patch set updated for coreboot: 9738336 Make broadcast SIPI optional.
by Ronald G. Minnich 20 Jul '12

20 Jul '12

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1256 -gerrit commit 973833648d159a486bcc39fee683efb24d7ee468 Author: Ronald G. Minnich <rminnich(a)google.com> Date: Fri Jul 20 11:13:51 2012 -0700 Make broadcast SIPI optional. Broadcast SIPI breaks some platforms. This change introduces a new configuration variable, BROADCAST_SIPI, that controls how SIPI is managed. The default is off, since we know that works. You can turn it on but be aware that even if your platform boots it may get very odd crashes. We need to finish up the broadcast SIPI code and that will take some work. Change-Id: Icf0bd0357353ab7ac4b217939152aa67e8255fa2 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/arch/x86/Kconfig | 18 ++- src/arch/x86/include/arch/cpu.h | 27 +++ src/arch/x86/lib/cpu.c | 38 ++++- src/cpu/intel/hyperthreading/intel_sibling.c | 46 ++++- src/cpu/intel/model_1067x/model_1067x_init.c | 10 + src/cpu/intel/model_106cx/Kconfig | 1 - src/cpu/intel/model_106cx/model_106cx_init.c | 9 + src/cpu/intel/model_206ax/acpi.c | 16 ++ src/cpu/intel/model_206ax/model_206ax_init.c | 64 ++++++ src/cpu/intel/model_6ex/model_6ex_init.c | 5 + src/cpu/intel/model_6fx/model_6fx_init.c | 6 + src/cpu/intel/model_f2x/model_f2x_init.c | 6 + src/cpu/intel/model_f3x/model_f3x_init.c | 7 + src/cpu/intel/model_f4x/model_f4x_init.c | 7 + src/cpu/x86/lapic/lapic_cpu_init.c | 286 ++++++++++++++++++++++++-- src/cpu/x86/lapic/secondary.S | 23 ++- src/cpu/x86/pae/pgtbl.c | 11 + src/drivers/i2c/w83795/w83795.c | 9 +- src/include/cpu/cpu.h | 12 +- 19 files changed, 573 insertions(+), 28 deletions(-) diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 4dfbe70..f679fa0 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -2,7 +2,23 @@ menu "Architecture (x86)" # This is an SMP option. It relates to starting up APs. # It is usually set in mainboard/*/Kconfig. -# TODO: Improve description. +# If set, startup uses a BROADCAST to start all cores at once +# It is wrong for some HT cores, e.g. those in chromebooks. +# Because it is breaks some platforms, and the old code works on +# all platforms, we leave it off. +config BROADCAST_SIPI + bool + default n + depends on ARCH_X86 + +# This is another SMP option. On some HT platforms the AP +# must not try to halt, but rather must wait in the +# secondary start code for another SIPI so it can stop +# correctly. +config AP_IN_SIPI_WAIT + bool + default n + depends on ARCH_X86 && ! BROADCAST_SIPI # Aligns 16bit entry code in bootblock so that hyper-threading CPUs # can boot AP CPUs to enable their shared caches. diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 0fe5ea5..29215fd 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -158,6 +158,33 @@ struct cpu_driver { struct device; struct cpu_driver *find_cpu_driver(struct device *cpu); +#if CONFIG_BROADCAST_SIPI == 0 +struct cpu_info { + device_t cpu; + unsigned int index; +}; + +static inline struct cpu_info *cpu_info(void) +{ + struct cpu_info *ci; + __asm__("andl %%esp,%0; " + "orl %2, %0 " + :"=r" (ci) + : "0" (~(CONFIG_STACK_SIZE - 1)), + "r" (CONFIG_STACK_SIZE - sizeof(struct cpu_info)) + ); + return ci; +} + +static inline unsigned long cpu_index(void) +{ + struct cpu_info *ci; + ci = cpu_info(); + return ci->index; +} + +#endif /* ! CONFIG_BROADCAST_SIPI */ + struct cpuinfo_x86 { uint8_t x86; /* CPU family */ uint8_t x86_vendor; /* CPU vendor */ diff --git a/src/arch/x86/lib/cpu.c b/src/arch/x86/lib/cpu.c index 7cd955e..9e13897 100644 --- a/src/arch/x86/lib/cpu.c +++ b/src/arch/x86/lib/cpu.c @@ -9,7 +9,9 @@ #include <device/path.h> #include <device/device.h> #include <smp/spinlock.h> +#if CONFIG_BROADCAST_SIPI == 1 #include <cpu/x86/lapic.h> +#endif /* CONFIG_BROADCAST_SIPI */ /* Standard macro to see if a specific flag is changeable */ static inline int flag_is_changeable_p(uint32_t flag) @@ -235,7 +237,15 @@ static void set_cpu_ops(struct device *cpu) cpu->ops = driver ? driver->ops : NULL; } +#if CONFIG_BROADCAST_SIPI == 0 +void cpu_initialize(unsigned int index) +#else /* CONFIG_BROADCAST_SIPI */ +#if CONFIG_SMP +static spinlock_t start_cpu_lock = SPIN_LOCK_UNLOCKED; +#endif + void cpu_initialize(struct bus *cpu_bus, int index) +#endif /* CONFIG_BROADCAST_SIPI */ { /* Because we busy wait at the printk spinlock. * It is important to keep the number of printed messages @@ -244,16 +254,41 @@ void cpu_initialize(struct bus *cpu_bus, int index) */ struct device *cpu; struct cpuinfo_x86 c; +#if CONFIG_BROADCAST_SIPI == 1 struct device_path cpu_path; unsigned char id = lapicid(); cpu_path.type = DEVICE_PATH_APIC; cpu_path.apic.apic_id = id; + cpu_path.type = DEVICE_PATH_APIC; + cpu_path.apic.apic_id = id; + cpu_path.apic.index = index; +#if CONFIG_SMP + spin_lock(&start_cpu_lock); +#endif cpu = alloc_find_dev(cpu_bus, &cpu_path); +#if CONFIG_SMP + spin_unlock(&start_cpu_lock); +#endif + printk(BIOS_DEBUG, "Initializing CPU #%d\n", id); +#else /* ! CONFIG_BROADCAST_SIPI */ + struct cpu_info *info; + info = cpu_info(); + + cpu = info->cpu; + if (!cpu) { + die("CPU: missing cpu device structure"); + } + cpu->path.apic.index = index; printk(BIOS_DEBUG, "Initializing CPU #%d\n", id); + cpu = info->cpu; + if (!cpu) { + die("CPU: missing cpu device structure"); + } +#endif /* CONFIG_BROADCAST_SIPI */ /* Find what type of cpu we are dealing with */ identify_cpu(cpu); @@ -284,8 +319,7 @@ void cpu_initialize(struct bus *cpu_bus, int index) cpu->ops->init(cpu); } - printk(BIOS_INFO, "CPU #%d initialized\n", id); + printk(BIOS_INFO, "CPU #%d ,lapic id %d, initialized\n", index, id); - return; } diff --git a/src/cpu/intel/hyperthreading/intel_sibling.c b/src/cpu/intel/hyperthreading/intel_sibling.c index 8377cd0..cabd3cc 100644 --- a/src/cpu/intel/hyperthreading/intel_sibling.c +++ b/src/cpu/intel/hyperthreading/intel_sibling.c @@ -7,13 +7,55 @@ #include <smp/spinlock.h> #include <assert.h> +#if CONFIG_BROADCAST_SIPI == 0 +#if !CONFIG_SERIAL_CPU_INIT +#error Intel hyper-threading requires serialized cpu init +#endif + +static int first_time = 1; +static int disable_siblings = !CONFIG_LOGICAL_CPUS; + +void intel_sibling_init(device_t cpu) +{ + unsigned int core_ids, apic_ids, threads; + + /* See if I am a sibling cpu */ + if (cpu->path.apic.apic_id & (siblings -1)) { + if (disable_siblings) { + cpu->enabled = 0; + } + return; + } + /* I am the primary cpu start up my siblings */ + for(i = 1; i < siblings; i++) { + struct device_path cpu_path; + device_t new; + /* Build the cpu device path */ + cpu_path.type = DEVICE_PATH_APIC; + cpu_path.apic.apic_id = cpu->path.apic.apic_id + i; + + /* Allocate new cpu device structure iff sibling CPU + * was not in static device tree. + */ + new = alloc_find_dev(cpu->bus, &cpu_path); + + if (!new) { + continue; + } + + printk(BIOS_DEBUG, "CPU: %u has sibling %u\n", + cpu->path.apic.apic_id, + new->path.apic.apic_id); + } +} + +#else /* CONFIG_BROADCAST_SIPI */ /* Return true if running thread does not have the smallest lapic ID * within a CPU core. */ int intel_ht_sibling(void) { unsigned int core_ids, apic_ids, threads; - apic_ids = 1; if (cpuid_eax(0) >= 1) apic_ids = (cpuid_ebx(1) >> 16) & 0xff; @@ -27,3 +69,5 @@ int intel_ht_sibling(void) threads = (apic_ids / core_ids); return !!(lapicid() & (threads-1)); } +#endif /* CONFIG_BROADCAST_SIPI */ + diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c index ddd1381..4a91b04 100644 --- a/src/cpu/intel/model_1067x/model_1067x_init.c +++ b/src/cpu/intel/model_1067x/model_1067x_init.c @@ -29,6 +29,10 @@ #include <cpu/x86/lapic.h> #include <cpu/intel/microcode.h> #include <cpu/intel/speedstep.h> + +#if CONFIG_BROADCAST_SIPI == 0 +#include <cpu/intel/hyperthreading.h> +#endif /* ! CONFIG_BROADCAST_SIPI */ #include <cpu/x86/cache.h> #include <cpu/x86/name.h> @@ -220,6 +224,12 @@ static void model_1067x_init(device_t cpu) /* PIC thermal sensor control */ configure_pic_thermal_sensors(); +#if CONFIG_BROADCAST_SIPI == 0 + + /* Start up my cpu siblings */ + intel_sibling_init(cpu); +#endif /* ! CONFIG_BROADCAST_SIPI */ + } static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_106cx/Kconfig b/src/cpu/intel/model_106cx/Kconfig index 2ef7392..00abf6b 100644 --- a/src/cpu/intel/model_106cx/Kconfig +++ b/src/cpu/intel/model_106cx/Kconfig @@ -11,4 +11,3 @@ config CPU_ADDR_BITS default 32 endif - diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c index 8d2ef3d..16660ac 100644 --- a/src/cpu/intel/model_106cx/model_106cx_init.c +++ b/src/cpu/intel/model_106cx/model_106cx_init.c @@ -27,6 +27,10 @@ #include <cpu/x86/lapic.h> #include <cpu/intel/microcode.h> #include <cpu/intel/speedstep.h> + +#if CONFIG_BROADCAST_SIPI == 0 +#include <cpu/intel/hyperthreading.h> +#endif /* ! CONFIG_BROADCAST_SIPI */ #include <cpu/x86/cache.h> #include <cpu/x86/name.h> #include <usbdebug.h> @@ -177,6 +181,11 @@ static void model_106cx_init(device_t cpu) configure_misc(); /* TODO: PIC thermal sensor control */ +#if CONFIG_BROADCAST_SIPI == 0 + + /* Start up my cpu siblings */ + intel_sibling_init(cpu); +#endif /* ! CONFIG_BROADCAST_SIPI */ } static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_206ax/acpi.c b/src/cpu/intel/model_206ax/acpi.c index dea23e7..1b5fa0a 100644 --- a/src/cpu/intel/model_206ax/acpi.c +++ b/src/cpu/intel/model_206ax/acpi.c @@ -26,7 +26,9 @@ #include <arch/acpigen.h> #include <arch/cpu.h> #include <cpu/x86/msr.h> +#if CONFIG_BROADCAST_SIPI == 1 #include <cpu/x86/lapic.h> +#endif /* CONFIG_BROADCAST_SIPI */ #include <cpu/intel/acpi.h> #include <cpu/intel/speedstep.h> #include <cpu/intel/turbo.h> @@ -89,8 +91,14 @@ static int generate_cstate_entries(acpi_cstate_t *cstates, static int generate_C_state_entries(void) { +#if CONFIG_BROADCAST_SIPI == 0 + struct cpu_info *info; +#endif /* ! CONFIG_BROADCAST_SIPI */ + struct cpu_driver *cpu; +#if CONFIG_BROADCAST_SIPI == 1 struct cpu_driver *cpu; struct device *cpu_dev; +#endif /* CONFIG_BROADCAST_SIPI */ int len, lenif; device_t lapic; struct cpu_intel_model_206ax_config *conf = NULL; @@ -104,10 +112,18 @@ static int generate_C_state_entries(void) return 0; /* Find CPU map of supported C-states */ +#if CONFIG_BROADCAST_SIPI == 0 + info = cpu_info(); + if (!info) + return 0; + cpu = find_cpu_driver(info->cpu); +#else /* CONFIG_BROADCAST_SIPI */ cpu_dev = dev_find_lapic(lapicid()); if (!cpu_dev) return 0; cpu = find_cpu_driver(cpu_dev); +#endif /* CONFIG_BROADCAST_SIPI */ + if (!cpu || !cpu->cstates) return 0; diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index d60c237..6e76d7f 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -414,6 +414,63 @@ static void configure_mca(void) static unsigned ehci_debug_addr; #endif +#if CONFIG_BROADCAST_SIPI == 0 +/* + * Initialize any extra cores/threads in this package. + */ +static void intel_cores_init(device_t cpu) +{ + struct cpuid_result result; + unsigned cores, threads, i; + + result = cpuid_ext(0xb, 0); /* Threads per core */ + threads = result.ebx & 0xff; + + result = cpuid_ext(0xb, 1); /* Cores per package */ + cores = result.ebx & 0xff; + + /* Only initialize extra cores from BSP */ + if (cpu->path.apic.apic_id) + return; + + printk(BIOS_DEBUG, "CPU: %u has %u cores %u threads\n", + cpu->path.apic.apic_id, cores, threads); + + for (i = 1; i < cores; ++i) { + struct device_path cpu_path; + device_t new; + + /* Build the cpu device path */ + cpu_path.type = DEVICE_PATH_APIC; + cpu_path.apic.apic_id = + cpu->path.apic.apic_id + i; + + /* Update APIC ID if no hyperthreading */ + if (threads == 1) + cpu_path.apic.apic_id <<= 1; + + /* Allocate the new cpu device structure */ + new = alloc_dev(cpu->bus, &cpu_path); + if (!new) + continue; + + printk(BIOS_DEBUG, "CPU: %u has core %u\n", + cpu->path.apic.apic_id, + new->path.apic.apic_id); + +#if CONFIG_SMP && CONFIG_MAX_CPUS > 1 + /* Start the new cpu */ + if (!start_cpu(new)) { + /* Record the error in cpu? */ + printk(BIOS_ERR, "CPU %u would not start!\n", + new->path.apic.apic_id); + } +#endif + } +} + +#endif /* ! CONFIG_BROADCAST_SIPI */ + static void model_206ax_init(device_t cpu) { char processor_name[49]; @@ -476,6 +533,13 @@ static void model_206ax_init(device_t cpu) /* Enable Turbo */ enable_turbo(); + +#if CONFIG_BROADCAST_SIPI == 0 + + /* Start up extra cores */ + intel_cores_init(cpu); +#endif /* ! CONFIG_BROADCAST_SIPI */ + } static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c index a0afd2e..989ca27 100644 --- a/src/cpu/intel/model_6ex/model_6ex_init.c +++ b/src/cpu/intel/model_6ex/model_6ex_init.c @@ -205,6 +205,11 @@ static void model_6ex_init(device_t cpu) /* PIC thermal sensor control */ configure_pic_thermal_sensors(); +#if CONFIG_BROADCAST_SIPI == 0 + + /* Start up my cpu siblings */ + intel_sibling_init(cpu); +#endif /* ! CONFIG_BROADCAST_SIPI */ } static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c index c5d7a6b..171059a 100644 --- a/src/cpu/intel/model_6fx/model_6fx_init.c +++ b/src/cpu/intel/model_6fx/model_6fx_init.c @@ -243,6 +243,12 @@ static void model_6fx_init(device_t cpu) /* PIC thermal sensor control */ configure_pic_thermal_sensors(); + +#if CONFIG_BROADCAST_SIPI == 0 + + /* Start up my cpu siblings */ + intel_sibling_init(cpu); +#endif /* ! CONFIG_BROADCAST_SIPI */ } static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_f2x/model_f2x_init.c b/src/cpu/intel/model_f2x/model_f2x_init.c index fa9e05f..87c3157 100644 --- a/src/cpu/intel/model_f2x/model_f2x_init.c +++ b/src/cpu/intel/model_f2x/model_f2x_init.c @@ -60,6 +60,12 @@ static void model_f2x_init(device_t cpu) /* Enable the local cpu apics */ setup_lapic(); + +#if CONFIG_BROADCAST_SIPI == 0 + + /* Start up my cpu siblings */ + intel_sibling_init(cpu); +#endif /* ! CONFIG_BROADCAST_SIPI */ }; static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_f3x/model_f3x_init.c b/src/cpu/intel/model_f3x/model_f3x_init.c index dd2a45f..96c38cd 100644 --- a/src/cpu/intel/model_f3x/model_f3x_init.c +++ b/src/cpu/intel/model_f3x/model_f3x_init.c @@ -43,6 +43,13 @@ static void model_f3x_init(device_t cpu) /* Enable the local cpu apics */ setup_lapic(); + +#if CONFIG_BROADCAST_SIPI == 0 + + /* Start up my cpu siblings */ + intel_sibling_init(cpu); +#endif /* ! CONFIG_BROADCAST_SIPI */ + }; static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_f4x/model_f4x_init.c b/src/cpu/intel/model_f4x/model_f4x_init.c index af7d9d2..cade95f 100644 --- a/src/cpu/intel/model_f4x/model_f4x_init.c +++ b/src/cpu/intel/model_f4x/model_f4x_init.c @@ -51,6 +51,13 @@ static void model_f4x_init(device_t cpu) /* Enable the local cpu apics */ setup_lapic(); + +#if CONFIG_BROADCAST_SIPI == 0 + + /* Start up my cpu siblings */ + intel_sibling_init(cpu); +#endif /* ! CONFIG_BROADCAST_SIPI */ + }; static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index b6dc560..b29340d 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -60,9 +60,27 @@ static void copy_secondary_start_to_1m_below(void) printk(BIOS_DEBUG, "start_eip=0x%08lx, code_size=0x%08lx\n", (long unsigned int)AP_SIPI_VECTOR, code_size); } -static struct bus *current_cpu_bus; +#ifdef __SSE3__ +static __inline__ __attribute__((always_inline)) unsigned long readcr4(void) +{ + unsigned long value; + __asm__ __volatile__ ( + "mov %%cr4, %[value]" + : [value] "=a" (value)); + return value; +} -static int lapic_start_cpus(struct bus *cpu_bus) +static __inline__ __attribute__((always_inline)) void + writecr4(unsigned long Data) +{ + __asm__ __volatile__ ( + "mov %%eax, %%cr4" + : + : "a" (Data) + ); +} +#if CONFIG_BROADCAST_SIPI == 0 +static int lapic_start_cpu(unsigned long apicid) { int timeout; unsigned long send_status, accept_status; @@ -187,26 +205,239 @@ static void stop_all_ap_cpus(void) mdelay(10); } -#ifdef __SSE3__ -static __inline__ __attribute__((always_inline)) unsigned long readcr4(void) + +/* C entry point of secondary cpus */ +void secondary_cpu_init(int index) { - unsigned long value; - __asm__ __volatile__ ( - "mov %%cr4, %[value]" - : [value] "=a" (value)); - return value; +#ifdef __SSE3__ + /* + * Seems that CR4 was cleared when AP start via lapic_start_cpu() + * Turn on CR4.OSFXSR and CR4.OSXMMEXCPT when SSE options enabled + */ + u32 cr4_val; + cr4_val = readcr4(); + cr4_val |= (1 << 9 | 1 << 10); + writecr4(cr4_val); +#endif + atomic_inc(&active_cpus); + cpu_initialize(current_cpu_bus, index); + atomic_dec(&active_cpus); } -static __inline__ __attribute__((always_inline)) void writecr4(unsigned long Data) +static void wait_other_cpus_stop(struct bus *cpu_bus) { - __asm__ __volatile__ ( - "mov %%eax, %%cr4" - : - : "a" (Data) - ); + device_t cpu; + int old_active_count, active_count; + long loopcount = 0; + + /* Now loop until the other cpus have finished initializing */ + old_active_count = 1; + active_count = atomic_read(&active_cpus); + while(active_count > 1) { + if (active_count != old_active_count) { + printk(BIOS_INFO, "Waiting for %d CPUS to stop\n", active_count - 1); + old_active_count = active_count; + } + udelay(10); + active_count = atomic_read(&active_cpus); + loopcount++; + } + for(cpu = cpu_bus->children; cpu; cpu = cpu->sibling) { + if (cpu->path.type != DEVICE_PATH_APIC) { + continue; + } + if (cpu->path.apic.apic_id == SPEEDSTEP_APIC_MAGIC) { + continue; + } + if (!cpu->initialized) { + printk(BIOS_ERR, "CPU 0x%02x did not initialize!\n", + cpu->path.apic.apic_id); + } + } + stop_all_ap_cpus(); + printk(BIOS_DEBUG, "All AP CPUs stopped (%ld loops)\n", loopcount); } + +#endif /* CONFIG_SMP */ + +void initialize_cpus(struct bus *cpu_bus) +{ + struct device_path cpu_path; + +#if NEED_LAPIC == 1 + /* Ensure the local apic is enabled */ + enable_lapic(); + + /* Get the device path of the boot cpu */ + cpu_path.type = DEVICE_PATH_APIC; + cpu_path.apic.apic_id = lapicid(); +#else + /* Get the device path of the boot cpu */ + cpu_path.type = DEVICE_PATH_CPU; + cpu_path.cpu.id = 0; +#endif + +#if CONFIG_SMP + copy_secondary_start_to_1m_below(); // why here? In case some day we can start core1 in amd_sibling_init +#endif + +#if CONFIG_HAVE_SMI_HANDLER + smm_init(); #endif + cpus_ready_for_init(); + + /* Initialize the bootstrap processor */ + cpu_initialize(cpu_bus, 0); + +#if CONFIG_SMP + lapic_start_cpus(cpu_bus); + /* Now wait the rest of the cpus stop*/ + wait_other_cpus_stop(cpu_bus); +#endif +} + +#else + +static struct bus *current_cpu_bus; + +static int lapic_start_cpus(struct bus *cpu_bus) +#if CONFIG_SMP && CONFIG_MAX_CPUS > 1 + +static struct bus *current_cpu_bus; + +static int lapic_start_cpus(struct bus *cpu_bus) +{ + int timeout; + unsigned long send_status, accept_status, start_eip; + int maxlvt; + + /* + * Starting actual IPI sequence... + */ + + current_cpu_bus = cpu_bus; + + printk(BIOS_SPEW, "Asserting INIT.\n"); + + /* Send INIT SIPI to target chip */ + lapic_write_around(LAPIC_ICR2, 0); + lapic_write_around(LAPIC_ICR, LAPIC_INT_ASSERT + | LAPIC_DM_INIT | LAPIC_DEST_ALLBUT); + + printk(BIOS_DEBUG, "Waiting for send to finish...\n"); + timeout = 0; + do { + printk(BIOS_SPEW, "+"); + udelay(100); + send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY; + } while (send_status && (timeout++ < 1000)); + if (timeout >= 1000) { + printk(BIOS_DEBUG, "First apic write timed out. Disabling\n"); + // too bad. + printk(BIOS_DEBUG, "ESR is 0x%lx\n", lapic_read(LAPIC_ESR)); + if (lapic_read(LAPIC_ESR)) { + printk(BIOS_DEBUG, "Try to reset ESR\n"); + lapic_write_around(LAPIC_ESR, 0); + printk(BIOS_DEBUG, "ESR is 0x%lx\n", lapic_read(LAPIC_ESR)); + } + return 0; + } + start_eip = get_valid_start_eip((unsigned long)_secondary_start); + + maxlvt = 4; + + printk(BIOS_SPEW, "Sending STARTUP.\n"); + lapic_read_around(LAPIC_SPIV); + lapic_write(LAPIC_ESR, 0); + lapic_read(LAPIC_ESR); + printk(BIOS_SPEW, "After apic_write.\n"); + + /* + * STARTUP IPI + */ + + /* Target chip */ + lapic_write_around(LAPIC_ICR2, 0); + printk(BIOS_SPEW, "After apic_write_around(LAPIC_ICR2, 0);\n"); + + /* Boot on the stack */ + /* Kick the second */ + lapic_write_around(LAPIC_ICR, + LAPIC_INT_ASSERT | LAPIC_DM_STARTUP | LAPIC_DEST_ALLBUT + | (start_eip >> 12)); + printk(BIOS_SPEW, "After apic_write_around allbut starteip %p.\n", + (void *)start_eip); + + /* + * Give the other CPU some time to accept the IPI. + */ + udelay(300); + + printk(BIOS_DEBUG, "Startup point 1.\n"); + + printk(BIOS_DEBUG, "Waiting for send to finish...\n"); + timeout = 0; + do { + printk(BIOS_DEBUG, "+"); + udelay(100); + send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY; + } while (send_status && (timeout++ < 1000)); + + /* + * Give the other CPU some time to accept the IPI. + */ + udelay(200); + /* + * Due to the Pentium erratum 3AP. + */ + if (maxlvt > 3) { + lapic_read_around(LAPIC_SPIV); + lapic_write(LAPIC_ESR, 0); + } + accept_status = (lapic_read(LAPIC_ESR) & 0xEF); + + printk(BIOS_DEBUG, "After Startup.\n"); + if (send_status) + printk(BIOS_WARNING, "APIC never delivered???\n"); + if (accept_status) + printk(BIOS_WARNING, "APIC delivery error (%lx).\n", + accept_status); + if (send_status || accept_status) + return 0; + return 1; +} + + +/* Number of cpus that are currently running in coreboot */ +static atomic_t active_cpus = ATOMIC_INIT(1); + +volatile unsigned long secondary_stack; +extern unsigned char _estack[]; + +static void stop_all_ap_cpus(void) +{ + unsigned long send_status; + int timeout; + /* send an LAPIC INIT to all but myself */ + lapic_write_around(LAPIC_ICR2, 0); + lapic_write_around(LAPIC_ICR, + LAPIC_INT_ASSERT | LAPIC_DM_INIT | LAPIC_DEST_ALLBUT); + + /* wait for the ipi send to finish */ + printk(BIOS_SPEW, "Waiting for send to finish...\n"); + timeout = 0; + do { + printk(BIOS_SPEW, "+"); + udelay(100); + send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY; + } while (send_status && (timeout++ < 1000)); + if (timeout >= 1000) { + printk(BIOS_ERR, "timed out\n"); + } + mdelay(10); +} + /* C entry point of secondary cpus */ void secondary_cpu_init(int index) { @@ -236,7 +467,8 @@ static void wait_other_cpus_stop(struct bus *cpu_bus) active_count = atomic_read(&active_cpus); while(active_count > 1) { if (active_count != old_active_count) { - printk(BIOS_INFO, "Waiting for %d CPUS to stop\n", active_count - 1); + printk(BIOS_INFO, "Waiting for %d CPUS to stop\n", + active_count - 1); old_active_count = active_count; } udelay(10); @@ -257,6 +489,23 @@ static void wait_other_cpus_stop(struct bus *cpu_bus) } stop_all_ap_cpus(); printk(BIOS_DEBUG, "All AP CPUs stopped (%ld loops)\n", loopcount); +#if 0 + for(i = 1; i <= last_cpu_index; i++){ + unsigned long *stack = stacks[i]; + int lowest; + int maxstack = (CONFIG_STACK_SIZE - sizeof(struct cpu_info)) + /sizeof(*stack) - 1; + if (stack[0] != 0xDEADBEEF) + printk(BIOS_ERR, "CPU%d overran its stack\n", i); + for(lowest = 0; lowest < maxstack; lowest++) + if (stack[lowest] != 0xDEADBEEF) + break; + printk(BIOS_SPEW, "CPU%d: stack allocated from %p to %p:", i, + stack, &stack[maxstack]); + printk(BIOS_SPEW, "lowest stack address was %p\n", + &stack[lowest]); + } +#endif } #endif /* CONFIG_SMP */ @@ -279,7 +528,8 @@ void initialize_cpus(struct bus *cpu_bus) #endif #if CONFIG_SMP - copy_secondary_start_to_1m_below(); // why here? In case some day we can start core1 in amd_sibling_init + // why here? In case some day we can start core1 in amd_sibling_init + copy_secondary_start_to_lowest_1M(); #endif #if CONFIG_HAVE_SMI_HANDLER @@ -297,4 +547,4 @@ void initialize_cpus(struct bus *cpu_bus) wait_other_cpus_stop(cpu_bus); #endif } - +#endif \ No newline at end of file diff --git a/src/cpu/x86/lapic/secondary.S b/src/cpu/x86/lapic/secondary.S index e6650ec..b56e378 100644 --- a/src/cpu/x86/lapic/secondary.S +++ b/src/cpu/x86/lapic/secondary.S @@ -2,7 +2,11 @@ #include <cpu/x86/lapic_def.h> .text - .globl _secondary_start, _secondary_start_end, cpucount, ap_protected_start + .globl _secondary_start, _secondary_start_end, ap_protected_start +#if CONFIG_BROADCAST_SIPI == 1 + .globl cpucount +#endif + .balign 4096 _secondary_start: .code16 cli @@ -49,6 +53,14 @@ __ap_protected_start: /* Load the Interrupt descriptor table */ lidt idtarg +#if CONFIG_BROADCAST_SIPI == 0 + /* Set the stack pointer, and flag that we are done */ + xorl %eax, %eax + movl secondary_stack, %esp + movl secondary_cpu_index, %edi + pushl %edi + movl %eax, secondary_stack +#else /* CONFIG_BROADCAST_SIPI */ /* increment our cpu index */ movl $1, %eax lock xadd %eax, cpucount @@ -61,10 +73,19 @@ __ap_protected_start: add %eax, %esp pushl %ecx +#endif /* CONFIG_BROADCAST_SIPI */ + call secondary_cpu_init 1: hlt jmp 1b +#if CONFIG_BROADCAST_SIPI == 1 cpucount: .long 1 +#endif /* CONFIG_BROADCAST_SIPI */ +gdtaddr: + .word gdt_limit /* the table limit */ + .long gdt /* we know the offset */ + +_secondary_start_end: .code32 diff --git a/src/cpu/x86/pae/pgtbl.c b/src/cpu/x86/pae/pgtbl.c index 7aa17c2..f84ec6e 100644 --- a/src/cpu/x86/pae/pgtbl.c +++ b/src/cpu/x86/pae/pgtbl.c @@ -7,6 +7,15 @@ #include <cpu/cpu.h> #include <cpu/x86/pae.h> #include <cpu/x86/lapic.h> + +#if CONFIG_BROADCAST_SIPI == 1 +#include <device/device.h> +#endif /* CONFIG_BROADCAST_SIPI */ +#include <cpu/cpu.h> +#include <cpu/x86/pae.h> +#if CONFIG_BROADCAST_SIPI == 1 +#include <cpu/x86/lapic.h> +#endif /* CONFIG_BROADCAST_SIPI */ #include <string.h> static void paging_off(void) @@ -45,6 +54,7 @@ static void paging_on(void *pdp) ); } +#if CONFIG_BROADCAST_SIPI == 1 static int cpu_index(void) { device_t dev = dev_find_lapic(lapicid()); @@ -53,6 +63,7 @@ static int cpu_index(void) return dev->path.apic.index; } +#endif /* CONFIG_BROADCAST_SIPI */ void *map_2M_page(unsigned long page) { struct pde { diff --git a/src/drivers/i2c/w83795/w83795.c b/src/drivers/i2c/w83795/w83795.c index 12be4da..14b12b3 100644 --- a/src/drivers/i2c/w83795/w83795.c +++ b/src/drivers/i2c/w83795/w83795.c @@ -22,7 +22,9 @@ #include <console/console.h> #include <device/device.h> #include "southbridge/amd/cimx/sb700/smbus.h" /*SMBUS_IO_BASE*/ +#if CONFIG_BROADCAST_SIPI == 1 #include <cpu/x86/lapic.h> +#endif /* CONFIG_BROADCAST_SIPI */ #include "w83795.h" static u32 w83795_set_bank(u8 bank) @@ -225,8 +227,13 @@ static void w83795_init(w83795_fan_mode_t mode, u8 dts_src) static void w83795_hwm_init(device_t dev) { struct device *cpu; - +#if CONFIG_BROADCAST_SIPI == 0 + struct cpu_info *info; + info = cpu_info(); + cpu = info->cpu; +#else /* CONFIG_BROADCAST_SIPI */ cpu = dev_find_lapic(lapicid()); +#endif /* CONFIG_BROADCAST_SIPI */ if (!cpu) die("CPU: missing cpu device structure"); diff --git a/src/include/cpu/cpu.h b/src/include/cpu/cpu.h index 9765dfd..0bf85d6 100644 --- a/src/include/cpu/cpu.h +++ b/src/include/cpu/cpu.h @@ -4,12 +4,18 @@ #include <arch/cpu.h> #if !defined(__ROMCC__) + +#if CONFIG_BROADCAST_SIPI == 0 +void secondary_cpu_init(unsigned int cpu_index)__attribute__((regparm(0))); +void cpu_initialize(unsigned int cpu_index); +#else /* CONFIG_BROADCAST_SIPI */ +void secondary_cpu_init(int index); +extern unsigned int cpucount; void cpu_initialize(struct bus *cpu_bus, int index); +#endif /* CONFIG_BROADCAST_SIPI */ + struct bus; void initialize_cpus(struct bus *cpu_bus); -void secondary_cpu_init(int index); - -extern unsigned int cpucount; #if !CONFIG_WAIT_BEFORE_CPUS_INIT #define cpus_ready_for_init() do {} while(0)

1 0

New patch to review for coreboot: 8ec22a4 Make broadcast SIPI optional.
by Ronald G. Minnich 20 Jul '12

20 Jul '12

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1256 -gerrit commit 8ec22a4dd5e583d49e4f1899a6bfc320d526507a Author: Ronald G. Minnich <rminnich(a)google.com> Date: Fri Jul 20 11:13:51 2012 -0700 Make broadcast SIPI optional. Broadcast SIPI breaks some platforms. This change introduces a new configuration variable, BROADCAST_SIPI, that controls how SIPI is managed. The default is off, since we know that works. You can turn it on but be aware that even if your platform boots it may get very odd crashes. We need to finish up the broadcast SIPI code and that will take some work. Change-Id: Icf0bd0357353ab7ac4b217939152aa67e8255fa2 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/arch/x86/Kconfig | 18 ++- src/arch/x86/include/arch/cpu.h | 27 +++ src/arch/x86/lib/cpu.c | 35 +++- src/cpu/intel/hyperthreading/intel_sibling.c | 46 ++++- src/cpu/intel/model_1067x/model_1067x_init.c | 10 + src/cpu/intel/model_106cx/Kconfig | 1 - src/cpu/intel/model_106cx/model_106cx_init.c | 9 + src/cpu/intel/model_206ax/acpi.c | 16 ++ src/cpu/intel/model_206ax/model_206ax_init.c | 64 ++++++ src/cpu/intel/model_6ex/model_6ex_init.c | 5 + src/cpu/intel/model_6fx/model_6fx_init.c | 6 + src/cpu/intel/model_f2x/model_f2x_init.c | 6 + src/cpu/intel/model_f3x/model_f3x_init.c | 7 + src/cpu/intel/model_f4x/model_f4x_init.c | 7 + src/cpu/x86/lapic/lapic_cpu_init.c | 286 ++++++++++++++++++++++++-- src/cpu/x86/lapic/secondary.S | 23 ++- src/cpu/x86/pae/pgtbl.c | 11 + src/drivers/i2c/w83795/w83795.c | 9 +- src/include/cpu/cpu.h | 12 +- 19 files changed, 570 insertions(+), 28 deletions(-) diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 4dfbe70..f679fa0 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -2,7 +2,23 @@ menu "Architecture (x86)" # This is an SMP option. It relates to starting up APs. # It is usually set in mainboard/*/Kconfig. -# TODO: Improve description. +# If set, startup uses a BROADCAST to start all cores at once +# It is wrong for some HT cores, e.g. those in chromebooks. +# Because it is breaks some platforms, and the old code works on +# all platforms, we leave it off. +config BROADCAST_SIPI + bool + default n + depends on ARCH_X86 + +# This is another SMP option. On some HT platforms the AP +# must not try to halt, but rather must wait in the +# secondary start code for another SIPI so it can stop +# correctly. +config AP_IN_SIPI_WAIT + bool + default n + depends on ARCH_X86 && ! BROADCAST_SIPI # Aligns 16bit entry code in bootblock so that hyper-threading CPUs # can boot AP CPUs to enable their shared caches. diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 0fe5ea5..29215fd 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -158,6 +158,33 @@ struct cpu_driver { struct device; struct cpu_driver *find_cpu_driver(struct device *cpu); +#if CONFIG_BROADCAST_SIPI == 0 +struct cpu_info { + device_t cpu; + unsigned int index; +}; + +static inline struct cpu_info *cpu_info(void) +{ + struct cpu_info *ci; + __asm__("andl %%esp,%0; " + "orl %2, %0 " + :"=r" (ci) + : "0" (~(CONFIG_STACK_SIZE - 1)), + "r" (CONFIG_STACK_SIZE - sizeof(struct cpu_info)) + ); + return ci; +} + +static inline unsigned long cpu_index(void) +{ + struct cpu_info *ci; + ci = cpu_info(); + return ci->index; +} + +#endif /* ! CONFIG_BROADCAST_SIPI */ + struct cpuinfo_x86 { uint8_t x86; /* CPU family */ uint8_t x86_vendor; /* CPU vendor */ diff --git a/src/arch/x86/lib/cpu.c b/src/arch/x86/lib/cpu.c index 7cd955e..dea980d 100644 --- a/src/arch/x86/lib/cpu.c +++ b/src/arch/x86/lib/cpu.c @@ -9,7 +9,9 @@ #include <device/path.h> #include <device/device.h> #include <smp/spinlock.h> +#if CONFIG_BROADCAST_SIPI == 1 #include <cpu/x86/lapic.h> +#endif /* CONFIG_BROADCAST_SIPI */ /* Standard macro to see if a specific flag is changeable */ static inline int flag_is_changeable_p(uint32_t flag) @@ -235,7 +237,15 @@ static void set_cpu_ops(struct device *cpu) cpu->ops = driver ? driver->ops : NULL; } +#if CONFIG_BROADCAST_SIPI == 0 +void cpu_initialize(unsigned int index) +#else /* CONFIG_BROADCAST_SIPI */ +#if CONFIG_SMP +static spinlock_t start_cpu_lock = SPIN_LOCK_UNLOCKED; +#endif + void cpu_initialize(struct bus *cpu_bus, int index) +#endif /* CONFIG_BROADCAST_SIPI */ { /* Because we busy wait at the printk spinlock. * It is important to keep the number of printed messages @@ -244,16 +254,38 @@ void cpu_initialize(struct bus *cpu_bus, int index) */ struct device *cpu; struct cpuinfo_x86 c; +#if CONFIG_BROADCAST_SIPI == 1 struct device_path cpu_path; unsigned char id = lapicid(); cpu_path.type = DEVICE_PATH_APIC; cpu_path.apic.apic_id = id; + cpu_path.type = DEVICE_PATH_APIC; + cpu_path.apic.apic_id = id; + cpu_path.apic.index = index; + +#if CONFIG_SMP + spin_lock(&start_cpu_lock); +#endif + cpu = alloc_find_dev(cpu_bus, &cpu_path); +#if CONFIG_SMP + spin_unlock(&start_cpu_lock); +#endif + printk(BIOS_DEBUG, "Initializing CPU #%d\n", id); +#else /* ! CONFIG_BROADCAST_SIPI */ + struct cpu_info *info; + info = cpu_info(); cpu = alloc_find_dev(cpu_bus, &cpu_path); cpu->path.apic.index = index; printk(BIOS_DEBUG, "Initializing CPU #%d\n", id); + cpu = info->cpu; + if (!cpu) { + die("CPU: missing cpu device structure"); + } +#else /* CONFIG_BROADCAST_SIPI */ +#endif /* CONFIG_BROADCAST_SIPI */ /* Find what type of cpu we are dealing with */ identify_cpu(cpu); @@ -284,8 +316,7 @@ void cpu_initialize(struct bus *cpu_bus, int index) cpu->ops->init(cpu); } - printk(BIOS_INFO, "CPU #%d initialized\n", id); + printk(BIOS_INFO, "CPU #%d ,lapic id %d, initialized\n", index, id); - return; } diff --git a/src/cpu/intel/hyperthreading/intel_sibling.c b/src/cpu/intel/hyperthreading/intel_sibling.c index 8377cd0..cabd3cc 100644 --- a/src/cpu/intel/hyperthreading/intel_sibling.c +++ b/src/cpu/intel/hyperthreading/intel_sibling.c @@ -7,13 +7,55 @@ #include <smp/spinlock.h> #include <assert.h> +#if CONFIG_BROADCAST_SIPI == 0 +#if !CONFIG_SERIAL_CPU_INIT +#error Intel hyper-threading requires serialized cpu init +#endif + +static int first_time = 1; +static int disable_siblings = !CONFIG_LOGICAL_CPUS; + +void intel_sibling_init(device_t cpu) +{ + unsigned int core_ids, apic_ids, threads; + + /* See if I am a sibling cpu */ + if (cpu->path.apic.apic_id & (siblings -1)) { + if (disable_siblings) { + cpu->enabled = 0; + } + return; + } + /* I am the primary cpu start up my siblings */ + for(i = 1; i < siblings; i++) { + struct device_path cpu_path; + device_t new; + /* Build the cpu device path */ + cpu_path.type = DEVICE_PATH_APIC; + cpu_path.apic.apic_id = cpu->path.apic.apic_id + i; + + /* Allocate new cpu device structure iff sibling CPU + * was not in static device tree. + */ + new = alloc_find_dev(cpu->bus, &cpu_path); + + if (!new) { + continue; + } + + printk(BIOS_DEBUG, "CPU: %u has sibling %u\n", + cpu->path.apic.apic_id, + new->path.apic.apic_id); + } +} + +#else /* CONFIG_BROADCAST_SIPI */ /* Return true if running thread does not have the smallest lapic ID * within a CPU core. */ int intel_ht_sibling(void) { unsigned int core_ids, apic_ids, threads; - apic_ids = 1; if (cpuid_eax(0) >= 1) apic_ids = (cpuid_ebx(1) >> 16) & 0xff; @@ -27,3 +69,5 @@ int intel_ht_sibling(void) threads = (apic_ids / core_ids); return !!(lapicid() & (threads-1)); } +#endif /* CONFIG_BROADCAST_SIPI */ + diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c index ddd1381..4a91b04 100644 --- a/src/cpu/intel/model_1067x/model_1067x_init.c +++ b/src/cpu/intel/model_1067x/model_1067x_init.c @@ -29,6 +29,10 @@ #include <cpu/x86/lapic.h> #include <cpu/intel/microcode.h> #include <cpu/intel/speedstep.h> + +#if CONFIG_BROADCAST_SIPI == 0 +#include <cpu/intel/hyperthreading.h> +#endif /* ! CONFIG_BROADCAST_SIPI */ #include <cpu/x86/cache.h> #include <cpu/x86/name.h> @@ -220,6 +224,12 @@ static void model_1067x_init(device_t cpu) /* PIC thermal sensor control */ configure_pic_thermal_sensors(); +#if CONFIG_BROADCAST_SIPI == 0 + + /* Start up my cpu siblings */ + intel_sibling_init(cpu); +#endif /* ! CONFIG_BROADCAST_SIPI */ + } static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_106cx/Kconfig b/src/cpu/intel/model_106cx/Kconfig index 2ef7392..00abf6b 100644 --- a/src/cpu/intel/model_106cx/Kconfig +++ b/src/cpu/intel/model_106cx/Kconfig @@ -11,4 +11,3 @@ config CPU_ADDR_BITS default 32 endif - diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c index 8d2ef3d..16660ac 100644 --- a/src/cpu/intel/model_106cx/model_106cx_init.c +++ b/src/cpu/intel/model_106cx/model_106cx_init.c @@ -27,6 +27,10 @@ #include <cpu/x86/lapic.h> #include <cpu/intel/microcode.h> #include <cpu/intel/speedstep.h> + +#if CONFIG_BROADCAST_SIPI == 0 +#include <cpu/intel/hyperthreading.h> +#endif /* ! CONFIG_BROADCAST_SIPI */ #include <cpu/x86/cache.h> #include <cpu/x86/name.h> #include <usbdebug.h> @@ -177,6 +181,11 @@ static void model_106cx_init(device_t cpu) configure_misc(); /* TODO: PIC thermal sensor control */ +#if CONFIG_BROADCAST_SIPI == 0 + + /* Start up my cpu siblings */ + intel_sibling_init(cpu); +#endif /* ! CONFIG_BROADCAST_SIPI */ } static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_206ax/acpi.c b/src/cpu/intel/model_206ax/acpi.c index dea23e7..1b5fa0a 100644 --- a/src/cpu/intel/model_206ax/acpi.c +++ b/src/cpu/intel/model_206ax/acpi.c @@ -26,7 +26,9 @@ #include <arch/acpigen.h> #include <arch/cpu.h> #include <cpu/x86/msr.h> +#if CONFIG_BROADCAST_SIPI == 1 #include <cpu/x86/lapic.h> +#endif /* CONFIG_BROADCAST_SIPI */ #include <cpu/intel/acpi.h> #include <cpu/intel/speedstep.h> #include <cpu/intel/turbo.h> @@ -89,8 +91,14 @@ static int generate_cstate_entries(acpi_cstate_t *cstates, static int generate_C_state_entries(void) { +#if CONFIG_BROADCAST_SIPI == 0 + struct cpu_info *info; +#endif /* ! CONFIG_BROADCAST_SIPI */ + struct cpu_driver *cpu; +#if CONFIG_BROADCAST_SIPI == 1 struct cpu_driver *cpu; struct device *cpu_dev; +#endif /* CONFIG_BROADCAST_SIPI */ int len, lenif; device_t lapic; struct cpu_intel_model_206ax_config *conf = NULL; @@ -104,10 +112,18 @@ static int generate_C_state_entries(void) return 0; /* Find CPU map of supported C-states */ +#if CONFIG_BROADCAST_SIPI == 0 + info = cpu_info(); + if (!info) + return 0; + cpu = find_cpu_driver(info->cpu); +#else /* CONFIG_BROADCAST_SIPI */ cpu_dev = dev_find_lapic(lapicid()); if (!cpu_dev) return 0; cpu = find_cpu_driver(cpu_dev); +#endif /* CONFIG_BROADCAST_SIPI */ + if (!cpu || !cpu->cstates) return 0; diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index d60c237..6e76d7f 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -414,6 +414,63 @@ static void configure_mca(void) static unsigned ehci_debug_addr; #endif +#if CONFIG_BROADCAST_SIPI == 0 +/* + * Initialize any extra cores/threads in this package. + */ +static void intel_cores_init(device_t cpu) +{ + struct cpuid_result result; + unsigned cores, threads, i; + + result = cpuid_ext(0xb, 0); /* Threads per core */ + threads = result.ebx & 0xff; + + result = cpuid_ext(0xb, 1); /* Cores per package */ + cores = result.ebx & 0xff; + + /* Only initialize extra cores from BSP */ + if (cpu->path.apic.apic_id) + return; + + printk(BIOS_DEBUG, "CPU: %u has %u cores %u threads\n", + cpu->path.apic.apic_id, cores, threads); + + for (i = 1; i < cores; ++i) { + struct device_path cpu_path; + device_t new; + + /* Build the cpu device path */ + cpu_path.type = DEVICE_PATH_APIC; + cpu_path.apic.apic_id = + cpu->path.apic.apic_id + i; + + /* Update APIC ID if no hyperthreading */ + if (threads == 1) + cpu_path.apic.apic_id <<= 1; + + /* Allocate the new cpu device structure */ + new = alloc_dev(cpu->bus, &cpu_path); + if (!new) + continue; + + printk(BIOS_DEBUG, "CPU: %u has core %u\n", + cpu->path.apic.apic_id, + new->path.apic.apic_id); + +#if CONFIG_SMP && CONFIG_MAX_CPUS > 1 + /* Start the new cpu */ + if (!start_cpu(new)) { + /* Record the error in cpu? */ + printk(BIOS_ERR, "CPU %u would not start!\n", + new->path.apic.apic_id); + } +#endif + } +} + +#endif /* ! CONFIG_BROADCAST_SIPI */ + static void model_206ax_init(device_t cpu) { char processor_name[49]; @@ -476,6 +533,13 @@ static void model_206ax_init(device_t cpu) /* Enable Turbo */ enable_turbo(); + +#if CONFIG_BROADCAST_SIPI == 0 + + /* Start up extra cores */ + intel_cores_init(cpu); +#endif /* ! CONFIG_BROADCAST_SIPI */ + } static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c index a0afd2e..989ca27 100644 --- a/src/cpu/intel/model_6ex/model_6ex_init.c +++ b/src/cpu/intel/model_6ex/model_6ex_init.c @@ -205,6 +205,11 @@ static void model_6ex_init(device_t cpu) /* PIC thermal sensor control */ configure_pic_thermal_sensors(); +#if CONFIG_BROADCAST_SIPI == 0 + + /* Start up my cpu siblings */ + intel_sibling_init(cpu); +#endif /* ! CONFIG_BROADCAST_SIPI */ } static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c index c5d7a6b..171059a 100644 --- a/src/cpu/intel/model_6fx/model_6fx_init.c +++ b/src/cpu/intel/model_6fx/model_6fx_init.c @@ -243,6 +243,12 @@ static void model_6fx_init(device_t cpu) /* PIC thermal sensor control */ configure_pic_thermal_sensors(); + +#if CONFIG_BROADCAST_SIPI == 0 + + /* Start up my cpu siblings */ + intel_sibling_init(cpu); +#endif /* ! CONFIG_BROADCAST_SIPI */ } static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_f2x/model_f2x_init.c b/src/cpu/intel/model_f2x/model_f2x_init.c index fa9e05f..87c3157 100644 --- a/src/cpu/intel/model_f2x/model_f2x_init.c +++ b/src/cpu/intel/model_f2x/model_f2x_init.c @@ -60,6 +60,12 @@ static void model_f2x_init(device_t cpu) /* Enable the local cpu apics */ setup_lapic(); + +#if CONFIG_BROADCAST_SIPI == 0 + + /* Start up my cpu siblings */ + intel_sibling_init(cpu); +#endif /* ! CONFIG_BROADCAST_SIPI */ }; static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_f3x/model_f3x_init.c b/src/cpu/intel/model_f3x/model_f3x_init.c index dd2a45f..96c38cd 100644 --- a/src/cpu/intel/model_f3x/model_f3x_init.c +++ b/src/cpu/intel/model_f3x/model_f3x_init.c @@ -43,6 +43,13 @@ static void model_f3x_init(device_t cpu) /* Enable the local cpu apics */ setup_lapic(); + +#if CONFIG_BROADCAST_SIPI == 0 + + /* Start up my cpu siblings */ + intel_sibling_init(cpu); +#endif /* ! CONFIG_BROADCAST_SIPI */ + }; static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_f4x/model_f4x_init.c b/src/cpu/intel/model_f4x/model_f4x_init.c index af7d9d2..cade95f 100644 --- a/src/cpu/intel/model_f4x/model_f4x_init.c +++ b/src/cpu/intel/model_f4x/model_f4x_init.c @@ -51,6 +51,13 @@ static void model_f4x_init(device_t cpu) /* Enable the local cpu apics */ setup_lapic(); + +#if CONFIG_BROADCAST_SIPI == 0 + + /* Start up my cpu siblings */ + intel_sibling_init(cpu); +#endif /* ! CONFIG_BROADCAST_SIPI */ + }; static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index b6dc560..b29340d 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -60,9 +60,27 @@ static void copy_secondary_start_to_1m_below(void) printk(BIOS_DEBUG, "start_eip=0x%08lx, code_size=0x%08lx\n", (long unsigned int)AP_SIPI_VECTOR, code_size); } -static struct bus *current_cpu_bus; +#ifdef __SSE3__ +static __inline__ __attribute__((always_inline)) unsigned long readcr4(void) +{ + unsigned long value; + __asm__ __volatile__ ( + "mov %%cr4, %[value]" + : [value] "=a" (value)); + return value; +} -static int lapic_start_cpus(struct bus *cpu_bus) +static __inline__ __attribute__((always_inline)) void + writecr4(unsigned long Data) +{ + __asm__ __volatile__ ( + "mov %%eax, %%cr4" + : + : "a" (Data) + ); +} +#if CONFIG_BROADCAST_SIPI == 0 +static int lapic_start_cpu(unsigned long apicid) { int timeout; unsigned long send_status, accept_status; @@ -187,26 +205,239 @@ static void stop_all_ap_cpus(void) mdelay(10); } -#ifdef __SSE3__ -static __inline__ __attribute__((always_inline)) unsigned long readcr4(void) + +/* C entry point of secondary cpus */ +void secondary_cpu_init(int index) { - unsigned long value; - __asm__ __volatile__ ( - "mov %%cr4, %[value]" - : [value] "=a" (value)); - return value; +#ifdef __SSE3__ + /* + * Seems that CR4 was cleared when AP start via lapic_start_cpu() + * Turn on CR4.OSFXSR and CR4.OSXMMEXCPT when SSE options enabled + */ + u32 cr4_val; + cr4_val = readcr4(); + cr4_val |= (1 << 9 | 1 << 10); + writecr4(cr4_val); +#endif + atomic_inc(&active_cpus); + cpu_initialize(current_cpu_bus, index); + atomic_dec(&active_cpus); } -static __inline__ __attribute__((always_inline)) void writecr4(unsigned long Data) +static void wait_other_cpus_stop(struct bus *cpu_bus) { - __asm__ __volatile__ ( - "mov %%eax, %%cr4" - : - : "a" (Data) - ); + device_t cpu; + int old_active_count, active_count; + long loopcount = 0; + + /* Now loop until the other cpus have finished initializing */ + old_active_count = 1; + active_count = atomic_read(&active_cpus); + while(active_count > 1) { + if (active_count != old_active_count) { + printk(BIOS_INFO, "Waiting for %d CPUS to stop\n", active_count - 1); + old_active_count = active_count; + } + udelay(10); + active_count = atomic_read(&active_cpus); + loopcount++; + } + for(cpu = cpu_bus->children; cpu; cpu = cpu->sibling) { + if (cpu->path.type != DEVICE_PATH_APIC) { + continue; + } + if (cpu->path.apic.apic_id == SPEEDSTEP_APIC_MAGIC) { + continue; + } + if (!cpu->initialized) { + printk(BIOS_ERR, "CPU 0x%02x did not initialize!\n", + cpu->path.apic.apic_id); + } + } + stop_all_ap_cpus(); + printk(BIOS_DEBUG, "All AP CPUs stopped (%ld loops)\n", loopcount); } + +#endif /* CONFIG_SMP */ + +void initialize_cpus(struct bus *cpu_bus) +{ + struct device_path cpu_path; + +#if NEED_LAPIC == 1 + /* Ensure the local apic is enabled */ + enable_lapic(); + + /* Get the device path of the boot cpu */ + cpu_path.type = DEVICE_PATH_APIC; + cpu_path.apic.apic_id = lapicid(); +#else + /* Get the device path of the boot cpu */ + cpu_path.type = DEVICE_PATH_CPU; + cpu_path.cpu.id = 0; +#endif + +#if CONFIG_SMP + copy_secondary_start_to_1m_below(); // why here? In case some day we can start core1 in amd_sibling_init +#endif + +#if CONFIG_HAVE_SMI_HANDLER + smm_init(); #endif + cpus_ready_for_init(); + + /* Initialize the bootstrap processor */ + cpu_initialize(cpu_bus, 0); + +#if CONFIG_SMP + lapic_start_cpus(cpu_bus); + /* Now wait the rest of the cpus stop*/ + wait_other_cpus_stop(cpu_bus); +#endif +} + +#else + +static struct bus *current_cpu_bus; + +static int lapic_start_cpus(struct bus *cpu_bus) +#if CONFIG_SMP && CONFIG_MAX_CPUS > 1 + +static struct bus *current_cpu_bus; + +static int lapic_start_cpus(struct bus *cpu_bus) +{ + int timeout; + unsigned long send_status, accept_status, start_eip; + int maxlvt; + + /* + * Starting actual IPI sequence... + */ + + current_cpu_bus = cpu_bus; + + printk(BIOS_SPEW, "Asserting INIT.\n"); + + /* Send INIT SIPI to target chip */ + lapic_write_around(LAPIC_ICR2, 0); + lapic_write_around(LAPIC_ICR, LAPIC_INT_ASSERT + | LAPIC_DM_INIT | LAPIC_DEST_ALLBUT); + + printk(BIOS_DEBUG, "Waiting for send to finish...\n"); + timeout = 0; + do { + printk(BIOS_SPEW, "+"); + udelay(100); + send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY; + } while (send_status && (timeout++ < 1000)); + if (timeout >= 1000) { + printk(BIOS_DEBUG, "First apic write timed out. Disabling\n"); + // too bad. + printk(BIOS_DEBUG, "ESR is 0x%lx\n", lapic_read(LAPIC_ESR)); + if (lapic_read(LAPIC_ESR)) { + printk(BIOS_DEBUG, "Try to reset ESR\n"); + lapic_write_around(LAPIC_ESR, 0); + printk(BIOS_DEBUG, "ESR is 0x%lx\n", lapic_read(LAPIC_ESR)); + } + return 0; + } + start_eip = get_valid_start_eip((unsigned long)_secondary_start); + + maxlvt = 4; + + printk(BIOS_SPEW, "Sending STARTUP.\n"); + lapic_read_around(LAPIC_SPIV); + lapic_write(LAPIC_ESR, 0); + lapic_read(LAPIC_ESR); + printk(BIOS_SPEW, "After apic_write.\n"); + + /* + * STARTUP IPI + */ + + /* Target chip */ + lapic_write_around(LAPIC_ICR2, 0); + printk(BIOS_SPEW, "After apic_write_around(LAPIC_ICR2, 0);\n"); + + /* Boot on the stack */ + /* Kick the second */ + lapic_write_around(LAPIC_ICR, + LAPIC_INT_ASSERT | LAPIC_DM_STARTUP | LAPIC_DEST_ALLBUT + | (start_eip >> 12)); + printk(BIOS_SPEW, "After apic_write_around allbut starteip %p.\n", + (void *)start_eip); + + /* + * Give the other CPU some time to accept the IPI. + */ + udelay(300); + + printk(BIOS_DEBUG, "Startup point 1.\n"); + + printk(BIOS_DEBUG, "Waiting for send to finish...\n"); + timeout = 0; + do { + printk(BIOS_DEBUG, "+"); + udelay(100); + send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY; + } while (send_status && (timeout++ < 1000)); + + /* + * Give the other CPU some time to accept the IPI. + */ + udelay(200); + /* + * Due to the Pentium erratum 3AP. + */ + if (maxlvt > 3) { + lapic_read_around(LAPIC_SPIV); + lapic_write(LAPIC_ESR, 0); + } + accept_status = (lapic_read(LAPIC_ESR) & 0xEF); + + printk(BIOS_DEBUG, "After Startup.\n"); + if (send_status) + printk(BIOS_WARNING, "APIC never delivered???\n"); + if (accept_status) + printk(BIOS_WARNING, "APIC delivery error (%lx).\n", + accept_status); + if (send_status || accept_status) + return 0; + return 1; +} + + +/* Number of cpus that are currently running in coreboot */ +static atomic_t active_cpus = ATOMIC_INIT(1); + +volatile unsigned long secondary_stack; +extern unsigned char _estack[]; + +static void stop_all_ap_cpus(void) +{ + unsigned long send_status; + int timeout; + /* send an LAPIC INIT to all but myself */ + lapic_write_around(LAPIC_ICR2, 0); + lapic_write_around(LAPIC_ICR, + LAPIC_INT_ASSERT | LAPIC_DM_INIT | LAPIC_DEST_ALLBUT); + + /* wait for the ipi send to finish */ + printk(BIOS_SPEW, "Waiting for send to finish...\n"); + timeout = 0; + do { + printk(BIOS_SPEW, "+"); + udelay(100); + send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY; + } while (send_status && (timeout++ < 1000)); + if (timeout >= 1000) { + printk(BIOS_ERR, "timed out\n"); + } + mdelay(10); +} + /* C entry point of secondary cpus */ void secondary_cpu_init(int index) { @@ -236,7 +467,8 @@ static void wait_other_cpus_stop(struct bus *cpu_bus) active_count = atomic_read(&active_cpus); while(active_count > 1) { if (active_count != old_active_count) { - printk(BIOS_INFO, "Waiting for %d CPUS to stop\n", active_count - 1); + printk(BIOS_INFO, "Waiting for %d CPUS to stop\n", + active_count - 1); old_active_count = active_count; } udelay(10); @@ -257,6 +489,23 @@ static void wait_other_cpus_stop(struct bus *cpu_bus) } stop_all_ap_cpus(); printk(BIOS_DEBUG, "All AP CPUs stopped (%ld loops)\n", loopcount); +#if 0 + for(i = 1; i <= last_cpu_index; i++){ + unsigned long *stack = stacks[i]; + int lowest; + int maxstack = (CONFIG_STACK_SIZE - sizeof(struct cpu_info)) + /sizeof(*stack) - 1; + if (stack[0] != 0xDEADBEEF) + printk(BIOS_ERR, "CPU%d overran its stack\n", i); + for(lowest = 0; lowest < maxstack; lowest++) + if (stack[lowest] != 0xDEADBEEF) + break; + printk(BIOS_SPEW, "CPU%d: stack allocated from %p to %p:", i, + stack, &stack[maxstack]); + printk(BIOS_SPEW, "lowest stack address was %p\n", + &stack[lowest]); + } +#endif } #endif /* CONFIG_SMP */ @@ -279,7 +528,8 @@ void initialize_cpus(struct bus *cpu_bus) #endif #if CONFIG_SMP - copy_secondary_start_to_1m_below(); // why here? In case some day we can start core1 in amd_sibling_init + // why here? In case some day we can start core1 in amd_sibling_init + copy_secondary_start_to_lowest_1M(); #endif #if CONFIG_HAVE_SMI_HANDLER @@ -297,4 +547,4 @@ void initialize_cpus(struct bus *cpu_bus) wait_other_cpus_stop(cpu_bus); #endif } - +#endif \ No newline at end of file diff --git a/src/cpu/x86/lapic/secondary.S b/src/cpu/x86/lapic/secondary.S index e6650ec..b56e378 100644 --- a/src/cpu/x86/lapic/secondary.S +++ b/src/cpu/x86/lapic/secondary.S @@ -2,7 +2,11 @@ #include <cpu/x86/lapic_def.h> .text - .globl _secondary_start, _secondary_start_end, cpucount, ap_protected_start + .globl _secondary_start, _secondary_start_end, ap_protected_start +#if CONFIG_BROADCAST_SIPI == 1 + .globl cpucount +#endif + .balign 4096 _secondary_start: .code16 cli @@ -49,6 +53,14 @@ __ap_protected_start: /* Load the Interrupt descriptor table */ lidt idtarg +#if CONFIG_BROADCAST_SIPI == 0 + /* Set the stack pointer, and flag that we are done */ + xorl %eax, %eax + movl secondary_stack, %esp + movl secondary_cpu_index, %edi + pushl %edi + movl %eax, secondary_stack +#else /* CONFIG_BROADCAST_SIPI */ /* increment our cpu index */ movl $1, %eax lock xadd %eax, cpucount @@ -61,10 +73,19 @@ __ap_protected_start: add %eax, %esp pushl %ecx +#endif /* CONFIG_BROADCAST_SIPI */ + call secondary_cpu_init 1: hlt jmp 1b +#if CONFIG_BROADCAST_SIPI == 1 cpucount: .long 1 +#endif /* CONFIG_BROADCAST_SIPI */ +gdtaddr: + .word gdt_limit /* the table limit */ + .long gdt /* we know the offset */ + +_secondary_start_end: .code32 diff --git a/src/cpu/x86/pae/pgtbl.c b/src/cpu/x86/pae/pgtbl.c index 7aa17c2..f84ec6e 100644 --- a/src/cpu/x86/pae/pgtbl.c +++ b/src/cpu/x86/pae/pgtbl.c @@ -7,6 +7,15 @@ #include <cpu/cpu.h> #include <cpu/x86/pae.h> #include <cpu/x86/lapic.h> + +#if CONFIG_BROADCAST_SIPI == 1 +#include <device/device.h> +#endif /* CONFIG_BROADCAST_SIPI */ +#include <cpu/cpu.h> +#include <cpu/x86/pae.h> +#if CONFIG_BROADCAST_SIPI == 1 +#include <cpu/x86/lapic.h> +#endif /* CONFIG_BROADCAST_SIPI */ #include <string.h> static void paging_off(void) @@ -45,6 +54,7 @@ static void paging_on(void *pdp) ); } +#if CONFIG_BROADCAST_SIPI == 1 static int cpu_index(void) { device_t dev = dev_find_lapic(lapicid()); @@ -53,6 +63,7 @@ static int cpu_index(void) return dev->path.apic.index; } +#endif /* CONFIG_BROADCAST_SIPI */ void *map_2M_page(unsigned long page) { struct pde { diff --git a/src/drivers/i2c/w83795/w83795.c b/src/drivers/i2c/w83795/w83795.c index 12be4da..14b12b3 100644 --- a/src/drivers/i2c/w83795/w83795.c +++ b/src/drivers/i2c/w83795/w83795.c @@ -22,7 +22,9 @@ #include <console/console.h> #include <device/device.h> #include "southbridge/amd/cimx/sb700/smbus.h" /*SMBUS_IO_BASE*/ +#if CONFIG_BROADCAST_SIPI == 1 #include <cpu/x86/lapic.h> +#endif /* CONFIG_BROADCAST_SIPI */ #include "w83795.h" static u32 w83795_set_bank(u8 bank) @@ -225,8 +227,13 @@ static void w83795_init(w83795_fan_mode_t mode, u8 dts_src) static void w83795_hwm_init(device_t dev) { struct device *cpu; - +#if CONFIG_BROADCAST_SIPI == 0 + struct cpu_info *info; + info = cpu_info(); + cpu = info->cpu; +#else /* CONFIG_BROADCAST_SIPI */ cpu = dev_find_lapic(lapicid()); +#endif /* CONFIG_BROADCAST_SIPI */ if (!cpu) die("CPU: missing cpu device structure"); diff --git a/src/include/cpu/cpu.h b/src/include/cpu/cpu.h index 9765dfd..0bf85d6 100644 --- a/src/include/cpu/cpu.h +++ b/src/include/cpu/cpu.h @@ -4,12 +4,18 @@ #include <arch/cpu.h> #if !defined(__ROMCC__) + +#if CONFIG_BROADCAST_SIPI == 0 +void secondary_cpu_init(unsigned int cpu_index)__attribute__((regparm(0))); +void cpu_initialize(unsigned int cpu_index); +#else /* CONFIG_BROADCAST_SIPI */ +void secondary_cpu_init(int index); +extern unsigned int cpucount; void cpu_initialize(struct bus *cpu_bus, int index); +#endif /* CONFIG_BROADCAST_SIPI */ + struct bus; void initialize_cpus(struct bus *cpu_bus); -void secondary_cpu_init(int index); - -extern unsigned int cpucount; #if !CONFIG_WAIT_BEFORE_CPUS_INIT #define cpus_ready_for_init() do {} while(0)

1 0

Patch set updated for coreboot: 7abfd04 AMD CPUs: Updated CPU list in powernow_acpi.c
by Jukka Rantala 20 Jul '12

20 Jul '12

Jukka Rantala (jukka.rantala(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1244 -gerrit commit 7abfd04cf614e9edd79929478d5fb6e365c04bbf Author: Jukka Rantala <jukka.rantala(a)gmail.com> Date: Fri Jul 20 02:10:16 2012 +0300 AMD CPUs: Updated CPU list in powernow_acpi.c Updated P state table to make frequency scaling work. Added these CPUs: http://support.amd.com/us/Processor_TechDocs/30430.pdf Also wrote a Python script for parsing AMD docs, but not sure where to put it: http://pastebin.com/1dSvkXwc Change-Id: I8f08111b73b9be551f3f59d2acb15051ccf36c1e Signed-off-by: Jukka Rantala <jukka.rantala(a)gmail.com> --- src/cpu/amd/model_fxx/powernow_acpi.c | 176 ++++++++++++++++++++++++++++++++- 1 files changed, 171 insertions(+), 5 deletions(-) diff --git a/src/cpu/amd/model_fxx/powernow_acpi.c b/src/cpu/amd/model_fxx/powernow_acpi.c index 81b1067..2a6e025 100644 --- a/src/cpu/amd/model_fxx/powernow_acpi.c +++ b/src/cpu/amd/model_fxx/powernow_acpi.c @@ -561,23 +561,189 @@ struct cpuentry entr[] = { {180, 0x2c, 0x20f32, 0x10, 0x10, 1100, {{2200, 1300, 1056}, {2000, 1250, 891}, {1800, 1200, 748}, {1000, 1100, 466}}}, - {3000, 0x4, 0x10ff0, 0xa, 0xa, 670, - {{1000, 1100, 210}}}, /* AMA3000BEX5AR */ {3000, 0x4, 0xf4a, 0xa, 0x0, 815, {{1600, 1400, 570}, {800, 1100, 190}}}, /* TMDML34BKX5LD, needs real TDP info */ {34, 0xa, 0x20f42, 0xa, 0x0, 350, {{1600, 1400, 340}, {800, 1000, 330}}}, + /* ADA3200AIO4BX */ + {3200, 0x4, 0x20fc2, 0xe, 0xe, 670, + {{2000, 1350, 647}, {1800, 1300, 548}, {1000, 1100, 275}}}, + /* ADA2800AEP4AP */ + {2800, 0x4, 0xf48, 0xa, 0xa, 890, + {{800, 1300, 350}}}, + /* ADA3000AEP4AP */ + {3000, 0x4, 0xf48, 0xc, 0xc, 890, + {{1800, 1400, 660}, {800, 1300, 350}}}, + /* ADA3200AEP5AP */ + {3200, 0x4, 0xf48, 0xc, 0xc, 890, + {{1800, 1400, 660}, {800, 1300, 350}}}, + /* ADA3400AEP5AP */ + {3400, 0x4, 0xf48, 0xe, 0xe, 890, + {{2000, 1400, 700}, {800, 1300, 350}}}, + /* ADA2800AEP4AR */ + {2800, 0x4, 0xf4a, 0xa, 0xa, 890, + {{1000, 1100, 220}}}, + /* ADA3000AEP4AR */ + {3000, 0x4, 0xf4a, 0xc, 0xc, 890, + {{1800, 1400, 660}, {1000, 1100, 220}}}, + /* ADA3700AEP5AR */ + {3700, 0x4, 0xf4a, 0x10, 0x10, 890, + {{2200, 1400, 720}, {2000, 1300, 530}, {1800, 1200, 390}, {1000, 1100, 220}}}, + /* ADA2800AEP4AX */ + {2800, 0x4, 0xfc0, 0xa, 0xa, 890, + {{1000, 1100, 220}}}, + /* ADA3000AEP4AX */ + {3000, 0x4, 0xfc0, 0xc, 0xc, 890, + {{1800, 1400, 670}, {1000, 1100, 220}}}, + /* ADA3200AEP4AX */ + {3200, 0x4, 0xfc0, 0xe, 0xe, 890, + {{2000, 1400, 690}, {1800, 1300, 500}, {1000, 1100, 220}}}, + /* ADA3400AEP4AX */ + {3400, 0x4, 0xfc0, 0x10, 0x10, 890, + {{2200, 1400, 720}, {2000, 1300, 530}, {1800, 1200, 390}, {1000, 1100, 220}}}, + /* ADA3500DEP4AS */ + {3500, 0x4, 0xf7a, 0xe, 0xe, 890, + {{2000, 1400, 690}, {1800, 1300, 500}, {1000, 1100, 220}}}, + /* ADA3500DEP4AW */ + {3500, 0x4, 0xff0, 0xe, 0xe, 890, + {{2000, 1400, 690}, {1800, 1300, 500}, {1000, 1100, 220}}}, + /* ADA3800DEP4AW */ + {3800, 0x4, 0xff0, 0x10, 0x10, 890, + {{2200, 1400, 720}, {2000, 1300, 530}, {1800, 1200, 390}, {1000, 1100, 220}}}, + /* ADA4000DEP5AS */ + {4000, 0x4, 0xf7a, 0x10, 0x10, 890, + {{2200, 1400, 720}, {2000, 1300, 530}, {1800, 1200, 390}, {1000, 1100, 220}}}, + /* ADA3500DAA4BN */ + {3500, 0x4, 0x20f71, 0xe, 0xe, 670, + {{2000, 1350, 647}, {1800, 1300, 548}, {1000, 1100, 275}}}, + /* ADA3700DAA5BN */ + {3700, 0x4, 0x20f71, 0xe, 0xe, 853, + {{2000, 1350, 830}, {1800, 1300, 704}, {1000, 1100, 361}}}, + /* ADA4000DAA5BN */ + {4000, 0x4, 0x20f71, 0x10, 0x10, 853, + {{2200, 1350, 830}, {2000, 1300, 706}, {1800, 1250, 596}, {1000, 1100, 350}}}, + /* ADA3700DKA5CF */ + {3700, 0x4, 0x30f72, 0xe, 0xe, 853, + {{2000, 1350, 830}, {1800, 1300, 704}, {1000, 1100, 361}}}, + /* ADA4000DKA5CF */ + {4000, 0x4, 0x30f72, 0x10, 0x10, 853, + {{2200, 1350, 830}, {2000, 1300, 706}, {1800, 1250, 596}, {1000, 1100, 350}}}, + /* ADA3800DAA4BP */ + {3800, 0x4, 0x20ff0, 0x10, 0x10, 853, + {{2200, 1350, 830}, {2000, 1300, 706}, {1800, 1250, 596}, {1000, 1100, 350}}}, + /* ADA3000DIK4BI */ + {3000, 0x4, 0x10ff0, 0xa, 0xa, 670, + {{1000, 1100, 210}}}, + /* ADA3200DIK4BI */ + {3200, 0x4, 0x10ff0, 0xc, 0xc, 670, + {{1800, 1350, 560}, {1000, 1100, 210}}}, + /* ADA3500DIK4BI */ + {3500, 0x4, 0x10ff0, 0xe, 0xe, 670, + {{2000, 1350, 560}, {1800, 1300, 460}, {1000, 1100, 200}}}, + /* ADA3000DAA4BP */ + {3000, 0x4, 0x20ff0, 0xa, 0xa, 670, + {{1000, 1100, 296}}}, + /* ADA3200DAA4BP */ + {3200, 0x4, 0x20ff0, 0xc, 0xc, 670, + {{1800, 1350, 647}, {1000, 1100, 286}}}, + /* ADA3500DAA4BP */ + {3500, 0x4, 0x20ff0, 0xe, 0xe, 670, + {{2000, 1350, 647}, {1800, 1300, 548}, {1000, 1100, 275}}}, + /* ADA3000DAA4BW */ + {3000, 0x4, 0x20ff2, 0xa, 0xa, 670, + {{1000, 1100, 296}}}, + /* ADA3200DAA4BW */ + {3200, 0x4, 0x20ff2, 0xc, 0xc, 670, + {{1800, 1350, 647}, {1000, 1100, 286}}}, + /* ADA3500DAA4BW */ + {3500, 0x4, 0x20ff2, 0xe, 0xe, 670, + {{2000, 1350, 647}, {1800, 1300, 548}, {1000, 1100, 275}}}, + /* ADA3200DKA4CG */ + {3200, 0x4, 0x30ff2, 0xc, 0xc, 670, + {{1800, 1350, 647}, {1000, 1100, 286}}}, + /* ADA3800DAA4BW */ + {3800, 0x4, 0x20ff2, 0x10, 0x10, 853, + {{2200, 1350, 830}, {2000, 1300, 706}, {1800, 1250, 596}, {1000, 1100, 350}}}, + /* ADA3000AIK4BX */ + {3000, 0x4, 0x20fc2, 0xc, 0xc, 510, + {{1800, 1350, 428}, {1000, 1100, 189}}}, + /* ADAFX53DEP5AS */ + {53, 0x24, 0xf7a, 0x2a, 0x10, 890, + {{1200, 1100, 250}}}, + /* ADAFX55DEI5AS */ + {55, 0x24, 0xf7a, 0x2a, 0x12, 1040, + {{1200, 1100, 250}}}, + /* ADAFX55DAA5BN */ + {55, 0x24, 0x20f71, 0x2a, 0x12, 1040, + {{1200, 1100, 422}}}, + /* ADAFX57DAA5BN */ + {57, 0x24, 0x20f71, 0x2a, 0x14, 1040, + {{1200, 1100, 434}}}, + /* SDA3100AIP3AX */ + {3100, 0x22, 0xfc0, 0xa, 0xa, 620, + {{1000, 1100, 200}}}, + /* SDA2600AIO2BA */ + {2600, 0x22, 0x10fc0, 0x8, 0x8, 590, + {}}, + /* SDA2800AIO3BA */ + {2800, 0x22, 0x10fc0, 0x8, 0x8, 590, + {}}, + /* SDA3000AIO2BA */ + {3000, 0x22, 0x10fc0, 0xa, 0xa, 590, + {{1000, 1100, 190}}}, + /* SDA3100AIO3BA */ + {3100, 0x22, 0x10fc0, 0xa, 0xa, 590, + {{1000, 1100, 190}}}, + /* SDA3300AIO2BA */ + {3300, 0x22, 0x10fc0, 0xc, 0xc, 590, + {{1800, 1350, 488}, {1000, 1100, 180}}}, + /* SDA2500AIO3BX */ + {2500, 0x26, 0x20fc2, 0x6, 0x6, 590, + {}}, + /* SDA2600AIO2BX */ + {2600, 0x26, 0x20fc2, 0x8, 0x8, 590, + {}}, + /* SDA2800AIO3BX */ + {2800, 0x26, 0x20fc2, 0x8, 0x8, 590, + {}}, + /* SDA3000AIO2BX */ + {3000, 0x26, 0x20fc2, 0xa, 0xa, 590, + {{1000, 1100, 217}}}, /* SDA3100AIO3BX */ {3100, 0x26, 0x20fc2, 0xa, 0xa, 590, {{1000, 1100, 217}}}, + /* SDA3300AIO2BX */ + {3300, 0x26, 0x20fc2, 0xc, 0xc, 590, + {{1800, 1350, 496}, {1000, 1100, 207}}}, /* SDA3400AIO3BX */ {3400, 0x26, 0x20fc2, 0xc, 0xc, 590, {{1800, 1350, 496}, {1000, 1100, 207}}}, - /* ADA3200AIO4BX */ - {3200, 0x4, 0x20fc2, 0xe, 0xe, 670, - {{2000, 1350, 647}, {1800, 1300, 548}, {1000, 1100, 275}}}, + /* TMSMT32BQX4LD */ + {32, 0xb, 0x20f42, 0xa, 0x0, 240, + {{1600, 1150, 199}, {800, 900, 77}}}, + /* TMSMT34BQX5LD */ + {34, 0xb, 0x20f42, 0xa, 0x0, 240, + {{1600, 1150, 199}, {800, 900, 79}}}, + /* TMSMT37BQX5LD */ + {37, 0xb, 0x20f42, 0xc, 0x0, 250, + {{1800, 1150, 209}, {1600, 1100, 175}, {800, 900, 79}}}, + /* ADA4400DAA6CD */ + {4400, 0x5, 0x20f32, 0xe, 0xe, 1100, + {{2000, 1300, 1056}, {1800, 1250, 891}, {1000, 1100, 490}}}, + /* ADA4800DAA6CD */ + {4800, 0x5, 0x20f32, 0x10, 0x10, 1100, + {{2200, 1300, 1056}, {2000, 1250, 891}, {1800, 1200, 748}, {1000, 1100, 466}}}, + /* ADA3800DAA5BV */ + {3800, 0x5, 0x20fb1, 0xc, 0xc, 890, + {{1800, 1300, 846}, {1000, 1100, 401}}}, + /* ADA4200DAA5BV */ + {4200, 0x5, 0x20fb1, 0xe, 0xe, 890, + {{2000, 1300, 846}, {1800, 1250, 709}, {1000, 1100, 376}}}, + /* ADA4600DAA5BV */ + {4600, 0x5, 0x20fb1, 0x10, 0x10, 1100, + {{2200, 1300, 1056}, {2000, 1250, 891}, {1800, 1200, 748}, {1000, 1100, 466}}}, }; static int pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)

1 0

New patch to review for coreboot: 19c16ed Simplify VGA card discovery
by Patrick Georgi 20 Jul '12

20 Jul '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1255 -gerrit commit 19c16edf950bd34d28ae06413bdcc31c75cfa821 Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Fri Jul 20 12:16:17 2012 +0200 Simplify VGA card discovery We were handling vga, vga_first, vga_last, vga_onboard just to determine an onboard chip and the first plugin card. We were also traversing the devices manually instead of using the utility functions we have, for the chance that there are non-VGA cards we need to cope with (but why would they require VGA-style handling?) Change-Id: I8aa73aefa102725a64287f78a59de3d5dda1c7f2 Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> --- src/devices/device.c | 43 +++++++++++++------------------------------ 1 files changed, 13 insertions(+), 30 deletions(-) diff --git a/src/devices/device.c b/src/devices/device.c index de27e88..9753de8 100644 --- a/src/devices/device.c +++ b/src/devices/device.c @@ -715,52 +715,35 @@ static void set_vga_bridge_bits(void) */ /* FIXME: Handle the VGA palette snooping. */ - struct device *dev, *vga, *vga_onboard, *vga_first, *vga_last; + struct device *dev, *vga, *vga_onboard; struct bus *bus; bus = 0; vga = 0; vga_onboard = 0; - vga_first = 0; - vga_last = 0; - - for (dev = all_devices; dev; dev = dev->next) { + dev = NULL; + while ((dev = dev_find_class(PCI_CLASS_DISPLAY_VGA << 8, dev))) { if (!dev->enabled) continue; - if (((dev->class >> 16) == PCI_BASE_CLASS_DISPLAY) && - ((dev->class >> 8) != PCI_CLASS_DISPLAY_OTHER)) { - if (!vga_first) { - if (dev->on_mainboard) - vga_onboard = dev; - else - vga_first = dev; - } else { - if (dev->on_mainboard) - vga_onboard = dev; - else - vga_last = dev; - } + printk(BIOS_DEBUG, "found VGA at %s\n", dev_path(dev)); - /* It isn't safe to enable other VGA cards. */ - dev->command &= ~(PCI_COMMAND_MEMORY | PCI_COMMAND_IO); + if (dev->on_mainboard) { + vga_onboard = dev; + } else if (!vga) { + vga = dev; } - } - vga = vga_last; + /* It isn't safe to enable all VGA cards. */ + dev->command &= ~(PCI_COMMAND_MEMORY | PCI_COMMAND_IO); + }; if (!vga) - vga = vga_first; + vga = vga_onboard; -#if CONFIG_ONBOARD_VGA_IS_PRIMARY - if (vga_onboard) /* Will use onboard VGA as primary. */ -#else - if (!vga) /* Will use last add-on adapter as primary. */ -#endif - { + if (CONFIG_ONBOARD_VGA_IS_PRIMARY && vga_onboard) vga = vga_onboard; - } /* If we prefer plugin VGA over chipset VGA, the chipset might want to know. */

1 0

New patch to review for coreboot: 11d98bb Fix udelay() implementation for i945 romstage
by Patrick Georgi 20 Jul '12

20 Jul '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1254 -gerrit commit 11d98bbd78ba811d961b11033240521a6f9ffb68 Author: Nico Huber <nico.huber(a)secunet.com> Date: Thu Jul 19 16:16:59 2012 +0200 Fix udelay() implementation for i945 romstage Work around 32-bit overflow with 64-bit multiplication. Calculate correct CPU frequency. Change-Id: I86d78f2d70b9f9c62fd4e1e0d765e92e4de83f67 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- src/northbridge/intel/i945/udelay.c | 18 ++++++++++++++---- 1 files changed, 14 insertions(+), 4 deletions(-) diff --git a/src/northbridge/intel/i945/udelay.c b/src/northbridge/intel/i945/udelay.c index 9170335..ce5e9d8 100644 --- a/src/northbridge/intel/i945/udelay.c +++ b/src/northbridge/intel/i945/udelay.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007-2008 coresystems GmbH + * 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -22,6 +23,17 @@ #include <cpu/x86/tsc.h> #include <cpu/x86/msr.h> +/* Simple 32- to 64-bit multiplication. Uses 16-bit words to avoid overflow. */ +static inline void multiply_to_tsc(tsc_t *const tsc, const u32 a, const u32 b) +{ + tsc->lo = (a & 0xffff) * (b & 0xffff); + tsc->hi = ((tsc->lo >> 16) + + ((a & 0xffff) * (b >> 16)) + + ((b & 0xffff) * (a >> 16))); + tsc->lo = ((tsc->hi & 0xffff) << 16) | (tsc->lo & 0xffff); + tsc->hi = ((a >> 16) * (b >> 16)) + (tsc->hi >> 16); +} + /** * Intel Core(tm) cpus always run the TSC at the maximum possible CPU clock */ @@ -33,7 +45,6 @@ void udelay(u32 us) msr_t msr; u32 fsb = 0, divisor; u32 d; /* ticks per us */ - u32 dn = 0x1000000 / 2; /* how many us before we need to use hi */ msr = rdmsr(0xcd); switch (msr.lo & 0x07) { @@ -63,10 +74,9 @@ void udelay(u32 us) msr = rdmsr(0x198); divisor = (msr.hi >> 8) & 0x1f; - d = fsb * divisor; + d = (fsb * divisor) / 4; /* CPU clock is always a quarter. */ - tscd.hi = us / dn; - tscd.lo = (us - tscd.hi * dn) * d; + multiply_to_tsc(&tscd, us, d); tsc1 = rdtsc(); dword = tsc1.lo + tscd.lo;

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New patch to review for coreboot: 9d6f00a AMD CPUs: Cleaned up white space in powernow_acpi.c
by Jukka Rantala 20 Jul '12

20 Jul '12

Jukka Rantala (jukka.rantala(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1253 -gerrit commit 9d6f00a1282adff285727b4de061c8cc0aaad4d2 Author: Jukka Rantala <jukka.rantala(a)gmail.com> Date: Fri Jul 20 14:59:34 2012 +0300 AMD CPUs: Cleaned up white space in powernow_acpi.c Cleaned up white space in powernow_acpi.c cpu table. Change-Id: I9dea19ce529dad56b54f5bc2a1d114c320673818 Signed-off-by: Jukka Rantala <jukka.rantala(a)gmail.com> --- src/cpu/amd/model_fxx/powernow_acpi.c | 232 ++++++++++++++++---------------- 1 files changed, 116 insertions(+), 116 deletions(-) diff --git a/src/cpu/amd/model_fxx/powernow_acpi.c b/src/cpu/amd/model_fxx/powernow_acpi.c index dec790c..2a6e025 100644 --- a/src/cpu/amd/model_fxx/powernow_acpi.c +++ b/src/cpu/amd/model_fxx/powernow_acpi.c @@ -570,179 +570,179 @@ struct cpuentry entr[] = { /* ADA3200AIO4BX */ {3200, 0x4, 0x20fc2, 0xe, 0xe, 670, {{2000, 1350, 647}, {1800, 1300, 548}, {1000, 1100, 275}}}, - /* ADA2800AEP4AP */ - {2800, 0x4, 0xf48, 0xa, 0xa, 890, + /* ADA2800AEP4AP */ + {2800, 0x4, 0xf48, 0xa, 0xa, 890, {{800, 1300, 350}}}, - /* ADA3000AEP4AP */ - {3000, 0x4, 0xf48, 0xc, 0xc, 890, + /* ADA3000AEP4AP */ + {3000, 0x4, 0xf48, 0xc, 0xc, 890, {{1800, 1400, 660}, {800, 1300, 350}}}, - /* ADA3200AEP5AP */ - {3200, 0x4, 0xf48, 0xc, 0xc, 890, + /* ADA3200AEP5AP */ + {3200, 0x4, 0xf48, 0xc, 0xc, 890, {{1800, 1400, 660}, {800, 1300, 350}}}, - /* ADA3400AEP5AP */ - {3400, 0x4, 0xf48, 0xe, 0xe, 890, + /* ADA3400AEP5AP */ + {3400, 0x4, 0xf48, 0xe, 0xe, 890, {{2000, 1400, 700}, {800, 1300, 350}}}, - /* ADA2800AEP4AR */ - {2800, 0x4, 0xf4a, 0xa, 0xa, 890, + /* ADA2800AEP4AR */ + {2800, 0x4, 0xf4a, 0xa, 0xa, 890, {{1000, 1100, 220}}}, - /* ADA3000AEP4AR */ - {3000, 0x4, 0xf4a, 0xc, 0xc, 890, + /* ADA3000AEP4AR */ + {3000, 0x4, 0xf4a, 0xc, 0xc, 890, {{1800, 1400, 660}, {1000, 1100, 220}}}, - /* ADA3700AEP5AR */ - {3700, 0x4, 0xf4a, 0x10, 0x10, 890, + /* ADA3700AEP5AR */ + {3700, 0x4, 0xf4a, 0x10, 0x10, 890, {{2200, 1400, 720}, {2000, 1300, 530}, {1800, 1200, 390}, {1000, 1100, 220}}}, - /* ADA2800AEP4AX */ - {2800, 0x4, 0xfc0, 0xa, 0xa, 890, + /* ADA2800AEP4AX */ + {2800, 0x4, 0xfc0, 0xa, 0xa, 890, {{1000, 1100, 220}}}, - /* ADA3000AEP4AX */ - {3000, 0x4, 0xfc0, 0xc, 0xc, 890, + /* ADA3000AEP4AX */ + {3000, 0x4, 0xfc0, 0xc, 0xc, 890, {{1800, 1400, 670}, {1000, 1100, 220}}}, - /* ADA3200AEP4AX */ - {3200, 0x4, 0xfc0, 0xe, 0xe, 890, + /* ADA3200AEP4AX */ + {3200, 0x4, 0xfc0, 0xe, 0xe, 890, {{2000, 1400, 690}, {1800, 1300, 500}, {1000, 1100, 220}}}, - /* ADA3400AEP4AX */ - {3400, 0x4, 0xfc0, 0x10, 0x10, 890, + /* ADA3400AEP4AX */ + {3400, 0x4, 0xfc0, 0x10, 0x10, 890, {{2200, 1400, 720}, {2000, 1300, 530}, {1800, 1200, 390}, {1000, 1100, 220}}}, - /* ADA3500DEP4AS */ - {3500, 0x4, 0xf7a, 0xe, 0xe, 890, + /* ADA3500DEP4AS */ + {3500, 0x4, 0xf7a, 0xe, 0xe, 890, {{2000, 1400, 690}, {1800, 1300, 500}, {1000, 1100, 220}}}, - /* ADA3500DEP4AW */ - {3500, 0x4, 0xff0, 0xe, 0xe, 890, + /* ADA3500DEP4AW */ + {3500, 0x4, 0xff0, 0xe, 0xe, 890, {{2000, 1400, 690}, {1800, 1300, 500}, {1000, 1100, 220}}}, - /* ADA3800DEP4AW */ - {3800, 0x4, 0xff0, 0x10, 0x10, 890, + /* ADA3800DEP4AW */ + {3800, 0x4, 0xff0, 0x10, 0x10, 890, {{2200, 1400, 720}, {2000, 1300, 530}, {1800, 1200, 390}, {1000, 1100, 220}}}, - /* ADA4000DEP5AS */ - {4000, 0x4, 0xf7a, 0x10, 0x10, 890, + /* ADA4000DEP5AS */ + {4000, 0x4, 0xf7a, 0x10, 0x10, 890, {{2200, 1400, 720}, {2000, 1300, 530}, {1800, 1200, 390}, {1000, 1100, 220}}}, - /* ADA3500DAA4BN */ - {3500, 0x4, 0x20f71, 0xe, 0xe, 670, + /* ADA3500DAA4BN */ + {3500, 0x4, 0x20f71, 0xe, 0xe, 670, {{2000, 1350, 647}, {1800, 1300, 548}, {1000, 1100, 275}}}, - /* ADA3700DAA5BN */ - {3700, 0x4, 0x20f71, 0xe, 0xe, 853, + /* ADA3700DAA5BN */ + {3700, 0x4, 0x20f71, 0xe, 0xe, 853, {{2000, 1350, 830}, {1800, 1300, 704}, {1000, 1100, 361}}}, - /* ADA4000DAA5BN */ - {4000, 0x4, 0x20f71, 0x10, 0x10, 853, + /* ADA4000DAA5BN */ + {4000, 0x4, 0x20f71, 0x10, 0x10, 853, {{2200, 1350, 830}, {2000, 1300, 706}, {1800, 1250, 596}, {1000, 1100, 350}}}, - /* ADA3700DKA5CF */ - {3700, 0x4, 0x30f72, 0xe, 0xe, 853, + /* ADA3700DKA5CF */ + {3700, 0x4, 0x30f72, 0xe, 0xe, 853, {{2000, 1350, 830}, {1800, 1300, 704}, {1000, 1100, 361}}}, - /* ADA4000DKA5CF */ - {4000, 0x4, 0x30f72, 0x10, 0x10, 853, + /* ADA4000DKA5CF */ + {4000, 0x4, 0x30f72, 0x10, 0x10, 853, {{2200, 1350, 830}, {2000, 1300, 706}, {1800, 1250, 596}, {1000, 1100, 350}}}, - /* ADA3800DAA4BP */ - {3800, 0x4, 0x20ff0, 0x10, 0x10, 853, + /* ADA3800DAA4BP */ + {3800, 0x4, 0x20ff0, 0x10, 0x10, 853, {{2200, 1350, 830}, {2000, 1300, 706}, {1800, 1250, 596}, {1000, 1100, 350}}}, - /* ADA3000DIK4BI */ - {3000, 0x4, 0x10ff0, 0xa, 0xa, 670, + /* ADA3000DIK4BI */ + {3000, 0x4, 0x10ff0, 0xa, 0xa, 670, {{1000, 1100, 210}}}, - /* ADA3200DIK4BI */ - {3200, 0x4, 0x10ff0, 0xc, 0xc, 670, + /* ADA3200DIK4BI */ + {3200, 0x4, 0x10ff0, 0xc, 0xc, 670, {{1800, 1350, 560}, {1000, 1100, 210}}}, - /* ADA3500DIK4BI */ - {3500, 0x4, 0x10ff0, 0xe, 0xe, 670, + /* ADA3500DIK4BI */ + {3500, 0x4, 0x10ff0, 0xe, 0xe, 670, {{2000, 1350, 560}, {1800, 1300, 460}, {1000, 1100, 200}}}, - /* ADA3000DAA4BP */ - {3000, 0x4, 0x20ff0, 0xa, 0xa, 670, + /* ADA3000DAA4BP */ + {3000, 0x4, 0x20ff0, 0xa, 0xa, 670, {{1000, 1100, 296}}}, - /* ADA3200DAA4BP */ - {3200, 0x4, 0x20ff0, 0xc, 0xc, 670, + /* ADA3200DAA4BP */ + {3200, 0x4, 0x20ff0, 0xc, 0xc, 670, {{1800, 1350, 647}, {1000, 1100, 286}}}, - /* ADA3500DAA4BP */ - {3500, 0x4, 0x20ff0, 0xe, 0xe, 670, + /* ADA3500DAA4BP */ + {3500, 0x4, 0x20ff0, 0xe, 0xe, 670, {{2000, 1350, 647}, {1800, 1300, 548}, {1000, 1100, 275}}}, - /* ADA3000DAA4BW */ - {3000, 0x4, 0x20ff2, 0xa, 0xa, 670, + /* ADA3000DAA4BW */ + {3000, 0x4, 0x20ff2, 0xa, 0xa, 670, {{1000, 1100, 296}}}, - /* ADA3200DAA4BW */ - {3200, 0x4, 0x20ff2, 0xc, 0xc, 670, + /* ADA3200DAA4BW */ + {3200, 0x4, 0x20ff2, 0xc, 0xc, 670, {{1800, 1350, 647}, {1000, 1100, 286}}}, - /* ADA3500DAA4BW */ - {3500, 0x4, 0x20ff2, 0xe, 0xe, 670, + /* ADA3500DAA4BW */ + {3500, 0x4, 0x20ff2, 0xe, 0xe, 670, {{2000, 1350, 647}, {1800, 1300, 548}, {1000, 1100, 275}}}, - /* ADA3200DKA4CG */ - {3200, 0x4, 0x30ff2, 0xc, 0xc, 670, + /* ADA3200DKA4CG */ + {3200, 0x4, 0x30ff2, 0xc, 0xc, 670, {{1800, 1350, 647}, {1000, 1100, 286}}}, - /* ADA3800DAA4BW */ - {3800, 0x4, 0x20ff2, 0x10, 0x10, 853, + /* ADA3800DAA4BW */ + {3800, 0x4, 0x20ff2, 0x10, 0x10, 853, {{2200, 1350, 830}, {2000, 1300, 706}, {1800, 1250, 596}, {1000, 1100, 350}}}, - /* ADA3000AIK4BX */ - {3000, 0x4, 0x20fc2, 0xc, 0xc, 510, + /* ADA3000AIK4BX */ + {3000, 0x4, 0x20fc2, 0xc, 0xc, 510, {{1800, 1350, 428}, {1000, 1100, 189}}}, - /* ADAFX53DEP5AS */ - {53, 0x24, 0xf7a, 0x2a, 0x10, 890, + /* ADAFX53DEP5AS */ + {53, 0x24, 0xf7a, 0x2a, 0x10, 890, {{1200, 1100, 250}}}, - /* ADAFX55DEI5AS */ - {55, 0x24, 0xf7a, 0x2a, 0x12, 1040, + /* ADAFX55DEI5AS */ + {55, 0x24, 0xf7a, 0x2a, 0x12, 1040, {{1200, 1100, 250}}}, - /* ADAFX55DAA5BN */ - {55, 0x24, 0x20f71, 0x2a, 0x12, 1040, + /* ADAFX55DAA5BN */ + {55, 0x24, 0x20f71, 0x2a, 0x12, 1040, {{1200, 1100, 422}}}, - /* ADAFX57DAA5BN */ - {57, 0x24, 0x20f71, 0x2a, 0x14, 1040, + /* ADAFX57DAA5BN */ + {57, 0x24, 0x20f71, 0x2a, 0x14, 1040, {{1200, 1100, 434}}}, - /* SDA3100AIP3AX */ - {3100, 0x22, 0xfc0, 0xa, 0xa, 620, + /* SDA3100AIP3AX */ + {3100, 0x22, 0xfc0, 0xa, 0xa, 620, {{1000, 1100, 200}}}, - /* SDA2600AIO2BA */ - {2600, 0x22, 0x10fc0, 0x8, 0x8, 590, + /* SDA2600AIO2BA */ + {2600, 0x22, 0x10fc0, 0x8, 0x8, 590, {}}, - /* SDA2800AIO3BA */ - {2800, 0x22, 0x10fc0, 0x8, 0x8, 590, + /* SDA2800AIO3BA */ + {2800, 0x22, 0x10fc0, 0x8, 0x8, 590, {}}, - /* SDA3000AIO2BA */ - {3000, 0x22, 0x10fc0, 0xa, 0xa, 590, + /* SDA3000AIO2BA */ + {3000, 0x22, 0x10fc0, 0xa, 0xa, 590, {{1000, 1100, 190}}}, - /* SDA3100AIO3BA */ - {3100, 0x22, 0x10fc0, 0xa, 0xa, 590, + /* SDA3100AIO3BA */ + {3100, 0x22, 0x10fc0, 0xa, 0xa, 590, {{1000, 1100, 190}}}, - /* SDA3300AIO2BA */ - {3300, 0x22, 0x10fc0, 0xc, 0xc, 590, + /* SDA3300AIO2BA */ + {3300, 0x22, 0x10fc0, 0xc, 0xc, 590, {{1800, 1350, 488}, {1000, 1100, 180}}}, - /* SDA2500AIO3BX */ - {2500, 0x26, 0x20fc2, 0x6, 0x6, 590, + /* SDA2500AIO3BX */ + {2500, 0x26, 0x20fc2, 0x6, 0x6, 590, {}}, - /* SDA2600AIO2BX */ - {2600, 0x26, 0x20fc2, 0x8, 0x8, 590, + /* SDA2600AIO2BX */ + {2600, 0x26, 0x20fc2, 0x8, 0x8, 590, {}}, - /* SDA2800AIO3BX */ - {2800, 0x26, 0x20fc2, 0x8, 0x8, 590, + /* SDA2800AIO3BX */ + {2800, 0x26, 0x20fc2, 0x8, 0x8, 590, {}}, - /* SDA3000AIO2BX */ - {3000, 0x26, 0x20fc2, 0xa, 0xa, 590, + /* SDA3000AIO2BX */ + {3000, 0x26, 0x20fc2, 0xa, 0xa, 590, {{1000, 1100, 217}}}, - /* SDA3100AIO3BX */ - {3100, 0x26, 0x20fc2, 0xa, 0xa, 590, + /* SDA3100AIO3BX */ + {3100, 0x26, 0x20fc2, 0xa, 0xa, 590, {{1000, 1100, 217}}}, - /* SDA3300AIO2BX */ - {3300, 0x26, 0x20fc2, 0xc, 0xc, 590, + /* SDA3300AIO2BX */ + {3300, 0x26, 0x20fc2, 0xc, 0xc, 590, {{1800, 1350, 496}, {1000, 1100, 207}}}, - /* SDA3400AIO3BX */ - {3400, 0x26, 0x20fc2, 0xc, 0xc, 590, + /* SDA3400AIO3BX */ + {3400, 0x26, 0x20fc2, 0xc, 0xc, 590, {{1800, 1350, 496}, {1000, 1100, 207}}}, - /* TMSMT32BQX4LD */ - {32, 0xb, 0x20f42, 0xa, 0x0, 240, + /* TMSMT32BQX4LD */ + {32, 0xb, 0x20f42, 0xa, 0x0, 240, {{1600, 1150, 199}, {800, 900, 77}}}, - /* TMSMT34BQX5LD */ - {34, 0xb, 0x20f42, 0xa, 0x0, 240, + /* TMSMT34BQX5LD */ + {34, 0xb, 0x20f42, 0xa, 0x0, 240, {{1600, 1150, 199}, {800, 900, 79}}}, - /* TMSMT37BQX5LD */ - {37, 0xb, 0x20f42, 0xc, 0x0, 250, + /* TMSMT37BQX5LD */ + {37, 0xb, 0x20f42, 0xc, 0x0, 250, {{1800, 1150, 209}, {1600, 1100, 175}, {800, 900, 79}}}, - /* ADA4400DAA6CD */ - {4400, 0x5, 0x20f32, 0xe, 0xe, 1100, + /* ADA4400DAA6CD */ + {4400, 0x5, 0x20f32, 0xe, 0xe, 1100, {{2000, 1300, 1056}, {1800, 1250, 891}, {1000, 1100, 490}}}, - /* ADA4800DAA6CD */ - {4800, 0x5, 0x20f32, 0x10, 0x10, 1100, + /* ADA4800DAA6CD */ + {4800, 0x5, 0x20f32, 0x10, 0x10, 1100, {{2200, 1300, 1056}, {2000, 1250, 891}, {1800, 1200, 748}, {1000, 1100, 466}}}, - /* ADA3800DAA5BV */ - {3800, 0x5, 0x20fb1, 0xc, 0xc, 890, + /* ADA3800DAA5BV */ + {3800, 0x5, 0x20fb1, 0xc, 0xc, 890, {{1800, 1300, 846}, {1000, 1100, 401}}}, - /* ADA4200DAA5BV */ - {4200, 0x5, 0x20fb1, 0xe, 0xe, 890, + /* ADA4200DAA5BV */ + {4200, 0x5, 0x20fb1, 0xe, 0xe, 890, {{2000, 1300, 846}, {1800, 1250, 709}, {1000, 1100, 376}}}, - /* ADA4600DAA5BV */ - {4600, 0x5, 0x20fb1, 0x10, 0x10, 1100, + /* ADA4600DAA5BV */ + {4600, 0x5, 0x20fb1, 0x10, 0x10, 1100, {{2200, 1300, 1056}, {2000, 1250, 891}, {1800, 1200, 748}, {1000, 1100, 466}}}, };

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coreboot July 2012