coreboot July 2012

coreboot@coreboot.org

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Patch set updated for coreboot: f8d58cf SMM: Fix state table for Intel Core2 CPUs
by Stefan Reinauer 25 Jul '12

25 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1353 -gerrit commit f8d58cf0f780238a4d820e0fb9a8227fac44a6ad Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Jul 24 14:53:15 2012 -0700 SMM: Fix state table for Intel Core2 CPUs When fixing the SMM state table for SandyBridge/IvyBridge CPUs the wrong table was used for older 64bit capable CPUs. Change-Id: Ia7dff21aa3f0e5aa61575634fc839777de6bef10 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/cpu/x86/smm/smihandler.c | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/src/cpu/x86/smm/smihandler.c b/src/cpu/x86/smm/smihandler.c index 83ebaf9..10f38f9 100644 --- a/src/cpu/x86/smm/smihandler.c +++ b/src/cpu/x86/smm/smihandler.c @@ -158,6 +158,7 @@ void smi_handler(u32 smm_revision) state_save.type = EM64T; state_save.em64t_state_save = (em64t_smm_state_save_area_t *) (smm_base + 0x7d00 - (node * 0x400)); + break; case 0x00030101: /* SandyBridge/IvyBridge */ state_save.type = EM64T101; state_save.em64t101_state_save =

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Patch set updated for coreboot: bbd48e6 Enable Microcode in CBFS for all SandyBridge/IvyBridge systems
by Stefan Reinauer 25 Jul '12

25 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1332 -gerrit commit bbd48e6574183e28fa6fc5ab3568c5b777cdb01e Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Jul 10 17:02:21 2012 -0700 Enable Microcode in CBFS for all SandyBridge/IvyBridge systems Change-Id: Idee4facc18e0be60906d2a2f0e99bd39de8d7247 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/cpu/Kconfig | 5 +---- src/cpu/intel/model_206ax/Kconfig | 4 +--- src/cpu/intel/model_206ax/bootblock.c | 10 ---------- src/cpu/intel/model_206ax/model_206ax_init.c | 10 ---------- 4 files changed, 2 insertions(+), 27 deletions(-) diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index f37bbf6..baf686e 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -62,13 +62,10 @@ config SSE2 streaming SIMD instructions. Some parts of coreboot can be built with more efficient code if SSE2 instructions are available. -if CPU_INTEL_MODEL_206AX || CPU_INTEL_MODEL_306AX - config MICROCODE_IN_CBFS bool "Look for microcode in CBFS" + default n help Load microcode updates from CBFS instead of compiling them in. -endif - endif # ARCH_X86 diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index 1d4ff02..071683e 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -12,6 +12,7 @@ config CPU_SPECIFIC_OPTIONS select SSE2 select UDELAY_LAPIC select SMM_TSEG + select MICROCODE_IN_CBFS config BOOTBLOCK_CPU_INIT string @@ -21,14 +22,11 @@ config SMM_TSEG_SIZE hex default 0x800000 -if MICROCODE_IN_CBFS config MICROCODE_INCLUDE_PATH string default "src/cpu/intel/model_206ax" endif -endif - if CPU_INTEL_MODEL_206AX config CPU_MODEL_NAME string diff --git a/src/cpu/intel/model_206ax/bootblock.c b/src/cpu/intel/model_206ax/bootblock.c index dbc3591..02958bb 100644 --- a/src/cpu/intel/model_206ax/bootblock.c +++ b/src/cpu/intel/model_206ax/bootblock.c @@ -25,12 +25,6 @@ #include <arch/io.h> #include <arch/romcc_io.h> -#if !CONFIG_MICROCODE_IN_CBFS -static const uint32_t microcode_updates[] = { - #include "microcode_blob.h" -}; -#endif - #include <cpu/intel/microcode/microcode.c> #include "model_206ax.h" @@ -125,9 +119,5 @@ static void bootblock_cpu_init(void) /* Set flex ratio and reset if needed */ set_flex_ratio_to_tdp_nominal(); enable_rom_caching(); -#if CONFIG_MICROCODE_IN_CBFS intel_update_microcode_from_cbfs(); -#else - intel_update_microcode(microcode_updates); -#endif } diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 08757d1..70a655a 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -115,12 +115,6 @@ static acpi_cstate_t cstate_map[] = { { 0 } }; -#if !CONFIG_MICROCODE_IN_CBFS -static const uint32_t microcode_updates[] = { - #include "microcode_blob.h" -}; -#endif - /* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */ static const u8 power_limit_time_sec_to_msr[] = { [0] = 0x00, @@ -421,11 +415,7 @@ static void model_206ax_init(device_t cpu) /* Turn on caching if we haven't already */ x86_enable_cache(); -#if CONFIG_MICROCODE_IN_CBFS intel_update_microcode_from_cbfs(); -#else - intel_update_microcode(microcode_updates); -#endif /* Clear out pending MCEs */ configure_mca();

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Patch merged into coreboot/master: 5b88dbb ELOG: Log boot-time events found in southbridge
by gerrit＠coreboot.org 25 Jul '12

25 Jul '12

the following patch was just integrated into master: commit 5b88dbbbe84baa481d07cab23e8034e01685f1a6 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Sat Jun 23 17:06:47 2012 -0700 ELOG: Log boot-time events found in southbridge This is called from the SMI handler install because those setup functions clear many of these registers. Ensure that these events show up in the log as appropriate. Example log output: 159 | 2012-06-23 14:31:54 | SUS Power Fail 160 | 2012-06-23 14:31:54 | System Reset 161 | 2012-06-23 14:31:54 | ACPI Wake | S5 Change-Id: I48c423c10ee7e6c2829bcc95f6cfabb4979c25a9 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Build-Tested: build bot (Jenkins) at Tue Jul 24 18:07:37 2012, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Wed Jul 25 22:25:21 2012, giving +2 See http://review.coreboot.org/1319 for details. -gerrit

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Patch merged into coreboot/master: 7a33471 ELOG: Log events for Chrome OS developer/recovery mode
by gerrit＠coreboot.org 25 Jul '12

25 Jul '12

the following patch was just integrated into master: commit 7a33471cb4802513b5349967fd5f328a9f491b13 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Sat Jun 23 17:33:30 2012 -0700 ELOG: Log events for Chrome OS developer/recovery mode If a Chrome OS device is in developer mode log an event. When the device is in recovery mode also log an event and provide the recovery reason. Enable developer mode and trigger recovery mode and verify that the events are logged: 238 | 2012-06-23 17:31:56 | Chrome OS Developer Mode 239 | 2012-06-23 17:31:56 | Chrome OS Recovery Mode | User Requested from Developer Screen Change-Id: I14d41f44e04fd91340569617c7314da7e35a154f Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Build-Tested: build bot (Jenkins) at Tue Jul 24 18:38:41 2012, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Wed Jul 25 22:24:56 2012, giving +2 See http://review.coreboot.org/1321 for details. -gerrit

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Patch merged into coreboot/master: d95d46c Fix comment to reference IvyBridge, too
by gerrit＠coreboot.org 25 Jul '12

25 Jul '12

the following patch was just integrated into master: commit d95d46c972a6a150e11cfc61bde2830545ad61d3 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Jul 10 17:16:10 2012 -0700 Fix comment to reference IvyBridge, too On both SandyBridge and IvyBridge BCLK is fixed at 100MHz. Have the comment reflect that. Change-Id: Ia81c3501dc3e68cf3143c3bc864dfbf88901f9f9 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Build-Tested: build bot (Jenkins) at Wed Jul 25 02:29:55 2012, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Wed Jul 25 22:24:26 2012, giving +2 See http://review.coreboot.org/1336 for details. -gerrit

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Patch merged into coreboot/master: f7bf0c3 Include SandyBridge Microcode when IvyBridge is enabled
by gerrit＠coreboot.org 25 Jul '12

25 Jul '12

the following patch was just integrated into master: commit f7bf0c3ba600c4ffb9a11bea6ab7b049cfe732c7 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Jul 23 16:12:52 2012 -0700 Include SandyBridge Microcode when IvyBridge is enabled .. in case the system has pluggable CPUs or might come in different SKUs. Change-Id: I7a7cd95b4de5dd78370355f448688e8d000434c1 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Build-Tested: build bot (Jenkins) at Wed Jul 25 01:29:11 2012, giving +1 Reviewed-By: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> at Tue Jul 24 23:15:16 2012, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Wed Jul 25 22:23:40 2012, giving +2 See http://review.coreboot.org/1333 for details. -gerrit

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Patch merged into coreboot/master: decc049 AMD parmer: Set correct azalia code verb table
by gerrit＠coreboot.org 25 Jul '12

25 Jul '12

the following patch was just integrated into master: commit decc049c17ecd3d06f3c6b31f69a5d462fee6a80 Author: zbao <fishbaozi(a)gmail.com> Date: Tue Jul 24 19:03:03 2012 +0800 AMD parmer: Set correct azalia code verb table Change-Id: I0b10080deb971cdefa4d3916fabd40f5a81b11f4 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> Build-Tested: build bot (Jenkins) at Wed Jul 25 06:30:22 2012, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Wed Jul 25 22:22:32 2012, giving +2 See http://review.coreboot.org/1352 for details. -gerrit

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Patch merged into coreboot/master: b4a40ce AMD family15tn: Add BIOS callback hook for getting VBIOS Image
by gerrit＠coreboot.org 25 Jul '12

25 Jul '12

the following patch was just integrated into master: commit b4a40ce9ff8b73f485723ba87553bbe63f260e77 Author: zbao <fishbaozi(a)gmail.com> Date: Tue Jul 24 17:59:43 2012 +0800 AMD family15tn: Add BIOS callback hook for getting VBIOS Image This is for GfxInitSview(GnbSview.c). It would create warning message if it could not get VBIOS image. Change-Id: I3b2726f612b4b7a237644a4b63b56efad52b7ab5 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> Build-Tested: build bot (Jenkins) at Wed Jul 25 06:16:13 2012, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Wed Jul 25 22:22:08 2012, giving +2 See http://review.coreboot.org/1351 for details. -gerrit

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Patch merged into coreboot/master: 96e5b66 AMD Family 15tn: Set the default return value as AGESA_SUCCESS instead of TRUE
by gerrit＠coreboot.org 25 Jul '12

25 Jul '12

the following patch was just integrated into master: commit 96e5b66538e4ab0e38057212e25002070d77531e Author: zbao <fishbaozi(a)gmail.com> Date: Tue Jul 24 17:58:30 2012 +0800 AMD Family 15tn: Set the default return value as AGESA_SUCCESS instead of TRUE The default return value should be AGESA_SUCCESS, which is zero. If it was set as TRUE, the AGESA wrapper would think it was AGESA_UNSUPPORTED. That would make no sense. And it would produce ASSERT warning in AGESA wrapper. On my parmer board, with Engine sample processor, it can not create the correct DMI table. Routine initlate will return AGESS_ERROR. ------Serial message--------- ASSERTION FAILED: file 'src/mainboard/amd/parmer/agesawrapper.c', line 427 DmiTable:100123c3, AcpiPstatein: 10010126, AcpiSrat:0,AcpiSlit:0, Mce:100111ba, Cmc:1001127c,Alib:1001ccd4, AcpiIvrs:0 in agesawrapper_amdinitlate agesawrapper_amdinitlate failed: 5 ----------------------------- I believe the processor with acceptable name string will create the right DMI. Change-Id: Ie86955cf9affffc964a7c9f4a2c63077ef2030de Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> Build-Tested: build bot (Jenkins) at Wed Jul 25 06:02:07 2012, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Wed Jul 25 22:21:24 2012, giving +2 See http://review.coreboot.org/1350 for details. -gerrit

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Patch merged into coreboot/master: dddbbed AMD Family15tn: Set the mask of MTRR to 0000FFFXX0000800
by gerrit＠coreboot.org 25 Jul '12

25 Jul '12

the following patch was just integrated into master: commit dddbbed1725ae8a781c3cecd39d3cf5e354d33ff Author: zbao <fishbaozi(a)gmail.com> Date: Tue Jul 24 17:56:48 2012 +0800 AMD Family15tn: Set the mask of MTRR to 0000FFFXX0000800 Remove the warning message from linux dmesg, mtrr: your BIOS has configured as incorrect mask, fixing it. Change-Id: I355509db12ab10c33b7c1c23e2c7c4783f30e67e Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> Build-Tested: build bot (Jenkins) at Wed Jul 25 05:46:11 2012, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Wed Jul 25 22:20:55 2012, giving +2 See http://review.coreboot.org/1349 for details. -gerrit

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coreboot July 2012