coreboot July 2012

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Patch merged into coreboot/master: 13b6519 NVS: Add a temp sensor ID and an ACPI Method to set it
by gerrit＠coreboot.org 26 Jul '12

26 Jul '12

the following patch was just integrated into master: commit 13b65191bbcc97e2526c74cec03eba5f8e50d5fd Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Jul 16 11:28:52 2012 -0700 NVS: Add a temp sensor ID and an ACPI Method to set it This will allow various teams to select which thermal sensor will control the thermal zones. Also add a method to notify the thermalzones of a change so these threshold/sensor methods take effect. Needs a modified BIOS that uses the NVS TMPS value in the thermalzone to read a different sensor. Then, use a kernel driver that contains the following: /* Adjust temperature sensor id to 2 */ union acpi_object param; struct acpi_object_list input; param.type = ACPI_TYPE_INTEGER param.integer.value = 2 input.count = 1; input.pointer = &param; acpi_evaluate_object(NULL, "\\TMPU", &input, NULL); And ensure that the temperature sensor that is being monitored switches to ID 2. Change-Id: I6319741358ba31eb8a3dc635d64f3f0acf683386 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Build-Tested: build bot (Jenkins) at Wed Jul 25 03:26:19 2012, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Thu Jul 26 20:31:30 2012, giving +2 See http://review.coreboot.org/1340 for details. -gerrit

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Patch merged into coreboot/master: c939c3d ME: Move ME v8 lockdown to finalize step
by gerrit＠coreboot.org 26 Jul '12

26 Jul '12

the following patch was just integrated into master: commit c939c3d9957c2a3c7a6619815374520226f7f78d Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Jul 10 15:15:41 2012 -0700 ME: Move ME v8 lockdown to finalize step The ME device was being sent EOP and the PCI device hidden during coreboot so it was not available in the SMI finalize step. This also flips the PCI vendor/device dword around for the match. Boot on Panther Point with serial and SMI debugging enabled and see that ME EOP message is sent and the device is hidden at end of U-boot and before the kernel loads. Finalizing Coreboot SMI# #0 ME: mkhi_end_of_post ME: END OF POST message successful (0) PM1_STS: TMROF PM1_EN: 120 Starting kernel ... Change-Id: I230038c62c50db2a1c94078c0a2a67bdc232440e Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Build-Tested: build bot (Jenkins) at Wed Jul 25 02:58:44 2012, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Thu Jul 26 20:31:12 2012, giving +2 See http://review.coreboot.org/1338 for details. -gerrit

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Patch merged into coreboot/master: 035c331 Reserve bd82x6x LPC decode ranges in the resource allocator
by gerrit＠coreboot.org 26 Jul '12

26 Jul '12

the following patch was just integrated into master: commit 035c331b3e4a344f7c04b4074e958544bc46ef9a Author: Marc Jones <marc.jones(a)se-eng.com> Date: Fri Jul 13 14:14:34 2012 -0600 Reserve bd82x6x LPC decode ranges in the resource allocator The LPC bus normally allocates the range for legacy devices, 0-0x1000. Some devices on LPC are above that range and need to be accounted for. Check the decode range settings for addresses > 0x1000 and reserve them. Change-Id: Idba800d7cee3185296f29dd237ba306f3de8de55 Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Build-Tested: build bot (Jenkins) at Wed Jul 25 02:44:20 2012, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Thu Jul 26 20:30:52 2012, giving +2 See http://review.coreboot.org/1337 for details. -gerrit

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Patch merged into coreboot/master: 85c8a36 ELOG: Log run-time SMI southbridge events
by gerrit＠coreboot.org 26 Jul '12

26 Jul '12

the following patch was just integrated into master: commit 85c8a36b7d8c2a838fb275eeaa02d60e080e941e Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Sat Jun 23 17:30:19 2012 -0700 ELOG: Log run-time SMI southbridge events Events are logged for SMIs that trigger ACPI sleeps state entry and when the power button press triggers an SMI such as at the developer/recovery screens. Generate ACPI sleep state events and power button events and verify they show up in the log: 153 | 2012-06-23 17:12:59 | ACPI Enter | S5 184 | 2012-06-23 17:15:50 | ACPI Enter | S3 216 | 2012-06-23 17:28:58 | Power Button Change-Id: Iba134d619780e459bce189d36d57844997ffb009 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Build-Tested: build bot (Jenkins) at Tue Jul 24 18:22:59 2012, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Thu Jul 26 20:29:58 2012, giving +2 See http://review.coreboot.org/1320 for details. -gerrit

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Patch merged into coreboot/master: 99d48b5 SATA: Add option to configure gen3 transmitter
by gerrit＠coreboot.org 26 Jul '12

26 Jul '12

the following patch was just integrated into master: commit 99d48b5837f2ce45a6bdb918542815fa39b7de11 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Jul 16 16:16:31 2012 -0700 SATA: Add option to configure gen3 transmitter Unfortunately the drive strength values are very much board specific and different between mobile and desktop so we don't try to do any fancy detection here but let it be specified directly in the devicetree. Change-Id: I66674bff0de04ecd088fb09afad1cf801a374df2 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Build-Tested: build bot (Jenkins) at Wed Jul 25 05:04:55 2012, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Thu Jul 26 20:29:15 2012, giving +2 See http://review.coreboot.org/1347 for details. -gerrit

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Patch merged into coreboot/master: d66dc4e ELOG: Support GSMI in CPT/PPT southbridge SMI handler
by gerrit＠coreboot.org 26 Jul '12

26 Jul '12

the following patch was just integrated into master: commit d66dc4e5e6d8b4c227a78a973ba3b057824fbb22 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Sat Jun 23 17:25:29 2012 -0700 ELOG: Support GSMI in CPT/PPT southbridge SMI handler In order to support the GSMI interface the SMI handler needs to find and use the state save area from the same CPU that initiated the SMI. In this case it is a synchronous SMI resulting form an IO write to port 0xB2. To find the right CPU state save area iterate over the region until the "IO Misc Info" field reports the expected value and then proceed to use that state save area. This is needed because the coreboot SMI handler only executes on one core, and that core is non-deterministic. It is likely that the core executing the C SMM handler is not the same one that actually did the IO write to 0xB2 and generated the SMI. The GSMI parameter buffer is passed as a pointer to EBX in the tate save area, and the GSMI command is extracted from EAX before it is used as the return value. This interface is tested by enabling CONFIG_GOOGLE_GSMI in the kernel and generating events and verifying that they end up in the event log. 159 | 2012-06-23 16:22:45 | Kernl Event | Clean Shutdown 184 | 2012-06-23 17:14:05 | Kernl Event | Oops 185 | 2012-06-23 17:14:05 | Kernl Event | Panic Change-Id: Ic121ea69e9f50c88467c435e095c3e3629989806 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Build-Tested: build bot (Jenkins) at Tue Jul 24 17:38:21 2012, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Thu Jul 26 20:28:37 2012, giving +2 See http://review.coreboot.org/1317 for details. -gerrit

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New patch to review for coreboot: e0b9fa8 Refactor driver structs
by Patrick Georgi 26 Jul '12

26 Jul '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1358 -gerrit commit e0b9fa8b6e58d3e4e84b4a01e897bd505fb561b9 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Thu Jul 26 19:48:23 2012 +0200 Refactor driver structs Our driver infrastructure became more flexible recently. Make use of it. These are the low hanging fruits (files with 5 device variants or more), but there are still lots of files with less potential for deduplication. Change-Id: If6b7be5046581f81485a511b150f99b029b95c3b Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/northbridge/amd/cimx/rd890/late.c | 40 +++++--------------- src/northbridge/intel/sandybridge/gma.c | 48 +++---------------------- src/southbridge/amd/rs780/gfx.c | 60 +++++++----------------------- src/southbridge/amd/sb600/usb.c | 31 +++++----------- src/southbridge/intel/i82801gx/pcie.c | 46 +++++------------------ src/southbridge/intel/i82801gx/sata.c | 56 ++++++----------------------- src/southbridge/nvidia/mcp55/lpc.c | 48 ++++++------------------- src/southbridge/nvidia/mcp55/pcie.c | 32 +++++----------- src/southbridge/via/k8t890/ctrl.c | 33 +++++------------ src/southbridge/via/k8t890/error.c | 33 +++++------------ 10 files changed, 99 insertions(+), 328 deletions(-) diff --git a/src/northbridge/amd/cimx/rd890/late.c b/src/northbridge/amd/cimx/rd890/late.c index 208e5f1..33da2b4 100644 --- a/src/northbridge/amd/cimx/rd890/late.c +++ b/src/northbridge/amd/cimx/rd890/late.c @@ -220,38 +220,18 @@ static struct device_operations ht_ops = { .ops_pci = &lops_pci, }; -static const struct pci_driver ht_driver_sr5690 __pci_driver = { - .ops = &ht_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_AMD_SR5690_HT, -}; - -static const struct pci_driver ht_driver_sr5670 __pci_driver = { - .ops = &ht_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_AMD_SR5670_HT, -}; - -static const struct pci_driver ht_driver_sr5650 __pci_driver = { - .ops = &ht_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_AMD_SR5650_HT, -}; - -static const struct pci_driver ht_driver_rd890tv __pci_driver = { - .ops = &ht_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_AMD_RD890TV_HT, +static const unsigned short driver_ids[] = { + PCI_DEVICE_ID_AMD_SR5690_HT, + PCI_DEVICE_ID_AMD_SR5670_HT, + PCI_DEVICE_ID_AMD_SR5650_HT, + PCI_DEVICE_ID_AMD_RD890TV_HT, + PCI_DEVICE_ID_AMD_RD890_HT, + PCI_DEVICE_ID_AMD_990FX_HT, + 0 }; -static const struct pci_driver ht_driver_rd890 __pci_driver = { - .ops = &ht_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_AMD_RD890_HT, -}; - -static const struct pci_driver ht_driver_990fx __pci_driver = { +static const struct pci_driver ht_driver_sr5690 __pci_driver = { .ops = &ht_ops, .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_AMD_990FX_HT, + .devices= driver_ids, }; diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index 9a8b631..c2bb2ea 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -659,50 +659,12 @@ static struct device_operations gma_func0_ops = { .ops_pci = &gma_pci_ops, }; -static const struct pci_driver gma_gt1_desktop __pci_driver = { - .ops = &gma_func0_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x0102, -}; - -static const struct pci_driver gma_gt1_mobile __pci_driver = { - .ops = &gma_func0_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x0106, +static const unsigned short gma_ids[] = { + 0x0102, 0x0106, 0x010a, 0x0112, 0x0116, 0x0122, 0x0126, 0x166, + 0, }; - -static const struct pci_driver gma_gt1_server __pci_driver = { - .ops = &gma_func0_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x010a, -}; - -static const struct pci_driver gma_gt2_desktop __pci_driver = { - .ops = &gma_func0_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x0112, -}; - -static const struct pci_driver gma_gt2_mobile __pci_driver = { - .ops = &gma_func0_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x0116, -}; - -static const struct pci_driver gma_gt2_desktop_fast __pci_driver = { - .ops = &gma_func0_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x0122, -}; - -static const struct pci_driver gma_gt2_mobile_fast __pci_driver = { +static const struct pci_driver gma_gt1_desktop __pci_driver = { .ops = &gma_func0_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x0126, -}; - -static const struct pci_driver gma_func0_driver_3 __pci_driver = { - .ops = &gma_func0_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x0166, + .devices= gma_ids, }; diff --git a/src/southbridge/amd/rs780/gfx.c b/src/southbridge/amd/rs780/gfx.c index 904e154..f70cd9b 100644 --- a/src/southbridge/amd/rs780/gfx.c +++ b/src/southbridge/amd/rs780/gfx.c @@ -1005,56 +1005,24 @@ static struct device_operations pcie_ops = { /* * We should list all of them here. * */ -static const struct pci_driver pcie_driver_780 __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_RS780_INT_GFX, +static const unsigned short pcie_780_ids[] = { + PCI_DEVICE_ID_ATI_RS780_INT_GFX, + PCI_DEVICE_ID_ATI_RS780C_INT_GFX, + PCI_DEVICE_ID_ATI_RS780M_INT_GFX, + PCI_DEVICE_ID_ATI_RS780MC_INT_GFX, + PCI_DEVICE_ID_ATI_RS780E_INT_GFX, + PCI_DEVICE_ID_ATI_RS785G_INT_GFX, + PCI_DEVICE_ID_ATI_RS785C_INT_GFX, + PCI_DEVICE_ID_ATI_RS785M_INT_GFX, + PCI_DEVICE_ID_ATI_RS785MC_INT_GFX, + PCI_DEVICE_ID_ATI_RS785D_INT_GFX, + 0 }; -static const struct pci_driver pcie_driver_780c __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_RS780C_INT_GFX, -}; -static const struct pci_driver pcie_driver_780m __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_RS780M_INT_GFX, -}; -static const struct pci_driver pcie_driver_780mc __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_RS780MC_INT_GFX, -}; -static const struct pci_driver pcie_driver_780e __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_RS780E_INT_GFX, -}; -static const struct pci_driver pcie_driver_785g __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_RS785G_INT_GFX, -}; -static const struct pci_driver pcie_driver_785c __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_RS785C_INT_GFX, -}; -static const struct pci_driver pcie_driver_785m __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_RS785M_INT_GFX, -}; -static const struct pci_driver pcie_driver_785mc __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_RS785MC_INT_GFX, -}; -static const struct pci_driver pcie_driver_785d __pci_driver = { +static const struct pci_driver pcie_driver_780 __pci_driver = { .ops = &pcie_ops, .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_RS785D_INT_GFX, + .devices = pcie_780_ids, }; /* step 12 ~ step 14 from rpr */ diff --git a/src/southbridge/amd/sb600/usb.c b/src/southbridge/amd/sb600/usb.c index 7ff8f5c..5023578 100644 --- a/src/southbridge/amd/sb600/usb.c +++ b/src/southbridge/amd/sb600/usb.c @@ -164,30 +164,19 @@ static struct device_operations usb_ops = { .ops_pci = &lops_pci, }; -static const struct pci_driver usb_0_driver __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB600_USB_0, -}; -static const struct pci_driver usb_1_driver __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB600_USB_1, -}; -static const struct pci_driver usb_2_driver __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB600_USB_2, +static const unsigned short usb_ids[] = { + PCI_DEVICE_ID_ATI_SB600_USB_0, + PCI_DEVICE_ID_ATI_SB600_USB_1, + PCI_DEVICE_ID_ATI_SB600_USB_2, + PCI_DEVICE_ID_ATI_SB600_USB_3, + PCI_DEVICE_ID_ATI_SB600_USB_4, + 0, }; -static const struct pci_driver usb_3_driver __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB600_USB_3, -}; -static const struct pci_driver usb_4_driver __pci_driver = { + +static const struct pci_driver usb_0_driver __pci_driver = { .ops = &usb_ops, .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB600_USB_4, + .devices= usb_ids, }; static struct device_operations usb_ops2 = { diff --git a/src/southbridge/intel/i82801gx/pcie.c b/src/southbridge/intel/i82801gx/pcie.c index d69bc6d..0cd9473 100644 --- a/src/southbridge/intel/i82801gx/pcie.c +++ b/src/southbridge/intel/i82801gx/pcie.c @@ -121,44 +121,18 @@ static struct device_operations device_ops = { .ops_pci = &pci_ops, }; -/* 82801GB/GR/GDH/GBM/GHM (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH) */ -static const struct pci_driver i82801gx_pcie_port1 __pci_driver = { - .ops = &device_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x27d0, -}; - -/* 82801GB/GR/GDH/GBM/GHM (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH) */ -static const struct pci_driver i82801gx_pcie_port2 __pci_driver = { - .ops = &device_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x27d2, -}; - -/* 82801GB/GR/GDH/GBM/GHM (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH) */ -static const struct pci_driver i82801gx_pcie_port3 __pci_driver = { - .ops = &device_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x27d4, -}; - -/* 82801GB/GR/GDH/GBM/GHM (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH) */ -static const struct pci_driver i82801gx_pcie_port4 __pci_driver = { - .ops = &device_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x27d6, -}; - -/* 82801GR/GDH/GHM (ICH7R/ICH7DH/ICH7-M DH) */ -static const struct pci_driver i82801gx_pcie_port5 __pci_driver = { - .ops = &device_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x27e0, +static const unsigned short i28801gx_pcie_ids[] = { + 0x27d0, /* 82801GB/GR/GDH/GBM/GHM (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH) */ + 0x27d2, /* 82801GB/GR/GDH/GBM/GHM (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH) */ + 0x27d4, /* 82801GB/GR/GDH/GBM/GHM (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH) */ + 0x27d6, /* 82801GB/GR/GDH/GBM/GHM (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH) */ + 0x27e0, /* 82801GR/GDH/GHM (ICH7R/ICH7DH/ICH7-M DH) */ + 0x27e2, /* 82801GR/GDH/GHM (ICH7R/ICH7DH/ICH7-M DH) */ + 0 }; -/* 82801GR/GDH/GHM (ICH7R/ICH7DH/ICH7-M DH) */ -static const struct pci_driver i82801gx_pcie_port6 __pci_driver = { +static const struct pci_driver i82801gx_pcie __pci_driver = { .ops = &device_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x27e2, + .devices= i82801gx_pcie_ids, }; diff --git a/src/southbridge/intel/i82801gx/sata.c b/src/southbridge/intel/i82801gx/sata.c index 0e7a1a7..a8d6f30 100644 --- a/src/southbridge/intel/i82801gx/sata.c +++ b/src/southbridge/intel/i82801gx/sata.c @@ -213,53 +213,19 @@ static struct device_operations sata_ops = { .ops_pci = &sata_pci_ops, }; -/* Desktop Non-AHCI and Non-RAID Mode */ -/* 82801GB/GR/GDH (ICH7/ICH7R/ICH7DH) */ -static const struct pci_driver i82801gx_sata_normal_driver __pci_driver = { - .ops = &sata_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x27c0, -}; - -/* Mobile Non-AHCI and Non-RAID Mode */ -/* 82801GBM/GHM (ICH7-M/ICH7-M DH) */ -static const struct pci_driver i82801gx_sata_mobile_normal_driver __pci_driver = { - .ops = &sata_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x27c4, -}; - - -/* NOTE: Any of the below are not properly supported yet. */ - -/* Desktop AHCI Mode */ -/* 82801GB/GR/GDH (ICH7/ICH7R/ICH7DH) */ -static const struct pci_driver i82801gx_sata_ahci_driver __pci_driver = { - .ops = &sata_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x27c1, -}; - -/* Desktop RAID mode */ -/* 82801GB/GR/GDH (ICH7/ICH7R/ICH7DH) */ -static const struct pci_driver i82801gx_sata_raid_driver __pci_driver = { - .ops = &sata_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x27c3, -}; - -/* Mobile AHCI Mode */ -/* 82801GBM/GHM (ICH7-M/ICH7-M DH) */ -static const struct pci_driver i82801gx_sata_mobile_ahci_driver __pci_driver = { - .ops = &sata_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x27c5, +static const unsigned short sata_ids[] = { + 0x27c0, /* Desktop Non-AHCI and Non-RAID Mode: 82801GB/GR/GDH (ICH7/ICH7R/ICH7DH) */ + 0x27c4, /* Mobile Non-AHCI and Non-RAID Mode: 82801GBM/GHM (ICH7-M/ICH7-M DH) */ + /* NOTE: Any of the below are not properly supported yet. */ + 0x27c1, /* Desktop AHCI Mode: 82801GB/GR/GDH (ICH7/ICH7R/ICH7DH) */ + 0x27c3, /* Desktop RAID mode: 82801GB/GR/GDH (ICH7/ICH7R/ICH7DH) */ + 0x27c5, /* Mobile AHCI Mode: 82801GBM/GHM (ICH7-M/ICH7-M DH) */ + 0x27c6, /* ICH7M DH Raid Mode: 82801GHM (ICH7-M DH) */ + 0 }; -/* ICH7M DH Raid Mode */ -/* 82801GHM (ICH7-M DH) */ -static const struct pci_driver i82801gx_sata_ich7dh_raid_driver __pci_driver = { +static const struct pci_driver i82801gx_sata_driver __pci_driver = { .ops = &sata_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x27c6, + .devices= sata_ids, }; diff --git a/src/southbridge/nvidia/mcp55/lpc.c b/src/southbridge/nvidia/mcp55/lpc.c index 9ea1923..d16e3cc 100644 --- a/src/southbridge/nvidia/mcp55/lpc.c +++ b/src/southbridge/nvidia/mcp55/lpc.c @@ -260,46 +260,20 @@ static struct device_operations lpc_ops = { // .enable = mcp55_enable, .ops_pci = &mcp55_pci_ops, }; -static const struct pci_driver lpc_driver __pci_driver = { - .ops = &lpc_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_MCP55_LPC, -}; - -static const struct pci_driver lpc_driver_pro __pci_driver = { - .ops = &lpc_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_MCP55_PRO, +static const unsigned short lpc_ids[] = { + PCI_DEVICE_ID_NVIDIA_MCP55_LPC, + PCI_DEVICE_ID_NVIDIA_MCP55_PRO, + PCI_DEVICE_ID_NVIDIA_MCP55_LPC_2, + PCI_DEVICE_ID_NVIDIA_MCP55_LPC_3, + PCI_DEVICE_ID_NVIDIA_MCP55_LPC_4, + PCI_DEVICE_ID_NVIDIA_MCP55_LPC_5, + PCI_DEVICE_ID_NVIDIA_MCP55_LPC_6, + 0 }; - -static const struct pci_driver lpc_driver_lpc2 __pci_driver = { - .ops = &lpc_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_MCP55_LPC_2, -}; - -static const struct pci_driver lpc_driver_lpc3 __pci_driver = { - .ops = &lpc_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_MCP55_LPC_3, -}; - -static const struct pci_driver lpc_driver_lpc4 __pci_driver = { - .ops = &lpc_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_MCP55_LPC_4, -}; - -static const struct pci_driver lpc_driver_lpc5 __pci_driver = { - .ops = &lpc_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_MCP55_LPC_5, -}; - -static const struct pci_driver lpc_driver_lpc6 __pci_driver = { +static const struct pci_driver lpc_driver __pci_driver = { .ops = &lpc_ops, .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_MCP55_LPC_6, + .devices = lpc_ids, }; static struct device_operations lpc_slave_ops = { diff --git a/src/southbridge/nvidia/mcp55/pcie.c b/src/southbridge/nvidia/mcp55/pcie.c index cd43f87..108a9b1 100644 --- a/src/southbridge/nvidia/mcp55/pcie.c +++ b/src/southbridge/nvidia/mcp55/pcie.c @@ -50,29 +50,17 @@ static struct device_operations pcie_ops = { // .enable = mcp55_enable, }; -static const struct pci_driver pciebc_driver __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_B_C, -}; -static const struct pci_driver pciee_driver __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_E, +static const unsigned short pcie_ids[] = { + PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_B_C, + PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_E, + PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_A, + PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_F, + PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_D, + 0 }; -static const struct pci_driver pciea_driver __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_A, -}; -static const struct pci_driver pcief_driver __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_F, -}; -static const struct pci_driver pcied_driver __pci_driver = { + +static const struct pci_driver pciebc_driver __pci_driver = { .ops = &pcie_ops, .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_D, + .devices= pcie_ids, }; - diff --git a/src/southbridge/via/k8t890/ctrl.c b/src/southbridge/via/k8t890/ctrl.c index fc851f8..3b92493 100644 --- a/src/southbridge/via/k8t890/ctrl.c +++ b/src/southbridge/via/k8t890/ctrl.c @@ -193,32 +193,17 @@ static const struct device_operations ctrl_ops = { .ops_pci = &lops_pci, }; -static const struct pci_driver northbridge_driver_t800 __pci_driver = { - .ops = &ctrl_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_K8T800_NB_SB_CTR, -}; - -static const struct pci_driver northbridge_driver_m800 __pci_driver = { - .ops = &ctrl_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_K8M800_NB_SB_CTR, -}; - -static const struct pci_driver northbridge_driver_t890 __pci_driver = { - .ops = &ctrl_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_K8T890CE_7, -}; - -static const struct pci_driver northbridge_driver_t890cf __pci_driver = { - .ops = &ctrl_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_K8T890CF_7, +static const unsigned short ctrl_ids[] = { + PCI_DEVICE_ID_VIA_K8T800_NB_SB_CTR, + PCI_DEVICE_ID_VIA_K8M800_NB_SB_CTR, + PCI_DEVICE_ID_VIA_K8T890CE_7, + PCI_DEVICE_ID_VIA_K8T890CF_7, + PCI_DEVICE_ID_VIA_K8M890CE_7, + 0 }; -static const struct pci_driver northbridge_driver_m890 __pci_driver = { +static const struct pci_driver northbridge_driver_t800 __pci_driver = { .ops = &ctrl_ops, .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_K8M890CE_7, + .devices= ctrl_ids, }; diff --git a/src/southbridge/via/k8t890/error.c b/src/southbridge/via/k8t890/error.c index 1f6979a..846ccfb 100644 --- a/src/southbridge/via/k8t890/error.c +++ b/src/southbridge/via/k8t890/error.c @@ -53,32 +53,17 @@ static const struct device_operations error_ops = { .ops_pci = &lops_pci, }; -static const struct pci_driver northbridge_driver_t800 __pci_driver = { - .ops = &error_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_K8T800_ERR, -}; - -static const struct pci_driver northbridge_driver_m800 __pci_driver = { - .ops = &error_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_K8M800_ERR, -}; - -static const struct pci_driver northbridge_driver_t890 __pci_driver = { - .ops = &error_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_K8T890CE_1, -}; - -static const struct pci_driver northbridge_driver_tcf __pci_driver = { - .ops = &error_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_K8T890CF_1, +static const unsigned short error_ids[] = { + PCI_DEVICE_ID_VIA_K8T800_ERR, + PCI_DEVICE_ID_VIA_K8M800_ERR, + PCI_DEVICE_ID_VIA_K8T890CE_1, + PCI_DEVICE_ID_VIA_K8T890CF_1, + PCI_DEVICE_ID_VIA_K8M890CE_1, + 0 }; -static const struct pci_driver northbridge_driver_m __pci_driver = { +static const struct pci_driver northbridge_driver_t800 __pci_driver = { .ops = &error_ops, .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_K8M890CE_1, + .devices= error_ids, };

1 0

Patch set updated for coreboot: be9b76d buildsystem: Make CPU microcode updating more configurable
by Alexandru Gagniuc 26 Jul '12

26 Jul '12

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1245 -gerrit commit be9b76dd8b5926832df76b7964f238953124756b Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Fri Jul 20 00:11:21 2012 -0500 buildsystem: Make CPU microcode updating more configurable This patch aims to improve the microcode in CBFS handling that was brought by the last patches from Stefan and the Chromium team. choices in Kconfig - 1) Generate microcode from tree (default) - 2) Include external microcode file - 3) Do not put microcode in CBFS The idea is to give the user full control over including non-free blobs in the final ROM image. MICROCODE_INCLUDE_PATH Kconfig variable is eliminated. Microcode is handled by a special class, cpu_microcode, as such: cpu_microcode-y += microcode_file.c These files are then be compiled and assembled into a binary CBFS file. the advantage of doing it this way versus the current method is that 1) The rule is CPU-agnostic 2) This rule can work with no Kconfig variables. We use vars to respect the user's choice, and intel microcode updating still requires CPU_MICROCODE_IN_CBFS. 3) When cpu_microcode-y is not specified, no microcode file is created 4) The rules for building the microcode binary are kept in src/cpu/Makefile.inc, and thus would not clobber the other makefiles, which are already overloaded and very difficult to navigate. Change-Id: I38d0c9851691aa112e93031860e94895857ebb76 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- Makefile.inc | 2 +- src/arch/x86/Makefile.inc | 28 ++++----- src/cpu/Kconfig | 88 ++++++++++++++++++++++++++- src/cpu/Makefile.inc | 32 ++++++++++ src/cpu/intel/microcode/Makefile.inc | 20 ++----- src/cpu/intel/microcode/microcode.c | 8 +- src/cpu/intel/microcode/microcode_blob.c | 22 ------- src/cpu/intel/model_206ax/Kconfig | 5 +- src/cpu/intel/model_206ax/Makefile.inc | 2 + src/cpu/intel/model_206ax/microcode_blob.c | 22 +++++++ src/include/cpu/intel/microcode.h | 2 +- 11 files changed, 164 insertions(+), 67 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 176ff67..4122bc4 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -59,7 +59,7 @@ subdirs-y += site-local ####################################################################### # Add source classes and their build options -classes-y := ramstage romstage driver smm +classes-y := ramstage romstage driver smm cpu_microcode romstage-c-ccopts:=-D__PRE_RAM__ romstage-S-ccopts:=-D__PRE_RAM__ diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 306f239..3b27fe3 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -1,6 +1,8 @@ +################################################################################ ## ## This file is part of the coreboot project. ## +## Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> ## Copyright (C) 2009-2010 coresystems GmbH ## Copyright (C) 2009 Ronald G. Minnich ## @@ -17,8 +19,8 @@ ## along with this program; if not, write to the Free Software ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +################################################################################ -####################################################################### # Take care of subdirectories subdirs-y += boot # subdirs-y += init @@ -34,13 +36,7 @@ cmos_layout.bin-type = 0x01aa OPTION_TABLE_H:=$(obj)/option_table.h endif -ifeq ($(CONFIG_MICROCODE_IN_CBFS),y) -cbfs-files-y += microcode_blob.bin -microcode_blob.bin-file = $(obj)/microcode_blob.bin -microcode_blob.bin-type = 0x53 -endif - -####################################################################### +################################################################################ # Build the final rom image COREBOOT_ROM_DEPENDENCIES:= ifeq ($(CONFIG_PAYLOAD_ELF),y) @@ -123,7 +119,7 @@ cbfs-files-$(CONFIG_BOOTSPLASH) += bootsplash.jpg bootsplash.jpg-file := $(call strip_quotes,$(CONFIG_BOOTSPLASH_FILE)) bootsplash.jpg-type := bootsplash -####################################################################### +################################################################################ # i386 specific tools NVRAMTOOL:=$(objutil)/nvramtool/nvramtool @@ -135,7 +131,7 @@ $(obj)/cmos_layout.bin: $(NVRAMTOOL) $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.l @printf " OPTION $(subst $(obj)/,,$(@))\n" $(NVRAMTOOL) -y $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout -L $@ -####################################################################### +################################################################################ # Common recipes for all stages $(objcbfs)/%.bin: $(objcbfs)/%.elf @@ -150,7 +146,7 @@ $(objcbfs)/%.elf: $(objcbfs)/%.debug $(OBJCOPY) --add-gnu-debuglink=$< $@.tmp mv $@.tmp $@ -####################################################################### +################################################################################ # Build the coreboot_ram (stage 2) $(objcbfs)/coreboot_ram.debug: $(objgenerated)/coreboot_ram.o $(src)/arch/x86/coreboot_ram.ld @@ -174,7 +170,7 @@ $(objgenerated)/ramstage.a: $$(ramstage-objs) rm -f $@ $(AR) cr $@ $^ -####################################################################### +################################################################################ # Ramstage for AP CPU (AMD K8, obsolete?) $(objcbfs)/coreboot_ap.debug: $(objgenerated)/coreboot_ap.o $(src)/arch/x86/init/ldscript_apc.lb @@ -185,7 +181,7 @@ $(objgenerated)/coreboot_ap.o: $(src)/mainboard/$(MAINBOARDDIR)/ap_romstage.c $( @printf " CC $(subst $(obj)/,,$(@))\n" $(CC) -MMD $(CFLAGS) -I$(src) -D__PRE_RAM__ -I. -I$(obj) -c $< -o $@ -####################################################################### +################################################################################ # done crt0s = $(src)/arch/x86/init/prologue.inc @@ -264,7 +260,7 @@ ifeq ($(CONFIG_HAVE_BUS_CONFIG),y) ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/get_bus_conf.c endif -####################################################################### +################################################################################ # Build the final rom image $(obj)/coreboot.pre: $(objcbfs)/romstage_xip.elf $(obj)/coreboot.pre1 $(CBFSTOOL) @@ -274,7 +270,7 @@ $(obj)/coreboot.pre: $(objcbfs)/romstage_xip.elf $(obj)/coreboot.pre1 $(CBFSTOOL $(CONFIG_CBFS_PREFIX)/romstage x $(shell cat $(objcbfs)/base_xip.txt) mv $@.tmp $@ -####################################################################### +################################################################################ # Build the bootblock bootblock_lds = $(src)/arch/x86/init/ldscript_failover.lb @@ -331,7 +327,7 @@ else $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/bootblock.ld $< endif -####################################################################### +################################################################################ # Build the romstage $(objcbfs)/romstage_null.debug: $$(romstage-objs) $(objgenerated)/romstage_null.ld diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index baf686e..1ed721f 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -62,10 +62,90 @@ config SSE2 streaming SIMD instructions. Some parts of coreboot can be built with more efficient code if SSE2 instructions are available. -config MICROCODE_IN_CBFS - bool "Look for microcode in CBFS" +endif # ARCH_X86 + +config CPU_MICROCODE_IN_CBFS + bool default n + +choice + prompt "Include CPU microcode in CBFS" + default CPU_MICROCODE_CBFS_GENERATE if CPU_MICROCODE_IN_CBFS + default CPU_MICROCODE_CBFS_NONE if !CPU_MICROCODE_IN_CBFS + +config CPU_MICROCODE_CBFS_GENERATE + bool "Generate from tree" help - Load microcode updates from CBFS instead of compiling them in. + Select this option if you want microcode updates to be assembled when + building coreboot and included in the final image as a separate CBFS + file. Microcode will not be hard-coded into ramstage. -endif # ARCH_X86 + The microcode file and may be removed from the ROM image at a later + time with cbfstool, if desired. + + If unsure, select this option. + +config CPU_MICROCODE_CBFS_EXTERNAL + bool "Include external microcode file" + help + Select this option if you want to include an external file containing + the CPU microcode. This will be included as a separate file in CBFS. + A word of caution: only select this option if you are sure the + microcode that you have is newer than the microcode shipping with + coreboot. + + The microcode file and may be removed from the ROM image at a later + time with cbfstool, if desired. + + If unsure, select "Generate from tree" + +config CPU_MICROCODE_FILE + string "Path and filename of CPU microcode" + depends on CPU_MICROCODE_CBFS_EXTERNAL + default "cpu_microcode.bin" + help + The path and filename of the file containing the CPU microcode. + +config CPU_MICROCODE_CBFS_NONE + bool "Do not include microcode updates" + help + Select this option if you do not want CPU microcode included in CBFS. + Note that for some CPUs, the microcode is hard-coded into the source + tree and is not loaded from CBFS. In this case, microcode will still + be updated. There is a push to move all microcode to CBFS, but this + change is not implemented for all CPUs. + + This option currently applies to: + - Intel SandyBridge/IvyBridge + - VIA Nano + + Microcode may be added to the ROM image at a later time with cbfstool, + if desired. + + If unsure, select "Generate from tree" + + The GOOD: + Microcode updates intend to solve issues that have been discovered + after CPU production. The expected effect is that systems work as + intended with the updated microcode, but we have also seen cases where + issues were solved by not applying microcode updates. + + The BAD: + Note that some operating system include these same microcode patches, + so you may need to also disable microcode updates in your operating + system for this option to have an effect. + + The UGLY: + A word of CAUTION: some CPUs depend on microcode updates to function + correctly. Not updating the microcode may leave the CPU operating at + less than optimal performance, or may cause outright hangups. + There are CPUs where coreboot cannot properly initialize the CPU + without microcode updates + For example, if running with the factory microcode, some Intel + SandyBridge CPUs may hang when enabling CAR, or some VIA Nano CPUs + will hang when changing the frequency. + + Make sure you have a way of flashing the ROM externally before + selecting this option. + +endchoice diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc index 57273cf..033e3f8 100644 --- a/src/cpu/Makefile.inc +++ b/src/cpu/Makefile.inc @@ -1,3 +1,35 @@ +################################################################################ +## Subdirectories +################################################################################ subdirs-y += amd subdirs-y += intel subdirs-y += via + +################################################################################ +## Rules for building the microcode blob in CBFS +################################################################################ + +ifneq ($(CONFIG_CPU_MICROCODE_CBFS_NONE), y) + +cbfs-files-y += cpu_microcode_blob.bin + +cpu_microcode_blob.bin-type = 0x53 + +# External microcode file, or are we generating one ? +ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL), y) + cpu_microcode_blob.bin-file = $(CONFIG_CPU_MICROCODE_FILE) +else + cpu_microcode_blob.bin-file = $(obj)/cpu_microcode_blob.bin +endif + +$(obj)/cpu_microcode_blob.o: $$(cpu_microcode-objs) + @printf " CACAVACA $< -> $@ \n" + $(warning $(cpu_microcode-objs)) + $(warning $$(cpu_microcode-objs)) + cat $< > $@ + +$(obj)/cpu_microcode_blob.bin: $(obj)/cpu_microcode_blob.o + @printf " MICROCODE $(subst $(obj)/,,$(@))\n" + $(OBJCOPY) -j .data -O binary $< $@ + +endif \ No newline at end of file diff --git a/src/cpu/intel/microcode/Makefile.inc b/src/cpu/intel/microcode/Makefile.inc index f4d0102..22655c9 100644 --- a/src/cpu/intel/microcode/Makefile.inc +++ b/src/cpu/intel/microcode/Makefile.inc @@ -1,15 +1,5 @@ -ramstage-y += microcode.c - - -ifeq ($(CONFIG_MICROCODE_IN_CBFS),y) - -SRC_PATH = src/cpu/intel/microcode -FLAGS = -I $(CONFIG_MICROCODE_INCLUDE_PATH) -include $(obj)/config.h -$(obj)/microcode_blob.o: $(SRC_PATH)/microcode_blob.c - $(CC) $(FLAGS) -MMD -c -o $@ $< - -$(obj)/microcode_blob.bin: $(obj)/microcode_blob.o - objcopy -j .data -O binary $< $@ - --include $(obj)/microcode_blob.d -endif +################################################################################ +## One small file with the awesome super-power of updating the cpu microcode +## directly from CBFS. You have been WARNED!!! +################################################################################ +ramstage-y += microcode.c \ No newline at end of file diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index e84bad9..a4471ca 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -28,7 +28,7 @@ #include <cpu/x86/msr.h> #include <cpu/intel/microcode.h> -#if CONFIG_MICROCODE_IN_CBFS +#if CONFIG_CPU_MICROCODE_IN_CBFS #ifdef __PRE_RAM__ #include <arch/cbfs.h> #else @@ -77,7 +77,7 @@ static inline u32 read_microcode_rev(void) return msr.hi; } -#if CONFIG_MICROCODE_IN_CBFS +#if CONFIG_CPU_MICROCODE_IN_CBFS static #endif void intel_update_microcode(const void *microcode_updates) @@ -144,9 +144,9 @@ void intel_update_microcode(const void *microcode_updates) } } -#if CONFIG_MICROCODE_IN_CBFS +#if CONFIG_CPU_MICROCODE_IN_CBFS -#define MICROCODE_CBFS_FILE "microcode_blob.bin" +#define MICROCODE_CBFS_FILE "cpu_microcode_blob.bin" void intel_update_microcode_from_cbfs(void) { diff --git a/src/cpu/intel/microcode/microcode_blob.c b/src/cpu/intel/microcode/microcode_blob.c deleted file mode 100644 index 69238a9..0000000 --- a/src/cpu/intel/microcode/microcode_blob.c +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -unsigned microcode[] = { -#include <microcode_blob.h> -}; diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index 071683e..1b4351e 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -12,7 +12,7 @@ config CPU_SPECIFIC_OPTIONS select SSE2 select UDELAY_LAPIC select SMM_TSEG - select MICROCODE_IN_CBFS + select CPU_MICROCODE_IN_CBFS config BOOTBLOCK_CPU_INIT string @@ -22,9 +22,6 @@ config SMM_TSEG_SIZE hex default 0x800000 -config MICROCODE_INCLUDE_PATH - string - default "src/cpu/intel/model_206ax" endif if CPU_INTEL_MODEL_206AX diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc index e9b8e6d..6ab4840 100644 --- a/src/cpu/intel/model_206ax/Makefile.inc +++ b/src/cpu/intel/model_206ax/Makefile.inc @@ -5,4 +5,6 @@ ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c +cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c + cpu_incs += $(src)/cpu/intel/model_206ax/cache_as_ram.inc diff --git a/src/cpu/intel/model_206ax/microcode_blob.c b/src/cpu/intel/model_206ax/microcode_blob.c new file mode 100644 index 0000000..c2538e8 --- /dev/null +++ b/src/cpu/intel/model_206ax/microcode_blob.c @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +unsigned microcode[] = { +#include "microcode_blob.h" +}; diff --git a/src/include/cpu/intel/microcode.h b/src/include/cpu/intel/microcode.h index 289e919..e9c13f9 100644 --- a/src/include/cpu/intel/microcode.h +++ b/src/include/cpu/intel/microcode.h @@ -21,7 +21,7 @@ #define __CPU__INTEL__MICROCODE__ #ifndef __PRE_RAM__ -#if CONFIG_MICROCODE_IN_CBFS +#if CONFIG_CPU_MICROCODE_IN_CBFS void intel_update_microcode_from_cbfs(void); #else void intel_update_microcode(const void *microcode_updates);

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Patch merged into coreboot/master: e5ef86a Add correct bios callout into read event routine
by gerrit＠coreboot.org 26 Jul '12

26 Jul '12

the following patch was just integrated into master: commit e5ef86aa853de415e2254db14d11d9c8ab80332f Author: zbao <fishbaozi(a)gmail.com> Date: Mon Jul 23 19:57:43 2012 +0800 Add correct bios callout into read event routine Read event routine didn't get the correct BIOS callout. So it could not get the heap address. Then it would creat many warning in serial port. Change-Id: Ia35601bda1579c7f726ed767d7be78713ac185d2 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> Build-Tested: build bot (Jenkins) at Mon Jul 23 13:26:54 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Thu Jul 26 19:09:52 2012, giving +2 See http://review.coreboot.org/1266 for details. -gerrit

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Patch merged into coreboot/master: e9063a8 ibase/mb899: Rename NIC BIOS disable driver and hook up
by gerrit＠coreboot.org 26 Jul '12

26 Jul '12

the following patch was just integrated into master: commit e9063a856dee8d681de67f3ce0ed2904ebcfbcf7 Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Thu Jul 26 11:32:50 2012 +0200 ibase/mb899: Rename NIC BIOS disable driver and hook up The board has a marvell NIC, but the driver to disable NIC BIOS was adapted from a Realtek 8168 driver. Rename to reflect the change. Also hook up as driver, so coreboot can actually find it. Change-Id: Ibdfd6074eb28ba537d68552a3346b06493cef2a6 Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> Build-Tested: build bot (Jenkins) at Thu Jul 26 12:06:41 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Thu Jul 26 19:03:43 2012, giving +2 See http://review.coreboot.org/1355 for details. -gerrit

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coreboot July 2012