coreboot July 2012

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Patch set updated for coreboot: b037189 Refactor driver structs
by Patrick Georgi 26 Jul '12

26 Jul '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1358 -gerrit commit b037189c856e1c436a19d72c829f19ae9588e049 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Thu Jul 26 19:48:23 2012 +0200 Refactor driver structs Our driver infrastructure became more flexible recently. Make use of it. These are the low hanging fruits (files with 5 device variants or more), but there are still lots of files with less potential for deduplication. Change-Id: If6b7be5046581f81485a511b150f99b029b95c3b Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/northbridge/amd/cimx/rd890/late.c | 40 +++++--------------- src/northbridge/intel/sandybridge/gma.c | 48 +++---------------------- src/southbridge/amd/rs780/gfx.c | 60 +++++++----------------------- src/southbridge/amd/sb600/usb.c | 31 +++++----------- src/southbridge/intel/i82801gx/pcie.c | 46 +++++------------------ src/southbridge/intel/i82801gx/sata.c | 56 ++++++----------------------- src/southbridge/nvidia/mcp55/lpc.c | 48 ++++++------------------- src/southbridge/nvidia/mcp55/pcie.c | 32 +++++----------- src/southbridge/via/k8t890/ctrl.c | 33 +++++------------ src/southbridge/via/k8t890/error.c | 33 +++++------------ 10 files changed, 99 insertions(+), 328 deletions(-) diff --git a/src/northbridge/amd/cimx/rd890/late.c b/src/northbridge/amd/cimx/rd890/late.c index 208e5f1..33da2b4 100644 --- a/src/northbridge/amd/cimx/rd890/late.c +++ b/src/northbridge/amd/cimx/rd890/late.c @@ -220,38 +220,18 @@ static struct device_operations ht_ops = { .ops_pci = &lops_pci, }; -static const struct pci_driver ht_driver_sr5690 __pci_driver = { - .ops = &ht_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_AMD_SR5690_HT, -}; - -static const struct pci_driver ht_driver_sr5670 __pci_driver = { - .ops = &ht_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_AMD_SR5670_HT, -}; - -static const struct pci_driver ht_driver_sr5650 __pci_driver = { - .ops = &ht_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_AMD_SR5650_HT, -}; - -static const struct pci_driver ht_driver_rd890tv __pci_driver = { - .ops = &ht_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_AMD_RD890TV_HT, +static const unsigned short driver_ids[] = { + PCI_DEVICE_ID_AMD_SR5690_HT, + PCI_DEVICE_ID_AMD_SR5670_HT, + PCI_DEVICE_ID_AMD_SR5650_HT, + PCI_DEVICE_ID_AMD_RD890TV_HT, + PCI_DEVICE_ID_AMD_RD890_HT, + PCI_DEVICE_ID_AMD_990FX_HT, + 0 }; -static const struct pci_driver ht_driver_rd890 __pci_driver = { - .ops = &ht_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_AMD_RD890_HT, -}; - -static const struct pci_driver ht_driver_990fx __pci_driver = { +static const struct pci_driver ht_driver_sr5690 __pci_driver = { .ops = &ht_ops, .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_AMD_990FX_HT, + .devices= driver_ids, }; diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index 9a8b631..c2bb2ea 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -659,50 +659,12 @@ static struct device_operations gma_func0_ops = { .ops_pci = &gma_pci_ops, }; -static const struct pci_driver gma_gt1_desktop __pci_driver = { - .ops = &gma_func0_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x0102, -}; - -static const struct pci_driver gma_gt1_mobile __pci_driver = { - .ops = &gma_func0_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x0106, +static const unsigned short gma_ids[] = { + 0x0102, 0x0106, 0x010a, 0x0112, 0x0116, 0x0122, 0x0126, 0x166, + 0, }; - -static const struct pci_driver gma_gt1_server __pci_driver = { - .ops = &gma_func0_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x010a, -}; - -static const struct pci_driver gma_gt2_desktop __pci_driver = { - .ops = &gma_func0_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x0112, -}; - -static const struct pci_driver gma_gt2_mobile __pci_driver = { - .ops = &gma_func0_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x0116, -}; - -static const struct pci_driver gma_gt2_desktop_fast __pci_driver = { - .ops = &gma_func0_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x0122, -}; - -static const struct pci_driver gma_gt2_mobile_fast __pci_driver = { +static const struct pci_driver gma_gt1_desktop __pci_driver = { .ops = &gma_func0_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x0126, -}; - -static const struct pci_driver gma_func0_driver_3 __pci_driver = { - .ops = &gma_func0_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x0166, + .devices= gma_ids, }; diff --git a/src/southbridge/amd/rs780/gfx.c b/src/southbridge/amd/rs780/gfx.c index 904e154..f70cd9b 100644 --- a/src/southbridge/amd/rs780/gfx.c +++ b/src/southbridge/amd/rs780/gfx.c @@ -1005,56 +1005,24 @@ static struct device_operations pcie_ops = { /* * We should list all of them here. * */ -static const struct pci_driver pcie_driver_780 __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_RS780_INT_GFX, +static const unsigned short pcie_780_ids[] = { + PCI_DEVICE_ID_ATI_RS780_INT_GFX, + PCI_DEVICE_ID_ATI_RS780C_INT_GFX, + PCI_DEVICE_ID_ATI_RS780M_INT_GFX, + PCI_DEVICE_ID_ATI_RS780MC_INT_GFX, + PCI_DEVICE_ID_ATI_RS780E_INT_GFX, + PCI_DEVICE_ID_ATI_RS785G_INT_GFX, + PCI_DEVICE_ID_ATI_RS785C_INT_GFX, + PCI_DEVICE_ID_ATI_RS785M_INT_GFX, + PCI_DEVICE_ID_ATI_RS785MC_INT_GFX, + PCI_DEVICE_ID_ATI_RS785D_INT_GFX, + 0 }; -static const struct pci_driver pcie_driver_780c __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_RS780C_INT_GFX, -}; -static const struct pci_driver pcie_driver_780m __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_RS780M_INT_GFX, -}; -static const struct pci_driver pcie_driver_780mc __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_RS780MC_INT_GFX, -}; -static const struct pci_driver pcie_driver_780e __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_RS780E_INT_GFX, -}; -static const struct pci_driver pcie_driver_785g __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_RS785G_INT_GFX, -}; -static const struct pci_driver pcie_driver_785c __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_RS785C_INT_GFX, -}; -static const struct pci_driver pcie_driver_785m __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_RS785M_INT_GFX, -}; -static const struct pci_driver pcie_driver_785mc __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_RS785MC_INT_GFX, -}; -static const struct pci_driver pcie_driver_785d __pci_driver = { +static const struct pci_driver pcie_driver_780 __pci_driver = { .ops = &pcie_ops, .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_RS785D_INT_GFX, + .devices = pcie_780_ids, }; /* step 12 ~ step 14 from rpr */ diff --git a/src/southbridge/amd/sb600/usb.c b/src/southbridge/amd/sb600/usb.c index 7ff8f5c..5023578 100644 --- a/src/southbridge/amd/sb600/usb.c +++ b/src/southbridge/amd/sb600/usb.c @@ -164,30 +164,19 @@ static struct device_operations usb_ops = { .ops_pci = &lops_pci, }; -static const struct pci_driver usb_0_driver __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB600_USB_0, -}; -static const struct pci_driver usb_1_driver __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB600_USB_1, -}; -static const struct pci_driver usb_2_driver __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB600_USB_2, +static const unsigned short usb_ids[] = { + PCI_DEVICE_ID_ATI_SB600_USB_0, + PCI_DEVICE_ID_ATI_SB600_USB_1, + PCI_DEVICE_ID_ATI_SB600_USB_2, + PCI_DEVICE_ID_ATI_SB600_USB_3, + PCI_DEVICE_ID_ATI_SB600_USB_4, + 0, }; -static const struct pci_driver usb_3_driver __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB600_USB_3, -}; -static const struct pci_driver usb_4_driver __pci_driver = { + +static const struct pci_driver usb_0_driver __pci_driver = { .ops = &usb_ops, .vendor = PCI_VENDOR_ID_ATI, - .device = PCI_DEVICE_ID_ATI_SB600_USB_4, + .devices= usb_ids, }; static struct device_operations usb_ops2 = { diff --git a/src/southbridge/intel/i82801gx/pcie.c b/src/southbridge/intel/i82801gx/pcie.c index d69bc6d..73bc69d 100644 --- a/src/southbridge/intel/i82801gx/pcie.c +++ b/src/southbridge/intel/i82801gx/pcie.c @@ -121,44 +121,18 @@ static struct device_operations device_ops = { .ops_pci = &pci_ops, }; -/* 82801GB/GR/GDH/GBM/GHM (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH) */ -static const struct pci_driver i82801gx_pcie_port1 __pci_driver = { - .ops = &device_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x27d0, -}; - -/* 82801GB/GR/GDH/GBM/GHM (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH) */ -static const struct pci_driver i82801gx_pcie_port2 __pci_driver = { - .ops = &device_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x27d2, -}; - -/* 82801GB/GR/GDH/GBM/GHM (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH) */ -static const struct pci_driver i82801gx_pcie_port3 __pci_driver = { - .ops = &device_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x27d4, -}; - -/* 82801GB/GR/GDH/GBM/GHM (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH) */ -static const struct pci_driver i82801gx_pcie_port4 __pci_driver = { - .ops = &device_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x27d6, -}; - -/* 82801GR/GDH/GHM (ICH7R/ICH7DH/ICH7-M DH) */ -static const struct pci_driver i82801gx_pcie_port5 __pci_driver = { - .ops = &device_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x27e0, +static const unsigned short i82801gx_pcie_ids[] = { + 0x27d0, /* 82801GB/GR/GDH/GBM/GHM (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH) */ + 0x27d2, /* 82801GB/GR/GDH/GBM/GHM (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH) */ + 0x27d4, /* 82801GB/GR/GDH/GBM/GHM (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH) */ + 0x27d6, /* 82801GB/GR/GDH/GBM/GHM (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH) */ + 0x27e0, /* 82801GR/GDH/GHM (ICH7R/ICH7DH/ICH7-M DH) */ + 0x27e2, /* 82801GR/GDH/GHM (ICH7R/ICH7DH/ICH7-M DH) */ + 0 }; -/* 82801GR/GDH/GHM (ICH7R/ICH7DH/ICH7-M DH) */ -static const struct pci_driver i82801gx_pcie_port6 __pci_driver = { +static const struct pci_driver i82801gx_pcie __pci_driver = { .ops = &device_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x27e2, + .devices= i82801gx_pcie_ids, }; diff --git a/src/southbridge/intel/i82801gx/sata.c b/src/southbridge/intel/i82801gx/sata.c index 0e7a1a7..a8d6f30 100644 --- a/src/southbridge/intel/i82801gx/sata.c +++ b/src/southbridge/intel/i82801gx/sata.c @@ -213,53 +213,19 @@ static struct device_operations sata_ops = { .ops_pci = &sata_pci_ops, }; -/* Desktop Non-AHCI and Non-RAID Mode */ -/* 82801GB/GR/GDH (ICH7/ICH7R/ICH7DH) */ -static const struct pci_driver i82801gx_sata_normal_driver __pci_driver = { - .ops = &sata_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x27c0, -}; - -/* Mobile Non-AHCI and Non-RAID Mode */ -/* 82801GBM/GHM (ICH7-M/ICH7-M DH) */ -static const struct pci_driver i82801gx_sata_mobile_normal_driver __pci_driver = { - .ops = &sata_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x27c4, -}; - - -/* NOTE: Any of the below are not properly supported yet. */ - -/* Desktop AHCI Mode */ -/* 82801GB/GR/GDH (ICH7/ICH7R/ICH7DH) */ -static const struct pci_driver i82801gx_sata_ahci_driver __pci_driver = { - .ops = &sata_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x27c1, -}; - -/* Desktop RAID mode */ -/* 82801GB/GR/GDH (ICH7/ICH7R/ICH7DH) */ -static const struct pci_driver i82801gx_sata_raid_driver __pci_driver = { - .ops = &sata_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x27c3, -}; - -/* Mobile AHCI Mode */ -/* 82801GBM/GHM (ICH7-M/ICH7-M DH) */ -static const struct pci_driver i82801gx_sata_mobile_ahci_driver __pci_driver = { - .ops = &sata_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x27c5, +static const unsigned short sata_ids[] = { + 0x27c0, /* Desktop Non-AHCI and Non-RAID Mode: 82801GB/GR/GDH (ICH7/ICH7R/ICH7DH) */ + 0x27c4, /* Mobile Non-AHCI and Non-RAID Mode: 82801GBM/GHM (ICH7-M/ICH7-M DH) */ + /* NOTE: Any of the below are not properly supported yet. */ + 0x27c1, /* Desktop AHCI Mode: 82801GB/GR/GDH (ICH7/ICH7R/ICH7DH) */ + 0x27c3, /* Desktop RAID mode: 82801GB/GR/GDH (ICH7/ICH7R/ICH7DH) */ + 0x27c5, /* Mobile AHCI Mode: 82801GBM/GHM (ICH7-M/ICH7-M DH) */ + 0x27c6, /* ICH7M DH Raid Mode: 82801GHM (ICH7-M DH) */ + 0 }; -/* ICH7M DH Raid Mode */ -/* 82801GHM (ICH7-M DH) */ -static const struct pci_driver i82801gx_sata_ich7dh_raid_driver __pci_driver = { +static const struct pci_driver i82801gx_sata_driver __pci_driver = { .ops = &sata_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x27c6, + .devices= sata_ids, }; diff --git a/src/southbridge/nvidia/mcp55/lpc.c b/src/southbridge/nvidia/mcp55/lpc.c index 9ea1923..d16e3cc 100644 --- a/src/southbridge/nvidia/mcp55/lpc.c +++ b/src/southbridge/nvidia/mcp55/lpc.c @@ -260,46 +260,20 @@ static struct device_operations lpc_ops = { // .enable = mcp55_enable, .ops_pci = &mcp55_pci_ops, }; -static const struct pci_driver lpc_driver __pci_driver = { - .ops = &lpc_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_MCP55_LPC, -}; - -static const struct pci_driver lpc_driver_pro __pci_driver = { - .ops = &lpc_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_MCP55_PRO, +static const unsigned short lpc_ids[] = { + PCI_DEVICE_ID_NVIDIA_MCP55_LPC, + PCI_DEVICE_ID_NVIDIA_MCP55_PRO, + PCI_DEVICE_ID_NVIDIA_MCP55_LPC_2, + PCI_DEVICE_ID_NVIDIA_MCP55_LPC_3, + PCI_DEVICE_ID_NVIDIA_MCP55_LPC_4, + PCI_DEVICE_ID_NVIDIA_MCP55_LPC_5, + PCI_DEVICE_ID_NVIDIA_MCP55_LPC_6, + 0 }; - -static const struct pci_driver lpc_driver_lpc2 __pci_driver = { - .ops = &lpc_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_MCP55_LPC_2, -}; - -static const struct pci_driver lpc_driver_lpc3 __pci_driver = { - .ops = &lpc_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_MCP55_LPC_3, -}; - -static const struct pci_driver lpc_driver_lpc4 __pci_driver = { - .ops = &lpc_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_MCP55_LPC_4, -}; - -static const struct pci_driver lpc_driver_lpc5 __pci_driver = { - .ops = &lpc_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_MCP55_LPC_5, -}; - -static const struct pci_driver lpc_driver_lpc6 __pci_driver = { +static const struct pci_driver lpc_driver __pci_driver = { .ops = &lpc_ops, .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_MCP55_LPC_6, + .devices = lpc_ids, }; static struct device_operations lpc_slave_ops = { diff --git a/src/southbridge/nvidia/mcp55/pcie.c b/src/southbridge/nvidia/mcp55/pcie.c index cd43f87..108a9b1 100644 --- a/src/southbridge/nvidia/mcp55/pcie.c +++ b/src/southbridge/nvidia/mcp55/pcie.c @@ -50,29 +50,17 @@ static struct device_operations pcie_ops = { // .enable = mcp55_enable, }; -static const struct pci_driver pciebc_driver __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_B_C, -}; -static const struct pci_driver pciee_driver __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_E, +static const unsigned short pcie_ids[] = { + PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_B_C, + PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_E, + PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_A, + PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_F, + PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_D, + 0 }; -static const struct pci_driver pciea_driver __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_A, -}; -static const struct pci_driver pcief_driver __pci_driver = { - .ops = &pcie_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_F, -}; -static const struct pci_driver pcied_driver __pci_driver = { + +static const struct pci_driver pciebc_driver __pci_driver = { .ops = &pcie_ops, .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_D, + .devices= pcie_ids, }; - diff --git a/src/southbridge/via/k8t890/ctrl.c b/src/southbridge/via/k8t890/ctrl.c index fc851f8..3b92493 100644 --- a/src/southbridge/via/k8t890/ctrl.c +++ b/src/southbridge/via/k8t890/ctrl.c @@ -193,32 +193,17 @@ static const struct device_operations ctrl_ops = { .ops_pci = &lops_pci, }; -static const struct pci_driver northbridge_driver_t800 __pci_driver = { - .ops = &ctrl_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_K8T800_NB_SB_CTR, -}; - -static const struct pci_driver northbridge_driver_m800 __pci_driver = { - .ops = &ctrl_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_K8M800_NB_SB_CTR, -}; - -static const struct pci_driver northbridge_driver_t890 __pci_driver = { - .ops = &ctrl_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_K8T890CE_7, -}; - -static const struct pci_driver northbridge_driver_t890cf __pci_driver = { - .ops = &ctrl_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_K8T890CF_7, +static const unsigned short ctrl_ids[] = { + PCI_DEVICE_ID_VIA_K8T800_NB_SB_CTR, + PCI_DEVICE_ID_VIA_K8M800_NB_SB_CTR, + PCI_DEVICE_ID_VIA_K8T890CE_7, + PCI_DEVICE_ID_VIA_K8T890CF_7, + PCI_DEVICE_ID_VIA_K8M890CE_7, + 0 }; -static const struct pci_driver northbridge_driver_m890 __pci_driver = { +static const struct pci_driver northbridge_driver_t800 __pci_driver = { .ops = &ctrl_ops, .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_K8M890CE_7, + .devices= ctrl_ids, }; diff --git a/src/southbridge/via/k8t890/error.c b/src/southbridge/via/k8t890/error.c index 1f6979a..846ccfb 100644 --- a/src/southbridge/via/k8t890/error.c +++ b/src/southbridge/via/k8t890/error.c @@ -53,32 +53,17 @@ static const struct device_operations error_ops = { .ops_pci = &lops_pci, }; -static const struct pci_driver northbridge_driver_t800 __pci_driver = { - .ops = &error_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_K8T800_ERR, -}; - -static const struct pci_driver northbridge_driver_m800 __pci_driver = { - .ops = &error_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_K8M800_ERR, -}; - -static const struct pci_driver northbridge_driver_t890 __pci_driver = { - .ops = &error_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_K8T890CE_1, -}; - -static const struct pci_driver northbridge_driver_tcf __pci_driver = { - .ops = &error_ops, - .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_K8T890CF_1, +static const unsigned short error_ids[] = { + PCI_DEVICE_ID_VIA_K8T800_ERR, + PCI_DEVICE_ID_VIA_K8M800_ERR, + PCI_DEVICE_ID_VIA_K8T890CE_1, + PCI_DEVICE_ID_VIA_K8T890CF_1, + PCI_DEVICE_ID_VIA_K8M890CE_1, + 0 }; -static const struct pci_driver northbridge_driver_m __pci_driver = { +static const struct pci_driver northbridge_driver_t800 __pci_driver = { .ops = &error_ops, .vendor = PCI_VENDOR_ID_VIA, - .device = PCI_DEVICE_ID_VIA_K8M890CE_1, + .devices= error_ids, };

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Patch merged into coreboot/master: 5cd8eeb CTDP: Only do TDP down/nominal change from TNP0
by gerrit＠coreboot.org 26 Jul '12

26 Jul '12

the following patch was just integrated into master: commit 5cd8eeb6fe2e2415794a551383afc68465a677a8 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed Jul 18 15:33:45 2012 -0700 CTDP: Only do TDP down/nominal change from TNP0 Otherwise there is a flurry of TDP changes with suspend/resume as the kernel powers devices off on suspend and brings them back online in resume. This also adds a mutex around the TDP operations since it is split across two methods and can't just rely on being Serialized. Change-Id: I7757d3ddad34ac985a9c8ce2fc202e2b2dcb2527 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Build-Tested: build bot (Jenkins) at Thu Jul 26 21:09:24 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Thu Jul 26 21:12:31 2012, giving +2 See http://review.coreboot.org/1348 for details. -gerrit

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Patch set updated for coreboot: b9eea92 bd82x6x: Use CMOS variable if available for power-on on power failure
by Stefan Reinauer 26 Jul '12

26 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1324 -gerrit commit b9eea92bd0015ce9d3fc461ec89cbcd2c4467912 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Jun 28 12:22:28 2012 -0700 bd82x6x: Use CMOS variable if available for power-on on power failure We used a hard coded value for some reason. Don't do that, but use CMOS instead. Modelled after http://review.coreboot.org/#/c/443 to get bd82x6x in sync. Change-Id: I36d715310157b9f9074f2a1c80710f85833020b4 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/southbridge/intel/bd82x6x/smihandler.c | 14 ++++++++++---- 1 files changed, 10 insertions(+), 4 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index 29f1a1e..da5b52b 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -29,6 +29,7 @@ #include <device/pci_def.h> #include <cpu/x86/smm.h> #include <elog.h> +#include <pc80/mc146818rtc.h> #include "pch.h" #include "nvs.h" @@ -324,11 +325,16 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat u8 reg8; u32 reg32; u8 slp_typ; - /* FIXME: the power state on boot should be read from - * CMOS or even better from GNVS. Right now it's hard - * coded at compile time. - */ u8 s5pwr = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + + // save and recover RTC port values + u8 tmp70, tmp72; + tmp70 = inb(0x70); + tmp72 = inb(0x72); + get_option(&s5pwr, "power_on_after_fail"); + outb(tmp70, 0x70); + outb(tmp72, 0x72); + void (*mainboard_sleep)(u8 slp_typ) = mainboard_smi_sleep; /* First, disable further SMIs */

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Patch set updated for coreboot: 5cd8eeb CTDP: Only do TDP down/nominal change from TNP0
by Ronald G. Minnich 26 Jul '12

26 Jul '12

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1348 -gerrit commit 5cd8eeb6fe2e2415794a551383afc68465a677a8 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed Jul 18 15:33:45 2012 -0700 CTDP: Only do TDP down/nominal change from TNP0 Otherwise there is a flurry of TDP changes with suspend/resume as the kernel powers devices off on suspend and brings them back online in resume. This also adds a mutex around the TDP operations since it is split across two methods and can't just rely on being Serialized. Change-Id: I7757d3ddad34ac985a9c8ce2fc202e2b2dcb2527 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- .../intel/sandybridge/acpi/hostbridge.asl | 30 ++++++++++++++++---- 1 files changed, 24 insertions(+), 6 deletions(-) diff --git a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl index 8dd1de6..93db98d 100644 --- a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl +++ b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl @@ -101,6 +101,8 @@ Device (MCHC) TLUD, 32, } + Mutex (CTCM, 1) /* CTDP Switch Mutex (sync level 1) */ + Name (CTCC, 0) /* CTDP Current Selection */ Name (CTCN, 0) /* CTDP Nominal Select */ Name (CTCD, 1) /* CTDP Down Select */ Name (CTCU, 2) /* CTDP Up Select */ @@ -167,12 +169,16 @@ Device (MCHC) /* Set TDP Down */ Method (STND, 0, Serialized) { - Store ("Set TDP Down", Debug) - - If (LEqual (CTCD, CTCS)) { + If (Acquire (CTCM, 100)) { + Return (0) + } + If (LEqual (CTCD, CTCC)) { + Release (CTCM) Return (0) } + Store ("Set TDP Down", Debug) + /* Set CTC */ Store (CTCD, CTCS) @@ -189,18 +195,26 @@ Device (MCHC) /* Set PL1 */ Store (CTDD, PL1V) + /* Store the new TDP Down setting */ + Store (CTCD, CTCC) + + Release (CTCM) Return (1) } /* Set TDP Nominal from Down */ Method (STDN, 0, Serialized) { - Store ("Set TDP Nominal", Debug) - - If (LEqual (CTCN, CTCS)) { + If (Acquire (CTCM, 100)) { + Return (0) + } + If (LEqual (CTCN, CTCC)) { + Release (CTCM) Return (0) } + Store ("Set TDP Nominal", Debug) + /* Set PL1 */ Store (CTDN, PL1V) @@ -217,6 +231,10 @@ Device (MCHC) /* Set CTC */ Store (CTCN, CTCS) + /* Store the new TDP Nominal setting */ + Store (CTCN, CTCC) + + Release (CTCM) Return (1) } }

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Patch merged into coreboot/master: a8d447a ELOG: Fix reporting of developer/recovery modes
by gerrit＠coreboot.org 26 Jul '12

26 Jul '12

the following patch was just integrated into master: commit a8d447a324ef126fab9dce1d1f8268fb97d24b72 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Jul 16 12:47:45 2012 -0700 ELOG: Fix reporting of developer/recovery modes Recent changes in EC/Vboot/U-boot have completely broken the logging of developer and recovery modes. Recovery mode may not be in VBNV, so if that is zero and yet we are in recovery mode then assume it is there because the button/key was pressed. Since there may not be any actual developer mode switch we look if option rom is loaded and the system is not in recovery mode and consider that as developer mode. Change-Id: I70104877b24de477217e1ff5b3a019aef22343ec Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Build-Tested: build bot (Jenkins) at Wed Jul 25 04:51:17 2012, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Thu Jul 26 20:34:12 2012, giving +2 See http://review.coreboot.org/1346 for details. -gerrit

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Patch merged into coreboot/master: 369ab60 Log event for abnormal management engine status
by gerrit＠coreboot.org 26 Jul '12

26 Jul '12

the following patch was just integrated into master: commit 369ab60207dd36c3072ed86939143809bc7d6bae Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri Jul 13 10:11:54 2012 -0700 Log event for abnormal management engine status This will log if the ME is disabled or has an error. 1) disable ME via EC console: gpioset PCH_HDA_SDO 1 2) boot the device 3) read eventlog with "mosys eventlog list" 71 | 2012-07-13 10:10:55 | Management Engine | Disabled Change-Id: I9f6ee452d2aea76e6a5ea2cd50a50ff36245692a Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Build-Tested: build bot (Jenkins) at Wed Jul 25 04:37:05 2012, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Thu Jul 26 20:33:44 2012, giving +2 See http://review.coreboot.org/1345 for details. -gerrit

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Patch merged into coreboot/master: 8b58555 ACPI: Add support for runtime config TDP down
by gerrit＠coreboot.org 26 Jul '12

26 Jul '12

the following patch was just integrated into master: commit 8b58555a396576d2ab85e0e724ca8cfd679bddfd Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Jul 16 12:27:42 2012 -0700 ACPI: Add support for runtime config TDP down The required power MSRs are mirrored in MCHBAR so it is possible to configure TDP at runtime via ASL. This adds the required fields and a set of methods to configure "TDP down" and "TDP nominal". It explicitly does not support "TDP up" at the moment. PSSS: method is added to assist in searching the _PSS table for the appropriate entry that corresponds to the desired max non-turbo ratio. STND: Set TDP Down from Nominal. This will limit CPU to the TDP down configuration by sequencing the required changes in the right order. STDN: Set TDP Nominal from Down. This will set the CPU back to nominal configuration by sequencing the required changes in the correct (reverse) order. This does not introduce any functional changes and must be paired with additional changes to be useful. The current configured TDP can be checked to see that the transition to/from a desired level is successful. > mmio_read8 0xfed15f50 0x00 # TDP-Nominal > mmio_read8 0xfed15f50 0x01 # TDP-Down Change-Id: I31a2f30cc9d134cc5eee980ae9288ae45e71c6e6 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Build-Tested: build bot (Jenkins) at Wed Jul 25 04:23:22 2012, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Thu Jul 26 20:33:05 2012, giving +2 See http://review.coreboot.org/1344 for details. -gerrit

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Patch merged into coreboot/master: fa4e269 CPU: Add option to set TCC activation offset
by gerrit＠coreboot.org 26 Jul '12

26 Jul '12

the following patch was just integrated into master: commit fa4e269220a4c7d1ec5b03da23420bb7fc744646 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Jul 16 12:19:00 2012 -0700 CPU: Add option to set TCC activation offset The default TCC activation offset is 0, which means TCC activation starts at Tj_max. For devices with limited cooling ability it may be desired to lower TCC activation. This adds an option that can be declared in the devicetree to set the TCC activation to a non-zero value. Enable tcc_offset=15 in devicetree.cb and build/boot the BIOS and check that the value is set in the MSR: > and $(shr $(rdmsr 0 0x1a2) 24) 0xf 0xf Change-Id: I88f6857b40fd354f70fa9d5d9c1d8ceaea6dfcd1 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Build-Tested: build bot (Jenkins) at Wed Jul 25 04:09:34 2012, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Thu Jul 26 20:32:44 2012, giving +2 See http://review.coreboot.org/1343 for details. -gerrit

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Patch merged into coreboot/master: b69c7c9 ACPI: Add a method to notify OS to re-read _PPC
by gerrit＠coreboot.org 26 Jul '12

26 Jul '12

the following patch was just integrated into master: commit b69c7c9ecf211352131ab37172cf7e9ebddc9af3 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Jul 16 12:14:49 2012 -0700 ACPI: Add a method to notify OS to re-read _PPC Split this behavior out from PNOT() so the OS can update _PPC limit without re-reading C-state tables. Change-Id: I81b9111a4866f6b9916f74ac57a3caefaa77c565 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Build-Tested: build bot (Jenkins) at Wed Jul 25 03:55:00 2012, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Thu Jul 26 20:32:10 2012, giving +2 See http://review.coreboot.org/1342 for details. -gerrit

1 0

Patch merged into coreboot/master: 1eb5629 ACPI: Add function to write _PPC using NVS
by gerrit＠coreboot.org 26 Jul '12

26 Jul '12

the following patch was just integrated into master: commit 1eb5629e24af2b52941848d57ae251565b5dc207 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Jul 16 12:11:53 2012 -0700 ACPI: Add function to write _PPC using NVS The existing NVS variable for PPCM will be used to select a dynamic max P-state. By itself this does not change existing behavior because the NVS PPCM variable is initialized to zero. PPCM can be tested by building and booting a modified BIOS that sets gnvs->ppcm to a value greater than 1 and checking from the OS that the P-state is limited to that value. Change-Id: Ia7b3bbc6b84c1aa42349bb236abee5cc92486561 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Build-Tested: build bot (Jenkins) at Wed Jul 25 03:40:26 2012, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Thu Jul 26 20:31:51 2012, giving +2 See http://review.coreboot.org/1341 for details. -gerrit

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coreboot July 2012