coreboot July 2012

coreboot@coreboot.org

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Patch set updated for coreboot: 6577cf8 Drop CONFIG_CPU_MODEL_NAME and fix CPU name displayed in logs
by Patrick Georgi 26 Jul '12

26 Jul '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1335 -gerrit commit 6577cf8133240029a256d8bee19e078ffdb5292e Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Jul 10 17:13:04 2012 -0700 Drop CONFIG_CPU_MODEL_NAME and fix CPU name displayed in logs On SandyBridge systems configured to work with Panther Point the CPU would wrongly be described as IvyBridge. Fix this issue and drop an unneeded Kconfig variable at the same time. Change-Id: I501a4fa00613e589cd315cfee61b2f9561dfcb4d Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/cpu/intel/model_206ax/Kconfig | 12 ------------ src/cpu/intel/model_206ax/acpi.c | 2 +- 2 files changed, 1 insertions(+), 13 deletions(-) diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index 071683e..effcdd1 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -26,15 +26,3 @@ config MICROCODE_INCLUDE_PATH string default "src/cpu/intel/model_206ax" endif - -if CPU_INTEL_MODEL_206AX - config CPU_MODEL_NAME - string - default "Intel SandyBridge CPU" -endif - -if CPU_INTEL_MODEL_306AX - config CPU_MODEL_NAME - string - default "Intel IvyBridge CPU" -endif diff --git a/src/cpu/intel/model_206ax/acpi.c b/src/cpu/intel/model_206ax/acpi.c index 7b49555..9784c47 100644 --- a/src/cpu/intel/model_206ax/acpi.c +++ b/src/cpu/intel/model_206ax/acpi.c @@ -362,5 +362,5 @@ void generate_cpu_entries(void) } struct chip_operations cpu_intel_model_206ax_ops = { - CHIP_NAME(CONFIG_CPU_MODEL_NAME) + CHIP_NAME("Intel SandyBridge/IvyBridge CPU") };

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Patch set updated for coreboot: 099a348 RFC: buildsystem: Make CPU microcode updating more configurable
by Alexandru Gagniuc 26 Jul '12

26 Jul '12

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1245 -gerrit commit 099a348a717580a04228d92ad59435f0887f2908 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Fri Jul 20 00:11:21 2012 -0500 RFC: buildsystem: Make CPU microcode updating more configurable This patch aims to improve the microcode in CBFS handling that was implemented in the last patches from Stefan and the Chromium team. When the CPU selects MICROCODE_IN_CBFS, the user is given three choices in Kconfig - 1) Generate microcode from tree (default) - 2) Include external microcode file - 3) Do not put microcode in CBFS The idea is to give the user full control over including non-free blobs in the final ROM image. The idea is to create a special class, cpu_microcode, which we can use to specify microcode files as such: cpu_microcode-y += microcode_file.c These files would then be compiled and assembled into a binary CBFS file. the advantage of doing it this way versus the current method is that 1) The rule is CPU-agnostic 2) The only Kconfig variable needed by the CPU is CPU_MICROCODE_IN_CBFS, which will later be eliminated as all CPUs are converted to CBFS loading 3) We sould be able to eliminate cpu_microcode_blob.bin as a dependency when no cpu_microcode-y is specified, thus eliminating the need for CPU_MICROCODE_IN_CBFS. 4) The rules for building the microcode binary are kept in src/cpu/Makefile.inc, and thus would not clobber the other makefiles, which are already overloaded and very difficult to navigate. The implementation is at the moment, clumsy and disfunctional. Suggestions are welcome. Change-Id: I38d0c9851691aa112e93031860e94895857ebb76 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- Makefile.inc | 2 +- src/arch/x86/Makefile.inc | 28 ++++----- src/cpu/Kconfig | 88 ++++++++++++++++++++++++++- src/cpu/Makefile.inc | 28 +++++++++ src/cpu/intel/microcode/Makefile.inc | 20 ++----- src/cpu/intel/microcode/microcode.c | 8 +- src/cpu/intel/microcode/microcode_blob.c | 22 ------- src/cpu/intel/model_206ax/Kconfig | 5 +- src/cpu/intel/model_206ax/Makefile.inc | 2 + src/cpu/intel/model_206ax/microcode_blob.c | 22 +++++++ src/include/cpu/intel/microcode.h | 2 +- 11 files changed, 160 insertions(+), 67 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 176ff67..4122bc4 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -59,7 +59,7 @@ subdirs-y += site-local ####################################################################### # Add source classes and their build options -classes-y := ramstage romstage driver smm +classes-y := ramstage romstage driver smm cpu_microcode romstage-c-ccopts:=-D__PRE_RAM__ romstage-S-ccopts:=-D__PRE_RAM__ diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 306f239..3b27fe3 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -1,6 +1,8 @@ +################################################################################ ## ## This file is part of the coreboot project. ## +## Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> ## Copyright (C) 2009-2010 coresystems GmbH ## Copyright (C) 2009 Ronald G. Minnich ## @@ -17,8 +19,8 @@ ## along with this program; if not, write to the Free Software ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +################################################################################ -####################################################################### # Take care of subdirectories subdirs-y += boot # subdirs-y += init @@ -34,13 +36,7 @@ cmos_layout.bin-type = 0x01aa OPTION_TABLE_H:=$(obj)/option_table.h endif -ifeq ($(CONFIG_MICROCODE_IN_CBFS),y) -cbfs-files-y += microcode_blob.bin -microcode_blob.bin-file = $(obj)/microcode_blob.bin -microcode_blob.bin-type = 0x53 -endif - -####################################################################### +################################################################################ # Build the final rom image COREBOOT_ROM_DEPENDENCIES:= ifeq ($(CONFIG_PAYLOAD_ELF),y) @@ -123,7 +119,7 @@ cbfs-files-$(CONFIG_BOOTSPLASH) += bootsplash.jpg bootsplash.jpg-file := $(call strip_quotes,$(CONFIG_BOOTSPLASH_FILE)) bootsplash.jpg-type := bootsplash -####################################################################### +################################################################################ # i386 specific tools NVRAMTOOL:=$(objutil)/nvramtool/nvramtool @@ -135,7 +131,7 @@ $(obj)/cmos_layout.bin: $(NVRAMTOOL) $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.l @printf " OPTION $(subst $(obj)/,,$(@))\n" $(NVRAMTOOL) -y $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout -L $@ -####################################################################### +################################################################################ # Common recipes for all stages $(objcbfs)/%.bin: $(objcbfs)/%.elf @@ -150,7 +146,7 @@ $(objcbfs)/%.elf: $(objcbfs)/%.debug $(OBJCOPY) --add-gnu-debuglink=$< $@.tmp mv $@.tmp $@ -####################################################################### +################################################################################ # Build the coreboot_ram (stage 2) $(objcbfs)/coreboot_ram.debug: $(objgenerated)/coreboot_ram.o $(src)/arch/x86/coreboot_ram.ld @@ -174,7 +170,7 @@ $(objgenerated)/ramstage.a: $$(ramstage-objs) rm -f $@ $(AR) cr $@ $^ -####################################################################### +################################################################################ # Ramstage for AP CPU (AMD K8, obsolete?) $(objcbfs)/coreboot_ap.debug: $(objgenerated)/coreboot_ap.o $(src)/arch/x86/init/ldscript_apc.lb @@ -185,7 +181,7 @@ $(objgenerated)/coreboot_ap.o: $(src)/mainboard/$(MAINBOARDDIR)/ap_romstage.c $( @printf " CC $(subst $(obj)/,,$(@))\n" $(CC) -MMD $(CFLAGS) -I$(src) -D__PRE_RAM__ -I. -I$(obj) -c $< -o $@ -####################################################################### +################################################################################ # done crt0s = $(src)/arch/x86/init/prologue.inc @@ -264,7 +260,7 @@ ifeq ($(CONFIG_HAVE_BUS_CONFIG),y) ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/get_bus_conf.c endif -####################################################################### +################################################################################ # Build the final rom image $(obj)/coreboot.pre: $(objcbfs)/romstage_xip.elf $(obj)/coreboot.pre1 $(CBFSTOOL) @@ -274,7 +270,7 @@ $(obj)/coreboot.pre: $(objcbfs)/romstage_xip.elf $(obj)/coreboot.pre1 $(CBFSTOOL $(CONFIG_CBFS_PREFIX)/romstage x $(shell cat $(objcbfs)/base_xip.txt) mv $@.tmp $@ -####################################################################### +################################################################################ # Build the bootblock bootblock_lds = $(src)/arch/x86/init/ldscript_failover.lb @@ -331,7 +327,7 @@ else $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/bootblock.ld $< endif -####################################################################### +################################################################################ # Build the romstage $(objcbfs)/romstage_null.debug: $$(romstage-objs) $(objgenerated)/romstage_null.ld diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index baf686e..daf8083 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -62,10 +62,90 @@ config SSE2 streaming SIMD instructions. Some parts of coreboot can be built with more efficient code if SSE2 instructions are available. -config MICROCODE_IN_CBFS - bool "Look for microcode in CBFS" +endif # ARCH_X86 + +config CPU_MICROCODE_IN_CBFS + bool default n + +choice + prompt "Include CPU microcode in CBFS" + default CPU_MICROCODE_CBFS_GENERATE + depends on CPU_MICROCODE_IN_CBFS + +config CPU_MICROCODE_CBFS_GENERATE + bool "Generate from tree" help - Load microcode updates from CBFS instead of compiling them in. + Select this option if you want microcode updates to be assembled when + building coreboot and included in the final image as a separate CBFS + file. Microcode will not be hard-coded into ramstage. -endif # ARCH_X86 + The microcode file and may be removed from the ROM image at a later + time with cbfstool, if desired. + + If unsure, select this option. + +config CPU_MICROCODE_CBFS_EXTERNAL + bool "Include external microcode file" + help + Select this option if you want to include an external file containing + the CPU microcode. This will be included as a separate file in CBFS. + A word of caution: only select this option if you are sure the + microcode that you have is newer than the microcode shipping with + coreboot. + + The microcode file and may be removed from the ROM image at a later + time with cbfstool, if desired. + + If unsure, select "Generate from tree" + +config CPU_MICROCODE_FILE + string "Path and filename of CPU microcode" + depends on CPU_MICROCODE_CBFS_EXTERNAL + default "cpu_microcode.bin" + help + The path and filename of the file containing the CPU microcode. + +config CPU_MICROCODE_CBFS_NONE + bool "Do not include microcode updates" + help + Select this option if you do not want CPU microcode included in CBFS. + Note that for some CPUs, the microcode is hard-coded into the source + tree and is not loaded from CBFS. In this case, microcode will still + be updated. There is a push to move all microcode to CBFS, but this + change is not implemented for all CPUs. + + This option currently applies to: + - Intel SandyBridge/IvyBridge + - VIA Nano + + Microcode may be added to the ROM image at a later time with cbfstool, + if desired. + + If unsure, select "Generate from tree" + + The GOOD: + Microcode updates intend to solve issues that have been discovered + after CPU production. The expected effect is that systems work as + intended with the updated microcode, but we have also seen cases where + issues were solved by not applying microcode updates. + + The BAD: + Note that some operating system include these same microcode patches, + so you may need to also disable microcode updates in your operating + system for this option to have an effect. + + The UGLY: + A word of CAUTION: some CPUs depend on microcode updates to function + correctly. Not updating the microcode may leave the CPU operating at + less than optimal performance, or may cause outright hangups. + There are CPUs where coreboot cannot properly initialize the CPU + without microcode updates + For example, if running with the factory microcode, some Intel + SandyBridge CPUs may hang when enabling CAR, or some VIA Nano CPUs + will hang when changing the frequency. + + Make sure you have a way of flashing the ROM externally before + selecting this option. + +endchoice diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc index 57273cf..fdece11 100644 --- a/src/cpu/Makefile.inc +++ b/src/cpu/Makefile.inc @@ -1,3 +1,31 @@ +################################################################################ +## Subdirectories +################################################################################ subdirs-y += amd subdirs-y += intel subdirs-y += via + + +################################################################################ +## Rules for building the microcode blob in CBFS +################################################################################ + +ifneq ($(CONFIG_CPU_MICROCODE_CBFS_NONE), y) +cbfs-files-y += cpu_microcode_blob.bin +cpu_microcode_blob.bin-type = 0x53 + +# External microcode file, or are we generating one ? +ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL), y) + microcode_blob.bin-file = $(CONFIG_CPU_MICROCODE_FILE) +else + cpu_microcode_blob.bin-file = $(obj)/cpu_microcode_blob.bin +endif + +$(obj)/cpu_microcode_blob.o.bin: $$(cpu_microcode-objs) + cat $< > $@ + +$(obj)/cpu_microcode_blob.bin: $(obj)/cpu_microcode_blob.o.bin + @printf " MICROCODE $(subst $(obj)/,,$(@))\n" + $(OBJCOPY) -j .data -O binary $< $@ + +endif diff --git a/src/cpu/intel/microcode/Makefile.inc b/src/cpu/intel/microcode/Makefile.inc index f4d0102..22655c9 100644 --- a/src/cpu/intel/microcode/Makefile.inc +++ b/src/cpu/intel/microcode/Makefile.inc @@ -1,15 +1,5 @@ -ramstage-y += microcode.c - - -ifeq ($(CONFIG_MICROCODE_IN_CBFS),y) - -SRC_PATH = src/cpu/intel/microcode -FLAGS = -I $(CONFIG_MICROCODE_INCLUDE_PATH) -include $(obj)/config.h -$(obj)/microcode_blob.o: $(SRC_PATH)/microcode_blob.c - $(CC) $(FLAGS) -MMD -c -o $@ $< - -$(obj)/microcode_blob.bin: $(obj)/microcode_blob.o - objcopy -j .data -O binary $< $@ - --include $(obj)/microcode_blob.d -endif +################################################################################ +## One small file with the awesome super-power of updating the cpu microcode +## directly from CBFS. You have been WARNED!!! +################################################################################ +ramstage-y += microcode.c \ No newline at end of file diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index e84bad9..a4471ca 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -28,7 +28,7 @@ #include <cpu/x86/msr.h> #include <cpu/intel/microcode.h> -#if CONFIG_MICROCODE_IN_CBFS +#if CONFIG_CPU_MICROCODE_IN_CBFS #ifdef __PRE_RAM__ #include <arch/cbfs.h> #else @@ -77,7 +77,7 @@ static inline u32 read_microcode_rev(void) return msr.hi; } -#if CONFIG_MICROCODE_IN_CBFS +#if CONFIG_CPU_MICROCODE_IN_CBFS static #endif void intel_update_microcode(const void *microcode_updates) @@ -144,9 +144,9 @@ void intel_update_microcode(const void *microcode_updates) } } -#if CONFIG_MICROCODE_IN_CBFS +#if CONFIG_CPU_MICROCODE_IN_CBFS -#define MICROCODE_CBFS_FILE "microcode_blob.bin" +#define MICROCODE_CBFS_FILE "cpu_microcode_blob.bin" void intel_update_microcode_from_cbfs(void) { diff --git a/src/cpu/intel/microcode/microcode_blob.c b/src/cpu/intel/microcode/microcode_blob.c deleted file mode 100644 index 69238a9..0000000 --- a/src/cpu/intel/microcode/microcode_blob.c +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -unsigned microcode[] = { -#include <microcode_blob.h> -}; diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index 071683e..1b4351e 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -12,7 +12,7 @@ config CPU_SPECIFIC_OPTIONS select SSE2 select UDELAY_LAPIC select SMM_TSEG - select MICROCODE_IN_CBFS + select CPU_MICROCODE_IN_CBFS config BOOTBLOCK_CPU_INIT string @@ -22,9 +22,6 @@ config SMM_TSEG_SIZE hex default 0x800000 -config MICROCODE_INCLUDE_PATH - string - default "src/cpu/intel/model_206ax" endif if CPU_INTEL_MODEL_206AX diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc index e9b8e6d..990a7fa 100644 --- a/src/cpu/intel/model_206ax/Makefile.inc +++ b/src/cpu/intel/model_206ax/Makefile.inc @@ -5,4 +5,6 @@ ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c +cpu_microcode-y += microcode_blob.c + cpu_incs += $(src)/cpu/intel/model_206ax/cache_as_ram.inc diff --git a/src/cpu/intel/model_206ax/microcode_blob.c b/src/cpu/intel/model_206ax/microcode_blob.c new file mode 100644 index 0000000..c2538e8 --- /dev/null +++ b/src/cpu/intel/model_206ax/microcode_blob.c @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +unsigned microcode[] = { +#include "microcode_blob.h" +}; diff --git a/src/include/cpu/intel/microcode.h b/src/include/cpu/intel/microcode.h index 289e919..e9c13f9 100644 --- a/src/include/cpu/intel/microcode.h +++ b/src/include/cpu/intel/microcode.h @@ -21,7 +21,7 @@ #define __CPU__INTEL__MICROCODE__ #ifndef __PRE_RAM__ -#if CONFIG_MICROCODE_IN_CBFS +#if CONFIG_CPU_MICROCODE_IN_CBFS void intel_update_microcode_from_cbfs(void); #else void intel_update_microcode(const void *microcode_updates);

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Patch set updated for coreboot: 1ae90fd RFC: buildsystem: Make CPU microcode updating more configurable
by Alexandru Gagniuc 26 Jul '12

26 Jul '12

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1245 -gerrit commit 1ae90fd40b81c25c236ee8fb637e0d2d3efefe64 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Fri Jul 20 00:11:21 2012 -0500 RFC: buildsystem: Make CPU microcode updating more configurable This patch aims to improve the microcode in CBFS handling that was implemented in the last patches from Stefan and the Chromium team. When the CPU selects MICROCODE_IN_CBFS, the user is given three choices in Kconfig - 1) Generate microcode from tree (default) - 2) Include external microcode file - 3) Do not put microcode in CBFS The idea is to give the user full control over including non-free blobs in the final ROM image. The idea is to create a special class, cpu_microcode, which we can use to specify microcode files as such: cpu_microcode-y += microcode_file.c These files would then be compiled and assembled into a binary CBFS file. the advantage of doing it this way versus the current method is that 1) The rule is CPU-agnostic 2) The only Kconfig variable needed by the CPU is CPU_MICROCODE_IN_CBFS, which will later be eliminated as all CPUs are converted to CBFS loading 3) We sould be able to eliminate cpu_microcode_blob.bin as a dependency when no cpu_microcode-y is specified, thus eliminating the need for CPU_MICROCODE_IN_CBFS. 4) The rules for building the microcode binary are kept in src/cpu/Makefile.inc, and thus would not clobber the other makefiles, which are already overloaded and very difficult to navigate. The implementation is at the moment, clumsy and disfunctional. Suggestions are welcome. Change-Id: I38d0c9851691aa112e93031860e94895857ebb76 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- Makefile.inc | 2 +- src/arch/x86/Makefile.inc | 29 +++++----- src/cpu/Kconfig | 88 ++++++++++++++++++++++++++- src/cpu/Makefile.inc | 25 ++++++++ src/cpu/intel/microcode/Makefile.inc | 20 ++----- src/cpu/intel/microcode/microcode.c | 8 +- src/cpu/intel/microcode/microcode_blob.c | 22 ------- src/cpu/intel/model_206ax/Kconfig | 5 +- src/cpu/intel/model_206ax/Makefile.inc | 2 + src/cpu/intel/model_206ax/microcode_blob.c | 22 +++++++ src/include/cpu/intel/microcode.h | 2 +- 11 files changed, 159 insertions(+), 66 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 176ff67..4122bc4 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -59,7 +59,7 @@ subdirs-y += site-local ####################################################################### # Add source classes and their build options -classes-y := ramstage romstage driver smm +classes-y := ramstage romstage driver smm cpu_microcode romstage-c-ccopts:=-D__PRE_RAM__ romstage-S-ccopts:=-D__PRE_RAM__ diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 306f239..b2e7b0e 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -1,6 +1,8 @@ +################################################################################ ## ## This file is part of the coreboot project. ## +## Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> ## Copyright (C) 2009-2010 coresystems GmbH ## Copyright (C) 2009 Ronald G. Minnich ## @@ -17,8 +19,8 @@ ## along with this program; if not, write to the Free Software ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +################################################################################ -####################################################################### # Take care of subdirectories subdirs-y += boot # subdirs-y += init @@ -34,13 +36,10 @@ cmos_layout.bin-type = 0x01aa OPTION_TABLE_H:=$(obj)/option_table.h endif -ifeq ($(CONFIG_MICROCODE_IN_CBFS),y) -cbfs-files-y += microcode_blob.bin -microcode_blob.bin-file = $(obj)/microcode_blob.bin -microcode_blob.bin-type = 0x53 -endif +################################################################################ + -####################################################################### +################################################################################ # Build the final rom image COREBOOT_ROM_DEPENDENCIES:= ifeq ($(CONFIG_PAYLOAD_ELF),y) @@ -123,7 +122,7 @@ cbfs-files-$(CONFIG_BOOTSPLASH) += bootsplash.jpg bootsplash.jpg-file := $(call strip_quotes,$(CONFIG_BOOTSPLASH_FILE)) bootsplash.jpg-type := bootsplash -####################################################################### +################################################################################ # i386 specific tools NVRAMTOOL:=$(objutil)/nvramtool/nvramtool @@ -135,7 +134,7 @@ $(obj)/cmos_layout.bin: $(NVRAMTOOL) $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.l @printf " OPTION $(subst $(obj)/,,$(@))\n" $(NVRAMTOOL) -y $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout -L $@ -####################################################################### +################################################################################ # Common recipes for all stages $(objcbfs)/%.bin: $(objcbfs)/%.elf @@ -150,7 +149,7 @@ $(objcbfs)/%.elf: $(objcbfs)/%.debug $(OBJCOPY) --add-gnu-debuglink=$< $@.tmp mv $@.tmp $@ -####################################################################### +################################################################################ # Build the coreboot_ram (stage 2) $(objcbfs)/coreboot_ram.debug: $(objgenerated)/coreboot_ram.o $(src)/arch/x86/coreboot_ram.ld @@ -174,7 +173,7 @@ $(objgenerated)/ramstage.a: $$(ramstage-objs) rm -f $@ $(AR) cr $@ $^ -####################################################################### +################################################################################ # Ramstage for AP CPU (AMD K8, obsolete?) $(objcbfs)/coreboot_ap.debug: $(objgenerated)/coreboot_ap.o $(src)/arch/x86/init/ldscript_apc.lb @@ -185,7 +184,7 @@ $(objgenerated)/coreboot_ap.o: $(src)/mainboard/$(MAINBOARDDIR)/ap_romstage.c $( @printf " CC $(subst $(obj)/,,$(@))\n" $(CC) -MMD $(CFLAGS) -I$(src) -D__PRE_RAM__ -I. -I$(obj) -c $< -o $@ -####################################################################### +################################################################################ # done crt0s = $(src)/arch/x86/init/prologue.inc @@ -264,7 +263,7 @@ ifeq ($(CONFIG_HAVE_BUS_CONFIG),y) ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/get_bus_conf.c endif -####################################################################### +################################################################################ # Build the final rom image $(obj)/coreboot.pre: $(objcbfs)/romstage_xip.elf $(obj)/coreboot.pre1 $(CBFSTOOL) @@ -274,7 +273,7 @@ $(obj)/coreboot.pre: $(objcbfs)/romstage_xip.elf $(obj)/coreboot.pre1 $(CBFSTOOL $(CONFIG_CBFS_PREFIX)/romstage x $(shell cat $(objcbfs)/base_xip.txt) mv $@.tmp $@ -####################################################################### +################################################################################ # Build the bootblock bootblock_lds = $(src)/arch/x86/init/ldscript_failover.lb @@ -331,7 +330,7 @@ else $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/bootblock.ld $< endif -####################################################################### +################################################################################ # Build the romstage $(objcbfs)/romstage_null.debug: $$(romstage-objs) $(objgenerated)/romstage_null.ld diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index baf686e..daf8083 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -62,10 +62,90 @@ config SSE2 streaming SIMD instructions. Some parts of coreboot can be built with more efficient code if SSE2 instructions are available. -config MICROCODE_IN_CBFS - bool "Look for microcode in CBFS" +endif # ARCH_X86 + +config CPU_MICROCODE_IN_CBFS + bool default n + +choice + prompt "Include CPU microcode in CBFS" + default CPU_MICROCODE_CBFS_GENERATE + depends on CPU_MICROCODE_IN_CBFS + +config CPU_MICROCODE_CBFS_GENERATE + bool "Generate from tree" help - Load microcode updates from CBFS instead of compiling them in. + Select this option if you want microcode updates to be assembled when + building coreboot and included in the final image as a separate CBFS + file. Microcode will not be hard-coded into ramstage. -endif # ARCH_X86 + The microcode file and may be removed from the ROM image at a later + time with cbfstool, if desired. + + If unsure, select this option. + +config CPU_MICROCODE_CBFS_EXTERNAL + bool "Include external microcode file" + help + Select this option if you want to include an external file containing + the CPU microcode. This will be included as a separate file in CBFS. + A word of caution: only select this option if you are sure the + microcode that you have is newer than the microcode shipping with + coreboot. + + The microcode file and may be removed from the ROM image at a later + time with cbfstool, if desired. + + If unsure, select "Generate from tree" + +config CPU_MICROCODE_FILE + string "Path and filename of CPU microcode" + depends on CPU_MICROCODE_CBFS_EXTERNAL + default "cpu_microcode.bin" + help + The path and filename of the file containing the CPU microcode. + +config CPU_MICROCODE_CBFS_NONE + bool "Do not include microcode updates" + help + Select this option if you do not want CPU microcode included in CBFS. + Note that for some CPUs, the microcode is hard-coded into the source + tree and is not loaded from CBFS. In this case, microcode will still + be updated. There is a push to move all microcode to CBFS, but this + change is not implemented for all CPUs. + + This option currently applies to: + - Intel SandyBridge/IvyBridge + - VIA Nano + + Microcode may be added to the ROM image at a later time with cbfstool, + if desired. + + If unsure, select "Generate from tree" + + The GOOD: + Microcode updates intend to solve issues that have been discovered + after CPU production. The expected effect is that systems work as + intended with the updated microcode, but we have also seen cases where + issues were solved by not applying microcode updates. + + The BAD: + Note that some operating system include these same microcode patches, + so you may need to also disable microcode updates in your operating + system for this option to have an effect. + + The UGLY: + A word of CAUTION: some CPUs depend on microcode updates to function + correctly. Not updating the microcode may leave the CPU operating at + less than optimal performance, or may cause outright hangups. + There are CPUs where coreboot cannot properly initialize the CPU + without microcode updates + For example, if running with the factory microcode, some Intel + SandyBridge CPUs may hang when enabling CAR, or some VIA Nano CPUs + will hang when changing the frequency. + + Make sure you have a way of flashing the ROM externally before + selecting this option. + +endchoice diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc index 57273cf..572b707 100644 --- a/src/cpu/Makefile.inc +++ b/src/cpu/Makefile.inc @@ -1,3 +1,28 @@ +################################################################################ +## Subdirectories +################################################################################ subdirs-y += amd subdirs-y += intel subdirs-y += via + + +################################################################################ +## Rules for building the microcode blob in CBFS +################################################################################ + +ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL), y) +cbfs-files-y += cpu_microcode_blob.bin +microcode_blob.bin-file = $(CONFIG_CPU_MICROCODE_FILE) +microcode_blob.bin-type = 0x53 +endif + +ifneq ($(CONFIG_CPU_MICROCODE_CBFS_NONE), y) +cbfs-files-y += cpu_microcode_blob.bin +cpu_microcode_blob.bin-file = $(obj)/cpu_microcode_blob.bin +cpu_microcode_blob.bin-type = 0x53 + +$(obj)/cpu_microcode_blob.bin: $$(cpu_microcode-objs) + @printf " ASSM $(subst $(obj)/,,$(@))\n" + $(CC) -MMD -o $@ -L$(obj) $(cpu_microcode-objs) + +endif diff --git a/src/cpu/intel/microcode/Makefile.inc b/src/cpu/intel/microcode/Makefile.inc index f4d0102..22655c9 100644 --- a/src/cpu/intel/microcode/Makefile.inc +++ b/src/cpu/intel/microcode/Makefile.inc @@ -1,15 +1,5 @@ -ramstage-y += microcode.c - - -ifeq ($(CONFIG_MICROCODE_IN_CBFS),y) - -SRC_PATH = src/cpu/intel/microcode -FLAGS = -I $(CONFIG_MICROCODE_INCLUDE_PATH) -include $(obj)/config.h -$(obj)/microcode_blob.o: $(SRC_PATH)/microcode_blob.c - $(CC) $(FLAGS) -MMD -c -o $@ $< - -$(obj)/microcode_blob.bin: $(obj)/microcode_blob.o - objcopy -j .data -O binary $< $@ - --include $(obj)/microcode_blob.d -endif +################################################################################ +## One small file with the awesome super-power of updating the cpu microcode +## directly from CBFS. You have been WARNED!!! +################################################################################ +ramstage-y += microcode.c \ No newline at end of file diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index e84bad9..a4471ca 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -28,7 +28,7 @@ #include <cpu/x86/msr.h> #include <cpu/intel/microcode.h> -#if CONFIG_MICROCODE_IN_CBFS +#if CONFIG_CPU_MICROCODE_IN_CBFS #ifdef __PRE_RAM__ #include <arch/cbfs.h> #else @@ -77,7 +77,7 @@ static inline u32 read_microcode_rev(void) return msr.hi; } -#if CONFIG_MICROCODE_IN_CBFS +#if CONFIG_CPU_MICROCODE_IN_CBFS static #endif void intel_update_microcode(const void *microcode_updates) @@ -144,9 +144,9 @@ void intel_update_microcode(const void *microcode_updates) } } -#if CONFIG_MICROCODE_IN_CBFS +#if CONFIG_CPU_MICROCODE_IN_CBFS -#define MICROCODE_CBFS_FILE "microcode_blob.bin" +#define MICROCODE_CBFS_FILE "cpu_microcode_blob.bin" void intel_update_microcode_from_cbfs(void) { diff --git a/src/cpu/intel/microcode/microcode_blob.c b/src/cpu/intel/microcode/microcode_blob.c deleted file mode 100644 index 69238a9..0000000 --- a/src/cpu/intel/microcode/microcode_blob.c +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -unsigned microcode[] = { -#include <microcode_blob.h> -}; diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index 071683e..1b4351e 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -12,7 +12,7 @@ config CPU_SPECIFIC_OPTIONS select SSE2 select UDELAY_LAPIC select SMM_TSEG - select MICROCODE_IN_CBFS + select CPU_MICROCODE_IN_CBFS config BOOTBLOCK_CPU_INIT string @@ -22,9 +22,6 @@ config SMM_TSEG_SIZE hex default 0x800000 -config MICROCODE_INCLUDE_PATH - string - default "src/cpu/intel/model_206ax" endif if CPU_INTEL_MODEL_206AX diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc index e9b8e6d..990a7fa 100644 --- a/src/cpu/intel/model_206ax/Makefile.inc +++ b/src/cpu/intel/model_206ax/Makefile.inc @@ -5,4 +5,6 @@ ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c +cpu_microcode-y += microcode_blob.c + cpu_incs += $(src)/cpu/intel/model_206ax/cache_as_ram.inc diff --git a/src/cpu/intel/model_206ax/microcode_blob.c b/src/cpu/intel/model_206ax/microcode_blob.c new file mode 100644 index 0000000..c2538e8 --- /dev/null +++ b/src/cpu/intel/model_206ax/microcode_blob.c @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +unsigned microcode[] = { +#include "microcode_blob.h" +}; diff --git a/src/include/cpu/intel/microcode.h b/src/include/cpu/intel/microcode.h index 289e919..e9c13f9 100644 --- a/src/include/cpu/intel/microcode.h +++ b/src/include/cpu/intel/microcode.h @@ -21,7 +21,7 @@ #define __CPU__INTEL__MICROCODE__ #ifndef __PRE_RAM__ -#if CONFIG_MICROCODE_IN_CBFS +#if CONFIG_CPU_MICROCODE_IN_CBFS void intel_update_microcode_from_cbfs(void); #else void intel_update_microcode(const void *microcode_updates);

1 0

Patch set updated for coreboot: 0a540e8 buildsystem(NOTYETREADY): Make CPU microcode updating more configurable
by Alexandru Gagniuc 26 Jul '12

26 Jul '12

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1245 -gerrit commit 0a540e8cb547c076c529b731150cbf09b12330da Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Fri Jul 20 00:11:21 2012 -0500 buildsystem(NOTYETREADY): Make CPU microcode updating more configurable This patch aims to improve the microcode in CBFS handling that was implemented in the last patches from Stefan and the Chromium team. When the CPU selects MICROCODE_IN_CBFS, the user is given three choices in Kconfig - 1) Generate microcode from tree (default) - 2) Include external microcode file - 3) Do not put microcode in CBFS The idea is to give the user full control over including non-free blobs in the final ROM image. The implementation is at the moment, clumsy and disfunctional. Suggestions are welcome. Change-Id: I38d0c9851691aa112e93031860e94895857ebb76 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/arch/x86/Makefile.inc | 34 ++++++++++++++++---------- src/cpu/Kconfig | 44 ++++++++++++++++++++++++++++++++- src/cpu/Makefile.inc | 24 ++++++++++++++++++ src/cpu/intel/microcode/Makefile.inc | 20 ++++----------- src/cpu/intel/microcode/microcode.c | 8 +++--- src/cpu/intel/model_206ax/Kconfig | 2 +- src/include/cpu/intel/microcode.h | 2 +- 7 files changed, 98 insertions(+), 36 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 306f239..78ecb42 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -1,3 +1,4 @@ +################################################################################ ## ## This file is part of the coreboot project. ## @@ -17,8 +18,8 @@ ## along with this program; if not, write to the Free Software ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +################################################################################ -####################################################################### # Take care of subdirectories subdirs-y += boot # subdirs-y += init @@ -34,13 +35,20 @@ cmos_layout.bin-type = 0x01aa OPTION_TABLE_H:=$(obj)/option_table.h endif -ifeq ($(CONFIG_MICROCODE_IN_CBFS),y) -cbfs-files-y += microcode_blob.bin -microcode_blob.bin-file = $(obj)/microcode_blob.bin +################################################################################ +ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL), y) +cbfs-files-y += cpu_microcode_blob.bin +microcode_blob.bin-file = $(CONFIG_CPU_MICROCODE_FILE) microcode_blob.bin-type = 0x53 endif -####################################################################### +ifeq ($(CONFIG_CPU_MICROCODE_CBFS_GENERATE), y) +cbfs-files-y += cpu_microcode_blob.bin +microcode_blob.bin-file = $(obj)/cpu_microcode_blob.bin +microcode_blob.bin-type = 0x53 +endif + +################################################################################ # Build the final rom image COREBOOT_ROM_DEPENDENCIES:= ifeq ($(CONFIG_PAYLOAD_ELF),y) @@ -123,7 +131,7 @@ cbfs-files-$(CONFIG_BOOTSPLASH) += bootsplash.jpg bootsplash.jpg-file := $(call strip_quotes,$(CONFIG_BOOTSPLASH_FILE)) bootsplash.jpg-type := bootsplash -####################################################################### +################################################################################ # i386 specific tools NVRAMTOOL:=$(objutil)/nvramtool/nvramtool @@ -135,7 +143,7 @@ $(obj)/cmos_layout.bin: $(NVRAMTOOL) $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.l @printf " OPTION $(subst $(obj)/,,$(@))\n" $(NVRAMTOOL) -y $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout -L $@ -####################################################################### +################################################################################ # Common recipes for all stages $(objcbfs)/%.bin: $(objcbfs)/%.elf @@ -150,7 +158,7 @@ $(objcbfs)/%.elf: $(objcbfs)/%.debug $(OBJCOPY) --add-gnu-debuglink=$< $@.tmp mv $@.tmp $@ -####################################################################### +################################################################################ # Build the coreboot_ram (stage 2) $(objcbfs)/coreboot_ram.debug: $(objgenerated)/coreboot_ram.o $(src)/arch/x86/coreboot_ram.ld @@ -174,7 +182,7 @@ $(objgenerated)/ramstage.a: $$(ramstage-objs) rm -f $@ $(AR) cr $@ $^ -####################################################################### +################################################################################ # Ramstage for AP CPU (AMD K8, obsolete?) $(objcbfs)/coreboot_ap.debug: $(objgenerated)/coreboot_ap.o $(src)/arch/x86/init/ldscript_apc.lb @@ -185,7 +193,7 @@ $(objgenerated)/coreboot_ap.o: $(src)/mainboard/$(MAINBOARDDIR)/ap_romstage.c $( @printf " CC $(subst $(obj)/,,$(@))\n" $(CC) -MMD $(CFLAGS) -I$(src) -D__PRE_RAM__ -I. -I$(obj) -c $< -o $@ -####################################################################### +################################################################################ # done crt0s = $(src)/arch/x86/init/prologue.inc @@ -264,7 +272,7 @@ ifeq ($(CONFIG_HAVE_BUS_CONFIG),y) ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/get_bus_conf.c endif -####################################################################### +################################################################################ # Build the final rom image $(obj)/coreboot.pre: $(objcbfs)/romstage_xip.elf $(obj)/coreboot.pre1 $(CBFSTOOL) @@ -274,7 +282,7 @@ $(obj)/coreboot.pre: $(objcbfs)/romstage_xip.elf $(obj)/coreboot.pre1 $(CBFSTOOL $(CONFIG_CBFS_PREFIX)/romstage x $(shell cat $(objcbfs)/base_xip.txt) mv $@.tmp $@ -####################################################################### +################################################################################ # Build the bootblock bootblock_lds = $(src)/arch/x86/init/ldscript_failover.lb @@ -331,7 +339,7 @@ else $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/bootblock.ld $< endif -####################################################################### +################################################################################ # Build the romstage $(objcbfs)/romstage_null.debug: $$(romstage-objs) $(objgenerated)/romstage_null.ld diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index baf686e..53f978e 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -62,10 +62,50 @@ config SSE2 streaming SIMD instructions. Some parts of coreboot can be built with more efficient code if SSE2 instructions are available. -config MICROCODE_IN_CBFS +endif # ARCH_X86 + +config CPU_MICROCODE_IN_CBFS bool "Look for microcode in CBFS" default n help Load microcode updates from CBFS instead of compiling them in. -endif # ARCH_X86 +choice + prompt "Include CPU microcode in CBFS" + default CPU_MICROCODE_CBFS_GENERATE + depends on CPU_MICROCODE_IN_CBFS + +config CPU_MICROCODE_CBFS_GENERATE + bool "Generate from tree" + help + Select this option if you want microcode updates to be assembled when + building coreboot and included in the final image as a separate CBFS + file. Microcode will not be hard-coded into ramstage, and may be + removed from the ROM image at a later time with cbfstool. + +config CPU_MICROCODE_CBFS_EXTERNAL + depends on CPU_MICROCODE_IN_CBFS + bool "Include external microcode file" + help + Select this option if you want to include an external file containing + the CPU microcode. This will be included as a separate file in CBFS. + A word of caution: only select this option if you are sure the + microcode that you have is newer than the microcode shipping with + coreboot. + +config CPU_MICROCODE_FILE + string "Path and filename of CPU microcode" + depends on CPU_MICROCODE_CBFS_EXTERNAL + default "cpu_microcode.bin" + help + The path and filename of the file containing the CPU microcode. + +config CPU_MICROCODE_CBFS_NONE + bool "Do not include microcode updates" + help + Select this option if you do not want CPU microcode included in CBFS. + Note that for some CPUs, the microcode is hard-coded into the source + tree and is not loaded from CBFS. In this case, microcode will still + be updated. + +endchoice diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc index 57273cf..ca39871 100644 --- a/src/cpu/Makefile.inc +++ b/src/cpu/Makefile.inc @@ -1,3 +1,27 @@ +################################################################################ +## Subdirectories +################################################################################ subdirs-y += amd subdirs-y += intel subdirs-y += via + + +################################################################################ +## Rules for building the microcode blob in CBFS +################################################################################ + +ifeq ($(CONFIG_CPU_MICROCODE_CBFS_GENERATE),y) +########################### +# FIXME FIXME FIXME FIXME # +########################### +SRC_PATH = src/cpu/intel/ + +FLAGS = -I $(CONFIG_MICROCODE_INCLUDE_PATH) -include $(obj)/config.h +$(obj)/cpu_microcode_blob.o: $(SRC_PATH)/microcode_blob.c + $(CC) $(FLAGS) -MMD -c -o $@ $< + +$(obj)/cpu_microcode_blob.bin: $(obj)/cpu_microcode_blob.o + $(OBJCOPY) -j .data -O binary $< $@ + +-include $(obj)/microcode_blob.d +endif \ No newline at end of file diff --git a/src/cpu/intel/microcode/Makefile.inc b/src/cpu/intel/microcode/Makefile.inc index f4d0102..22655c9 100644 --- a/src/cpu/intel/microcode/Makefile.inc +++ b/src/cpu/intel/microcode/Makefile.inc @@ -1,15 +1,5 @@ -ramstage-y += microcode.c - - -ifeq ($(CONFIG_MICROCODE_IN_CBFS),y) - -SRC_PATH = src/cpu/intel/microcode -FLAGS = -I $(CONFIG_MICROCODE_INCLUDE_PATH) -include $(obj)/config.h -$(obj)/microcode_blob.o: $(SRC_PATH)/microcode_blob.c - $(CC) $(FLAGS) -MMD -c -o $@ $< - -$(obj)/microcode_blob.bin: $(obj)/microcode_blob.o - objcopy -j .data -O binary $< $@ - --include $(obj)/microcode_blob.d -endif +################################################################################ +## One small file with the awesome super-power of updating the cpu microcode +## directly from CBFS. You have been WARNED!!! +################################################################################ +ramstage-y += microcode.c \ No newline at end of file diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index e84bad9..a4471ca 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -28,7 +28,7 @@ #include <cpu/x86/msr.h> #include <cpu/intel/microcode.h> -#if CONFIG_MICROCODE_IN_CBFS +#if CONFIG_CPU_MICROCODE_IN_CBFS #ifdef __PRE_RAM__ #include <arch/cbfs.h> #else @@ -77,7 +77,7 @@ static inline u32 read_microcode_rev(void) return msr.hi; } -#if CONFIG_MICROCODE_IN_CBFS +#if CONFIG_CPU_MICROCODE_IN_CBFS static #endif void intel_update_microcode(const void *microcode_updates) @@ -144,9 +144,9 @@ void intel_update_microcode(const void *microcode_updates) } } -#if CONFIG_MICROCODE_IN_CBFS +#if CONFIG_CPU_MICROCODE_IN_CBFS -#define MICROCODE_CBFS_FILE "microcode_blob.bin" +#define MICROCODE_CBFS_FILE "cpu_microcode_blob.bin" void intel_update_microcode_from_cbfs(void) { diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index 071683e..60338e1 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -12,7 +12,7 @@ config CPU_SPECIFIC_OPTIONS select SSE2 select UDELAY_LAPIC select SMM_TSEG - select MICROCODE_IN_CBFS + select CPU_MICROCODE_IN_CBFS config BOOTBLOCK_CPU_INIT string diff --git a/src/include/cpu/intel/microcode.h b/src/include/cpu/intel/microcode.h index 289e919..e9c13f9 100644 --- a/src/include/cpu/intel/microcode.h +++ b/src/include/cpu/intel/microcode.h @@ -21,7 +21,7 @@ #define __CPU__INTEL__MICROCODE__ #ifndef __PRE_RAM__ -#if CONFIG_MICROCODE_IN_CBFS +#if CONFIG_CPU_MICROCODE_IN_CBFS void intel_update_microcode_from_cbfs(void); #else void intel_update_microcode(const void *microcode_updates);

1 0

Patch set updated for coreboot: e4ae8a6 buildsystem(NOTYETREADY): Make CPU microcode updating more configurable
by Alexandru Gagniuc 26 Jul '12

26 Jul '12

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1245 -gerrit commit e4ae8a651f7a78fa1e030658ccd375e87ff7bcfa Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Fri Jul 20 00:11:21 2012 -0500 buildsystem(NOTYETREADY): Make CPU microcode updating more configurable This patch aims to improve the microcode in CBFS handling that was implemented in the last patches from Stefan and the Chromium team. When the CPU selects MICROCODE_IN_CBFS, the user is given three choices in Kconfig - 1) Generate microcode from tree (default) - 2) Include external microcode file - 3) Do not put microcode in CBFS The idea is to give the user full control over including non-free blobs in the final ROM image. Change-Id: I38d0c9851691aa112e93031860e94895857ebb76 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/arch/x86/Makefile.inc | 10 +++++-- src/cpu/Kconfig | 44 ++++++++++++++++++++++++++++++++- src/cpu/intel/microcode/Makefile.inc | 6 ++-- src/cpu/intel/microcode/microcode.c | 8 +++--- src/cpu/intel/model_206ax/Kconfig | 2 +- src/include/cpu/intel/microcode.h | 2 +- 6 files changed, 58 insertions(+), 14 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 306f239..d56bbf5 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -34,9 +34,13 @@ cmos_layout.bin-type = 0x01aa OPTION_TABLE_H:=$(obj)/option_table.h endif -ifeq ($(CONFIG_MICROCODE_IN_CBFS),y) -cbfs-files-y += microcode_blob.bin -microcode_blob.bin-file = $(obj)/microcode_blob.bin +ifeq ($(CONFIG_CPU_MICROCODE_IN_CBFS),y) +cbfs-files-y += cpu_microcode_blob.bin + ifeq ($(CPU_MICROCODE_CBFS_EXTERNAL), y) + microcode_blob.bin-file = $(CPU_MICROCODE_FILE) + else + microcode_blob.bin-file = $(obj)/cpu_microcode_blob.bin + endif microcode_blob.bin-type = 0x53 endif diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index baf686e..d8b5e7d 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -62,10 +62,50 @@ config SSE2 streaming SIMD instructions. Some parts of coreboot can be built with more efficient code if SSE2 instructions are available. -config MICROCODE_IN_CBFS +endif # ARCH_X86 + +config CPU_MICROCODE_IN_CBFS bool "Look for microcode in CBFS" default n help Load microcode updates from CBFS instead of compiling them in. -endif # ARCH_X86 +choice + prompt "Include CPU microcode in CBFS" + default CPU_MICROCODE_CBFS_GENERATE + depends on CPU_MICROCODE_IN_CBFS + +config CPU_MICROCODE_CBFS_GENERATE + bool "Generate from tree" + help + Select this option if you want microcode updates to be assembled when + building coreboot and included in the final image as a separate CBFS + file. Microcode will not be hard-coded into ramstage, and may be + removed from the ROM image at a later time with cbfstool. + +config CPU_MICROCODE_CBFS_EXTERNAL + depends on CPU_MICROCODE_IN_CBFS + bool "Include external microcode file" + help + Select this option if you want to include an external file containing + the CPU microcode. This will be included as a separate file in CBFS. + A word of caution: only select this option if you are sure the + microcode that you have is newer than the microcode shipping with + coreboot. + +config CPU_MICROCODE_FILE + string "Path and filename of CPU microcode" + depends on CPU_MICROCODE_CBFS_EXTERNAL + default "microcode.bin" + help + The path and filename of the file containing the CPU microcode. + +config CPU_MICROCODE_CBFS_NONE + bool "Do not include microcode updates" + help + Select this option if you do not want CPU microcode included in CBFS. + Note that for some CPUs, the microcode is hard-coded into the source + tree and is not loaded from CBFS. In this case, microcode will still + be updated. + +endchoice diff --git a/src/cpu/intel/microcode/Makefile.inc b/src/cpu/intel/microcode/Makefile.inc index f4d0102..38b0139 100644 --- a/src/cpu/intel/microcode/Makefile.inc +++ b/src/cpu/intel/microcode/Makefile.inc @@ -1,15 +1,15 @@ ramstage-y += microcode.c -ifeq ($(CONFIG_MICROCODE_IN_CBFS),y) +ifeq ($(CONFIG_CPU_MICROCODE_IN_CBFS),y) SRC_PATH = src/cpu/intel/microcode FLAGS = -I $(CONFIG_MICROCODE_INCLUDE_PATH) -include $(obj)/config.h $(obj)/microcode_blob.o: $(SRC_PATH)/microcode_blob.c $(CC) $(FLAGS) -MMD -c -o $@ $< -$(obj)/microcode_blob.bin: $(obj)/microcode_blob.o - objcopy -j .data -O binary $< $@ +$(obj)/cpu_microcode_blob.bin: $(obj)/microcode_blob.o + $(OBJCOPY) -j .data -O binary $< $@ -include $(obj)/microcode_blob.d endif diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index e84bad9..a4471ca 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -28,7 +28,7 @@ #include <cpu/x86/msr.h> #include <cpu/intel/microcode.h> -#if CONFIG_MICROCODE_IN_CBFS +#if CONFIG_CPU_MICROCODE_IN_CBFS #ifdef __PRE_RAM__ #include <arch/cbfs.h> #else @@ -77,7 +77,7 @@ static inline u32 read_microcode_rev(void) return msr.hi; } -#if CONFIG_MICROCODE_IN_CBFS +#if CONFIG_CPU_MICROCODE_IN_CBFS static #endif void intel_update_microcode(const void *microcode_updates) @@ -144,9 +144,9 @@ void intel_update_microcode(const void *microcode_updates) } } -#if CONFIG_MICROCODE_IN_CBFS +#if CONFIG_CPU_MICROCODE_IN_CBFS -#define MICROCODE_CBFS_FILE "microcode_blob.bin" +#define MICROCODE_CBFS_FILE "cpu_microcode_blob.bin" void intel_update_microcode_from_cbfs(void) { diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index 071683e..60338e1 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -12,7 +12,7 @@ config CPU_SPECIFIC_OPTIONS select SSE2 select UDELAY_LAPIC select SMM_TSEG - select MICROCODE_IN_CBFS + select CPU_MICROCODE_IN_CBFS config BOOTBLOCK_CPU_INIT string diff --git a/src/include/cpu/intel/microcode.h b/src/include/cpu/intel/microcode.h index 289e919..e9c13f9 100644 --- a/src/include/cpu/intel/microcode.h +++ b/src/include/cpu/intel/microcode.h @@ -21,7 +21,7 @@ #define __CPU__INTEL__MICROCODE__ #ifndef __PRE_RAM__ -#if CONFIG_MICROCODE_IN_CBFS +#if CONFIG_CPU_MICROCODE_IN_CBFS void intel_update_microcode_from_cbfs(void); #else void intel_update_microcode(const void *microcode_updates);

1 0

Patch set updated for coreboot: 4241e40 buildsystem(NOTYETREADY): Make CPU microcode updating more configurable
by Alexandru Gagniuc 26 Jul '12

26 Jul '12

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1245 -gerrit commit 4241e40123f80ffb2e154c9477bb23f18b5e0822 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Fri Jul 20 00:11:21 2012 -0500 buildsystem(NOTYETREADY): Make CPU microcode updating more configurable This patch aims to improve the microcode in CBFS handling that was implemented in the last patches from Stefan and the Chromium team. When the CPU selects MICROCODE_IN_CBFS, the user is given three choices in Kconfig - 1) Generate microcode from tree (default) - 2) Include external microcode file - 3) Do not put microcode in CBFS The idea is to give the user full control over including non-free blobs in the final ROM image. Change-Id: I38d0c9851691aa112e93031860e94895857ebb76 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/arch/x86/Makefile.inc | 13 ++++++++-- src/cpu/Kconfig | 43 +++++++++++++++++++++++++++++++++- src/cpu/amd/model_10xxx/Kconfig | 33 +------------------------- src/cpu/intel/microcode/Makefile.inc | 4 +- src/cpu/intel/microcode/microcode.c | 8 +++--- src/cpu/intel/model_206ax/Kconfig | 2 +- src/include/cpu/intel/microcode.h | 2 +- 7 files changed, 61 insertions(+), 44 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 306f239..521f1db 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -34,9 +34,9 @@ cmos_layout.bin-type = 0x01aa OPTION_TABLE_H:=$(obj)/option_table.h endif -ifeq ($(CONFIG_MICROCODE_IN_CBFS),y) -cbfs-files-y += microcode_blob.bin -microcode_blob.bin-file = $(obj)/microcode_blob.bin +ifeq ($(CONFIG_CPU_MICROCODE_IN_CBFS),y) +cbfs-files-y += cpu_microcode_blob.bin +microcode_blob.bin-file = $(obj)/cpu_microcode_blob.bin microcode_blob.bin-type = 0x53 endif @@ -55,6 +55,9 @@ endif ifeq ($(CONFIG_AP_CODE_IN_CAR),y) COREBOOT_ROM_DEPENDENCIES+=$(objcbfs)/coreboot_ap.elf endif +ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL),y) +COREBOOT_ROM_DEPENDENCIES+=$(CONFIG_CPU_MICROCODE_FILE) +endif extract_nth=$(word $(1), $(subst |, ,$(2))) @@ -106,6 +109,10 @@ ifeq ($(CONFIG_INCLUDE_CONFIG_FILE),y) sed -e '/^#/d' -e '/^ *$$/d' $(DOTCONFIG) >> $(obj)/config.tmp ; \ $(CBFSTOOL) $@.tmp add $(obj)/config.tmp config raw; rm -f $(obj)/config.tmp ; fi endif +ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL),y) + @printf " CPU uCode cpu_microcode\n" + $(CBFSTOOL) $@.tmp add $(CONFIG_CPU_MICROCODE_FILE) cpu_microcode microcode +endif mv $@.tmp $@ @printf " CBFSPRINT $(subst $(obj)/,,$(@))\n\n" $(CBFSTOOL) $@ print diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index baf686e..ebae1b9 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -62,10 +62,51 @@ config SSE2 streaming SIMD instructions. Some parts of coreboot can be built with more efficient code if SSE2 instructions are available. -config MICROCODE_IN_CBFS +config CPU_MICROCODE_IN_CBFS bool "Look for microcode in CBFS" default n help Load microcode updates from CBFS instead of compiling them in. endif # ARCH_X86 + + +choice + prompt "Include CPU microcode in CBFS" + default CPU_MICROCODE_CBFS_GENERATE + depends on CPU_MICROCODE_IN_CBFS + +config CPU_MICROCODE_CBFS_GENERATE + bool "Generate from tree" + help + Select this option if you want microcode updates to be assembled when + building coreboot and included in the final image as a separate CBFS + file. Microcode will not be hard-coded into ramstage, and may be + removed from the ROM image at a later time with cbfstool. + +config CPU_MICROCODE_CBFS_EXTERNAL + depends on CPU_MICROCODE_IN_CBFS + bool "Include external microcode file" + help + Select this option if you want to include an external file containing + the CPU microcode. This will be included as a separate file in CBFS. + A word of caution: only select this option if you are sure the + microcode that you have is newer than the microcode shipping with + coreboot. + +config CPU_MICROCODE_CBFS_NONE + bool "Do not include microcode updates" + help + Select this option if you do not want CPU microcode included in CBFS. + Note that for some CPUs, the microcode is hard-coded into the source + tree and is not loaded from CBFS. In this case, microcode will still + be updated. + +endchoice + +config CPU_MICROCODE_FILE + string "Path and filename of CPU microcode" + depends on CPU_MICROCODE_CBFS_EXTERNAL + default "microcode.bin" + help + The path and filename of the file containing the CPU microcode. \ No newline at end of file diff --git a/src/cpu/amd/model_10xxx/Kconfig b/src/cpu/amd/model_10xxx/Kconfig index 221d044..64ac850 100644 --- a/src/cpu/amd/model_10xxx/Kconfig +++ b/src/cpu/amd/model_10xxx/Kconfig @@ -3,6 +3,7 @@ config CPU_AMD_MODEL_10XXX select SSE select SSE2 select MMCONF_SUPPORT_DEFAULT + select RESPECTS_UPDATE_CPU_MICROCODE_OPTION if CPU_AMD_MODEL_10XXX config CPU_ADDR_BITS @@ -51,36 +52,4 @@ config SET_FIDVID_CORE_RANGE endif # SET_FIDVID -config UPDATE_CPU_MICROCODE - bool - default y - -config UPDATE_CPU_MICROCODE - bool "Update CPU microcode" - default y - depends on EXPERT && CPU_AMD_MODEL_10XXX - help - Select this to apply patches to the CPU microcode provided by - AMD without source, and distributed with coreboot, to address - issues in the CPU post production. - - Microcode updates distributed with coreboot are not necessarily - the latest version available from AMD. Updates are only applied - if they are newer than the microcode already in your CPU. - - Unselect this to let Fam10h CPUs run with microcode as shipped - from factory. No binary microcode patches will be included in the - coreboot image in that case, which can help with creating an image - for which complete source code is available, which in turn might - simplify license compliance. - - Microcode updates intend to solve issues that have been discovered - after CPU production. The common case is that systems work as - intended with updated microcode, but we have also seen cases where - issues were solved by not applying the microcode updates. - - Note that some operating system include these same microcode - patches, so you may need to also disable microcode updates in - your operating system in order for this option to matter. - endif # CPU_AMD_MODEL_10XXX diff --git a/src/cpu/intel/microcode/Makefile.inc b/src/cpu/intel/microcode/Makefile.inc index f4d0102..754689a 100644 --- a/src/cpu/intel/microcode/Makefile.inc +++ b/src/cpu/intel/microcode/Makefile.inc @@ -1,14 +1,14 @@ ramstage-y += microcode.c -ifeq ($(CONFIG_MICROCODE_IN_CBFS),y) +ifeq ($(CONFIG_CPU_MICROCODE_IN_CBFS),y) SRC_PATH = src/cpu/intel/microcode FLAGS = -I $(CONFIG_MICROCODE_INCLUDE_PATH) -include $(obj)/config.h $(obj)/microcode_blob.o: $(SRC_PATH)/microcode_blob.c $(CC) $(FLAGS) -MMD -c -o $@ $< -$(obj)/microcode_blob.bin: $(obj)/microcode_blob.o +$(obj)/cpu_microcode_blob.bin: $(obj)/microcode_blob.o objcopy -j .data -O binary $< $@ -include $(obj)/microcode_blob.d diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index e84bad9..a4471ca 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -28,7 +28,7 @@ #include <cpu/x86/msr.h> #include <cpu/intel/microcode.h> -#if CONFIG_MICROCODE_IN_CBFS +#if CONFIG_CPU_MICROCODE_IN_CBFS #ifdef __PRE_RAM__ #include <arch/cbfs.h> #else @@ -77,7 +77,7 @@ static inline u32 read_microcode_rev(void) return msr.hi; } -#if CONFIG_MICROCODE_IN_CBFS +#if CONFIG_CPU_MICROCODE_IN_CBFS static #endif void intel_update_microcode(const void *microcode_updates) @@ -144,9 +144,9 @@ void intel_update_microcode(const void *microcode_updates) } } -#if CONFIG_MICROCODE_IN_CBFS +#if CONFIG_CPU_MICROCODE_IN_CBFS -#define MICROCODE_CBFS_FILE "microcode_blob.bin" +#define MICROCODE_CBFS_FILE "cpu_microcode_blob.bin" void intel_update_microcode_from_cbfs(void) { diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index 071683e..60338e1 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -12,7 +12,7 @@ config CPU_SPECIFIC_OPTIONS select SSE2 select UDELAY_LAPIC select SMM_TSEG - select MICROCODE_IN_CBFS + select CPU_MICROCODE_IN_CBFS config BOOTBLOCK_CPU_INIT string diff --git a/src/include/cpu/intel/microcode.h b/src/include/cpu/intel/microcode.h index 289e919..e9c13f9 100644 --- a/src/include/cpu/intel/microcode.h +++ b/src/include/cpu/intel/microcode.h @@ -21,7 +21,7 @@ #define __CPU__INTEL__MICROCODE__ #ifndef __PRE_RAM__ -#if CONFIG_MICROCODE_IN_CBFS +#if CONFIG_CPU_MICROCODE_IN_CBFS void intel_update_microcode_from_cbfs(void); #else void intel_update_microcode(const void *microcode_updates);

1 0

Patch merged into coreboot/master: bbd48e6 Enable Microcode in CBFS for all SandyBridge/IvyBridge systems
by gerrit＠coreboot.org 26 Jul '12

26 Jul '12

the following patch was just integrated into master: commit bbd48e6574183e28fa6fc5ab3568c5b777cdb01e Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Jul 10 17:02:21 2012 -0700 Enable Microcode in CBFS for all SandyBridge/IvyBridge systems Change-Id: Idee4facc18e0be60906d2a2f0e99bd39de8d7247 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Build-Tested: build bot (Jenkins) at Wed Jul 25 22:46:49 2012, giving +1 Reviewed-By: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> at Wed Jul 25 22:29:46 2012, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Thu Jul 26 00:19:56 2012, giving +2 See http://review.coreboot.org/1332 for details. -gerrit

1 0

Patch merged into coreboot/master: e5b0852 ELOG: Add support for SMM and kernel GSMI driver
by gerrit＠coreboot.org 26 Jul '12

26 Jul '12

the following patch was just integrated into master: commit e5b0852cb546d30252dbec1f323f2ce3292a6c89 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Sat Jun 23 16:48:38 2012 -0700 ELOG: Add support for SMM and kernel GSMI driver The linux kernel contains an SMI driver that was written by me (Duncan) and upstreamed a couple years ago called GSMI. This driver will format a parameter buffer and pass pointers to this parameter buffer to the SMI handler. It uses this to generate events for kernel shutdown reasons: Clean, Panic, Oops, etc. This function expects to be passed pointers into the SMM state save area that correspond to the prameter buffer and the return code, which are typically EAX and EBX. The format of the parameter buffer is defined in the kernel driver so we implement the same interface here in order to be compatible. GSMI_CMD_HANDSHAKE: this is an early call that it does to try and detect what kind of BIOS is running. GSMI_CMD_SET_EVENT_LOG: this contains a parameter buffer that has event type and data. The kernel-specific events are translated here and raw events are passed through as well which allows any run-time event to be added for testing. GSMI_CMD_CLEAR_EVENT_LOG: this command clears the event log. First the gsmi driver must be enabled in the kernel with CONFIG_GOOGLE_GSMI and then events can be added via sysfs and events are automatically generated for various kernel shutdown reasons. These can be seen in the event log as the 'Kernel Event' type: 169 | 2012-06-23 15:03:04 | Kernl Event | Clean Shutdown 181 | 2012-06-23 16:26:32 | Kernl Event | Oops 181 | 2012-06-23 16:26:32 | Kernl Event | Panic Change-Id: Ic0a3916401f0d9811e4aa8b2c560657dccc920c1 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Build-Tested: build bot (Jenkins) at Tue Jul 24 17:22:50 2012, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Thu Jul 26 00:19:39 2012, giving +2 See http://review.coreboot.org/1316 for details. -gerrit

1 0

Patch merged into coreboot/master: f8d58cf SMM: Fix state table for Intel Core2 CPUs
by gerrit＠coreboot.org 25 Jul '12

25 Jul '12

the following patch was just integrated into master: commit f8d58cf0f780238a4d820e0fb9a8227fac44a6ad Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Jul 24 14:53:15 2012 -0700 SMM: Fix state table for Intel Core2 CPUs When fixing the SMM state table for SandyBridge/IvyBridge CPUs the wrong table was used for older 64bit capable CPUs. Change-Id: Ia7dff21aa3f0e5aa61575634fc839777de6bef10 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Build-Tested: build bot (Jenkins) at Wed Jul 25 23:17:29 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Wed Jul 25 23:42:48 2012, giving +2 See http://review.coreboot.org/1353 for details. -gerrit

1 0

Patch merged into coreboot/master: 81a02a1 SMM: Skip locking SPI registers in finalize step
by gerrit＠coreboot.org 25 Jul '12

25 Jul '12

the following patch was just integrated into master: commit 81a02a12b1f4a1fb9be6217f3249debb34ed7043 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Sat Jun 23 17:02:29 2012 -0700 SMM: Skip locking SPI registers in finalize step This is a temporary workaround so the SPI bus can be accessed at runtime in SMM code until the SPI opcode menu is used properly. Change-Id: I93d188c55b66d8dce49fa91a1de53ee195944b30 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Build-Tested: build bot (Jenkins) at Tue Jul 24 17:52:43 2012, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Wed Jul 25 22:59:43 2012, giving +2 See http://review.coreboot.org/1318 for details. -gerrit

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coreboot July 2012