coreboot July 2012

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Patch merged into coreboot/master: 80dab53 Remove copies of rtl8168.c
by gerrit＠coreboot.org 26 Jul '12

26 Jul '12

the following patch was just integrated into master: commit 80dab53598a994913a21e6fd3578a12a5df799d3 Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Thu Jul 26 11:34:57 2012 +0200 Remove copies of rtl8168.c One copy was slightly different, but all the differences were commented out Change-Id: I3cc7b5621c681a1eb286f9b16ef3ebdce03abb6b Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> Build-Tested: build bot (Jenkins) at Thu Jul 26 12:27:30 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Thu Jul 26 19:02:59 2012, giving +2 See http://review.coreboot.org/1356 for details. -gerrit

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Patch set updated for coreboot: a6462e2 buildsystem: Make CPU microcode updating more configurable
by Alexandru Gagniuc 26 Jul '12

26 Jul '12

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1245 -gerrit commit a6462e2ac2ba2fb8d9b1ed23db028fe4aeab0241 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Fri Jul 20 00:11:21 2012 -0500 buildsystem: Make CPU microcode updating more configurable This patch aims to improve the microcode in CBFS handling that was brought by the last patches from Stefan and the Chromium team. choices in Kconfig - 1) Generate microcode from tree (default) - 2) Include external microcode file - 3) Do not put microcode in CBFS The idea is to give the user full control over including non-free blobs in the final ROM image. MICROCODE_INCLUDE_PATH Kconfig variable is eliminated. Microcode is handled by a special class, cpu_microcode, as such: cpu_microcode-y += microcode_file.c These files are then be compiled and assembled into a binary CBFS file. the advantage of doing it this way versus the current method is that 1) The rule is CPU-agnostic 2) This rule can work with no Kconfig variables. We use some to respect the user's choice, and intel microcode updating still requires CPU_MICROCODE_IN_CBFS. 3) When cpu_microcode-y is not specified, no microcode file is created 4) The rules for building the microcode binary are kept in src/cpu/Makefile.inc, and thus would not clobber the other makefiles, which are already overloaded and very difficult to navigate. Change-Id: I38d0c9851691aa112e93031860e94895857ebb76 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- Makefile.inc | 2 +- src/arch/x86/Makefile.inc | 28 ++++----- src/cpu/Kconfig | 89 ++++++++++++++++++++++++++-- src/cpu/Makefile.inc | 32 ++++++++++ src/cpu/intel/microcode/Makefile.inc | 20 ++----- src/cpu/intel/microcode/microcode.c | 8 +- src/cpu/intel/microcode/microcode_blob.c | 22 ------- src/cpu/intel/model_206ax/Kconfig | 5 +- src/cpu/intel/model_206ax/Makefile.inc | 2 + src/cpu/intel/model_206ax/microcode_blob.c | 22 +++++++ src/include/cpu/intel/microcode.h | 2 +- 11 files changed, 164 insertions(+), 68 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 176ff67..4122bc4 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -59,7 +59,7 @@ subdirs-y += site-local ####################################################################### # Add source classes and their build options -classes-y := ramstage romstage driver smm +classes-y := ramstage romstage driver smm cpu_microcode romstage-c-ccopts:=-D__PRE_RAM__ romstage-S-ccopts:=-D__PRE_RAM__ diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 306f239..3b27fe3 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -1,6 +1,8 @@ +################################################################################ ## ## This file is part of the coreboot project. ## +## Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> ## Copyright (C) 2009-2010 coresystems GmbH ## Copyright (C) 2009 Ronald G. Minnich ## @@ -17,8 +19,8 @@ ## along with this program; if not, write to the Free Software ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +################################################################################ -####################################################################### # Take care of subdirectories subdirs-y += boot # subdirs-y += init @@ -34,13 +36,7 @@ cmos_layout.bin-type = 0x01aa OPTION_TABLE_H:=$(obj)/option_table.h endif -ifeq ($(CONFIG_MICROCODE_IN_CBFS),y) -cbfs-files-y += microcode_blob.bin -microcode_blob.bin-file = $(obj)/microcode_blob.bin -microcode_blob.bin-type = 0x53 -endif - -####################################################################### +################################################################################ # Build the final rom image COREBOOT_ROM_DEPENDENCIES:= ifeq ($(CONFIG_PAYLOAD_ELF),y) @@ -123,7 +119,7 @@ cbfs-files-$(CONFIG_BOOTSPLASH) += bootsplash.jpg bootsplash.jpg-file := $(call strip_quotes,$(CONFIG_BOOTSPLASH_FILE)) bootsplash.jpg-type := bootsplash -####################################################################### +################################################################################ # i386 specific tools NVRAMTOOL:=$(objutil)/nvramtool/nvramtool @@ -135,7 +131,7 @@ $(obj)/cmos_layout.bin: $(NVRAMTOOL) $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.l @printf " OPTION $(subst $(obj)/,,$(@))\n" $(NVRAMTOOL) -y $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout -L $@ -####################################################################### +################################################################################ # Common recipes for all stages $(objcbfs)/%.bin: $(objcbfs)/%.elf @@ -150,7 +146,7 @@ $(objcbfs)/%.elf: $(objcbfs)/%.debug $(OBJCOPY) --add-gnu-debuglink=$< $@.tmp mv $@.tmp $@ -####################################################################### +################################################################################ # Build the coreboot_ram (stage 2) $(objcbfs)/coreboot_ram.debug: $(objgenerated)/coreboot_ram.o $(src)/arch/x86/coreboot_ram.ld @@ -174,7 +170,7 @@ $(objgenerated)/ramstage.a: $$(ramstage-objs) rm -f $@ $(AR) cr $@ $^ -####################################################################### +################################################################################ # Ramstage for AP CPU (AMD K8, obsolete?) $(objcbfs)/coreboot_ap.debug: $(objgenerated)/coreboot_ap.o $(src)/arch/x86/init/ldscript_apc.lb @@ -185,7 +181,7 @@ $(objgenerated)/coreboot_ap.o: $(src)/mainboard/$(MAINBOARDDIR)/ap_romstage.c $( @printf " CC $(subst $(obj)/,,$(@))\n" $(CC) -MMD $(CFLAGS) -I$(src) -D__PRE_RAM__ -I. -I$(obj) -c $< -o $@ -####################################################################### +################################################################################ # done crt0s = $(src)/arch/x86/init/prologue.inc @@ -264,7 +260,7 @@ ifeq ($(CONFIG_HAVE_BUS_CONFIG),y) ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/get_bus_conf.c endif -####################################################################### +################################################################################ # Build the final rom image $(obj)/coreboot.pre: $(objcbfs)/romstage_xip.elf $(obj)/coreboot.pre1 $(CBFSTOOL) @@ -274,7 +270,7 @@ $(obj)/coreboot.pre: $(objcbfs)/romstage_xip.elf $(obj)/coreboot.pre1 $(CBFSTOOL $(CONFIG_CBFS_PREFIX)/romstage x $(shell cat $(objcbfs)/base_xip.txt) mv $@.tmp $@ -####################################################################### +################################################################################ # Build the bootblock bootblock_lds = $(src)/arch/x86/init/ldscript_failover.lb @@ -331,7 +327,7 @@ else $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/bootblock.ld $< endif -####################################################################### +################################################################################ # Build the romstage $(objcbfs)/romstage_null.debug: $$(romstage-objs) $(objgenerated)/romstage_null.ld diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index baf686e..bcac1c1 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -62,10 +62,89 @@ config SSE2 streaming SIMD instructions. Some parts of coreboot can be built with more efficient code if SSE2 instructions are available. -config MICROCODE_IN_CBFS - bool "Look for microcode in CBFS" - default n +endif # ARCH_X86 + +config CPU_MICROCODE_IN_CBFS + bool + #default n + +choice + prompt "Include CPU microcode in CBFS" + default CPU_MICROCODE_CBFS_GENERATE + +config CPU_MICROCODE_CBFS_GENERATE + bool "Generate from tree" help - Load microcode updates from CBFS instead of compiling them in. + Select this option if you want microcode updates to be assembled when + building coreboot and included in the final image as a separate CBFS + file. Microcode will not be hard-coded into ramstage. -endif # ARCH_X86 + The microcode file and may be removed from the ROM image at a later + time with cbfstool, if desired. + + If unsure, select this option. + +config CPU_MICROCODE_CBFS_EXTERNAL + bool "Include external microcode file" + help + Select this option if you want to include an external file containing + the CPU microcode. This will be included as a separate file in CBFS. + A word of caution: only select this option if you are sure the + microcode that you have is newer than the microcode shipping with + coreboot. + + The microcode file and may be removed from the ROM image at a later + time with cbfstool, if desired. + + If unsure, select "Generate from tree" + +config CPU_MICROCODE_FILE + string "Path and filename of CPU microcode" + depends on CPU_MICROCODE_CBFS_EXTERNAL + default "cpu_microcode.bin" + help + The path and filename of the file containing the CPU microcode. + +config CPU_MICROCODE_CBFS_NONE + bool "Do not include microcode updates" + help + Select this option if you do not want CPU microcode included in CBFS. + Note that for some CPUs, the microcode is hard-coded into the source + tree and is not loaded from CBFS. In this case, microcode will still + be updated. There is a push to move all microcode to CBFS, but this + change is not implemented for all CPUs. + + This option currently applies to: + - Intel SandyBridge/IvyBridge + - VIA Nano + + Microcode may be added to the ROM image at a later time with cbfstool, + if desired. + + If unsure, select "Generate from tree" + + The GOOD: + Microcode updates intend to solve issues that have been discovered + after CPU production. The expected effect is that systems work as + intended with the updated microcode, but we have also seen cases where + issues were solved by not applying microcode updates. + + The BAD: + Note that some operating system include these same microcode patches, + so you may need to also disable microcode updates in your operating + system for this option to have an effect. + + The UGLY: + A word of CAUTION: some CPUs depend on microcode updates to function + correctly. Not updating the microcode may leave the CPU operating at + less than optimal performance, or may cause outright hangups. + There are CPUs where coreboot cannot properly initialize the CPU + without microcode updates + For example, if running with the factory microcode, some Intel + SandyBridge CPUs may hang when enabling CAR, or some VIA Nano CPUs + will hang when changing the frequency. + + Make sure you have a way of flashing the ROM externally before + selecting this option. + +endchoice diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc index 57273cf..baeae30 100644 --- a/src/cpu/Makefile.inc +++ b/src/cpu/Makefile.inc @@ -1,3 +1,35 @@ +################################################################################ +## Subdirectories +################################################################################ subdirs-y += amd subdirs-y += intel subdirs-y += via + + +################################################################################ +## Rules for building the microcode blob in CBFS +################################################################################ + +ifneq ($(CONFIG_CPU_MICROCODE_CBFS_NONE), y) +ifneq ($$(cpu_microcode-objs), $(empty)) + +cbfs-files-y += cpu_microcode_blob.bin + +cpu_microcode_blob.bin-type = 0x53 + +# External microcode file, or are we generating one ? +ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL), y) + cpu_microcode_blob.bin-file = $(CONFIG_CPU_MICROCODE_FILE) +else + cpu_microcode_blob.bin-file = $(obj)/cpu_microcode_blob.bin +endif + +$(obj)/cpu_microcode_blob.o: $$(cpu_microcode-objs) + cat $< > $@ + +$(obj)/cpu_microcode_blob.bin: $(obj)/cpu_microcode_blob.o + @printf " MICROCODE $(subst $(obj)/,,$(@))\n" + $(OBJCOPY) -j .data -O binary $< $@ + +endif +endif \ No newline at end of file diff --git a/src/cpu/intel/microcode/Makefile.inc b/src/cpu/intel/microcode/Makefile.inc index f4d0102..22655c9 100644 --- a/src/cpu/intel/microcode/Makefile.inc +++ b/src/cpu/intel/microcode/Makefile.inc @@ -1,15 +1,5 @@ -ramstage-y += microcode.c - - -ifeq ($(CONFIG_MICROCODE_IN_CBFS),y) - -SRC_PATH = src/cpu/intel/microcode -FLAGS = -I $(CONFIG_MICROCODE_INCLUDE_PATH) -include $(obj)/config.h -$(obj)/microcode_blob.o: $(SRC_PATH)/microcode_blob.c - $(CC) $(FLAGS) -MMD -c -o $@ $< - -$(obj)/microcode_blob.bin: $(obj)/microcode_blob.o - objcopy -j .data -O binary $< $@ - --include $(obj)/microcode_blob.d -endif +################################################################################ +## One small file with the awesome super-power of updating the cpu microcode +## directly from CBFS. You have been WARNED!!! +################################################################################ +ramstage-y += microcode.c \ No newline at end of file diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index e84bad9..a4471ca 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -28,7 +28,7 @@ #include <cpu/x86/msr.h> #include <cpu/intel/microcode.h> -#if CONFIG_MICROCODE_IN_CBFS +#if CONFIG_CPU_MICROCODE_IN_CBFS #ifdef __PRE_RAM__ #include <arch/cbfs.h> #else @@ -77,7 +77,7 @@ static inline u32 read_microcode_rev(void) return msr.hi; } -#if CONFIG_MICROCODE_IN_CBFS +#if CONFIG_CPU_MICROCODE_IN_CBFS static #endif void intel_update_microcode(const void *microcode_updates) @@ -144,9 +144,9 @@ void intel_update_microcode(const void *microcode_updates) } } -#if CONFIG_MICROCODE_IN_CBFS +#if CONFIG_CPU_MICROCODE_IN_CBFS -#define MICROCODE_CBFS_FILE "microcode_blob.bin" +#define MICROCODE_CBFS_FILE "cpu_microcode_blob.bin" void intel_update_microcode_from_cbfs(void) { diff --git a/src/cpu/intel/microcode/microcode_blob.c b/src/cpu/intel/microcode/microcode_blob.c deleted file mode 100644 index 69238a9..0000000 --- a/src/cpu/intel/microcode/microcode_blob.c +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -unsigned microcode[] = { -#include <microcode_blob.h> -}; diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index 071683e..1b4351e 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -12,7 +12,7 @@ config CPU_SPECIFIC_OPTIONS select SSE2 select UDELAY_LAPIC select SMM_TSEG - select MICROCODE_IN_CBFS + select CPU_MICROCODE_IN_CBFS config BOOTBLOCK_CPU_INIT string @@ -22,9 +22,6 @@ config SMM_TSEG_SIZE hex default 0x800000 -config MICROCODE_INCLUDE_PATH - string - default "src/cpu/intel/model_206ax" endif if CPU_INTEL_MODEL_206AX diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc index e9b8e6d..eb2dfa2 100644 --- a/src/cpu/intel/model_206ax/Makefile.inc +++ b/src/cpu/intel/model_206ax/Makefile.inc @@ -5,4 +5,6 @@ ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c +#cpu_microcode-y += microcode_blob.c + cpu_incs += $(src)/cpu/intel/model_206ax/cache_as_ram.inc diff --git a/src/cpu/intel/model_206ax/microcode_blob.c b/src/cpu/intel/model_206ax/microcode_blob.c new file mode 100644 index 0000000..c2538e8 --- /dev/null +++ b/src/cpu/intel/model_206ax/microcode_blob.c @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +unsigned microcode[] = { +#include "microcode_blob.h" +}; diff --git a/src/include/cpu/intel/microcode.h b/src/include/cpu/intel/microcode.h index 289e919..e9c13f9 100644 --- a/src/include/cpu/intel/microcode.h +++ b/src/include/cpu/intel/microcode.h @@ -21,7 +21,7 @@ #define __CPU__INTEL__MICROCODE__ #ifndef __PRE_RAM__ -#if CONFIG_MICROCODE_IN_CBFS +#if CONFIG_CPU_MICROCODE_IN_CBFS void intel_update_microcode_from_cbfs(void); #else void intel_update_microcode(const void *microcode_updates);

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Patch set updated for coreboot: bcf28c8 buildsystem: Make CPU microcode updating more configurable
by Alexandru Gagniuc 26 Jul '12

26 Jul '12

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1245 -gerrit commit bcf28c8e6ab79121289d6b83a7e3266221c2bf88 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Fri Jul 20 00:11:21 2012 -0500 buildsystem: Make CPU microcode updating more configurable This patch aims to improve the microcode in CBFS handling that was brought by the last patches from Stefan and the Chromium team. choices in Kconfig - 1) Generate microcode from tree (default) - 2) Include external microcode file - 3) Do not put microcode in CBFS The idea is to give the user full control over including non-free blobs in the final ROM image. MICROCODE_IN_CBFS, and MICROCODE_INCLUDE_PATH are eliminated. Microcode is handled by a special class, cpu_microcode, as such: cpu_microcode-y += microcode_file.c These files are then be compiled and assembled into a binary CBFS file. the advantage of doing it this way versus the current method is that 1) The rule is CPU-agnostic 2) This rule can work with no Kconfig variables (but we use some to respect the user's choice) 3) When cpu_microcode-y is not specified, no microcode file is created 4) The rules for building the microcode binary are kept in src/cpu/Makefile.inc, and thus would not clobber the other makefiles, which are already overloaded and very difficult to navigate. Change-Id: I38d0c9851691aa112e93031860e94895857ebb76 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- Makefile.inc | 2 +- src/arch/x86/Makefile.inc | 28 ++++----- src/cpu/Kconfig | 85 ++++++++++++++++++++++++++-- src/cpu/Makefile.inc | 32 ++++++++++ src/cpu/intel/microcode/Makefile.inc | 20 ++----- src/cpu/intel/microcode/microcode.c | 8 +- src/cpu/intel/microcode/microcode_blob.c | 22 ------- src/cpu/intel/model_206ax/Kconfig | 4 - src/cpu/intel/model_206ax/Makefile.inc | 2 + src/cpu/intel/model_206ax/microcode_blob.c | 22 +++++++ src/include/cpu/intel/microcode.h | 2 +- 11 files changed, 159 insertions(+), 68 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 176ff67..4122bc4 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -59,7 +59,7 @@ subdirs-y += site-local ####################################################################### # Add source classes and their build options -classes-y := ramstage romstage driver smm +classes-y := ramstage romstage driver smm cpu_microcode romstage-c-ccopts:=-D__PRE_RAM__ romstage-S-ccopts:=-D__PRE_RAM__ diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 306f239..3b27fe3 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -1,6 +1,8 @@ +################################################################################ ## ## This file is part of the coreboot project. ## +## Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> ## Copyright (C) 2009-2010 coresystems GmbH ## Copyright (C) 2009 Ronald G. Minnich ## @@ -17,8 +19,8 @@ ## along with this program; if not, write to the Free Software ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +################################################################################ -####################################################################### # Take care of subdirectories subdirs-y += boot # subdirs-y += init @@ -34,13 +36,7 @@ cmos_layout.bin-type = 0x01aa OPTION_TABLE_H:=$(obj)/option_table.h endif -ifeq ($(CONFIG_MICROCODE_IN_CBFS),y) -cbfs-files-y += microcode_blob.bin -microcode_blob.bin-file = $(obj)/microcode_blob.bin -microcode_blob.bin-type = 0x53 -endif - -####################################################################### +################################################################################ # Build the final rom image COREBOOT_ROM_DEPENDENCIES:= ifeq ($(CONFIG_PAYLOAD_ELF),y) @@ -123,7 +119,7 @@ cbfs-files-$(CONFIG_BOOTSPLASH) += bootsplash.jpg bootsplash.jpg-file := $(call strip_quotes,$(CONFIG_BOOTSPLASH_FILE)) bootsplash.jpg-type := bootsplash -####################################################################### +################################################################################ # i386 specific tools NVRAMTOOL:=$(objutil)/nvramtool/nvramtool @@ -135,7 +131,7 @@ $(obj)/cmos_layout.bin: $(NVRAMTOOL) $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.l @printf " OPTION $(subst $(obj)/,,$(@))\n" $(NVRAMTOOL) -y $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout -L $@ -####################################################################### +################################################################################ # Common recipes for all stages $(objcbfs)/%.bin: $(objcbfs)/%.elf @@ -150,7 +146,7 @@ $(objcbfs)/%.elf: $(objcbfs)/%.debug $(OBJCOPY) --add-gnu-debuglink=$< $@.tmp mv $@.tmp $@ -####################################################################### +################################################################################ # Build the coreboot_ram (stage 2) $(objcbfs)/coreboot_ram.debug: $(objgenerated)/coreboot_ram.o $(src)/arch/x86/coreboot_ram.ld @@ -174,7 +170,7 @@ $(objgenerated)/ramstage.a: $$(ramstage-objs) rm -f $@ $(AR) cr $@ $^ -####################################################################### +################################################################################ # Ramstage for AP CPU (AMD K8, obsolete?) $(objcbfs)/coreboot_ap.debug: $(objgenerated)/coreboot_ap.o $(src)/arch/x86/init/ldscript_apc.lb @@ -185,7 +181,7 @@ $(objgenerated)/coreboot_ap.o: $(src)/mainboard/$(MAINBOARDDIR)/ap_romstage.c $( @printf " CC $(subst $(obj)/,,$(@))\n" $(CC) -MMD $(CFLAGS) -I$(src) -D__PRE_RAM__ -I. -I$(obj) -c $< -o $@ -####################################################################### +################################################################################ # done crt0s = $(src)/arch/x86/init/prologue.inc @@ -264,7 +260,7 @@ ifeq ($(CONFIG_HAVE_BUS_CONFIG),y) ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/get_bus_conf.c endif -####################################################################### +################################################################################ # Build the final rom image $(obj)/coreboot.pre: $(objcbfs)/romstage_xip.elf $(obj)/coreboot.pre1 $(CBFSTOOL) @@ -274,7 +270,7 @@ $(obj)/coreboot.pre: $(objcbfs)/romstage_xip.elf $(obj)/coreboot.pre1 $(CBFSTOOL $(CONFIG_CBFS_PREFIX)/romstage x $(shell cat $(objcbfs)/base_xip.txt) mv $@.tmp $@ -####################################################################### +################################################################################ # Build the bootblock bootblock_lds = $(src)/arch/x86/init/ldscript_failover.lb @@ -331,7 +327,7 @@ else $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/bootblock.ld $< endif -####################################################################### +################################################################################ # Build the romstage $(objcbfs)/romstage_null.debug: $$(romstage-objs) $(objgenerated)/romstage_null.ld diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index baf686e..d41b1bd 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -62,10 +62,85 @@ config SSE2 streaming SIMD instructions. Some parts of coreboot can be built with more efficient code if SSE2 instructions are available. -config MICROCODE_IN_CBFS - bool "Look for microcode in CBFS" - default n +endif # ARCH_X86 + +choice + prompt "Include CPU microcode in CBFS" + default CPU_MICROCODE_CBFS_GENERATE + +config CPU_MICROCODE_CBFS_GENERATE + bool "Generate from tree" help - Load microcode updates from CBFS instead of compiling them in. + Select this option if you want microcode updates to be assembled when + building coreboot and included in the final image as a separate CBFS + file. Microcode will not be hard-coded into ramstage. -endif # ARCH_X86 + The microcode file and may be removed from the ROM image at a later + time with cbfstool, if desired. + + If unsure, select this option. + +config CPU_MICROCODE_CBFS_EXTERNAL + bool "Include external microcode file" + help + Select this option if you want to include an external file containing + the CPU microcode. This will be included as a separate file in CBFS. + A word of caution: only select this option if you are sure the + microcode that you have is newer than the microcode shipping with + coreboot. + + The microcode file and may be removed from the ROM image at a later + time with cbfstool, if desired. + + If unsure, select "Generate from tree" + +config CPU_MICROCODE_FILE + string "Path and filename of CPU microcode" + depends on CPU_MICROCODE_CBFS_EXTERNAL + default "cpu_microcode.bin" + help + The path and filename of the file containing the CPU microcode. + +config CPU_MICROCODE_CBFS_NONE + bool "Do not include microcode updates" + help + Select this option if you do not want CPU microcode included in CBFS. + Note that for some CPUs, the microcode is hard-coded into the source + tree and is not loaded from CBFS. In this case, microcode will still + be updated. There is a push to move all microcode to CBFS, but this + change is not implemented for all CPUs. + + This option currently applies to: + - Intel SandyBridge/IvyBridge + - VIA Nano + + Microcode may be added to the ROM image at a later time with cbfstool, + if desired. + + If unsure, select "Generate from tree" + + The GOOD: + Microcode updates intend to solve issues that have been discovered + after CPU production. The expected effect is that systems work as + intended with the updated microcode, but we have also seen cases where + issues were solved by not applying microcode updates. + + The BAD: + Note that some operating system include these same microcode patches, + so you may need to also disable microcode updates in your operating + system for this option to have an effect. + + The UGLY: + A word of CAUTION: some CPUs depend on microcode updates to function + correctly. Not updating the microcode may leave the CPU operating at + less than optimal performance, or may cause outright hangups. + There are CPUs where coreboot cannot properly initialize the CPU + without microcode updates + For example, if running with the factory microcode, some Intel + SandyBridge CPUs may hang when enabling CAR, or some VIA Nano CPUs + will hang when changing the frequency. + + Make sure you have a way of flashing the ROM externally before + selecting this option. + +endchoice diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc index 57273cf..f74970f 100644 --- a/src/cpu/Makefile.inc +++ b/src/cpu/Makefile.inc @@ -1,3 +1,35 @@ +################################################################################ +## Subdirectories +################################################################################ subdirs-y += amd subdirs-y += intel subdirs-y += via + + +################################################################################ +## Rules for building the microcode blob in CBFS +################################################################################ + +ifneq ($(CONFIG_CPU_MICROCODE_CBFS_NONE), y) +ifneq ($(cpu_microcode-objs), $(empty)) + +cbfs-files-y += cpu_microcode_blob.bin + +cpu_microcode_blob.bin-type = 0x53 + +# External microcode file, or are we generating one ? +ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL), y) + cpu_microcode_blob.bin-file = $(CONFIG_CPU_MICROCODE_FILE) +else + cpu_microcode_blob.bin-file = $(obj)/cpu_microcode_blob.bin +endif + +$(obj)/cpu_microcode_blob.o: $$(cpu_microcode-objs) + cat $< > $@ + +$(obj)/cpu_microcode_blob.bin: $(obj)/cpu_microcode_blob.o + @printf " MICROCODE $(subst $(obj)/,,$(@))\n" + $(OBJCOPY) -j .data -O binary $< $@ + +endif +endif \ No newline at end of file diff --git a/src/cpu/intel/microcode/Makefile.inc b/src/cpu/intel/microcode/Makefile.inc index f4d0102..22655c9 100644 --- a/src/cpu/intel/microcode/Makefile.inc +++ b/src/cpu/intel/microcode/Makefile.inc @@ -1,15 +1,5 @@ -ramstage-y += microcode.c - - -ifeq ($(CONFIG_MICROCODE_IN_CBFS),y) - -SRC_PATH = src/cpu/intel/microcode -FLAGS = -I $(CONFIG_MICROCODE_INCLUDE_PATH) -include $(obj)/config.h -$(obj)/microcode_blob.o: $(SRC_PATH)/microcode_blob.c - $(CC) $(FLAGS) -MMD -c -o $@ $< - -$(obj)/microcode_blob.bin: $(obj)/microcode_blob.o - objcopy -j .data -O binary $< $@ - --include $(obj)/microcode_blob.d -endif +################################################################################ +## One small file with the awesome super-power of updating the cpu microcode +## directly from CBFS. You have been WARNED!!! +################################################################################ +ramstage-y += microcode.c \ No newline at end of file diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index e84bad9..a4471ca 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -28,7 +28,7 @@ #include <cpu/x86/msr.h> #include <cpu/intel/microcode.h> -#if CONFIG_MICROCODE_IN_CBFS +#if CONFIG_CPU_MICROCODE_IN_CBFS #ifdef __PRE_RAM__ #include <arch/cbfs.h> #else @@ -77,7 +77,7 @@ static inline u32 read_microcode_rev(void) return msr.hi; } -#if CONFIG_MICROCODE_IN_CBFS +#if CONFIG_CPU_MICROCODE_IN_CBFS static #endif void intel_update_microcode(const void *microcode_updates) @@ -144,9 +144,9 @@ void intel_update_microcode(const void *microcode_updates) } } -#if CONFIG_MICROCODE_IN_CBFS +#if CONFIG_CPU_MICROCODE_IN_CBFS -#define MICROCODE_CBFS_FILE "microcode_blob.bin" +#define MICROCODE_CBFS_FILE "cpu_microcode_blob.bin" void intel_update_microcode_from_cbfs(void) { diff --git a/src/cpu/intel/microcode/microcode_blob.c b/src/cpu/intel/microcode/microcode_blob.c deleted file mode 100644 index 69238a9..0000000 --- a/src/cpu/intel/microcode/microcode_blob.c +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -unsigned microcode[] = { -#include <microcode_blob.h> -}; diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index 071683e..6c70993 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -12,7 +12,6 @@ config CPU_SPECIFIC_OPTIONS select SSE2 select UDELAY_LAPIC select SMM_TSEG - select MICROCODE_IN_CBFS config BOOTBLOCK_CPU_INIT string @@ -22,9 +21,6 @@ config SMM_TSEG_SIZE hex default 0x800000 -config MICROCODE_INCLUDE_PATH - string - default "src/cpu/intel/model_206ax" endif if CPU_INTEL_MODEL_206AX diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc index e9b8e6d..990a7fa 100644 --- a/src/cpu/intel/model_206ax/Makefile.inc +++ b/src/cpu/intel/model_206ax/Makefile.inc @@ -5,4 +5,6 @@ ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c +cpu_microcode-y += microcode_blob.c + cpu_incs += $(src)/cpu/intel/model_206ax/cache_as_ram.inc diff --git a/src/cpu/intel/model_206ax/microcode_blob.c b/src/cpu/intel/model_206ax/microcode_blob.c new file mode 100644 index 0000000..c2538e8 --- /dev/null +++ b/src/cpu/intel/model_206ax/microcode_blob.c @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +unsigned microcode[] = { +#include "microcode_blob.h" +}; diff --git a/src/include/cpu/intel/microcode.h b/src/include/cpu/intel/microcode.h index 289e919..e9c13f9 100644 --- a/src/include/cpu/intel/microcode.h +++ b/src/include/cpu/intel/microcode.h @@ -21,7 +21,7 @@ #define __CPU__INTEL__MICROCODE__ #ifndef __PRE_RAM__ -#if CONFIG_MICROCODE_IN_CBFS +#if CONFIG_CPU_MICROCODE_IN_CBFS void intel_update_microcode_from_cbfs(void); #else void intel_update_microcode(const void *microcode_updates);

1 0

Patch merged into coreboot/master: 58f58a2 USBDEBUG: buffer up to 8 bytes
by gerrit＠coreboot.org 26 Jul '12

26 Jul '12

the following patch was just integrated into master: commit 58f58a25e95d773b1ab454d2d1acbc27dfb143d4 Author: Sven Schnelle <svens(a)stackframe.org> Date: Thu Jul 26 14:31:40 2012 +0200 USBDEBUG: buffer up to 8 bytes EHCI debug allows to send message with 8 bytes length, but we're only sending one byte in each transaction. Buffer up to 8 bytes to speed up debug output. Change-Id: I9dbb406833c4966c3afbd610e1b13a8fa3d62f39 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> See http://review.coreboot.org/1357 for details. -gerrit

1 0

How can get 3rd party bins like mrc.bin for SandyBridge/Ivybridge
by wx 26 Jul '12

26 Jul '12

How can get 3rd party bins like mrc.bin for SandyBridge/Ivybridge ? Folder 3rdparty is empty when I download the coreboot src using git

2 1

Patch set updated for coreboot: 58f58a2 USBDEBUG: buffer up to 8 bytes
by Sven Schnelle 26 Jul '12

26 Jul '12

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1357 -gerrit commit 58f58a25e95d773b1ab454d2d1acbc27dfb143d4 Author: Sven Schnelle <svens(a)stackframe.org> Date: Thu Jul 26 14:31:40 2012 +0200 USBDEBUG: buffer up to 8 bytes EHCI debug allows to send message with 8 bytes length, but we're only sending one byte in each transaction. Buffer up to 8 bytes to speed up debug output. Change-Id: I9dbb406833c4966c3afbd610e1b13a8fa3d62f39 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/arch/x86/lib/romstage_console.c | 5 ++++- src/console/usbdebug_console.c | 9 +++++++-- src/cpu/x86/smm/smiutil.c | 7 ++++--- src/include/usbdebug.h | 5 ++++- src/lib/usbdebug.c | 33 ++++++++++++++++++++++++++------- 5 files changed, 45 insertions(+), 14 deletions(-) diff --git a/src/arch/x86/lib/romstage_console.c b/src/arch/x86/lib/romstage_console.c index 25eda9b..af2944d 100644 --- a/src/arch/x86/lib/romstage_console.c +++ b/src/arch/x86/lib/romstage_console.c @@ -44,7 +44,7 @@ static void console_tx_byte(unsigned char byte) uart8250_tx_byte(CONFIG_TTYS0_BASE, byte); #endif #if CONFIG_USBDEBUG - usbdebug_tx_byte(byte); + usbdebug_tx_byte(0, byte); #endif #if CONFIG_CONSOLE_NE2K ne2k_append_data(&byte, 1, CONFIG_CONSOLE_NE2K_IO_PORT); @@ -65,6 +65,9 @@ static void console_tx_flush(void) #if CONFIG_CONSOLE_NE2K ne2k_transmit(CONFIG_CONSOLE_NE2K_IO_PORT); #endif +#if CONFIG_USBDEBUG + usbdebug_tx_flush(0); +#endif } int do_printk(int msg_level, const char *fmt, ...) diff --git a/src/console/usbdebug_console.c b/src/console/usbdebug_console.c index a624b9d..58a62b8 100644 --- a/src/console/usbdebug_console.c +++ b/src/console/usbdebug_console.c @@ -55,8 +55,7 @@ static void dbgp_init(void) static void dbgp_tx_byte(unsigned char data) { - if (dbg_info.ehci_debug) - dbgp_bulk_write_x(&dbg_info, (char*)&data, 1); + usbdebug_tx_byte(&dbg_info, data); } static unsigned char dbgp_rx_byte(void) @@ -69,6 +68,11 @@ static unsigned char dbgp_rx_byte(void) return data; } +static void dbgp_tx_flush(void) +{ + usbdebug_tx_flush(&dbg_info); +} + static int dbgp_tst_byte(void) { return (int)dbg_info.ehci_debug; @@ -77,6 +81,7 @@ static int dbgp_tst_byte(void) static const struct console_driver usbdebug_direct_console __console = { .init = dbgp_init, .tx_byte = dbgp_tx_byte, + .tx_flush = dbgp_tx_flush, .rx_byte = dbgp_rx_byte, .tst_byte = dbgp_tst_byte, }; diff --git a/src/cpu/x86/smm/smiutil.c b/src/cpu/x86/smm/smiutil.c index 9cd63ed..1d2c86f 100644 --- a/src/cpu/x86/smm/smiutil.c +++ b/src/cpu/x86/smm/smiutil.c @@ -32,8 +32,9 @@ static u32 serial8250mem_base_address = 0; void console_tx_flush(void) { - // the tx_byte functions take care of the flush. - // if not, this should be implemented. +#if CONFIG_USBDEBUG + usbdebug_tx_flush(0); +#endif } void console_tx_byte(unsigned char byte) @@ -49,7 +50,7 @@ void console_tx_byte(unsigned char byte) uart8250_tx_byte(CONFIG_TTYS0_BASE, byte); #endif #if CONFIG_USBDEBUG - usbdebug_tx_byte(byte); + usbdebug_tx_byte(0, byte); #endif #if CONFIG_CONSOLE_NE2K ne2k_append_data(&byte, 1, CONFIG_CONSOLE_NE2K_IO_PORT); diff --git a/src/include/usbdebug.h b/src/include/usbdebug.h index a7ab21f..8caf361 100644 --- a/src/include/usbdebug.h +++ b/src/include/usbdebug.h @@ -30,6 +30,8 @@ struct ehci_debug_info { u32 devnum; u32 endpoint_out; u32 endpoint_in; + char buf[8]; + u8 bufidx; }; #ifndef __ROMCC__ @@ -41,7 +43,8 @@ void set_ehci_debug(unsigned ehci_debug); unsigned get_ehci_debug(void); void set_debug_port(unsigned port); int early_usbdebug_init(void); -void usbdebug_tx_byte(unsigned char data); +void usbdebug_tx_byte(struct ehci_debug_info *info, unsigned char data); +void usbdebug_tx_flush(struct ehci_debug_info *info); int usbdebug_init(unsigned ehci_bar, unsigned offset, struct ehci_debug_info *info); #endif #endif diff --git a/src/lib/usbdebug.c b/src/lib/usbdebug.c index 800ee52..fd23426 100644 --- a/src/lib/usbdebug.c +++ b/src/lib/usbdebug.c @@ -377,7 +377,7 @@ int usbdebug_init(unsigned ehci_bar, unsigned offset, struct ehci_debug_info *in HC_LENGTH(read32((unsigned long)&ehci_caps->hc_capbase))); ehci_debug = (struct ehci_dbg_port *)(ehci_bar + offset); info->ehci_debug = (void *)0; - + info->bufidx = 0; try_next_time: port_map_tried = 0; @@ -573,15 +573,34 @@ int early_usbdebug_init(void) return usbdebug_init(CONFIG_EHCI_BAR, CONFIG_EHCI_DEBUG_OFFSET, dbg_info); } -void usbdebug_tx_byte(unsigned char data) +void usbdebug_tx_byte(struct ehci_debug_info *dbg_info, unsigned char data) { - struct ehci_debug_info *dbg_info; - /* "Find" dbg_info structure in Cache */ - dbg_info = (struct ehci_debug_info *) - (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - sizeof(struct ehci_debug_info)); + if (!dbg_info) { + /* "Find" dbg_info structure in Cache */ + dbg_info = (struct ehci_debug_info *) + (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - sizeof(struct ehci_debug_info)); + } if (dbg_info->ehci_debug) { - dbgp_bulk_write_x(dbg_info, (char*)&data, 1); + dbg_info->buf[dbg_info->bufidx++] = data; + if (dbg_info->bufidx >= 8) { + dbgp_bulk_write_x(dbg_info, dbg_info->buf, dbg_info->bufidx); + dbg_info->bufidx = 0; + } + } +} + +void usbdebug_tx_flush(struct ehci_debug_info *dbg_info) +{ + if (!dbg_info) { + /* "Find" dbg_info structure in Cache */ + dbg_info = (struct ehci_debug_info *) + (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - sizeof(struct ehci_debug_info)); + } + + if (dbg_info->ehci_debug && dbg_info->bufidx > 0) { + dbgp_bulk_write_x(dbg_info, dbg_info->buf, dbg_info->bufidx); + dbg_info->bufidx = 0; } }

1 0

New patch to review for coreboot: 6b603ab USBDEBUG: buffer up to 8 bytes
by Sven Schnelle 26 Jul '12

26 Jul '12

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1357 -gerrit commit 6b603ab770494a30e3232934aba0ea753167e528 Author: Sven Schnelle <svens(a)stackframe.org> Date: Thu Jul 26 14:31:40 2012 +0200 USBDEBUG: buffer up to 8 bytes EHCI debug allows to send message with 8 bytes length, but we're only sending one byte in each transaction. Buffer up to 8 bytes to speed up debug output. Change-Id: I9dbb406833c4966c3afbd610e1b13a8fa3d62f39 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/arch/x86/lib/romstage_console.c | 5 ++++- src/console/usbdebug_console.c | 9 +++++++-- src/cpu/x86/smm/smiutil.c | 7 ++++--- src/include/usbdebug.h | 5 ++++- src/lib/usbdebug.c | 33 ++++++++++++++++++++++++++------- 5 files changed, 45 insertions(+), 14 deletions(-) diff --git a/src/arch/x86/lib/romstage_console.c b/src/arch/x86/lib/romstage_console.c index 25eda9b..af2944d 100644 --- a/src/arch/x86/lib/romstage_console.c +++ b/src/arch/x86/lib/romstage_console.c @@ -44,7 +44,7 @@ static void console_tx_byte(unsigned char byte) uart8250_tx_byte(CONFIG_TTYS0_BASE, byte); #endif #if CONFIG_USBDEBUG - usbdebug_tx_byte(byte); + usbdebug_tx_byte(0, byte); #endif #if CONFIG_CONSOLE_NE2K ne2k_append_data(&byte, 1, CONFIG_CONSOLE_NE2K_IO_PORT); @@ -65,6 +65,9 @@ static void console_tx_flush(void) #if CONFIG_CONSOLE_NE2K ne2k_transmit(CONFIG_CONSOLE_NE2K_IO_PORT); #endif +#if CONFIG_USBDEBUG + usbdebug_tx_flush(0); +#endif } int do_printk(int msg_level, const char *fmt, ...) diff --git a/src/console/usbdebug_console.c b/src/console/usbdebug_console.c index a624b9d..58a62b8 100644 --- a/src/console/usbdebug_console.c +++ b/src/console/usbdebug_console.c @@ -55,8 +55,7 @@ static void dbgp_init(void) static void dbgp_tx_byte(unsigned char data) { - if (dbg_info.ehci_debug) - dbgp_bulk_write_x(&dbg_info, (char*)&data, 1); + usbdebug_tx_byte(&dbg_info, data); } static unsigned char dbgp_rx_byte(void) @@ -69,6 +68,11 @@ static unsigned char dbgp_rx_byte(void) return data; } +static void dbgp_tx_flush(void) +{ + usbdebug_tx_flush(&dbg_info); +} + static int dbgp_tst_byte(void) { return (int)dbg_info.ehci_debug; @@ -77,6 +81,7 @@ static int dbgp_tst_byte(void) static const struct console_driver usbdebug_direct_console __console = { .init = dbgp_init, .tx_byte = dbgp_tx_byte, + .tx_flush = dbgp_tx_flush, .rx_byte = dbgp_rx_byte, .tst_byte = dbgp_tst_byte, }; diff --git a/src/cpu/x86/smm/smiutil.c b/src/cpu/x86/smm/smiutil.c index 9cd63ed..1d2c86f 100644 --- a/src/cpu/x86/smm/smiutil.c +++ b/src/cpu/x86/smm/smiutil.c @@ -32,8 +32,9 @@ static u32 serial8250mem_base_address = 0; void console_tx_flush(void) { - // the tx_byte functions take care of the flush. - // if not, this should be implemented. +#if CONFIG_USBDEBUG + usbdebug_tx_flush(0); +#endif } void console_tx_byte(unsigned char byte) @@ -49,7 +50,7 @@ void console_tx_byte(unsigned char byte) uart8250_tx_byte(CONFIG_TTYS0_BASE, byte); #endif #if CONFIG_USBDEBUG - usbdebug_tx_byte(byte); + usbdebug_tx_byte(0, byte); #endif #if CONFIG_CONSOLE_NE2K ne2k_append_data(&byte, 1, CONFIG_CONSOLE_NE2K_IO_PORT); diff --git a/src/include/usbdebug.h b/src/include/usbdebug.h index a7ab21f..8caf361 100644 --- a/src/include/usbdebug.h +++ b/src/include/usbdebug.h @@ -30,6 +30,8 @@ struct ehci_debug_info { u32 devnum; u32 endpoint_out; u32 endpoint_in; + char buf[8]; + u8 bufidx; }; #ifndef __ROMCC__ @@ -41,7 +43,8 @@ void set_ehci_debug(unsigned ehci_debug); unsigned get_ehci_debug(void); void set_debug_port(unsigned port); int early_usbdebug_init(void); -void usbdebug_tx_byte(unsigned char data); +void usbdebug_tx_byte(struct ehci_debug_info *info, unsigned char data); +void usbdebug_tx_flush(struct ehci_debug_info *info); int usbdebug_init(unsigned ehci_bar, unsigned offset, struct ehci_debug_info *info); #endif #endif diff --git a/src/lib/usbdebug.c b/src/lib/usbdebug.c index 800ee52..fd23426 100644 --- a/src/lib/usbdebug.c +++ b/src/lib/usbdebug.c @@ -377,7 +377,7 @@ int usbdebug_init(unsigned ehci_bar, unsigned offset, struct ehci_debug_info *in HC_LENGTH(read32((unsigned long)&ehci_caps->hc_capbase))); ehci_debug = (struct ehci_dbg_port *)(ehci_bar + offset); info->ehci_debug = (void *)0; - + info->bufidx = 0; try_next_time: port_map_tried = 0; @@ -573,15 +573,34 @@ int early_usbdebug_init(void) return usbdebug_init(CONFIG_EHCI_BAR, CONFIG_EHCI_DEBUG_OFFSET, dbg_info); } -void usbdebug_tx_byte(unsigned char data) +void usbdebug_tx_byte(struct ehci_debug_info *dbg_info, unsigned char data) { - struct ehci_debug_info *dbg_info; - /* "Find" dbg_info structure in Cache */ - dbg_info = (struct ehci_debug_info *) - (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - sizeof(struct ehci_debug_info)); + if (!dbg_info) { + /* "Find" dbg_info structure in Cache */ + dbg_info = (struct ehci_debug_info *) + (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - sizeof(struct ehci_debug_info)); + } if (dbg_info->ehci_debug) { - dbgp_bulk_write_x(dbg_info, (char*)&data, 1); + dbg_info->buf[dbg_info->bufidx++] = data; + if (dbg_info->bufidx >= 8) { + dbgp_bulk_write_x(dbg_info, dbg_info->buf, dbg_info->bufidx); + dbg_info->bufidx = 0; + } + } +} + +void usbdebug_tx_flush(struct ehci_debug_info *dbg_info) +{ + if (!dbg_info) { + /* "Find" dbg_info structure in Cache */ + dbg_info = (struct ehci_debug_info *) + (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - sizeof(struct ehci_debug_info)); + } + + if (dbg_info->ehci_debug && dbg_info->bufidx > 0) { + dbgp_bulk_write_x(dbg_info, dbg_info->buf, dbg_info->bufidx); + dbg_info->bufidx = 0; } }

1 0

New patch to review for coreboot: 80dab53 Remove copies of rtl8168.c
by Patrick Georgi 26 Jul '12

26 Jul '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1356 -gerrit commit 80dab53598a994913a21e6fd3578a12a5df799d3 Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Thu Jul 26 11:34:57 2012 +0200 Remove copies of rtl8168.c One copy was slightly different, but all the differences were commented out Change-Id: I3cc7b5621c681a1eb286f9b16ef3ebdce03abb6b Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> --- src/drivers/Kconfig | 1 + src/drivers/Makefile.inc | 1 + src/drivers/realtek/Kconfig | 6 ++ src/drivers/realtek/Makefile.inc | 20 +++++++ src/drivers/realtek/rtl8168.c | 49 +++++++++++++++++ src/mainboard/getac/p470/Kconfig | 1 + src/mainboard/getac/p470/Makefile.inc | 1 - src/mainboard/getac/p470/rtl8168.c | 77 --------------------------- src/mainboard/intel/d945gclf/Kconfig | 1 + src/mainboard/intel/d945gclf/Makefile.inc | 2 - src/mainboard/intel/d945gclf/rtl8168.c | 49 ----------------- src/mainboard/kontron/986lcd-m/Kconfig | 1 + src/mainboard/kontron/986lcd-m/Makefile.inc | 2 - src/mainboard/kontron/986lcd-m/rtl8168.c | 49 ----------------- src/mainboard/roda/rk886ex/Kconfig | 1 + src/mainboard/roda/rk886ex/Makefile.inc | 1 - src/mainboard/roda/rk886ex/rtl8168.c | 49 ----------------- 17 files changed, 81 insertions(+), 230 deletions(-) diff --git a/src/drivers/Kconfig b/src/drivers/Kconfig index da90a03..56a1592 100644 --- a/src/drivers/Kconfig +++ b/src/drivers/Kconfig @@ -23,6 +23,7 @@ source src/drivers/emulation/Kconfig source src/drivers/generic/Kconfig source src/drivers/i2c/Kconfig source src/drivers/oxford/Kconfig +source src/drivers/realtek/Kconfig source src/drivers/sil/Kconfig source src/drivers/trident/Kconfig source src/drivers/ics/Kconfig diff --git a/src/drivers/Makefile.inc b/src/drivers/Makefile.inc index e10e685..a02b705 100644 --- a/src/drivers/Makefile.inc +++ b/src/drivers/Makefile.inc @@ -23,6 +23,7 @@ subdirs-y += emulation subdirs-y += generic subdirs-y += i2c subdirs-y += oxford +subdirs-y += realtek subdirs-y += sil subdirs-y += trident subdirs-y += ics diff --git a/src/drivers/realtek/Kconfig b/src/drivers/realtek/Kconfig new file mode 100644 index 0000000..0799445 --- /dev/null +++ b/src/drivers/realtek/Kconfig @@ -0,0 +1,6 @@ +config RTL8168_ROM_DISABLE + bool "Disable RTL8168 ROM" + default n + help + Just enough of a driver to make coreboot not look for an Option ROM. + No configuration is necessary for the OS to pick up the device. diff --git a/src/drivers/realtek/Makefile.inc b/src/drivers/realtek/Makefile.inc new file mode 100644 index 0000000..910d4b4 --- /dev/null +++ b/src/drivers/realtek/Makefile.inc @@ -0,0 +1,20 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2012 secunet Security Networks AG +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +driver-$(CONFIG_RTL8168_ROM_DISABLE) += rtl8168.c diff --git a/src/drivers/realtek/rtl8168.c b/src/drivers/realtek/rtl8168.c new file mode 100644 index 0000000..04fd56c --- /dev/null +++ b/src/drivers/realtek/rtl8168.c @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This code should work for all ICH* southbridges with a NIC. */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> + +static void nic_init(struct device *dev) +{ + printk(BIOS_DEBUG, "Initializing RTL8168 Gigabit Ethernet\n"); + // Nothing to do yet, but this has to be here to keep + // coreboot from trying to execute an option ROM. +} + +static struct device_operations nic_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = nic_init, + .scan_bus = 0, +}; + +static const struct pci_driver rtl8169_nic __pci_driver = { + .ops = &nic_ops, + .vendor = 0x10ec, + .device = 0x8168, +}; + + diff --git a/src/mainboard/getac/p470/Kconfig b/src/mainboard/getac/p470/Kconfig index b9ed04e..d1c6f7f 100644 --- a/src/mainboard/getac/p470/Kconfig +++ b/src/mainboard/getac/p470/Kconfig @@ -43,6 +43,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_1024 select GFXUMA select CHANNEL_XOR_RANDOMIZATION + select RTL8168_ROM_DISABLE config MAINBOARD_DIR string diff --git a/src/mainboard/getac/p470/Makefile.inc b/src/mainboard/getac/p470/Makefile.inc index 3b90bf8..f2d0968 100644 --- a/src/mainboard/getac/p470/Makefile.inc +++ b/src/mainboard/getac/p470/Makefile.inc @@ -17,7 +17,6 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -driver-y += rtl8168.c ramstage-$(CONFIG_HAVE_ACPI_SLIC) += acpi_slic.c smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c diff --git a/src/mainboard/getac/p470/rtl8168.c b/src/mainboard/getac/p470/rtl8168.c deleted file mode 100644 index 37ef674..0000000 --- a/src/mainboard/getac/p470/rtl8168.c +++ /dev/null @@ -1,77 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <delay.h> - -// #define RTL8168_DEBUG 1 - -static void nic_init(struct device *dev) -{ - printk(BIOS_DEBUG, "Initializing RTL8168 Gigabit Ethernet\n"); - // Nothing to do yet, but this has to be here to keep - // coreboot from trying to execute an option ROM. - -#ifdef RTL8168_DEBUG - u8 reg8; - - printk(BIOS_DEBUG, "Resetting device... "); - pci_write_config8(dev, 0x37, (1 << 4)); - do { - reg8 = pci_read_config8(dev, 0x37); - reg8 &= (1 << 4); - } while (reg8); - printk(BIOS_DEBUG, "ok\n"); - - printk(BIOS_DEBUG, "Eeprom Auto-Load... "); - reg8 = pci_read_config8(dev, 0x50); - reg8 &= 0x3f; - reg8 |= (1 << 6); - pci_write_config8(dev, 0x50, reg8); - mdelay(3); - printk(BIOS_DEBUG, "ok\n"); -#endif -} - -static struct device_operations nic_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = nic_init, - .scan_bus = 0, -}; - -static const struct pci_driver rtl8168_nic __pci_driver = { - .ops = &nic_ops, - .vendor = 0x10ec, - .device = 0x8168, -}; - -#ifdef RTL8168_DEBUG -static const struct pci_driver rtl8129_nic __pci_driver = { - .ops = &nic_ops, - .vendor = 0x10ec, - .device = 0x8129, -}; -#endif - diff --git a/src/mainboard/intel/d945gclf/Kconfig b/src/mainboard/intel/d945gclf/Kconfig index 32da387..57078da 100644 --- a/src/mainboard/intel/d945gclf/Kconfig +++ b/src/mainboard/intel/d945gclf/Kconfig @@ -41,6 +41,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_512 select GFXUMA select CHANNEL_XOR_RANDOMIZATION + select RTL8168_ROM_DISABLE config MAINBOARD_DIR string diff --git a/src/mainboard/intel/d945gclf/Makefile.inc b/src/mainboard/intel/d945gclf/Makefile.inc index eb01399..e0dd8ed 100644 --- a/src/mainboard/intel/d945gclf/Makefile.inc +++ b/src/mainboard/intel/d945gclf/Makefile.inc @@ -17,6 +17,4 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -driver-y += rtl8168.c - smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c diff --git a/src/mainboard/intel/d945gclf/rtl8168.c b/src/mainboard/intel/d945gclf/rtl8168.c deleted file mode 100644 index 04fd56c..0000000 --- a/src/mainboard/intel/d945gclf/rtl8168.c +++ /dev/null @@ -1,49 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* This code should work for all ICH* southbridges with a NIC. */ - -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> - -static void nic_init(struct device *dev) -{ - printk(BIOS_DEBUG, "Initializing RTL8168 Gigabit Ethernet\n"); - // Nothing to do yet, but this has to be here to keep - // coreboot from trying to execute an option ROM. -} - -static struct device_operations nic_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = nic_init, - .scan_bus = 0, -}; - -static const struct pci_driver rtl8169_nic __pci_driver = { - .ops = &nic_ops, - .vendor = 0x10ec, - .device = 0x8168, -}; - - diff --git a/src/mainboard/kontron/986lcd-m/Kconfig b/src/mainboard/kontron/986lcd-m/Kconfig index 322850e..49cc70e 100644 --- a/src/mainboard/kontron/986lcd-m/Kconfig +++ b/src/mainboard/kontron/986lcd-m/Kconfig @@ -21,6 +21,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select GFXUMA select CHANNEL_XOR_RANDOMIZATION select OVERRIDE_CLOCK_DISABLE + select RTL8168_ROM_DISABLE config MAINBOARD_DIR string diff --git a/src/mainboard/kontron/986lcd-m/Makefile.inc b/src/mainboard/kontron/986lcd-m/Makefile.inc index 8ca1aeb..fb78b3d 100644 --- a/src/mainboard/kontron/986lcd-m/Makefile.inc +++ b/src/mainboard/kontron/986lcd-m/Makefile.inc @@ -17,6 +17,4 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -driver-y += rtl8168.c - smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c diff --git a/src/mainboard/kontron/986lcd-m/rtl8168.c b/src/mainboard/kontron/986lcd-m/rtl8168.c deleted file mode 100644 index 04fd56c..0000000 --- a/src/mainboard/kontron/986lcd-m/rtl8168.c +++ /dev/null @@ -1,49 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* This code should work for all ICH* southbridges with a NIC. */ - -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> - -static void nic_init(struct device *dev) -{ - printk(BIOS_DEBUG, "Initializing RTL8168 Gigabit Ethernet\n"); - // Nothing to do yet, but this has to be here to keep - // coreboot from trying to execute an option ROM. -} - -static struct device_operations nic_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = nic_init, - .scan_bus = 0, -}; - -static const struct pci_driver rtl8169_nic __pci_driver = { - .ops = &nic_ops, - .vendor = 0x10ec, - .device = 0x8168, -}; - - diff --git a/src/mainboard/roda/rk886ex/Kconfig b/src/mainboard/roda/rk886ex/Kconfig index ee1dc59..6539805 100644 --- a/src/mainboard/roda/rk886ex/Kconfig +++ b/src/mainboard/roda/rk886ex/Kconfig @@ -23,6 +23,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_1024 select CHANNEL_XOR_RANDOMIZATION select GFXUMA + select RTL8168_ROM_DISABLE config MAINBOARD_DIR string diff --git a/src/mainboard/roda/rk886ex/Makefile.inc b/src/mainboard/roda/rk886ex/Makefile.inc index 549654a..96458f8 100644 --- a/src/mainboard/roda/rk886ex/Makefile.inc +++ b/src/mainboard/roda/rk886ex/Makefile.inc @@ -18,6 +18,5 @@ ## ramstage-y += m3885.c -driver-y += rtl8168.c smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c diff --git a/src/mainboard/roda/rk886ex/rtl8168.c b/src/mainboard/roda/rk886ex/rtl8168.c deleted file mode 100644 index 04fd56c..0000000 --- a/src/mainboard/roda/rk886ex/rtl8168.c +++ /dev/null @@ -1,49 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* This code should work for all ICH* southbridges with a NIC. */ - -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> - -static void nic_init(struct device *dev) -{ - printk(BIOS_DEBUG, "Initializing RTL8168 Gigabit Ethernet\n"); - // Nothing to do yet, but this has to be here to keep - // coreboot from trying to execute an option ROM. -} - -static struct device_operations nic_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = nic_init, - .scan_bus = 0, -}; - -static const struct pci_driver rtl8169_nic __pci_driver = { - .ops = &nic_ops, - .vendor = 0x10ec, - .device = 0x8168, -}; - -

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New patch to review for coreboot: e9063a8 ibase/mb899: Rename NIC BIOS disable driver and hook up
by Patrick Georgi 26 Jul '12

26 Jul '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1355 -gerrit commit e9063a856dee8d681de67f3ce0ed2904ebcfbcf7 Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Thu Jul 26 11:32:50 2012 +0200 ibase/mb899: Rename NIC BIOS disable driver and hook up The board has a marvell NIC, but the driver to disable NIC BIOS was adapted from a Realtek 8168 driver. Rename to reflect the change. Also hook up as driver, so coreboot can actually find it. Change-Id: Ibdfd6074eb28ba537d68552a3346b06493cef2a6 Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> --- src/mainboard/ibase/mb899/Makefile.inc | 2 +- src/mainboard/ibase/mb899/mv88e8053.c | 49 ++++++++++++++++++++++++++++++++ src/mainboard/ibase/mb899/rtl8168.c | 49 -------------------------------- 3 files changed, 50 insertions(+), 50 deletions(-) diff --git a/src/mainboard/ibase/mb899/Makefile.inc b/src/mainboard/ibase/mb899/Makefile.inc index 0d22927..95c8987 100644 --- a/src/mainboard/ibase/mb899/Makefile.inc +++ b/src/mainboard/ibase/mb899/Makefile.inc @@ -17,6 +17,6 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -ramstage-y += rtl8168.c +driver-y += mv88e8053.c smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c diff --git a/src/mainboard/ibase/mb899/mv88e8053.c b/src/mainboard/ibase/mb899/mv88e8053.c new file mode 100644 index 0000000..101099b --- /dev/null +++ b/src/mainboard/ibase/mb899/mv88e8053.c @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This code should work for all ICH* southbridges with a NIC. */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> + +static void nic_init(struct device *dev) +{ + printk(BIOS_DEBUG, "Initializing 88E8053 Gigabit Ethernet\n"); + // Nothing to do yet, but this has to be here to keep + // coreboot from trying to execute an option ROM. +} + +static struct device_operations nic_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = nic_init, + .scan_bus = 0, +}; + +static const struct pci_driver rtl8169_nic __pci_driver = { + .ops = &nic_ops, + .vendor = 0x11ab, + .device = 0x4362, +}; + + diff --git a/src/mainboard/ibase/mb899/rtl8168.c b/src/mainboard/ibase/mb899/rtl8168.c deleted file mode 100644 index 101099b..0000000 --- a/src/mainboard/ibase/mb899/rtl8168.c +++ /dev/null @@ -1,49 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* This code should work for all ICH* southbridges with a NIC. */ - -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> - -static void nic_init(struct device *dev) -{ - printk(BIOS_DEBUG, "Initializing 88E8053 Gigabit Ethernet\n"); - // Nothing to do yet, but this has to be here to keep - // coreboot from trying to execute an option ROM. -} - -static struct device_operations nic_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = nic_init, - .scan_bus = 0, -}; - -static const struct pci_driver rtl8169_nic __pci_driver = { - .ops = &nic_ops, - .vendor = 0x11ab, - .device = 0x4362, -}; - -

1 0

Patch merged into coreboot/master: 6577cf8 Drop CONFIG_CPU_MODEL_NAME and fix CPU name displayed in logs
by gerrit＠coreboot.org 26 Jul '12

26 Jul '12

the following patch was just integrated into master: commit 6577cf8133240029a256d8bee19e078ffdb5292e Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Jul 10 17:13:04 2012 -0700 Drop CONFIG_CPU_MODEL_NAME and fix CPU name displayed in logs On SandyBridge systems configured to work with Panther Point the CPU would wrongly be described as IvyBridge. Fix this issue and drop an unneeded Kconfig variable at the same time. Change-Id: I501a4fa00613e589cd315cfee61b2f9561dfcb4d Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Thu Jul 26 11:12:53 2012, giving +2 See http://review.coreboot.org/1335 for details. -gerrit

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coreboot July 2012