coreboot July 2012

coreboot@coreboot.org

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New patch to review for coreboot: c774817 libpayload: Fix typo
by Patrick Georgi 27 Jul '12

27 Jul '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1370 -gerrit commit c77481762b54b32abab39e3abf4a197aa1661d29 Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Fri Jul 27 09:51:32 2012 +0200 libpayload: Fix typo Change-Id: I8708703e497053aa1251f06402bd8ea59bd9d24e Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> --- payloads/libpayload/drivers/usb/ohci.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/payloads/libpayload/drivers/usb/ohci.c b/payloads/libpayload/drivers/usb/ohci.c index 606e467..2cfabb4 100644 --- a/payloads/libpayload/drivers/usb/ohci.c +++ b/payloads/libpayload/drivers/usb/ohci.c @@ -54,7 +54,7 @@ ohci_reset (hci_t *controller) OHCI_INST(controller)->opreg->HcCommandStatus = HostControllerReset; mdelay(2); /* wait 2ms */ - OCHI_INST(controller)->opreg->HcControl = 0; + OHCI_INST(controller)->opreg->HcControl = 0; mdelay(10); /* wait 10ms */ } @@ -118,7 +118,7 @@ ohci_init (pcidev_t addr) OHCI_INST (controller)->roothub = controller->devices[0]; controller->bus_address = addr; - /* regarding OHCI spec, Appendix A, BAR_OCHI register description, Table A-4 + /* regarding OHCI spec, Appendix A, BAR_OHCI register description, Table A-4 * BASE ADDRESS only [31-12] bits. All other usually 0, but not all */ controller->reg_base = pci_read_config32 (controller->bus_address, 0x10) & 0xfffff000; // OHCI mandates MMIO, so bit 0 is clear OHCI_INST (controller)->opreg = (opreg_t*)phys_to_virt(controller->reg_base);

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Patch merged into coreboot/master: 133271d x86emu: Use NULL instead of 0 when assigning pointer
by gerrit＠coreboot.org 27 Jul '12

27 Jul '12

the following patch was just integrated into master: commit 133271d603ea015e4ab80d3aa99e57eec9b8b8c2 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Jul 26 15:04:24 2012 -0700 x86emu: Use NULL instead of 0 when assigning pointer Change-Id: Ie79b9aa79d45dd10c2e5be7f58eed970c243060a Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Fri Jul 27 09:16:36 2012, giving +2 See http://review.coreboot.org/1361 for details. -gerrit

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Patch set updated for coreboot: 2863e55 Intel and GFXUMA: fix MTRR and use uma_resource()
by Kyösti Mälkki 27 Jul '12

27 Jul '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1239 -gerrit commit 2863e55ffa17b8f822f1bbd1b6b3a7cb46f3f5a2 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Jul 27 08:42:20 2012 +0300 Intel and GFXUMA: fix MTRR and use uma_resource() Commit 2d42b340034ff005693482ef9ca34ce3e0f08371 changed the variable MTRR setup and removed compensation of uma_memory_size in the cacheable memory resources. Since the cacheable region size was no longer divisible by a large power of 2, like 256 MB, this caused excessive use of MTRRs. As first symptoms, slow boot with grub and poor user response. As a solution, register the actual top of low ram with ram_resource(), and do not subtract the UMA/TSEG regions from it. TSEG may require further work as the original did not appear exactly right to begin with. To have UMA as un-cacheable, use uma_resource(). Change-Id: I4ca99b5c2ca4e474296590b3d0c6ef5d09550d80 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/intel/i82810/northbridge.c | 11 +++++---- src/northbridge/intel/i82830/northbridge.c | 14 +++++----- src/northbridge/intel/i945/northbridge.c | 34 ++++++++++++++------------- src/northbridge/intel/sch/northbridge.c | 26 +++++++++++---------- 4 files changed, 45 insertions(+), 40 deletions(-) diff --git a/src/northbridge/intel/i82810/northbridge.c b/src/northbridge/intel/i82810/northbridge.c index 892fc28..f6d14e0 100644 --- a/src/northbridge/intel/i82810/northbridge.c +++ b/src/northbridge/intel/i82810/northbridge.c @@ -93,7 +93,7 @@ static void pci_domain_set_resources(device_t dev) if (!mc_dev) return; - unsigned long tomk; + unsigned long tomk, tomk_stolen; int idx, drp_value; u8 reg8; @@ -123,21 +123,22 @@ static void pci_domain_set_resources(device_t dev) tomk += (unsigned long)(translate_i82810_to_mb[drp_value]); /* Convert tomk from MB to KB. */ tomk = tomk << 10; - tomk -= igd_memory; + tomk_stolen = tomk - igd_memory; /* For reserving UMA memory in the memory map */ - uma_memory_base = tomk * 1024ULL; + uma_memory_base = tomk_stolen * 1024ULL; uma_memory_size = igd_memory * 1024ULL; - printk(BIOS_DEBUG, "Available memory: %ldKB\n", tomk); + printk(BIOS_DEBUG, "Available memory: %ldKB\n", tomk_stolen); /* Report the memory regions. */ idx = 10; ram_resource(dev, idx++, 0, 640); ram_resource(dev, idx++, 768, tomk - 768); + uma_resource(dev, idx++, uma_memory_base >> 10, uma_memory_size >> 10); #if CONFIG_WRITE_HIGH_TABLES /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; + high_tables_base = (tomk_stolen * 1024) - HIGH_MEMORY_SIZE; high_tables_size = HIGH_MEMORY_SIZE; #endif assign_resources(dev->link_list); diff --git a/src/northbridge/intel/i82830/northbridge.c b/src/northbridge/intel/i82830/northbridge.c index 4ada4d7..649a203 100644 --- a/src/northbridge/intel/i82830/northbridge.c +++ b/src/northbridge/intel/i82830/northbridge.c @@ -73,7 +73,7 @@ static void pci_domain_set_resources(device_t dev) if (!mc_dev) return; - unsigned long tomk; + unsigned long tomk, tomk_stolen; int idx; if (CONFIG_VIDEO_MB == 512) { @@ -89,24 +89,24 @@ static void pci_domain_set_resources(device_t dev) * i.e. 1 means 32MB. */ tomk = ((unsigned long)pci_read_config8(mc_dev, DRB + 3)) << 15; - tomk -= igd_memory; + tomk_stolen = tomk - igd_memory; /* For reserving UMA memory in the memory map */ - uma_memory_base = tomk * 1024ULL; + uma_memory_base = tomk_stolen * 1024ULL; uma_memory_size = igd_memory * 1024ULL; - printk(BIOS_DEBUG, "Available memory: %ldKB\n", tomk); + printk(BIOS_DEBUG, "Available memory: %ldKB\n", tomk_stolen); /* Report the memory regions. */ idx = 10; ram_resource(dev, idx++, 0, 640); - ram_resource(dev, idx++, 768, 256); - ram_resource(dev, idx++, 1024, tomk - 1024); + ram_resource(dev, idx++, 768, tomk - 768); + uma_resource(dev, idx++, uma_memory_base >> 10, uma_memory_size >> 10); assign_resources(dev->link_list); #if CONFIG_WRITE_HIGH_TABLES /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; + high_tables_base = (tomk_stolen * 1024) - HIGH_MEMORY_SIZE; high_tables_size = HIGH_MEMORY_SIZE; #endif } diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 9a69823..9d6d0df 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -73,16 +73,9 @@ static void add_fixed_resources(struct device *dev, int index) struct resource *resource; u32 pcie_config_base, pcie_config_size; - printk(BIOS_DEBUG, "Adding UMA memory area\n"); - resource = new_resource(dev, index); - resource->base = (resource_t) uma_memory_base; - resource->size = (resource_t) uma_memory_size; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; - if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) { printk(BIOS_DEBUG, "Adding PCIe config bar\n"); - resource = new_resource(dev, index+1); + resource = new_resource(dev, index++); resource->base = (resource_t) pcie_config_base; resource->size = (resource_t) pcie_config_size; resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | @@ -99,7 +92,8 @@ static void pci_domain_set_resources(device_t dev) uint32_t pci_tolm; uint8_t tolud, reg8; uint16_t reg16; - unsigned long long tomk; + unsigned long long tomk, tomk_stolen; + uint64_t tseg_memory_base = 0, tseg_memory_size = 0; /* Can we find out how much memory we can use at most * this way? @@ -114,6 +108,7 @@ static void pci_domain_set_resources(device_t dev) printk(BIOS_SPEW, "Top of Low Used DRAM: 0x%08x\n", tolud << 24); tomk = tolud << 14; + tomk_stolen = tomk; /* Note: subtract IGD device and TSEG */ reg8 = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), 0x9e); @@ -135,7 +130,11 @@ static void pci_domain_set_resources(device_t dev) } printk(BIOS_DEBUG, "%dM\n", tseg_size >> 10); - tomk -= tseg_size; + tomk_stolen -= tseg_size; + + /* For reserving TSEG memory in the memory map */ + tseg_memory_base = tomk_stolen * 1024ULL; + tseg_memory_size = tseg_size * 1024ULL; } reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), GGC); @@ -154,29 +153,32 @@ static void pci_domain_set_resources(device_t dev) } printk(BIOS_DEBUG, "%dM UMA\n", uma_size >> 10); - tomk -= uma_size; + tomk_stolen -= uma_size; /* For reserving UMA memory in the memory map */ - uma_memory_base = tomk * 1024ULL; + uma_memory_base = tomk_stolen * 1024ULL; uma_memory_size = uma_size * 1024ULL; } /* The following needs to be 2 lines, otherwise the second * number is always 0 */ - printk(BIOS_INFO, "Available memory: %dK", (uint32_t)tomk); - printk(BIOS_INFO, " (%dM)\n", (uint32_t)(tomk >> 10)); + printk(BIOS_INFO, "Available memory: %dK", (uint32_t)tomk_stolen); + printk(BIOS_INFO, " (%dM)\n", (uint32_t)(tomk_stolen >> 10)); /* Report the memory regions */ ram_resource(dev, 3, 0, 640); ram_resource(dev, 4, 768, (tomk - 768)); - add_fixed_resources(dev, 6); + uma_resource(dev, 5, uma_memory_base >> 10, uma_memory_size >> 10); + mmio_resource(dev, 6, tseg_memory_base >> 10, tseg_memory_size >> 10); + + add_fixed_resources(dev, 7); assign_resources(dev->link_list); #if CONFIG_WRITE_HIGH_TABLES /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; + high_tables_base = (tomk_stolen * 1024) - HIGH_MEMORY_SIZE; high_tables_size = HIGH_MEMORY_SIZE; #endif } diff --git a/src/northbridge/intel/sch/northbridge.c b/src/northbridge/intel/sch/northbridge.c index 52b688a..419a82c 100644 --- a/src/northbridge/intel/sch/northbridge.c +++ b/src/northbridge/intel/sch/northbridge.c @@ -78,13 +78,6 @@ static void add_fixed_resources(struct device *dev, int index) struct resource *resource; u32 pcie_config_base, pcie_config_size; - printk(BIOS_DEBUG, "Adding UMA memory area\n"); - resource = new_resource(dev, index++); - resource->base = (resource_t) uma_memory_base; - resource->size = (resource_t) uma_memory_size; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; - if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) { printk(BIOS_DEBUG, "Adding PCIe config bar\n"); resource = new_resource(dev, index++); @@ -111,7 +104,8 @@ static void pci_domain_set_resources(device_t dev) u32 pci_tolm; u8 reg8; u16 reg16; - unsigned long long tomk, tolud; + unsigned long long tomk, tolud, tomk_stolen; + uint64_t tseg_memory_base = 0, tseg_memory_size = 0; /* Can we find out how much memory we can use at most this way? */ pci_tolm = find_pci_tolm(dev->link_list); @@ -123,6 +117,7 @@ static void pci_domain_set_resources(device_t dev) printk(BIOS_SPEW, "Top of Low Used DRAM: 0x%08llx\n", tolud << 24); tomk = tolud << 14; + tomk_stolen = tomk; /* Note: subtract IGD device and TSEG. */ reg8 = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), 0x9e); @@ -144,7 +139,11 @@ static void pci_domain_set_resources(device_t dev) } printk(BIOS_DEBUG, "%dM\n", tseg_size >> 10); - tomk -= tseg_size; + tomk_stolen -= tseg_size; + + /* For reserving TSEG memory in the memory map */ + tseg_memory_base = tomk_stolen * 1024ULL; + tseg_memory_size = tseg_size * 1024ULL; } reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), GGC); @@ -165,10 +164,10 @@ static void pci_domain_set_resources(device_t dev) break; } printk(BIOS_DEBUG, "%dM UMA\n", uma_size >> 10); - tomk -= uma_size; + tomk_stolen -= uma_size; /* For reserving UMA memory in the memory map. */ - uma_memory_base = tomk * 1024ULL; + uma_memory_base = tomk_stolen * 1024ULL; uma_memory_size = uma_size * 1024ULL; } @@ -182,7 +181,10 @@ static void pci_domain_set_resources(device_t dev) /* Report the memory regions. */ ram_resource(dev, 3, 0, 640); ram_resource(dev, 4, 768, (tomk - 768)); - add_fixed_resources(dev, 6); + uma_resource(dev, 5, uma_memory_base >> 10, uma_memory_size >> 10); + mmio_resource(dev, 6, tseg_memory_base >> 10, tseg_memory_size >> 10); + + add_fixed_resources(dev, 7); assign_resources(dev->link_list);

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New patch to review for coreboot: bebe95d Intel 82810 and 82830: always room for PCI memory
by Kyösti Mälkki 27 Jul '12

27 Jul '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1369 -gerrit commit bebe95db1a971eae1658f70c9be13d59a7ea0650 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Jul 27 08:40:46 2012 +0300 Intel 82810 and 82830: always room for PCI memory No need for the test, tomk is at most 1GB on these chipsets. Even if there was no room, adjusting the memory resource would not not divert accesses in the hardware from DRAM to PCI. Change-Id: I2213b8d9d2e6ab8da8fd3e8081cc62bb05b6b316 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/intel/i82810/northbridge.c | 13 ++----------- src/northbridge/intel/i82830/northbridge.c | 13 ++----------- 2 files changed, 4 insertions(+), 22 deletions(-) diff --git a/src/northbridge/intel/i82810/northbridge.c b/src/northbridge/intel/i82810/northbridge.c index 3337417..892fc28 100644 --- a/src/northbridge/intel/i82810/northbridge.c +++ b/src/northbridge/intel/i82810/northbridge.c @@ -87,15 +87,13 @@ static int translate_i82810_to_mb[] = { static void pci_domain_set_resources(device_t dev) { device_t mc_dev; - uint32_t pci_tolm; int igd_memory = 0; - pci_tolm = find_pci_tolm(dev->link_list); mc_dev = dev->link_list->children; if (!mc_dev) return; - unsigned long tomk, tolmk; + unsigned long tomk; int idx, drp_value; u8 reg8; @@ -132,17 +130,10 @@ static void pci_domain_set_resources(device_t dev) uma_memory_size = igd_memory * 1024ULL; printk(BIOS_DEBUG, "Available memory: %ldKB\n", tomk); - /* Compute the top of low memory. */ - tolmk = pci_tolm >> 10; - if (tolmk >= tomk) { - /* The PCI hole does does not overlap the memory. */ - tolmk = tomk; - } - /* Report the memory regions. */ idx = 10; ram_resource(dev, idx++, 0, 640); - ram_resource(dev, idx++, 768, tolmk - 768); + ram_resource(dev, idx++, 768, tomk - 768); #if CONFIG_WRITE_HIGH_TABLES /* Leave some space for ACPI, PIRQ and MP tables */ diff --git a/src/northbridge/intel/i82830/northbridge.c b/src/northbridge/intel/i82830/northbridge.c index 22f59dc..4ada4d7 100644 --- a/src/northbridge/intel/i82830/northbridge.c +++ b/src/northbridge/intel/i82830/northbridge.c @@ -67,15 +67,13 @@ int add_northbridge_resources(struct lb_memory *mem) static void pci_domain_set_resources(device_t dev) { device_t mc_dev; - uint32_t pci_tolm; int igd_memory = 0; - pci_tolm = find_pci_tolm(dev->link_list); mc_dev = dev->link_list->children; if (!mc_dev) return; - unsigned long tomk, tolmk; + unsigned long tomk; int idx; if (CONFIG_VIDEO_MB == 512) { @@ -98,18 +96,11 @@ static void pci_domain_set_resources(device_t dev) uma_memory_size = igd_memory * 1024ULL; printk(BIOS_DEBUG, "Available memory: %ldKB\n", tomk); - /* Compute the top of low memory. */ - tolmk = pci_tolm >> 10; - if (tolmk >= tomk) { - /* The PCI hole does does not overlap the memory. */ - tolmk = tomk; - } - /* Report the memory regions. */ idx = 10; ram_resource(dev, idx++, 0, 640); ram_resource(dev, idx++, 768, 256); - ram_resource(dev, idx++, 1024, tolmk - 1024); + ram_resource(dev, idx++, 1024, tomk - 1024); assign_resources(dev->link_list);

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New patch to review for coreboot: 46df204 Intel i945 and sch: no memory over 4GB
by Kyösti Mälkki 27 Jul '12

27 Jul '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1368 -gerrit commit 46df20489fa44e61007e4b719b186ab4e4c9e675 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Jul 27 08:40:14 2012 +0300 Intel i945 and sch: no memory over 4GB No need for the test, tomk is top of low memory and always below 4GB. Change-Id: Ifc8f29268b761aa9b07b578673236a673f0c70b5 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/intel/i945/northbridge.c | 4 ---- src/northbridge/intel/sch/northbridge.c | 3 --- 2 files changed, 0 insertions(+), 7 deletions(-) diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 58e70d7..9a69823 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -170,10 +170,6 @@ static void pci_domain_set_resources(device_t dev) /* Report the memory regions */ ram_resource(dev, 3, 0, 640); ram_resource(dev, 4, 768, (tomk - 768)); - if (tomk > 4 * 1024 * 1024) { - ram_resource(dev, 5, 4096 * 1024, tomk - 4 * 1024 * 1024); - } - add_fixed_resources(dev, 6); assign_resources(dev->link_list); diff --git a/src/northbridge/intel/sch/northbridge.c b/src/northbridge/intel/sch/northbridge.c index 581f97c..52b688a 100644 --- a/src/northbridge/intel/sch/northbridge.c +++ b/src/northbridge/intel/sch/northbridge.c @@ -182,9 +182,6 @@ static void pci_domain_set_resources(device_t dev) /* Report the memory regions. */ ram_resource(dev, 3, 0, 640); ram_resource(dev, 4, 768, (tomk - 768)); - if (tomk > 4 * 1024 * 1024) - ram_resource(dev, 5, 4096 * 1024, tomk - 4 * 1024 * 1024); - add_fixed_resources(dev, 6); assign_resources(dev->link_list);

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New patch to review for coreboot: 94e8058 Allocators for different memory regions types
by Kyösti Mälkki 27 Jul '12

27 Jul '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1367 -gerrit commit 94e805875a650d57b88e1536d3c175cfecf8b1ff Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Jul 27 08:37:12 2012 +0300 Allocators for different memory regions types Hide some details of the resource allocator from rest of the world. These should come in handy when fixing some aspects of MTRR setup. Change-Id: I8acad98f25e56cd8bae64fb52539d81ce94f9c73 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/devices/device_util.c | 23 +++++------------------ src/include/device/device.h | 19 +++++++++++++++---- 2 files changed, 20 insertions(+), 22 deletions(-) diff --git a/src/devices/device_util.c b/src/devices/device_util.c index 9362525..6f088b2 100644 --- a/src/devices/device_util.c +++ b/src/devices/device_util.c @@ -795,8 +795,8 @@ void show_all_devs_resources(int debug_level, const char* msg) } } -void ram_resource(device_t dev, unsigned long index, - unsigned long basek, unsigned long sizek) +void fixed_mem_resource(device_t dev, unsigned long index, + unsigned long basek, unsigned long sizek, unsigned long type) { struct resource *resource; @@ -806,23 +806,10 @@ void ram_resource(device_t dev, unsigned long index, resource = new_resource(dev, index); resource->base = ((resource_t)basek) << 10; resource->size = ((resource_t)sizek) << 10; - resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \ - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; -} - -void uma_resource(device_t dev, unsigned long index, - unsigned long basek, unsigned long sizek) -{ - struct resource *resource; - - if (!sizek) - return; + resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | + IORESOURCE_STORED | IORESOURCE_ASSIGNED; - resource = new_resource(dev, index); - resource->base = ((resource_t)basek) << 10; - resource->size = ((resource_t)sizek) << 10; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | IORESOURCE_UMA_FB | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + resource->flags |= type; } void tolm_test(void *gp, struct device *dev, struct resource *new) diff --git a/src/include/device/device.h b/src/include/device/device.h index 8cc937f..1515b45 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -170,10 +170,21 @@ void pci_domain_read_resources(struct device *dev); unsigned int pci_domain_scan_bus(struct device *dev, unsigned int max); unsigned int scan_static_bus(device_t bus, unsigned int max); -void ram_resource(device_t dev, unsigned long index, - unsigned long basek, unsigned long sizek); -void uma_resource(device_t dev, unsigned long index, - unsigned long basek, unsigned long sizek); +void fixed_mem_resource(device_t dev, unsigned long index, + unsigned long basek, unsigned long sizek, unsigned long type); + +#define ram_resource(dev, idx, basek, sizek) \ + fixed_mem_resource(dev, idx, basek, sizek, IORESOURCE_CACHEABLE) + +#define bad_ram_resource(dev, idx, basek, sizek) \ + fixed_mem_resource(dev, idx, basek, sizek, IORESOURCE_RESERVE | IORESOURCE_CACHEABLE ) + +#define uma_resource(dev, idx, basek, sizek) \ + fixed_mem_resource(dev, idx, basek, sizek, IORESOURCE_RESERVE | IORESOURCE_UMA_FB) + +#define mmio_resource(dev, idx, basek, sizek) \ + fixed_mem_resource(dev, idx, basek, sizek, IORESOURCE_RESERVE) + void tolm_test(void *gp, struct device *dev, struct resource *new); u32 find_pci_tolm(struct bus *bus);

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Patch merged into coreboot/master: caea002 Re-run the git-describe if it fails at first try.
by gerrit＠coreboot.org 27 Jul '12

27 Jul '12

the following patch was just integrated into master: commit caea00287693097c2b3724485892526357e64d13 Author: zbao <fishbaozi(a)gmail.com> Date: Mon Jul 23 12:11:59 2012 +0800 Re-run the git-describe if it fails at first try. Old rev (1.6.6, in my case) git-describe doesn't take the --dirty and says error. Remove the --dirty at second try. Change-Id: Id6c6f9889ab20fb7c2b238f8c0bbe20134757369 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Fri Jul 27 07:58:37 2012, giving +2 See http://review.coreboot.org/1261 for details. -gerrit

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QEMU version step-by-step
by David Griffith 27 Jul '12

27 Jul '12

Would someone post step-by-step instructions for building coreboot for QEMU and then starting QEMU? I keep getting problems like this: Multiboot Information structure has been written. 0. FREE SPACE 07fe9c00 00016400 1. GDT 07fe0200 00000200 2. IRQ TABLE 07fe0400 00001000 3. SMBIOS 07fe1400 00000800 4. COREBOOT 07fe1c00 00008000 CBFS: Looking for 'fallback/payload' CBFS: found. Got a payload CPU0: stack from 00118000 to 00120000:Lowest stack address 0011fba8 Loading segment from rom address 0xfffc97f8 code (compression=1) New segment dstaddr 0xe5fac memsize 0x1a054 srcaddr 0xfffc9830 filesize 0xd0e2 (cleaned up) New segment addr 0xe5fac size 0x1a054 offset 0xfffc9830 filesize 0xd0e2 Loading segment from rom address 0xfffc9814 Entry Point 0x00000000 Loading Segment: addr: 0x00000000000e5fac memsz: 0x000000000001a054 filesz: 0x000000000000d0e2 lb: [0x0000000000100000, 0x0000000000124000) Post relocation: addr: 0x00000000000e5fac memsz: 0x000000000001a054 filesz: 0x000000000000d0e2 using LZMA lzma: Decoding error = 1 Boot failed -- David Griffith dave(a)661.org

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New patch to review for coreboot: 18080c5 x86emu: Fix more mis-decoding of the data prefix
by Stefan Reinauer 27 Jul '12

27 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1366 -gerrit commit 18080c5dfbaacbf573efa49d24d8d2133f6855f6 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Jul 26 16:25:53 2012 -0700 x86emu: Fix more mis-decoding of the data prefix cc2c73ddcb4370a7c3ad439cda4da825156c26c9's three-cent titanium tax doesn't go too far enough. Fix the rest of the call and jmp instructions to handle the data prefix correctly. Reference: Intel 64 and IA-32 Architectures Software Developer's Manual Volume 2A: Instruction Set Reference, A-M http://www.intel.com/Assets/PDF/manual/253666.pdf Imported from: http://cgit.freedesktop.org/xorg/xserver/commit/hw/xfree86/x86emu?id=bb18f2… Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Change-Id: I83e6245d9748ee86722cfb7d8ac65258c35c013c Reviewed-by: Julien Cristau <jcristau(a)debian.org> Signed-off-by: Adam Jackson <ajax(a)redhat.com> --- src/devices/oprom/x86emu/ops.c | 67 ++++++++++++++++++++++++++++------------ 1 files changed, 47 insertions(+), 20 deletions(-) diff --git a/src/devices/oprom/x86emu/ops.c b/src/devices/oprom/x86emu/ops.c index e58dafb..6917a08 100644 --- a/src/devices/oprom/x86emu/ops.c +++ b/src/devices/oprom/x86emu/ops.c @@ -2294,15 +2294,20 @@ Handles opcode 0x9a ****************************************************************************/ static void x86emuOp_call_far_IMM(u8 X86EMU_UNUSED(op1)) { - u16 farseg, faroff; + u32 farseg, faroff; START_OF_INSTR(); - DECODE_PRINTF("CALL\t"); - faroff = fetch_word_imm(); - farseg = fetch_word_imm(); - DECODE_PRINTF2("%04x:", farseg); - DECODE_PRINTF2("%04x\n", faroff); - CALL_TRACE(M.x86.saved_cs, M.x86.saved_ip, farseg, faroff, "FAR "); + DECODE_PRINTF("CALL\t"); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + faroff = fetch_long_imm(); + farseg = fetch_word_imm(); + } else { + faroff = fetch_word_imm(); + farseg = fetch_word_imm(); + } + DECODE_PRINTF2("%04x:", farseg); + DECODE_PRINTF2("%04x\n", faroff); + CALL_TRACE(M.x86.saved_cs, M.x86.saved_ip, farseg, faroff, "FAR "); /* XXX * @@ -2313,8 +2318,12 @@ static void x86emuOp_call_far_IMM(u8 X86EMU_UNUSED(op1)) TRACE_AND_STEP(); push_word(M.x86.R_CS); M.x86.R_CS = farseg; - push_word(M.x86.R_IP); - M.x86.R_IP = faroff; + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + push_long(M.x86.R_EIP); + } else { + push_word(M.x86.R_IP); + } + M.x86.R_EIP = faroff & 0xffff; DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } @@ -4258,17 +4267,30 @@ Handles opcode 0xe8 ****************************************************************************/ static void x86emuOp_call_near_IMM(u8 X86EMU_UNUSED(op1)) { - s16 ip; + s16 ip16 = 0; /* Initialize to keep GCC silent */ + s32 ip32 = 0; START_OF_INSTR(); - DECODE_PRINTF("CALL\t"); - ip = (s16) fetch_word_imm(); - ip += (s16) M.x86.R_IP; /* CHECK SIGN */ - DECODE_PRINTF2("%04x\n", ip); - CALL_TRACE(M.x86.saved_cs, M.x86.saved_ip, M.x86.R_CS, ip, ""); + DECODE_PRINTF("CALL\t"); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + ip32 = (s32) fetch_long_imm(); + ip32 += (s16) M.x86.R_IP; /* CHECK SIGN */ + DECODE_PRINTF2("%04x\n", (u16)ip32); + CALL_TRACE(M.x86.saved_cs, M.x86.saved_ip, M.x86.R_CS, ip32, ""); + } else { + ip16 = (s16) fetch_word_imm(); + ip16 += (s16) M.x86.R_IP; /* CHECK SIGN */ + DECODE_PRINTF2("%04x\n", ip16); + CALL_TRACE(M.x86.saved_cs, M.x86.saved_ip, M.x86.R_CS, ip16, ""); + } TRACE_AND_STEP(); - push_word(M.x86.R_IP); - M.x86.R_IP = ip; + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + push_long(M.x86.R_EIP); + M.x86.R_EIP = ip32 & 0xffff; + } else { + push_word(M.x86.R_IP); + M.x86.R_EIP = ip16; + } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } @@ -4308,17 +4330,22 @@ Handles opcode 0xea ****************************************************************************/ static void x86emuOp_jump_far_IMM(u8 X86EMU_UNUSED(op1)) { - u16 cs, ip; + u16 cs; + u32 ip; START_OF_INSTR(); DECODE_PRINTF("JMP\tFAR "); - ip = fetch_word_imm(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + ip = fetch_long_imm(); + } else { + ip = fetch_word_imm(); + } cs = fetch_word_imm(); DECODE_PRINTF2("%04x:", cs); DECODE_PRINTF2("%04x\n", ip); JMP_TRACE(M.x86.saved_cs, M.x86.saved_ip, cs, ip, " FAR "); TRACE_AND_STEP(); - M.x86.R_IP = ip; + M.x86.R_EIP = ip & 0xffff; M.x86.R_CS = cs; DECODE_CLEAR_SEGOVR(); END_OF_INSTR();

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New patch to review for coreboot: aba752b x86emu: fix jump_near_IMM to handle DATA: flag correctly
by Stefan Reinauer 27 Jul '12

27 Jul '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1365 -gerrit commit aba752bc719378b667954175d05891c5b69e2c55 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Jul 26 15:48:17 2012 -0700 x86emu: fix jump_near_IMM to handle DATA: flag correctly Before (data flag ignored -> broken): 66 DATA: e944f1 JMP 1ff6 After (fixed): 66 DATA: e944f1ffff JMP 00001ff8 This subtle difference in the length of decoded instruction meant that the VBE call jumped to the routine setting AX=0x14F (VBE Failed) instead of the routine that set AX=0x4F (VBE success). The ability to run the same code in vm86 significantly aided the debugging of this issue. Those X.org developers who would like to drop vm86 better take special care towards _all_ vesa bugs, as those will expose further issues. Imported from: http://cgit.freedesktop.org/xorg/xserver/commit/hw/xfree86/x86emu?id=cc2c73… Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Change-Id: Id08ead9b17468cf19ede45508e5dcc50e45b5acf Signed-off-by: Luc Verhaegen <libv(a)skynet.be> Tested-by: Luc Verhaegen <libv(a)skynet.be> Reviewed-by: Adam Jackson <ajax(a)redhat.com> Signed-off-by: Keith Packard <keithp(a)keithp.com> --- src/devices/oprom/x86emu/ops.c | 23 ++++++++++++++++------- 1 files changed, 16 insertions(+), 7 deletions(-) diff --git a/src/devices/oprom/x86emu/ops.c b/src/devices/oprom/x86emu/ops.c index 6bfc71c..e58dafb 100644 --- a/src/devices/oprom/x86emu/ops.c +++ b/src/devices/oprom/x86emu/ops.c @@ -4279,16 +4279,25 @@ Handles opcode 0xe9 ****************************************************************************/ static void x86emuOp_jump_near_IMM(u8 X86EMU_UNUSED(op1)) { - int ip; + u32 ip; START_OF_INSTR(); DECODE_PRINTF("JMP\t"); - ip = (s16)fetch_word_imm(); - ip += (s16)M.x86.R_IP; - DECODE_PRINTF2("%04x\n", ip); - JMP_TRACE(M.x86.saved_cs, M.x86.saved_ip, M.x86.R_CS, ip, " NEAR "); - TRACE_AND_STEP(); - M.x86.R_IP = (u16)ip; + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + ip = (u32)fetch_long_imm(); + ip += (u32)M.x86.R_EIP; + DECODE_PRINTF2("%08x\n", (u32)ip); + JMP_TRACE(M.x86.saved_cs, M.x86.saved_ip, M.x86.R_CS, ip, " NEAR "); + TRACE_AND_STEP(); + M.x86.R_EIP = (u32)ip; + } else { + ip = (s16)fetch_word_imm(); + ip += (s16)M.x86.R_IP; + DECODE_PRINTF2("%04x\n", (u16)ip); + JMP_TRACE(M.x86.saved_cs, M.x86.saved_ip, M.x86.R_CS, ip, " NEAR "); + TRACE_AND_STEP(); + M.x86.R_IP = (u16)ip; + } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); }

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coreboot July 2012