coreboot July 2012

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Patch set updated for coreboot: 0af8543 x86emu: Fix more mis-decoding of the data prefix
by Ronald G. Minnich 27 Jul '12

27 Jul '12

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1366 -gerrit commit 0af854397bdeb4412803ac46a2edefcfec1e17a5 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Jul 26 16:25:53 2012 -0700 x86emu: Fix more mis-decoding of the data prefix cc2c73ddcb4370a7c3ad439cda4da825156c26c9's three-cent titanium tax doesn't go too far enough. Fix the rest of the call and jmp instructions to handle the data prefix correctly. Reference: Intel 64 and IA-32 Architectures Software Developer's Manual Volume 2A: Instruction Set Reference, A-M http://www.intel.com/Assets/PDF/manual/253666.pdf Imported from: http://cgit.freedesktop.org/xorg/xserver/commit/hw/xfree86/x86emu?id=bb18f2… Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Change-Id: I83e6245d9748ee86722cfb7d8ac65258c35c013c Reviewed-by: Julien Cristau <jcristau(a)debian.org> Signed-off-by: Adam Jackson <ajax(a)redhat.com> --- src/devices/oprom/x86emu/ops.c | 67 ++++++++++++++++++++++++++++------------ 1 files changed, 47 insertions(+), 20 deletions(-) diff --git a/src/devices/oprom/x86emu/ops.c b/src/devices/oprom/x86emu/ops.c index e58dafb..6917a08 100644 --- a/src/devices/oprom/x86emu/ops.c +++ b/src/devices/oprom/x86emu/ops.c @@ -2294,15 +2294,20 @@ Handles opcode 0x9a ****************************************************************************/ static void x86emuOp_call_far_IMM(u8 X86EMU_UNUSED(op1)) { - u16 farseg, faroff; + u32 farseg, faroff; START_OF_INSTR(); - DECODE_PRINTF("CALL\t"); - faroff = fetch_word_imm(); - farseg = fetch_word_imm(); - DECODE_PRINTF2("%04x:", farseg); - DECODE_PRINTF2("%04x\n", faroff); - CALL_TRACE(M.x86.saved_cs, M.x86.saved_ip, farseg, faroff, "FAR "); + DECODE_PRINTF("CALL\t"); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + faroff = fetch_long_imm(); + farseg = fetch_word_imm(); + } else { + faroff = fetch_word_imm(); + farseg = fetch_word_imm(); + } + DECODE_PRINTF2("%04x:", farseg); + DECODE_PRINTF2("%04x\n", faroff); + CALL_TRACE(M.x86.saved_cs, M.x86.saved_ip, farseg, faroff, "FAR "); /* XXX * @@ -2313,8 +2318,12 @@ static void x86emuOp_call_far_IMM(u8 X86EMU_UNUSED(op1)) TRACE_AND_STEP(); push_word(M.x86.R_CS); M.x86.R_CS = farseg; - push_word(M.x86.R_IP); - M.x86.R_IP = faroff; + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + push_long(M.x86.R_EIP); + } else { + push_word(M.x86.R_IP); + } + M.x86.R_EIP = faroff & 0xffff; DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } @@ -4258,17 +4267,30 @@ Handles opcode 0xe8 ****************************************************************************/ static void x86emuOp_call_near_IMM(u8 X86EMU_UNUSED(op1)) { - s16 ip; + s16 ip16 = 0; /* Initialize to keep GCC silent */ + s32 ip32 = 0; START_OF_INSTR(); - DECODE_PRINTF("CALL\t"); - ip = (s16) fetch_word_imm(); - ip += (s16) M.x86.R_IP; /* CHECK SIGN */ - DECODE_PRINTF2("%04x\n", ip); - CALL_TRACE(M.x86.saved_cs, M.x86.saved_ip, M.x86.R_CS, ip, ""); + DECODE_PRINTF("CALL\t"); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + ip32 = (s32) fetch_long_imm(); + ip32 += (s16) M.x86.R_IP; /* CHECK SIGN */ + DECODE_PRINTF2("%04x\n", (u16)ip32); + CALL_TRACE(M.x86.saved_cs, M.x86.saved_ip, M.x86.R_CS, ip32, ""); + } else { + ip16 = (s16) fetch_word_imm(); + ip16 += (s16) M.x86.R_IP; /* CHECK SIGN */ + DECODE_PRINTF2("%04x\n", ip16); + CALL_TRACE(M.x86.saved_cs, M.x86.saved_ip, M.x86.R_CS, ip16, ""); + } TRACE_AND_STEP(); - push_word(M.x86.R_IP); - M.x86.R_IP = ip; + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + push_long(M.x86.R_EIP); + M.x86.R_EIP = ip32 & 0xffff; + } else { + push_word(M.x86.R_IP); + M.x86.R_EIP = ip16; + } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } @@ -4308,17 +4330,22 @@ Handles opcode 0xea ****************************************************************************/ static void x86emuOp_jump_far_IMM(u8 X86EMU_UNUSED(op1)) { - u16 cs, ip; + u16 cs; + u32 ip; START_OF_INSTR(); DECODE_PRINTF("JMP\tFAR "); - ip = fetch_word_imm(); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + ip = fetch_long_imm(); + } else { + ip = fetch_word_imm(); + } cs = fetch_word_imm(); DECODE_PRINTF2("%04x:", cs); DECODE_PRINTF2("%04x\n", ip); JMP_TRACE(M.x86.saved_cs, M.x86.saved_ip, cs, ip, " FAR "); TRACE_AND_STEP(); - M.x86.R_IP = ip; + M.x86.R_EIP = ip & 0xffff; M.x86.R_CS = cs; DECODE_CLEAR_SEGOVR(); END_OF_INSTR();

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Patch set updated for coreboot: a408915 x86emu: fix jump_near_IMM to handle DATA: flag correctly
by Ronald G. Minnich 27 Jul '12

27 Jul '12

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1365 -gerrit commit a408915a1c9d323a0735778ab72a0842b82c9df5 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Jul 26 15:48:17 2012 -0700 x86emu: fix jump_near_IMM to handle DATA: flag correctly Before (data flag ignored -> broken): 66 DATA: e944f1 JMP 1ff6 After (fixed): 66 DATA: e944f1ffff JMP 00001ff8 This subtle difference in the length of decoded instruction meant that the VBE call jumped to the routine setting AX=0x14F (VBE Failed) instead of the routine that set AX=0x4F (VBE success). The ability to run the same code in vm86 significantly aided the debugging of this issue. Those X.org developers who would like to drop vm86 better take special care towards _all_ vesa bugs, as those will expose further issues. Imported from: http://cgit.freedesktop.org/xorg/xserver/commit/hw/xfree86/x86emu?id=cc2c73… Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Change-Id: Id08ead9b17468cf19ede45508e5dcc50e45b5acf Signed-off-by: Luc Verhaegen <libv(a)skynet.be> Tested-by: Luc Verhaegen <libv(a)skynet.be> Reviewed-by: Adam Jackson <ajax(a)redhat.com> Signed-off-by: Keith Packard <keithp(a)keithp.com> --- src/devices/oprom/x86emu/ops.c | 23 ++++++++++++++++------- 1 files changed, 16 insertions(+), 7 deletions(-) diff --git a/src/devices/oprom/x86emu/ops.c b/src/devices/oprom/x86emu/ops.c index 6bfc71c..e58dafb 100644 --- a/src/devices/oprom/x86emu/ops.c +++ b/src/devices/oprom/x86emu/ops.c @@ -4279,16 +4279,25 @@ Handles opcode 0xe9 ****************************************************************************/ static void x86emuOp_jump_near_IMM(u8 X86EMU_UNUSED(op1)) { - int ip; + u32 ip; START_OF_INSTR(); DECODE_PRINTF("JMP\t"); - ip = (s16)fetch_word_imm(); - ip += (s16)M.x86.R_IP; - DECODE_PRINTF2("%04x\n", ip); - JMP_TRACE(M.x86.saved_cs, M.x86.saved_ip, M.x86.R_CS, ip, " NEAR "); - TRACE_AND_STEP(); - M.x86.R_IP = (u16)ip; + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + ip = (u32)fetch_long_imm(); + ip += (u32)M.x86.R_EIP; + DECODE_PRINTF2("%08x\n", (u32)ip); + JMP_TRACE(M.x86.saved_cs, M.x86.saved_ip, M.x86.R_CS, ip, " NEAR "); + TRACE_AND_STEP(); + M.x86.R_EIP = (u32)ip; + } else { + ip = (s16)fetch_word_imm(); + ip += (s16)M.x86.R_IP; + DECODE_PRINTF2("%04x\n", (u16)ip); + JMP_TRACE(M.x86.saved_cs, M.x86.saved_ip, M.x86.R_CS, ip, " NEAR "); + TRACE_AND_STEP(); + M.x86.R_IP = (u16)ip; + } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); }

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Patch set updated for coreboot: ade868c x86emu: Respect the LEA 67h address size prefix
by Ronald G. Minnich 27 Jul '12

27 Jul '12

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1364 -gerrit commit ade868c0ad60486a911b98037e59bc5726bdc0df Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Jul 26 15:40:06 2012 -0700 x86emu: Respect the LEA 67h address size prefix From http://cgit.freedesktop.org/xorg/xserver/commit/hw/xfree86/x86emu?id=f57bc0… Change-Id: Ibdcaa27e936464cec512edb46447aa6284a34975 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Signed-off-by: Christian Zander <chzander(a)nvidia.com> Signed-off-by: Aaron Plattner <aplattner(a)nvidia.com> Tested-by: Tiago Vignatti <tiago.vignatti(a)nokia.com> Signed-off-by: Keith Packard <keithp(a)keithp.com> --- src/devices/oprom/x86emu/ops.c | 30 ++++++++++++++++-------------- 1 files changed, 16 insertions(+), 14 deletions(-) diff --git a/src/devices/oprom/x86emu/ops.c b/src/devices/oprom/x86emu/ops.c index 70e048d..6bfc71c 100644 --- a/src/devices/oprom/x86emu/ops.c +++ b/src/devices/oprom/x86emu/ops.c @@ -2058,27 +2058,29 @@ Handles opcode 0x8d static void x86emuOp_lea_word_R_M(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; - u16 *srcreg; uint destoffset; -/* - * TODO: Need to handle address size prefix! - * - * lea eax,[eax+ebx*2] ?? - */ - START_OF_INSTR(); DECODE_PRINTF("LEA\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - destoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *srcreg = (u16)destoffset; + if (M.x86.mode & SYSMODE_PREFIX_ADDR) { + u32 *srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *srcreg = (u32)destoffset; + } else { + u16 *srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *srcreg = (u16)destoffset; } - /* } else { undefined. Do nothing. } */ + } + /* else { undefined. Do nothing. } */ DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); }

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Patch merged into coreboot/master: 62b6afc x86emu: Fix BSF and BSR instructions
by gerrit＠coreboot.org 27 Jul '12

27 Jul '12

the following patch was just integrated into master: commit 62b6afc5c3f8bb9bf077042b4a5fa60aaff73467 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Jul 26 15:02:49 2012 -0700 x86emu: Fix BSF and BSR instructions Patch courtesy of Michael Yaroslavtsev. Synced from Xorg http://cgit.freedesktop.org/xorg/xserver/commit/?id=66fa87292ef26bd0f464481… Change-Id: I266f910d4a535eab4e2ad77f2540f2f1495bed61 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Build-Tested: build bot (Jenkins) at Fri Jul 27 02:20:35 2012, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Fri Jul 27 17:48:07 2012, giving +2 See http://review.coreboot.org/1360 for details. -gerrit

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Patch merged into coreboot/master: 5dac6d8 Intel and GFXUMA: fix MTRR and use uma_resource()
by gerrit＠coreboot.org 27 Jul '12

27 Jul '12

the following patch was just integrated into master: commit 5dac6d8ac870bcac7959ad24893161bf6a133ab6 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Jul 27 08:42:20 2012 +0300 Intel and GFXUMA: fix MTRR and use uma_resource() Commit 2d42b340034ff005693482ef9ca34ce3e0f08371 changed the variable MTRR setup and removed compensation of uma_memory_size in the cacheable memory resources. Since the cacheable region size was no longer divisible by a large power of 2, like 256 MB, this caused excessive use of MTRRs. As first symptoms, slow boot with grub and poor user response. As a solution, register the actual top of low ram with ram_resource(), and do not subtract the UMA/TSEG regions from it. TSEG may require further work as the original did not appear exactly right to begin with. To have UMA as un-cacheable, use uma_resource(). Change-Id: I4ca99b5c2ca4e474296590b3d0c6ef5d09550d80 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Build-Tested: build bot (Jenkins) at Fri Jul 27 15:50:22 2012, giving +1 Reviewed-By: Anton Kochkov <anton.kochkov(a)gmail.com> at Fri Jul 27 14:08:05 2012, giving +2 See http://review.coreboot.org/1239 for details. -gerrit

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Patch merged into coreboot/master: 8a27000 x86emu: fix comment for BTS instruction
by gerrit＠coreboot.org 27 Jul '12

27 Jul '12

the following patch was just integrated into master: commit 8a27000703712f31184d66f2de861a499ac5eb30 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Jul 26 15:20:13 2012 -0700 x86emu: fix comment for BTS instruction Change-Id: Iacce58945f66213e75c7aac89541e785e80664cb Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Fri Jul 27 14:42:05 2012, giving +2 See http://review.coreboot.org/1363 for details. -gerrit

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Patch merged into coreboot/master: 7e2ee67 x86emu: Add an RDTSC implementation to the x86 emulator
by gerrit＠coreboot.org 27 Jul '12

27 Jul '12

the following patch was just integrated into master: commit 7e2ee67a5b61e66390413d13c7ca62daad272f02 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Jul 26 15:15:38 2012 -0700 x86emu: Add an RDTSC implementation to the x86 emulator This instruction is being used in some debug VBIOSes. This implementation doesn't even try to be accurate. Instead, it just increments the counter by a fixed amount every time an rdtsc instruction in encountered, to avoid divides by zero. Imported from: http://cgit.freedesktop.org/xorg/xserver/commit/?id=c4b7e9d1c16797c3e4b1200… Change-Id: I8fba1a060c57ccb7bbd44aa321dd349bc56bf574 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Fri Jul 27 14:41:20 2012, giving +2 See http://review.coreboot.org/1362 for details. -gerrit

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Patch set updated for coreboot: 5dac6d8 Intel and GFXUMA: fix MTRR and use uma_resource()
by Anton Kochkov 27 Jul '12

27 Jul '12

Anton Kochkov (anton.kochkov(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1239 -gerrit commit 5dac6d8ac870bcac7959ad24893161bf6a133ab6 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Jul 27 08:42:20 2012 +0300 Intel and GFXUMA: fix MTRR and use uma_resource() Commit 2d42b340034ff005693482ef9ca34ce3e0f08371 changed the variable MTRR setup and removed compensation of uma_memory_size in the cacheable memory resources. Since the cacheable region size was no longer divisible by a large power of 2, like 256 MB, this caused excessive use of MTRRs. As first symptoms, slow boot with grub and poor user response. As a solution, register the actual top of low ram with ram_resource(), and do not subtract the UMA/TSEG regions from it. TSEG may require further work as the original did not appear exactly right to begin with. To have UMA as un-cacheable, use uma_resource(). Change-Id: I4ca99b5c2ca4e474296590b3d0c6ef5d09550d80 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/intel/i82810/northbridge.c | 11 +++++---- src/northbridge/intel/i82830/northbridge.c | 14 +++++----- src/northbridge/intel/i945/northbridge.c | 34 ++++++++++++++------------- src/northbridge/intel/sch/northbridge.c | 26 +++++++++++---------- 4 files changed, 45 insertions(+), 40 deletions(-) diff --git a/src/northbridge/intel/i82810/northbridge.c b/src/northbridge/intel/i82810/northbridge.c index 892fc28..f6d14e0 100644 --- a/src/northbridge/intel/i82810/northbridge.c +++ b/src/northbridge/intel/i82810/northbridge.c @@ -93,7 +93,7 @@ static void pci_domain_set_resources(device_t dev) if (!mc_dev) return; - unsigned long tomk; + unsigned long tomk, tomk_stolen; int idx, drp_value; u8 reg8; @@ -123,21 +123,22 @@ static void pci_domain_set_resources(device_t dev) tomk += (unsigned long)(translate_i82810_to_mb[drp_value]); /* Convert tomk from MB to KB. */ tomk = tomk << 10; - tomk -= igd_memory; + tomk_stolen = tomk - igd_memory; /* For reserving UMA memory in the memory map */ - uma_memory_base = tomk * 1024ULL; + uma_memory_base = tomk_stolen * 1024ULL; uma_memory_size = igd_memory * 1024ULL; - printk(BIOS_DEBUG, "Available memory: %ldKB\n", tomk); + printk(BIOS_DEBUG, "Available memory: %ldKB\n", tomk_stolen); /* Report the memory regions. */ idx = 10; ram_resource(dev, idx++, 0, 640); ram_resource(dev, idx++, 768, tomk - 768); + uma_resource(dev, idx++, uma_memory_base >> 10, uma_memory_size >> 10); #if CONFIG_WRITE_HIGH_TABLES /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; + high_tables_base = (tomk_stolen * 1024) - HIGH_MEMORY_SIZE; high_tables_size = HIGH_MEMORY_SIZE; #endif assign_resources(dev->link_list); diff --git a/src/northbridge/intel/i82830/northbridge.c b/src/northbridge/intel/i82830/northbridge.c index 4ada4d7..649a203 100644 --- a/src/northbridge/intel/i82830/northbridge.c +++ b/src/northbridge/intel/i82830/northbridge.c @@ -73,7 +73,7 @@ static void pci_domain_set_resources(device_t dev) if (!mc_dev) return; - unsigned long tomk; + unsigned long tomk, tomk_stolen; int idx; if (CONFIG_VIDEO_MB == 512) { @@ -89,24 +89,24 @@ static void pci_domain_set_resources(device_t dev) * i.e. 1 means 32MB. */ tomk = ((unsigned long)pci_read_config8(mc_dev, DRB + 3)) << 15; - tomk -= igd_memory; + tomk_stolen = tomk - igd_memory; /* For reserving UMA memory in the memory map */ - uma_memory_base = tomk * 1024ULL; + uma_memory_base = tomk_stolen * 1024ULL; uma_memory_size = igd_memory * 1024ULL; - printk(BIOS_DEBUG, "Available memory: %ldKB\n", tomk); + printk(BIOS_DEBUG, "Available memory: %ldKB\n", tomk_stolen); /* Report the memory regions. */ idx = 10; ram_resource(dev, idx++, 0, 640); - ram_resource(dev, idx++, 768, 256); - ram_resource(dev, idx++, 1024, tomk - 1024); + ram_resource(dev, idx++, 768, tomk - 768); + uma_resource(dev, idx++, uma_memory_base >> 10, uma_memory_size >> 10); assign_resources(dev->link_list); #if CONFIG_WRITE_HIGH_TABLES /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; + high_tables_base = (tomk_stolen * 1024) - HIGH_MEMORY_SIZE; high_tables_size = HIGH_MEMORY_SIZE; #endif } diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 9a69823..9d6d0df 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -73,16 +73,9 @@ static void add_fixed_resources(struct device *dev, int index) struct resource *resource; u32 pcie_config_base, pcie_config_size; - printk(BIOS_DEBUG, "Adding UMA memory area\n"); - resource = new_resource(dev, index); - resource->base = (resource_t) uma_memory_base; - resource->size = (resource_t) uma_memory_size; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; - if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) { printk(BIOS_DEBUG, "Adding PCIe config bar\n"); - resource = new_resource(dev, index+1); + resource = new_resource(dev, index++); resource->base = (resource_t) pcie_config_base; resource->size = (resource_t) pcie_config_size; resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | @@ -99,7 +92,8 @@ static void pci_domain_set_resources(device_t dev) uint32_t pci_tolm; uint8_t tolud, reg8; uint16_t reg16; - unsigned long long tomk; + unsigned long long tomk, tomk_stolen; + uint64_t tseg_memory_base = 0, tseg_memory_size = 0; /* Can we find out how much memory we can use at most * this way? @@ -114,6 +108,7 @@ static void pci_domain_set_resources(device_t dev) printk(BIOS_SPEW, "Top of Low Used DRAM: 0x%08x\n", tolud << 24); tomk = tolud << 14; + tomk_stolen = tomk; /* Note: subtract IGD device and TSEG */ reg8 = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), 0x9e); @@ -135,7 +130,11 @@ static void pci_domain_set_resources(device_t dev) } printk(BIOS_DEBUG, "%dM\n", tseg_size >> 10); - tomk -= tseg_size; + tomk_stolen -= tseg_size; + + /* For reserving TSEG memory in the memory map */ + tseg_memory_base = tomk_stolen * 1024ULL; + tseg_memory_size = tseg_size * 1024ULL; } reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), GGC); @@ -154,29 +153,32 @@ static void pci_domain_set_resources(device_t dev) } printk(BIOS_DEBUG, "%dM UMA\n", uma_size >> 10); - tomk -= uma_size; + tomk_stolen -= uma_size; /* For reserving UMA memory in the memory map */ - uma_memory_base = tomk * 1024ULL; + uma_memory_base = tomk_stolen * 1024ULL; uma_memory_size = uma_size * 1024ULL; } /* The following needs to be 2 lines, otherwise the second * number is always 0 */ - printk(BIOS_INFO, "Available memory: %dK", (uint32_t)tomk); - printk(BIOS_INFO, " (%dM)\n", (uint32_t)(tomk >> 10)); + printk(BIOS_INFO, "Available memory: %dK", (uint32_t)tomk_stolen); + printk(BIOS_INFO, " (%dM)\n", (uint32_t)(tomk_stolen >> 10)); /* Report the memory regions */ ram_resource(dev, 3, 0, 640); ram_resource(dev, 4, 768, (tomk - 768)); - add_fixed_resources(dev, 6); + uma_resource(dev, 5, uma_memory_base >> 10, uma_memory_size >> 10); + mmio_resource(dev, 6, tseg_memory_base >> 10, tseg_memory_size >> 10); + + add_fixed_resources(dev, 7); assign_resources(dev->link_list); #if CONFIG_WRITE_HIGH_TABLES /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; + high_tables_base = (tomk_stolen * 1024) - HIGH_MEMORY_SIZE; high_tables_size = HIGH_MEMORY_SIZE; #endif } diff --git a/src/northbridge/intel/sch/northbridge.c b/src/northbridge/intel/sch/northbridge.c index 52b688a..419a82c 100644 --- a/src/northbridge/intel/sch/northbridge.c +++ b/src/northbridge/intel/sch/northbridge.c @@ -78,13 +78,6 @@ static void add_fixed_resources(struct device *dev, int index) struct resource *resource; u32 pcie_config_base, pcie_config_size; - printk(BIOS_DEBUG, "Adding UMA memory area\n"); - resource = new_resource(dev, index++); - resource->base = (resource_t) uma_memory_base; - resource->size = (resource_t) uma_memory_size; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; - if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) { printk(BIOS_DEBUG, "Adding PCIe config bar\n"); resource = new_resource(dev, index++); @@ -111,7 +104,8 @@ static void pci_domain_set_resources(device_t dev) u32 pci_tolm; u8 reg8; u16 reg16; - unsigned long long tomk, tolud; + unsigned long long tomk, tolud, tomk_stolen; + uint64_t tseg_memory_base = 0, tseg_memory_size = 0; /* Can we find out how much memory we can use at most this way? */ pci_tolm = find_pci_tolm(dev->link_list); @@ -123,6 +117,7 @@ static void pci_domain_set_resources(device_t dev) printk(BIOS_SPEW, "Top of Low Used DRAM: 0x%08llx\n", tolud << 24); tomk = tolud << 14; + tomk_stolen = tomk; /* Note: subtract IGD device and TSEG. */ reg8 = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), 0x9e); @@ -144,7 +139,11 @@ static void pci_domain_set_resources(device_t dev) } printk(BIOS_DEBUG, "%dM\n", tseg_size >> 10); - tomk -= tseg_size; + tomk_stolen -= tseg_size; + + /* For reserving TSEG memory in the memory map */ + tseg_memory_base = tomk_stolen * 1024ULL; + tseg_memory_size = tseg_size * 1024ULL; } reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), GGC); @@ -165,10 +164,10 @@ static void pci_domain_set_resources(device_t dev) break; } printk(BIOS_DEBUG, "%dM UMA\n", uma_size >> 10); - tomk -= uma_size; + tomk_stolen -= uma_size; /* For reserving UMA memory in the memory map. */ - uma_memory_base = tomk * 1024ULL; + uma_memory_base = tomk_stolen * 1024ULL; uma_memory_size = uma_size * 1024ULL; } @@ -182,7 +181,10 @@ static void pci_domain_set_resources(device_t dev) /* Report the memory regions. */ ram_resource(dev, 3, 0, 640); ram_resource(dev, 4, 768, (tomk - 768)); - add_fixed_resources(dev, 6); + uma_resource(dev, 5, uma_memory_base >> 10, uma_memory_size >> 10); + mmio_resource(dev, 6, tseg_memory_base >> 10, tseg_memory_size >> 10); + + add_fixed_resources(dev, 7); assign_resources(dev->link_list);

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Patch merged into coreboot/master: 8f9c748 Intel 82810 and 82830: always room for PCI memory
by gerrit＠coreboot.org 27 Jul '12

27 Jul '12

the following patch was just integrated into master: commit 8f9c7489171d53c42ee7e9a387628c57adce8ddd Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Jul 27 08:40:46 2012 +0300 Intel 82810 and 82830: always room for PCI memory No need for the test, tomk is at most 1GB on these chipsets. Even if there was no room, adjusting the memory resource would not not divert accesses in the hardware from DRAM to PCI. Change-Id: I2213b8d9d2e6ab8da8fd3e8081cc62bb05b6b316 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Build-Tested: build bot (Jenkins) at Fri Jul 27 11:44:14 2012, giving +1 Reviewed-By: Anton Kochkov <anton.kochkov(a)gmail.com> at Fri Jul 27 14:05:15 2012, giving +2 See http://review.coreboot.org/1369 for details. -gerrit

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Patch set updated for coreboot: b161e56 Intel and GFXUMA: drop redundant use of lb_add_memory_range()
by Kyösti Mälkki 27 Jul '12

27 Jul '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1238 -gerrit commit b161e5614ce6660b14a10d39d9a673715b88160c Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Jul 18 14:38:54 2012 +0300 Intel and GFXUMA: drop redundant use of lb_add_memory_range() Use of uma_resource() in northbridge code created a memory resource marked as reserved. Such resources are removed from system memory in write_coreboot_table(). Change-Id: I14bfd560140d8d30ec156562f23072bfae747bde Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/asus/mew-am/mainboard.c | 2 +- src/mainboard/asus/mew-vm/mainboard.c | 2 +- src/mainboard/ecs/p6iwp-fe/mainboard.c | 2 +- src/mainboard/hp/e_vectra_p2706t/mainboard.c | 2 +- src/mainboard/intel/d810e2cb/mainboard.c | 2 +- src/mainboard/intel/emeraldlake2/mainboard.c | 2 +- src/mainboard/mitac/6513wu/mainboard.c | 2 +- src/mainboard/msi/ms6178/mainboard.c | 2 +- src/mainboard/nec/powermate2000/mainboard.c | 2 +- src/mainboard/rca/rm4100/mainboard.c | 2 +- src/mainboard/samsung/lumpy/mainboard.c | 2 +- src/mainboard/samsung/stumpy/mainboard.c | 2 +- src/mainboard/thomson/ip1000/mainboard.c | 2 +- src/northbridge/intel/i82810/northbridge.c | 9 --------- src/northbridge/intel/i82830/northbridge.c | 9 --------- src/northbridge/intel/sandybridge/northbridge.c | 5 ----- 16 files changed, 13 insertions(+), 36 deletions(-) diff --git a/src/mainboard/asus/mew-am/mainboard.c b/src/mainboard/asus/mew-am/mainboard.c index 8887218..6409dab 100644 --- a/src/mainboard/asus/mew-am/mainboard.c +++ b/src/mainboard/asus/mew-am/mainboard.c @@ -23,7 +23,7 @@ int add_mainboard_resources(struct lb_memory *mem) { - return add_northbridge_resources(mem); + return 0; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/asus/mew-vm/mainboard.c b/src/mainboard/asus/mew-vm/mainboard.c index e278565..2e43be2 100644 --- a/src/mainboard/asus/mew-vm/mainboard.c +++ b/src/mainboard/asus/mew-vm/mainboard.c @@ -3,7 +3,7 @@ int add_mainboard_resources(struct lb_memory *mem) { - return add_northbridge_resources(mem); + return 0; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/ecs/p6iwp-fe/mainboard.c b/src/mainboard/ecs/p6iwp-fe/mainboard.c index 9031ac7..667ac5e 100644 --- a/src/mainboard/ecs/p6iwp-fe/mainboard.c +++ b/src/mainboard/ecs/p6iwp-fe/mainboard.c @@ -23,7 +23,7 @@ int add_mainboard_resources(struct lb_memory *mem) { - return add_northbridge_resources(mem); + return 0; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/hp/e_vectra_p2706t/mainboard.c b/src/mainboard/hp/e_vectra_p2706t/mainboard.c index 0f9b75e..80e6f61 100644 --- a/src/mainboard/hp/e_vectra_p2706t/mainboard.c +++ b/src/mainboard/hp/e_vectra_p2706t/mainboard.c @@ -23,7 +23,7 @@ int add_mainboard_resources(struct lb_memory *mem) { - return add_northbridge_resources(mem); + return 0; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/intel/d810e2cb/mainboard.c b/src/mainboard/intel/d810e2cb/mainboard.c index 7589d6e..8455377 100644 --- a/src/mainboard/intel/d810e2cb/mainboard.c +++ b/src/mainboard/intel/d810e2cb/mainboard.c @@ -22,7 +22,7 @@ int add_mainboard_resources(struct lb_memory *mem) { - return add_northbridge_resources(mem); + return 0; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/intel/emeraldlake2/mainboard.c b/src/mainboard/intel/emeraldlake2/mainboard.c index 5717edf..796f71e 100644 --- a/src/mainboard/intel/emeraldlake2/mainboard.c +++ b/src/mainboard/intel/emeraldlake2/mainboard.c @@ -44,7 +44,7 @@ void mainboard_suspend_resume(void) int add_mainboard_resources(struct lb_memory *mem) { - return add_northbridge_resources(mem); + return 0; } #if defined(CONFIG_PCI_OPTION_ROM_RUN_REALMODE) && CONFIG_PCI_OPTION_ROM_RUN_REALMODE diff --git a/src/mainboard/mitac/6513wu/mainboard.c b/src/mainboard/mitac/6513wu/mainboard.c index 968b9e9..04af449 100644 --- a/src/mainboard/mitac/6513wu/mainboard.c +++ b/src/mainboard/mitac/6513wu/mainboard.c @@ -23,7 +23,7 @@ int add_mainboard_resources(struct lb_memory *mem) { - return add_northbridge_resources(mem); + return 0; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/msi/ms6178/mainboard.c b/src/mainboard/msi/ms6178/mainboard.c index 0aeedb8..76c8c04 100644 --- a/src/mainboard/msi/ms6178/mainboard.c +++ b/src/mainboard/msi/ms6178/mainboard.c @@ -23,7 +23,7 @@ int add_mainboard_resources(struct lb_memory *mem) { - return add_northbridge_resources(mem); + return 0; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/nec/powermate2000/mainboard.c b/src/mainboard/nec/powermate2000/mainboard.c index 3b29c7c..3bbaa11 100644 --- a/src/mainboard/nec/powermate2000/mainboard.c +++ b/src/mainboard/nec/powermate2000/mainboard.c @@ -23,7 +23,7 @@ int add_mainboard_resources(struct lb_memory *mem) { - return add_northbridge_resources(mem); + return 0; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/rca/rm4100/mainboard.c b/src/mainboard/rca/rm4100/mainboard.c index 613c1d7..ff98977 100644 --- a/src/mainboard/rca/rm4100/mainboard.c +++ b/src/mainboard/rca/rm4100/mainboard.c @@ -24,7 +24,7 @@ int add_mainboard_resources(struct lb_memory *mem) { - return add_northbridge_resources(mem); + return 0; } static void mainboard_init(device_t dev) diff --git a/src/mainboard/samsung/lumpy/mainboard.c b/src/mainboard/samsung/lumpy/mainboard.c index 20b59b7..e83516a 100644 --- a/src/mainboard/samsung/lumpy/mainboard.c +++ b/src/mainboard/samsung/lumpy/mainboard.c @@ -51,7 +51,7 @@ void mainboard_suspend_resume(void) int add_mainboard_resources(struct lb_memory *mem) { - return add_northbridge_resources(mem); + return 0; } #if defined(CONFIG_PCI_OPTION_ROM_RUN_REALMODE) && CONFIG_PCI_OPTION_ROM_RUN_REALMODE diff --git a/src/mainboard/samsung/stumpy/mainboard.c b/src/mainboard/samsung/stumpy/mainboard.c index 2456e70..246b261 100644 --- a/src/mainboard/samsung/stumpy/mainboard.c +++ b/src/mainboard/samsung/stumpy/mainboard.c @@ -44,7 +44,7 @@ void mainboard_suspend_resume(void) int add_mainboard_resources(struct lb_memory *mem) { - return add_northbridge_resources(mem); + return 0; } #if defined(CONFIG_PCI_OPTION_ROM_RUN_REALMODE) && CONFIG_PCI_OPTION_ROM_RUN_REALMODE diff --git a/src/mainboard/thomson/ip1000/mainboard.c b/src/mainboard/thomson/ip1000/mainboard.c index e5c3ea1..ae5872d 100644 --- a/src/mainboard/thomson/ip1000/mainboard.c +++ b/src/mainboard/thomson/ip1000/mainboard.c @@ -30,7 +30,7 @@ int add_mainboard_resources(struct lb_memory *mem) { - return add_northbridge_resources(mem); + return 0; } // setting the bit disables the led. diff --git a/src/northbridge/intel/i82810/northbridge.c b/src/northbridge/intel/i82810/northbridge.c index f6d14e0..c738de7 100644 --- a/src/northbridge/intel/i82810/northbridge.c +++ b/src/northbridge/intel/i82810/northbridge.c @@ -62,15 +62,6 @@ static const struct pci_driver i810e_northbridge_driver __pci_driver = { .device = 0x7124, }; -int add_northbridge_resources(struct lb_memory *mem) -{ - printk(BIOS_DEBUG, "Adding IGD UMA memory area\n"); - lb_add_memory_range(mem, LB_MEM_RESERVED, - uma_memory_base, uma_memory_size); - - return 0; -} - /* Table which returns the RAM size in MB when fed the DRP[7:4] or [3:0] value. * Note that 2 is a value which the DRP should never be programmed to. * Some size values appear twice, due to single-sided vs dual-sided banks. diff --git a/src/northbridge/intel/i82830/northbridge.c b/src/northbridge/intel/i82830/northbridge.c index 649a203..4951c4f 100644 --- a/src/northbridge/intel/i82830/northbridge.c +++ b/src/northbridge/intel/i82830/northbridge.c @@ -52,15 +52,6 @@ static const struct pci_driver northbridge_driver __pci_driver = { .device = 0x3575, }; -int add_northbridge_resources(struct lb_memory *mem) -{ - printk(BIOS_DEBUG, "Adding IGD UMA memory area\n"); - lb_add_memory_range(mem, LB_MEM_RESERVED, - uma_memory_base, uma_memory_size); - - return 0; -} - #if CONFIG_WRITE_HIGH_TABLES #include <cbmem.h> #endif diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 5a9388e..eec49dd 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -61,11 +61,6 @@ int bridge_silicon_revision(void) static const int legacy_hole_base_k = 0xa0000 / 1024; static const int legacy_hole_size_k = 384; -int add_northbridge_resources(struct lb_memory *mem) -{ - return 0; -} - void cbmem_post_handling(void) { update_mrc_cache();

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coreboot July 2012