coreboot March 2012

coreboot@coreboot.org

58 participants
718 discussions

Start a nNew thread

Trac reminder: list of new ticket(s)
by coreboot tracker 26 Mar '12

26 Mar '12

1 0

Coreboot Support
by Marc Dunivan 26 Mar '12

26 Mar '12

Is this motherboard supported? Also, who controls the copyright to coreboot? I assume coreboot is licensed under the GPL and the copyright has be assigned to Free Software Foundation. HP Pavilion AMD64, ASUS M2N68-LA http://h10025.www1.hp.com/ewfrf/wc/document?lc=en&dlc=en&cc=de&docname=c009… NVidia MCP61P Super I/O F8000 lspci -tvnn -[0000:00]-+-00.0 nVidia Corporation MCP61 Memory Controller [10de:03ea] +-01.0 nVidia Corporation MCP61 LPC Bridge [10de:03e0] +-01.1 nVidia Corporation MCP61 SMBus [10de:03eb] +-01.2 nVidia Corporation MCP61 Memory Controller [10de:03f5] +-02.0 nVidia Corporation MCP61 USB Controller [10de:03f1] +-02.1 nVidia Corporation MCP61 USB Controller [10de:03f2] +-04.0-[01]----0a.0 Ralink corp. RT2800 802.11n PCI [1814:0601] +-05.0 nVidia Corporation MCP61 High Definition Audio [10de:03f0] +-06.0 nVidia Corporation MCP61 IDE [10de:03ec] +-07.0 nVidia Corporation MCP61 Ethernet [10de:03ef] +-08.0 nVidia Corporation MCP61 SATA Controller [10de:03f6] +-08.1 nVidia Corporation MCP61 SATA Controller [10de:03f6] +-09.0-[02]-- +-0b.0-[03]-- +-0d.0 nVidia Corporation C61 [GeForce 6150SE nForce 430] [10de:03d0] +-18.0 Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration [1022:1100] +-18.1 Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Address Map [1022:1101] +-18.2 Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] DRAM Controller [1022:1102] sudo superiotool -dV superiotool r5050 Probing for ALi Super I/O at 0x3f0... Failed. Returned data: id=0xffff, rev=0xff Probing for ALi Super I/O at 0x370... Failed. Returned data: id=0xffff, rev=0xff Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0x3419, id=0x8105 Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0xffff, id=0xffff Probing for ITE Super I/O (init=standard) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id=0x0581, rev=0x9 Probing for ITE Super I/O (init=standard) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=legacy/it8661f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=legacy/it8671f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for NSC Super I/O at 0x2e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x4e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x15c... Failed. Returned data: port=0xff, port+1=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id/oldid=0x05/0x0f, rev=0x81 Probing for Winbond Super I/O (init=0x88) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for VIA Super I/O at 0x3f0... PCI device 1106:0686 not found. No Super I/O found sudo flashrom flashrom v0.9.2-r1141 on Linux 2.6.38-13-generic (x86_64), built with libpci 3.1.7, GCC 4.5.1, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. No coreboot table found. Found chipset "NVIDIA MCP61", enabling flash write... This chipset is not really supported yet. Guesswork... SPI on this chipset is WIP. Write is unsupported! Mapping NVIDIA MCP6x SPI at 0xfec80000, unaligned size 0x544. Please send the output of "flashrom -V" to flashrom(a)flashrom.org to help us finish support for your chipset. Thanks. OK. This chipset supports the following protocols: SPI. Found chip "Winbond W25x40" (512 KB, SPI) at physical address 0xfff80000. No operations were specified.

1 0

Re: [coreboot] asus l1n64 - this is damn Nvidia
by Julian Shulika 25 Mar '12

25 Mar '12

coreboot-4.0-2135-gccee625-dirty Fri Mar 23 15:02:04 EDT 2012 starting... BSP Family_Model: 00100f42 *sysinfo range: [000cc000,000cdfa0] bsp_apicid = 00 cpu_init_detectedx = 00000000 microcode: equivalent rev id = 0x1041, current patch id = 0x00000000 microcode: patch id to apply = 0x01000086 microcode: updated to patch id = 0x01000086 success POST: 0x33 cpuSetAMDMSR done POST: 0x34 Enter amd_ht_init() AMD_CB_EventNotify() event class: 05 event: 1004 data: 04 00 02 01 AMD_CB_ManualBUIDSwapList() AMD_CB_EventNotify() event class: 05 event: 2006 data: 04 00 01 ff Exit amd_ht_init() POST: 0x35 cpuSetAMDPCI 00 done cpuSetAMDPCI 01 done Prep FID/VID Node:00 F3x80: e600e681 F3x84: 80e641e6 F3xD4: c3310f24 F3xD8: 03001615 F3xDC: 00006322 Prep FID/VID Node:01 F3x80: e600e681 F3x84: 80e641e6 F3xD4: c3310f24 F3xD8: 03001615 F3xDC: 00006322 setup_remote_node: 01 done Start node 01 done. POST: 0x36 core0 started: POST: 0x30 core0: --- { APICID = 04 NODEID = 01 COREID = 00} --- 01microcode: equivalent rev id = 0x1041, current patch id = 0x00000000 itarmit_cortochoedr_e:c opreast(ch) d to apply = 0x01000086 iincriotc nooded:e: u0pd0a t ceodr teos : p0a3tc h id = 0x01000086 success StcapurSt eottAhMDeMrS cRo re - nodeid: 00 cores: 03 :nit dnoondee ( 0i1 ni tc_ofriedsv:i d0_3a p -stSatgaer1t) o atphiecri dco: re04 s nFIoDdeVIiDd :o n0 1A P :c o0r4e : 03 POST: 0x37 started ap apicid: PPPOOOSSSTTT::: 000xxx333000 x cccooorrreeexxx::: --------- {{{ AAAPPPIIICCCIIIDDD === 000132 NNNOOODDDEEEIIIDDD === 00x * mAm33m3Pii00i0c ccrr0roo1occcooodddeee::: eeeqqquuuiiivvvaaallleeennnttt rrreeevvv iiiddd === 0 s m tedmm RE iciiccccocrrororroeorocecxcexoxoo: d:d:d e e e :-: :- - - -p-p-p-a a-at t{t {c{cc Ah h hA P A iPiIiPIdIddCO R R EIEIIDD D= == 0 10032}} }- -------- tmmii*icc crrArmmmooPoiiiccc cccrroo0orooodd2dceccee::o:oodd d eueeuup:p::p d dd eaeaeaqtqtqteueueuididdiv v a t t h c h h iiiddd === 000xxx000000000000000000000000 AicAcMMapuuruSStSeeeemmdtmittiA 6 McrorDDrDoMcoMMScSocSoRoRRde d d e:e:: p appaattcthcchh i iidd dt ttoo oa aapppplppllyy y= = = 0 06 u*mi iicAccrrPro ooc c0 cd3ooddododdoonnenee::ee:e u u pppdddaaattteeeddd tttooo pppaaatttccchhh iiiddd === 000xxx000111000000000000888666 sssuuucs AfAfMiipaipiunnurnuSSiiStietetteetdt_t__Af MiMDDddDdMvMMvviSiSSiRdRddR _ _ _aaappp(((ssstttaaagggeee111))) aaapppiiiccciiiddd::: 000123 F*III DDDAVVVP III ddDDD0dooo 5nnnooonneeen A A APPP::: 000123 itiiiannnriiitttet__d_fff iidddvvviiiddd___aaappp(((ssstttaaagggeee111))) aaapppiiiccciiiddd::: 000657 FFF*I IIDDADVVVPIII D0DD 6 ooonnn AAAPPP::: 000657 started * AP 07started POST: 0x38 Begin FIDVID MSR 0xc0010071 0x30b000a3 0x40034040 POST: 0x39 FIDVID on BSP, APIC_id: 00 BSP fid = 10600 Wait for AP stage 1: ap_apicid = 1 readback = 1010601 common_fid(packed) = 10600 Wait for AP stage 1: ap_apicid = 2 readback = 2010601 common_fid(packed) = 10600 Wait for AP stage 1: ap_apicid = 3 readback = 3010601 common_fid(packed) = 10600 Wait for AP stage 1: ap_apicid = 4 readback = 4010601 common_fid(packed) = 10600 Wait for AP stage 1: ap_apicid = 5 readback = 5010601 common_fid(packed) = 10600 Wait for AP stage 1: ap_apicid = 6 readback = 6010601 common_fid(packed) = 10600 Wait for AP stage 1: ap_apicid = 7 readback = 7010601 common_fid(packed) = 10600 common_fid = 10600 FID Change Node:00, F3xD4: c3310f26 FID Change Node:01, F3xD4: c3310f26 POST: 0x3a End FIDVIDMSR 0xc0010071 0x30b000a3 0x30003040 mcp55_num:01 ...WARM RESET...

1 0

asus l1n64 - this is damn Nvidia
by Julian Shulika 25 Mar '12

25 Mar '12

---------- Forwarded message ---------- From: Julian Shulika <hercares(a)gmail.com> Date: 2012/3/26 Subject: Re: coreboot and opteron 8431 To: Arne Georg Gleditsch <arne(a)gledits.ch> I tried to port asus l1n64 more than one year. This board also based on mcp55,this is only one board for AMD 4x4 platform. It differs from other similar board by different scheme Tyan S2912, supermicro h8dmr have connection diagram, if I use just cpu0,I can't use second mcp55 *mcp55 <->cpu1 <-> cpu0 <-> mcp55 *Asus L1N64 has different connection diagram *mcp55 <-> mcp55<->cpu0 <-> cpu1 * I saw your posts when you try to help guy with supermicro board,but I'm stuck in one place,because I have not reached to memory init, I think it's because of wrong devicetree. Could you please look at lspci output, may be you can see something... Thanks for your work done chip northbridge/amd/amdfam10/root_complex # Root complex device lapic_cluster 0 on # (L)APIC cluster chip cpu/amd/socket_F_1207 # CPU socket device lapic 0 on end # Local APIC of the CPU end end device pci_domain 0 on # PCI domain subsystemid 0x10de 0x81fb inherit chip northbridge/amd/amdfam10 # Northbridge / RAM controller device pci 18.0 on end device pci 18.0 on end chip southbridge/nvidia/mcp55 # Southbridge device pci 0.0 on end # HT device pci 1.0 on end # LPC device pci 1.1 on end # LPC device pci 5.1 on end # SATA 1 device pci 5.2 on end # SATA 2 device pci a.0 off end # PCI E 5 device pci f.0 off end # PCI E 5 end device pci 18.0 on # SB on link 2 chip southbridge/nvidia/mcp55 # Southbridge device pci 0.0 on end # HT device pci 1.0 on # LPC chip superio/ite/it8716f # Super I/O device pnp 2e.0 on # Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end device pnp 2e.1 on # Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end device pnp 2e.2 off # Com2 (N/A) end device pnp 2e.3 on # Parallel port io 0x60 = 0x378 io 0x62 = 0x000 irq 0x70 = 7 drq 0x74 = 4 end device pnp 2e.4 on # Environment controller io 0x60 = 0x290 io 0x62 = 0x000 irq 0x70 = 0 end device pnp 2e.5 on # PS/2 keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 # PS/2 keyboard IRQ end device pnp 2e.6 on # PS/2 mouse irq 0x70 = 12 # PS/2 mouse IRQ end device pnp 2e.7 off # GPIO io 0x60 = 0x0000 # SMI# Normal Run Access io 0x62 = 0x800 # Simple I/O io 0x64 = 0x0000 # Serial Flash I/F end device pnp 2e.8 off # MIDI (N/A) end device pnp 2e.9 off # Game port (N/A) end device pnp 2e.a off # Consumer IR (N/A) end end # Super I/O end device pci 1.1 on # SM 0 chip drivers/generic/generic # DIMM 0-0-0 device i2c 50 on end end chip drivers/generic/generic # DIMM 0-0-1 device i2c 51 on end end chip drivers/generic/generic # DIMM 0-1-0 device i2c 52 on end end chip drivers/generic/generic # DIMM 0-1-1 device i2c 53 on end end end device pci 2.0 on end # USB 1.1 device pci 2.1 on end # USB 2 device pci 4.0 on end # IDE device pci 5.0 on end # SATA 0 device pci 5.1 on end # SATA 1 device pci 5.2 on end # SATA 2 device pci 6.0 on # PCI device pci 6.0 on end end device pci 6.1 on end # AZA device pci 8.0 on end # NIC device pci 9.0 on end # NIC device pci a.0 on end # PCI E 5 device pci d.0 on end # PCI E 2 device pci e.0 on end # PCI E 1 device pci f.0 on end # PCI E 0 register "ide0_enable" = "1" register "sata0_enable" = "1" register "sata1_enable" = "1" # 1: SMBus under 2e.8, 2: SM0 3: SM1 register "mac_eeprom_smbus" = "3" register "mac_eeprom_addr" = "0x51" end end device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end device pci 18.4 on end end end # chip drivers/generic/debug # device pnp 0.0 off end # chip name # device pnp 0.1 on end # pci_regs_all # device pnp 0.2 on end # mem # device pnp 0.3 off end # cpuid # device pnp 0.4 on end # smbus_regs_all # device pnp 0.5 off end # dual core msr # device pnp 0.6 off end # cache size # device pnp 0.7 off end # tsc # device pnp 0.8 off end # io # device pnp 0.9 off end # io # end end

1 0

New patch to review for coreboot: 8f69c9a Disable the GDB stub by default
by Rudolf Marek 25 Mar '12

25 Mar '12

Rudolf Marek (r.marek(a)assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/811 -gerrit commit 8f69c9a5fefe2107dffd711f94b3f2c3d81df506 Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Sun Mar 25 20:51:16 2012 +0200 Disable the GDB stub by default I would prefer to see the exception dump on serial rather than cryptic GDB protocol. Change-Id: Ib25513d33e6a31da24586fecb00adb5206bb43bd Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> --- src/Kconfig | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index c165d93..845d26f 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -570,7 +570,7 @@ menu "Debugging" # TODO: Better help text and detailed instructions. config GDB_STUB bool "GDB debugging support" - default y + default n help If enabled, you will be able to set breakpoints for gdb debugging. See src/arch/x86/lib/c_start.S for details.

1 0

Patch merged into coreboot/master: af24a61 Fix possible deadlock on SMP stop_this_cpu
by gerrit＠coreboot.org 25 Mar '12

25 Mar '12

the following patch was just integrated into master: commit af24a610077c3bca7aa2e47bb0a05b4b1035f996 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Mar 4 02:24:36 2012 +0200 Fix possible deadlock on SMP stop_this_cpu Do not use printk on the running thread after it has been sent the INIT IPI, execution may halt with console spinlock held. Change-Id: I64608935ea740fb827fa0307442f3fb102de7a08 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Build-Tested: build bot (Jenkins) at Sat Mar 10 05:53:05 2012, giving +1 Reviewed-By: Rudolf Marek <r.marek(a)assembler.cz> at Sun Mar 25 20:35:24 2012, giving +2 See http://review.coreboot.org/776 for details. -gerrit

1 0

Patch merged into coreboot/master: bf36231 Intel cpus: Fix deadlock on hyper-threading init
by gerrit＠coreboot.org 25 Mar '12

25 Mar '12

the following patch was just integrated into master: commit bf362311db9948925b5580a9922a58c4c8726c82 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Mar 9 17:02:37 2012 +0200 Intel cpus: Fix deadlock on hyper-threading init Only the BSP CPU was able to start its hyper-threading CPU siblings. When an AP CPU attempts this it calls start_cpu() within start_cpu(), deadlocking the system with start_cpu_lock. At the time intel_sibling_init() is run, the BSP CPU is still walking the cpu_bus linked list in lapic_cpu_init: start_other_cpus(). A sibling CPU appended at the end of this list will get started. Also fail compile with #error if SERIAL_CPU_INIT==0, as microcode updates on hyper-threading sibling CPUs must be serialized. Tested with HT-enabled P4 Xeons on dual-socket604 platform. Change-Id: I0053f58f49ed604605ce0a55e826d3e1afdc90b6 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Build-Tested: build bot (Jenkins) at Sat Mar 10 05:41:56 2012, giving +1 Reviewed-By: Rudolf Marek <r.marek(a)assembler.cz> at Sun Mar 25 20:33:24 2012, giving +2 See http://review.coreboot.org/775 for details. -gerrit

1 0

Patch merged into coreboot/master: c82896d Makefile: rename linker intermediate variable
by gerrit＠coreboot.org 25 Mar '12

25 Mar '12

the following patch was just integrated into master: commit c82896d576c16c91eab36be06743f57ea3d8bc0b Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Mar 19 19:12:49 2012 +0200 Makefile: rename linker intermediate variable Renamed CONFIG_ROMBASE to ROMSTAGE_BASE and removed it from Kconfig. Removed no-op calculation in ldscript. Change-Id: I53d39b60f07db76c8537b3133e59360687b9d4a7 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Sat Mar 24 21:36:22 2012, giving +2 Build-Tested: build bot (Jenkins) at Tue Mar 20 15:23:44 2012, giving +1 Reviewed-By: Rudolf Marek <r.marek(a)assembler.cz> at Sun Mar 25 20:23:20 2012, giving +2 See http://review.coreboot.org/802 for details. -gerrit

1 0

Patch merged into coreboot/master: 635885d gitconfig: Improve commit-msg hook
by gerrit＠coreboot.org 25 Mar '12

25 Mar '12

the following patch was just integrated into master: commit 635885de98a5d784625f2cf14b02698ab2e9d1bf Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Wed Mar 7 09:30:03 2012 +0100 gitconfig: Improve commit-msg hook There was some corner case where commit-msg failed. Update to latest upstream version. Change-Id: I822d6c3f64728de7356401465e00575ac5af8196 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Build-Tested: build bot (Jenkins) at Sat Mar 17 09:29:14 2012, giving +1 Reviewed-By: Rudolf Marek <r.marek(a)assembler.cz> at Sun Mar 25 20:20:30 2012, giving +2 See http://review.coreboot.org/798 for details. -gerrit

1 0

Patch merged into coreboot/master: 00612df Replace ramtest pattern to assist in DIMM configuration
by gerrit＠coreboot.org 25 Mar '12

25 Mar '12

the following patch was just integrated into master: commit 00612df5a95be99ea5f930d9c9cc1517ab9da23d Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Mar 17 08:09:14 2012 +0100 Replace ramtest pattern to assist in DIMM configuration This is developer's testtool. Output from a "rotate ones" -style pattern helps figure out how DIMM addresses are encoded or routed on a certain mainboard. Scattered test should cover every data and address lines on the memory bus, but is probably limited to the first bank of first DIMM. Change-Id: I533a7a873bcc434f99e7faed9dc9337d9ab64196 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> [pg: rebase] Build-Tested: build bot (Jenkins) at Sat Mar 17 09:17:03 2012, giving +1 Reviewed-By: Rudolf Marek <r.marek(a)assembler.cz> at Sun Mar 25 20:17:17 2012, giving +2 See http://review.coreboot.org/294 for details. -gerrit

1 0

← Newer
1
...
16
17
18
19
20
21
22
...
72
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot March 2012