coreboot March 2012

coreboot@coreboot.org

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718 discussions

Patch set updated for coreboot: 8c0a8fe Add 64KB romchip chip size
by Rudolf Marek 26 Mar '12

26 Mar '12

Rudolf Marek (r.marek(a)assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/809 -gerrit commit 8c0a8fe1d3e0e86e54f4fe8f6beae89e5c09a40c Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Sun Mar 25 19:19:03 2012 +0200 Add 64KB romchip chip size This is handy for bifferboard to provide same size as original bootloader. Change-Id: I179917d8c6354fa55cebdd70918a96cd299c4f3c Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> --- src/mainboard/Kconfig | 10 ++++++++++ 1 files changed, 10 insertions(+), 0 deletions(-) diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig index 5de47c3..fe70211 100644 --- a/src/mainboard/Kconfig +++ b/src/mainboard/Kconfig @@ -188,6 +188,8 @@ source "src/mainboard/via/Kconfig" source "src/mainboard/winent/Kconfig" source "src/mainboard/wyse/Kconfig" +config BOARD_ROMSIZE_KB_64 + bool config BOARD_ROMSIZE_KB_128 bool config BOARD_ROMSIZE_KB_256 @@ -208,6 +210,7 @@ config BOARD_ROMSIZE_KB_16384 # TODO: No help text possible for choice fields? choice prompt "ROM chip size" + default COREBOOT_ROMSIZE_KB_64 if BOARD_ROMSIZE_KB_64 default COREBOOT_ROMSIZE_KB_128 if BOARD_ROMSIZE_KB_128 default COREBOOT_ROMSIZE_KB_256 if BOARD_ROMSIZE_KB_256 default COREBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512 @@ -222,6 +225,11 @@ choice The build system will take care of creating a coreboot.rom file of the matching size. +config COREBOOT_ROMSIZE_KB_64 + bool "64 KB" + help + Choose this option if you have a 64 KB ROM chip. + config COREBOOT_ROMSIZE_KB_128 bool "128 KB" help @@ -267,6 +275,7 @@ endchoice # Map the config names to an integer (KB). config COREBOOT_ROMSIZE_KB int + default 64 if COREBOOT_ROMSIZE_KB_64 default 128 if COREBOOT_ROMSIZE_KB_128 default 256 if COREBOOT_ROMSIZE_KB_256 default 512 if COREBOOT_ROMSIZE_KB_512 @@ -279,6 +288,7 @@ config COREBOOT_ROMSIZE_KB # Map the config names to a hex value (bytes). config ROM_SIZE hex + default 0x10000 if COREBOOT_ROMSIZE_KB_64 default 0x20000 if COREBOOT_ROMSIZE_KB_128 default 0x40000 if COREBOOT_ROMSIZE_KB_256 default 0x80000 if COREBOOT_ROMSIZE_KB_512

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Patch set updated for coreboot: b6f0543 Add support for RDC R8610 Southbridge
by Rudolf Marek 26 Mar '12

26 Mar '12

Rudolf Marek (r.marek(a)assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/808 -gerrit commit b6f054306fac451e15796b0f8a2543cfe0da71df Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Sun Mar 25 18:16:11 2012 +0200 Add support for RDC R8610 Southbridge So far it just setups things right for Bifferboard. We may change it in the future to fit other hardware. Change-Id: I1c4ccff4e47b9cb9e31a738f038fc4f4ebe59087 Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> --- src/southbridge/Kconfig | 1 + src/southbridge/Makefile.inc | 1 + src/southbridge/rdc/Kconfig | 1 + src/southbridge/rdc/Makefile.inc | 1 + src/southbridge/rdc/r8610/Kconfig | 26 +++++++ src/southbridge/rdc/r8610/Makefile.inc | 20 ++++++ src/southbridge/rdc/r8610/bootblock.c | 29 ++++++++ src/southbridge/rdc/r8610/r8610.c | 118 ++++++++++++++++++++++++++++++++ 8 files changed, 197 insertions(+), 0 deletions(-) diff --git a/src/southbridge/Kconfig b/src/southbridge/Kconfig index 77fe385..31b7cc6 100644 --- a/src/southbridge/Kconfig +++ b/src/southbridge/Kconfig @@ -2,6 +2,7 @@ source src/southbridge/amd/Kconfig source src/southbridge/broadcom/Kconfig source src/southbridge/intel/Kconfig source src/southbridge/nvidia/Kconfig +source src/southbridge/rdc/Kconfig source src/southbridge/ricoh/Kconfig source src/southbridge/sis/Kconfig source src/southbridge/ti/Kconfig diff --git a/src/southbridge/Makefile.inc b/src/southbridge/Makefile.inc index b7e04db..130d459 100644 --- a/src/southbridge/Makefile.inc +++ b/src/southbridge/Makefile.inc @@ -2,6 +2,7 @@ subdirs-y += amd subdirs-y += broadcom subdirs-y += intel subdirs-y += nvidia +subdirs-y += rdc subdirs-y += ricoh subdirs-y += sis subdirs-y += ti diff --git a/src/southbridge/rdc/Kconfig b/src/southbridge/rdc/Kconfig new file mode 100644 index 0000000..50ef475 --- /dev/null +++ b/src/southbridge/rdc/Kconfig @@ -0,0 +1 @@ +source src/southbridge/rdc/r8610/Kconfig diff --git a/src/southbridge/rdc/Makefile.inc b/src/southbridge/rdc/Makefile.inc new file mode 100644 index 0000000..34f3efd --- /dev/null +++ b/src/southbridge/rdc/Makefile.inc @@ -0,0 +1 @@ +subdirs-$(CONFIG_SOUTHBRIDGE_RDC_R8610) += r8610 diff --git a/src/southbridge/rdc/r8610/Kconfig b/src/southbridge/rdc/r8610/Kconfig new file mode 100644 index 0000000..e9941f0 --- /dev/null +++ b/src/southbridge/rdc/r8610/Kconfig @@ -0,0 +1,26 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008-2009 coresystems GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config SOUTHBRIDGE_RDC_R8610 + bool + +config BOOTBLOCK_SOUTHBRIDGE_INIT + string + default "southbridge/rdc/r8610/bootblock.c" + depends on SOUTHBRIDGE_RDC_R8610 diff --git a/src/southbridge/rdc/r8610/Makefile.inc b/src/southbridge/rdc/r8610/Makefile.inc new file mode 100644 index 0000000..24d76a8 --- /dev/null +++ b/src/southbridge/rdc/r8610/Makefile.inc @@ -0,0 +1,20 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007, 2009 Rudolf Marek <r.marek(a)assembler.cz> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +driver-y += r8610.c diff --git a/src/southbridge/rdc/r8610/bootblock.c b/src/southbridge/rdc/r8610/bootblock.c new file mode 100644 index 0000000..ec6d271 --- /dev/null +++ b/src/southbridge/rdc/r8610/bootblock.c @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Rudolf Marek <r.marek(a)assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <device/pci_def.h> + +static void bootblock_southbridge_init(void) { + uint32_t tmp; + tmp = pci_read_config32(PCI_DEV(0,7,0), 0x40); + /* decode all flash ranges */ + pci_write_config32(PCI_DEV(0,7,0), 0x40, tmp | 0x07ff0000); +} diff --git a/src/southbridge/rdc/r8610/r8610.c b/src/southbridge/rdc/r8610/r8610.c new file mode 100644 index 0000000..6b45669 --- /dev/null +++ b/src/southbridge/rdc/r8610/r8610.c @@ -0,0 +1,118 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Rudolf Marek <r.marek(a)assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <pc80/i8259.h> +#include <stdlib.h> + +static const unsigned char enetIrqs[4] = { 10, 0, 0, 0 }; +static const unsigned char usbIrqs[4] = { 15, 14, 0, 0 }; + +static void pci_routing_fixup(struct device *dev) +{ + pci_assign_irqs(0, 0x8, enetIrqs); + pci_assign_irqs(0, 0xa, usbIrqs); +} + +static void r8610_init(struct device *dev) +{ + device_t nb_dev; + u32 tmp; + + printk(BIOS_DEBUG, "r8610 init\n"); + + /* clear DMA? */ + outb(0x4, 0x8); + outb(0x4, 0x10); + + outb(0xfc, 0x61); + + /* Set serial base */ + pci_write_config32(dev, 0x54, 0x3f8); + /* serial IRQ disable, LPC disable, COM2 goes to LPC, internal UART for COM1 */ + pci_write_config32(dev, 0x50, 0x84101012); + + /* Enable internal Port92, enable chipselect for flash */ + tmp = pci_read_config32(dev, 0x40); + pci_write_config32(dev, 0x40, tmp | 0x07FF0600); + + /* buffer strength SB pins */ + pci_write_config32(dev, 0x5c, 0x2315); + + /* EHCI 14, OHCI 15, MAC1 disable, MAC0 10, INTD 9, INTC 9, INTB 12, INTA INT10 */ + pci_write_config32(dev, 0x58, 0xdf0311b3); + + /* USB PHY control */ + nb_dev = dev_find_device(PCI_VENDOR_ID_RDC, + PCI_DEVICE_ID_RDC_R8610_NB, 0); + + tmp = pci_read_config32(nb_dev, 0xc0); + tmp |= 0x40000; + pci_write_config32(nb_dev, 0xc0, tmp); + + setup_i8259(); +} + +static void r8610_read_resources(device_t dev) +{ + struct resource *res; + + pci_dev_read_resources(dev); + + res = new_resource(dev, 1); + res->base = 0x0UL; + res->size = 0x1000UL; + res->limit = 0xffffUL; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + /* Reserve space for flash */ + res = new_resource(dev, 2); + res->base = 0xff800000; + res->size = 8*1024*1024; + res->limit = 0xffffffffUL; + res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | + IORESOURCE_ASSIGNED; +} + +static void southbridge_init(struct device *dev) +{ + r8610_init(dev); + pci_routing_fixup(dev); +} + +static struct device_operations r8610_sb_ops = { + .read_resources = r8610_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = &southbridge_init, + .scan_bus = scan_static_bus, + .enable = 0, + .ops_pci = 0, +}; + +static const struct pci_driver lpc_driver __pci_driver = { + .ops = &r8610_sb_ops, + .vendor = PCI_VENDOR_ID_RDC, + .device = PCI_DEVICE_ID_RDC_R8610_SB, +}; +

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Patch set updated for coreboot: a8fdb3b Add the support for RDC R8610 Northbridge
by Rudolf Marek 26 Mar '12

26 Mar '12

Rudolf Marek (r.marek(a)assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/807 -gerrit commit a8fdb3bed14a89b05940130bb6369664ab1cfcaf Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Sun Mar 25 18:14:02 2012 +0200 Add the support for RDC R8610 Northbridge So far the it just setups the internal resource management for coreboot and detects the memory size. Change-Id: I8506390fa6656abfa40d92b8f6ede9b91fe98680 Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> --- src/northbridge/Kconfig | 1 + src/northbridge/Makefile.inc | 1 + src/northbridge/rdc/Kconfig | 1 + src/northbridge/rdc/Makefile.inc | 2 + src/northbridge/rdc/r8610/Kconfig | 2 + src/northbridge/rdc/r8610/Makefile.inc | 21 +++++ src/northbridge/rdc/r8610/chip.h | 24 ++++++ src/northbridge/rdc/r8610/northbridge.c | 135 +++++++++++++++++++++++++++++++ 8 files changed, 187 insertions(+), 0 deletions(-) diff --git a/src/northbridge/Kconfig b/src/northbridge/Kconfig index eeedc89..b2b8abe 100644 --- a/src/northbridge/Kconfig +++ b/src/northbridge/Kconfig @@ -1,3 +1,4 @@ source src/northbridge/amd/Kconfig source src/northbridge/intel/Kconfig +source src/northbridge/rdc/Kconfig source src/northbridge/via/Kconfig diff --git a/src/northbridge/Makefile.inc b/src/northbridge/Makefile.inc index 57273cf..283ba4e 100644 --- a/src/northbridge/Makefile.inc +++ b/src/northbridge/Makefile.inc @@ -1,3 +1,4 @@ subdirs-y += amd subdirs-y += intel +subdirs-y += rdc subdirs-y += via diff --git a/src/northbridge/rdc/Kconfig b/src/northbridge/rdc/Kconfig new file mode 100644 index 0000000..73ac740 --- /dev/null +++ b/src/northbridge/rdc/Kconfig @@ -0,0 +1 @@ +source src/northbridge/rdc/r8610/Kconfig diff --git a/src/northbridge/rdc/Makefile.inc b/src/northbridge/rdc/Makefile.inc new file mode 100644 index 0000000..766fea2 --- /dev/null +++ b/src/northbridge/rdc/Makefile.inc @@ -0,0 +1,2 @@ +subdirs-$(CONFIG_NORTHBRIDGE_RDC_R8610) += r8610 + diff --git a/src/northbridge/rdc/r8610/Kconfig b/src/northbridge/rdc/r8610/Kconfig new file mode 100644 index 0000000..85461b7 --- /dev/null +++ b/src/northbridge/rdc/r8610/Kconfig @@ -0,0 +1,2 @@ +config NORTHBRIDGE_RDC_R8610 + bool diff --git a/src/northbridge/rdc/r8610/Makefile.inc b/src/northbridge/rdc/r8610/Makefile.inc new file mode 100644 index 0000000..c976967 --- /dev/null +++ b/src/northbridge/rdc/r8610/Makefile.inc @@ -0,0 +1,21 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007 Corey Osgood <corey.osgood(a)gmail.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +driver-y += northbridge.c diff --git a/src/northbridge/rdc/r8610/chip.h b/src/northbridge/rdc/r8610/chip.h new file mode 100644 index 0000000..01c8356 --- /dev/null +++ b/src/northbridge/rdc/r8610/chip.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Corey Osgood <corey.osgood(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +struct northbridge_rdc_r8610_config { +}; + +extern struct chip_operations northbridge_rdc_r8610_ops; diff --git a/src/northbridge/rdc/r8610/northbridge.c b/src/northbridge/rdc/r8610/northbridge.c new file mode 100644 index 0000000..48d830c --- /dev/null +++ b/src/northbridge/rdc/r8610/northbridge.c @@ -0,0 +1,135 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Rudolf Marek <r.marek(a)assembler.cz> + * + * Based on qemu-x86/northbridge.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include <console/console.h> +#include <arch/io.h> +#include <stdint.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <stdlib.h> +#include <string.h> +#include <bitops.h> +#include <smbios.h> +#include "chip.h" + +#if CONFIG_WRITE_HIGH_TABLES==1 +#include <cbmem.h> +#endif + +static unsigned long get_memory_size(void) +{ + device_t nb_dev; + u8 size; + + nb_dev = dev_find_device(PCI_VENDOR_ID_RDC, + PCI_DEVICE_ID_RDC_R8610_NB, 0); + size = pci_read_config8(nb_dev, 0x6d) & 0xf; + return (2 * 1024) << size; +} + +static void cpu_pci_domain_set_resources(device_t dev) +{ + u32 pci_tolm = find_pci_tolm(dev->link_list); + unsigned long tomk = 0, tolmk; + int idx; + + tomk = get_memory_size(); + printk(BIOS_DEBUG, "Detected %lu Kbytes (%lu MiB) RAM.\n", + tomk, tomk / 1024); + + /* Compute the top of Low memory */ + tolmk = pci_tolm >> 10; + if (tolmk >= tomk) { + /* The PCI hole does not overlap the memory. */ + tolmk = tomk; + } + + /* Report the memory regions. */ + idx = 10; + ram_resource(dev, idx++, 0, 640); + ram_resource(dev, idx++, 768, tolmk - 768); + +#if CONFIG_WRITE_HIGH_TABLES==1 + /* Leave some space for ACPI, PIRQ and MP tables */ + high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; + high_tables_size = HIGH_MEMORY_SIZE; +#endif + + assign_resources(dev->link_list); +} + +static void cpu_pci_domain_read_resources(struct device *dev) +{ + pci_domain_read_resources(dev); +} + +#if CONFIG_GENERATE_SMBIOS_TABLES +static int rdc_get_smbios_data16(int handle, unsigned long *current) +{ + struct smbios_type16 *t = (struct smbios_type16 *)*current; + int len = sizeof(struct smbios_type16); + + memset(t, 0, sizeof(struct smbios_type16)); + t->type = SMBIOS_PHYS_MEMORY_ARRAY; + t->handle = handle; + t->length = len - 2; + t->location = 3; /* Location: System Board */ + t->use = 3; /* System memory */ + t->memory_error_correction = 3; /* No error correction */ + t->maximum_capacity = get_memory_size(); + *current += len; + return len; +} + +static int rdc_get_smbios_data(device_t dev, int *handle, unsigned long *current) +{ + int len; + len = rdc_get_smbios_data16(*handle, current); + *handle += 1; + return len; +} +#endif +static struct device_operations pci_domain_ops = { + .read_resources = cpu_pci_domain_read_resources, + .set_resources = cpu_pci_domain_set_resources, + .enable_resources = NULL, + .init = NULL, + .scan_bus = pci_domain_scan_bus, +#if CONFIG_GENERATE_SMBIOS_TABLES + .get_smbios_data = rdc_get_smbios_data, +#endif +}; + +static void enable_dev(struct device *dev) +{ + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) { + dev->ops = &pci_domain_ops; + pci_set_method(dev); + } +} + +struct chip_operations northbridge_rdc_r8610_ops = { + CHIP_NAME("RDC R8610 Northbridge") + .enable_dev = enable_dev, +};

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Patch set updated for coreboot: e4cda7e Add RDC R8610 PCI IDs.
by Rudolf Marek 26 Mar '12

26 Mar '12

Rudolf Marek (r.marek(a)assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/806 -gerrit commit e4cda7e562ca9cd487df9775a076f401b7bf7836 Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Sun Mar 25 15:58:09 2012 +0200 Add RDC R8610 PCI IDs. Change-Id: I3f3585f15265aa1377f72ba23accf1adb08cb8ac Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> --- src/include/device/pci_ids.h | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 60399ef..a2d6884 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -1938,6 +1938,10 @@ #define PCI_VENDOR_ID_PDC 0x15e9 #define PCI_DEVICE_ID_PDC_1841 0x1841 +#define PCI_VENDOR_ID_RDC 0x17f3 +#define PCI_DEVICE_ID_RDC_R8610_NB 0x6020 +#define PCI_DEVICE_ID_RDC_R8610_SB 0x6030 + #define PCI_VENDOR_ID_ALTIMA 0x173b #define PCI_DEVICE_ID_ALTIMA_AC1000 0x03e8 #define PCI_DEVICE_ID_ALTIMA_AC9100 0x03ea

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Re: [coreboot] porting asus l1n64
by Marc Jones 26 Mar '12

26 Mar '12

Hi Julian, On Sat, Mar 24, 2012 at 6:26 AM, Julian Shulika <hercares(a)gmail.com> wrote: > Hi. Please,scomeone,add these files to coreboot project (attached archive). > I've fount that Asus L1N64 is very similar to Asus M2N-E as hardware > (mcp+ite8716f+adt7475) and pcb > So I fix m2n-e files for diffrent socket Socket_F, add select > DIMM_REGISTERED , turn on device pci e.0 on end > I can't read any information from i2c-tools > . I have the similar log from Asus M2N-E, I could continue after I replaced > memory stick to last dimm. > At this board Asus L1n64 two first dimms connect to CPU0,others - to CPU1, > I've tried all variants - nothing change. Maybe someone can explain how > these two mcp55 aree connected between them to nforce 680a. > Scheme of this board,look at attached image > > Log from serial, system turned off then > coreboot-4.0-2135-gccee625-dirty Thu Mar 22 20:45:03 EDT 2012 starting... > *sysinfo range: [000cf000,000cf730] > bsp_apicid=0x00 > > Enabling routing table for node 00 done. > Enabling UP settings > coherent_ht_finalize > done > core0 started: > started ap apicid: * AP 01started > > SBLink=01 > NC node|link=00 > busn=40 > NC node|link=01 > entering optimize_link_incoherent_ht > sysinfo->link_pair_num=0x2 > entering ht_optimize_link > pos=0xaa, unfiltered freq_cap=0x8075 > pos=0xaa, filtered freq_cap=0x75 > pos=0x52, unfiltered freq_cap=0x807f > pos=0x52, filtered freq_cap=0x7f > freq_cap1=0x75, > freq_cap2=0x7f > dev1 old_freq=0x0, freq=0x6, > needs_reset=0x1 > dev2 old_freq=0x0, freq=0x6, > needs_reset=0x1 > width_cap1=0x11, > width_cap2=0x11 > dev1 input ln_width1=0x4, > ln_width2=0x4 > dev1 input > width=0x1 > dev1 output ln_width1=0x4, > ln_width2=0x4 > dev1 input|output > width=0x11 > old dev1 input|output > width=0x11 > dev2 input|output > width=0x11 > old dev2 input|output > width=0x11 > after ht_optimize_link for link pair 0, > reset_needed=0x1 > entering > ht_optimize_link > pos=0x8a, unfiltered > freq_cap=0x8075 > pos=0x8a, filtered > freq_cap=0x75 > pos=0x52, unfiltered > freq_cap=0x807f > pos=0x52, filtered > freq_cap=0x7f > freq_cap1=0x75, > freq_cap2=0x7f > dev1 old_freq=0x0, freq=0x6, > needs_reset=0x1 > dev2 old_freq=0x0, freq=0x6, > needs_reset=0x1 > width_cap1=0x11, > width_cap2=0x11 > dev1 input ln_width1=0x4, > ln_width2=0x4 > dev1 input > width=0x1 > dev1 output ln_width1=0x4, > ln_width2=0x4 > dev1 input|output > width=0x11 > old dev1 input|output > width=0x11 > dev2 input|output > width=0x11 > old dev2 input|output > width=0x11 > after ht_optimize_link for link pair 1, > reset_needed=0x1 > after optimize_link_read_pointers_chain, > reset_needed=0x1 > mcp55_num:01 > > You should continue to develop the code before we commit it to coreboot. Also, you can read up on git, formatting patches, and sign-off procedures on the wiki. http://www.coreboot.org/Development_Guidelines http://www.coreboot.org/Git Once you are satisfied with your changes, you can push the to gerrit for review. Marc -- http://se-eng.com

1 0

New patch to review for coreboot: c81993b Makefile: rename romstage linking filenames
by Kyösti Mälkki 26 Mar '12

26 Mar '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/812 -gerrit commit c81993b926372a1bcddc3c6c1666e789868fdd5a Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Mar 26 19:03:44 2012 +0300 Makefile: rename romstage linking filenames $(obj)/location.txt -> $(obj)/romstage/base_xip.txt $(obj)/romstage/link1st.ld -> $(obj)/romstage/link_null.ld $(obj)/romstage/link2nd.ld -> $(obj)/romstage/link_xip.ld Change-Id: I15cf29b13a846729f19ecefb21819c4e66681155 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/Makefile.inc | 20 ++++++++++---------- 1 files changed, 10 insertions(+), 10 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index f131af9..00e7b86 100755 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -274,7 +274,7 @@ $(obj)/coreboot.pre: $(obj)/coreboot.romstage $(obj)/coreboot.pre1 $(CBFSTOOL) @printf " CBFS $(subst $(obj)/,,$(@))\n" cp $(obj)/coreboot.pre1 $@.tmp $(CBFSTOOL) $@.tmp add-stage $(obj)/romstage.elf \ - $(CONFIG_CBFS_PREFIX)/romstage x $(shell cat $(obj)/location.txt) + $(CONFIG_CBFS_PREFIX)/romstage x $(shell cat $(obj)/romstage/base_xip.txt) mv $@.tmp $@ ####################################################################### @@ -344,21 +344,21 @@ $(obj)/bootblock.elf: $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.o $(obj)/bootbl ####################################################################### # Build the romstage -$(obj)/romstage.bin: $$(romstage-objs) $(obj)/romstage/link1st.ld +$(obj)/romstage.bin: $$(romstage-objs) $(obj)/romstage/link_null.ld @printf " LINK $(subst $(obj)/,,$(@))\n" - $(CC) -nostdlib -nostartfiles -static -o $(obj)/romstage.elf -L$(obj) -T $(obj)/romstage/link1st.ld $(romstage-objs) + $(CC) -nostdlib -nostartfiles -static -o $(obj)/romstage.elf -L$(obj) -T $(obj)/romstage/link_null.ld $(romstage-objs) $(OBJCOPY) -O binary $(obj)/romstage.elf $@ -$(obj)/coreboot.romstage: $$(romstage-objs) $(obj)/romstage/link2nd.ld +$(obj)/coreboot.romstage: $$(romstage-objs) $(obj)/romstage/link_xip.ld @printf " LINK $(subst $(obj)/,,$(@))\n" - $(CC) -nostdlib -nostartfiles -static -o $(obj)/romstage.elf -L$(obj) -T $(obj)/romstage/link2nd.ld $(romstage-objs) + $(CC) -nostdlib -nostartfiles -static -o $(obj)/romstage.elf -L$(obj) -T $(obj)/romstage/link_xip.ld $(romstage-objs) $(NM) -n $(obj)/romstage.elf | sort > $(obj)/romstage.map $(OBJCOPY) --only-keep-debug $(obj)/romstage.elf $(obj)/romstage.debug $(OBJCOPY) --strip-debug $(obj)/romstage.elf $(OBJCOPY) --add-gnu-debuglink=$(obj)/romstage.debug $(obj)/romstage.elf $(OBJCOPY) -O binary $(obj)/romstage.elf $@ -$(obj)/romstage/link1st.ld: $$(ldscripts) $(obj)/ldoptions +$(obj)/romstage/link_null.ld: $$(ldscripts) $(obj)/ldoptions @printf " GEN $(subst $(obj)/,,$(@))\n" mkdir -p $(obj)/romstage rm -f $@ @@ -366,14 +366,14 @@ $(obj)/romstage/link1st.ld: $$(ldscripts) $(obj)/ldoptions printf '$(foreach ldscript,ldoptions $(ldscripts),INCLUDE "$(ldscript:$(obj)/%=%)"\n)' >> $@.tmp mv $@.tmp $@ -$(obj)/romstage/link2nd.ld: $(obj)/romstage/link1st.ld $(obj)/location.txt +$(obj)/romstage/link_xip.ld: $(obj)/romstage/link_null.ld $(obj)/romstage/base_xip.txt @printf " GEN $(subst $(obj)/,,$(@))\n" rm -f $@ - sed -e 's/^/ROMSTAGE_BASE = /g' -e 's/$$/;/g' $(obj)/location.txt > $@.tmp - sed -e '/ROMSTAGE_BASE/d' $(obj)/romstage/link1st.ld >> $@.tmp + sed -e 's/^/ROMSTAGE_BASE = /g' -e 's/$$/;/g' $(obj)/romstage/base_xip.txt > $@.tmp + sed -e '/ROMSTAGE_BASE/d' $(obj)/romstage/link_null.ld >> $@.tmp mv $@.tmp $@ -$(obj)/location.txt: $(obj)/coreboot.pre1 $(obj)/romstage.bin +$(obj)/romstage/base_xip.txt: $(obj)/coreboot.pre1 $(obj)/romstage.bin rm -f $@ $(CBFSTOOL) $(obj)/coreboot.pre1 locate $(obj)/romstage.bin $(CONFIG_CBFS_PREFIX)/romstage $(CONFIG_XIP_ROM_SIZE) > $@.tmp \ || { echo "The romstage is larger than XIP size. Please expand the CONFIG_XIP_ROM_SIZE" ; exit 1; }

4 3

Patch set updated for coreboot: dd90cc6 Makefile: split romstage linking to separate rules
by Kyösti Mälkki 26 Mar '12

26 Mar '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/803 -gerrit commit dd90cc60f10135aacd7dca36716d32c2226ba459 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Mar 25 17:21:21 2012 +0300 Makefile: split romstage linking to separate rules After change it is more clear how romstage is linked twice and with what scripts. Also with the change, it is easier to add some object of static size that need to be re-compiled for the 2nd link. One such object could be md5sum of executable. Change-Id: Ib34d1876071a51345c5c7319a0ed937868817fd1 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/Makefile.inc | 41 ++++++++++++++++++++++++++++------------- 1 files changed, 28 insertions(+), 13 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index fc3cd14..a437d18 100755 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -272,8 +272,7 @@ $(obj)/coreboot.pre: $(obj)/coreboot.romstage $(obj)/coreboot.pre1 $(CBFSTOOL) rm -f $@ cp $(obj)/coreboot.pre1 $@ $(CBFSTOOL) $@ add-stage $(obj)/romstage.elf \ - $(CONFIG_CBFS_PREFIX)/romstage x 0x$(shell cat $(obj)/location.txt) -#FIXME: location.txt might require an offset of header size + $(CONFIG_CBFS_PREFIX)/romstage x $(shell cat $(obj)/location.txt) ####################################################################### # Build the bootblock @@ -340,26 +339,42 @@ $(obj)/bootblock.elf: $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.o $(obj)/bootbl ####################################################################### # Build the romstage -$(obj)/coreboot.romstage: $(obj)/coreboot.pre1 $$(romstage-objs) $(obj)/romstage/ldscript.ld + +$(obj)/romstage.bin: $$(romstage-objs) $(obj)/romstage/link1st.ld + @printf " LINK $(subst $(obj)/,,$(@))\n" + $(CC) -nostdlib -nostartfiles -static -o $(obj)/romstage.elf -L$(obj) -T $(obj)/romstage/link1st.ld $(romstage-objs) + $(OBJCOPY) -O binary $(obj)/romstage.elf $@ + +$(obj)/coreboot.romstage: $$(romstage-objs) $(obj)/romstage/link2nd.ld @printf " LINK $(subst $(obj)/,,$(@))\n" - printf "ROMSTAGE_BASE = 0x0;\n" > $(obj)/location.ld - $(CC) -nostdlib -nostartfiles -static -o $(obj)/romstage.elf -L$(obj) -T $(obj)/romstage/ldscript.ld $(romstage-objs) - $(OBJCOPY) -O binary $(obj)/romstage.elf $(obj)/romstage.bin - printf "ROMSTAGE_BASE = 0x" > $(obj)/location.ld - $(CBFSTOOL) $(obj)/coreboot.pre1 locate $(obj)/romstage.bin $(CONFIG_CBFS_PREFIX)/romstage $(CONFIG_XIP_ROM_SIZE) > $(obj)/location.txt || { echo "The romstage is larger than XIP size. Please expand the CONFIG_XIP_ROM_SIZE" ; exit 1; } - cat $(obj)/location.txt >> $(obj)/location.ld - printf ';\n' >> $(obj)/location.ld - $(CC) -nostdlib -nostartfiles -static -o $(obj)/romstage.elf -L$(obj) -T $(obj)/romstage/ldscript.ld $(romstage-objs) + $(CC) -nostdlib -nostartfiles -static -o $(obj)/romstage.elf -L$(obj) -T $(obj)/romstage/link2nd.ld $(romstage-objs) $(NM) -n $(obj)/romstage.elf | sort > $(obj)/romstage.map $(OBJCOPY) --only-keep-debug $(obj)/romstage.elf $(obj)/romstage.debug $(OBJCOPY) --strip-debug $(obj)/romstage.elf $(OBJCOPY) --add-gnu-debuglink=$(obj)/romstage.debug $(obj)/romstage.elf $(OBJCOPY) -O binary $(obj)/romstage.elf $@ -$(obj)/romstage/ldscript.ld: $$(ldscripts) $(obj)/ldoptions +$(obj)/romstage/link1st.ld: $$(ldscripts) $(obj)/ldoptions @printf " GEN $(subst $(obj)/,,$(@))\n" mkdir -p $(obj)/romstage - printf '$(foreach ldscript,ldoptions location.ld $(ldscripts),INCLUDE "$(ldscript:$(obj)/%=%)"\n)' > $@ + rm -f $@ + printf "ROMSTAGE_BASE = 0x0;\n" > $@.tmp + printf '$(foreach ldscript,ldoptions $(ldscripts),INCLUDE "$(ldscript:$(obj)/%=%)"\n)' >> $@.tmp + mv $@.tmp $@ + +$(obj)/romstage/link2nd.ld: $(obj)/romstage/link1st.ld $(obj)/location.txt + @printf " GEN $(subst $(obj)/,,$(@))\n" + rm -f $@ + sed -e 's/^/ROMSTAGE_BASE = /g' -e 's/$$/;/g' $(obj)/location.txt > $@.tmp + sed -e '/ROMSTAGE_BASE/d' $(obj)/romstage/link1st.ld >> $@.tmp + mv $@.tmp $@ + +$(obj)/location.txt: $(obj)/coreboot.pre1 $(obj)/romstage.bin + rm -f $@ + $(CBFSTOOL) $(obj)/coreboot.pre1 locate $(obj)/romstage.bin $(CONFIG_CBFS_PREFIX)/romstage $(CONFIG_XIP_ROM_SIZE) > $@.tmp \ + || { echo "The romstage is larger than XIP size. Please expand the CONFIG_XIP_ROM_SIZE" ; exit 1; } + sed -i -e 's/^/0x/g' $@.tmp + mv $@.tmp $@ $(obj)/romstage/crt0.S: $$(crt0s) @printf " GEN $(subst $(obj)/,,$(@))\n"

1 0

Patch set updated for coreboot: 73eeacc Fix coreboot makefiles not to produce half baked output.
by Kyösti Mälkki 26 Mar '12

26 Mar '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/750 -gerrit commit 73eeaccdab5d28d5a7f91cec772096f21d69f152 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Mar 25 22:59:20 2012 +0300 Fix coreboot makefiles not to produce half baked output. It looks like the cbfstool utility generates the output file even when it fails to generate it properly. This causes make, if started second time in a row, after cbfstool failure, to continue beyond the point of failure (as the corrupted output file is present in the output tree, the second make invocation presumes that it is valid, as it is newer than the dependencies). For the same reason, cases where output file is generated and modified within a recipe have to use a temporary file name too. The output file should be created only when successful, in an atomic operation. There could be other places in the make system which require a similar fix, this needs to be investigated further. Change-Id: I7c17f033ee5937eb712b1a594122430cee5c9146 Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/Makefile.inc | 50 ++++++++++++++++++++++++-------------------- 1 files changed, 27 insertions(+), 23 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index a437d18..f131af9 100755 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -58,13 +58,15 @@ extract_nth=$(word $(1), $(subst |, ,$(2))) ifneq ($(CONFIG_UPDATE_IMAGE),y) prebuild-files = \ $(foreach file,$(cbfs-files), \ - $(CBFSTOOL) $@ add $(call extract_nth,1,$(file)) $(call extract_nth,2,$(file)) $(call extract_nth,3,$(file)) $(call extract_nth,4,$(file)); ) + $(CBFSTOOL) $@.tmp add $(call extract_nth,1,$(file)) \ + $(call extract_nth,2,$(file)) $(call extract_nth,3,$(file)) \ + $(call extract_nth,4,$(file)) &&) prebuilt-files = $(foreach file,$(cbfs-files), $(call extract_nth,1,$(file))) $(obj)/coreboot.pre1: $(obj)/coreboot.bootblock $$(prebuilt-files) $(CBFSTOOL) - rm -f $@ - $(CBFSTOOL) $@ create $(CONFIG_COREBOOT_ROMSIZE_KB)K $(obj)/coreboot.bootblock - $(prebuild-files) + $(CBFSTOOL) $@.tmp create $(CONFIG_COREBOOT_ROMSIZE_KB)K $(obj)/coreboot.bootblock + $(prebuild-files) true + mv $@.tmp $@ else .PHONY: $(obj)/coreboot.pre1 $(obj)/coreboot.pre1: $(CBFSTOOL) @@ -144,11 +146,12 @@ $(objutil)/options/build_opt_tbl: $(top)/util/options/build_opt_tbl.c $(top)/src $(obj)/coreboot_ram: $(obj)/coreboot_ram.o $(src)/arch/x86/coreboot_ram.ld #ldoptions @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(src)/arch/x86/coreboot_ram.ld $(obj)/coreboot_ram.o - $(NM) -n $(obj)/coreboot_ram | sort > $(obj)/coreboot_ram.map - $(OBJCOPY) --only-keep-debug $@ $(obj)/coreboot_ram.debug - $(OBJCOPY) --strip-debug $@ - $(OBJCOPY) --add-gnu-debuglink=$(obj)/coreboot_ram.debug $@ + $(CC) -nostdlib -nostartfiles -static -o $@.tmp -L$(obj) -T $(src)/arch/x86/coreboot_ram.ld $(obj)/coreboot_ram.o + $(NM) -n $@.tmp | sort > $@.map + $(OBJCOPY) --only-keep-debug $@.tmp $@.debug + $(OBJCOPY) --strip-debug $@.tmp + $(OBJCOPY) --add-gnu-debuglink=$@.debug $@.tmp + mv $@.tmp $@ $(obj)/coreboot_ram.o: $(obj)/arch/x86/lib/c_start.ramstage.o $$(driver-objs) $(obj)/coreboot.a $(LIBGCC_FILE_NAME) @printf " CC $(subst $(obj)/,,$(@))\n" @@ -166,12 +169,12 @@ ifeq ($(CONFIG_AP_CODE_IN_CAR),y) $(obj)/coreboot_ap: $(obj)/mainboard/$(MAINBOARDDIR)/ap_romstage.o @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(src)/arch/x86/init/ldscript_apc.lb $^ - $(OBJCOPY) --only-keep-debug $@ $(obj)/coreboot_ap.debug - $(OBJCOPY) --strip-debug $@ - $(OBJCOPY) --add-gnu-debuglink=$(obj)/coreboot_ap.debug $@ - $(NM) -n $(obj)/coreboot_ap | sort > $(obj)/coreboot_ap.map - + $(CC) -nostdlib -nostartfiles -static -o $@.tmp -L$(obj) -T $(src)/arch/x86/init/ldscript_apc.lb $^ + $(OBJCOPY) --only-keep-debug $@.tmp $@.debug + $(OBJCOPY) --strip-debug $@.tmp + $(OBJCOPY) --add-gnu-debuglink=$@.debug $@.tmp + $(NM) -n $@.tmp | sort > $@.map + mv $@.tmp $@ endif @@ -269,10 +272,10 @@ endif $(obj)/coreboot.pre: $(obj)/coreboot.romstage $(obj)/coreboot.pre1 $(CBFSTOOL) @printf " CBFS $(subst $(obj)/,,$(@))\n" - rm -f $@ - cp $(obj)/coreboot.pre1 $@ - $(CBFSTOOL) $@ add-stage $(obj)/romstage.elf \ + cp $(obj)/coreboot.pre1 $@.tmp + $(CBFSTOOL) $@.tmp add-stage $(obj)/romstage.elf \ $(CONFIG_CBFS_PREFIX)/romstage x $(shell cat $(obj)/location.txt) + mv $@.tmp $@ ####################################################################### # Build the bootblock @@ -331,11 +334,12 @@ $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.inc: $(src)/arch/x86/init/$(subst ",, $(obj)/bootblock.elf: $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.o $(obj)/bootblock/ldscript.ld @printf " LINK $(subst $(obj)/,,$(@))\n" - $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(obj)/bootblock/ldscript.ld $< - $(NM) -n $(obj)/bootblock.elf | sort > $(obj)/bootblock.map - $(OBJCOPY) --only-keep-debug $@ $(obj)/bootblock.debug - $(OBJCOPY) --strip-debug $@ - $(OBJCOPY) --add-gnu-debuglink=$(obj)/bootblock.debug $@ + $(CC) -nostdlib -nostartfiles -static -o $@.tmp -L$(obj) -T $(obj)/bootblock/ldscript.ld $< + $(NM) -n $@.tmp | sort > $(obj)/bootblock.map + $(OBJCOPY) --only-keep-debug $@.tmp $(obj)/bootblock.debug + $(OBJCOPY) --strip-debug $@.tmp + $(OBJCOPY) --add-gnu-debuglink=$(obj)/bootblock.debug $@.tmp + mv $@.tmp $@ ####################################################################### # Build the romstage

1 0

Patch merged into coreboot/master: e9bda83 Fix cleaning SeaBIOS from coreboot makefile
by gerrit＠coreboot.org 26 Mar '12

26 Mar '12

the following patch was just integrated into master: commit e9bda83e277bceee880e3c79701f968e07f65673 Author: Marc Jones <marc.jones(a)se-eng.com> Date: Mon Mar 19 17:32:33 2012 -0600 Fix cleaning SeaBIOS from coreboot makefile The coreboot makefile didn't pass the OUT and CC variables to seabios, so the clean didn't clean anything. Change-Id: Ieaf0c417d6e5dfb9e0a11df70b03d6313919578b Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Build-Tested: build bot (Jenkins) at Tue Mar 20 00:51:54 2012, giving +1 Reviewed-By: Marc Jones <marcj303(a)gmail.com> at Mon Mar 26 19:12:21 2012, giving +2 See http://review.coreboot.org/801 for details. -gerrit

1 0

Patch merged into coreboot/master: 8f69c9a Disable the GDB stub by default
by gerrit＠coreboot.org 26 Mar '12

26 Mar '12

the following patch was just integrated into master: commit 8f69c9a5fefe2107dffd711f94b3f2c3d81df506 Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Sun Mar 25 20:51:16 2012 +0200 Disable the GDB stub by default I would prefer to see the exception dump on serial rather than cryptic GDB protocol. Change-Id: Ib25513d33e6a31da24586fecb00adb5206bb43bd Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Sun Mar 25 21:00:57 2012, giving +2 See http://review.coreboot.org/811 for details. -gerrit

1 0

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coreboot March 2012