coreboot March 2012

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Patch set updated for coreboot: 2f99291 S3 code in vendorcode folder.
by Zheng Bao 27 Mar '12

27 Mar '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/622 -gerrit commit 2f992910ac5da6e377d25fdb4290f3c5c8fd1c24 Author: zbao <fishbaozi(a)gmail.com> Date: Fri Mar 23 11:41:20 2012 +0800 S3 code in vendorcode folder. Change the ExecuteFinalHltInstruction to assembly code. so we can make sure the code can run stackless. Change-Id: I783ced6cf7c5bc29c12a37aef29077e610d8957d Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- src/cpu/amd/agesa/family14/Makefile.inc | 1 + src/vendorcode/amd/agesa/f14/Include/gcc-intrin.h | 10 +- src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.c | 150 +-------------- src/vendorcode/amd/agesa/f14/Proc/CPU/cahaltasm.S | 204 ++++++++++++++++++++ .../amd/agesa/f14/Proc/Common/AmdS3Save.c | 2 +- .../amd/agesa/f14/Proc/Mem/Feat/S3/mfs3.c | 10 +- src/vendorcode/amd/agesa/f14/gcccar.inc | 140 ++++++++------ 7 files changed, 301 insertions(+), 216 deletions(-) diff --git a/src/cpu/amd/agesa/family14/Makefile.inc b/src/cpu/amd/agesa/family14/Makefile.inc index 774d401..b08ceeb 100644 --- a/src/cpu/amd/agesa/family14/Makefile.inc +++ b/src/cpu/amd/agesa/family14/Makefile.inc @@ -113,6 +113,7 @@ agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Gfx/GfxInitAtMidPost.c agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/cpuF14CacheDefaults.c agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/ON/mpuon3.c agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cahalt.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cahaltasm.S agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mt.c agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/ON/F14OnMicrocodePatchTables.c agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/ON/F14OnPciTables.c diff --git a/src/vendorcode/amd/agesa/f14/Include/gcc-intrin.h b/src/vendorcode/amd/agesa/f14/Include/gcc-intrin.h index 58438b9..5ce3ee3 100644 --- a/src/vendorcode/amd/agesa/f14/Include/gcc-intrin.h +++ b/src/vendorcode/amd/agesa/f14/Include/gcc-intrin.h @@ -305,7 +305,9 @@ static __inline__ __attribute__((always_inline)) unsigned long __readcr0(void) unsigned long value; __asm__ __volatile__ ( "mov %%cr0, %[value]" - : [value] "=a" (value)); + : [value] "=a" (value) + : + : "memory"); return value; } @@ -379,6 +381,7 @@ static __inline__ __attribute__((always_inline)) void __writecr0(unsigned long D "mov %%eax, %%cr0" : : "a" (Data) + : "memory" ); } @@ -508,13 +511,16 @@ static __inline__ __attribute__((always_inline)) void __debugbreak(void) __asm__ __volatile__ ("int3"); } +static __inline__ __attribute__((always_inline)) void __invd(void) +{ + __asm__ __volatile__ ("invd"); +} static __inline__ __attribute__((always_inline)) void __wbinvd(void) { __asm__ __volatile__ ("wbinvd"); } - static __inline__ __attribute__((always_inline)) void __lidt(void *Source) { __asm__ __volatile__("lidt %0" : : "m"(*(short*)Source)); diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.c index c4c3892..fa9abbf 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.c @@ -72,14 +72,7 @@ * P R O T O T Y P E S O F L O C A L F U N C T I O N S *---------------------------------------------------------------------------------------- */ - -VOID -ExecuteFinalHltInstruction ( - IN UINT32 SharedCore, - IN AP_MTRR_SETTINGS *ApMtrrSettingsList, - IN AMD_CONFIG_PARAMS *StdHeader - ); - + VOID SetIdtr ( IN IDT_BASE_LIMIT *IdtInfo, @@ -113,149 +106,16 @@ ExecuteWbinvdInstruction ( */ -//---------------------------------------------------------------------------- - -STATIC -VOID -PrimaryCoreFunctions (AP_MTRR_SETTINGS *ApMtrrSettingsList) - { - UINT64 data; - UINT32 msrno; - // Configure the MTRRs on the AP so - // when it runs remote code it will execute - // out of RAM instead of ROM. - // Disable MTRRs and turn on modification enable bit - - data = __readmsr (0xC0010010); // MTRR_SYS_CFG - data &= ~(1 << 18); // MtrrFixDramEn - data &= ~(1 << 20); // MtrrVarDramEn - data |= (1 << 19); // MtrrFixDramModEn - data |= (1 << 17); // SysUcLockEn - - - __writemsr (0xC0010010, data); - - // Set 7FFFh-00000h and 9FFFFh-80000h as WB DRAM - __writemsr (0x250, 0x1E1E1E1E1E1E1E1E); // AMD_MTRR_FIX64k_00000 - __writemsr (0x258, 0x1E1E1E1E1E1E1E1E); // AMD_MTRR_FIX16k_80000 - - // Set BFFFFh-A0000h, DFFFFh-C0000h as Uncacheable Memory-mapped IO - __writemsr (0x259, 0); // AMD_AP_MTRR_FIX16k_A0000 - __writemsr (0x268, 0); // AMD_MTRR_FIX4k_C0000 - __writemsr (0x269, 0); // AMD_MTRR_FIX4k_C8000 - __writemsr (0x26A, 0); // AMD_MTRR_FIX4k_D0000 - __writemsr (0x26B, 0); // AMD_MTRR_FIX4k_D8000 - - // Set FFFFFh-E0000h as Uncacheable Memory - for (msrno = 0x26C; msrno <= 0x26F; msrno++) - __writemsr (msrno, 0x1818181818181818); - - // If IBV provided settings for Fixed-Sized MTRRs, - // overwrite the default settings. - if ((uintptr_t) ApMtrrSettingsList != 0 && (uintptr_t) ApMtrrSettingsList != 0xFFFFFFFF) - { - int index; - for (index = 0; ApMtrrSettingsList [index].MsrAddr != CPU_LIST_TERMINAL; index++) - __writemsr (ApMtrrSettingsList [index].MsrAddr, ApMtrrSettingsList [index].MsrData); - } - - // restore variable MTTR6 and MTTR7 to default states - for (msrno = 0x20F; msrno <= 0x20C; msrno--) // decrement so that the pair is disable before the base is cleared - __writemsr (msrno, 0); - - // Enable fixed-range and variable-range MTRRs - // Set Fixed-Range Enable (FE) and MTRR Enable (E) bits - __writemsr (0x2FF, __readmsr (0x2FF) | 0xC00); - - // Enable Top-of-Memory setting - // Enable use of RdMem/WrMem bits attributes - data = __readmsr (0xC0010010); // MTRR_SYS_CFG - data |= (1 << 18); // MtrrFixDramEn - data |= (1 << 20); // MtrrVarDramEn - data &= ~(1 << 19); // MtrrFixDramModEn - __writemsr (0xC0010010, data); - } - -//---------------------------------------------------------------------------- - +/* see cahaltasm.S VOID ExecuteFinalHltInstruction ( - IN UINT32 SharedCore, + IN UINT32 HaltFlags, IN AP_MTRR_SETTINGS *ApMtrrSettingsList, IN AMD_CONFIG_PARAMS *StdHeader ) { - int abcdRegs [4]; - UINT32 cr0val; - UINT64 data; - - cr0val = __readcr0 (); - if (SharedCore & 2) - { - // set CombineCr0Cd and enable cache in CR0 - __writemsr (MSR_CU_CFG3, __readmsr (MSR_CU_CFG3) | 1ULL << 49); - __writecr0 (cr0val & ~0x60000000); - } - else - __writecr0 (cr0val | 0x60000000); - - if (SharedCore & 1) PrimaryCoreFunctions (ApMtrrSettingsList); - - // Make sure not to touch any Shared MSR from this point on - - // Restore settings that were temporarily overridden for the cache as ram phase - data = __readmsr (0xC0011022); // MSR_DC_CFG - data &= ~(1 << 4); // DC_DIS_SPEC_TLB_RLD - data &= ~(1 << 8); // DIS_CLR_WBTOL2_SMC_HIT - data &= ~(1 << 13); // DIS_HW_PF - __writemsr (0xC0011022, data); - - data = __readmsr (0xC0011021); // MSR_IC_CFG - C001_1021 - data &= ~(1 << 9); // IC_DIS_SPEC_TLB_RLD - __writemsr (0xC0011021, data); - - // AMD_DISABLE_STACK_FAMILY_HOOK - __cpuid (abcdRegs, 1); - if ((abcdRegs [0] >> 20) == 1) //-----family 10h (Hydra) only----- - { - data = __readmsr (0xC0011022); - data &= ~(1 << 4); - data &= ~(1 << 8); - data &= ~(1 << 13); - __writemsr (0xC0011022, data); - - data = __readmsr (0xC0011021); - data &= ~(1 << 14); - data &= ~(1 << 9); - __writemsr (0xC0011021, data); - - data = __readmsr (0xC001102A); - data &= ~(1 << 15); - data &= ~(1ull << 35); - __writemsr (0xC001102A, data); - } - else if ((abcdRegs [0] >> 20) == 6) //-----family 15h (Orochi) only----- - { - data = __readmsr (0xC0011020); - data &= ~(1 << 28); - __writemsr (0xC0011020, data); - - data = __readmsr (0xC0011021); - data &= ~(1 << 9); - __writemsr (0xC0011021, data); - - data = __readmsr (0xC0011022); - data &= ~(1 << 4); - data &= ~(1l << 13); - __writemsr (0xC0011022, data); - } - - for (;;) - { - _disable (); - __halt (); - } - } +} +*/ //---------------------------------------------------------------------------- diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cahaltasm.S b/src/vendorcode/amd/agesa/f14/Proc/CPU/cahaltasm.S new file mode 100644 index 0000000..509e962 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cahaltasm.S @@ -0,0 +1,204 @@ +/* + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +.include "src/vendorcode/amd/agesa/f14/gcccar.inc" + +.code32 +.align 4 +.globl ExecuteFinalHltInstruction + .type ExecuteFinalHltInstruction, @function +/* ExecuteFinalHltInstruction ( + IN UINT32 HaltFlags, + IN AP_MTRR_SETTINGS *ApMtrrSettingsList, + IN AMD_CONFIG_PARAMS *StdHeader + ) +*/ + +/* This function disables CAR. We don't care about the stack on this CPU */ +ExecuteFinalHltInstruction: +/* AMD- TODO - check these stack access are correct */ + movl 4(%esp), %esi /* HaltFlags*/ + movl 8(%esp), %edi /* ApMtrrSettingList */ + +/* Do these special steps in case if the core is part of a compute unit + * Note: The following bits are family specific flags, that gets set during build time, + * and indicates things like "family cache control methodology", etc. + * esi bit0 = 0 -> not a Primary core + * esi bit0 = 1 -> Primary core + * esi bit1 = 0 -> Cache disable + * esi bit1 = 1 -> Cache enable + */ + + bt $1, %esi /* .if (esi & 2h) */ + jz 0f + /* Set CombineCr0Cd bit */ + movl $CU_CFG3, %ecx + rdmsr + bts $(COMBINE_CR0_CD - 32), %edx + wrmsr + /* Clear the CR0.CD bit */ + movl %cr0, %eax /* Make sure cache is enabled for all APs */ + btr $CR0_CD, %eax + btr $CR0_NW, %eax + mov %eax, %cr0 /* Write back to CR0 */ + jmp 1f /* .else */ +0: + movl %cr0, %eax /* Make sure cache is disabled for all APs */ + bts $CR0_CD, %eax /* Disable cache */ + bts $CR0_NW, %eax + movl %eax, %cr0 /* Write back to CR0 */ +1: /* .endif */ + + bt $0, %esi /* .if (esi & 1h) */ + jz 2f + /* This core is a primary core and needs to do all the MTRRs, including shared MTRRs. */ + movl %edi, %esi /* Get ApMtrrSettingList */ + + /* Configure the MTRRs on the AP so + * when it runs remote code it will execute + * out of RAM instead of ROM. + */ + + /* Disable MTRRs and turn on modification enable bit */ + movl $MTRR_SYS_CFG, %ecx + rdmsr + btr $MTRR_VAR_DRAM_EN, %eax /* Disable */ + bts $MTRR_FIX_DRAM_MOD_EN, %eax /* Enable */ + btr $MTRR_FIX_DRAM_EN, %eax /* Disable */ + bts $SYS_UC_LOCK_EN, %eax + wrmsr + + /* Setup default values for Fixed-Sized MTRRs */ + /* Set 7FFFh-00000h as WB */ + movl $AMD_AP_MTRR_FIX64k_00000, %ecx + movl $0x1E1E1E1E, %eax + movl %eax, %edx + wrmsr + + /* Set 9FFFFh-80000h also as WB */ + movl $AMD_AP_MTRR_FIX16k_80000, %ecx + wrmsr + + /* Set BFFFFh-A0000h as Uncacheable Memory-mapped IO */ + movl $AMD_AP_MTRR_FIX16k_A0000, %ecx + xorl %eax, %eax + xorl %edx, %edx + wrmsr + + /* Set DFFFFh-C0000h as Uncacheable Memory-mapped IO */ + xorl %eax, %eax + xorl %edx, %edx + movl $AMD_AP_MTRR_FIX4k_C0000, %ecx + +CDLoop: + wrmsr + inc %ecx + cmp $AMD_AP_MTRR_FIX4k_D8000, %ecx + jbe CDLoop + + /* Set FFFFFh-E0000h as Uncacheable Memory */ + movl $0x18181818, %eax + movl %eax, %edx + + mov $AMD_AP_MTRR_FIX4k_E0000, %ecx + +EFLoop: + wrmsr + inc %ecx + cmp $AMD_AP_MTRR_FIX4k_F8000, %ecx + jbe EFLoop + + /* If IBV provided settings for Fixed-Sized MTRRs, + * overwrite the default settings. */ + cmp $0, %esi /*.if ((esi != 0) && (esi != 0FFFFFFFFh)) */ + jz 4f + cmp $0xFFFFFFFF, %esi + jz 4f + 5: + mov (%esi), %ecx /* (AP_MTRR_SETTINGS ptr [esi]).MsrAddr */ + /* While we are not at the end of the list */ + cmp $CPU_LIST_TERMINAL, %ecx /* .while (ecx != CPU_LIST_TERMINAL)*/ + je 4f + /* TODO - coreboot isn't checking for valid data. + * Ensure that the MSR address is valid for Fixed-Sized MTRRs */ + /*.if ( ((ecx >= AMD_AP_MTRR_FIX4k_C0000) && (ecx <= AMD_AP_MTRR_FIX4k_F8000)) || \ + (ecx == AMD_AP_MTRR_FIX64k_00000) || (ecx == AMD_AP_MTRR_FIX16k_80000 ) || \ + (ecx == AMD_AP_MTRR_FIX16k_A0000)) + */ + mov 4(%esi), %eax /* MsrData */ + mov 8(%esi), %edx /* MsrData */ + wrmsr + /* .endif */ + add $12, %esi /* sizeof (AP_MTRR_SETTINGS) */ + jmp 5b /* .endw */ + 4: /* .endif */ + + /* restore variable MTTR6 and MTTR7 to default states */ + movl $AMD_MTRR_VARIABLE_BASE6, %ecx /* clear MTRRPhysBase6 MTRRPhysMask6 */ + xor %eax, %eax /* and MTRRPhysBase7 MTRRPhysMask7 */ + xor %edx, %edx + cmp $10, %ecx /* .while (cl < 010h) */ + jge 6f + wrmsr + inc %ecx + 6: /* .endw */ + + /* Enable fixed-range and variable-range MTRRs */ + mov $AMD_MTRR_DEFTYPE, %ecx + rdmsr + bts $MTRR_DEF_TYPE_EN, %eax /* MtrrDefTypeEn */ + bts $MTRR_DEF_TYPE_FIX_EN, %eax /* MtrrDefTypeFixEn */ + wrmsr + + /* Enable Top-of-Memory setting */ + /* Enable use of RdMem/WrMem bits attributes */ + mov $MTRR_SYS_CFG, %ecx + rdmsr + bts $MTRR_VAR_DRAM_EN, %eax /* Enable */ + btr $MTRR_FIX_DRAM_MOD_EN, %eax /* Disable */ + bts $MTRR_FIX_DRAM_EN, %eax /* Enable */ + wrmsr + + bts $FLAG_IS_PRIMARY, %esi + jmp 3f /* .else ; end if primary core */ + 2: + xor %esi, %esi + 3: /* .endif*/ + + /* Make sure not to touch any Shared MSR from this point on */ + + AMD_DISABLE_STACK_FAMILY_HOOK + + xor %eax, %eax + +7: + cli + hlt + jmp 7b /* ExecuteHltInstruction */ + + .size ExecuteFinalHltInstruction, .-ExecuteFinalHltInstruction diff --git a/src/vendorcode/amd/agesa/f14/Proc/Common/AmdS3Save.c b/src/vendorcode/amd/agesa/f14/Proc/Common/AmdS3Save.c index f994c87..448d0f9 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Common/AmdS3Save.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Common/AmdS3Save.c @@ -245,7 +245,7 @@ AmdS3Save ( HeapStatus = AmdS3SaveParams->StdHeader.HeapStatus; AmdS3SaveParams->StdHeader.HeapStatus = HEAP_S3_RESUME; - AmdS3SaveParams->StdHeader.HeapBasePtr = (UINT64) HeapPtr; + AmdS3SaveParams->StdHeader.HeapBasePtr = (VOID *) HeapPtr; for (i = 0; i < S3LATE_TABLE_SIZE; i++) { if (HeapPtrs[i] != NULL) { diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/S3/mfs3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/S3/mfs3.c index df2071f..eee9804 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/S3/mfs3.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/S3/mfs3.c @@ -259,30 +259,30 @@ MemFS3GetDeviceList ( (*DeviceBlockHdrPtr)->RelativeOrMaskOffset = (UINT16) AllocHeapParams.RequestedBufferSize; // Copy device list on the stack to the heap. - BufferOffset = sizeof (DEVICE_BLOCK_HEADER) + (UINT64) AllocHeapParams.BufferPtr; + BufferOffset = sizeof (DEVICE_BLOCK_HEADER) + (UINT64) (UINT32) AllocHeapParams.BufferPtr; for (Die = 0; Die < DieCount; Die ++) { for (i = PRESELFREF; i <= POSTSELFREF; i ++) { // Copy PCI device descriptor to the heap if it exists. if (DeviceDescript[Die].PCIDevice[i].RegisterListID != 0xFFFFFFFF) { - LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Die].PCIDevice[i]), sizeof (PCI_DEVICE_DESCRIPTOR), StdHeader); + LibAmdMemCopy ((VOID *)(UINT32) BufferOffset, &(DeviceDescript[Die].PCIDevice[i]), sizeof (PCI_DEVICE_DESCRIPTOR), StdHeader); (*DeviceBlockHdrPtr)->NumDevices ++; BufferOffset += sizeof (PCI_DEVICE_DESCRIPTOR); } // Copy conditional PCI device descriptor to the heap if it exists. if (DeviceDescript[Die].CPCIDevice[i].RegisterListID != 0xFFFFFFFF) { - LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Die].CPCIDevice[i]), sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR), StdHeader); + LibAmdMemCopy ((VOID *)(UINT32) BufferOffset, &(DeviceDescript[Die].CPCIDevice[i]), sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR), StdHeader); (*DeviceBlockHdrPtr)->NumDevices ++; BufferOffset += sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR); } // Copy MSR device descriptor to the heap if it exists. if (DeviceDescript[Die].MSRDevice[i].RegisterListID != 0xFFFFFFFF) { - LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Die].MSRDevice[i]), sizeof (MSR_DEVICE_DESCRIPTOR), StdHeader); + LibAmdMemCopy ((VOID *)(UINT32) BufferOffset, &(DeviceDescript[Die].MSRDevice[i]), sizeof (MSR_DEVICE_DESCRIPTOR), StdHeader); (*DeviceBlockHdrPtr)->NumDevices ++; BufferOffset += sizeof (MSR_DEVICE_DESCRIPTOR); } // Copy conditional MSR device descriptor to the heap if it exists. if (DeviceDescript[Die].CMSRDevice[i].RegisterListID != 0xFFFFFFFF) { - LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Die].PCIDevice[i]), sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR), StdHeader); + LibAmdMemCopy ((VOID *)(UINT32) BufferOffset, &(DeviceDescript[Die].PCIDevice[i]), sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR), StdHeader); (*DeviceBlockHdrPtr)->NumDevices ++; BufferOffset += sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR); } diff --git a/src/vendorcode/amd/agesa/f14/gcccar.inc b/src/vendorcode/amd/agesa/f14/gcccar.inc index 63f3ea9..ad5a21d 100644 --- a/src/vendorcode/amd/agesa/f14/gcccar.inc +++ b/src/vendorcode/amd/agesa/f14/gcccar.inc @@ -37,69 +37,83 @@ .altmacro -BSP_STACK_BASE_ADDR = 0x30000 /* Base address for primary cores stack */ -BSP_STACK_SIZE = 0x10000 /* 64KB for BSP core */ -CORE0_STACK_BASE_ADDR = 0x80000 /* Base address for primary cores stack */ -CORE0_STACK_SIZE = 0x4000 /* 16KB for primary cores */ -CORE1_STACK_BASE_ADDR = 0x40000 /* Base address for AP cores */ -CORE1_STACK_SIZE = 0x1000 /* 4KB for each AP cores */ - -APIC_BASE_ADDRESS = 0x0000001B - APIC_BSC = 8 /* Boot Strap Core */ - -AMD_MTRR_VARIABLE_BASE0 = 0x0200 -AMD_MTRR_VARIABLE_BASE6 = 0x020C -AMD_MTRR_FIX64k_00000 = 0x0250 -AMD_MTRR_FIX16k_80000 = 0x0258 -AMD_MTRR_FIX16k_A0000 = 0x0259 -AMD_MTRR_FIX4k_C0000 = 0x0268 -AMD_MTRR_FIX4k_C8000 = 0x0269 -AMD_MTRR_FIX4k_D0000 = 0x026A -AMD_MTRR_FIX4k_D8000 = 0x026B -AMD_MTRR_FIX4k_E0000 = 0x026C -AMD_MTRR_FIX4k_E8000 = 0x026D -AMD_MTRR_FIX4k_F0000 = 0x026E -AMD_MTRR_FIX4k_F8000 = 0x026F - -AMD_MTRR_DEFTYPE = 0x02FF - WB_DRAM_TYPE = 0x1E /* MemType - memory type */ - MTRR_DEF_TYPE_EN = 11 /* MtrrDefTypeEn - variable and fixed MTRRs default enabled */ - MTRR_DEF_TYPE_FIX_EN = 10 /* MtrrDefTypeEn - fixed MTRRs default enabled */ - -HWCR = 0x0C0010015 /* Hardware Configuration */ - INVD_WBINVD = 0x04 /* INVD to WBINVD conversion */ - -IORR_BASE = 0x0C0010016 /* IO Range Regusters Base/Mask, 2 pairs */ - /* uses 16h - 19h */ -TOP_MEM = 0x0C001001A /* Top of Memory */ -TOP_MEM2 = 0x0C001001D /* Top of Memory2 */ - -LS_CFG = 0x0C0011020 /* Load-Store Configuration */ - DIS_SS = 28 /* Family 10h,12h,15h:Disable Streng Store functionality */ - DIS_STREAM_ST = 28 /* Family 14h:DisStreamSt - Disable Streaming Store functionality */ - -IC_CFG = 0x0C0011021 /* Instruction Cache Config Register */ - IC_DIS_SPEC_TLB_RLD = 9 /* Disable speculative TLB reloads */ - DIS_IND = 14 /* Family 10-14h:Disable Indirect Branch Predictor */ - DIS_I_CACHE = 14 /* Family 15h:DisICache - Disable Indirect Branch Predictor */ - -DC_CFG = 0x0C0011022 /* Data Cache Configuration */ - DC_DIS_SPEC_TLB_RLD = 4 /* Disable speculative TLB reloads */ - DIS_CLR_WBTOL2_SMC_HIT = 8 /* self modifying code check buffer bit */ - DIS_HW_PF = 13 /* Hardware prefetches bit */ - -DE_CFG = 0x0C0011029 /* Decode Configuration */ - CL_FLUSH_SERIALIZE = 23 /* Family 12h,15h: CL Flush Serialization */ - -BU_CFG2 = 0x0C001102A /* Family 10h: Bus Unit Configuration 2 */ -CU_CFG2 = 0x0C001102A /* Family 15h: Combined Unit Configuration 2 */ - F10_CL_LINES_TO_NB_DIS = 15 /* ClLinesToNbDis - allows WP code to be cached in L2 */ - IC_DIS_SPEC_TLB_WR = 35 /* IcDisSpecTlbWr - ITLB speculative writes */ - -CU_CFG3 = 0x0C001102B /* Combined Unit Configuration 3 */ - COMBINE_CR0_CD = 49 /* Combine CR0.CD for both cores of a compute unit */ - - +BSP_STACK_BASE_ADDR = 0x30000 /* Base address for primary cores stack */ +BSP_STACK_SIZE = 0x10000 /* 64KB for BSP core */ +CORE0_STACK_BASE_ADDR = 0x80000 /* Base address for primary cores stack */ +CORE0_STACK_SIZE = 0x4000 /* 16KB for primary cores */ +CORE1_STACK_BASE_ADDR = 0x40000 /* Base address for AP cores */ +CORE1_STACK_SIZE = 0x1000 /* 4KB for each AP cores */ + +APIC_BASE_ADDRESS = 0x0000001B + APIC_BSC = 8 /* Boot Strap Core */ + +AMD_MTRR_VARIABLE_BASE0 = 0x0200 +AMD_MTRR_VARIABLE_BASE6 = 0x020C +AMD_MTRR_FIX64k_00000 = 0x0250 +AMD_MTRR_FIX16k_80000 = 0x0258 +AMD_MTRR_FIX16k_A0000 = 0x0259 +AMD_MTRR_FIX4k_C0000 = 0x0268 +AMD_MTRR_FIX4k_C8000 = 0x0269 +AMD_MTRR_FIX4k_D0000 = 0x026A +AMD_MTRR_FIX4k_D8000 = 0x026B +AMD_MTRR_FIX4k_E0000 = 0x026C +AMD_MTRR_FIX4k_E8000 = 0x026D +AMD_MTRR_FIX4k_F0000 = 0x026E +AMD_MTRR_FIX4k_F8000 = 0x026F + +/* Reproduced from AGESA.h */ +AMD_AP_MTRR_FIX64k_00000 = 0x00000250 +AMD_AP_MTRR_FIX16k_80000 = 0x00000258 +AMD_AP_MTRR_FIX16k_A0000 = 0x00000259 +AMD_AP_MTRR_FIX4k_C0000 = 0x00000268 +AMD_AP_MTRR_FIX4k_C8000 = 0x00000269 +AMD_AP_MTRR_FIX4k_D0000 = 0x0000026A +AMD_AP_MTRR_FIX4k_D8000 = 0x0000026B +AMD_AP_MTRR_FIX4k_E0000 = 0x0000026C +AMD_AP_MTRR_FIX4k_E8000 = 0x0000026D +AMD_AP_MTRR_FIX4k_F0000 = 0x0000026E +AMD_AP_MTRR_FIX4k_F8000 = 0x0000026F +CPU_LIST_TERMINAL = 0xFFFFFFFF + +AMD_MTRR_DEFTYPE = 0x02FF + WB_DRAM_TYPE = 0x1E /* MemType - memory type */ + MTRR_DEF_TYPE_EN = 11 /* MtrrDefTypeEn - variable and fixed MTRRs default enabled */ + MTRR_DEF_TYPE_FIX_EN = 10 /* MtrrDefTypeEn - fixed MTRRs default enabled */ + +HWCR = 0x0C0010015 /* Hardware Configuration */ + INVD_WBINVD = 0x04 /* INVD to WBINVD conversion */ + +IORR_BASE = 0x0C0010016 /* IO Range Regusters Base/Mask, 2 pairs */ + /* uses 16h - 19h */ +TOP_MEM = 0x0C001001A /* Top of Memory */ +TOP_MEM2 = 0x0C001001D /* Top of Memory2 */ + +LS_CFG = 0x0C0011020 /* Load-Store Configuration */ + DIS_SS = 28 /* Family 10h,12h,15h:Disable Streng Store functionality */ + DIS_STREAM_ST = 28 /* Family 14h:DisStreamSt - Disable Streaming Store functionality */ + +IC_CFG = 0x0C0011021 /* Instruction Cache Config Register */ + IC_DIS_SPEC_TLB_RLD = 9 /* Disable speculative TLB reloads */ + DIS_IND = 14 /* Family 10-14h:Disable Indirect Branch Predictor */ + DIS_I_CACHE = 14 /* Family 15h:DisICache - Disable Indirect Branch Predictor */ + +DC_CFG = 0x0C0011022 /* Data Cache Configuration */ + DC_DIS_SPEC_TLB_RLD = 4 /* Disable speculative TLB reloads */ + DIS_CLR_WBTOL2_SMC_HIT = 8 /* self modifying code check buffer bit */ + DIS_HW_PF = 13 /* Hardware prefetches bit */ + +DE_CFG = 0x0C0011029 /* Decode Configuration */ + CL_FLUSH_SERIALIZE = 23 /* Family 12h,15h: CL Flush Serialization */ + +BU_CFG2 = 0x0C001102A /* Family 10h: Bus Unit Configuration 2 */ +CU_CFG2 = 0x0C001102A /* Family 15h: Combined Unit Configuration 2 */ + F10_CL_LINES_TO_NB_DIS = 15 /* ClLinesToNbDis - allows WP code to be cached in L2 */ + IC_DIS_SPEC_TLB_WR = 35 /* IcDisSpecTlbWr - ITLB speculative writes */ + +CU_CFG3 = 0x0C001102B /* Combined Unit Configuration 3 */ + COMBINE_CR0_CD = 49 /* Combine CR0.CD for both cores of a compute unit */ + + CR0_PE = 1 # Protection Enable CR0_NW = 29 # Not Write-through CR0_CD = 30 # Cache Disable

1 0

Patch set updated for coreboot: 725a62c Add faster, architecture dependent memcpy()
by Zheng Bao 27 Mar '12

27 Mar '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/736 -gerrit commit 725a62c002dbcd8dd59c435859291b8f187b5e41 Author: zbao <fishbaozi(a)gmail.com> Date: Fri Mar 23 11:33:14 2012 +0800 Add faster, architecture dependent memcpy() Change-Id: I38d15f3f1ec65f0cb7974d2dd4ae6356433bddd8 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> Reviewed-by: Duncan Laurie <dlaurie(a)google.com> --- src/arch/x86/Kconfig | 4 ++++ src/arch/x86/lib/Makefile.inc | 4 ++++ src/arch/x86/lib/memcpy.c | 13 +++++++++++++ src/lib/Makefile.inc | 9 ++++++++- 4 files changed, 29 insertions(+), 1 deletions(-) diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 314646f..5ee7c4a 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -76,6 +76,10 @@ config CMOS_DEFAULT_FILE config BOOTBLOCK_SOUTHBRIDGE_INIT string +config HAVE_ARCH_MEMCPY + bool + default y + config BIG_ENDIAN bool default n diff --git a/src/arch/x86/lib/Makefile.inc b/src/arch/x86/lib/Makefile.inc index 3388a9d..f99e429 100644 --- a/src/arch/x86/lib/Makefile.inc +++ b/src/arch/x86/lib/Makefile.inc @@ -8,8 +8,12 @@ ramstage-$(CONFIG_MMCONF_SUPPORT) += pci_ops_mmconf.c ramstage-y += pci_ops_auto.c ramstage-y += exception.c ramstage-$(CONFIG_IOAPIC) += ioapic.c +ramstage-y += memcpy.c romstage-y += romstage_console.c romstage-y += cbfs_and_run.c +romstage-y += memcpy.c + +smm-y += memcpy.c $(obj)/arch/x86/lib/console.ramstage.o :: $(obj)/build.h diff --git a/src/arch/x86/lib/memcpy.c b/src/arch/x86/lib/memcpy.c new file mode 100644 index 0000000..de21092 --- /dev/null +++ b/src/arch/x86/lib/memcpy.c @@ -0,0 +1,13 @@ +#include <string.h> + +void *memcpy(void *__restrict __dest, + __const void *__restrict __src, size_t __n) +{ + asm("cld\n" + "rep\n" + "movsb" + : /* no input (?) */ + :"S"(__src), "D"(__dest), "c"(__n) + ); + return __dest; +} diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index e0e5e75..8c3401d 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -2,7 +2,9 @@ romstage-y += memset.c romstage-y += memchr.c +ifneq ($(CONFIG_HAVE_ARCH_MEMCPY),y) romstage-y += memcpy.c +endif romstage-y += memcmp.c romstage-y += cbfs.c romstage-y += lzma.c @@ -17,7 +19,9 @@ romstage-$(CONFIG_USBDEBUG) += usbdebug.c ramstage-y += memset.c ramstage-y += memchr.c +ifneq ($(CONFIG_HAVE_ARCH_MEMCPY),y) ramstage-y += memcpy.c +endif ramstage-y += memcmp.c ramstage-y += memmove.c ramstage-y += malloc.c @@ -39,7 +43,10 @@ ramstage-$(CONFIG_TRACE) += trace.c driver-$(CONFIG_CONSOLE_NE2K) += ne2k.c -smm-y += memcpy.c cbfs.c memset.c memcmp.c +ifneq ($(CONFIG_HAVE_ARCH_MEMCPY),y) +smm-y += memcpy.c +endif +smm-y += cbfs.c memset.c memcmp.c smm-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c smm-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c smm-$(CONFIG_USBDEBUG) += usbdebug.c

1 0

Patch set updated for coreboot: 1e2892a S3 code in the mainboard.
by Zheng Bao 27 Mar '12

27 Mar '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/624 -gerrit commit 1e2892a899e2f83f7f4068168c77d6fb3e98e10c Author: zbao <fishbaozi(a)gmail.com> Date: Tue Mar 27 19:00:41 2012 +0800 S3 code in the mainboard. Persimmon is the demo board. Tested by Linux and Windows 7. Change-Id: I5ded942b51e63ebeb08ace0b202b4ed239b0c14c Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- src/mainboard/amd/persimmon/BiosCallOuts.c | 17 +- src/mainboard/amd/persimmon/BiosCallOuts.h | 4 +- src/mainboard/amd/persimmon/Kconfig | 1 + src/mainboard/amd/persimmon/PlatformGnbPcie.c | 2 +- .../amd/persimmon/PlatformGnbPcieComplex.h | 1 + src/mainboard/amd/persimmon/agesawrapper.c | 173 +++++++++++++++++++- src/mainboard/amd/persimmon/agesawrapper.h | 5 + src/mainboard/amd/persimmon/buildOpts.c | 6 +- src/mainboard/amd/persimmon/get_bus_conf.c | 21 ++- src/mainboard/amd/persimmon/mainboard.c | 16 ++- src/mainboard/amd/persimmon/romstage.c | 90 ++++++++-- 11 files changed, 299 insertions(+), 37 deletions(-) diff --git a/src/mainboard/amd/persimmon/BiosCallOuts.c b/src/mainboard/amd/persimmon/BiosCallOuts.c index c8379ff..98f9e3e 100644 --- a/src/mainboard/amd/persimmon/BiosCallOuts.c +++ b/src/mainboard/amd/persimmon/BiosCallOuts.c @@ -115,8 +115,10 @@ AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AllocParams->BufferPointer = NULL; AvailableHeapSize = BIOS_HEAP_SIZE - sizeof (BIOS_HEAP_MANAGER); - BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS; - BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS; + BiosHeapBaseAddr = (UINT8 *) GetHeapBase(&(AllocParams->StdHeader)); + BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BiosHeapBaseAddr; + + printk(BIOS_SPEW, "%s BiosHeapBaseAddr: %x\n", __func__, (u32) BiosHeapBaseAddr); if (BiosHeapBasePtr->StartOfAllocatedNodes == 0) { /* First allocation */ @@ -237,9 +239,6 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) BIOS_HEAP_MANAGER *BiosHeapBasePtr; AGESA_BUFFER_PARAMS *AllocParams; - BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS; - BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS; - AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr; /* Find target node to deallocate in list of allocated nodes. @@ -247,6 +246,10 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) */ AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); + BiosHeapBaseAddr = (UINT8 *) GetHeapBase(&(AllocParams->StdHeader)); + BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BiosHeapBaseAddr; + + PrevNodeOffset = AllocNodeOffset; while (AllocNodePtr->BufferHandle != AllocParams->BufferHandle) { @@ -348,8 +351,8 @@ AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr; - BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS; - BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS; + BiosHeapBaseAddr = (UINT8 *) GetHeapBase(&(AllocParams->StdHeader)); + BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BiosHeapBaseAddr; AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); diff --git a/src/mainboard/amd/persimmon/BiosCallOuts.h b/src/mainboard/amd/persimmon/BiosCallOuts.h index d9e4497..071c73c 100644 --- a/src/mainboard/amd/persimmon/BiosCallOuts.h +++ b/src/mainboard/amd/persimmon/BiosCallOuts.h @@ -23,8 +23,8 @@ #include "Porting.h" #include "AGESA.h" -#define BIOS_HEAP_START_ADDRESS 0x00010000 -#define BIOS_HEAP_SIZE 0x20000 /* 64MB */ +#define BIOS_HEAP_SIZE 0x20000 +#define BSP_STACK_BASE_ADDR 0x30000 typedef struct _BIOS_HEAP_MANAGER { //UINT32 AvailableSize; diff --git a/src/mainboard/amd/persimmon/Kconfig b/src/mainboard/amd/persimmon/Kconfig index 9212e20..27e27a5 100644 --- a/src/mainboard/amd/persimmon/Kconfig +++ b/src/mainboard/amd/persimmon/Kconfig @@ -33,6 +33,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select HAVE_MAINBOARD_RESOURCES + select HAVE_ACPI_RESUME select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID diff --git a/src/mainboard/amd/persimmon/PlatformGnbPcie.c b/src/mainboard/amd/persimmon/PlatformGnbPcie.c index 5e37f51..bdfcb66 100644 --- a/src/mainboard/amd/persimmon/PlatformGnbPcie.c +++ b/src/mainboard/amd/persimmon/PlatformGnbPcie.c @@ -23,6 +23,7 @@ #include "heapManager.h" #include "PlatformGnbPcieComplex.h" #include "Filecode.h" +#include "BiosCallOuts.h" #define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE @@ -165,4 +166,3 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; InitEarly->GnbConfig.PsppPolicy = 0; } - diff --git a/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h b/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h index b50cb1a..a49be62 100644 --- a/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h +++ b/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h @@ -23,6 +23,7 @@ #include "Porting.h" #include "AGESA.h" #include "amdlib.h" +#include <cpu/amd/agesa/s3_resume.h> //GNB GPP Port4 #define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable diff --git a/src/mainboard/amd/persimmon/agesawrapper.c b/src/mainboard/amd/persimmon/agesawrapper.c index 6e9997f..53ca04c 100644 --- a/src/mainboard/amd/persimmon/agesawrapper.c +++ b/src/mainboard/amd/persimmon/agesawrapper.c @@ -33,10 +33,12 @@ #include "cpuLateInit.h" #include "Dispatcher.h" #include "cpuCacheInit.h" +#include "heapManager.h" #include "amdlib.h" #include "PlatformGnbPcieComplex.h" #include "Filecode.h" #include <arch/io.h> +#include <cpu/amd/agesa/s3_resume.h> #define FILECODE UNASSIGNED_FILE_FILECODE @@ -243,6 +245,35 @@ agesawrapper_amdinitearly ( return (UINT32)status; } + +UINT32 GetHeapBase( + AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT64 MsrReg; + UINT32 sys_mem, uma_base, uma_size; + + /* TOP_MEM: the top of DRAM below 4G */ + LibAmdMsrRead(TOP_MEM, &MsrReg, StdHeader); + + /* refer to UMA Size Consideration in Family14h BKDG. */ + sys_mem = (UINT32)(MsrReg & 0xFFFFFFFFUL) + 0x1000000; // Ignore 16MB allocated for C6 when finding UMA size, refer MemNGetUmaSizeON() + if ((MsrReg & 0x0000000F00000000) || (sys_mem >= 0x80000000)) { + uma_size = 0x18000000; /* >= 2G memory, 384M recommended UMA */ + } + else { + if (sys_mem >= 0x40000000) { + uma_size = 0x10000000; /* >= 1G memory, 256M recommended UMA */ + } + else { + uma_size = 0x4000000; /* <1G memory, 64M recommended UMA */ + } + } + + uma_base = (UINT32)(MsrReg & 0xFFFFFFFFUL) - uma_size ; /* TOP_MEM1 */ + return uma_base - BIOS_HEAP_SIZE; +} + UINT32 agesawrapper_amdinitpost ( VOID @@ -272,7 +303,7 @@ agesawrapper_amdinitpost ( AmdReleaseStruct (&AmdParamStruct); /* Initialize heap space */ - BiosManagerPtr = (BIOS_HEAP_MANAGER *)BIOS_HEAP_START_ADDRESS; + BiosManagerPtr = (BIOS_HEAP_MANAGER *)GetHeapBase(&AmdParamStruct.StdHeader); HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof (BIOS_HEAP_MANAGER)); for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++) { @@ -496,6 +527,146 @@ agesawrapper_amdinitlate ( return (UINT32)Status; } +#if CONFIG_HAVE_ACPI_RESUME == 1 +UINT32 +agesawrapper_amdinitresume ( + VOID + ) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_RESUME_PARAMS *AmdResumeParamsPtr; + S3_DATA_TYPE S3DataType; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME; + AmdParamStruct.AllocationMethod = PreMemHeap; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct (&AmdParamStruct); + + AmdResumeParamsPtr = (AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr; + + AmdResumeParamsPtr->S3DataBlock.NvStorageSize = 0; + AmdResumeParamsPtr->S3DataBlock.VolatileStorageSize = 0; + S3DataType = S3DataTypeNonVolatile; + + OemAgesaGetS3Info (S3DataType, + (u32 *) &AmdResumeParamsPtr->S3DataBlock.NvStorageSize, + (void **) &AmdResumeParamsPtr->S3DataBlock.NvStorage); + + status = AmdInitResume ((AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr); + + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AmdReleaseStruct (&AmdParamStruct); + + return (UINT32)status; +} + +UINT32 +agesawrapper_amds3laterestore ( + VOID + ) +{ + AGESA_STATUS Status; + AMD_INTERFACE_PARAMS AmdInterfaceParams; + AMD_S3LATE_PARAMS AmdS3LateParams; + AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; + S3_DATA_TYPE S3DataType; + + LibAmdMemFill (&AmdS3LateParams, + 0, + sizeof (AMD_S3LATE_PARAMS), + &(AmdS3LateParams.StdHeader)); + AmdInterfaceParams.StdHeader.ImageBasePtr = 0; + AmdInterfaceParams.AllocationMethod = ByHost; + AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE; + AmdInterfaceParams.NewStructPtr = &AmdS3LateParams; + AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdS3LateParamsPtr = &AmdS3LateParams; + AmdInterfaceParams.NewStructSize = sizeof (AMD_S3LATE_PARAMS); + + AmdCreateStruct (&AmdInterfaceParams); + + AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = 0; + S3DataType = S3DataTypeVolatile; + + OemAgesaGetS3Info (S3DataType, + (u32 *) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize, + (void **) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorage); + + Status = AmdS3LateRestore (AmdS3LateParamsPtr); + if (Status != AGESA_SUCCESS) { + agesawrapper_amdreadeventlog(); + ASSERT(Status == AGESA_SUCCESS); + } + + return (UINT32)Status; +} + +UINT32 +agesawrapper_amdS3Save ( + VOID + ) +{ + AGESA_STATUS Status; + AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr; + AMD_INTERFACE_PARAMS AmdInterfaceParams; + S3_DATA_TYPE S3DataType; + + LibAmdMemFill (&AmdInterfaceParams, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdInterfaceParams.StdHeader)); + + AmdInterfaceParams.StdHeader.ImageBasePtr = 0; + AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; + AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdInterfaceParams.AllocationMethod = PostMemDram; + AmdInterfaceParams.AgesaFunctionName = AMD_S3_SAVE; + AmdInterfaceParams.StdHeader.AltImageBasePtr = 0; + AmdInterfaceParams.StdHeader.Func = 0; + AmdCreateStruct(&AmdInterfaceParams); + + AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *)AmdInterfaceParams.NewStructPtr; + AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader; + + Status = AmdS3Save (AmdS3SaveParamsPtr); + if (Status != AGESA_SUCCESS) { + agesawrapper_amdreadeventlog(); + ASSERT(Status == AGESA_SUCCESS); + } + + S3DataType = S3DataTypeNonVolatile; + + Status = OemAgesaSaveS3Info ( + S3DataType, + AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, + AmdS3SaveParamsPtr->S3DataBlock.NvStorage); + + if (AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize != 0) { + S3DataType = S3DataTypeVolatile; + + Status = OemAgesaSaveS3Info ( + S3DataType, + AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, + AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage + ); + } + + OemAgesaSaveMtrr(); + AmdReleaseStruct (&AmdInterfaceParams); + + return (UINT32)Status; +} +#endif + UINT32 agesawrapper_amdlaterunaptask ( UINT32 Func, diff --git a/src/mainboard/amd/persimmon/agesawrapper.h b/src/mainboard/amd/persimmon/agesawrapper.h index 7bed570..7babd58 100644 --- a/src/mainboard/amd/persimmon/agesawrapper.h +++ b/src/mainboard/amd/persimmon/agesawrapper.h @@ -84,7 +84,12 @@ UINT32 agesawrapper_amdreadeventlog (void); UINT32 agesawrapper_amdinitcpuio (void); UINT32 agesawrapper_amdinitmmio (void); +UINT32 agesawrapper_amdinitresume (void); +UINT32 agesawrapper_amdS3Save (void); +UINT32 agesawrapper_amds3laterestore (void); UINT32 agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, VOID *ConfigPtr); void *agesawrapper_getlateinitptr (int pick); +UINT32 GetHeapBase(AMD_CONFIG_PARAMS *StdHeader); + #endif diff --git a/src/mainboard/amd/persimmon/buildOpts.c b/src/mainboard/amd/persimmon/buildOpts.c index 3e5b14e..389e1d4 100644 --- a/src/mainboard/amd/persimmon/buildOpts.c +++ b/src/mainboard/amd/persimmon/buildOpts.c @@ -120,8 +120,8 @@ #define AGESA_ENTRY_INIT_LATE TRUE #define AGESA_ENTRY_INIT_S3SAVE TRUE #define AGESA_ENTRY_INIT_RESUME TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE FALSE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE +#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE +#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE #define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER @@ -169,7 +169,7 @@ //#define BLDCFG_USE_HT_ASSIST TRUE //#define BLDCFG_USE_ATM_MODE TRUE //#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm -#define BLDCFG_S3_LATE_RESTORE FALSE +#define BLDCFG_S3_LATE_RESTORE TRUE //#define BLDCFG_USE_32_BYTE_REFRESH FALSE //#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY FALSE //#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance diff --git a/src/mainboard/amd/persimmon/get_bus_conf.c b/src/mainboard/amd/persimmon/get_bus_conf.c index 0142762..4c094ae 100644 --- a/src/mainboard/amd/persimmon/get_bus_conf.c +++ b/src/mainboard/amd/persimmon/get_bus_conf.c @@ -51,6 +51,9 @@ u32 sbdn_sb800; static u32 get_bus_conf_done = 0; +#if CONFIG_HAVE_ACPI_RESUME == 1 +extern u8 acpi_slp_type; +#endif void get_bus_conf(void) { @@ -80,11 +83,20 @@ void get_bus_conf(void) * of each of the write functions called prior to the ACPI write functions, so this * becomes the best place for this call. */ +#if CONFIG_HAVE_ACPI_RESUME == 1 + if (acpi_slp_type != 3) { + status = agesawrapper_amdinitlate(); + if(status) + printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); + status = agesawrapper_amdS3Save(); + if(status) + printk(BIOS_DEBUG, "agesawrapper_amds3save failed: %x \n", status); + } +#else status = agesawrapper_amdinitlate(); - if(status) { + if(status) printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); - } - +#endif sbdn_sb800 = 0; for (i = 0; i < 3; i++) { @@ -124,7 +136,8 @@ void get_bus_conf(void) for (j = bus_sb800[2]; j < bus_isa; j++) bus_type[j] = 1; - /* I/O APICs: APIC ID Version State Address */ + + /* I/O APICs: APIC ID Version State Address */ bus_isa = 10; apicid_base = CONFIG_MAX_CPUS; apicid_sb800 = apicid_base; diff --git a/src/mainboard/amd/persimmon/mainboard.c b/src/mainboard/amd/persimmon/mainboard.c index 3b181a1..9a8428e 100644 --- a/src/mainboard/amd/persimmon/mainboard.c +++ b/src/mainboard/amd/persimmon/mainboard.c @@ -23,10 +23,13 @@ #include <arch/io.h> #include <boot/tables.h> #include <cpu/x86/msr.h> -#include <cpu/amd/mtrr.h> #include <device/pci_def.h> -//#include <southbridge/amd/sb800/sb800.h> +#include <southbridge/amd/sb800/sb800.h> +#include <arch/acpi.h> #include "chip.h" +#include "BiosCallOuts.h" +#include <cpu/amd/agesa/s3_resume.h> +#include <cpu/amd/mtrr.h> void set_pcie_reset(void); void set_pcie_dereset(void); @@ -56,6 +59,14 @@ static void persimmon_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); +/* + * The mainboard is the first place that we get control in ramstage. Check + * for S3 resume and call the approriate AGESA/CIMx resume functions. + */ +#if CONFIG_HAVE_ACPI_RESUME == 1 + acpi_slp_type = acpi_get_sleep_type(); +#endif + #if (CONFIG_GFXUMA == 1) msr_t msr, msr2; uint32_t sys_mem; @@ -110,6 +121,7 @@ int add_mainboard_resources(struct lb_memory *mem) #endif return 0; } + struct chip_operations mainboard_ops = { CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard") .enable_dev = persimmon_enable, diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c index dfb1aca..f52b447 100644 --- a/src/mainboard/amd/persimmon/romstage.c +++ b/src/mainboard/amd/persimmon/romstage.c @@ -35,9 +35,14 @@ #include "cpu/x86/lapic/boot_cpu.c" #include "pc80/i8254.c" #include "pc80/i8259.c" +#include <cpu/x86/cache.h> #include "sb_cimx.h" #include "SBPLATFORM.h" +#include "cbmem.h" +#include "cpu/amd/mtrr.h" +#include "cpu/amd/agesa/s3_resume.h" +void disable_cache_as_ram(void); /* cache_as_ram.inc */ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); #define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1) @@ -46,6 +51,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; +#if CONFIG_HAVE_ACPI_RESUME == 1 + void *resume_backup_memory; +#endif + /* * All cores: allow caching of flash chip code and data * (there are no cache-as-ram reliability concerns with family 14h) @@ -98,28 +107,75 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) else printk(BIOS_DEBUG, "passed.\n"); - post_code(0x40); - printk(BIOS_DEBUG, "agesawrapper_amdinitpost "); - val = agesawrapper_amdinitpost (); - if (val) - printk(BIOS_DEBUG, "error level: %x \n", val); - else - printk(BIOS_DEBUG, "passed.\n"); - - post_code(0x41); - printk(BIOS_DEBUG, "agesawrapper_amdinitenv "); - val = agesawrapper_amdinitenv (); - if (val) - printk(BIOS_DEBUG, "error level: %x \n", val); - else - printk(BIOS_DEBUG, "passed.\n"); +#if CONFIG_HAVE_ACPI_RESUME == 1 + if (!acpi_is_wakeup_early()) { /* Check for S3 resume */ +#endif + post_code(0x40); + printk(BIOS_DEBUG, "agesawrapper_amdinitpost "); + val = agesawrapper_amdinitpost (); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); + + post_code(0x42); + printk(BIOS_DEBUG, "agesawrapper_amdinitenv "); + val = agesawrapper_amdinitenv (); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); + +#if CONFIG_HAVE_ACPI_RESUME == 1 + } else { /* S3 detect */ + printk(BIOS_INFO, "S3 detected\n"); + + post_code(0x60); + printk(BIOS_DEBUG, "agesawrapper_amdinitresume "); + val = agesawrapper_amdinitresume(); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); + + printk(BIOS_DEBUG, "agesawrapper_amds3laterestore "); + val = agesawrapper_amds3laterestore (); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); + + post_code(0x61); + printk(BIOS_DEBUG, "Find resume memory location\n"); + resume_backup_memory = backup_resume(); + + post_code(0x62); + printk(BIOS_DEBUG, "Move CAR stack.\n"); + move_stack_high_mem(resume_backup_memory + HIGH_MEMORY_SAVE); + printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE)); + + post_code(0x63); + disable_cache_as_ram(); + printk(BIOS_DEBUG, "CAR disabled.\n"); + set_resume_cache(); + + /* + * Copy the system memory that is in the ramstage area to the + * reserved area. + */ + if (resume_backup_memory) + memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE); + + printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n"); + } +#endif /* Initialize i8259 pic */ - post_code(0x41); + post_code(0x43); setup_i8259 (); /* Initialize i8254 timers */ - post_code(0x42); + post_code(0x44); setup_i8254 (); post_code(0x50);

1 0

Patch set updated for coreboot: 0171b7b S3 code whitespaces changes.
by Zheng Bao 27 Mar '12

27 Mar '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/625 -gerrit commit 0171b7b0b68cf4b5a1ea817d143b0094111e4f9e Author: zbao <fishbaozi(a)gmail.com> Date: Tue Mar 27 19:01:04 2012 +0800 S3 code whitespaces changes. some blank changing is integrated into the previous patches, which hold the unsplitted diff hunk. Change-Id: If9e5066927c5e27fee7ac8422dbfbf2cbeac7df5 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- src/cpu/amd/agesa/family14/model_14_init.c | 40 ++++---- src/mainboard/amd/persimmon/BiosCallOuts.c | 111 ++++++++++--------- src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.c | 22 ++-- src/vendorcode/amd/agesa/f14/gcccar.inc | 136 ++++++++++++------------ 4 files changed, 158 insertions(+), 151 deletions(-) diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c index 4fd2b85..d90695a 100644 --- a/src/cpu/amd/agesa/family14/model_14_init.c +++ b/src/cpu/amd/agesa/family14/model_14_init.c @@ -39,22 +39,22 @@ msr_t rdmsr_amd(u32 index) { - msr_t result; - __asm__ __volatile__( - "rdmsr" - :"=a"(result.lo), "=d"(result.hi) - :"c"(index), "D"(0x9c5a203a) - ); - return result; + msr_t result; + __asm__ __volatile__( + "rdmsr" + :"=a"(result.lo), "=d"(result.hi) + :"c"(index), "D"(0x9c5a203a) + ); + return result; } void wrmsr_amd(u32 index, msr_t msr) { - __asm__ __volatile__( - "wrmsr" - : /* No outputs */ - :"c"(index), "a"(msr.lo), "d"(msr.hi), "D"(0x9c5a203a) - ); + __asm__ __volatile__( + "wrmsr" + : /* No outputs */ + :"c"(index), "a"(msr.lo), "d"(msr.hi), "D"(0x9c5a203a) + ); } static void model_14_init(device_t dev) @@ -140,18 +140,18 @@ static void model_14_init(device_t dev) } static struct device_operations cpu_dev_ops = { - .init = model_14_init, + .init = model_14_init, }; static struct cpu_device_id cpu_table[] = { - { X86_VENDOR_AMD, 0x500f00 }, /* ON-A0 */ - { X86_VENDOR_AMD, 0x500f01 }, /* ON-A1 */ - { X86_VENDOR_AMD, 0x500f10 }, /* ON-B0 */ - { X86_VENDOR_AMD, 0x500f20 }, /* ON-C0 */ - { 0, 0 }, + { X86_VENDOR_AMD, 0x500f00 }, /* ON-A0 */ + { X86_VENDOR_AMD, 0x500f01 }, /* ON-A1 */ + { X86_VENDOR_AMD, 0x500f10 }, /* ON-B0 */ + { X86_VENDOR_AMD, 0x500f20 }, /* ON-C0 */ + { 0, 0 }, }; static const struct cpu_driver model_14 __cpu_driver = { - .ops = &cpu_dev_ops, - .id_table = cpu_table, + .ops = &cpu_dev_ops, + .id_table = cpu_table, }; diff --git a/src/mainboard/amd/persimmon/BiosCallOuts.c b/src/mainboard/amd/persimmon/BiosCallOuts.c index 98f9e3e..06426c2 100644 --- a/src/mainboard/amd/persimmon/BiosCallOuts.c +++ b/src/mainboard/amd/persimmon/BiosCallOuts.c @@ -81,6 +81,10 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AGESA_STATUS CalloutStatus; UINTN CallOutCount = sizeof (BiosCallouts) / sizeof (BiosCallouts [0]); + /* + * printk(BIOS_SPEW,"%s function: %x\n", __func__, (u32) Func); + */ + CalloutStatus = AGESA_UNSUPPORTED; for (i = 0; i < CallOutCount; i++) { @@ -95,20 +99,20 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - UINT32 AvailableHeapSize; - UINT8 *BiosHeapBaseAddr; - UINT32 CurrNodeOffset; - UINT32 PrevNodeOffset; - UINT32 FreedNodeOffset; - UINT32 BestFitNodeOffset; - UINT32 BestFitPrevNodeOffset; - UINT32 NextFreeOffset; - BIOS_BUFFER_NODE *CurrNodePtr; - BIOS_BUFFER_NODE *FreedNodePtr; - BIOS_BUFFER_NODE *BestFitNodePtr; - BIOS_BUFFER_NODE *BestFitPrevNodePtr; - BIOS_BUFFER_NODE *NextFreePtr; - BIOS_HEAP_MANAGER *BiosHeapBasePtr; + UINT32 AvailableHeapSize; + UINT8 *BiosHeapBaseAddr; + UINT32 CurrNodeOffset; + UINT32 PrevNodeOffset; + UINT32 FreedNodeOffset; + UINT32 BestFitNodeOffset; + UINT32 BestFitPrevNodeOffset; + UINT32 NextFreeOffset; + BIOS_BUFFER_NODE *CurrNodePtr; + BIOS_BUFFER_NODE *FreedNodePtr; + BIOS_BUFFER_NODE *BestFitNodePtr; + BIOS_BUFFER_NODE *BestFitPrevNodePtr; + BIOS_BUFFER_NODE *NextFreePtr; + BIOS_HEAP_MANAGER *BiosHeapBasePtr; AGESA_BUFFER_PARAMS *AllocParams; AllocParams = ((AGESA_BUFFER_PARAMS *) ConfigPtr); @@ -151,8 +155,9 @@ AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) } CurrNodeOffset = CurrNodePtr->NextNodeOffset; /* If BufferHandle has not been allocated on the heap, CurrNodePtr here points - to the end of the allocated nodes list. + to the end of the allocated nodes list. */ + } /* Find the node that best fits the requested buffer size */ FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes; @@ -201,7 +206,7 @@ AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) } /* If BestFitNode is the first buffer in the list, then update - StartOfFreedNodes to reflect the new free node + StartOfFreedNodes to reflect the new free node */ if (BestFitNodeOffset == BiosHeapBasePtr->StartOfFreedNodes) { BiosHeapBasePtr->StartOfFreedNodes = NextFreeOffset; @@ -226,33 +231,33 @@ AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - UINT8 *BiosHeapBaseAddr; - UINT32 AllocNodeOffset; - UINT32 PrevNodeOffset; - UINT32 NextNodeOffset; - UINT32 FreedNodeOffset; - UINT32 EndNodeOffset; - BIOS_BUFFER_NODE *AllocNodePtr; - BIOS_BUFFER_NODE *PrevNodePtr; - BIOS_BUFFER_NODE *FreedNodePtr; - BIOS_BUFFER_NODE *NextNodePtr; - BIOS_HEAP_MANAGER *BiosHeapBasePtr; + UINT8 *BiosHeapBaseAddr; + UINT32 AllocNodeOffset; + UINT32 PrevNodeOffset; + UINT32 NextNodeOffset; + UINT32 FreedNodeOffset; + UINT32 EndNodeOffset; + BIOS_BUFFER_NODE *AllocNodePtr; + BIOS_BUFFER_NODE *PrevNodePtr; + BIOS_BUFFER_NODE *FreedNodePtr; + BIOS_BUFFER_NODE *NextNodePtr; + BIOS_HEAP_MANAGER *BiosHeapBasePtr; AGESA_BUFFER_PARAMS *AllocParams; AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr; - /* Find target node to deallocate in list of allocated nodes. - Return AGESA_BOUNDS_CHK if the BufferHandle is not found - */ - AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; - AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); BiosHeapBaseAddr = (UINT8 *) GetHeapBase(&(AllocParams->StdHeader)); BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BiosHeapBaseAddr; + /* Find target node to deallocate in list of allocated nodes. + Return AGESA_BOUNDS_CHK if the BufferHandle is not found + */ + AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; + AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); PrevNodeOffset = AllocNodeOffset; - while (AllocNodePtr->BufferHandle != AllocParams->BufferHandle) { + while (AllocNodePtr->BufferHandle != AllocParams->BufferHandle) { if (AllocNodePtr->NextNodeOffset == 0) { return AGESA_BOUNDS_CHK; } @@ -286,10 +291,11 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) /* Clear the BufferSize and NextNodeOffset of the previous first node */ FreedNodePtr->BufferSize = 0; FreedNodePtr->NextNodeOffset = 0; + } else { /* Otherwise, add freed node to the start of the list - Update NextNodeOffset and BufferSize to include the - size of BIOS_BUFFER_NODE + Update NextNodeOffset and BufferSize to include the + size of BIOS_BUFFER_NODE */ AllocNodePtr->NextNodeOffset = FreedNodeOffset; } @@ -297,21 +303,21 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) BiosHeapBasePtr->StartOfFreedNodes = AllocNodeOffset; } else { /* Traverse list of freed nodes to find where the deallocated node - should be place + should be place */ NextNodeOffset = FreedNodeOffset; NextNodePtr = FreedNodePtr; while (AllocNodeOffset > NextNodeOffset) { PrevNodeOffset = NextNodeOffset; if (NextNodePtr->NextNodeOffset == 0) { - break; + break; } NextNodeOffset = NextNodePtr->NextNodeOffset; NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset); } /* If deallocated node is adjacent to the next node, - concatenate both nodes + concatenate both nodes */ if (NextNodeOffset == EndNodeOffset) { NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset); @@ -325,13 +331,14 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AllocNodePtr->NextNodeOffset = NextNodeOffset; } /* If deallocated node is adjacent to the previous node, - concatenate both nodes + concatenate both nodes */ PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset); EndNodeOffset = PrevNodeOffset + PrevNodePtr->BufferSize; if (AllocNodeOffset == EndNodeOffset) { PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset; PrevNodePtr->BufferSize += AllocNodePtr->BufferSize; + AllocNodePtr->BufferSize = 0; AllocNodePtr->NextNodeOffset = 0; } else { @@ -401,17 +408,17 @@ AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) // 0xCF9 (Reset Port). // switch (ResetType) { - case WARM_RESET_WHENEVER: - case COLD_RESET_WHENEVER: + case WARM_RESET_WHENEVER: + case COLD_RESET_WHENEVER: break; - case WARM_RESET_IMMEDIATELY: - case COLD_RESET_IMMEDIATELY: - Value = 0x06; - LibAmdIoWrite (AccessWidth8, 0xCf9, &Value, StdHeader); + case WARM_RESET_IMMEDIATELY: + case COLD_RESET_IMMEDIATELY: + Value = 0x06; + LibAmdIoWrite (AccessWidth8, 0xCf9, &Value, StdHeader); break; - default: + default: break; } @@ -558,13 +565,13 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { case 4: switch (ResetInfo->ResetControl) { - case AssertSlotReset: + case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); Data8 &= ~(UINT8)BIT6 ; Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 Status = AGESA_SUCCESS; break; - case DeassertSlotReset: + case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); Data8 |= BIT6 ; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 @@ -574,13 +581,13 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) break; case 6: switch (ResetInfo->ResetControl) { - case AssertSlotReset: + case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); Data8 &= ~(UINT8)BIT6 ; Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 Status = AGESA_SUCCESS; break; - case DeassertSlotReset: + case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); Data8 |= BIT6 ; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 @@ -590,13 +597,13 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) break; case 7: switch (ResetInfo->ResetControl) { - case AssertSlotReset: + case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02); Data8 &= ~(UINT8)BIT6 ; Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 Status = AGESA_SUCCESS; break; - case DeassertSlotReset: + case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); Data8 |= BIT6 ; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.c index fa9abbf..938300a 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.c @@ -25,7 +25,7 @@ * * Copyright (c) 2011, Advanced Micro Devices, Inc. * All rights reserved. - * + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright @@ -33,10 +33,10 @@ * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. - * + * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -47,7 +47,7 @@ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * * *************************************************************************** * */ @@ -66,7 +66,7 @@ *---------------------------------------------------------------------------------------- */ -// typedef unsigned int uintptr_t; +// typedef unsigned int uintptr_t; /*---------------------------------------------------------------------------------------- * P R O T O T Y P E S O F L O C A L F U N C T I O N S @@ -78,28 +78,28 @@ SetIdtr ( IN IDT_BASE_LIMIT *IdtInfo, IN OUT AMD_CONFIG_PARAMS *StdHeaderPtr ); - + VOID GetCsSelector ( IN UINT16 *Selector, IN OUT AMD_CONFIG_PARAMS *StdHeaderPtr ); - + VOID NmiHandler ( IN OUT AMD_CONFIG_PARAMS *StdHeaderPtr ); - + VOID ExecuteHltInstruction ( IN OUT AMD_CONFIG_PARAMS *StdHeaderPtr ); - + VOID ExecuteWbinvdInstruction ( IN AMD_CONFIG_PARAMS *StdHeader ); - + /*---------------------------------------------------------------------------------------- * E X P O R T E D F U N C T I O N S *---------------------------------------------------------------------------------------- diff --git a/src/vendorcode/amd/agesa/f14/gcccar.inc b/src/vendorcode/amd/agesa/f14/gcccar.inc index ad5a21d..d81b6af 100644 --- a/src/vendorcode/amd/agesa/f14/gcccar.inc +++ b/src/vendorcode/amd/agesa/f14/gcccar.inc @@ -1,7 +1,7 @@ /* * Copyright (c) 2011, Advanced Micro Devices, Inc. * All rights reserved. - * + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright @@ -9,10 +9,10 @@ * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. - * + * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -23,9 +23,9 @@ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * */ - + /****************************************************************************** * AMD Generic Encapsulated Software Architecture * @@ -118,32 +118,32 @@ CR0_PE = 1 # Protection Enable CR0_NW = 29 # Not Write-through CR0_CD = 30 # Cache Disable CR0_PG = 31 # Paging Enable - -/* CPUID Functions */ - -CPUID_MODEL = 1 -AMD_CPUID_FMF = 0x80000001 /* Family Model Features information */ -AMD_CPUID_APIC = 0x80000008 /* Long Mode and APIC info., core count */ - -NB_CFG = 0x0C001001F /* Northbridge Configuration Register */ - INIT_APIC_ID_CPU_ID_LO = 54 /* InitApicIdCpuIdLo - is core# in high or low half of APIC ID? */ - -MTRR_SYS_CFG = 0x0C0010010 /* System Configuration Register */ - CHX_TO_DIRTY_DIS = 16 /* ChxToDirtyDis Change to dirty disable */ - SYS_UC_LOCK_EN = 17 /* SysUcLockEn System lock command enable */ - MTRR_FIX_DRAM_EN = 18 /* MtrrFixDramEn MTRR fixed RdDram and WrDram attributes enable */ - MTRR_FIX_DRAM_MOD_EN = 19 /* MtrrFixDramModEn MTRR fixed RdDram and WrDram modification enable */ - MTRR_VAR_DRAM_EN = 20 /* MtrrVarDramEn MTRR variable DRAM enable */ - MTRR_TOM2_EN = 21 /* MtrrTom2En MTRR top of memory 2 enable */ - -PERF_CONTROL3 = 0x0C0010003 /* Performance event control three */ - PERF_CONTROL3_RESERVE_L = 0x00200000 /* Preserve the reserved bits */ - PERF_CONTROL3_RESERVE_H = 0x0FCF0 /* Preserve the reserved bits */ - CONFIG_EVENT_L = 0x0F0E2 /* All cores with level detection */ - CONFIG_EVENT_H = 4 /* Increment count by number of event */ - /* occured in clock cycle */ - EVENT_ENABLE = 22 /* Enable the event */ -PERF_COUNTER3 = 0x0C0010007 /* Performance event counter three */ + +/* CPUID Functions */ + +CPUID_MODEL = 1 +AMD_CPUID_FMF = 0x80000001 /* Family Model Features information */ +AMD_CPUID_APIC = 0x80000008 /* Long Mode and APIC info., core count */ + +NB_CFG = 0x0C001001F /* Northbridge Configuration Register */ + INIT_APIC_ID_CPU_ID_LO = 54 /* InitApicIdCpuIdLo - is core# in high or low half of APIC ID? */ + +MTRR_SYS_CFG = 0x0C0010010 /* System Configuration Register */ + CHX_TO_DIRTY_DIS = 16 /* ChxToDirtyDis Change to dirty disable */ + SYS_UC_LOCK_EN = 17 /* SysUcLockEn System lock command enable */ + MTRR_FIX_DRAM_EN = 18 /* MtrrFixDramEn MTRR fixed RdDram and WrDram attributes enable */ + MTRR_FIX_DRAM_MOD_EN = 19 /* MtrrFixDramModEn MTRR fixed RdDram and WrDram modification enable */ + MTRR_VAR_DRAM_EN = 20 /* MtrrVarDramEn MTRR variable DRAM enable */ + MTRR_TOM2_EN = 21 /* MtrrTom2En MTRR top of memory 2 enable */ + +PERF_CONTROL3 = 0x0C0010003 /* Performance event control three */ + PERF_CONTROL3_RESERVE_L = 0x00200000 /* Preserve the reserved bits */ + PERF_CONTROL3_RESERVE_H = 0x0FCF0 /* Preserve the reserved bits */ + CONFIG_EVENT_L = 0x0F0E2 /* All cores with level detection */ + CONFIG_EVENT_H = 4 /* Increment count by number of event */ + /* occured in clock cycle */ + EVENT_ENABLE = 22 /* Enable the event */ +PERF_COUNTER3 = 0x0C0010007 /* Performance event counter three */ # Local use flags, in upper most byte if ESI FLAG_UNKNOWN_FAMILY = 24 # Signals that the family# of the installed processor is not recognized @@ -158,28 +158,28 @@ MSR_MASK = ((1 << MTRR_DEF_TYPE_EN)+(1 << MTRR_DEF_TYPE_FIX_EN)) * CPU MACROS - PUBLIC * ****************************************************************************/ -.macro _WRMSR - .byte 0x0f, 0x30 +.macro _WRMSR + .byte 0x0f, 0x30 .endm -.macro _RDMSR - .byte 0x0F, 0x32 +.macro _RDMSR + .byte 0x0F, 0x32 .endm .macro AMD_CPUID arg0 - .ifb \arg0 - mov $0x1, %eax + .ifb \arg0 + mov $0x1, %eax .byte 0x0F, 0x0A2 /* Execute instruction */ - bswap %eax + bswap %eax xchg %ah, %al /* Ext model in al now */ rol $0x08, %eax /* Ext model in ah, model in al */ and $0x0FFCF, ax /* Keep 23:16, 7:6, 3:0 */ .else - mov \arg0, %eax - .byte 0x0F, 0x0A2 + mov \arg0, %eax + .byte 0x0F, 0x0A2 .endif .endm - + /**************************************************************************** * * AMD_ENABLE_STACK_FAMILY_HOOK Macro - Stackless @@ -194,12 +194,12 @@ MSR_MASK = ((1 << MTRR_DEF_TYPE_EN)+(1 << MTRR_DEF_TYPE_FIX_EN)) ****************************************************************************/ .macro AMD_ENABLE_STACK_FAMILY_HOOK - AMD_ENABLE_STACK_FAMILY_HOOK_F10 - AMD_ENABLE_STACK_FAMILY_HOOK_F12 - AMD_ENABLE_STACK_FAMILY_HOOK_F14 - AMD_ENABLE_STACK_FAMILY_HOOK_F15 + AMD_ENABLE_STACK_FAMILY_HOOK_F10 + AMD_ENABLE_STACK_FAMILY_HOOK_F12 + AMD_ENABLE_STACK_FAMILY_HOOK_F14 + AMD_ENABLE_STACK_FAMILY_HOOK_F15 .endm - + /**************************************************************************** * * AMD_DISABLE_STACK_FAMILY_HOOK Macro - Stackless @@ -220,7 +220,7 @@ MSR_MASK = ((1 << MTRR_DEF_TYPE_EN)+(1 << MTRR_DEF_TYPE_FIX_EN)) AMD_DISABLE_STACK_FAMILY_HOOK_F15 .endm - + /**************************************************************************** * * GET_NODE_ID_CORE_ID Macro - Stackless @@ -252,9 +252,9 @@ MSR_MASK = ((1 << MTRR_DEF_TYPE_EN)+(1 << MTRR_DEF_TYPE_FIX_EN)) */ cmp $-1, %si # Has family (node/core) already been discovered? jnz node_core_exit # Br if yes - + mov $((1 << FLAG_UNKNOWN_FAMILY)+(1 << FLAG_IS_PRIMARY)), %esi # No, Set error code, Only let BSP continue - + mov $APIC_BASE_ADDRESS, %ecx # MSR:0000_001B _RDMSR bt $APIC_BSC, %eax # Is this the BSC? @@ -263,7 +263,7 @@ MSR_MASK = ((1 << MTRR_DEF_TYPE_EN)+(1 << MTRR_DEF_TYPE_FIX_EN)) node_core_exit: .endm - + /**************************************************************************** ## Family 10h MACROS ##*************************************************************************** @@ -291,7 +291,7 @@ node_core_exit: # * MSRC001_102A[ClLinesToNbDis]=1 # * No INVD or WBINVD, no exceptions, page faults or interrupts ****************************************************************************/ -.macro AMD_ENABLE_STACK_FAMILY_HOOK_F10 +.macro AMD_ENABLE_STACK_FAMILY_HOOK_F10 LOCAL fam10_enable_stack_hook_exit AMD_CPUID $CPUID_MODEL @@ -324,7 +324,7 @@ node_core_exit: jc fam10_skipClearingBit4 btr $INVD_WBINVD, %eax # disable INVD -> WBINVD conversion _WRMSR - + fam10_skipClearingBit4: mov %esi, %eax # load core# or %al, %al # If (BSP) @@ -347,7 +347,7 @@ fam10_skipClearingBit4: fam10_enable_stack_hook_exit: .endm - + /**************************************************************************** * * AMD_DISABLE_STACK_FAMILY_HOOK_F10 Macro - Stackless @@ -371,7 +371,7 @@ fam10_enable_stack_hook_exit: * * MSRC001_102A[IcDisSpecTlbWr]=0 * * MSRC001_102A[ClLinesToNbDis]=0 *****************************************************************************/ - + .macro AMD_DISABLE_STACK_FAMILY_HOOK_F10 LOCAL fam10_disable_stack_hook_exit @@ -427,7 +427,7 @@ fam10_enable_stack_hook_exit: _WRMSR # Disable the event fam10_disable_stack_hook_exit: -.endm +.endm /**************************************************************************** * @@ -589,7 +589,7 @@ node_core_f10_exit: jc fam12_skipClearingBit4 btr $INVD_WBINVD, %eax # disable INVD -> WBINVD conversion _WRMSR - + fam12_skipClearingBit4: mov $DE_CFG, %ecx # MSR:C001_1029 _RDMSR @@ -893,7 +893,7 @@ node_core_f14_exit: _RDMSR btr $INVD_WBINVD, %eax # disable INVD -> WBINVD conversion _WRMSR - + fam15_skipClearingBit4: mov $LS_CFG, %ecx # MSR:C001_1020 _RDMSR @@ -973,7 +973,7 @@ fam15_enable_stack_hook_exit: btr $DIS_HW_PF, %eax # Turn on hardware prefetches #.endif # End workaround for erratum 498 0: - _WRMSR + _WRMSR #-------------------------------------------------------------------------- # Begin critical sequence in which EAX, BX, ECX, and EDX must be preserved. #-------------------------------------------------------------------------- @@ -1135,7 +1135,7 @@ node_core_f15_shared: #.break .if (ch == bl) # Does 2nd match MyCore#? cmp %bl, %ch je 9f - jmp 2f + jmp 2f #.else # No 2nd core 4: #.break .if (ch == bl) # Does 1st match MyCore#? @@ -1240,7 +1240,7 @@ node_core_f15_exit: * | >|MA|IN| B|IO|S |RA|NG|E | | | | | | |< | >|EX|TE|ND|ED| B|IO|S |ZO|NE| | | | | |< | * +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ *****************************************************************************/ -.macro AMD_ENABLE_STACK +.macro AMD_ENABLE_STACK # These are local labels. Declared so linker doesn't cause 'redefined label' errors LOCAL SetupStack @@ -1308,7 +1308,7 @@ SetupStack: #.if (carry?) # Families using shared groups do not need to clear the MTRRs since that is done at power-on reset # Note: Relying on MSRs to be cleared to 0's at reset for families w/shared cores # Clear all variable and Fixed MTRRs for non-shared cores - jnc 0f + jnc 0f mov $AMD_MTRR_VARIABLE_BASE0, %ecx xor %eax, %eax xor %edx, %edx @@ -1344,20 +1344,20 @@ SetupStack: _WRMSR #.endif # End Is_Primary #.endif # End Stack_ReEntry - 0: + 0: # Clear IORRs (C001_0016-19) and TOM2(C001_001D) for all cores xor %eax, %eax xor %edx, %edx mov $IORR_BASE, %ecx # MSR:C001_0016 - 0019 #.while (cl != 1Ah) jmp 1f - 2: + 2: _WRMSR inc %cl #.endw - 1: + 1: cmp $0x1A, %cl - jne 2b + jne 2b mov $TOP_MEM2, %ecx # MSR:C001_001D _WRMSR @@ -1428,7 +1428,7 @@ SetupStack: mov %eax, %ebp #.endif 0: - + # Now set the MTRR. Add this to already existing settings (don't clear any MTRR) mov $WB_DRAM_TYPE, %edi # Load Cache type in 1st slot mov %bh, %cl # ShiftCount = ((slot# ... @@ -1584,7 +1584,7 @@ ClearTheStack: # Stack base is in SS, stack pointer is * Destroyed: * eax, ecx, edx, esp *****************************************************************************/ -.macro AMD_DISABLE_STACK +.macro AMD_DISABLE_STACK mov %ebx, %esp # Save return address

1 0

Re: [coreboot] porting Coreboot to a new motherboard....
by ali hagigat 27 Mar '12

27 Mar '12

My RAM code was OK(I remember all the members of this mailing list said:"your RAM initialization is not OK", if RAM is not OK how "romstage", "ramstage" and now "filo" are being executed!! Hey, you'd better take a closer look at the source code!!). The reason, hardwaremain() could not be executed, returns to CPU. Now "ramstage" part is copied into RAM and executed and i have added FILO 0.5.6 as a payload. main() function of FILO is executed and tried to read vmlinuz and initrd from harddisk and copy them to 0x100000. Every thing is OK, IDE is initialized correctly and it seems that those files are read and copied well. (/boot and all its files and folders are recognized even lost+found !!) But finally the kernel seems not to become executed and after a few seconds delay hardwaremain() seems to get executed at last!!(strange) and in the middle of hardwaremain() CPU stops!!, hope this time you guys help me find what would be the cause of the problem(I have Fedora 8 and 2.6.23 as the kernel), the serial port shows the followings: coreboot-4.0-1959-g950f20a-dirty Wed Mar 14 18:57:56 IRST 2012 booting... clocks_per_usec: 1003 Enumerating buses... Show all devs...Before device enumeration. Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:1e.0: enabled 1 PCI: 00:1f.0: enabled 1 PNP: 002e.0: enabled 1 PNP: 002e.1: enabled 1 PNP: 002e.2: enabled 1 PNP: 002e.3: enabled 1 PNP: 002e.5: enabled 1 PNP: 002e.6: enabled 0 PNP: 002e.7: enabled 1 PNP: 002e.8: enabled 1 PNP: 002e.9: enabled 1 PNP: 002e.a: enabled 1 PNP: 002e.b: enabled 1 PCI: 00:1f.1: enabled 1 PCI: 00:1f.2: enabled 1 PCI: 00:1f.3: enabled 1 PCI: 00:1f.4: enabled 1 PCI: 00:1f.5: enabled 1 PCI: 00:1f.6: enabled 0 Compare with tree... Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:1e.0: enabled 1 PCI: 00:1f.0: enabled 1 PNP: 002e.0: enabled 1 PNP: 002e.1: enabled 1 PNP: 002e.2: enabled 1 PNP: 002e.3: enabled 1 PNP: 002e.5: enabled 1 PNP: 002e.6: enabled 0 PNP: 002e.7: enabled 1 PNP: 002e.8: enabled 1 PNP: 002e.9: enabled 1 PNP: 002e.a: enabled 1 PNP: 002e.b: enabled 1 PCI: 00:1f.1: enabled 1 PCI: 00:1f.2: enabled 1 PCI: 00:1f.3: enabled 1 PCI: 00:1f.4: enabled 1 PCI: 00:1f.5: enabled 1 PCI: 00:1f.6: enabled 0 scan_static_bus for Root Device APIC_CLUSTER: 0 enabled Finding PCI configuration type. PCI: Using configuration type 1 PCI_DOMAIN: 0000 enabled PCI_DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 PCI: 00:00.0 [8086/1130] enabled PCI: 00:01.0 [8086/1131] enabled PCI: 00:1e.0 [8086/244e] bus ops PCI: 00:1e.0 [8086/244e] enabled PCI: 00:1f.0 [8086/2440] bus ops PCI: 00:1f.0 [8086/2440] enabled PCI: 00:1f.1 [8086/244b] ops PCI: 00:1f.1 [8086/244b] enabled PCI: 00:1f.2 [8086/2442] ops PCI: 00:1f.2 [8086/2442] enabled PCI: 00:1f.3 [8086/2443] bus ops PCI: 00:1f.3 [8086/2443] enabled PCI: 00:1f.4 [8086/2444] ops PCI: 00:1f.4 [8086/2444] enabled PCI: 00:1f.5 [8086/2445] ops PCI: 00:1f.5 [8086/2445] enabled do_pci_scan_bridge for PCI: 00:01.0 PCI: pci_scan_bus for bus 01 PCI: 01:00.0 [1002/5159] enabled PCI: pci_scan_bus returning with max=001 do_pci_scan_bridge returns max 1 do_pci_scan_bridge for PCI: 00:1e.0 PCI: pci_scan_bus for bus 02 PCI: pci_scan_bus returning with max=002 do_pci_scan_bridge returns max 2 scan_static_bus for PCI: 00:1f.0 PNP: 002e.0 enabled PNP: 002e.1 enabled PNP: 002e.2 enabled PNP: 002e.3 enabled PNP: 002e.5 enabled PNP: 002e.6 disabled PNP: 002e.7 enabled PNP: 002e.8 enabled PNP: 002e.9 enabled PNP: 002e.a enabled PNP: 002e.b enabled scan_static_bus for PCI: 00:1f.0 done scan_static_bus for PCI: 00:1f.3 scan_static_bus for PCI: 00:1f.3 done PCI: pci_scan_bus returning with max=002 scan_static_bus for Root Device done done Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 APIC_CLUSTER: 0 read_resources bus 0 link: 0 APIC: 00 missing read_resources APIC_CLUSTER: 0 read_resources bus 0 link: 0 done PCI_DOMAIN: 0000 read_resources bus 0 link: 0 PCI: 00:01.0 read_resources bus 1 link: 0 PCI: 00:01.0 read_resources bus 1 link: 0 done PCI: 00:1e.0 read_resources bus 2 link: 0 PCI: 00:1e.0 read_resources bus 2 link: 0 done PCI: 00:1f.0 read_resources bus 0 link: 0 PCI: 00:1f.0 read_resources bus 0 link: 0 done PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 APIC_CLUSTER: 0 APIC_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 PCI_DOMAIN: 0000 child on link 0 PCI: 00:00.0 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 PCI: 00:00.0 PCI: 00:00.0 resource base 0 size 4000000 align 26 gran 26 limit ffffffff flags 1200 index 10 PCI: 00:01.0 child on link 0 PCI: 01:00.0 PCI: 00:01.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 81202 index 24 PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 01:00.0 PCI: 01:00.0 resource base 0 size 8000000 align 27 gran 27 limit ffffffff flags 1200 index 10 PCI: 01:00.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 14 PCI: 01:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 200 index 18 PCI: 01:00.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 2200 index 30 PCI: 00:1e.0 PCI: 00:1e.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c PCI: 00:1e.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 81202 index 24 PCI: 00:1e.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 00:1f.0 child on link 0 PNP: 002e.0 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100 PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 PNP: 002e.0 PNP: 002e.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 002e.0 resource base 6 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.0 resource base 2 size 1 align 0 gran 0 limit 0 flags c0000800 index 74 PNP: 002e.1 PNP: 002e.1 resource base 378 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 002e.1 resource base 7 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.1 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000800 index 74 PNP: 002e.2 PNP: 002e.2 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.3 PNP: 002e.3 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 002e.3 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.5 PNP: 002e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 60 PNP: 002e.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 62 PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.5 resource base c size 1 align 0 gran 0 limit 0 flags c0000400 index 72 PNP: 002e.6 PNP: 002e.6 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 60 PNP: 002e.6 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.7 PNP: 002e.7 resource base 201 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 60 PNP: 002e.7 resource base 330 size 2 align 1 gran 1 limit 7ff flags c0000100 index 62 PNP: 002e.7 resource base 9 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.8 PNP: 002e.9 PNP: 002e.a PNP: 002e.b PNP: 002e.b resource base 290 size 8 align 3 gran 3 limit fff flags c0000100 index 60 PNP: 002e.b resource base 5 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PCI: 00:1f.1 PCI: 00:1f.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 PCI: 00:1f.2 PCI: 00:1f.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 PCI: 00:1f.3 PCI: 00:1f.3 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 PCI: 00:1f.4 PCI: 00:1f.4 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 PCI: 00:1f.5 PCI: 00:1f.5 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10 PCI: 00:1f.5 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 14 PCI: 00:1f.6 PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff PCI: 00:01.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 01:00.0 14 * [0x0 - 0xff] io PCI: 00:01.0 compute_resources_io: base: 100 size: 1000 align: 12 gran: 12 limit: ffff done PCI: 00:1e.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 00:1e.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done PCI: 00:01.0 1c * [0x0 - 0xfff] io PCI: 00:1f.5 10 * [0x1000 - 0x10ff] io PCI: 00:1f.5 14 * [0x1400 - 0x143f] io PCI: 00:1f.2 20 * [0x1440 - 0x145f] io PCI: 00:1f.4 20 * [0x1460 - 0x147f] io PCI: 00:1f.1 20 * [0x1480 - 0x148f] io PCI: 00:1f.3 20 * [0x1490 - 0x149f] io PCI_DOMAIN: 0000 compute_resources_io: base: 14a0 size: 14a0 align: 12 gran: 0 limit: ffff done PCI_DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff PCI: 00:01.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 01:00.0 10 * [0x0 - 0x7ffffff] prefmem PCI: 00:01.0 compute_resources_prefmem: base: 8000000 size: 8000000 align: 27 gran: 20 limit: ffffffff done PCI: 00:01.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 01:00.0 30 * [0x0 - 0x1ffff] mem PCI: 01:00.0 18 * [0x20000 - 0x2ffff] mem PCI: 00:01.0 compute_resources_mem: base: 30000 size: 100000 align: 20 gran: 20 limit: ffffffff done PCI: 00:1e.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:1e.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:1e.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:1e.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:01.0 24 * [0x0 - 0x7ffffff] prefmem PCI: 00:00.0 10 * [0x8000000 - 0xbffffff] prefmem PCI: 00:01.0 20 * [0xc000000 - 0xc0fffff] mem PCI_DOMAIN: 0000 compute_resources_mem: base: c100000 size: c100000 align: 27 gran: 0 limit: ffffffff done avoid_fixed_resources: PCI_DOMAIN: 0000 avoid_fixed_resources:@PCI_DOMAIN: 0000 10000000 limit 0000ffff avoid_fixed_resources:@PCI_DOMAIN: 0000 10000100 limit ffffffff constrain_resources: PCI_DOMAIN: 0000 constrain_resources: PCI: 00:00.0 constrain_resources: PCI: 00:01.0 constrain_resources: PCI: 01:00.0 constrain_resources: PCI: 00:1e.0 constrain_resources: PCI: 00:1f.0 constrain_resources: PNP: 002e.0 constrain_resources: PNP: 002e.1 constrain_resources: PNP: 002e.2 constrain_resources: PNP: 002e.3 constrain_resources: PNP: 002e.5 constrain_resources: PNP: 002e.7 constrain_resources: PNP: 002e.8 constrain_resources: PNP: 002e.9 constrain_resources: PNP: 002e.a constrain_resources: PNP: 002e.b constrain_resources: PCI: 00:1f.1 constrain_resources: PCI: 00:1f.2 constrain_resources: PCI: 00:1f.3 constrain_resources: PCI: 00:1f.4 constrain_resources: PCI: 00:1f.5 avoid_fixed_resources2: PCI_DOMAIN: 0000@10000000 limit 0000ffff lim->base 00001000 lim->limit 0000ffff avoid_fixed_resources2: PCI_DOMAIN: 0000@10000100 limit ffffffff lim->base 00000000 lim->limit febfffff Setting resources... PCI_DOMAIN: 0000 allocate_resources_io: base:1000 size:14a0 align:12 gran:0 limit:ffff Assigned: PCI: 00:01.0 1c * [0x1000 - 0x1fff] io Assigned: PCI: 00:1f.5 10 * [0x2000 - 0x20ff] io Assigned: PCI: 00:1f.5 14 * [0x2400 - 0x243f] io Assigned: PCI: 00:1f.2 20 * [0x2440 - 0x245f] io Assigned: PCI: 00:1f.4 20 * [0x2460 - 0x247f] io Assigned: PCI: 00:1f.1 20 * [0x2480 - 0x248f] io Assigned: PCI: 00:1f.3 20 * [0x2490 - 0x249f] io PCI_DOMAIN: 0000 allocate_resources_io: next_base: 24a0 size: 14a0 align: 12 gran: 0 done PCI: 00:01.0 allocate_resources_io: base:1000 size:1000 align:12 gran:12 limit:ffff Assigned: PCI: 01:00.0 14 * [0x1000 - 0x10ff] io PCI: 00:01.0 allocate_resources_io: next_base: 1100 size: 1000 align: 12 gran: 12 done PCI: 00:1e.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:1e.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done PCI_DOMAIN: 0000 allocate_resources_mem: base:f0000000 size:c100000 align:27 gran:0 limit:febfffff Assigned: PCI: 00:01.0 24 * [0xf0000000 - 0xf7ffffff] prefmem Assigned: PCI: 00:00.0 10 * [0xf8000000 - 0xfbffffff] prefmem Assigned: PCI: 00:01.0 20 * [0xfc000000 - 0xfc0fffff] mem PCI_DOMAIN: 0000 allocate_resources_mem: next_base: fc100000 size: c100000 align: 27 gran: 0 done PCI: 00:01.0 allocate_resources_prefmem: base:f0000000 size:8000000 align:27 gran:20 limit:febfffff Assigned: PCI: 01:00.0 10 * [0xf0000000 - 0xf7ffffff] prefmem PCI: 00:01.0 allocate_resources_prefmem: next_base: f8000000 size: 8000000 align: 27 gran: 20 done PCI: 00:01.0 allocate_resources_mem: base:fc000000 size:100000 align:20 gran:20 limit:febfffff Assigned: PCI: 01:00.0 30 * [0xfc000000 - 0xfc01ffff] mem Assigned: PCI: 01:00.0 18 * [0xfc020000 - 0xfc02ffff] mem PCI: 00:01.0 allocate_resources_mem: next_base: fc030000 size: 100000 align: 20 gran: 20 done PCI: 00:1e.0 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 limit:febfffff PCI: 00:1e.0 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 gran: 20 done PCI: 00:1e.0 allocate_resources_mem: base:febfffff size:0 align:20 gran:20 limit:febfffff PCI: 00:1e.0 allocate_resources_mem: next_base: febfffff size: 0 align: 20 gran: 20 done Root Device assign_resources, bus 0 link: 0 No IGD UMA Memory Available memory: 524288KB PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 PCI: 00:00.0 10 <- [0x00f8000000 - 0x00fbffffff] size 0x04000000 gran 0x1a prefmem PCI: 00:01.0 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 01 io PCI: 00:01.0 24 <- [0x00f0000000 - 0x00f7ffffff] size 0x08000000 gran 0x14 bus 01 prefmem PCI: 00:01.0 20 <- [0x00fc000000 - 0x00fc0fffff] size 0x00100000 gran 0x14 bus 01 mem PCI: 00:01.0 assign_resources, bus 1 link: 0 PCI: 01:00.0 10 <- [0x00f0000000 - 0x00f7ffffff] size 0x08000000 gran 0x1b prefmem PCI: 01:00.0 14 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io PCI: 01:00.0 18 <- [0x00fc020000 - 0x00fc02ffff] size 0x00010000 gran 0x10 mem PCI: 01:00.0 30 <- [0x00fc000000 - 0x00fc01ffff] size 0x00020000 gran 0x11 romem PCI: 00:01.0 assign_resources, bus 1 link: 0 PCI: 00:1e.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io PCI: 00:1e.0 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 02 prefmem PCI: 00:1e.0 20 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 02 mem PCI: 00:1f.0 assign_resources, bus 0 link: 0 PNP: 002e.0 60 <- [0x00000003f0 - 0x00000003f7] size 0x00000008 gran 0x03 io PNP: 002e.0 70 <- [0x0000000006 - 0x0000000006] size 0x00000001 gran 0x00 irq PNP: 002e.0 74 <- [0x0000000002 - 0x0000000002] size 0x00000001 gran 0x00 drq PNP: 002e.1 60 <- [0x0000000378 - 0x000000037f] size 0x00000008 gran 0x03 io PNP: 002e.1 70 <- [0x0000000007 - 0x0000000007] size 0x00000001 gran 0x00 irq PNP: 002e.1 74 <- [0x0000000003 - 0x0000000003] size 0x00000001 gran 0x00 drq PNP: 002e.2 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io PNP: 002e.2 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq PNP: 002e.3 60 <- [0x00000002f8 - 0x00000002ff] size 0x00000008 gran 0x03 io PNP: 002e.3 70 <- [0x0000000003 - 0x0000000003] size 0x00000001 gran 0x00 irq PNP: 002e.5 60 <- [0x0000000060 - 0x0000000060] size 0x00000001 gran 0x00 io PNP: 002e.5 62 <- [0x0000000064 - 0x0000000064] size 0x00000001 gran 0x00 io PNP: 002e.5 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00 irq PNP: 002e.5 72 <- [0x000000000c - 0x000000000c] size 0x00000001 gran 0x00 irq PNP: 002e.7 60 <- [0x0000000201 - 0x0000000201] size 0x00000001 gran 0x00 io PNP: 002e.7 62 <- [0x0000000330 - 0x0000000331] size 0x00000002 gran 0x01 io PNP: 002e.7 70 <- [0x0000000009 - 0x0000000009] size 0x00000001 gran 0x00 irq PNP: 002e.b 60 <- [0x0000000290 - 0x0000000297] size 0x00000008 gran 0x03 io PNP: 002e.b 70 <- [0x0000000005 - 0x0000000005] size 0x00000001 gran 0x00 irq PCI: 00:1f.0 assign_resources, bus 0 link: 0 PCI: 00:1f.1 20 <- [0x0000002480 - 0x000000248f] size 0x00000010 gran 0x04 io PCI: 00:1f.2 20 <- [0x0000002440 - 0x000000245f] size 0x00000020 gran 0x05 io PCI: 00:1f.3 20 <- [0x0000002490 - 0x000000249f] size 0x00000010 gran 0x04 io PCI: 00:1f.4 20 <- [0x0000002460 - 0x000000247f] size 0x00000020 gran 0x05 io PCI: 00:1f.5 10 <- [0x0000002000 - 0x00000020ff] size 0x00000100 gran 0x08 io PCI: 00:1f.5 14 <- [0x0000002400 - 0x000000243f] size 0x00000040 gran 0x06 io PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device child on link 0 APIC_CLUSTER: 0 APIC_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 PCI_DOMAIN: 0000 child on link 0 PCI: 00:00.0 PCI_DOMAIN: 0000 resource base 1000 size 14a0 align 12 gran 0 limit ffff flags 40040100 index 10000000 PCI_DOMAIN: 0000 resource base f0000000 size c100000 align 27 gran 0 limit febfffff flags 40040200 index 10000100 PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index a PCI_DOMAIN: 0000 resource base c0000 size 1ff40000 align 0 gran 0 limit 0 flags e0004200 index b PCI: 00:00.0 PCI: 00:00.0 resource base f8000000 size 4000000 align 26 gran 26 limit febfffff flags 60001200 index 10 PCI: 00:01.0 child on link 0 PCI: 01:00.0 PCI: 00:01.0 resource base 1000 size 1000 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:01.0 resource base f0000000 size 8000000 align 27 gran 20 limit febfffff flags 60081202 index 24 PCI: 00:01.0 resource base fc000000 size 100000 align 20 gran 20 limit febfffff flags 60080202 index 20 PCI: 01:00.0 PCI: 01:00.0 resource base f0000000 size 8000000 align 27 gran 27 limit febfffff flags 60001200 index 10 PCI: 01:00.0 resource base 1000 size 100 align 8 gran 8 limit ffff flags 60000100 index 14 PCI: 01:00.0 resource base fc020000 size 10000 align 16 gran 16 limit febfffff flags 60000200 index 18 PCI: 01:00.0 resource base fc000000 size 20000 align 17 gran 17 limit febfffff flags 60002200 index 30 PCI: 00:1e.0 PCI: 00:1e.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:1e.0 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60081202 index 24 PCI: 00:1e.0 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60080202 index 20 PCI: 00:1f.0 child on link 0 PNP: 002e.0 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100 PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 PNP: 002e.0 PNP: 002e.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 PNP: 002e.0 resource base 6 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PNP: 002e.0 resource base 2 size 1 align 0 gran 0 limit 0 flags e0000800 index 74 PNP: 002e.1 PNP: 002e.1 resource base 378 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 PNP: 002e.1 resource base 7 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PNP: 002e.1 resource base 3 size 1 align 0 gran 0 limit 0 flags e0000800 index 74 PNP: 002e.2 PNP: 002e.2 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PNP: 002e.3 PNP: 002e.3 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 PNP: 002e.3 resource base 3 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PNP: 002e.5 PNP: 002e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 60 PNP: 002e.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 62 PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PNP: 002e.5 resource base c size 1 align 0 gran 0 limit 0 flags e0000400 index 72 PNP: 002e.6 PNP: 002e.6 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 60 PNP: 002e.6 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.7 PNP: 002e.7 resource base 201 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 60 PNP: 002e.7 resource base 330 size 2 align 1 gran 1 limit 7ff flags e0000100 index 62 PNP: 002e.7 resource base 9 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PNP: 002e.8 PNP: 002e.9 PNP: 002e.a PNP: 002e.b PNP: 002e.b resource base 290 size 8 align 3 gran 3 limit fff flags e0000100 index 60 PNP: 002e.b resource base 5 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PCI: 00:1f.1 PCI: 00:1f.1 resource base 2480 size 10 align 4 gran 4 limit ffff flags 60000100 index 20 PCI: 00:1f.2 PCI: 00:1f.2 resource base 2440 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 PCI: 00:1f.3 PCI: 00:1f.3 resource base 2490 size 10 align 4 gran 4 limit ffff flags 60000100 index 20 PCI: 00:1f.4 PCI: 00:1f.4 resource base 2460 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 PCI: 00:1f.5 PCI: 00:1f.5 resource base 2000 size 100 align 8 gran 8 limit ffff flags 60000100 index 10 PCI: 00:1f.5 resource base 2400 size 40 align 6 gran 6 limit ffff flags 60000100 index 14 PCI: 00:1f.6 Done allocating resources. Enabling resources... PCI: 00:00.0 subsystem <- 0000/0000 PCI: 00:00.0 cmd <- 06 PCI: 00:01.0 bridge ctrl <- 0003 PCI: 00:01.0 cmd <- 07 PCI: 00:1e.0 bridge ctrl <- 0003 PCI: 00:1e.0 cmd <- 01 PCI: 00:1f.0 cmd <- 0f PCI: 00:1f.1 cmd <- 01 PCI: 00:1f.2 cmd <- 01 PCI: 00:1f.3 cmd <- 01 PCI: 00:1f.4 cmd <- 01 PCI: 00:1f.5 cmd <- 01 PCI: 01:00.0 cmd <- 83 W83627HF HWM SMBus enabled done. Initializing devices... Root Device init APIC_CLUSTER: 0 init start_eip=0x00004000, offset=0x00100000, code_size=0x0000005b Initializing CPU #0 CPU: vendor Intel device 6b1 CPU: family 06, model 0b, stepping 01 Enabling cache CPU: Intel(R) Celeron(TM) CPU 1000MHz. Setting up local apic... apic_id: 0x00 done. CPU #0 initialized All AP CPUs stopped PCI: 00:00.0 init PCI: 00:1e.0 init PCI: 00:1f.0 init IOAPIC Southbridge enabled 2186 Southbridge APIC ID = 2000000 Set power on if power fails RTC Init PCI: 00:1f.1 init IDE: Primary IDE interface: on IDE: Secondary IDE interface: on PCI: 00:1f.2 init PCI: 00:1f.4 init PCI: 01:00.0 init PNP: 002e.0 init PNP: 002e.1 init PNP: 002e.2 init PNP: 002e.3 init PNP: 002e.5 init PNP: 002e.7 init PNP: 002e.8 init PNP: 002e.9 init PNP: 002e.a init PNP: 002e.b init base = 0x0295, reg = 0x40, value = 0x81 base = 0x0295, reg = 0x48, value = 0x2a base = 0x0295, reg = 0x4a, value = 0x21 base = 0x0295, reg = 0x4e, value = 0x00 base = 0x0295, reg = 0x43, value = 0xff base = 0x0295, reg = 0x44, value = 0x3f base = 0x0295, reg = 0x4c, value = 0x1f base = 0x0295, reg = 0x4d, value = 0x8f Devices initialized Show all devs...After init. Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:1e.0: enabled 1 PCI: 00:1f.0: enabled 1 PNP: 002e.0: enabled 1 PNP: 002e.1: enabled 1 PNP: 002e.2: enabled 1 PNP: 002e.3: enabled 1 PNP: 002e.5: enabled 1 PNP: 002e.6: enabled 0 PNP: 002e.7: enabled 1 PNP: 002e.8: enabled 1 PNP: 002e.9: enabled 1 PNP: 002e.a: enabled 1 PNP: 002e.b: enabled 1 PCI: 00:1f.1: enabled 1 PCI: 00:1f.2: enabled 1 PCI: 00:1f.3: enabled 1 PCI: 00:1f.4: enabled 1 PCI: 00:1f.5: enabled 1 PCI: 00:1f.6: enabled 0 PCI: 01:00.0: enabled 1 ERROR: High Tables Base is not set. High Tables Base is 0. Adjust low_table_end from 0x00000500 to 0x00001000 Adjust rom_table_end from 0x000f0000 to 0x000f0000 Adding IGD UMA memory area coreboot memory table: 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM 2. 00000000000c0000-00000000000effff: RAM 3. 00000000000f0000-000000001fffffff: RAM 4. 00000000000f0000-00000000000effff: CONFIGURATION TABLES 5. 0000000020000000-000000001fffffff: RESERVED Wrote coreboot table at: 00000500 - 000006e8 checksum cb85 Got a payload Loading segment from rom address 0xfffdb0f8 data (compression=1) New segment dstaddr 0x100000 memsize 0x28130 srcaddr 0xfffdb14c filesize 0x4fad (cleaned up) New segment addr 0x100000 size 0x28130 offset 0xfffdb14c filesize 0x4fad Loading segment from rom address 0xfffdb114 data (compression=1) New segment dstaddr 0x128130 memsize 0x48 srcaddr 0xfffe00f9 filesize 0x2e (cleaned up) New segment addr 0x128130 size 0x48 offset 0xfffe00f9 filesize 0x2e Loading segment from rom address 0xfffdb130 Entry Point 0x00000000 Loading Segment: addr: 0x0000000000100000 memsz: 0x0000000000028130 filesz: 0x0000000000004fad lb: [0x0000000000100000, 0x0000000000124000) segment: [0x0000000000100000, 0x0000000000104fad, 0x0000000000128130) bounce: [0x000000001ffb3ed0, 0x000000001ffb8e7d, 0x000000001ffdc000) Post relocation: addr: 0x000000001ffb3ed0 memsz: 0x0000000000028130 filesz: 0x0000000000004fad using LZMA [ 0x1ffb3ed0, 1ffbdefc, 0x1ffdc000) <- fffdb14c Clearing Segment: addr: 0x000000001ffbdefc memsz: 0x000000000001e104 dest 1ffb3ed0, end 1ffdc000, bouncebuffer 1ffb3ed0 move suffix around: from 1ffd7ed0, to 124000, amount: 4130 Loading Segment: addr: 0x0000000000128130 memsz: 0x0000000000000048 filesz: 0x000000000000002e lb: [0x0000000000100000, 0x0000000000124000) Post relocation: addr: 0x0000000000128130 memsz: 0x0000000000000048 filesz: 0x000000000000002e using LZMA [ 0x00128130, 00128178, 0x00128178) <- fffe00f9 dest 00128130, end 00128178, bouncebuffer 1ffb3ed0 Loaded segments ICH Watchdog disabled Jumping to boot code at 10008c entry = 0x0010008c lb_start = 0x00100000 lb_size = 0x00024000 adjust = 0x1fedc000 buffer = 0x1ffb3ed0 elf_boot_notes = 0x00110f64 adjusted_boot_notes = 0x1ffecf64 FILO version 0.5.6 (root(a)localhost.localdomain) Wed Mar 14 18:57:32 IRST 2012 collect_sys_info: boot eax = 0xe1fb007 collect_sys_info: boot ebx = 0x1ffecf64 collect_sys_info: boot arg = 0x1ffecf64 collect_linuxbios_info: Searching for LinuxBIOS tables... find_lb_table: Found candidate at: 00000500 find_lb_table: header checksum o.k. find_lb_table: table checksum o.k. find_lb_table: record count o.k. collect_linuxbios_info: Found LinuxBIOS table at: 00000500 convert_memmap: 0x00000000000000 0x00000000001000 16 convert_memmap: 0x00000000001000 0x0000000009f000 1 convert_memmap: 0x000000000c0000 0x00000000030000 1 convert_memmap: 0x000000000f0000 0x0000001ff10000 1 convert_memmap: 0x000000000f0000 0x00000000000000 16 convert_memmap: 0x00000020000000 0x00000000000000 2 collect_sys_info: 0000000000001000-00000000000a0000 collect_sys_info: 00000000000c0000-00000000000f0000 collect_sys_info: 00000000000f0000-0000000020000000 collect_sys_info: RAM 512 MB relocate: Current location: 0x100000-0x128177 relocate: Relocating to 0x1ffd7000-0x1ffff177... ok setup_timers: CPU 1002 MHz pci_init: Scanning PCI: found 10 devices malloc_diag: alloc: 0 bytes (0 blocks), free: 32760 bytes (1 blocks) malloc_diag: alloc: 128 bytes (1 blocks), free: 32632 bytes (1 blocks) pci_init: 00:00.0 8086:1130 0600 00 pci_init: 00:01.0 8086:1131 0604 00 pci_init: 00:1e.0 8086:244e 0604 00 pci_init: 00:1f.0 8086:2440 0601 00 pci_init: 00:1f.1 8086:244b 0101 80 pci_init: 00:1f.2 8086:2442 0c03 00 pci_init: 00:1f.3 8086:2443 0c05 00 pci_init: 00:1f.4 8086:2444 0c03 00 pci_init: 00:1f.5 8086:2445 0401 00 pci_init: 01:00.0 1002:5159 0300 00 Press <Enter> for default boot, or <Esc> for boot prompt... 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 timed out boot: hda1:/vmlinuz-2.6.23.1-42.fc8 root=/dev/sda3 initrd=sda1:/boot/initrd-2.6.23.1-42.fc8.img console=tty0 console=ttyS0,38400 malloc_diag: alloc: 264 bytes (2 blocks), free: 32496 bytes (1 blocks) malloc_diag: alloc: 280 bytes (3 blocks), free: 32480 bytes (1 blocks) file_open: dev=hda1, path=/vmlinuz-2.6.23.1-42.fc8 find_ide_controller: found PCI IDE controller 8086:244b prog_if=0x80 find_ide_controller: primary channel: compatibility mode find_ide_controller_compat: skipping 0 native PCI controllers, new index=0 find_ide_controller: cmd_base=0x1f0 ctrl_base=0x3f4 init_controller: init_controller: drive 0 ide_software_reset: Waiting for ide0 to become ready for reset... ok ide_software_reset: Resetting ide0... ok init_drive: Testing for hda init_drive: Probing for hda init_drive: LBA mode, sectors=58633344 init_drive: Init device params... ok hda: LBA 30GB: QUANTUM FIREBALLlct20 30 init_controller: MASTER CHECK: master yes init_drive: Testing for hdb init_drive: Probing for hdb print_status: IDE: status=0x51, err=0x4 init_drive: Testing for hdb init_drive: Probing for hdb hdb: ATAPI: SONY DVD RW DRU-190A init_controller: /*slave */ -- drive is 0 devopen: Partition 1 start 63 length 1044162 Mounted EXT2 filesystem inode 2 dirname=/vmlinuz-2.6.23.1-42.fc8 ipg=2040, dpb=32 group_id=0 group_desc=0 desc=0 fsblock 2 buffer 1124496 inode table fsblock=262 fsblock 262 buffer 1125520 ipb=8, sizeof(inode)=128 inode=112c90, raw_inode=112d10 offset into inode table block=128 00 00 00 00 00 00 00 00 e1 8a 60 4f e1 8a 60 4f e1 8a 60 4f 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ed first word=41ed first word=41ed dirname=vmlinuz-2.6.23.1-42.fc8, rest=, loc=0 ed 41 00 00 00 04 00 00 97 b6 60 4f f1 98 60 4f f1 98 60 4f 00 00 00 00 00 00 04 00 04 00 00 00 00 00 00 00 00 00 00 00 05 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 13 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 logical block 0 returning 517 returning 517 fs block=517 fsblock 517 buffer 1126672 directory entry ino=2 entry=. dirname=vmlinuz-2.6.23.1-42.fc8, rest=, loc=12 ed 41 00 00 00 04 00 00 97 b6 60 4f f1 98 60 4f f1 98 60 4f 00 00 00 00 00 00 04 00 04 00 00 00 00 00 00 00 00 00 00 00 05 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 13 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 logical block 0 returning 517 returning 517 fs block=517 fsblock 517 buffer 1126672 directory entry ino=2 entry=.. dirname=vmlinuz-2.6.23.1-42.fc8, rest=, loc=24 ed 41 00 00 00 04 00 00 97 b6 60 4f f1 98 60 4f f1 98 60 4f 00 00 00 00 00 00 04 00 04 00 00 00 00 00 00 00 00 00 00 00 05 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 13 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 logical block 0 returning 517 returning 517 fs block=517 fsblock 517 buffer 1126672 directory entry ino=11 entry=lost+found dirname=vmlinuz-2.6.23.1-42.fc8, rest=, loc=44 ed 41 00 00 00 04 00 00 97 b6 60 4f f1 98 60 4f f1 98 60 4f 00 00 00 00 00 00 04 00 04 00 00 00 00 00 00 00 00 00 00 00 05 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 13 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 logical block 0 returning 517 returning 517 fs block=517 fsblock 517 buffer 1126672 directory entry ino=65281 entry=grub dirname=vmlinuz-2.6.23.1-42.fc8, rest=, loc=56 ed 41 00 00 00 04 00 00 97 b6 60 4f f1 98 60 4f f1 98 60 4f 00 00 00 00 00 00 04 00 04 00 00 00 00 00 00 00 00 00 00 00 05 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 13 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 logical block 0 returning 517 returning 517 fs block=517 fsblock 517 buffer 1126672 directory entry ino=14 entry=config-2.6.23.1-42.fc8db dirname=vmlinuz-2.6.23.1-42.fc8, rest=, loc=88 ed 41 00 00 00 04 00 00 97 b6 60 4f f1 98 60 4f f1 98 60 4f 00 00 00 00 00 00 04 00 04 00 00 00 00 00 00 00 00 00 00 00 05 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 13 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................................... ................................... ................................... 80 81 00 00 84 88 2c 00 3a 09 70 4f 6c 98 60 4f 6c 98 60 4f 00 00 00 00 00 00 01 00 62 16 00 00 00 00 00 00 00 00 00 00 01 10 00 00 02 10 00 00 03 10 00 00 04 10 00 00 05 10 00 00 06 10 00 00 07 10 00 00 08 10 00 00 09 10 00 00 0a 10 00 00 0b 10 00 00 0c 10 00 00 0d 10 00 00 0e 11 00 00 00 00 00 00 eb 22 38 50 16 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 logical block 2850 map=10436 ok malloc_diag: alloc: 256 bytes (2 blocks), free: 32504 bytes (1 blocks) start_linux: eip=0x100000 Jumping to entry point... coreboot-4.0-1959-g950f20a-dirty Tue Mar 27 13:28:26 IRDT 2012 booting... clocks_per_usec: 1003 Enumerating buses... Show all devs...Before device enumeration. Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:1e.0: enabled 1 PCI: 00:1f.0: enabled 1 PNP: 002e.0: enabled 1 PNP: 002e.1: enabled 1 PNP: 002e.2: enabled 1 PNP: 002e.3: enabled 1 PNP: 002e.5: enabled 1 PNP: 002e.6: enabled 0 PNP: 002e.7: enabled 1 PNP: 002e.8: enabled 1 PNP: 002e.9: enabled 1 PNP: 002e.a: enabled 1 PNP: 002e.b: enabled 1 PCI: 00:1f.1: enabled 1 PCI: 00:1f.2: enabled 1 PCI: 00:1f.3: enabled 1 PCI: 00:1f.4: enabled 1 PCI: 00:1f.5: enabled 1 PCI: 00:1f.6: enabled 0 Compare with tree... Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:1e.0: enabled 1 PCI: 00:1f.0: enabled 1 PNP: 002e.0: enabled 1 PNP: 002e.1: enabled 1 PNP: 002e.2: enabled 1 PNP: 002e.3: enabled 1 PNP: 002e.5: enabled 1 PNP: 002e.6: enabled 0 PNP: 002e.7: enabled 1 PNP: 002e.8: enabled 1 PNP: 002e.9: enabled 1 PNP: 002e.a: enabled 1 PNP: 002e.b: enabled 1 PCI: 00:1f.1: enabled 1 PCI: 00:1f.2: enabled 1 PCI: 00:1f.3: enabled 1 PCI: 00:1f.4: enabled 1 PCI: 00:1f.5: enabled 1 PCI: 00:1f.6: enabled 0 scan_static_bus for Root Device APIC_CLUSTER: 0 enabled Finding PCI configuration type. PCI: Using configuration type 1 PCI_DOMAIN: 0000 enabled PCI_DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 PCI: 00:00.0 [8086/1130] enabled PCI: 00:01.0 [8086/1131] enabled PCI: 00:1e.0 [8086/244e] bus ops PCI: 00:1e.0 [8086/244e] enabled PCI: 00:1f.0 [8086/2440] bus ops PCI: 00:1f.0 [8086/2440] enabled PCI: 00:1f.1 [8086/244b] ops PCI: 00:1f.1 [8086/244b] enabled PCI: 00:1f.2 [8086/2442] ops PCI: 00:1f.2 [8086/2442] enabled PCI: 00:1f.3 [8086/2443] bus ops PCI: 00:1f.3 [8086/2443] enabled PCI: 00:1f.4 [8086/2444] ops PCI: 00:1f.4 [8086/2444] enabled PCI: 00:1f.5 [8086/2445] ops PCI: 00:1f.5 [8086/2445] enabled do_pci_scan_bridge for PCI: 00:01.0 PCI: pci_scan_bus for bus 01 PCI: 01:00.0 [1002/5159] enabled PCI: pci_scan_bus returning with max=001 do_pci_scan_bridge returns max 1 do_pci_scan_bridge for PCI: 00:1e.0 PCI: pci_scan_bus for bus 02 PCI: pci_scan_bus returning with max=002 do_pci_scan_bridge returns max 2 scan_static_bus for PCI: 00:1f.0 PNP: 002e.0 enabled PNP: 002e.1 enabled PNP: 002e.2 enabled PNP: 002e.3 enabled PNP: 002e.5 enabled PNP: 002e.6 disabled PNP: 002e.7 enabled PNP: 002e.8 enabled PNP: 002e.9 enabled PNP: 002e.a enabled PNP: 002e.b enabled scan_static_bus for PCI: 00:1f.0 done scan_static_bus for PCI: 00:1f.3 scan_static_bus for PCI: 00:1f.3 done PCI: pci_scan_bus returning with max=002 scan_static_bus for Root Device done done Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 APIC_CLUSTER: 0 read_resources bus 0 link: 0 APIC: 00 missing read_resources APIC_CLUSTER: 0 read_resources bus 0 link: 0 done PCI_DOMAIN: 0000 read_resources bus 0 link: 0

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Re: [coreboot] Badheaders from gerrit? (was Re: New patch to review for coreboot: c81993b Makefile: rename romstage linking filenames)
by Georgi, Patrick 27 Mar '12

27 Mar '12

> -----Ursprüngliche Nachricht----- > Von: coreboot-bounces(a)coreboot.org [mailto:coreboot- > bounces(a)coreboot.org] Im Auftrag von Oliver Schinagl > Gesendet: Montag, 26. März 2012 21:58 > An: coreboot(a)coreboot.org > Betreff: Re: [coreboot] Badheaders from gerrit? (was Re: New patch to > review for coreboot: c81993b Makefile: rename romstage linking filenames) > > Ah, ok, unfortunately, not enough time to fix gerrit :( But ... typical. > So typical. Errors in mails to the list aren't gerrit's fault, but mine. Patrick -- Patrick Georgi Fachbereich SINA-Entwicklung Geschäftsbereich Hochsicherheit secunet Security Networks AG Mergenthalerallee 77 65760 Eschborn, Germany Telefon +49 201 54 54-3610 Telefax +49 201 54 54-1325 Patrick.Georgi(a)secunet.com www.secunet.com Sitz: Kronprinzenstraße 30, 45128 Essen Amtsgericht Essen HRB 13615 Vorstand: Dr. Rainer Baumgart (Vors.), Thomas Koelzer, Thomas Pleines Aufsichtsratsvorsitzender: Dr. Karsten Ottenberg Diese E-Mail kann vertrauliche Informationen enthalten. Falls Sie diese E-Mail irrtümlich erhalten haben, informieren Sie bitte unverzüglich den Absender und löschen Sie diese E-Mail von jedem Rechner, auch von den Mailservern. Jede Verbreitung des Inhalts, auch die teilweise Verbreitung, ist in diesem Fall untersagt. Außer bei Vorsatz oder grober Fahrlässigkeit schließen wir jegliche Haftung für Verluste oder Schäden aus, die durch Viren befallene Software oder E-Mails verursacht werden. This e-mail may contain confidential information. If you received this e-mail in error, please contact the sender and delete this e-mail from your computer, including your mailservers. Any dissemination, even partly, is prohibited. Except in case of gross negligence or wilful misconduct we accept no liability for any loss or damage caused by software or e-mail viruses.

2 1

Compal JHL90 (JHXXX family)
by Swift Geek 26 Mar '12

26 Mar '12

Compal JHL90 (schematics under NDA): CPU: merom/penryn support (µPGA-478) 667/800/1066 MHz FSB Intel Cantiga + ICH9M 2x DDR2 SO-DIMM GPU on MXM-II slot (nvidia 9600M GT) EC: ENE KB926 (datasheet under NDA, firmware description as part of service manual — very well documented) ——— Flash chips: One on SMBus — contains some information which can be changed by retailer, re-branding is common practice One on SPI bus connected to SB — ¿¿¿¿¿¿¿ for iTPM and HDCP in 8M (1MiB) One on SPI bus connected to EC — Contains EC firmware, BIOS (PHOENIX) and VBIOS (NVIDIA) in 16M (2MiB) ——— lspci -tvvv output ——— -[0000:00]-+-00.0 Intel Corporation Mobile 4 Series Chipset Memory Controller Hub +-01.0-[01]----00.0 NVIDIA Corporation G96 [GeForce 9600M GT] +-1a.0 Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #4 +-1a.1 Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #5 +-1a.2 Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #6 +-1a.7 Intel Corporation 82801I (ICH9 Family) USB2 EHCI Controller #2 +-1b.0 Intel Corporation 82801I (ICH9 Family) HD Audio Controller +-1c.0-[02-03]-- +-1c.1-[08]-- +-1c.2-[0e]----00.0 Atheros Communications Inc. AR242x / AR542x Wireless Network Adapter (PCI-Express) +-1c.3-[14]----00.0 Realtek Semiconductor Co., Ltd. RTL8111/8168B PCI Express Gigabit Ethernet controller +-1c.4-[1a]--+-00.0 JMicron Technology Corp. SD/MMC Host Controller | +-00.2 JMicron Technology Corp. Standard SD Host Controller | +-00.3 JMicron Technology Corp. MS Host Controller | \-00.4 JMicron Technology Corp. xD Host Controller +-1d.0 Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #1 +-1d.1 Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #2 +-1d.2 Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #3 +-1d.7 Intel Corporation 82801I (ICH9 Family) USB2 EHCI Controller #1 +-1e.0-[26]-- +-1f.0 Intel Corporation ICH9M LPC Interface Controller +-1f.2 Intel Corporation 82801IBM/IEM (ICH9M/ICH9M-E) 4 port SATA Controller [AHCI mode] \-1f.3 Intel Corporation 82801I (ICH9 Family) SMBus Controller ——— Features LPC connector(s) ☺ ——— What i want to do (for now): · Connect second main spi flash on top of existing one with help of chip select (only one resistor has to be removed from pcb for that!) · Connect additional Super I/O (W83627THF/W83627THG) with hefras pin active to get configuration register on 4Eh instead of 2Eh (which is being used by EC). No conflicts have been found (yet). PCB with Super I/O IC will reside in place of Optical Disk Drive (RepRapped in future, for now from scrap HDPE). · Run SerialICE thanks to the rs232 on that additional Super I/O · Port flashrom if using phoenix tool will be not possible. ——— What i want to have: · rw access to WikiPage about JHL90 ——— Yes, i know that porting coreboot to this board will be hard and painful, and could be even completely unsuccessful.

1 0

Re: [coreboot] asus l1n64 - this is damn Nvidia
by Marc Jones 26 Mar '12

26 Mar '12

Hi Jullian On Sun, Mar 25, 2012 at 3:11 PM, Julian Shulika <hercares(a)gmail.com> wrote: > coreboot-4.0-2135-gccee625-dirty Fri Mar 23 15:02:04 EDT 2012 starting... > > BSP Family_Model: 00100f42 > > *sysinfo range: [000cc000,000cdfa0] > > bsp_apicid = 00 > cpu_init_detectedx = 00000000 > microcode: equivalent rev id = 0x1041, current patch id = 0x00000000 > microcode: patch id to apply = 0x01000086 > microcode: updated to patch id = 0x01000086 success > > POST: 0x33 > cpuSetAMDMSR done > POST: 0x34 > Enter amd_ht_init() > AMD_CB_EventNotify() > event class: 05 > event: 1004 > data: 04 00 02 01 > AMD_CB_ManualBUIDSwapList() > AMD_CB_EventNotify() > event class: 05 > event: 2006 > data: 04 00 01 ff > Exit amd_ht_init() > POST: 0x35 > cpuSetAMDPCI 00 done > cpuSetAMDPCI 01 done > Prep FID/VID Node:00 > F3x80: e600e681 > F3x84: 80e641e6 > F3xD4: c3310f24 > F3xD8: 03001615 > F3xDC: 00006322 > Prep FID/VID Node:01 > F3x80: e600e681 > F3x84: 80e641e6 > F3xD4: c3310f24 > F3xD8: 03001615 > F3xDC: 00006322 > setup_remote_node: 01 done > Start node 01 done. > POST: 0x36 > core0 started: POST: 0x30 > core0: --- { APICID = 04 NODEID = 01 COREID = 00} --- > 01microcode: equivalent rev id = 0x1041, current patch id = 0x00000000 > > itarmit_cortochoedr_e:c opreast(ch) > d to apply = 0x01000086 > iincriotc nooded:e: u0pd0a t ceodr teos : p0a3tc h > id = 0x01000086 success > > StcapurSt eottAhMDeMrS cRo re - nodeid: 00 cores: 03 > :nit dnoondee > ( 0i1 ni tc_ofriedsv:i d0_3a p > -stSatgaer1t) o atphiecri dco: re04 > s nFIoDdeVIiDd :o n0 1A P :c o0r4e > : 03 > POST: 0x37 > started ap apicid: PPPOOOSSSTTT::: 000xxx333000 > > > x cccooorrreeexxx::: --------- {{{ AAAPPPIIICCCIIIDDD === > 000132 NNNOOODDDEEEIIIDDD === 00x > > > * mAm33m3Pii00i0c ccrr0roo1occcooodddeee::: > eeeqqquuuiiivvvaaallleeennnttt rrreeevvv iiiddd === 0 > > > s > > > m tedmm > RE iciiccccocrrororroeorocecxcexoxoo: d:d:d e e e :-: :- - - -p-p-p-a a-at > t{t {c{cc Ah h hA P A iPiIiPIdIddCO > R > R > EIEIIDD D= == 0 10032}} }- -------- > > > tmmii*icc crrArmmmooPoiiiccc cccrroo0orooodd2dceccee::o:oodd d eueeuup:p::p > d dd eaeaeaqtqtqteueueuididdiv v a > t > t > h c > h > h > iiiddd === 000xxx000000000000000000000000 > > > AicAcMMapuuruSStSeeeemmdtmittiA > 6 McrorDDrDoMcoMMScSocSoRoRRde d d e:e:: p appaattcthcchh i iidd dt > ttoo oa aapppplppllyy y= = = 0 06 > > > u*mi iicAccrrPro ooc c0 cd3ooddododdoonnenee::ee:e > u > u > pppdddaaattteeeddd tttooo pppaaatttccchhh iiiddd === > 000xxx000111000000000000888666 sssuuucs > > > > > > AfAfMiipaipiunnurnuSSiiStietetteetdt_t__Af > MiMDDddDdMvMMvviSiSSiRdRddR _ _ _aaappp(((ssstttaaagggeee111))) > aaapppiiiccciiiddd::: 000123 > > > F*III DDDAVVVP III ddDDD0dooo 5nnnooonneeen > A > A > APPP::: 000123 > > > itiiiannnriiitttet__d_fff > iidddvvviiiddd___aaappp(((ssstttaaagggeee111))) aaapppiiiccciiiddd::: > 000657 > > > FFF*I IIDDADVVVPIII D0DD 6 ooonnn AAAPPP::: 000657 > > > started > * AP 07started > > POST: 0x38 > > Begin FIDVID MSR 0xc0010071 0x30b000a3 0x40034040 > POST: 0x39 > FIDVID on BSP, APIC_id: 00 > BSP fid = 10600 > Wait for AP stage 1: ap_apicid = 1 > readback = 1010601 > common_fid(packed) = 10600 > Wait for AP stage 1: ap_apicid = 2 > readback = 2010601 > common_fid(packed) = 10600 > Wait for AP stage 1: ap_apicid = 3 > readback = 3010601 > common_fid(packed) = 10600 > Wait for AP stage 1: ap_apicid = 4 > readback = 4010601 > common_fid(packed) = 10600 > Wait for AP stage 1: ap_apicid = 5 > readback = 5010601 > common_fid(packed) = 10600 > Wait for AP stage 1: ap_apicid = 6 > readback = 6010601 > common_fid(packed) = 10600 > Wait for AP stage 1: ap_apicid = 7 > readback = 7010601 > common_fid(packed) = 10600 > common_fid = 10600 > FID Change Node:00, F3xD4: c3310f26 > FID Change Node:01, F3xD4: c3310f26 > POST: 0x3a > End FIDVIDMSR 0xc0010071 0x30b000a3 0x30003040 > mcp55_num:01 > ...WARM RESET... After the warm reset, coreboot should start again and get past the fid/vid setup and to the memory setup. Does it have a problem doing the warm reset? That could be a southbridge reset problem. marc -- http://se-eng.com

1 0

Re: [coreboot] asus l1n64 - this is damn Nvidia
by Marc Jones 26 Mar '12

26 Mar '12

Hi Julian, On Sun, Mar 25, 2012 at 3:09 PM, Julian Shulika <hercares(a)gmail.com> wrote: > > > ---------- Forwarded message ---------- > From: Julian Shulika <hercares(a)gmail.com> > Date: 2012/3/26 > Subject: Re: coreboot and opteron 8431 > To: Arne Georg Gleditsch <arne(a)gledits.ch> > > > I tried to port asus l1n64 more than one year. This board also based on > mcp55,this is only one board for AMD 4x4 platform. It differs from other > similar board by different scheme > > > Tyan S2912, supermicro h8dmr have > connection diagram, if I use just cpu0,I can't use second mcp55 mcp55 > <->cpu1 <-> cpu0 <-> mcp55 > > > Asus L1N64 has different connection diagram mcp55 <-> > mcp55<->cpu0 <-> cpu1 > I saw your posts when you try to help guy with supermicro board,but > I'm stuck in one place,because I have not reached to memory init, I think > it's because of wrong devicetree. Could you please look at lspci output, may > be you can see something... > Thanks for your work done The devicetree isn't really used prior to memory init. Most of what you should examine is called in romstage.c. Marc > > chip northbridge/amd/amdfam10/root_complex # Root complex > device lapic_cluster 0 on # (L)APIC cluster > chip cpu/amd/socket_F_1207 # CPU socket > device lapic 0 on end # Local APIC of the CPU > end > end > device pci_domain 0 on # PCI domain > subsystemid 0x10de 0x81fb inherit > chip northbridge/amd/amdfam10 # Northbridge / RAM controller > device pci 18.0 on end > device pci 18.0 on end > chip southbridge/nvidia/mcp55 # Southbridge > device pci 0.0 on end # HT > device pci 1.0 on end # LPC > device pci 1.1 on end # LPC > device pci 5.1 on end # SATA 1 > device pci 5.2 on end # SATA 2 > device pci a.0 off end # PCI E 5 > device pci f.0 off end # PCI E 5 > end > device pci 18.0 on # SB on link 2 > chip southbridge/nvidia/mcp55 # Southbridge > device pci 0.0 on end # HT > device pci 1.0 on # LPC > chip superio/ite/it8716f # Super I/O > device pnp 2e.0 on # Floppy > io 0x60 = 0x3f0 > irq 0x70 = 6 > drq 0x74 = 2 > end > device pnp 2e.1 on # Com1 > io 0x60 = 0x3f8 > irq 0x70 = 4 > end > device pnp 2e.2 off # Com2 (N/A) > end > device pnp 2e.3 on # Parallel port > io 0x60 = 0x378 > io 0x62 = 0x000 > irq 0x70 = 7 > drq 0x74 = 4 > end > device pnp 2e.4 on # Environment controller > io 0x60 = 0x290 > io 0x62 = 0x000 > irq 0x70 = 0 > end > device pnp 2e.5 on # PS/2 keyboard > io 0x60 = 0x60 > io 0x62 = 0x64 > irq 0x70 = 1 # PS/2 keyboard IRQ > end > device pnp 2e.6 on # PS/2 mouse > irq 0x70 = 12 # PS/2 mouse IRQ > end > device pnp 2e.7 off # GPIO > io 0x60 = 0x0000 # SMI# Normal Run Access > io 0x62 = 0x800 # Simple I/O > io 0x64 = 0x0000 # Serial Flash I/F > end > device pnp 2e.8 off # MIDI (N/A) > end > device pnp 2e.9 off # Game port (N/A) > end > device pnp 2e.a off # Consumer IR (N/A) > end > end # Super I/O > end > device pci 1.1 on # SM 0 > chip drivers/generic/generic # DIMM 0-0-0 > device i2c 50 on end > end > chip drivers/generic/generic # DIMM 0-0-1 > device i2c 51 on end > end > chip drivers/generic/generic # DIMM 0-1-0 > device i2c 52 on end > end > chip drivers/generic/generic # DIMM 0-1-1 > device i2c 53 on end > end > > end > > device pci 2.0 on end # USB 1.1 > device pci 2.1 on end # USB 2 > device pci 4.0 on end # IDE > device pci 5.0 on end # SATA 0 > device pci 5.1 on end # SATA 1 > device pci 5.2 on end # SATA 2 > device pci 6.0 on # PCI > device pci 6.0 on end > end > device pci 6.1 on end # AZA > device pci 8.0 on end # NIC > device pci 9.0 on end # NIC > device pci a.0 on end # PCI E 5 > device pci d.0 on end # PCI E 2 > device pci e.0 on end # PCI E 1 > device pci f.0 on end # PCI E 0 > register "ide0_enable" = "1" > register "sata0_enable" = "1" > register "sata1_enable" = "1" > # 1: SMBus under 2e.8, 2: SM0 3: SM1 > register "mac_eeprom_smbus" = "3" > register "mac_eeprom_addr" = "0x51" > end > end > device pci 18.1 on end > device pci 18.2 on end > device pci 18.3 on end > device pci 18.4 on end > end > end > # chip drivers/generic/debug > # device pnp 0.0 off end # chip name > # device pnp 0.1 on end # pci_regs_all > # device pnp 0.2 on end # mem > # device pnp 0.3 off end # cpuid > # device pnp 0.4 on end # smbus_regs_all > # device pnp 0.5 off end # dual core msr > # device pnp 0.6 off end # cache size > # device pnp 0.7 off end # tsc > # device pnp 0.8 off end # io > # device pnp 0.9 off end # io > # end > end > > > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot -- http://se-eng.com

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Patch set updated for coreboot: 82d775d Add bifferboard
by Rudolf Marek 26 Mar '12

26 Mar '12

Rudolf Marek (r.marek(a)assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/810 -gerrit commit 82d775d53fa2b4394e78b28e3a7ad7d06b0644a5 Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Sun Mar 25 19:55:43 2012 +0200 Add bifferboard This commit adds support for Bifferboard, a 32MB 486 PC Change-Id: Iad790ebf242ef07bf6298f8e3577783e5e743113 Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> --- src/mainboard/Kconfig | 3 + src/mainboard/bifferos/Kconfig | 36 ++++++++++++ src/mainboard/bifferos/bifferboard/Kconfig | 19 +++++++ src/mainboard/bifferos/bifferboard/Makefile.inc | 1 + src/mainboard/bifferos/bifferboard/chip.h | 23 ++++++++ src/mainboard/bifferos/bifferboard/devicetree.cb | 8 +++ src/mainboard/bifferos/bifferboard/mainboard.c | 26 +++++++++ src/mainboard/bifferos/bifferboard/romstage.c | 64 ++++++++++++++++++++++ 8 files changed, 180 insertions(+), 0 deletions(-) diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig index fe70211..a968b51 100644 --- a/src/mainboard/Kconfig +++ b/src/mainboard/Kconfig @@ -36,6 +36,8 @@ config VENDOR_AZZA bool "AZZA" config VENDOR_BCOM bool "BCOM" +config VENDOR_BIFFEROS + bool "Bifferos" config VENDOR_BIOSTAR bool "Biostar" config VENDOR_BROADCOM @@ -143,6 +145,7 @@ source "src/mainboard/avalue/Kconfig" source "src/mainboard/axus/Kconfig" source "src/mainboard/azza/Kconfig" source "src/mainboard/bcom/Kconfig" +source "src/mainboard/bifferos/Kconfig" source "src/mainboard/biostar/Kconfig" source "src/mainboard/broadcom/Kconfig" source "src/mainboard/compaq/Kconfig" diff --git a/src/mainboard/bifferos/Kconfig b/src/mainboard/bifferos/Kconfig new file mode 100644 index 0000000..98cbab8 --- /dev/null +++ b/src/mainboard/bifferos/Kconfig @@ -0,0 +1,36 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +if VENDOR_BIFFEROS + +choice + prompt "Mainboard model" + +config BOARD_BIFFEROS_BIFFERBOARD + bool "Bifferboard" + +endchoice + +source "src/mainboard/bifferos/bifferboard/Kconfig" + +config MAINBOARD_VENDOR + string + default "Bifferos" + +endif # VENDOR_BIFFEROS diff --git a/src/mainboard/bifferos/bifferboard/Kconfig b/src/mainboard/bifferos/bifferboard/Kconfig new file mode 100644 index 0000000..4b4b5da --- /dev/null +++ b/src/mainboard/bifferos/bifferboard/Kconfig @@ -0,0 +1,19 @@ +if BOARD_BIFFEROS_BIFFERBOARD + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select ARCH_X86 + select ROMCC + select BOARD_ROMSIZE_KB_128 + select NORTHBRIDGE_RDC_R8610 + select SOUTHBRIDGE_RDC_R8610 + +config MAINBOARD_DIR + string + default bifferos/bifferboard + +config MAINBOARD_PART_NUMBER + string + default "Bifferos" + +endif # BOARD_BIFFEROS_BIFFERBOARD diff --git a/src/mainboard/bifferos/bifferboard/Makefile.inc b/src/mainboard/bifferos/bifferboard/Makefile.inc new file mode 100644 index 0000000..7678401 --- /dev/null +++ b/src/mainboard/bifferos/bifferboard/Makefile.inc @@ -0,0 +1 @@ +ROMCCFLAGS := -mcpu=i386 -O diff --git a/src/mainboard/bifferos/bifferboard/chip.h b/src/mainboard/bifferos/bifferboard/chip.h new file mode 100644 index 0000000..be42783 --- /dev/null +++ b/src/mainboard/bifferos/bifferboard/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; + diff --git a/src/mainboard/bifferos/bifferboard/devicetree.cb b/src/mainboard/bifferos/bifferboard/devicetree.cb new file mode 100644 index 0000000..757ddd5 --- /dev/null +++ b/src/mainboard/bifferos/bifferboard/devicetree.cb @@ -0,0 +1,8 @@ +chip northbridge/rdc/r8610 + device pci_domain 0 on + device pci 0.0 on end + chip southbridge/rdc/r8610 # Southbridge + device pci 7.0 on end # SB + end + end +end diff --git a/src/mainboard/bifferos/bifferboard/mainboard.c b/src/mainboard/bifferos/bifferboard/mainboard.c new file mode 100644 index 0000000..5840f95 --- /dev/null +++ b/src/mainboard/bifferos/bifferboard/mainboard.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Rudolf Marek <r.marek(a)assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include "chip.h" + +struct chip_operations mainboard_ops = { + CHIP_NAME("Bifferos Bifferboard") +}; + diff --git a/src/mainboard/bifferos/bifferboard/romstage.c b/src/mainboard/bifferos/bifferboard/romstage.c new file mode 100644 index 0000000..854aaa9 --- /dev/null +++ b/src/mainboard/bifferos/bifferboard/romstage.c @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Rudolf Marek <r.marek(a)assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/romcc_io.h> +#include <arch/hlt.h> +#include <pc80/mc146818rtc.h> +#include <console/console.h> +#include <cpu/x86/cache.h> + +static void main(void) +{ + uint32_t tmp; + post_code(0x05); + + /* Set timer1 to pulse generator 15us for memory refresh */ + outb(0x54, 0x43); + outb(0x12, 0x41); + + /* CPU setup, romcc pukes on invd() */ + asm volatile ("invd"); + enable_cache(); + + /* Set serial base */ + pci_write_config32(PCI_DEV(0,7,0), 0x54, 0x3f8); + /* serial IRQ disable, LPC disable, COM2 goes to LPC, internal UART for COM1 */ + pci_write_config32(PCI_DEV(0,7,0), 0x50, 0x84101012); + + console_init(); + + /* memory init */ + pci_write_config32(PCI_DEV(0,0,0), 0x68, 0x6c99f); + pci_write_config32(PCI_DEV(0,0,0), 0x6c, 0x800451); + pci_write_config32(PCI_DEV(0,0,0), 0x70, 0x4000003); + + /* memory phase/buffer strength for read and writes */ + tmp = pci_read_config32(PCI_DEV(0,0,0), 0x64); + tmp &= 0x0FF00FFFF; + tmp |= 0x790000; + pci_write_config32(PCI_DEV(0,0,0), 0x64, tmp); + /* Route Cseg, Dseg, Eseg and Fseg to RAM */ + pci_write_config32(PCI_DEV(0,0,0), 0x84, 0x3ffffff0); +} +

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coreboot March 2012