coreboot March 2012

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New patch to review for coreboot: 49f816c Add bifferboard
by Rudolf Marek 25 Mar '12

25 Mar '12

Rudolf Marek (r.marek(a)assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/810 -gerrit commit 49f816cbeab72a521461018644bdf08c6f6259c2 Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Sun Mar 25 19:55:43 2012 +0200 Add bifferboard This commit adds support for Bifferboard, a 32MB 486 PC Change-Id: Iad790ebf242ef07bf6298f8e3577783e5e743113 Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> --- src/mainboard/Kconfig | 3 + src/mainboard/bifferos/Kconfig | 36 ++++++++++++ src/mainboard/bifferos/bifferboard/Kconfig | 19 +++++++ src/mainboard/bifferos/bifferboard/Makefile.inc | 1 + src/mainboard/bifferos/bifferboard/chip.h | 23 ++++++++ src/mainboard/bifferos/bifferboard/devicetree.cb | 8 +++ src/mainboard/bifferos/bifferboard/mainboard.c | 26 +++++++++ src/mainboard/bifferos/bifferboard/romstage.c | 64 ++++++++++++++++++++++ 8 files changed, 180 insertions(+), 0 deletions(-) diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig index fe70211..a968b51 100644 --- a/src/mainboard/Kconfig +++ b/src/mainboard/Kconfig @@ -36,6 +36,8 @@ config VENDOR_AZZA bool "AZZA" config VENDOR_BCOM bool "BCOM" +config VENDOR_BIFFEROS + bool "Bifferos" config VENDOR_BIOSTAR bool "Biostar" config VENDOR_BROADCOM @@ -143,6 +145,7 @@ source "src/mainboard/avalue/Kconfig" source "src/mainboard/axus/Kconfig" source "src/mainboard/azza/Kconfig" source "src/mainboard/bcom/Kconfig" +source "src/mainboard/bifferos/Kconfig" source "src/mainboard/biostar/Kconfig" source "src/mainboard/broadcom/Kconfig" source "src/mainboard/compaq/Kconfig" diff --git a/src/mainboard/bifferos/Kconfig b/src/mainboard/bifferos/Kconfig new file mode 100644 index 0000000..98cbab8 --- /dev/null +++ b/src/mainboard/bifferos/Kconfig @@ -0,0 +1,36 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +if VENDOR_BIFFEROS + +choice + prompt "Mainboard model" + +config BOARD_BIFFEROS_BIFFERBOARD + bool "Bifferboard" + +endchoice + +source "src/mainboard/bifferos/bifferboard/Kconfig" + +config MAINBOARD_VENDOR + string + default "Bifferos" + +endif # VENDOR_BIFFEROS diff --git a/src/mainboard/bifferos/bifferboard/Kconfig b/src/mainboard/bifferos/bifferboard/Kconfig new file mode 100644 index 0000000..4b4b5da --- /dev/null +++ b/src/mainboard/bifferos/bifferboard/Kconfig @@ -0,0 +1,19 @@ +if BOARD_BIFFEROS_BIFFERBOARD + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select ARCH_X86 + select ROMCC + select BOARD_ROMSIZE_KB_128 + select NORTHBRIDGE_RDC_R8610 + select SOUTHBRIDGE_RDC_R8610 + +config MAINBOARD_DIR + string + default bifferos/bifferboard + +config MAINBOARD_PART_NUMBER + string + default "Bifferos" + +endif # BOARD_BIFFEROS_BIFFERBOARD diff --git a/src/mainboard/bifferos/bifferboard/Makefile.inc b/src/mainboard/bifferos/bifferboard/Makefile.inc new file mode 100644 index 0000000..7678401 --- /dev/null +++ b/src/mainboard/bifferos/bifferboard/Makefile.inc @@ -0,0 +1 @@ +ROMCCFLAGS := -mcpu=i386 -O diff --git a/src/mainboard/bifferos/bifferboard/chip.h b/src/mainboard/bifferos/bifferboard/chip.h new file mode 100644 index 0000000..be42783 --- /dev/null +++ b/src/mainboard/bifferos/bifferboard/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; + diff --git a/src/mainboard/bifferos/bifferboard/devicetree.cb b/src/mainboard/bifferos/bifferboard/devicetree.cb new file mode 100644 index 0000000..757ddd5 --- /dev/null +++ b/src/mainboard/bifferos/bifferboard/devicetree.cb @@ -0,0 +1,8 @@ +chip northbridge/rdc/r8610 + device pci_domain 0 on + device pci 0.0 on end + chip southbridge/rdc/r8610 # Southbridge + device pci 7.0 on end # SB + end + end +end diff --git a/src/mainboard/bifferos/bifferboard/mainboard.c b/src/mainboard/bifferos/bifferboard/mainboard.c new file mode 100644 index 0000000..5840f95 --- /dev/null +++ b/src/mainboard/bifferos/bifferboard/mainboard.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Rudolf Marek <r.marek(a)assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include "chip.h" + +struct chip_operations mainboard_ops = { + CHIP_NAME("Bifferos Bifferboard") +}; + diff --git a/src/mainboard/bifferos/bifferboard/romstage.c b/src/mainboard/bifferos/bifferboard/romstage.c new file mode 100644 index 0000000..fc0dfea --- /dev/null +++ b/src/mainboard/bifferos/bifferboard/romstage.c @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Rudolf Marek <r.marek(a)assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/romcc_io.h> +#include <arch/hlt.h> +#include <pc80/mc146818rtc.h> +#include <console/console.h> +#include <cpu/x86/cache.h> + +static void main(void) +{ + uint32_t tmp; + post_code(0x05); + + /* Set timer1 to pulse generator 15us for memory refresh */ + outb(0x54, 0x43); + outb(0x12, 0x41); + + /* CPU setup, romcc pukes on invd() */ + asm volatile ("invd"); + enable_cache(); + + /* Set serial base */ + pci_write_config32(PCI_DEV(0,7,0), 0x54, 0x3f8); + /* serial IRQ disable, LPC disable, COM2 goes to LPC, internal UART for COM1 */ + pci_write_config32(PCI_DEV(0,7,0), 0x50, 0x84101012); + + console_init(); + + /* memory init */ + pci_write_config32(PCI_DEV(0,0,0), 0x68, 0x6c99f); + pci_write_config32(PCI_DEV(0,0,0), 0x6c, 0x800451); + pci_write_config32(PCI_DEV(0,0,0), 0x70, 0x4000003); + + /* memory phase/buffer strength for read and writes */ + tmp = pci_read_config32(PCI_DEV(0,0,0), 0x64); + tmp &= 0x0FF00FFFF; + tmp |= 0x790000; + pci_write_config32(PCI_DEV(0,0,0), 0x64, tmp); + /* Unknown */ + pci_write_config32(PCI_DEV(0,0,0), 0x84, 0x3ff00000); +} +

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New patch to review for coreboot: 1040337 Add 64KB romchip chip size
by Rudolf Marek 25 Mar '12

25 Mar '12

Rudolf Marek (r.marek(a)assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/809 -gerrit commit 10403372eb4c13fb7dec98bfeda1972bf6217faa Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Sun Mar 25 19:19:03 2012 +0200 Add 64KB romchip chip size This is handy for bifferboard to provide same size as original bootloader. Change-Id: I179917d8c6354fa55cebdd70918a96cd299c4f3c Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> --- src/mainboard/Kconfig | 10 ++++++++++ 1 files changed, 10 insertions(+), 0 deletions(-) diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig index 5de47c3..fe70211 100644 --- a/src/mainboard/Kconfig +++ b/src/mainboard/Kconfig @@ -188,6 +188,8 @@ source "src/mainboard/via/Kconfig" source "src/mainboard/winent/Kconfig" source "src/mainboard/wyse/Kconfig" +config BOARD_ROMSIZE_KB_64 + bool config BOARD_ROMSIZE_KB_128 bool config BOARD_ROMSIZE_KB_256 @@ -208,6 +210,7 @@ config BOARD_ROMSIZE_KB_16384 # TODO: No help text possible for choice fields? choice prompt "ROM chip size" + default COREBOOT_ROMSIZE_KB_64 if BOARD_ROMSIZE_KB_64 default COREBOOT_ROMSIZE_KB_128 if BOARD_ROMSIZE_KB_128 default COREBOOT_ROMSIZE_KB_256 if BOARD_ROMSIZE_KB_256 default COREBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512 @@ -222,6 +225,11 @@ choice The build system will take care of creating a coreboot.rom file of the matching size. +config COREBOOT_ROMSIZE_KB_64 + bool "64 KB" + help + Choose this option if you have a 64 KB ROM chip. + config COREBOOT_ROMSIZE_KB_128 bool "128 KB" help @@ -267,6 +275,7 @@ endchoice # Map the config names to an integer (KB). config COREBOOT_ROMSIZE_KB int + default 64 if COREBOOT_ROMSIZE_KB_64 default 128 if COREBOOT_ROMSIZE_KB_128 default 256 if COREBOOT_ROMSIZE_KB_256 default 512 if COREBOOT_ROMSIZE_KB_512 @@ -279,6 +288,7 @@ config COREBOOT_ROMSIZE_KB # Map the config names to a hex value (bytes). config ROM_SIZE hex + default 0x10000 if COREBOOT_ROMSIZE_KB_64 default 0x20000 if COREBOOT_ROMSIZE_KB_128 default 0x40000 if COREBOOT_ROMSIZE_KB_256 default 0x80000 if COREBOOT_ROMSIZE_KB_512

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New patch to review for coreboot: 764f0c3 Add support for RDC R8610 Southbridge
by Rudolf Marek 25 Mar '12

25 Mar '12

Rudolf Marek (r.marek(a)assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/808 -gerrit commit 764f0c304f357b04105c2fa7e507ae0b6776e34b Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Sun Mar 25 18:16:11 2012 +0200 Add support for RDC R8610 Southbridge So far it just setups things right for Bifferboard. We may change it in the future to fit other hardware. Change-Id: I1c4ccff4e47b9cb9e31a738f038fc4f4ebe59087 Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> --- src/southbridge/Kconfig | 1 + src/southbridge/Makefile.inc | 1 + src/southbridge/rdc/Kconfig | 1 + src/southbridge/rdc/Makefile.inc | 1 + src/southbridge/rdc/r8610/Kconfig | 26 +++++++ src/southbridge/rdc/r8610/Makefile.inc | 20 ++++++ src/southbridge/rdc/r8610/bootblock.c | 29 ++++++++ src/southbridge/rdc/r8610/r8610.c | 118 ++++++++++++++++++++++++++++++++ 8 files changed, 197 insertions(+), 0 deletions(-) diff --git a/src/southbridge/Kconfig b/src/southbridge/Kconfig index 77fe385..31b7cc6 100644 --- a/src/southbridge/Kconfig +++ b/src/southbridge/Kconfig @@ -2,6 +2,7 @@ source src/southbridge/amd/Kconfig source src/southbridge/broadcom/Kconfig source src/southbridge/intel/Kconfig source src/southbridge/nvidia/Kconfig +source src/southbridge/rdc/Kconfig source src/southbridge/ricoh/Kconfig source src/southbridge/sis/Kconfig source src/southbridge/ti/Kconfig diff --git a/src/southbridge/Makefile.inc b/src/southbridge/Makefile.inc index b7e04db..130d459 100644 --- a/src/southbridge/Makefile.inc +++ b/src/southbridge/Makefile.inc @@ -2,6 +2,7 @@ subdirs-y += amd subdirs-y += broadcom subdirs-y += intel subdirs-y += nvidia +subdirs-y += rdc subdirs-y += ricoh subdirs-y += sis subdirs-y += ti diff --git a/src/southbridge/rdc/Kconfig b/src/southbridge/rdc/Kconfig new file mode 100644 index 0000000..50ef475 --- /dev/null +++ b/src/southbridge/rdc/Kconfig @@ -0,0 +1 @@ +source src/southbridge/rdc/r8610/Kconfig diff --git a/src/southbridge/rdc/Makefile.inc b/src/southbridge/rdc/Makefile.inc new file mode 100644 index 0000000..34f3efd --- /dev/null +++ b/src/southbridge/rdc/Makefile.inc @@ -0,0 +1 @@ +subdirs-$(CONFIG_SOUTHBRIDGE_RDC_R8610) += r8610 diff --git a/src/southbridge/rdc/r8610/Kconfig b/src/southbridge/rdc/r8610/Kconfig new file mode 100644 index 0000000..e9941f0 --- /dev/null +++ b/src/southbridge/rdc/r8610/Kconfig @@ -0,0 +1,26 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008-2009 coresystems GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config SOUTHBRIDGE_RDC_R8610 + bool + +config BOOTBLOCK_SOUTHBRIDGE_INIT + string + default "southbridge/rdc/r8610/bootblock.c" + depends on SOUTHBRIDGE_RDC_R8610 diff --git a/src/southbridge/rdc/r8610/Makefile.inc b/src/southbridge/rdc/r8610/Makefile.inc new file mode 100644 index 0000000..24d76a8 --- /dev/null +++ b/src/southbridge/rdc/r8610/Makefile.inc @@ -0,0 +1,20 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007, 2009 Rudolf Marek <r.marek(a)assembler.cz> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +driver-y += r8610.c diff --git a/src/southbridge/rdc/r8610/bootblock.c b/src/southbridge/rdc/r8610/bootblock.c new file mode 100644 index 0000000..ec6d271 --- /dev/null +++ b/src/southbridge/rdc/r8610/bootblock.c @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Rudolf Marek <r.marek(a)assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <device/pci_def.h> + +static void bootblock_southbridge_init(void) { + uint32_t tmp; + tmp = pci_read_config32(PCI_DEV(0,7,0), 0x40); + /* decode all flash ranges */ + pci_write_config32(PCI_DEV(0,7,0), 0x40, tmp | 0x07ff0000); +} diff --git a/src/southbridge/rdc/r8610/r8610.c b/src/southbridge/rdc/r8610/r8610.c new file mode 100644 index 0000000..6b45669 --- /dev/null +++ b/src/southbridge/rdc/r8610/r8610.c @@ -0,0 +1,118 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Rudolf Marek <r.marek(a)assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <pc80/i8259.h> +#include <stdlib.h> + +static const unsigned char enetIrqs[4] = { 10, 0, 0, 0 }; +static const unsigned char usbIrqs[4] = { 15, 14, 0, 0 }; + +static void pci_routing_fixup(struct device *dev) +{ + pci_assign_irqs(0, 0x8, enetIrqs); + pci_assign_irqs(0, 0xa, usbIrqs); +} + +static void r8610_init(struct device *dev) +{ + device_t nb_dev; + u32 tmp; + + printk(BIOS_DEBUG, "r8610 init\n"); + + /* clear DMA? */ + outb(0x4, 0x8); + outb(0x4, 0x10); + + outb(0xfc, 0x61); + + /* Set serial base */ + pci_write_config32(dev, 0x54, 0x3f8); + /* serial IRQ disable, LPC disable, COM2 goes to LPC, internal UART for COM1 */ + pci_write_config32(dev, 0x50, 0x84101012); + + /* Enable internal Port92, enable chipselect for flash */ + tmp = pci_read_config32(dev, 0x40); + pci_write_config32(dev, 0x40, tmp | 0x07FF0600); + + /* buffer strength SB pins */ + pci_write_config32(dev, 0x5c, 0x2315); + + /* EHCI 14, OHCI 15, MAC1 disable, MAC0 10, INTD 9, INTC 9, INTB 12, INTA INT10 */ + pci_write_config32(dev, 0x58, 0xdf0311b3); + + /* USB PHY control */ + nb_dev = dev_find_device(PCI_VENDOR_ID_RDC, + PCI_DEVICE_ID_RDC_R8610_NB, 0); + + tmp = pci_read_config32(nb_dev, 0xc0); + tmp |= 0x40000; + pci_write_config32(nb_dev, 0xc0, tmp); + + setup_i8259(); +} + +static void r8610_read_resources(device_t dev) +{ + struct resource *res; + + pci_dev_read_resources(dev); + + res = new_resource(dev, 1); + res->base = 0x0UL; + res->size = 0x1000UL; + res->limit = 0xffffUL; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + /* Reserve space for flash */ + res = new_resource(dev, 2); + res->base = 0xff800000; + res->size = 8*1024*1024; + res->limit = 0xffffffffUL; + res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | + IORESOURCE_ASSIGNED; +} + +static void southbridge_init(struct device *dev) +{ + r8610_init(dev); + pci_routing_fixup(dev); +} + +static struct device_operations r8610_sb_ops = { + .read_resources = r8610_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = &southbridge_init, + .scan_bus = scan_static_bus, + .enable = 0, + .ops_pci = 0, +}; + +static const struct pci_driver lpc_driver __pci_driver = { + .ops = &r8610_sb_ops, + .vendor = PCI_VENDOR_ID_RDC, + .device = PCI_DEVICE_ID_RDC_R8610_SB, +}; +

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New patch to review for coreboot: 2b13a44 Add the support for RDC R8610 Northbridge
by Rudolf Marek 25 Mar '12

25 Mar '12

Rudolf Marek (r.marek(a)assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/807 -gerrit commit 2b13a443d08efd84dc0cfda7e4c980e641ff2aba Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Sun Mar 25 18:14:02 2012 +0200 Add the support for RDC R8610 Northbridge So far the it just setups the internal resource management for coreboot and detects the memory size. Change-Id: I8506390fa6656abfa40d92b8f6ede9b91fe98680 Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> --- src/northbridge/Kconfig | 1 + src/northbridge/Makefile.inc | 1 + src/northbridge/rdc/Kconfig | 1 + src/northbridge/rdc/Makefile.inc | 2 + src/northbridge/rdc/r8610/Kconfig | 2 + src/northbridge/rdc/r8610/Makefile.inc | 21 +++++ src/northbridge/rdc/r8610/chip.h | 24 ++++++ src/northbridge/rdc/r8610/northbridge.c | 135 +++++++++++++++++++++++++++++++ 8 files changed, 187 insertions(+), 0 deletions(-) diff --git a/src/northbridge/Kconfig b/src/northbridge/Kconfig index eeedc89..b2b8abe 100644 --- a/src/northbridge/Kconfig +++ b/src/northbridge/Kconfig @@ -1,3 +1,4 @@ source src/northbridge/amd/Kconfig source src/northbridge/intel/Kconfig +source src/northbridge/rdc/Kconfig source src/northbridge/via/Kconfig diff --git a/src/northbridge/Makefile.inc b/src/northbridge/Makefile.inc index 57273cf..283ba4e 100644 --- a/src/northbridge/Makefile.inc +++ b/src/northbridge/Makefile.inc @@ -1,3 +1,4 @@ subdirs-y += amd subdirs-y += intel +subdirs-y += rdc subdirs-y += via diff --git a/src/northbridge/rdc/Kconfig b/src/northbridge/rdc/Kconfig new file mode 100644 index 0000000..73ac740 --- /dev/null +++ b/src/northbridge/rdc/Kconfig @@ -0,0 +1 @@ +source src/northbridge/rdc/r8610/Kconfig diff --git a/src/northbridge/rdc/Makefile.inc b/src/northbridge/rdc/Makefile.inc new file mode 100644 index 0000000..766fea2 --- /dev/null +++ b/src/northbridge/rdc/Makefile.inc @@ -0,0 +1,2 @@ +subdirs-$(CONFIG_NORTHBRIDGE_RDC_R8610) += r8610 + diff --git a/src/northbridge/rdc/r8610/Kconfig b/src/northbridge/rdc/r8610/Kconfig new file mode 100644 index 0000000..85461b7 --- /dev/null +++ b/src/northbridge/rdc/r8610/Kconfig @@ -0,0 +1,2 @@ +config NORTHBRIDGE_RDC_R8610 + bool diff --git a/src/northbridge/rdc/r8610/Makefile.inc b/src/northbridge/rdc/r8610/Makefile.inc new file mode 100644 index 0000000..c976967 --- /dev/null +++ b/src/northbridge/rdc/r8610/Makefile.inc @@ -0,0 +1,21 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007 Corey Osgood <corey.osgood(a)gmail.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +driver-y += northbridge.c diff --git a/src/northbridge/rdc/r8610/chip.h b/src/northbridge/rdc/r8610/chip.h new file mode 100644 index 0000000..01c8356 --- /dev/null +++ b/src/northbridge/rdc/r8610/chip.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Corey Osgood <corey.osgood(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +struct northbridge_rdc_r8610_config { +}; + +extern struct chip_operations northbridge_rdc_r8610_ops; diff --git a/src/northbridge/rdc/r8610/northbridge.c b/src/northbridge/rdc/r8610/northbridge.c new file mode 100644 index 0000000..48d830c --- /dev/null +++ b/src/northbridge/rdc/r8610/northbridge.c @@ -0,0 +1,135 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Rudolf Marek <r.marek(a)assembler.cz> + * + * Based on qemu-x86/northbridge.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include <console/console.h> +#include <arch/io.h> +#include <stdint.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <stdlib.h> +#include <string.h> +#include <bitops.h> +#include <smbios.h> +#include "chip.h" + +#if CONFIG_WRITE_HIGH_TABLES==1 +#include <cbmem.h> +#endif + +static unsigned long get_memory_size(void) +{ + device_t nb_dev; + u8 size; + + nb_dev = dev_find_device(PCI_VENDOR_ID_RDC, + PCI_DEVICE_ID_RDC_R8610_NB, 0); + size = pci_read_config8(nb_dev, 0x6d) & 0xf; + return (2 * 1024) << size; +} + +static void cpu_pci_domain_set_resources(device_t dev) +{ + u32 pci_tolm = find_pci_tolm(dev->link_list); + unsigned long tomk = 0, tolmk; + int idx; + + tomk = get_memory_size(); + printk(BIOS_DEBUG, "Detected %lu Kbytes (%lu MiB) RAM.\n", + tomk, tomk / 1024); + + /* Compute the top of Low memory */ + tolmk = pci_tolm >> 10; + if (tolmk >= tomk) { + /* The PCI hole does not overlap the memory. */ + tolmk = tomk; + } + + /* Report the memory regions. */ + idx = 10; + ram_resource(dev, idx++, 0, 640); + ram_resource(dev, idx++, 768, tolmk - 768); + +#if CONFIG_WRITE_HIGH_TABLES==1 + /* Leave some space for ACPI, PIRQ and MP tables */ + high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; + high_tables_size = HIGH_MEMORY_SIZE; +#endif + + assign_resources(dev->link_list); +} + +static void cpu_pci_domain_read_resources(struct device *dev) +{ + pci_domain_read_resources(dev); +} + +#if CONFIG_GENERATE_SMBIOS_TABLES +static int rdc_get_smbios_data16(int handle, unsigned long *current) +{ + struct smbios_type16 *t = (struct smbios_type16 *)*current; + int len = sizeof(struct smbios_type16); + + memset(t, 0, sizeof(struct smbios_type16)); + t->type = SMBIOS_PHYS_MEMORY_ARRAY; + t->handle = handle; + t->length = len - 2; + t->location = 3; /* Location: System Board */ + t->use = 3; /* System memory */ + t->memory_error_correction = 3; /* No error correction */ + t->maximum_capacity = get_memory_size(); + *current += len; + return len; +} + +static int rdc_get_smbios_data(device_t dev, int *handle, unsigned long *current) +{ + int len; + len = rdc_get_smbios_data16(*handle, current); + *handle += 1; + return len; +} +#endif +static struct device_operations pci_domain_ops = { + .read_resources = cpu_pci_domain_read_resources, + .set_resources = cpu_pci_domain_set_resources, + .enable_resources = NULL, + .init = NULL, + .scan_bus = pci_domain_scan_bus, +#if CONFIG_GENERATE_SMBIOS_TABLES + .get_smbios_data = rdc_get_smbios_data, +#endif +}; + +static void enable_dev(struct device *dev) +{ + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) { + dev->ops = &pci_domain_ops; + pci_set_method(dev); + } +} + +struct chip_operations northbridge_rdc_r8610_ops = { + CHIP_NAME("RDC R8610 Northbridge") + .enable_dev = enable_dev, +};

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New patch to review for coreboot: ff534c2 Add RDC R8610 PCI IDs.
by Rudolf Marek 25 Mar '12

25 Mar '12

Rudolf Marek (r.marek(a)assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/806 -gerrit commit ff534c20a533823ae617a5585c0c447e54cb9794 Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Sun Mar 25 15:58:09 2012 +0200 Add RDC R8610 PCI IDs. Change-Id: I3f3585f15265aa1377f72ba23accf1adb08cb8ac Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> --- src/include/device/pci_ids.h | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 60399ef..a2d6884 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -1938,6 +1938,10 @@ #define PCI_VENDOR_ID_PDC 0x15e9 #define PCI_DEVICE_ID_PDC_1841 0x1841 +#define PCI_VENDOR_ID_RDC 0x17f3 +#define PCI_DEVICE_ID_RDC_R8610_NB 0x6020 +#define PCI_DEVICE_ID_RDC_R8610_SB 0x6030 + #define PCI_VENDOR_ID_ALTIMA 0x173b #define PCI_DEVICE_ID_ALTIMA_AC1000 0x03e8 #define PCI_DEVICE_ID_ALTIMA_AC9100 0x03ea

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Patch set updated for coreboot: 732b783 Makefile: split romstage linking to separate rules
by Kyösti Mälkki 25 Mar '12

25 Mar '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/803 -gerrit commit 732b7831334f501e74de23730c0c791ef86bf215 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Mar 25 17:21:21 2012 +0300 Makefile: split romstage linking to separate rules After change it is more clear how romstage is linked twice and with what scripts. Also with the change, it is easier to add some object of static size that need to be re-compiled for the 2nd link. One such object could be md5sum of executable. Change-Id: Ib34d1876071a51345c5c7319a0ed937868817fd1 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/Makefile.inc | 41 ++++++++++++++++++++++++++++------------- 1 files changed, 28 insertions(+), 13 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index fc3cd14..a437d18 100755 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -272,8 +272,7 @@ $(obj)/coreboot.pre: $(obj)/coreboot.romstage $(obj)/coreboot.pre1 $(CBFSTOOL) rm -f $@ cp $(obj)/coreboot.pre1 $@ $(CBFSTOOL) $@ add-stage $(obj)/romstage.elf \ - $(CONFIG_CBFS_PREFIX)/romstage x 0x$(shell cat $(obj)/location.txt) -#FIXME: location.txt might require an offset of header size + $(CONFIG_CBFS_PREFIX)/romstage x $(shell cat $(obj)/location.txt) ####################################################################### # Build the bootblock @@ -340,26 +339,42 @@ $(obj)/bootblock.elf: $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.o $(obj)/bootbl ####################################################################### # Build the romstage -$(obj)/coreboot.romstage: $(obj)/coreboot.pre1 $$(romstage-objs) $(obj)/romstage/ldscript.ld + +$(obj)/romstage.bin: $$(romstage-objs) $(obj)/romstage/link1st.ld + @printf " LINK $(subst $(obj)/,,$(@))\n" + $(CC) -nostdlib -nostartfiles -static -o $(obj)/romstage.elf -L$(obj) -T $(obj)/romstage/link1st.ld $(romstage-objs) + $(OBJCOPY) -O binary $(obj)/romstage.elf $@ + +$(obj)/coreboot.romstage: $$(romstage-objs) $(obj)/romstage/link2nd.ld @printf " LINK $(subst $(obj)/,,$(@))\n" - printf "ROMSTAGE_BASE = 0x0;\n" > $(obj)/location.ld - $(CC) -nostdlib -nostartfiles -static -o $(obj)/romstage.elf -L$(obj) -T $(obj)/romstage/ldscript.ld $(romstage-objs) - $(OBJCOPY) -O binary $(obj)/romstage.elf $(obj)/romstage.bin - printf "ROMSTAGE_BASE = 0x" > $(obj)/location.ld - $(CBFSTOOL) $(obj)/coreboot.pre1 locate $(obj)/romstage.bin $(CONFIG_CBFS_PREFIX)/romstage $(CONFIG_XIP_ROM_SIZE) > $(obj)/location.txt || { echo "The romstage is larger than XIP size. Please expand the CONFIG_XIP_ROM_SIZE" ; exit 1; } - cat $(obj)/location.txt >> $(obj)/location.ld - printf ';\n' >> $(obj)/location.ld - $(CC) -nostdlib -nostartfiles -static -o $(obj)/romstage.elf -L$(obj) -T $(obj)/romstage/ldscript.ld $(romstage-objs) + $(CC) -nostdlib -nostartfiles -static -o $(obj)/romstage.elf -L$(obj) -T $(obj)/romstage/link2nd.ld $(romstage-objs) $(NM) -n $(obj)/romstage.elf | sort > $(obj)/romstage.map $(OBJCOPY) --only-keep-debug $(obj)/romstage.elf $(obj)/romstage.debug $(OBJCOPY) --strip-debug $(obj)/romstage.elf $(OBJCOPY) --add-gnu-debuglink=$(obj)/romstage.debug $(obj)/romstage.elf $(OBJCOPY) -O binary $(obj)/romstage.elf $@ -$(obj)/romstage/ldscript.ld: $$(ldscripts) $(obj)/ldoptions +$(obj)/romstage/link1st.ld: $$(ldscripts) $(obj)/ldoptions @printf " GEN $(subst $(obj)/,,$(@))\n" mkdir -p $(obj)/romstage - printf '$(foreach ldscript,ldoptions location.ld $(ldscripts),INCLUDE "$(ldscript:$(obj)/%=%)"\n)' > $@ + rm -f $@ + printf "ROMSTAGE_BASE = 0x0;\n" > $@.tmp + printf '$(foreach ldscript,ldoptions $(ldscripts),INCLUDE "$(ldscript:$(obj)/%=%)"\n)' >> $@.tmp + mv $@.tmp $@ + +$(obj)/romstage/link2nd.ld: $(obj)/romstage/link1st.ld $(obj)/location.txt + @printf " GEN $(subst $(obj)/,,$(@))\n" + rm -f $@ + sed -e 's/^/ROMSTAGE_BASE = /g' -e 's/$$/;/g' $(obj)/location.txt > $@.tmp + sed -e '/ROMSTAGE_BASE/d' $(obj)/romstage/link1st.ld >> $@.tmp + mv $@.tmp $@ + +$(obj)/location.txt: $(obj)/coreboot.pre1 $(obj)/romstage.bin + rm -f $@ + $(CBFSTOOL) $(obj)/coreboot.pre1 locate $(obj)/romstage.bin $(CONFIG_CBFS_PREFIX)/romstage $(CONFIG_XIP_ROM_SIZE) > $@.tmp \ + || { echo "The romstage is larger than XIP size. Please expand the CONFIG_XIP_ROM_SIZE" ; exit 1; } + sed -i -e 's/^/0x/g' $@.tmp + mv $@.tmp $@ $(obj)/romstage/crt0.S: $$(crt0s) @printf " GEN $(subst $(obj)/,,$(@))\n"

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Re: [coreboot] l1n64
by Julian Shulika 25 Mar '12

25 Mar '12

Is that normal when while I see messages from serial beginning from post_code(0x30) to post_code(0x3a) in my pci post 0x80 all the time? 2012/3/25 Julian Shulika <hercares(a)gmail.com> > > > 2012/3/25 Julian Shulika <hercares(a)gmail.com> > >> ..... > > > >> And I can't find nothing about this string >> >> *+-0a.0-[82]-- >> \-0f.0-[81]--* >> >> These pci express won't work with one cpu for some reason. > >

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Re: [coreboot] l1n64
by Julian Shulika 25 Mar '12

25 Mar '12

2012/3/25 Julian Shulika <hercares(a)gmail.com> > ..... > And I can't find nothing about this string > > *+-0a.0-[82]-- > \-0f.0-[81]--* > > These pci express won't work with one cpu for some reason.

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l1n64
by Julian Shulika 25 Mar '12

25 Mar '12

Hi,everyone. I need help to correct my devicetree.cb. Can I create two sections for southbridge? I can't see post on my pci post card so pci tree is not correct yet. output from 'lspci -tv' and 'lspci -D' And I can't find nothing about this string *+-0a.0-[82]-- \-0f.0-[81]--* -+-[0000:80]-+-00.0 NVIDIA Corporation MCP55 Memory Controller | +-01.0 NVIDIA Corporation MCP55 LPC Bridge | +-01.1 NVIDIA Corporation MCP55 SMBus | +-05.0 NVIDIA Corporation MCP55 SATA Controller | +-05.1 NVIDIA Corporation MCP55 SATA Controller | +-05.2 NVIDIA Corporation MCP55 SATA Controller | +-0a.0-[82]-- | \-0f.0-[81]-- \-[0000:00]-+-00.0 NVIDIA Corporation MCP55 Memory Controller +-01.0 NVIDIA Corporation MCP55 LPC Bridge +-01.1 NVIDIA Corporation MCP55 SMBus +-02.0 NVIDIA Corporation MCP55 USB Controller +-02.1 NVIDIA Corporation MCP55 USB Controller +-04.0 NVIDIA Corporation MCP55 IDE +-05.0 NVIDIA Corporation MCP55 SATA Controller +-05.1 NVIDIA Corporation MCP55 SATA Controller +-05.2 NVIDIA Corporation MCP55 SATA Controller +-06.0-[05]--+-06.0 Hangzhou Silan Microelectronics Co., Ltd. SC92031 PCI Fast Ethernet Adapter | \-0b.0 VIA Technologies, Inc. VT6306/7/8 [Fire II(M)] IEEE 1394 OHCI Controller +-06.1 NVIDIA Corporation MCP55 High Definition Audio +-08.0 NVIDIA Corporation MCP55 Ethernet +-09.0 NVIDIA Corporation MCP55 Ethernet +-0a.0-[04]----00.0 NVIDIA Corporation G86 [GeForce 8500 GT] +-0d.0-[03]-- +-0e.0-[02]----00.0 Silicon Image, Inc. SiI 3531 [SATALink/SATARaid] Serial ATA Controller +-0f.0-[01]-- +-18.0 Advanced Micro Devices [AMD] Family 10h Processor HyperTransport Configuration +-18.1 Advanced Micro Devices [AMD] Family 10h Processor Address Map +-18.2 Advanced Micro Devices [AMD] Family 10h Processor DRAM Controller +-18.3 Advanced Micro Devices [AMD] Family 10h Processor Miscellaneous Control \-18.4 Advanced Micro Devices [AMD] Family 10h Processor Link Control 0000:00:00.0 RAM memory: NVIDIA Corporation MCP55 Memory Controller (rev a2) 0000:00:01.0 ISA bridge: NVIDIA Corporation MCP55 LPC Bridge (rev a3) 0000:00:01.1 SMBus: NVIDIA Corporation MCP55 SMBus (rev a3) 0000:00:02.0 USB controller: NVIDIA Corporation MCP55 USB Controller (rev a1) 0000:00:02.1 USB controller: NVIDIA Corporation MCP55 USB Controller (rev a2) 0000:00:04.0 IDE interface: NVIDIA Corporation MCP55 IDE (rev a1) 0000:00:05.0 IDE interface: NVIDIA Corporation MCP55 SATA Controller (rev a3) 0000:00:05.1 IDE interface: NVIDIA Corporation MCP55 SATA Controller (rev a3) 0000:00:05.2 IDE interface: NVIDIA Corporation MCP55 SATA Controller (rev a3) 0000:00:06.0 PCI bridge: NVIDIA Corporation MCP55 PCI bridge (rev a2) 0000:00:06.1 Audio device: NVIDIA Corporation MCP55 High Definition Audio (rev a2) 0000:00:08.0 Bridge: NVIDIA Corporation MCP55 Ethernet (rev a3) 0000:00:09.0 Bridge: NVIDIA Corporation MCP55 Ethernet (rev a3) 0000:00:0a.0 PCI bridge: NVIDIA Corporation MCP55 PCI Express bridge (rev a3) 0000:00:0d.0 PCI bridge: NVIDIA Corporation MCP55 PCI Express bridge (rev a3) 0000:00:0e.0 PCI bridge: NVIDIA Corporation MCP55 PCI Express bridge (rev a3) 0000:00:0f.0 PCI bridge: NVIDIA Corporation MCP55 PCI Express bridge (rev a3) 0000:00:18.0 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor HyperTransport Configuration 0000:00:18.1 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor Address Map 0000:00:18.2 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor DRAM Controller 0000:00:18.3 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor Miscellaneous Control 0000:00:18.4 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor Link Control 0000:01:00.0 VGA compatible controller: NVIDIA Corporation G86 [GeForce 8500 GT] (rev a1) 0000:02:00.0 Mass storage controller: Silicon Image, Inc. SiI 3531 [SATALink/SATARaid] Serial ATA Controller (rev 01) 0000:05:0b.0 FireWire (IEEE 1394): VIA Technologies, Inc. VT6306/7/8 [Fire II(M)] IEEE 1394 OHCI Controller (rev c0) 0000:80:00.0 RAM memory: NVIDIA Corporation MCP55 Memory Controller (rev a2) 0000:80:01.0 RAM memory: NVIDIA Corporation MCP55 LPC Bridge (rev a3) 0000:80:01.1 SMBus: NVIDIA Corporation MCP55 SMBus (rev a3) 0000:80:05.0 IDE interface: NVIDIA Corporation MCP55 SATA Controller (rev a3) 0000:80:05.1 IDE interface: NVIDIA Corporation MCP55 SATA Controller (rev a3) 0000:80:05.2 IDE interface: NVIDIA Corporation MCP55 SATA Controller (rev a3) 0000:80:0a.0 PCI bridge: NVIDIA Corporation MCP55 PCI Express bridge (rev a3) 0000:80:0f.0 PCI bridge: NVIDIA Corporation MCP55 PCI Express bridge (rev a3)

1 0

Patch merged into coreboot/master: 98907a6 i82801gx: Support power-on-after-power-fail better
by gerrit＠coreboot.org 24 Mar '12

24 Mar '12

the following patch was just integrated into master: commit 98907a679ecb191ab7f7d93d7c325079d9f69107 Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Tue Nov 22 10:52:43 2011 +0100 i82801gx: Support power-on-after-power-fail better Changing CMOS value for power-on-after-power-fail was only honored after reboot, which is counter intuitive (set from "enable" to "disable", power-off, replug device -> device turns on; and similar cases). Change-Id: If1d88c1c34c3333b636ed3ec1e1fb9bea394e615 Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> Build-Tested: build bot (Jenkins) at Sat Mar 24 16:23:30 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Sat Mar 24 20:40:38 2012, giving +2 See http://review.coreboot.org/444 for details. -gerrit

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coreboot March 2012