coreboot March 2012

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Patch set updated for coreboot: 3451173 Add Southbridge support for S3.
by Zheng Bao 23 Mar '12

23 Mar '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/621 -gerrit commit 345117383fe6ab69b20411c34f20bf5e91b1a49c Author: zbao <fishbaozi(a)gmail.com> Date: Fri Mar 23 11:38:15 2012 +0800 Add Southbridge support for S3. 1. Add some CIMX call for S3. 2. Detect sleep type. Change-Id: I62888e8d8a03987ca88f5c935fa660f6b49a4fe9 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- src/southbridge/amd/cimx/sb800/cfg.c | 65 +++++++++++++++++++++++++++-- src/southbridge/amd/cimx/sb800/early.c | 8 ++++ src/southbridge/amd/cimx/sb800/late.c | 19 +++++++++ src/southbridge/amd/cimx/sb800/lpc.c | 4 +- src/southbridge/amd/cimx/sb800/lpc.h | 3 + src/southbridge/amd/cimx/sb800/sb_cimx.h | 4 ++ 6 files changed, 97 insertions(+), 6 deletions(-) diff --git a/src/southbridge/amd/cimx/sb800/cfg.c b/src/southbridge/amd/cimx/sb800/cfg.c index a9e35bc..2a2ad2b 100644 --- a/src/southbridge/amd/cimx/sb800/cfg.c +++ b/src/southbridge/amd/cimx/sb800/cfg.c @@ -17,10 +17,63 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - +#include <console/console.h> #include "SBPLATFORM.h" #include "cfg.h" +#include <cbmem.h> + +#include <arch/io.h> +#include <arch/acpi.h> + +#define SB800_ACPI_IO_BASE 0x800 + +#define ACPI_PM_EVT_BLK (SB800_ACPI_IO_BASE + 0x00) /* 4 bytes */ +#define ACPI_PM1_CNT_BLK (SB800_ACPI_IO_BASE + 0x04) /* 2 bytes */ +#define ACPI_PMA_CNT_BLK (SB800_ACPI_IO_BASE + 0x0E) /* 1 byte */ +#define ACPI_PM_TMR_BLK (SB800_ACPI_IO_BASE + 0x18) /* 4 bytes */ +#define ACPI_GPE0_BLK (SB800_ACPI_IO_BASE + 0x10) /* 8 bytes */ +#define ACPI_CPU_CONTROL (SB800_ACPI_IO_BASE + 0x08) /* 6 bytes */ + +#if CONFIG_HAVE_ACPI_RESUME == 1 +int acpi_get_sleep_type(void) +{ + u16 tmp = inw(ACPI_PM1_CNT_BLK); + tmp = ((tmp & (7 << 10)) >> 10); + printk(BIOS_DEBUG, "SLP_TYP type was %x\n", tmp); + return (int)tmp; +} +#endif + +#define BIOSRAM_INDEX 0xcd4 +#define BIOSRAM_DATA 0xcd5 + +#ifndef __PRE_RAM__ +void set_cbmem_toc(struct cbmem_entry *toc) +{ + u32 dword = (u32) toc; + int nvram_pos = 0xf8, i; /* temp */ + printk(BIOS_DEBUG, "dword=%x\n", dword); + for (i = 0; i<4; i++) { + printk(BIOS_DEBUG, "nvram_pos=%x, dword>>(8*i)=%x\n", nvram_pos, (dword >>(8 * i)) & 0xff); + outb(nvram_pos, BIOSRAM_INDEX); + outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA); + nvram_pos++; + } +} +#endif +struct cbmem_entry *get_cbmem_toc(void) +{ + u32 xdata = 0; + int xnvram_pos = 0xf8, xi; + for (xi = 0; xi<4; xi++) { + outb(xnvram_pos, BIOSRAM_INDEX); + xdata &= ~(0xff << (xi * 8)); + xdata |= inb(BIOSRAM_DATA) << (xi *8); + xnvram_pos++; + } + return (struct cbmem_entry *) xdata; +} /** * @brief South Bridge CIMx configuration @@ -30,10 +83,13 @@ */ void sb800_cimx_config(AMDSBCFG *sb_config) { - if (!sb_config) { + if (!sb_config) return; - } - //memset(sb_config, 0, sizeof(AMDSBCFG)); + +#if CONFIG_HAVE_ACPI_RESUME == 1 + if (acpi_get_sleep_type() == 3) + sb_config->S3Resume = 1; +#endif /* header */ sb_config->StdHeader.PcieBasePtr = PCIEX_BASE_ADDRESS; @@ -132,4 +188,3 @@ void sb800_cimx_config(AMDSBCFG *sb_config) } #endif //!__PRE_RAM__ } - diff --git a/src/southbridge/amd/cimx/sb800/early.c b/src/southbridge/amd/cimx/sb800/early.c index 9d49a52..f692897 100644 --- a/src/southbridge/amd/cimx/sb800/early.c +++ b/src/southbridge/amd/cimx/sb800/early.c @@ -23,9 +23,11 @@ #include <device/pci_ids.h> #include <arch/io.h> /* inl, outl */ #include <arch/romcc_io.h> /* device_t */ +#include <arch/acpi.h> #include "SBPLATFORM.h" #include "sb_cimx.h" #include "cfg.h" /*sb800_cimx_config*/ +#include "cbmem.h" #if CONFIG_RAMINIT_SYSINFO == 1 @@ -80,3 +82,9 @@ void sb800_clk_output_48Mhz(void) *(volatile u32 *)(ACPI_MMIO_BASE + MISC_BASE + 0x40) |= 1 << 1; /* 48Mhz */ } +#if CONFIG_HAVE_ACPI_RESUME == 1 +int acpi_is_wakeup_early(void) +{ + return (acpi_get_sleep_type() == 3); +} +#endif diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index 8c7abdb..c69782b 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -24,6 +24,7 @@ #include <arch/ioapic.h> #include <device/smbus.h> /* smbus_bus_operations */ #include <console/console.h> /* printk */ +#include <arch/acpi.h> #include "lpc.h" /* lpc_read_resources */ #include "SBPLATFORM.h" /* Platfrom Specific Definitions */ #include "cfg.h" /* sb800 Cimx configuration */ @@ -351,6 +352,17 @@ void sb_Late_Post(void) AmdSbDispatcher(sb_config); } +void sb_Before_Pci_Restore_Init(void) +{ + sb_config->StdHeader.Func = SB_BEFORE_PCI_RESTORE_INIT; + AmdSbDispatcher(sb_config); +} + +void sb_After_Pci_Restore_Init(void) +{ + sb_config->StdHeader.Func = SB_AFTER_PCI_RESTORE_INIT; + AmdSbDispatcher(sb_config); +} /** * @brief SB Cimx entry point sbBeforePciInit wrapper @@ -468,7 +480,14 @@ static void sb800_enable(device_t dev) /* call the CIMX entry at the last sb800 device, * so make sure the mainboard devicetree is complete */ +#if CONFIG_HAVE_ACPI_RESUME == 1 + if (acpi_slp_type != 3) + sb_Before_Pci_Init(); + else + sb_Before_Pci_Restore_Init(); +#else sb_Before_Pci_Init(); +#endif break; default: diff --git a/src/southbridge/amd/cimx/sb800/lpc.c b/src/southbridge/amd/cimx/sb800/lpc.c index bc643b5..472817d 100644 --- a/src/southbridge/amd/cimx/sb800/lpc.c +++ b/src/southbridge/amd/cimx/sb800/lpc.c @@ -20,7 +20,9 @@ #include <console/console.h> #include <device/pci.h> #include "lpc.h" - +#include <bitops.h> +#include <arch/io.h> +#include <cbmem.h> void lpc_read_resources(device_t dev) { diff --git a/src/southbridge/amd/cimx/sb800/lpc.h b/src/southbridge/amd/cimx/sb800/lpc.h index 7b165f8..f6ffd53 100644 --- a/src/southbridge/amd/cimx/sb800/lpc.h +++ b/src/southbridge/amd/cimx/sb800/lpc.h @@ -21,6 +21,9 @@ #define _SB800_LPC_H_ +#define BIOSRAM_INDEX 0xcd4 +#define BIOSRAM_DATA 0xcd5 + #define SPIROM_BASE_ADDRESS 0xA0 /* SPI ROM base address */ void lpc_read_resources(device_t dev); diff --git a/src/southbridge/amd/cimx/sb800/sb_cimx.h b/src/southbridge/amd/cimx/sb800/sb_cimx.h index 42a7ba9..5e510de 100644 --- a/src/southbridge/amd/cimx/sb800/sb_cimx.h +++ b/src/southbridge/amd/cimx/sb800/sb_cimx.h @@ -29,6 +29,10 @@ void sb_Before_Pci_Init(void); void sb_After_Pci_Init(void); void sb_Mid_Post_Init(void); void sb_Late_Post(void); +void sb_Before_Pci_Restore_Init(void); +void sb_After_Pci_Restore_Init(void); + +int acpi_is_wakeup_early(void); /** * CIMX not set the clock to 48Mhz until sbBeforePciInit,

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Patch set updated for coreboot: 92920af Add sb800 spi support.
by Zheng Bao 23 Mar '12

23 Mar '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/620 -gerrit commit 92920af6a6bcf5dd6764bf81a13cd4a04de89a22 Author: zbao <fishbaozi(a)gmail.com> Date: Fri Mar 23 11:36:08 2012 +0800 Add sb800 spi support. It is for S3, storing the recovring data in the nonvolatile storage, i.e., flash. Change-Id: Ie9e4f42a80c93d92d2e442f0e833ce06d88294f9 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- src/southbridge/amd/cimx/sb800/Makefile.inc | 2 + src/southbridge/amd/cimx/sb800/SBPLATFORM.h | 4 + src/southbridge/amd/cimx/sb800/spi.c | 209 +++++++++++++++++++++++++++ src/southbridge/amd/cimx/sb800/spi.h | 42 ++++++ 4 files changed, 257 insertions(+), 0 deletions(-) diff --git a/src/southbridge/amd/cimx/sb800/Makefile.inc b/src/southbridge/amd/cimx/sb800/Makefile.inc index 30d2133..2b55fee 100644 --- a/src/southbridge/amd/cimx/sb800/Makefile.inc +++ b/src/southbridge/amd/cimx/sb800/Makefile.inc @@ -27,6 +27,8 @@ romstage-y += smbus.c ramstage-y += cfg.c ramstage-y += late.c +ramstage-$(CONFIG_HAVE_ACPI_RESUME) += spi.c + driver-y += smbus.c driver-y += lpc.c diff --git a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h index db5343d..25aba95 100644 --- a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h +++ b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h @@ -158,4 +158,8 @@ typedef union _PCI_ADDR { #include "vendorcode/amd/cimx/sb800/AMDSBLIB.h" +#if CONFIG_HAVE_ACPI_RESUME == 1 +#include "spi.h" +#endif + #endif // _AMD_SBPLATFORM_H_ diff --git a/src/southbridge/amd/cimx/sb800/spi.c b/src/southbridge/amd/cimx/sb800/spi.c new file mode 100644 index 0000000..b0ef753 --- /dev/null +++ b/src/southbridge/amd/cimx/sb800/spi.c @@ -0,0 +1,209 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include <console/console.h> +#include <arch/io.h> +#include <device/device.h> +#include "SBPLATFORM.h" + + +void execute_command(volatile u8 * spi_address) +{ + *(spi_address + 2) |= 1; +} + +void wait4command_complete(volatile u8 * spi_address) +{ + while (*(spi_address + 2) & 1) + printk(BIOS_DEBUG, "wait4CommandComplete\n"); +} + +void reset_internal_fifo_pointer(volatile u8 * spi_address) +{ + u8 val; + + do { + *(spi_address + 2) |= 0x10; + val = *(spi_address + 0xd); + } while (val & 0x7); +} + +u8 read_spi_status(volatile u8 * spi_address) +{ + u8 val; + *spi_address = 0x05; + *(spi_address + 1) = 0x11; + reset_internal_fifo_pointer(spi_address); + *(spi_address + 0xC) = 0x0; /* dummy */ + reset_internal_fifo_pointer(spi_address); + execute_command(spi_address); + wait4command_complete(spi_address); + reset_internal_fifo_pointer(spi_address); + val = *(spi_address + 0xC); + val = *(spi_address + 0xC); + return val; +} + +void wait4flashpart_ready(volatile u8 * spi_address) +{ + while (read_spi_status(spi_address) & 1) ; +} + +void write_spi_status(volatile u8 * spi_address, u8 status) +{ + *spi_address = 0x50; /* EWSR */ + *(spi_address + 1) = 0; /* RxByte=TxByte=0 */ + execute_command(spi_address); + wait4command_complete(spi_address); + + *spi_address = 0x01; /* WRSR */ + *(spi_address + 1) = 0x01; + reset_internal_fifo_pointer(spi_address); + *(spi_address + 0xC) = status; + reset_internal_fifo_pointer(spi_address); + execute_command(spi_address); + wait4command_complete(spi_address); + wait4flashpart_ready(spi_address); + + read_spi_status(spi_address); +} + +void read_spi_id(volatile u8 * spi_address) +{ + u8 mid = 0, did = 0; + *spi_address = 0x90; + *(spi_address + 1) = 0x23; /* RxByte=2, TxByte=3 */ + reset_internal_fifo_pointer(spi_address); + *(spi_address + 0xC) = 0; + *(spi_address + 0xC) = 0; + *(spi_address + 0xC) = 0; + reset_internal_fifo_pointer(spi_address); + execute_command(spi_address); + wait4command_complete(spi_address); + reset_internal_fifo_pointer(spi_address); + mid = *(spi_address + 0xC); + printk(BIOS_DEBUG, "mid=%x, did=%x\n", mid, did); + mid = *(spi_address + 0xC); + printk(BIOS_DEBUG, "mid=%x, did=%x\n", mid, did); + mid = *(spi_address + 0xC); + printk(BIOS_DEBUG, "mid=%x, did=%x\n", mid, did); + + mid = *(spi_address + 0xC); + did = *(spi_address + 0xC); + printk(BIOS_DEBUG, "mid=%x, did=%x\n", mid, did); +} + +void spi_write_enable(volatile u8 * spi_address) +{ + *spi_address = 0x06; /* Write Enable */ + *(spi_address + 1) = 0x0; /* RxByte=0, TxByte=0 */ + execute_command(spi_address); + wait4command_complete(spi_address); +} + +void sector_erase_spi(volatile u8 * spi_address, u32 address) +{ + spi_write_enable(spi_address); + *spi_address = 0x20; + *(spi_address + 1) = 0x03; /* RxByte=0, TxByte=3 */ + + reset_internal_fifo_pointer(spi_address); + *(spi_address + 0xC) = (address >> 16) & 0xFF; + *(spi_address + 0xC) = (address >> 8) & 0xFF; + *(spi_address + 0xC) = (address >> 0) & 0xFF; + reset_internal_fifo_pointer(spi_address); + execute_command(spi_address); + wait4command_complete(spi_address); + wait4flashpart_ready(spi_address); +} + +void chip_erase_spi(volatile u8 * spi_address) +{ + spi_write_enable(spi_address); + *spi_address = 0xC7; + *(spi_address + 1) = 0x00; + execute_command(spi_address); + wait4command_complete(spi_address); + wait4flashpart_ready(spi_address); +} + +void byte_program(volatile u8 * spi_address, u32 address, u32 data) +{ + spi_write_enable(spi_address); + *spi_address = 0x02; + *(spi_address + 1) = 0x0 << 4 | 4; + reset_internal_fifo_pointer(spi_address); + *(spi_address + 0xC) = (address >> 16) & 0xFF; + *(spi_address + 0xC) = (address >> 8) & 0xFF; + *(spi_address + 0xC) = (address >> 0) & 0xFF; + *(spi_address + 0xC) = data & 0xFF; + reset_internal_fifo_pointer(spi_address); + execute_command(spi_address); + wait4command_complete(spi_address); + wait4flashpart_ready(spi_address); +} + +void dword_noneAAI_program(volatile u8 * spi_address, u32 address, u32 data) +{ + u8 i; + /* + * printk(BIOS_SPEW, "%s: addr=%x, data=%x\n", __func__, address, data); + */ + for (i = 0; i < 4; i++) { + spi_write_enable(spi_address); + *spi_address = 0x02; + *(spi_address + 1) = 0x0 << 4 | 4; + reset_internal_fifo_pointer(spi_address); + *(spi_address + 0xC) = (address >> 16) & 0xFF; + *(spi_address + 0xC) = (address >> 8) & 0xFF; + *(spi_address + 0xC) = (address >> 0) & 0xFF; + *(spi_address + 0xC) = data & 0xFF; + data >>= 8; + address++; + reset_internal_fifo_pointer(spi_address); + execute_command(spi_address); + wait4command_complete(spi_address); + wait4flashpart_ready(spi_address); + } +} + +void dword_program(volatile u8 * spi_address, u32 address, u32 data) +{ + spi_write_enable(spi_address); + *spi_address = 0x02; + *(spi_address + 1) = 0x0 << 4 | 7; + reset_internal_fifo_pointer(spi_address); + *(spi_address + 0xC) = (address >> 16) & 0xFF; + *(spi_address + 0xC) = (address >> 8) & 0xFF; + *(spi_address + 0xC) = (address >> 0) & 0xFF; + *(spi_address + 0xC) = data & 0xFF; + *(spi_address + 0xC) = (data >> 8) & 0xFF; + *(spi_address + 0xC) = (data >> 16) & 0xFF; + *(spi_address + 0xC) = (data >> 24) & 0xFF; + reset_internal_fifo_pointer(spi_address); + execute_command(spi_address); + wait4command_complete(spi_address); + wait4flashpart_ready(spi_address); +} + +void direct_byte_program(volatile u8 * spi_address, volatile u32 * address, u32 data) +{ + spi_write_enable(spi_address); + *address = data; + wait4flashpart_ready(spi_address); +} diff --git a/src/southbridge/amd/cimx/sb800/spi.h b/src/southbridge/amd/cimx/sb800/spi.h new file mode 100644 index 0000000..57921d9 --- /dev/null +++ b/src/southbridge/amd/cimx/sb800/spi.h @@ -0,0 +1,42 @@ +/* + ***************************************************************************** + * + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * *************************************************************************** + * + */ + +#ifndef _SB800_CIMX_SPI_H_ +#define _SB800_CIMX_SPI_H_ + +void execute_command(volatile u8 * spi_address); +void wait4command_complete(volatile u8 * spi_address); +void reset_internal_fifo_pointer(volatile u8 * spi_address); +u8 read_spi_status(volatile u8 * spi_address); +void wait4flashpart_ready(volatile u8 * spi_address); +void write_spi_status(volatile u8 * spi_address, u8 status); +void read_spi_id(volatile u8 * spi_address); +void spi_write_enable(volatile u8 * spi_address); +void sector_erase_spi(volatile u8 * spi_address, u32 address); +void chip_erase_spi(volatile u8 * spi_address); +void byte_program(volatile u8 * spi_address, u32 address, u32 data); +void dword_noneAAI_program(volatile u8 * spi_address, u32 address, u32 data); +void dword_program(volatile u8 * spi_address, u32 address, u32 data); +void direct_byte_program(volatile u8 * spi_address, volatile u32 * address, u32 data); + +#endif

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Patch set updated for coreboot: ffbefc9 S3 code in coreboot public folder.
by Zheng Bao 23 Mar '12

23 Mar '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/623 -gerrit commit ffbefc9a422e9535a0c19d9156ea37c36dc9c5fa Author: zbao <fishbaozi(a)gmail.com> Date: Fri Mar 23 11:46:12 2012 +0800 S3 code in coreboot public folder. 1. Move the Stack to high memory. 2. Restore the MTRR before Coreboot jump to the wakeup vector. Change-Id: I9872e02fcd7eed98e7f630aa29ece810ac32d55a Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- src/arch/x86/boot/tables.c | 2 +- src/cpu/amd/Makefile.inc | 12 + src/cpu/amd/agesa/Makefile.inc | 2 + src/cpu/amd/agesa/cache_as_ram.inc | 7 + src/cpu/amd/agesa/family14/model_14_init.c | 125 +++++---- src/cpu/amd/agesa/s3_resume.c | 348 ++++++++++++++++++++++ src/cpu/amd/agesa/s3_resume.h | 42 +++ src/include/cbmem.h | 9 +- src/northbridge/amd/agesa/Kconfig | 4 + src/northbridge/amd/agesa/family14/northbridge.c | 77 ++++- 10 files changed, 552 insertions(+), 76 deletions(-) diff --git a/src/arch/x86/boot/tables.c b/src/arch/x86/boot/tables.c index b7dc4fe..43a3060 100644 --- a/src/arch/x86/boot/tables.c +++ b/src/arch/x86/boot/tables.c @@ -236,7 +236,7 @@ struct lb_memory *write_tables(void) * it begin there during reboot time. We don't need the pointer, nor * the result right now. If it fails, ACPI resume will be disabled. */ - cbmem_add(CBMEM_ID_RESUME, HIGH_MEMORY_SAVE); + cbmem_add(CBMEM_ID_RESUME, HIGH_MEMORY_SAVE + HIGH_SCRATCH_MEMORY_SIZE); #endif #if CONFIG_MULTIBOOT diff --git a/src/cpu/amd/Makefile.inc b/src/cpu/amd/Makefile.inc index 6663d14..6d7b0e1 100644 --- a/src/cpu/amd/Makefile.inc +++ b/src/cpu/amd/Makefile.inc @@ -15,3 +15,15 @@ subdirs-$(CONFIG_CPU_AMD_SC520) += sc520 subdirs-$(CONFIG_CPU_AMD_SOCKET_S1G1) += socket_S1G1 subdirs-$(CONFIG_CPU_AMD_AGESA) += agesa + +$(obj)/s3.rom: + echo " S3 NVRAM 0xffff0000 (S3 storage area)" + echo -ne '\xFF' > $@ + for ((i=0;i<20479;i++)) do echo -ne '\xFF' >> $@ ; done + +ifeq ($(CONFIG_HAVE_ACPI_RESUME), y) +cbfs-files-y += s3nv +s3nv-file := $(obj)/s3.rom +s3nv-position := 0xffff0000 +s3nv-type := raw +endif diff --git a/src/cpu/amd/agesa/Makefile.inc b/src/cpu/amd/agesa/Makefile.inc index fb536dd..696173d 100644 --- a/src/cpu/amd/agesa/Makefile.inc +++ b/src/cpu/amd/agesa/Makefile.inc @@ -21,5 +21,7 @@ subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY12) += family12 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += family14 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15) += family15 +romstage-$(CONFIG_HAVE_ACPI_RESUME) += s3_resume.c +ramstage-$(CONFIG_HAVE_ACPI_RESUME) += s3_resume.c ramstage-y += apic_timer.c cpu_incs += $(src)/cpu/amd/agesa/cache_as_ram.inc diff --git a/src/cpu/amd/agesa/cache_as_ram.inc b/src/cpu/amd/agesa/cache_as_ram.inc index f328db4..2124bf3 100755 --- a/src/cpu/amd/agesa/cache_as_ram.inc +++ b/src/cpu/amd/agesa/cache_as_ram.inc @@ -86,6 +86,13 @@ disable_cache_as_ram: /* Save return stack */ movd %esp, %xmm0 + /* Disable cache */ + movl %cr0, %eax + orl $(1 << 30), %eax + movl %eax, %cr0 + + invd + AMD_DISABLE_STACK /* Restore the return stack */ diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c index 6f697cf..4fd2b85 100644 --- a/src/cpu/amd/agesa/family14/model_14_init.c +++ b/src/cpu/amd/agesa/family14/model_14_init.c @@ -32,6 +32,8 @@ #include <cpu/x86/cache.h> #include <cpu/x86/mtrr.h> #include <cpu/amd/amdfam14.h> +#include <arch/acpi.h> +#include <cpu/amd/agesa/s3_resume.h> #define MCI_STATUS 0x401 @@ -57,69 +59,84 @@ void wrmsr_amd(u32 index, msr_t msr) static void model_14_init(device_t dev) { - printk(BIOS_DEBUG, "Model 14 Init.\n"); - - u8 i; - msr_t msr; - int msrno; + u32 i; + msr_t msr; #if CONFIG_LOGICAL_CPUS == 1 - u32 siblings; + u32 siblings; +#endif + printk(BIOS_DEBUG, "Model 14 Init.\n"); + + disable_cache (); + /* + * AGESA sets the MTRRs main MTRRs. The shadow area needs to be set + * by coreboot. The amd_setup_mtrrs should work, but needs debug on fam14. + * TODO: + * amd_setup_mtrrs(); + */ + + /* Enable access to AMD RdDram and WrDram extension bits */ + msr = rdmsr(SYSCFG_MSR); + msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; + msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn; + wrmsr(SYSCFG_MSR, msr); + + /* Set shadow WB, RdMEM, WrMEM */ + msr.lo = msr.hi = 0; + wrmsr (0x259, msr); + msr.hi = msr.lo = 0x1e1e1e1e; + wrmsr(0x250, msr); + wrmsr(0x258, msr); + for (i = 0x268; i <= 0x26f; i++) + wrmsr(i, msr); + + msr = rdmsr(SYSCFG_MSR); + msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; + msr.lo |= SYSCFG_MSR_MtrrFixDramEn; + wrmsr(SYSCFG_MSR, msr); + +#if CONFIG_HAVE_ACPI_RESUME == 1 + if (acpi_slp_type == 3) + restore_mtrr(); #endif - disable_cache (); - /* Enable access to AMD RdDram and WrDram extension bits */ - msr = rdmsr(SYSCFG_MSR); - msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; - wrmsr(SYSCFG_MSR, msr); - - // BSP: make a0000-bffff UC, c0000-fffff WB, same as OntarioApMtrrSettingsList for APs - msr.lo = msr.hi = 0; - wrmsr (0x259, msr); - msr.lo = msr.hi = 0x1e1e1e1e; - for (msrno = 0x268; msrno <= 0x26f; msrno++) - wrmsr (msrno, msr); - - /* disable access to AMD RdDram and WrDram extension bits */ - msr = rdmsr(SYSCFG_MSR); - msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; - wrmsr(SYSCFG_MSR, msr); - enable_cache (); - - /* zero the machine check error status registers */ - msr.lo = 0; - msr.hi = 0; - for (i = 0; i < 6; i++) { - wrmsr(MCI_STATUS + (i * 4), msr); - } - - /* Enable the local cpu apics */ - setup_lapic(); + x86_mtrr_check(); + x86_enable_cache(); + + /* zero the machine check error status registers */ + msr.lo = 0; + msr.hi = 0; + for (i = 0; i < 6; i++) { + wrmsr(MCI_STATUS + (i * 4), msr); + } + + /* Enable the local cpu apics */ + setup_lapic(); #if CONFIG_LOGICAL_CPUS == 1 - siblings = cpuid_ecx(0x80000008) & 0xff; - - if (siblings > 0) { - msr = rdmsr_amd(CPU_ID_FEATURES_MSR); - msr.lo |= 1 << 28; - wrmsr_amd(CPU_ID_FEATURES_MSR, msr); - - msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR); - msr.hi |= 1 << (33 - 32); - wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr); - } - printk(BIOS_DEBUG, "siblings = %02d, ", siblings); + siblings = cpuid_ecx(0x80000008) & 0xff; + + if (siblings > 0) { + msr = rdmsr_amd(CPU_ID_FEATURES_MSR); + msr.lo |= 1 << 28; + wrmsr_amd(CPU_ID_FEATURES_MSR, msr); + + msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR); + msr.hi |= 1 << (33 - 32); + wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr); + } #endif - /* DisableCf8ExtCfg */ - msr = rdmsr(NB_CFG_MSR); - msr.hi &= ~(1 << (46 - 32)); - wrmsr(NB_CFG_MSR, msr); + /* DisableCf8ExtCfg */ + msr = rdmsr(NB_CFG_MSR); + msr.hi &= ~(1 << (46 - 32)); + wrmsr(NB_CFG_MSR, msr); + /* Write protect SMM space with SMMLOCK. */ + msr = rdmsr(HWCR_MSR); + msr.lo |= (1 << 0); + wrmsr(HWCR_MSR, msr); - /* Write protect SMM space with SMMLOCK. */ - msr = rdmsr(HWCR_MSR); - msr.lo |= (1 << 0); - wrmsr(HWCR_MSR, msr); + printk(BIOS_SPEW, "%s done.\n", __func__); } static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c new file mode 100644 index 0000000..e911f8b --- /dev/null +++ b/src/cpu/amd/agesa/s3_resume.c @@ -0,0 +1,348 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "AGESA.h" +#include "amdlib.h" +#include <console/console.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> +#include <cpu/amd/mtrr.h> +#include <cpu/x86/cache.h> +#if CONFIG_WRITE_HIGH_TABLES +#include <cbmem.h> +#endif +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ops.h> +#include <arch/io.h> +#include <arch/acpi.h> +#include <string.h> +#include "Porting.h" +#include "BiosCallOuts.h" +#include "s3_resume.h" +#include "agesawrapper.h" + +#ifndef __PRE_RAM__ +#include "spi.h" +#endif + +void restore_mtrr(void) +{ + u32 msr; + volatile UINT32 *msrPtr = (volatile UINT32 *)S3_DATA_MTRR_POS; + msr_t msr_data; + + printk(BIOS_SPEW, "%s\n", __func__); + + disable_cache(); + + /* Enable access to AMD RdDram and WrDram extension bits */ + msr_data = rdmsr(SYS_CFG); + msr_data.lo |= SYSCFG_MSR_MtrrFixDramModEn; + wrmsr(SYS_CFG, msr_data); + + /* Now restore the Fixed MTRRs */ + msr_data.lo = *msrPtr; + msrPtr ++; + msr_data.hi = *msrPtr; + msrPtr ++; + wrmsr(0x250, msr_data); + + msr_data.lo = *msrPtr; + msrPtr ++; + msr_data.hi = *msrPtr; + msrPtr ++; + wrmsr(0x258, msr_data); + + msr_data.lo = *msrPtr; + msrPtr ++; + msr_data.hi = *msrPtr; + msrPtr ++; + wrmsr(0x259, msr_data); + + for (msr = 0x268; msr <= 0x26F; msr++) { + msr_data.lo = *msrPtr; + msrPtr ++; + msr_data.hi = *msrPtr; + msrPtr ++; + wrmsr(msr, msr_data); + } + + /* Disable access to AMD RdDram and WrDram extension bits */ + msr_data = rdmsr(SYS_CFG); + msr_data.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; + wrmsr(SYS_CFG, msr_data); + + /* Restore the Variable MTRRs */ + for (msr = 0x200; msr <= 0x20F; msr++) { + msr_data.lo = *msrPtr; + msrPtr ++; + msr_data.hi = *msrPtr; + msrPtr ++; + wrmsr(msr, msr_data); + } + + /* Restore SYSCFG MTRR */ + msr_data.lo = *msrPtr; + msrPtr ++; + msr_data.hi = *msrPtr; + msrPtr ++; + wrmsr(SYS_CFG, msr_data); +} + +inline void *backup_resume(void) +{ + unsigned long high_ram_base; + void *resume_backup_memory; + + /* Start address of high memory tables */ + high_ram_base = (u32) get_cbmem_toc(); + + /* + * printk(BIOS_DEBUG, "CBMEM TOC is at: %x\n", (u32_t)high_ram_base); + * printk(BIOS_DEBUG, "CBMEM TOC 0-size:%x\n ",(u32_t)(high_ram_base + HIGH_MEMORY_SIZE + 4096)); + */ + + cbmem_reinit((u64) high_ram_base); + + resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); + if (((u32) resume_backup_memory == 0) + || ((u32) resume_backup_memory == -1)) { + printk(BIOS_ERR, "Error: resume_backup_memory: %x\n", + (u32) resume_backup_memory); + for (;;) ; + } + + return resume_backup_memory; +} + +void move_stack_high_mem(void *resume_backup_memory) +{ +#if 0 + u32 *sp, index; + __asm__ volatile ("mov %%esp, %0":"=r" (sp) + ::); + printk(BIOS_DEBUG, "%x:", (u32) sp); + printk(BIOS_DEBUG, "[%08x,%08x,%08x,%08x]\n", sp[0], sp[1], sp[2], sp[3]); + printk(BIOS_DEBUG, "%x:", (u32) (sp + 4)); + printk(BIOS_DEBUG, "[%08x,%08x,%08x,%08x]\n", sp[4], sp[5], sp[6], sp[7]); + printk(BIOS_DEBUG, "%x:", (u32) (sp + 8)); + printk(BIOS_DEBUG, "[%08x,%08x,%08x,%08x]\n", sp[8], sp[9], sp[10], sp[11]); +#endif + + memcpy(resume_backup_memory, (void *)BSP_STACK_BASE_ADDR, + (HIGH_SCRATCH_MEMORY_SIZE - BIOS_HEAP_SIZE)); + + __asm__ + volatile ("add %0, %%esp; add %0, %%ebp; invd"::"g" + (resume_backup_memory - BSP_STACK_BASE_ADDR) + :); + +#if 0 + __asm__ volatile ("mov %%esp, %0":"=r" (sp) + ::); + printk(BIOS_DEBUG, "%x:", (u32) sp); + printk(BIOS_DEBUG, "[%08x,%08x,%08x,%08x]\n", sp[0], sp[1], sp[2], sp[3]); + printk(BIOS_DEBUG, "%x:", (u32) (sp + 4)); + printk(BIOS_DEBUG, "[%08x,%08x,%08x,%08x]\n", sp[4], sp[5], sp[6],sp[7]); + printk(BIOS_DEBUG, "%x:", (u32) (sp + 8)); + printk(BIOS_DEBUG, "[%08x,%08x,%08x,%08x]\n", sp[8], sp[9], sp[10], sp[11]); +#endif +} + +void OemAgesaSaveMtrr(void) +{ +#ifndef __PRE_RAM__ + u32 spi_address; + msr_t msr_data; + device_t dev; + u32 nvram_pos = S3_DATA_MTRR_POS; + u32 i; + + dev = dev_find_slot(0, PCI_DEVFN(0x14, 3)); + spi_address = pci_read_config32(dev, 0xA0) & ~0x1F; + + /* Enable access to AMD RdDram and WrDram extension bits */ + msr_data = rdmsr(SYS_CFG); + msr_data.lo |= SYSCFG_MSR_MtrrFixDramModEn; + wrmsr(SYS_CFG, msr_data); + + /* Fixed MTRRs */ + msr_data = rdmsr(0x250); + dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo); + nvram_pos += 4; + dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi); + nvram_pos += 4; + + msr_data = rdmsr(0x258); + dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo); + nvram_pos += 4; + dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi); + nvram_pos += 4; + + msr_data = rdmsr(0x259); + dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo); + nvram_pos += 4; + dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi); + nvram_pos += 4; + + for (i = 0x268; i < 0x270; i++) { + msr_data = rdmsr(i); + dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo); + nvram_pos += 4; + dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi); + nvram_pos += 4; + } + + /* Disable access to AMD RdDram and WrDram extension bits */ + msr_data = rdmsr(SYS_CFG); + msr_data.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; + wrmsr(SYS_CFG, msr_data); + + /* Variable MTRRs */ + for (i = 0x200; i < 0x210; i++) { + msr_data = rdmsr(i); + dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo); + nvram_pos += 4; + dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi); + nvram_pos += 4; + } + + /* SYS_CFG */ + msr_data = rdmsr(0xC0010010); + dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo); + nvram_pos += 4; + dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi); + nvram_pos += 4; + + /* TOM */ + msr_data = rdmsr(0xC001001A); + dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo); + nvram_pos += 4; + dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi); + nvram_pos += 4; + + /* TOM2 */ + msr_data = rdmsr(0xC001001D); + dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo); + nvram_pos += 4; + dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi); + nvram_pos += 4; + +#endif +} + +void OemAgesaGetS3Info(S3_DATA_TYPE S3DataType, u32 *DataSize, void **Data) +{ + AMD_CONFIG_PARAMS StdHeader; + if (S3DataType == S3DataTypeNonVolatile) { + *Data = (void *)S3_DATA_NONVOLATILE_POS; + *DataSize = *(UINTN *) (*Data); + *Data += 4; + } else { + *DataSize = *(UINTN *) S3_DATA_VOLATILE_POS; + *Data = (void *) GetHeapBase(&StdHeader); + memcpy((void *)(*Data), (void *)(S3_DATA_VOLATILE_POS + 4), *DataSize); + } +} + +u32 OemAgesaSaveS3Info(S3_DATA_TYPE S3DataType, u32 DataSize, void *Data) +{ + + u32 pos = S3_DATA_VOLATILE_POS; +#ifndef __PRE_RAM__ + u32 spi_address, data; + u32 nvram_pos; + device_t dev; +#endif + + if (S3DataType == S3DataTypeNonVolatile) { + pos = S3_DATA_NONVOLATILE_POS; + } else { /* S3DataTypeVolatile */ + pos = S3_DATA_VOLATILE_POS; + } + +#ifndef __PRE_RAM__ + dev = dev_find_slot(0, PCI_DEVFN(0x14, 3)); + spi_address = pci_read_config32(dev, 0xA0) & ~0x1F; + + /* printk(BIOS_DEBUG, "spi_address=%x\n", spi_address); */ + read_spi_id((u8 *) spi_address); + write_spi_status((u8 *)spi_address, 0); + if (S3DataType == S3DataTypeNonVolatile) { + sector_erase_spi((u8 *) spi_address, S3_DATA_NONVOLATILE_POS); + } else { + sector_erase_spi((u8 *) spi_address, S3_DATA_VOLATILE_POS); + sector_erase_spi((u8 *) spi_address, + S3_DATA_VOLATILE_POS + 0x1000); + sector_erase_spi((u8 *) spi_address, + S3_DATA_VOLATILE_POS + 0x2000); + sector_erase_spi((u8 *) spi_address, + S3_DATA_VOLATILE_POS + 0x3000); + } + + nvram_pos = 0; + dword_noneAAI_program((u8 *) spi_address, nvram_pos + pos, DataSize); + + for (nvram_pos = 0; nvram_pos < DataSize; nvram_pos += 4) { + data = *(u32 *) (Data + nvram_pos); + dword_noneAAI_program((u8 *) spi_address, nvram_pos + pos + 4, + *(u32 *) (Data + nvram_pos)); + } +#endif + + return AGESA_SUCCESS; +} + +void set_resume_cache(void) +{ + msr_t msr; + + /* disable fixed mtrr for now, it will be enabled by mtrr restore */ + msr = rdmsr(SYSCFG_MSR); + msr.lo &= ~(SYSCFG_MSR_MtrrFixDramEn | SYSCFG_MSR_MtrrFixDramModEn); + wrmsr(SYSCFG_MSR, msr); + + /* Enable caching for 0 - coreboot ram using variable mtrr */ + msr.lo = 0 | MTRR_TYPE_WRBACK; + msr.hi = 0; + wrmsr(MTRRphysBase_MSR(0), msr); + msr.lo = ~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid; + msr.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1; + wrmsr(MTRRphysMask_MSR(0), msr); + + /* Set the default memory type and disable fixed and enable variable MTRRs */ + msr.hi = 0; + msr.lo = (1 << 11); + wrmsr(MTRRdefType_MSR, msr); + + enable_cache(); +} + +void s3_resume(void) +{ + int status; + + printk(BIOS_DEBUG, "agesawrapper_amds3laterestore "); + status = agesawrapper_amds3laterestore(); + if (status) + printk(BIOS_DEBUG, "error level: %x \n", (u32) status); + else + printk(BIOS_DEBUG, "passed.\n"); +} diff --git a/src/cpu/amd/agesa/s3_resume.h b/src/cpu/amd/agesa/s3_resume.h new file mode 100644 index 0000000..a62f90e --- /dev/null +++ b/src/cpu/amd/agesa/s3_resume.h @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef S3_RESUME_H +#define S3_RESUME_H + +#define S3_DATA_NONVOLATILE_POS 0xFFFF4000 +#define S3_DATA_VOLATILE_POS 0xFFFF0000 +#define S3_DATA_MTRR_POS 0xFFFF3100 + +typedef enum { + S3DataTypeNonVolatile=0, ///< NonVolatile Data Type + S3DataTypeVolatile ///< Volatile Data Type +} S3_DATA_TYPE; + +void restore_mtrr(void); +void s3_resume(void); +inline void *backup_resume(void); +void set_resume_cache(void); +void move_stack_high_mem(void *resume_backup_memory); + +u32 OemAgesaSaveS3Info (S3_DATA_TYPE S3DataType, u32 DataSize, void *Data); +void OemAgesaGetS3Info (S3_DATA_TYPE S3DataType, u32 *DataSize, void **Data); +void OemAgesaSaveMtrr (void); + +#endif diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 9806854..a57fe2e 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -25,11 +25,12 @@ extern uint64_t high_tables_base, high_tables_size; #if CONFIG_HAVE_ACPI_RESUME -#define HIGH_MEMORY_SIZE ((CONFIG_RAMTOP - CONFIG_RAMBASE) + HIGH_MEMORY_DEF_SIZE) -#define HIGH_MEMORY_SAVE ( HIGH_MEMORY_SIZE - HIGH_MEMORY_DEF_SIZE ) -#else +#define HIGH_SCRATCH_MEMORY_SIZE 0x71000 /* (0xA0000 - 0x30000 + 0x1000) which is max */ +#define HIGH_MEMORY_SAVE (CONFIG_RAMTOP - CONFIG_RAMBASE) +#define HIGH_MEMORY_SIZE (HIGH_MEMORY_SAVE + HIGH_SCRATCH_MEMORY_SIZE + HIGH_MEMORY_DEF_SIZE) +#else /* CONFIG_HAVE_ACPI_RESUME */ #define HIGH_MEMORY_SIZE HIGH_MEMORY_DEF_SIZE -#endif +#endif /* CONFIG_HAVE_ACPI_RESUME */ #define CBMEM_ID_FREESPACE 0x46524545 #define CBMEM_ID_GDT 0x4c474454 diff --git a/src/northbridge/amd/agesa/Kconfig b/src/northbridge/amd/agesa/Kconfig index 2ee921b..ebdda38 100644 --- a/src/northbridge/amd/agesa/Kconfig +++ b/src/northbridge/amd/agesa/Kconfig @@ -27,6 +27,10 @@ config CONSOLE_VGA_MULTI bool default n +config S3_VGA_ROM_RUN + bool + default n + source src/northbridge/amd/agesa/family10/Kconfig source src/northbridge/amd/agesa/family12/Kconfig source src/northbridge/amd/agesa/family14/Kconfig diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index 15efe12..2647814 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -745,20 +745,46 @@ static void domain_set_resources(device_t dev) printk(BIOS_DEBUG, " adsr - leaving this lovely routine.\n"); } -static void domain_enable_resources(device_t dev) { +extern u8 acpi_slp_type; + +static void domain_enable_resources(device_t dev) +{ u32 val; #if CONFIG_AMD_SB_CIMX + #if CONFIG_HAVE_ACPI_RESUME + if (acpi_slp_type != 3) { + sb_After_Pci_Init(); + sb_Mid_Post_Init(); + } else { + sb_After_Pci_Restore_Init(); + } + #else sb_After_Pci_Init(); sb_Mid_Post_Init(); + #endif #endif /* Must be called after PCI enumeration and resource allocation */ printk(BIOS_DEBUG, "\nFam14h - domain_enable_resources: AmdInitMid.\n"); - val = agesawrapper_amdinitmid(); - if (val) { - printk(BIOS_DEBUG, "agesawrapper_amdinitmid failed: %x \n", val); + +#if CONFIG_HAVE_ACPI_RESUME + if (acpi_slp_type != 3) { + printk(BIOS_DEBUG, "agesawrapper_amdinitmid "); + val = agesawrapper_amdinitmid (); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); } +#else + printk(BIOS_DEBUG, "agesawrapper_amdinitmid "); + val = agesawrapper_amdinitmid (); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); +#endif printk(BIOS_DEBUG, " ader - leaving domain_enable_resources.\n"); } @@ -788,24 +814,41 @@ static void cpu_bus_set_resources(device_t dev) { pci_dev_set_resources(dev); } -static void cpu_bus_init(device_t dev) { - struct device_path cpu_path; +static u32 cpu_bus_scan(device_t dev, u32 max) +{ device_t cpu; - int apic_id; + struct device_path cpu_path; + int apic_id, cores_found; - initialize_cpus(dev->link_list); + /* There is only one node for fam14, but there may be multiple cores. */ + cpu = dev_find_slot(0, PCI_DEVFN(0x18, 0)); + if (!cpu) + printk(BIOS_ERR, "ERROR: %02x:%02x.0 not found", 0, 0x18); - /* Build the AP cpu device path(s) */ - for (apic_id = 1; apic_id < CONFIG_MAX_CPUS; apic_id++) { + cores_found = (pci_read_config32(dev_find_slot(0,PCI_DEVFN(0x18,0x3)), 0xe8) >> 12) & 3; + printk(BIOS_DEBUG, " AP siblings=%d\n", cores_found); + + + for (apic_id = 0; apic_id <= cores_found; apic_id++) { cpu_path.type = DEVICE_PATH_APIC; cpu_path.apic.apic_id = apic_id; - cpu = alloc_dev(dev->link_list, &cpu_path); - if (!cpu) - return; - cpu->enabled = 1; - cpu->path.apic.node_id = 0; - cpu->path.apic.core_id = apic_id; + cpu = alloc_find_dev(dev->link_list, &cpu_path); + if (cpu) { + cpu->enabled = 1; + cpu->path.apic.node_id = 0; + cpu->path.apic.core_id = apic_id; + printk(BIOS_DEBUG, "CPU: %s %s\n", + dev_path(cpu), cpu->enabled?"enabled":"disabled"); + } else { + cpu->enabled = 0; + } } + return max; +} + +static void cpu_bus_init(device_t dev) +{ + initialize_cpus(dev->link_list); } /* North Bridge Structures */ @@ -844,7 +887,7 @@ static struct device_operations cpu_bus_ops = { .set_resources = cpu_bus_set_resources, .enable_resources = NULL, .init = cpu_bus_init, - .scan_bus = NULL, + .scan_bus = cpu_bus_scan, }; static void root_complex_enable_dev(struct device *dev) {

1 0

Patch set updated for coreboot: c31b86f S3 code in vendorcode folder.
by Zheng Bao 23 Mar '12

23 Mar '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/622 -gerrit commit c31b86fd11be97724bdf8785fe13dd168abc414d Author: zbao <fishbaozi(a)gmail.com> Date: Fri Mar 23 11:41:20 2012 +0800 S3 code in vendorcode folder. Change the ExecuteFinalHltInstruction to assembly code. so we can make sure the code can run stackless. Change-Id: I783ced6cf7c5bc29c12a37aef29077e610d8957d Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- src/cpu/amd/agesa/family14/Makefile.inc | 1 + src/vendorcode/amd/agesa/f14/Include/gcc-intrin.h | 10 +- src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.c | 150 +-------------- src/vendorcode/amd/agesa/f14/Proc/CPU/cahaltasm.S | 204 ++++++++++++++++++++ .../amd/agesa/f14/Proc/Common/AmdS3Save.c | 2 +- .../amd/agesa/f14/Proc/Mem/Feat/S3/mfs3.c | 10 +- src/vendorcode/amd/agesa/f14/gcccar.inc | 140 ++++++++------ 7 files changed, 301 insertions(+), 216 deletions(-) diff --git a/src/cpu/amd/agesa/family14/Makefile.inc b/src/cpu/amd/agesa/family14/Makefile.inc index 774d401..b08ceeb 100644 --- a/src/cpu/amd/agesa/family14/Makefile.inc +++ b/src/cpu/amd/agesa/family14/Makefile.inc @@ -113,6 +113,7 @@ agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Gfx/GfxInitAtMidPost.c agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/cpuF14CacheDefaults.c agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/ON/mpuon3.c agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cahalt.c +agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cahaltasm.S agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mt.c agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/ON/F14OnMicrocodePatchTables.c agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/ON/F14OnPciTables.c diff --git a/src/vendorcode/amd/agesa/f14/Include/gcc-intrin.h b/src/vendorcode/amd/agesa/f14/Include/gcc-intrin.h index 58438b9..5ce3ee3 100644 --- a/src/vendorcode/amd/agesa/f14/Include/gcc-intrin.h +++ b/src/vendorcode/amd/agesa/f14/Include/gcc-intrin.h @@ -305,7 +305,9 @@ static __inline__ __attribute__((always_inline)) unsigned long __readcr0(void) unsigned long value; __asm__ __volatile__ ( "mov %%cr0, %[value]" - : [value] "=a" (value)); + : [value] "=a" (value) + : + : "memory"); return value; } @@ -379,6 +381,7 @@ static __inline__ __attribute__((always_inline)) void __writecr0(unsigned long D "mov %%eax, %%cr0" : : "a" (Data) + : "memory" ); } @@ -508,13 +511,16 @@ static __inline__ __attribute__((always_inline)) void __debugbreak(void) __asm__ __volatile__ ("int3"); } +static __inline__ __attribute__((always_inline)) void __invd(void) +{ + __asm__ __volatile__ ("invd"); +} static __inline__ __attribute__((always_inline)) void __wbinvd(void) { __asm__ __volatile__ ("wbinvd"); } - static __inline__ __attribute__((always_inline)) void __lidt(void *Source) { __asm__ __volatile__("lidt %0" : : "m"(*(short*)Source)); diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.c index c4c3892..fa9abbf 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.c @@ -72,14 +72,7 @@ * P R O T O T Y P E S O F L O C A L F U N C T I O N S *---------------------------------------------------------------------------------------- */ - -VOID -ExecuteFinalHltInstruction ( - IN UINT32 SharedCore, - IN AP_MTRR_SETTINGS *ApMtrrSettingsList, - IN AMD_CONFIG_PARAMS *StdHeader - ); - + VOID SetIdtr ( IN IDT_BASE_LIMIT *IdtInfo, @@ -113,149 +106,16 @@ ExecuteWbinvdInstruction ( */ -//---------------------------------------------------------------------------- - -STATIC -VOID -PrimaryCoreFunctions (AP_MTRR_SETTINGS *ApMtrrSettingsList) - { - UINT64 data; - UINT32 msrno; - // Configure the MTRRs on the AP so - // when it runs remote code it will execute - // out of RAM instead of ROM. - // Disable MTRRs and turn on modification enable bit - - data = __readmsr (0xC0010010); // MTRR_SYS_CFG - data &= ~(1 << 18); // MtrrFixDramEn - data &= ~(1 << 20); // MtrrVarDramEn - data |= (1 << 19); // MtrrFixDramModEn - data |= (1 << 17); // SysUcLockEn - - - __writemsr (0xC0010010, data); - - // Set 7FFFh-00000h and 9FFFFh-80000h as WB DRAM - __writemsr (0x250, 0x1E1E1E1E1E1E1E1E); // AMD_MTRR_FIX64k_00000 - __writemsr (0x258, 0x1E1E1E1E1E1E1E1E); // AMD_MTRR_FIX16k_80000 - - // Set BFFFFh-A0000h, DFFFFh-C0000h as Uncacheable Memory-mapped IO - __writemsr (0x259, 0); // AMD_AP_MTRR_FIX16k_A0000 - __writemsr (0x268, 0); // AMD_MTRR_FIX4k_C0000 - __writemsr (0x269, 0); // AMD_MTRR_FIX4k_C8000 - __writemsr (0x26A, 0); // AMD_MTRR_FIX4k_D0000 - __writemsr (0x26B, 0); // AMD_MTRR_FIX4k_D8000 - - // Set FFFFFh-E0000h as Uncacheable Memory - for (msrno = 0x26C; msrno <= 0x26F; msrno++) - __writemsr (msrno, 0x1818181818181818); - - // If IBV provided settings for Fixed-Sized MTRRs, - // overwrite the default settings. - if ((uintptr_t) ApMtrrSettingsList != 0 && (uintptr_t) ApMtrrSettingsList != 0xFFFFFFFF) - { - int index; - for (index = 0; ApMtrrSettingsList [index].MsrAddr != CPU_LIST_TERMINAL; index++) - __writemsr (ApMtrrSettingsList [index].MsrAddr, ApMtrrSettingsList [index].MsrData); - } - - // restore variable MTTR6 and MTTR7 to default states - for (msrno = 0x20F; msrno <= 0x20C; msrno--) // decrement so that the pair is disable before the base is cleared - __writemsr (msrno, 0); - - // Enable fixed-range and variable-range MTRRs - // Set Fixed-Range Enable (FE) and MTRR Enable (E) bits - __writemsr (0x2FF, __readmsr (0x2FF) | 0xC00); - - // Enable Top-of-Memory setting - // Enable use of RdMem/WrMem bits attributes - data = __readmsr (0xC0010010); // MTRR_SYS_CFG - data |= (1 << 18); // MtrrFixDramEn - data |= (1 << 20); // MtrrVarDramEn - data &= ~(1 << 19); // MtrrFixDramModEn - __writemsr (0xC0010010, data); - } - -//---------------------------------------------------------------------------- - +/* see cahaltasm.S VOID ExecuteFinalHltInstruction ( - IN UINT32 SharedCore, + IN UINT32 HaltFlags, IN AP_MTRR_SETTINGS *ApMtrrSettingsList, IN AMD_CONFIG_PARAMS *StdHeader ) { - int abcdRegs [4]; - UINT32 cr0val; - UINT64 data; - - cr0val = __readcr0 (); - if (SharedCore & 2) - { - // set CombineCr0Cd and enable cache in CR0 - __writemsr (MSR_CU_CFG3, __readmsr (MSR_CU_CFG3) | 1ULL << 49); - __writecr0 (cr0val & ~0x60000000); - } - else - __writecr0 (cr0val | 0x60000000); - - if (SharedCore & 1) PrimaryCoreFunctions (ApMtrrSettingsList); - - // Make sure not to touch any Shared MSR from this point on - - // Restore settings that were temporarily overridden for the cache as ram phase - data = __readmsr (0xC0011022); // MSR_DC_CFG - data &= ~(1 << 4); // DC_DIS_SPEC_TLB_RLD - data &= ~(1 << 8); // DIS_CLR_WBTOL2_SMC_HIT - data &= ~(1 << 13); // DIS_HW_PF - __writemsr (0xC0011022, data); - - data = __readmsr (0xC0011021); // MSR_IC_CFG - C001_1021 - data &= ~(1 << 9); // IC_DIS_SPEC_TLB_RLD - __writemsr (0xC0011021, data); - - // AMD_DISABLE_STACK_FAMILY_HOOK - __cpuid (abcdRegs, 1); - if ((abcdRegs [0] >> 20) == 1) //-----family 10h (Hydra) only----- - { - data = __readmsr (0xC0011022); - data &= ~(1 << 4); - data &= ~(1 << 8); - data &= ~(1 << 13); - __writemsr (0xC0011022, data); - - data = __readmsr (0xC0011021); - data &= ~(1 << 14); - data &= ~(1 << 9); - __writemsr (0xC0011021, data); - - data = __readmsr (0xC001102A); - data &= ~(1 << 15); - data &= ~(1ull << 35); - __writemsr (0xC001102A, data); - } - else if ((abcdRegs [0] >> 20) == 6) //-----family 15h (Orochi) only----- - { - data = __readmsr (0xC0011020); - data &= ~(1 << 28); - __writemsr (0xC0011020, data); - - data = __readmsr (0xC0011021); - data &= ~(1 << 9); - __writemsr (0xC0011021, data); - - data = __readmsr (0xC0011022); - data &= ~(1 << 4); - data &= ~(1l << 13); - __writemsr (0xC0011022, data); - } - - for (;;) - { - _disable (); - __halt (); - } - } +} +*/ //---------------------------------------------------------------------------- diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cahaltasm.S b/src/vendorcode/amd/agesa/f14/Proc/CPU/cahaltasm.S new file mode 100644 index 0000000..509e962 --- /dev/null +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cahaltasm.S @@ -0,0 +1,204 @@ +/* + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +.include "src/vendorcode/amd/agesa/f14/gcccar.inc" + +.code32 +.align 4 +.globl ExecuteFinalHltInstruction + .type ExecuteFinalHltInstruction, @function +/* ExecuteFinalHltInstruction ( + IN UINT32 HaltFlags, + IN AP_MTRR_SETTINGS *ApMtrrSettingsList, + IN AMD_CONFIG_PARAMS *StdHeader + ) +*/ + +/* This function disables CAR. We don't care about the stack on this CPU */ +ExecuteFinalHltInstruction: +/* AMD- TODO - check these stack access are correct */ + movl 4(%esp), %esi /* HaltFlags*/ + movl 8(%esp), %edi /* ApMtrrSettingList */ + +/* Do these special steps in case if the core is part of a compute unit + * Note: The following bits are family specific flags, that gets set during build time, + * and indicates things like "family cache control methodology", etc. + * esi bit0 = 0 -> not a Primary core + * esi bit0 = 1 -> Primary core + * esi bit1 = 0 -> Cache disable + * esi bit1 = 1 -> Cache enable + */ + + bt $1, %esi /* .if (esi & 2h) */ + jz 0f + /* Set CombineCr0Cd bit */ + movl $CU_CFG3, %ecx + rdmsr + bts $(COMBINE_CR0_CD - 32), %edx + wrmsr + /* Clear the CR0.CD bit */ + movl %cr0, %eax /* Make sure cache is enabled for all APs */ + btr $CR0_CD, %eax + btr $CR0_NW, %eax + mov %eax, %cr0 /* Write back to CR0 */ + jmp 1f /* .else */ +0: + movl %cr0, %eax /* Make sure cache is disabled for all APs */ + bts $CR0_CD, %eax /* Disable cache */ + bts $CR0_NW, %eax + movl %eax, %cr0 /* Write back to CR0 */ +1: /* .endif */ + + bt $0, %esi /* .if (esi & 1h) */ + jz 2f + /* This core is a primary core and needs to do all the MTRRs, including shared MTRRs. */ + movl %edi, %esi /* Get ApMtrrSettingList */ + + /* Configure the MTRRs on the AP so + * when it runs remote code it will execute + * out of RAM instead of ROM. + */ + + /* Disable MTRRs and turn on modification enable bit */ + movl $MTRR_SYS_CFG, %ecx + rdmsr + btr $MTRR_VAR_DRAM_EN, %eax /* Disable */ + bts $MTRR_FIX_DRAM_MOD_EN, %eax /* Enable */ + btr $MTRR_FIX_DRAM_EN, %eax /* Disable */ + bts $SYS_UC_LOCK_EN, %eax + wrmsr + + /* Setup default values for Fixed-Sized MTRRs */ + /* Set 7FFFh-00000h as WB */ + movl $AMD_AP_MTRR_FIX64k_00000, %ecx + movl $0x1E1E1E1E, %eax + movl %eax, %edx + wrmsr + + /* Set 9FFFFh-80000h also as WB */ + movl $AMD_AP_MTRR_FIX16k_80000, %ecx + wrmsr + + /* Set BFFFFh-A0000h as Uncacheable Memory-mapped IO */ + movl $AMD_AP_MTRR_FIX16k_A0000, %ecx + xorl %eax, %eax + xorl %edx, %edx + wrmsr + + /* Set DFFFFh-C0000h as Uncacheable Memory-mapped IO */ + xorl %eax, %eax + xorl %edx, %edx + movl $AMD_AP_MTRR_FIX4k_C0000, %ecx + +CDLoop: + wrmsr + inc %ecx + cmp $AMD_AP_MTRR_FIX4k_D8000, %ecx + jbe CDLoop + + /* Set FFFFFh-E0000h as Uncacheable Memory */ + movl $0x18181818, %eax + movl %eax, %edx + + mov $AMD_AP_MTRR_FIX4k_E0000, %ecx + +EFLoop: + wrmsr + inc %ecx + cmp $AMD_AP_MTRR_FIX4k_F8000, %ecx + jbe EFLoop + + /* If IBV provided settings for Fixed-Sized MTRRs, + * overwrite the default settings. */ + cmp $0, %esi /*.if ((esi != 0) && (esi != 0FFFFFFFFh)) */ + jz 4f + cmp $0xFFFFFFFF, %esi + jz 4f + 5: + mov (%esi), %ecx /* (AP_MTRR_SETTINGS ptr [esi]).MsrAddr */ + /* While we are not at the end of the list */ + cmp $CPU_LIST_TERMINAL, %ecx /* .while (ecx != CPU_LIST_TERMINAL)*/ + je 4f + /* TODO - coreboot isn't checking for valid data. + * Ensure that the MSR address is valid for Fixed-Sized MTRRs */ + /*.if ( ((ecx >= AMD_AP_MTRR_FIX4k_C0000) && (ecx <= AMD_AP_MTRR_FIX4k_F8000)) || \ + (ecx == AMD_AP_MTRR_FIX64k_00000) || (ecx == AMD_AP_MTRR_FIX16k_80000 ) || \ + (ecx == AMD_AP_MTRR_FIX16k_A0000)) + */ + mov 4(%esi), %eax /* MsrData */ + mov 8(%esi), %edx /* MsrData */ + wrmsr + /* .endif */ + add $12, %esi /* sizeof (AP_MTRR_SETTINGS) */ + jmp 5b /* .endw */ + 4: /* .endif */ + + /* restore variable MTTR6 and MTTR7 to default states */ + movl $AMD_MTRR_VARIABLE_BASE6, %ecx /* clear MTRRPhysBase6 MTRRPhysMask6 */ + xor %eax, %eax /* and MTRRPhysBase7 MTRRPhysMask7 */ + xor %edx, %edx + cmp $10, %ecx /* .while (cl < 010h) */ + jge 6f + wrmsr + inc %ecx + 6: /* .endw */ + + /* Enable fixed-range and variable-range MTRRs */ + mov $AMD_MTRR_DEFTYPE, %ecx + rdmsr + bts $MTRR_DEF_TYPE_EN, %eax /* MtrrDefTypeEn */ + bts $MTRR_DEF_TYPE_FIX_EN, %eax /* MtrrDefTypeFixEn */ + wrmsr + + /* Enable Top-of-Memory setting */ + /* Enable use of RdMem/WrMem bits attributes */ + mov $MTRR_SYS_CFG, %ecx + rdmsr + bts $MTRR_VAR_DRAM_EN, %eax /* Enable */ + btr $MTRR_FIX_DRAM_MOD_EN, %eax /* Disable */ + bts $MTRR_FIX_DRAM_EN, %eax /* Enable */ + wrmsr + + bts $FLAG_IS_PRIMARY, %esi + jmp 3f /* .else ; end if primary core */ + 2: + xor %esi, %esi + 3: /* .endif*/ + + /* Make sure not to touch any Shared MSR from this point on */ + + AMD_DISABLE_STACK_FAMILY_HOOK + + xor %eax, %eax + +7: + cli + hlt + jmp 7b /* ExecuteHltInstruction */ + + .size ExecuteFinalHltInstruction, .-ExecuteFinalHltInstruction diff --git a/src/vendorcode/amd/agesa/f14/Proc/Common/AmdS3Save.c b/src/vendorcode/amd/agesa/f14/Proc/Common/AmdS3Save.c index f994c87..448d0f9 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Common/AmdS3Save.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Common/AmdS3Save.c @@ -245,7 +245,7 @@ AmdS3Save ( HeapStatus = AmdS3SaveParams->StdHeader.HeapStatus; AmdS3SaveParams->StdHeader.HeapStatus = HEAP_S3_RESUME; - AmdS3SaveParams->StdHeader.HeapBasePtr = (UINT64) HeapPtr; + AmdS3SaveParams->StdHeader.HeapBasePtr = (VOID *) HeapPtr; for (i = 0; i < S3LATE_TABLE_SIZE; i++) { if (HeapPtrs[i] != NULL) { diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/S3/mfs3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/S3/mfs3.c index df2071f..eee9804 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/S3/mfs3.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/S3/mfs3.c @@ -259,30 +259,30 @@ MemFS3GetDeviceList ( (*DeviceBlockHdrPtr)->RelativeOrMaskOffset = (UINT16) AllocHeapParams.RequestedBufferSize; // Copy device list on the stack to the heap. - BufferOffset = sizeof (DEVICE_BLOCK_HEADER) + (UINT64) AllocHeapParams.BufferPtr; + BufferOffset = sizeof (DEVICE_BLOCK_HEADER) + (UINT64) (UINT32) AllocHeapParams.BufferPtr; for (Die = 0; Die < DieCount; Die ++) { for (i = PRESELFREF; i <= POSTSELFREF; i ++) { // Copy PCI device descriptor to the heap if it exists. if (DeviceDescript[Die].PCIDevice[i].RegisterListID != 0xFFFFFFFF) { - LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Die].PCIDevice[i]), sizeof (PCI_DEVICE_DESCRIPTOR), StdHeader); + LibAmdMemCopy ((VOID *)(UINT32) BufferOffset, &(DeviceDescript[Die].PCIDevice[i]), sizeof (PCI_DEVICE_DESCRIPTOR), StdHeader); (*DeviceBlockHdrPtr)->NumDevices ++; BufferOffset += sizeof (PCI_DEVICE_DESCRIPTOR); } // Copy conditional PCI device descriptor to the heap if it exists. if (DeviceDescript[Die].CPCIDevice[i].RegisterListID != 0xFFFFFFFF) { - LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Die].CPCIDevice[i]), sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR), StdHeader); + LibAmdMemCopy ((VOID *)(UINT32) BufferOffset, &(DeviceDescript[Die].CPCIDevice[i]), sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR), StdHeader); (*DeviceBlockHdrPtr)->NumDevices ++; BufferOffset += sizeof (CONDITIONAL_PCI_DEVICE_DESCRIPTOR); } // Copy MSR device descriptor to the heap if it exists. if (DeviceDescript[Die].MSRDevice[i].RegisterListID != 0xFFFFFFFF) { - LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Die].MSRDevice[i]), sizeof (MSR_DEVICE_DESCRIPTOR), StdHeader); + LibAmdMemCopy ((VOID *)(UINT32) BufferOffset, &(DeviceDescript[Die].MSRDevice[i]), sizeof (MSR_DEVICE_DESCRIPTOR), StdHeader); (*DeviceBlockHdrPtr)->NumDevices ++; BufferOffset += sizeof (MSR_DEVICE_DESCRIPTOR); } // Copy conditional MSR device descriptor to the heap if it exists. if (DeviceDescript[Die].CMSRDevice[i].RegisterListID != 0xFFFFFFFF) { - LibAmdMemCopy ((VOID *) BufferOffset, &(DeviceDescript[Die].PCIDevice[i]), sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR), StdHeader); + LibAmdMemCopy ((VOID *)(UINT32) BufferOffset, &(DeviceDescript[Die].PCIDevice[i]), sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR), StdHeader); (*DeviceBlockHdrPtr)->NumDevices ++; BufferOffset += sizeof (CONDITIONAL_MSR_DEVICE_DESCRIPTOR); } diff --git a/src/vendorcode/amd/agesa/f14/gcccar.inc b/src/vendorcode/amd/agesa/f14/gcccar.inc index 63f3ea9..ad5a21d 100644 --- a/src/vendorcode/amd/agesa/f14/gcccar.inc +++ b/src/vendorcode/amd/agesa/f14/gcccar.inc @@ -37,69 +37,83 @@ .altmacro -BSP_STACK_BASE_ADDR = 0x30000 /* Base address for primary cores stack */ -BSP_STACK_SIZE = 0x10000 /* 64KB for BSP core */ -CORE0_STACK_BASE_ADDR = 0x80000 /* Base address for primary cores stack */ -CORE0_STACK_SIZE = 0x4000 /* 16KB for primary cores */ -CORE1_STACK_BASE_ADDR = 0x40000 /* Base address for AP cores */ -CORE1_STACK_SIZE = 0x1000 /* 4KB for each AP cores */ - -APIC_BASE_ADDRESS = 0x0000001B - APIC_BSC = 8 /* Boot Strap Core */ - -AMD_MTRR_VARIABLE_BASE0 = 0x0200 -AMD_MTRR_VARIABLE_BASE6 = 0x020C -AMD_MTRR_FIX64k_00000 = 0x0250 -AMD_MTRR_FIX16k_80000 = 0x0258 -AMD_MTRR_FIX16k_A0000 = 0x0259 -AMD_MTRR_FIX4k_C0000 = 0x0268 -AMD_MTRR_FIX4k_C8000 = 0x0269 -AMD_MTRR_FIX4k_D0000 = 0x026A -AMD_MTRR_FIX4k_D8000 = 0x026B -AMD_MTRR_FIX4k_E0000 = 0x026C -AMD_MTRR_FIX4k_E8000 = 0x026D -AMD_MTRR_FIX4k_F0000 = 0x026E -AMD_MTRR_FIX4k_F8000 = 0x026F - -AMD_MTRR_DEFTYPE = 0x02FF - WB_DRAM_TYPE = 0x1E /* MemType - memory type */ - MTRR_DEF_TYPE_EN = 11 /* MtrrDefTypeEn - variable and fixed MTRRs default enabled */ - MTRR_DEF_TYPE_FIX_EN = 10 /* MtrrDefTypeEn - fixed MTRRs default enabled */ - -HWCR = 0x0C0010015 /* Hardware Configuration */ - INVD_WBINVD = 0x04 /* INVD to WBINVD conversion */ - -IORR_BASE = 0x0C0010016 /* IO Range Regusters Base/Mask, 2 pairs */ - /* uses 16h - 19h */ -TOP_MEM = 0x0C001001A /* Top of Memory */ -TOP_MEM2 = 0x0C001001D /* Top of Memory2 */ - -LS_CFG = 0x0C0011020 /* Load-Store Configuration */ - DIS_SS = 28 /* Family 10h,12h,15h:Disable Streng Store functionality */ - DIS_STREAM_ST = 28 /* Family 14h:DisStreamSt - Disable Streaming Store functionality */ - -IC_CFG = 0x0C0011021 /* Instruction Cache Config Register */ - IC_DIS_SPEC_TLB_RLD = 9 /* Disable speculative TLB reloads */ - DIS_IND = 14 /* Family 10-14h:Disable Indirect Branch Predictor */ - DIS_I_CACHE = 14 /* Family 15h:DisICache - Disable Indirect Branch Predictor */ - -DC_CFG = 0x0C0011022 /* Data Cache Configuration */ - DC_DIS_SPEC_TLB_RLD = 4 /* Disable speculative TLB reloads */ - DIS_CLR_WBTOL2_SMC_HIT = 8 /* self modifying code check buffer bit */ - DIS_HW_PF = 13 /* Hardware prefetches bit */ - -DE_CFG = 0x0C0011029 /* Decode Configuration */ - CL_FLUSH_SERIALIZE = 23 /* Family 12h,15h: CL Flush Serialization */ - -BU_CFG2 = 0x0C001102A /* Family 10h: Bus Unit Configuration 2 */ -CU_CFG2 = 0x0C001102A /* Family 15h: Combined Unit Configuration 2 */ - F10_CL_LINES_TO_NB_DIS = 15 /* ClLinesToNbDis - allows WP code to be cached in L2 */ - IC_DIS_SPEC_TLB_WR = 35 /* IcDisSpecTlbWr - ITLB speculative writes */ - -CU_CFG3 = 0x0C001102B /* Combined Unit Configuration 3 */ - COMBINE_CR0_CD = 49 /* Combine CR0.CD for both cores of a compute unit */ - - +BSP_STACK_BASE_ADDR = 0x30000 /* Base address for primary cores stack */ +BSP_STACK_SIZE = 0x10000 /* 64KB for BSP core */ +CORE0_STACK_BASE_ADDR = 0x80000 /* Base address for primary cores stack */ +CORE0_STACK_SIZE = 0x4000 /* 16KB for primary cores */ +CORE1_STACK_BASE_ADDR = 0x40000 /* Base address for AP cores */ +CORE1_STACK_SIZE = 0x1000 /* 4KB for each AP cores */ + +APIC_BASE_ADDRESS = 0x0000001B + APIC_BSC = 8 /* Boot Strap Core */ + +AMD_MTRR_VARIABLE_BASE0 = 0x0200 +AMD_MTRR_VARIABLE_BASE6 = 0x020C +AMD_MTRR_FIX64k_00000 = 0x0250 +AMD_MTRR_FIX16k_80000 = 0x0258 +AMD_MTRR_FIX16k_A0000 = 0x0259 +AMD_MTRR_FIX4k_C0000 = 0x0268 +AMD_MTRR_FIX4k_C8000 = 0x0269 +AMD_MTRR_FIX4k_D0000 = 0x026A +AMD_MTRR_FIX4k_D8000 = 0x026B +AMD_MTRR_FIX4k_E0000 = 0x026C +AMD_MTRR_FIX4k_E8000 = 0x026D +AMD_MTRR_FIX4k_F0000 = 0x026E +AMD_MTRR_FIX4k_F8000 = 0x026F + +/* Reproduced from AGESA.h */ +AMD_AP_MTRR_FIX64k_00000 = 0x00000250 +AMD_AP_MTRR_FIX16k_80000 = 0x00000258 +AMD_AP_MTRR_FIX16k_A0000 = 0x00000259 +AMD_AP_MTRR_FIX4k_C0000 = 0x00000268 +AMD_AP_MTRR_FIX4k_C8000 = 0x00000269 +AMD_AP_MTRR_FIX4k_D0000 = 0x0000026A +AMD_AP_MTRR_FIX4k_D8000 = 0x0000026B +AMD_AP_MTRR_FIX4k_E0000 = 0x0000026C +AMD_AP_MTRR_FIX4k_E8000 = 0x0000026D +AMD_AP_MTRR_FIX4k_F0000 = 0x0000026E +AMD_AP_MTRR_FIX4k_F8000 = 0x0000026F +CPU_LIST_TERMINAL = 0xFFFFFFFF + +AMD_MTRR_DEFTYPE = 0x02FF + WB_DRAM_TYPE = 0x1E /* MemType - memory type */ + MTRR_DEF_TYPE_EN = 11 /* MtrrDefTypeEn - variable and fixed MTRRs default enabled */ + MTRR_DEF_TYPE_FIX_EN = 10 /* MtrrDefTypeEn - fixed MTRRs default enabled */ + +HWCR = 0x0C0010015 /* Hardware Configuration */ + INVD_WBINVD = 0x04 /* INVD to WBINVD conversion */ + +IORR_BASE = 0x0C0010016 /* IO Range Regusters Base/Mask, 2 pairs */ + /* uses 16h - 19h */ +TOP_MEM = 0x0C001001A /* Top of Memory */ +TOP_MEM2 = 0x0C001001D /* Top of Memory2 */ + +LS_CFG = 0x0C0011020 /* Load-Store Configuration */ + DIS_SS = 28 /* Family 10h,12h,15h:Disable Streng Store functionality */ + DIS_STREAM_ST = 28 /* Family 14h:DisStreamSt - Disable Streaming Store functionality */ + +IC_CFG = 0x0C0011021 /* Instruction Cache Config Register */ + IC_DIS_SPEC_TLB_RLD = 9 /* Disable speculative TLB reloads */ + DIS_IND = 14 /* Family 10-14h:Disable Indirect Branch Predictor */ + DIS_I_CACHE = 14 /* Family 15h:DisICache - Disable Indirect Branch Predictor */ + +DC_CFG = 0x0C0011022 /* Data Cache Configuration */ + DC_DIS_SPEC_TLB_RLD = 4 /* Disable speculative TLB reloads */ + DIS_CLR_WBTOL2_SMC_HIT = 8 /* self modifying code check buffer bit */ + DIS_HW_PF = 13 /* Hardware prefetches bit */ + +DE_CFG = 0x0C0011029 /* Decode Configuration */ + CL_FLUSH_SERIALIZE = 23 /* Family 12h,15h: CL Flush Serialization */ + +BU_CFG2 = 0x0C001102A /* Family 10h: Bus Unit Configuration 2 */ +CU_CFG2 = 0x0C001102A /* Family 15h: Combined Unit Configuration 2 */ + F10_CL_LINES_TO_NB_DIS = 15 /* ClLinesToNbDis - allows WP code to be cached in L2 */ + IC_DIS_SPEC_TLB_WR = 35 /* IcDisSpecTlbWr - ITLB speculative writes */ + +CU_CFG3 = 0x0C001102B /* Combined Unit Configuration 3 */ + COMBINE_CR0_CD = 49 /* Combine CR0.CD for both cores of a compute unit */ + + CR0_PE = 1 # Protection Enable CR0_NW = 29 # Not Write-through CR0_CD = 30 # Cache Disable

1 0

Patch set updated for coreboot: d7ae4a2 Add faster, architecture dependent memcpy()
by Zheng Bao 23 Mar '12

23 Mar '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/736 -gerrit commit d7ae4a25e5652278083a5836f303cc2eae91ee2d Author: zbao <fishbaozi(a)gmail.com> Date: Fri Mar 23 11:33:14 2012 +0800 Add faster, architecture dependent memcpy() Change-Id: I38d15f3f1ec65f0cb7974d2dd4ae6356433bddd8 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> Reviewed-by: Duncan Laurie <dlaurie(a)google.com> --- src/arch/x86/Kconfig | 4 ++++ src/arch/x86/lib/Makefile.inc | 4 ++++ src/arch/x86/lib/memcpy.c | 13 +++++++++++++ src/lib/Makefile.inc | 9 ++++++++- 4 files changed, 29 insertions(+), 1 deletions(-) diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index c5a0c0e..4062a56 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -80,6 +80,10 @@ config CMOS_DEFAULT_FILE config BOOTBLOCK_SOUTHBRIDGE_INIT string +config HAVE_ARCH_MEMCPY + bool + default y + config BIG_ENDIAN bool default n diff --git a/src/arch/x86/lib/Makefile.inc b/src/arch/x86/lib/Makefile.inc index 3388a9d..f99e429 100644 --- a/src/arch/x86/lib/Makefile.inc +++ b/src/arch/x86/lib/Makefile.inc @@ -8,8 +8,12 @@ ramstage-$(CONFIG_MMCONF_SUPPORT) += pci_ops_mmconf.c ramstage-y += pci_ops_auto.c ramstage-y += exception.c ramstage-$(CONFIG_IOAPIC) += ioapic.c +ramstage-y += memcpy.c romstage-y += romstage_console.c romstage-y += cbfs_and_run.c +romstage-y += memcpy.c + +smm-y += memcpy.c $(obj)/arch/x86/lib/console.ramstage.o :: $(obj)/build.h diff --git a/src/arch/x86/lib/memcpy.c b/src/arch/x86/lib/memcpy.c new file mode 100644 index 0000000..de21092 --- /dev/null +++ b/src/arch/x86/lib/memcpy.c @@ -0,0 +1,13 @@ +#include <string.h> + +void *memcpy(void *__restrict __dest, + __const void *__restrict __src, size_t __n) +{ + asm("cld\n" + "rep\n" + "movsb" + : /* no input (?) */ + :"S"(__src), "D"(__dest), "c"(__n) + ); + return __dest; +} diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index e0e5e75..8c3401d 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -2,7 +2,9 @@ romstage-y += memset.c romstage-y += memchr.c +ifneq ($(CONFIG_HAVE_ARCH_MEMCPY),y) romstage-y += memcpy.c +endif romstage-y += memcmp.c romstage-y += cbfs.c romstage-y += lzma.c @@ -17,7 +19,9 @@ romstage-$(CONFIG_USBDEBUG) += usbdebug.c ramstage-y += memset.c ramstage-y += memchr.c +ifneq ($(CONFIG_HAVE_ARCH_MEMCPY),y) ramstage-y += memcpy.c +endif ramstage-y += memcmp.c ramstage-y += memmove.c ramstage-y += malloc.c @@ -39,7 +43,10 @@ ramstage-$(CONFIG_TRACE) += trace.c driver-$(CONFIG_CONSOLE_NE2K) += ne2k.c -smm-y += memcpy.c cbfs.c memset.c memcmp.c +ifneq ($(CONFIG_HAVE_ARCH_MEMCPY),y) +smm-y += memcpy.c +endif +smm-y += cbfs.c memset.c memcmp.c smm-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c smm-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c smm-$(CONFIG_USBDEBUG) += usbdebug.c

1 0

Patch set updated for coreboot: 724cda4 S3 code in the mainboard.
by Zheng Bao 23 Mar '12

23 Mar '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/624 -gerrit commit 724cda4620ede27e2b41bd42aabd204e30824745 Author: zbao <fishbaozi(a)gmail.com> Date: Fri Mar 23 11:54:23 2012 +0800 S3 code in the mainboard. Persimmon is the demo board. Tested by Linux and Windows 7. Change-Id: I5ded942b51e63ebeb08ace0b202b4ed239b0c14c Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- src/mainboard/amd/persimmon/BiosCallOuts.c | 21 ++- src/mainboard/amd/persimmon/BiosCallOuts.h | 4 +- src/mainboard/amd/persimmon/Kconfig | 1 + src/mainboard/amd/persimmon/PlatformGnbPcie.c | 2 +- .../amd/persimmon/PlatformGnbPcieComplex.h | 1 + src/mainboard/amd/persimmon/agesawrapper.c | 173 +++++++++++++++++++- src/mainboard/amd/persimmon/agesawrapper.h | 5 + src/mainboard/amd/persimmon/buildOpts.c | 6 +- src/mainboard/amd/persimmon/get_bus_conf.c | 21 ++- src/mainboard/amd/persimmon/mainboard.c | 16 ++- src/mainboard/amd/persimmon/romstage.c | 90 ++++++++-- 11 files changed, 303 insertions(+), 37 deletions(-) diff --git a/src/mainboard/amd/persimmon/BiosCallOuts.c b/src/mainboard/amd/persimmon/BiosCallOuts.c index c8379ff..600f932 100644 --- a/src/mainboard/amd/persimmon/BiosCallOuts.c +++ b/src/mainboard/amd/persimmon/BiosCallOuts.c @@ -81,6 +81,10 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AGESA_STATUS CalloutStatus; UINTN CallOutCount = sizeof (BiosCallouts) / sizeof (BiosCallouts [0]); + /* + * printk(BIOS_SPEW,"%s function: %x\n", __func__, (u32) Func); + */ + CalloutStatus = AGESA_UNSUPPORTED; for (i = 0; i < CallOutCount; i++) { @@ -115,8 +119,10 @@ AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AllocParams->BufferPointer = NULL; AvailableHeapSize = BIOS_HEAP_SIZE - sizeof (BIOS_HEAP_MANAGER); - BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS; - BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS; + BiosHeapBaseAddr = (UINT8 *) GetHeapBase(&(AllocParams->StdHeader)); + BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BiosHeapBaseAddr; + + printk(BIOS_SPEW, "%s BiosHeapBaseAddr: %x\n", __func__, (u32) BiosHeapBaseAddr); if (BiosHeapBasePtr->StartOfAllocatedNodes == 0) { /* First allocation */ @@ -237,12 +243,13 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) BIOS_HEAP_MANAGER *BiosHeapBasePtr; AGESA_BUFFER_PARAMS *AllocParams; - BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS; - BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS; - AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr; /* Find target node to deallocate in list of allocated nodes. + BiosHeapBaseAddr = (UINT8 *) GetHeapBase(&(AllocParams->StdHeader)); + BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BiosHeapBaseAddr; + + Return AGESA_BOUNDS_CHK if the BufferHandle is not found */ AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; @@ -348,8 +355,8 @@ AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr; - BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS; - BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS; + BiosHeapBaseAddr = (UINT8 *) GetHeapBase(&(AllocParams->StdHeader)); + BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BiosHeapBaseAddr; AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); diff --git a/src/mainboard/amd/persimmon/BiosCallOuts.h b/src/mainboard/amd/persimmon/BiosCallOuts.h index d9e4497..071c73c 100644 --- a/src/mainboard/amd/persimmon/BiosCallOuts.h +++ b/src/mainboard/amd/persimmon/BiosCallOuts.h @@ -23,8 +23,8 @@ #include "Porting.h" #include "AGESA.h" -#define BIOS_HEAP_START_ADDRESS 0x00010000 -#define BIOS_HEAP_SIZE 0x20000 /* 64MB */ +#define BIOS_HEAP_SIZE 0x20000 +#define BSP_STACK_BASE_ADDR 0x30000 typedef struct _BIOS_HEAP_MANAGER { //UINT32 AvailableSize; diff --git a/src/mainboard/amd/persimmon/Kconfig b/src/mainboard/amd/persimmon/Kconfig index 9212e20..27e27a5 100644 --- a/src/mainboard/amd/persimmon/Kconfig +++ b/src/mainboard/amd/persimmon/Kconfig @@ -33,6 +33,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select HAVE_MAINBOARD_RESOURCES + select HAVE_ACPI_RESUME select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID diff --git a/src/mainboard/amd/persimmon/PlatformGnbPcie.c b/src/mainboard/amd/persimmon/PlatformGnbPcie.c index 5e37f51..bdfcb66 100644 --- a/src/mainboard/amd/persimmon/PlatformGnbPcie.c +++ b/src/mainboard/amd/persimmon/PlatformGnbPcie.c @@ -23,6 +23,7 @@ #include "heapManager.h" #include "PlatformGnbPcieComplex.h" #include "Filecode.h" +#include "BiosCallOuts.h" #define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE @@ -165,4 +166,3 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; InitEarly->GnbConfig.PsppPolicy = 0; } - diff --git a/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h b/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h index b50cb1a..a49be62 100644 --- a/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h +++ b/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h @@ -23,6 +23,7 @@ #include "Porting.h" #include "AGESA.h" #include "amdlib.h" +#include <cpu/amd/agesa/s3_resume.h> //GNB GPP Port4 #define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable diff --git a/src/mainboard/amd/persimmon/agesawrapper.c b/src/mainboard/amd/persimmon/agesawrapper.c index 6e9997f..53ca04c 100644 --- a/src/mainboard/amd/persimmon/agesawrapper.c +++ b/src/mainboard/amd/persimmon/agesawrapper.c @@ -33,10 +33,12 @@ #include "cpuLateInit.h" #include "Dispatcher.h" #include "cpuCacheInit.h" +#include "heapManager.h" #include "amdlib.h" #include "PlatformGnbPcieComplex.h" #include "Filecode.h" #include <arch/io.h> +#include <cpu/amd/agesa/s3_resume.h> #define FILECODE UNASSIGNED_FILE_FILECODE @@ -243,6 +245,35 @@ agesawrapper_amdinitearly ( return (UINT32)status; } + +UINT32 GetHeapBase( + AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT64 MsrReg; + UINT32 sys_mem, uma_base, uma_size; + + /* TOP_MEM: the top of DRAM below 4G */ + LibAmdMsrRead(TOP_MEM, &MsrReg, StdHeader); + + /* refer to UMA Size Consideration in Family14h BKDG. */ + sys_mem = (UINT32)(MsrReg & 0xFFFFFFFFUL) + 0x1000000; // Ignore 16MB allocated for C6 when finding UMA size, refer MemNGetUmaSizeON() + if ((MsrReg & 0x0000000F00000000) || (sys_mem >= 0x80000000)) { + uma_size = 0x18000000; /* >= 2G memory, 384M recommended UMA */ + } + else { + if (sys_mem >= 0x40000000) { + uma_size = 0x10000000; /* >= 1G memory, 256M recommended UMA */ + } + else { + uma_size = 0x4000000; /* <1G memory, 64M recommended UMA */ + } + } + + uma_base = (UINT32)(MsrReg & 0xFFFFFFFFUL) - uma_size ; /* TOP_MEM1 */ + return uma_base - BIOS_HEAP_SIZE; +} + UINT32 agesawrapper_amdinitpost ( VOID @@ -272,7 +303,7 @@ agesawrapper_amdinitpost ( AmdReleaseStruct (&AmdParamStruct); /* Initialize heap space */ - BiosManagerPtr = (BIOS_HEAP_MANAGER *)BIOS_HEAP_START_ADDRESS; + BiosManagerPtr = (BIOS_HEAP_MANAGER *)GetHeapBase(&AmdParamStruct.StdHeader); HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof (BIOS_HEAP_MANAGER)); for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++) { @@ -496,6 +527,146 @@ agesawrapper_amdinitlate ( return (UINT32)Status; } +#if CONFIG_HAVE_ACPI_RESUME == 1 +UINT32 +agesawrapper_amdinitresume ( + VOID + ) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_RESUME_PARAMS *AmdResumeParamsPtr; + S3_DATA_TYPE S3DataType; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME; + AmdParamStruct.AllocationMethod = PreMemHeap; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct (&AmdParamStruct); + + AmdResumeParamsPtr = (AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr; + + AmdResumeParamsPtr->S3DataBlock.NvStorageSize = 0; + AmdResumeParamsPtr->S3DataBlock.VolatileStorageSize = 0; + S3DataType = S3DataTypeNonVolatile; + + OemAgesaGetS3Info (S3DataType, + (u32 *) &AmdResumeParamsPtr->S3DataBlock.NvStorageSize, + (void **) &AmdResumeParamsPtr->S3DataBlock.NvStorage); + + status = AmdInitResume ((AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr); + + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AmdReleaseStruct (&AmdParamStruct); + + return (UINT32)status; +} + +UINT32 +agesawrapper_amds3laterestore ( + VOID + ) +{ + AGESA_STATUS Status; + AMD_INTERFACE_PARAMS AmdInterfaceParams; + AMD_S3LATE_PARAMS AmdS3LateParams; + AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; + S3_DATA_TYPE S3DataType; + + LibAmdMemFill (&AmdS3LateParams, + 0, + sizeof (AMD_S3LATE_PARAMS), + &(AmdS3LateParams.StdHeader)); + AmdInterfaceParams.StdHeader.ImageBasePtr = 0; + AmdInterfaceParams.AllocationMethod = ByHost; + AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE; + AmdInterfaceParams.NewStructPtr = &AmdS3LateParams; + AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdS3LateParamsPtr = &AmdS3LateParams; + AmdInterfaceParams.NewStructSize = sizeof (AMD_S3LATE_PARAMS); + + AmdCreateStruct (&AmdInterfaceParams); + + AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = 0; + S3DataType = S3DataTypeVolatile; + + OemAgesaGetS3Info (S3DataType, + (u32 *) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize, + (void **) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorage); + + Status = AmdS3LateRestore (AmdS3LateParamsPtr); + if (Status != AGESA_SUCCESS) { + agesawrapper_amdreadeventlog(); + ASSERT(Status == AGESA_SUCCESS); + } + + return (UINT32)Status; +} + +UINT32 +agesawrapper_amdS3Save ( + VOID + ) +{ + AGESA_STATUS Status; + AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr; + AMD_INTERFACE_PARAMS AmdInterfaceParams; + S3_DATA_TYPE S3DataType; + + LibAmdMemFill (&AmdInterfaceParams, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdInterfaceParams.StdHeader)); + + AmdInterfaceParams.StdHeader.ImageBasePtr = 0; + AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; + AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdInterfaceParams.AllocationMethod = PostMemDram; + AmdInterfaceParams.AgesaFunctionName = AMD_S3_SAVE; + AmdInterfaceParams.StdHeader.AltImageBasePtr = 0; + AmdInterfaceParams.StdHeader.Func = 0; + AmdCreateStruct(&AmdInterfaceParams); + + AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *)AmdInterfaceParams.NewStructPtr; + AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader; + + Status = AmdS3Save (AmdS3SaveParamsPtr); + if (Status != AGESA_SUCCESS) { + agesawrapper_amdreadeventlog(); + ASSERT(Status == AGESA_SUCCESS); + } + + S3DataType = S3DataTypeNonVolatile; + + Status = OemAgesaSaveS3Info ( + S3DataType, + AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, + AmdS3SaveParamsPtr->S3DataBlock.NvStorage); + + if (AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize != 0) { + S3DataType = S3DataTypeVolatile; + + Status = OemAgesaSaveS3Info ( + S3DataType, + AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, + AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage + ); + } + + OemAgesaSaveMtrr(); + AmdReleaseStruct (&AmdInterfaceParams); + + return (UINT32)Status; +} +#endif + UINT32 agesawrapper_amdlaterunaptask ( UINT32 Func, diff --git a/src/mainboard/amd/persimmon/agesawrapper.h b/src/mainboard/amd/persimmon/agesawrapper.h index 7bed570..7babd58 100644 --- a/src/mainboard/amd/persimmon/agesawrapper.h +++ b/src/mainboard/amd/persimmon/agesawrapper.h @@ -84,7 +84,12 @@ UINT32 agesawrapper_amdreadeventlog (void); UINT32 agesawrapper_amdinitcpuio (void); UINT32 agesawrapper_amdinitmmio (void); +UINT32 agesawrapper_amdinitresume (void); +UINT32 agesawrapper_amdS3Save (void); +UINT32 agesawrapper_amds3laterestore (void); UINT32 agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, VOID *ConfigPtr); void *agesawrapper_getlateinitptr (int pick); +UINT32 GetHeapBase(AMD_CONFIG_PARAMS *StdHeader); + #endif diff --git a/src/mainboard/amd/persimmon/buildOpts.c b/src/mainboard/amd/persimmon/buildOpts.c index 3e5b14e..389e1d4 100644 --- a/src/mainboard/amd/persimmon/buildOpts.c +++ b/src/mainboard/amd/persimmon/buildOpts.c @@ -120,8 +120,8 @@ #define AGESA_ENTRY_INIT_LATE TRUE #define AGESA_ENTRY_INIT_S3SAVE TRUE #define AGESA_ENTRY_INIT_RESUME TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE FALSE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE +#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE +#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE #define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER @@ -169,7 +169,7 @@ //#define BLDCFG_USE_HT_ASSIST TRUE //#define BLDCFG_USE_ATM_MODE TRUE //#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm -#define BLDCFG_S3_LATE_RESTORE FALSE +#define BLDCFG_S3_LATE_RESTORE TRUE //#define BLDCFG_USE_32_BYTE_REFRESH FALSE //#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY FALSE //#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance diff --git a/src/mainboard/amd/persimmon/get_bus_conf.c b/src/mainboard/amd/persimmon/get_bus_conf.c index 0142762..4c094ae 100644 --- a/src/mainboard/amd/persimmon/get_bus_conf.c +++ b/src/mainboard/amd/persimmon/get_bus_conf.c @@ -51,6 +51,9 @@ u32 sbdn_sb800; static u32 get_bus_conf_done = 0; +#if CONFIG_HAVE_ACPI_RESUME == 1 +extern u8 acpi_slp_type; +#endif void get_bus_conf(void) { @@ -80,11 +83,20 @@ void get_bus_conf(void) * of each of the write functions called prior to the ACPI write functions, so this * becomes the best place for this call. */ +#if CONFIG_HAVE_ACPI_RESUME == 1 + if (acpi_slp_type != 3) { + status = agesawrapper_amdinitlate(); + if(status) + printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); + status = agesawrapper_amdS3Save(); + if(status) + printk(BIOS_DEBUG, "agesawrapper_amds3save failed: %x \n", status); + } +#else status = agesawrapper_amdinitlate(); - if(status) { + if(status) printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); - } - +#endif sbdn_sb800 = 0; for (i = 0; i < 3; i++) { @@ -124,7 +136,8 @@ void get_bus_conf(void) for (j = bus_sb800[2]; j < bus_isa; j++) bus_type[j] = 1; - /* I/O APICs: APIC ID Version State Address */ + + /* I/O APICs: APIC ID Version State Address */ bus_isa = 10; apicid_base = CONFIG_MAX_CPUS; apicid_sb800 = apicid_base; diff --git a/src/mainboard/amd/persimmon/mainboard.c b/src/mainboard/amd/persimmon/mainboard.c index 3b181a1..9a8428e 100644 --- a/src/mainboard/amd/persimmon/mainboard.c +++ b/src/mainboard/amd/persimmon/mainboard.c @@ -23,10 +23,13 @@ #include <arch/io.h> #include <boot/tables.h> #include <cpu/x86/msr.h> -#include <cpu/amd/mtrr.h> #include <device/pci_def.h> -//#include <southbridge/amd/sb800/sb800.h> +#include <southbridge/amd/sb800/sb800.h> +#include <arch/acpi.h> #include "chip.h" +#include "BiosCallOuts.h" +#include <cpu/amd/agesa/s3_resume.h> +#include <cpu/amd/mtrr.h> void set_pcie_reset(void); void set_pcie_dereset(void); @@ -56,6 +59,14 @@ static void persimmon_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); +/* + * The mainboard is the first place that we get control in ramstage. Check + * for S3 resume and call the approriate AGESA/CIMx resume functions. + */ +#if CONFIG_HAVE_ACPI_RESUME == 1 + acpi_slp_type = acpi_get_sleep_type(); +#endif + #if (CONFIG_GFXUMA == 1) msr_t msr, msr2; uint32_t sys_mem; @@ -110,6 +121,7 @@ int add_mainboard_resources(struct lb_memory *mem) #endif return 0; } + struct chip_operations mainboard_ops = { CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard") .enable_dev = persimmon_enable, diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c index dfb1aca..f52b447 100644 --- a/src/mainboard/amd/persimmon/romstage.c +++ b/src/mainboard/amd/persimmon/romstage.c @@ -35,9 +35,14 @@ #include "cpu/x86/lapic/boot_cpu.c" #include "pc80/i8254.c" #include "pc80/i8259.c" +#include <cpu/x86/cache.h> #include "sb_cimx.h" #include "SBPLATFORM.h" +#include "cbmem.h" +#include "cpu/amd/mtrr.h" +#include "cpu/amd/agesa/s3_resume.h" +void disable_cache_as_ram(void); /* cache_as_ram.inc */ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); #define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1) @@ -46,6 +51,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; +#if CONFIG_HAVE_ACPI_RESUME == 1 + void *resume_backup_memory; +#endif + /* * All cores: allow caching of flash chip code and data * (there are no cache-as-ram reliability concerns with family 14h) @@ -98,28 +107,75 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) else printk(BIOS_DEBUG, "passed.\n"); - post_code(0x40); - printk(BIOS_DEBUG, "agesawrapper_amdinitpost "); - val = agesawrapper_amdinitpost (); - if (val) - printk(BIOS_DEBUG, "error level: %x \n", val); - else - printk(BIOS_DEBUG, "passed.\n"); - - post_code(0x41); - printk(BIOS_DEBUG, "agesawrapper_amdinitenv "); - val = agesawrapper_amdinitenv (); - if (val) - printk(BIOS_DEBUG, "error level: %x \n", val); - else - printk(BIOS_DEBUG, "passed.\n"); +#if CONFIG_HAVE_ACPI_RESUME == 1 + if (!acpi_is_wakeup_early()) { /* Check for S3 resume */ +#endif + post_code(0x40); + printk(BIOS_DEBUG, "agesawrapper_amdinitpost "); + val = agesawrapper_amdinitpost (); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); + + post_code(0x42); + printk(BIOS_DEBUG, "agesawrapper_amdinitenv "); + val = agesawrapper_amdinitenv (); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); + +#if CONFIG_HAVE_ACPI_RESUME == 1 + } else { /* S3 detect */ + printk(BIOS_INFO, "S3 detected\n"); + + post_code(0x60); + printk(BIOS_DEBUG, "agesawrapper_amdinitresume "); + val = agesawrapper_amdinitresume(); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); + + printk(BIOS_DEBUG, "agesawrapper_amds3laterestore "); + val = agesawrapper_amds3laterestore (); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); + + post_code(0x61); + printk(BIOS_DEBUG, "Find resume memory location\n"); + resume_backup_memory = backup_resume(); + + post_code(0x62); + printk(BIOS_DEBUG, "Move CAR stack.\n"); + move_stack_high_mem(resume_backup_memory + HIGH_MEMORY_SAVE); + printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE)); + + post_code(0x63); + disable_cache_as_ram(); + printk(BIOS_DEBUG, "CAR disabled.\n"); + set_resume_cache(); + + /* + * Copy the system memory that is in the ramstage area to the + * reserved area. + */ + if (resume_backup_memory) + memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE); + + printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n"); + } +#endif /* Initialize i8259 pic */ - post_code(0x41); + post_code(0x43); setup_i8259 (); /* Initialize i8254 timers */ - post_code(0x42); + post_code(0x44); setup_i8254 (); post_code(0x50);

1 0

Patch set updated for coreboot: d123472 S3 code whitespaces changes.
by Zheng Bao 23 Mar '12

23 Mar '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/625 -gerrit commit d123472dc4e4bb9475143776cc67eec9e9a4c69f Author: zbao <fishbaozi(a)gmail.com> Date: Fri Mar 23 11:55:13 2012 +0800 S3 code whitespaces changes. some blank changing is integrated into the previous patches, which hold the unsplitted diff hunk. Change-Id: If9e5066927c5e27fee7ac8422dbfbf2cbeac7df5 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- src/cpu/amd/agesa/family14/model_14_init.c | 40 ++++---- src/mainboard/amd/persimmon/BiosCallOuts.c | 101 +++++++++--------- src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.c | 22 ++-- src/vendorcode/amd/agesa/f14/gcccar.inc | 136 ++++++++++++------------ 4 files changed, 151 insertions(+), 148 deletions(-) diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c index 4fd2b85..d90695a 100644 --- a/src/cpu/amd/agesa/family14/model_14_init.c +++ b/src/cpu/amd/agesa/family14/model_14_init.c @@ -39,22 +39,22 @@ msr_t rdmsr_amd(u32 index) { - msr_t result; - __asm__ __volatile__( - "rdmsr" - :"=a"(result.lo), "=d"(result.hi) - :"c"(index), "D"(0x9c5a203a) - ); - return result; + msr_t result; + __asm__ __volatile__( + "rdmsr" + :"=a"(result.lo), "=d"(result.hi) + :"c"(index), "D"(0x9c5a203a) + ); + return result; } void wrmsr_amd(u32 index, msr_t msr) { - __asm__ __volatile__( - "wrmsr" - : /* No outputs */ - :"c"(index), "a"(msr.lo), "d"(msr.hi), "D"(0x9c5a203a) - ); + __asm__ __volatile__( + "wrmsr" + : /* No outputs */ + :"c"(index), "a"(msr.lo), "d"(msr.hi), "D"(0x9c5a203a) + ); } static void model_14_init(device_t dev) @@ -140,18 +140,18 @@ static void model_14_init(device_t dev) } static struct device_operations cpu_dev_ops = { - .init = model_14_init, + .init = model_14_init, }; static struct cpu_device_id cpu_table[] = { - { X86_VENDOR_AMD, 0x500f00 }, /* ON-A0 */ - { X86_VENDOR_AMD, 0x500f01 }, /* ON-A1 */ - { X86_VENDOR_AMD, 0x500f10 }, /* ON-B0 */ - { X86_VENDOR_AMD, 0x500f20 }, /* ON-C0 */ - { 0, 0 }, + { X86_VENDOR_AMD, 0x500f00 }, /* ON-A0 */ + { X86_VENDOR_AMD, 0x500f01 }, /* ON-A1 */ + { X86_VENDOR_AMD, 0x500f10 }, /* ON-B0 */ + { X86_VENDOR_AMD, 0x500f20 }, /* ON-C0 */ + { 0, 0 }, }; static const struct cpu_driver model_14 __cpu_driver = { - .ops = &cpu_dev_ops, - .id_table = cpu_table, + .ops = &cpu_dev_ops, + .id_table = cpu_table, }; diff --git a/src/mainboard/amd/persimmon/BiosCallOuts.c b/src/mainboard/amd/persimmon/BiosCallOuts.c index 600f932..06426c2 100644 --- a/src/mainboard/amd/persimmon/BiosCallOuts.c +++ b/src/mainboard/amd/persimmon/BiosCallOuts.c @@ -99,20 +99,20 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - UINT32 AvailableHeapSize; - UINT8 *BiosHeapBaseAddr; - UINT32 CurrNodeOffset; - UINT32 PrevNodeOffset; - UINT32 FreedNodeOffset; - UINT32 BestFitNodeOffset; - UINT32 BestFitPrevNodeOffset; - UINT32 NextFreeOffset; - BIOS_BUFFER_NODE *CurrNodePtr; - BIOS_BUFFER_NODE *FreedNodePtr; - BIOS_BUFFER_NODE *BestFitNodePtr; - BIOS_BUFFER_NODE *BestFitPrevNodePtr; - BIOS_BUFFER_NODE *NextFreePtr; - BIOS_HEAP_MANAGER *BiosHeapBasePtr; + UINT32 AvailableHeapSize; + UINT8 *BiosHeapBaseAddr; + UINT32 CurrNodeOffset; + UINT32 PrevNodeOffset; + UINT32 FreedNodeOffset; + UINT32 BestFitNodeOffset; + UINT32 BestFitPrevNodeOffset; + UINT32 NextFreeOffset; + BIOS_BUFFER_NODE *CurrNodePtr; + BIOS_BUFFER_NODE *FreedNodePtr; + BIOS_BUFFER_NODE *BestFitNodePtr; + BIOS_BUFFER_NODE *BestFitPrevNodePtr; + BIOS_BUFFER_NODE *NextFreePtr; + BIOS_HEAP_MANAGER *BiosHeapBasePtr; AGESA_BUFFER_PARAMS *AllocParams; AllocParams = ((AGESA_BUFFER_PARAMS *) ConfigPtr); @@ -155,8 +155,9 @@ AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) } CurrNodeOffset = CurrNodePtr->NextNodeOffset; /* If BufferHandle has not been allocated on the heap, CurrNodePtr here points - to the end of the allocated nodes list. + to the end of the allocated nodes list. */ + } /* Find the node that best fits the requested buffer size */ FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes; @@ -205,7 +206,7 @@ AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) } /* If BestFitNode is the first buffer in the list, then update - StartOfFreedNodes to reflect the new free node + StartOfFreedNodes to reflect the new free node */ if (BestFitNodeOffset == BiosHeapBasePtr->StartOfFreedNodes) { BiosHeapBasePtr->StartOfFreedNodes = NextFreeOffset; @@ -230,33 +231,33 @@ AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - UINT8 *BiosHeapBaseAddr; - UINT32 AllocNodeOffset; - UINT32 PrevNodeOffset; - UINT32 NextNodeOffset; - UINT32 FreedNodeOffset; - UINT32 EndNodeOffset; - BIOS_BUFFER_NODE *AllocNodePtr; - BIOS_BUFFER_NODE *PrevNodePtr; - BIOS_BUFFER_NODE *FreedNodePtr; - BIOS_BUFFER_NODE *NextNodePtr; - BIOS_HEAP_MANAGER *BiosHeapBasePtr; + UINT8 *BiosHeapBaseAddr; + UINT32 AllocNodeOffset; + UINT32 PrevNodeOffset; + UINT32 NextNodeOffset; + UINT32 FreedNodeOffset; + UINT32 EndNodeOffset; + BIOS_BUFFER_NODE *AllocNodePtr; + BIOS_BUFFER_NODE *PrevNodePtr; + BIOS_BUFFER_NODE *FreedNodePtr; + BIOS_BUFFER_NODE *NextNodePtr; + BIOS_HEAP_MANAGER *BiosHeapBasePtr; AGESA_BUFFER_PARAMS *AllocParams; AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr; - /* Find target node to deallocate in list of allocated nodes. BiosHeapBaseAddr = (UINT8 *) GetHeapBase(&(AllocParams->StdHeader)); BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BiosHeapBaseAddr; - Return AGESA_BOUNDS_CHK if the BufferHandle is not found + /* Find target node to deallocate in list of allocated nodes. + Return AGESA_BOUNDS_CHK if the BufferHandle is not found */ AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); PrevNodeOffset = AllocNodeOffset; - while (AllocNodePtr->BufferHandle != AllocParams->BufferHandle) { + while (AllocNodePtr->BufferHandle != AllocParams->BufferHandle) { if (AllocNodePtr->NextNodeOffset == 0) { return AGESA_BOUNDS_CHK; } @@ -290,10 +291,11 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) /* Clear the BufferSize and NextNodeOffset of the previous first node */ FreedNodePtr->BufferSize = 0; FreedNodePtr->NextNodeOffset = 0; + } else { /* Otherwise, add freed node to the start of the list - Update NextNodeOffset and BufferSize to include the - size of BIOS_BUFFER_NODE + Update NextNodeOffset and BufferSize to include the + size of BIOS_BUFFER_NODE */ AllocNodePtr->NextNodeOffset = FreedNodeOffset; } @@ -301,21 +303,21 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) BiosHeapBasePtr->StartOfFreedNodes = AllocNodeOffset; } else { /* Traverse list of freed nodes to find where the deallocated node - should be place + should be place */ NextNodeOffset = FreedNodeOffset; NextNodePtr = FreedNodePtr; while (AllocNodeOffset > NextNodeOffset) { PrevNodeOffset = NextNodeOffset; if (NextNodePtr->NextNodeOffset == 0) { - break; + break; } NextNodeOffset = NextNodePtr->NextNodeOffset; NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset); } /* If deallocated node is adjacent to the next node, - concatenate both nodes + concatenate both nodes */ if (NextNodeOffset == EndNodeOffset) { NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset); @@ -329,13 +331,14 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AllocNodePtr->NextNodeOffset = NextNodeOffset; } /* If deallocated node is adjacent to the previous node, - concatenate both nodes + concatenate both nodes */ PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset); EndNodeOffset = PrevNodeOffset + PrevNodePtr->BufferSize; if (AllocNodeOffset == EndNodeOffset) { PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset; PrevNodePtr->BufferSize += AllocNodePtr->BufferSize; + AllocNodePtr->BufferSize = 0; AllocNodePtr->NextNodeOffset = 0; } else { @@ -405,17 +408,17 @@ AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) // 0xCF9 (Reset Port). // switch (ResetType) { - case WARM_RESET_WHENEVER: - case COLD_RESET_WHENEVER: + case WARM_RESET_WHENEVER: + case COLD_RESET_WHENEVER: break; - case WARM_RESET_IMMEDIATELY: - case COLD_RESET_IMMEDIATELY: - Value = 0x06; - LibAmdIoWrite (AccessWidth8, 0xCf9, &Value, StdHeader); + case WARM_RESET_IMMEDIATELY: + case COLD_RESET_IMMEDIATELY: + Value = 0x06; + LibAmdIoWrite (AccessWidth8, 0xCf9, &Value, StdHeader); break; - default: + default: break; } @@ -562,13 +565,13 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { case 4: switch (ResetInfo->ResetControl) { - case AssertSlotReset: + case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); Data8 &= ~(UINT8)BIT6 ; Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 Status = AGESA_SUCCESS; break; - case DeassertSlotReset: + case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); Data8 |= BIT6 ; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 @@ -578,13 +581,13 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) break; case 6: switch (ResetInfo->ResetControl) { - case AssertSlotReset: + case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); Data8 &= ~(UINT8)BIT6 ; Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 Status = AGESA_SUCCESS; break; - case DeassertSlotReset: + case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); Data8 |= BIT6 ; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 @@ -594,13 +597,13 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) break; case 7: switch (ResetInfo->ResetControl) { - case AssertSlotReset: + case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02); Data8 &= ~(UINT8)BIT6 ; Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 Status = AGESA_SUCCESS; break; - case DeassertSlotReset: + case DeassertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); Data8 |= BIT6 ; Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.c index fa9abbf..938300a 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.c @@ -25,7 +25,7 @@ * * Copyright (c) 2011, Advanced Micro Devices, Inc. * All rights reserved. - * + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright @@ -33,10 +33,10 @@ * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. - * + * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -47,7 +47,7 @@ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * * *************************************************************************** * */ @@ -66,7 +66,7 @@ *---------------------------------------------------------------------------------------- */ -// typedef unsigned int uintptr_t; +// typedef unsigned int uintptr_t; /*---------------------------------------------------------------------------------------- * P R O T O T Y P E S O F L O C A L F U N C T I O N S @@ -78,28 +78,28 @@ SetIdtr ( IN IDT_BASE_LIMIT *IdtInfo, IN OUT AMD_CONFIG_PARAMS *StdHeaderPtr ); - + VOID GetCsSelector ( IN UINT16 *Selector, IN OUT AMD_CONFIG_PARAMS *StdHeaderPtr ); - + VOID NmiHandler ( IN OUT AMD_CONFIG_PARAMS *StdHeaderPtr ); - + VOID ExecuteHltInstruction ( IN OUT AMD_CONFIG_PARAMS *StdHeaderPtr ); - + VOID ExecuteWbinvdInstruction ( IN AMD_CONFIG_PARAMS *StdHeader ); - + /*---------------------------------------------------------------------------------------- * E X P O R T E D F U N C T I O N S *---------------------------------------------------------------------------------------- diff --git a/src/vendorcode/amd/agesa/f14/gcccar.inc b/src/vendorcode/amd/agesa/f14/gcccar.inc index ad5a21d..d81b6af 100644 --- a/src/vendorcode/amd/agesa/f14/gcccar.inc +++ b/src/vendorcode/amd/agesa/f14/gcccar.inc @@ -1,7 +1,7 @@ /* * Copyright (c) 2011, Advanced Micro Devices, Inc. * All rights reserved. - * + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright @@ -9,10 +9,10 @@ * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. - * + * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -23,9 +23,9 @@ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * */ - + /****************************************************************************** * AMD Generic Encapsulated Software Architecture * @@ -118,32 +118,32 @@ CR0_PE = 1 # Protection Enable CR0_NW = 29 # Not Write-through CR0_CD = 30 # Cache Disable CR0_PG = 31 # Paging Enable - -/* CPUID Functions */ - -CPUID_MODEL = 1 -AMD_CPUID_FMF = 0x80000001 /* Family Model Features information */ -AMD_CPUID_APIC = 0x80000008 /* Long Mode and APIC info., core count */ - -NB_CFG = 0x0C001001F /* Northbridge Configuration Register */ - INIT_APIC_ID_CPU_ID_LO = 54 /* InitApicIdCpuIdLo - is core# in high or low half of APIC ID? */ - -MTRR_SYS_CFG = 0x0C0010010 /* System Configuration Register */ - CHX_TO_DIRTY_DIS = 16 /* ChxToDirtyDis Change to dirty disable */ - SYS_UC_LOCK_EN = 17 /* SysUcLockEn System lock command enable */ - MTRR_FIX_DRAM_EN = 18 /* MtrrFixDramEn MTRR fixed RdDram and WrDram attributes enable */ - MTRR_FIX_DRAM_MOD_EN = 19 /* MtrrFixDramModEn MTRR fixed RdDram and WrDram modification enable */ - MTRR_VAR_DRAM_EN = 20 /* MtrrVarDramEn MTRR variable DRAM enable */ - MTRR_TOM2_EN = 21 /* MtrrTom2En MTRR top of memory 2 enable */ - -PERF_CONTROL3 = 0x0C0010003 /* Performance event control three */ - PERF_CONTROL3_RESERVE_L = 0x00200000 /* Preserve the reserved bits */ - PERF_CONTROL3_RESERVE_H = 0x0FCF0 /* Preserve the reserved bits */ - CONFIG_EVENT_L = 0x0F0E2 /* All cores with level detection */ - CONFIG_EVENT_H = 4 /* Increment count by number of event */ - /* occured in clock cycle */ - EVENT_ENABLE = 22 /* Enable the event */ -PERF_COUNTER3 = 0x0C0010007 /* Performance event counter three */ + +/* CPUID Functions */ + +CPUID_MODEL = 1 +AMD_CPUID_FMF = 0x80000001 /* Family Model Features information */ +AMD_CPUID_APIC = 0x80000008 /* Long Mode and APIC info., core count */ + +NB_CFG = 0x0C001001F /* Northbridge Configuration Register */ + INIT_APIC_ID_CPU_ID_LO = 54 /* InitApicIdCpuIdLo - is core# in high or low half of APIC ID? */ + +MTRR_SYS_CFG = 0x0C0010010 /* System Configuration Register */ + CHX_TO_DIRTY_DIS = 16 /* ChxToDirtyDis Change to dirty disable */ + SYS_UC_LOCK_EN = 17 /* SysUcLockEn System lock command enable */ + MTRR_FIX_DRAM_EN = 18 /* MtrrFixDramEn MTRR fixed RdDram and WrDram attributes enable */ + MTRR_FIX_DRAM_MOD_EN = 19 /* MtrrFixDramModEn MTRR fixed RdDram and WrDram modification enable */ + MTRR_VAR_DRAM_EN = 20 /* MtrrVarDramEn MTRR variable DRAM enable */ + MTRR_TOM2_EN = 21 /* MtrrTom2En MTRR top of memory 2 enable */ + +PERF_CONTROL3 = 0x0C0010003 /* Performance event control three */ + PERF_CONTROL3_RESERVE_L = 0x00200000 /* Preserve the reserved bits */ + PERF_CONTROL3_RESERVE_H = 0x0FCF0 /* Preserve the reserved bits */ + CONFIG_EVENT_L = 0x0F0E2 /* All cores with level detection */ + CONFIG_EVENT_H = 4 /* Increment count by number of event */ + /* occured in clock cycle */ + EVENT_ENABLE = 22 /* Enable the event */ +PERF_COUNTER3 = 0x0C0010007 /* Performance event counter three */ # Local use flags, in upper most byte if ESI FLAG_UNKNOWN_FAMILY = 24 # Signals that the family# of the installed processor is not recognized @@ -158,28 +158,28 @@ MSR_MASK = ((1 << MTRR_DEF_TYPE_EN)+(1 << MTRR_DEF_TYPE_FIX_EN)) * CPU MACROS - PUBLIC * ****************************************************************************/ -.macro _WRMSR - .byte 0x0f, 0x30 +.macro _WRMSR + .byte 0x0f, 0x30 .endm -.macro _RDMSR - .byte 0x0F, 0x32 +.macro _RDMSR + .byte 0x0F, 0x32 .endm .macro AMD_CPUID arg0 - .ifb \arg0 - mov $0x1, %eax + .ifb \arg0 + mov $0x1, %eax .byte 0x0F, 0x0A2 /* Execute instruction */ - bswap %eax + bswap %eax xchg %ah, %al /* Ext model in al now */ rol $0x08, %eax /* Ext model in ah, model in al */ and $0x0FFCF, ax /* Keep 23:16, 7:6, 3:0 */ .else - mov \arg0, %eax - .byte 0x0F, 0x0A2 + mov \arg0, %eax + .byte 0x0F, 0x0A2 .endif .endm - + /**************************************************************************** * * AMD_ENABLE_STACK_FAMILY_HOOK Macro - Stackless @@ -194,12 +194,12 @@ MSR_MASK = ((1 << MTRR_DEF_TYPE_EN)+(1 << MTRR_DEF_TYPE_FIX_EN)) ****************************************************************************/ .macro AMD_ENABLE_STACK_FAMILY_HOOK - AMD_ENABLE_STACK_FAMILY_HOOK_F10 - AMD_ENABLE_STACK_FAMILY_HOOK_F12 - AMD_ENABLE_STACK_FAMILY_HOOK_F14 - AMD_ENABLE_STACK_FAMILY_HOOK_F15 + AMD_ENABLE_STACK_FAMILY_HOOK_F10 + AMD_ENABLE_STACK_FAMILY_HOOK_F12 + AMD_ENABLE_STACK_FAMILY_HOOK_F14 + AMD_ENABLE_STACK_FAMILY_HOOK_F15 .endm - + /**************************************************************************** * * AMD_DISABLE_STACK_FAMILY_HOOK Macro - Stackless @@ -220,7 +220,7 @@ MSR_MASK = ((1 << MTRR_DEF_TYPE_EN)+(1 << MTRR_DEF_TYPE_FIX_EN)) AMD_DISABLE_STACK_FAMILY_HOOK_F15 .endm - + /**************************************************************************** * * GET_NODE_ID_CORE_ID Macro - Stackless @@ -252,9 +252,9 @@ MSR_MASK = ((1 << MTRR_DEF_TYPE_EN)+(1 << MTRR_DEF_TYPE_FIX_EN)) */ cmp $-1, %si # Has family (node/core) already been discovered? jnz node_core_exit # Br if yes - + mov $((1 << FLAG_UNKNOWN_FAMILY)+(1 << FLAG_IS_PRIMARY)), %esi # No, Set error code, Only let BSP continue - + mov $APIC_BASE_ADDRESS, %ecx # MSR:0000_001B _RDMSR bt $APIC_BSC, %eax # Is this the BSC? @@ -263,7 +263,7 @@ MSR_MASK = ((1 << MTRR_DEF_TYPE_EN)+(1 << MTRR_DEF_TYPE_FIX_EN)) node_core_exit: .endm - + /**************************************************************************** ## Family 10h MACROS ##*************************************************************************** @@ -291,7 +291,7 @@ node_core_exit: # * MSRC001_102A[ClLinesToNbDis]=1 # * No INVD or WBINVD, no exceptions, page faults or interrupts ****************************************************************************/ -.macro AMD_ENABLE_STACK_FAMILY_HOOK_F10 +.macro AMD_ENABLE_STACK_FAMILY_HOOK_F10 LOCAL fam10_enable_stack_hook_exit AMD_CPUID $CPUID_MODEL @@ -324,7 +324,7 @@ node_core_exit: jc fam10_skipClearingBit4 btr $INVD_WBINVD, %eax # disable INVD -> WBINVD conversion _WRMSR - + fam10_skipClearingBit4: mov %esi, %eax # load core# or %al, %al # If (BSP) @@ -347,7 +347,7 @@ fam10_skipClearingBit4: fam10_enable_stack_hook_exit: .endm - + /**************************************************************************** * * AMD_DISABLE_STACK_FAMILY_HOOK_F10 Macro - Stackless @@ -371,7 +371,7 @@ fam10_enable_stack_hook_exit: * * MSRC001_102A[IcDisSpecTlbWr]=0 * * MSRC001_102A[ClLinesToNbDis]=0 *****************************************************************************/ - + .macro AMD_DISABLE_STACK_FAMILY_HOOK_F10 LOCAL fam10_disable_stack_hook_exit @@ -427,7 +427,7 @@ fam10_enable_stack_hook_exit: _WRMSR # Disable the event fam10_disable_stack_hook_exit: -.endm +.endm /**************************************************************************** * @@ -589,7 +589,7 @@ node_core_f10_exit: jc fam12_skipClearingBit4 btr $INVD_WBINVD, %eax # disable INVD -> WBINVD conversion _WRMSR - + fam12_skipClearingBit4: mov $DE_CFG, %ecx # MSR:C001_1029 _RDMSR @@ -893,7 +893,7 @@ node_core_f14_exit: _RDMSR btr $INVD_WBINVD, %eax # disable INVD -> WBINVD conversion _WRMSR - + fam15_skipClearingBit4: mov $LS_CFG, %ecx # MSR:C001_1020 _RDMSR @@ -973,7 +973,7 @@ fam15_enable_stack_hook_exit: btr $DIS_HW_PF, %eax # Turn on hardware prefetches #.endif # End workaround for erratum 498 0: - _WRMSR + _WRMSR #-------------------------------------------------------------------------- # Begin critical sequence in which EAX, BX, ECX, and EDX must be preserved. #-------------------------------------------------------------------------- @@ -1135,7 +1135,7 @@ node_core_f15_shared: #.break .if (ch == bl) # Does 2nd match MyCore#? cmp %bl, %ch je 9f - jmp 2f + jmp 2f #.else # No 2nd core 4: #.break .if (ch == bl) # Does 1st match MyCore#? @@ -1240,7 +1240,7 @@ node_core_f15_exit: * | >|MA|IN| B|IO|S |RA|NG|E | | | | | | |< | >|EX|TE|ND|ED| B|IO|S |ZO|NE| | | | | |< | * +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ *****************************************************************************/ -.macro AMD_ENABLE_STACK +.macro AMD_ENABLE_STACK # These are local labels. Declared so linker doesn't cause 'redefined label' errors LOCAL SetupStack @@ -1308,7 +1308,7 @@ SetupStack: #.if (carry?) # Families using shared groups do not need to clear the MTRRs since that is done at power-on reset # Note: Relying on MSRs to be cleared to 0's at reset for families w/shared cores # Clear all variable and Fixed MTRRs for non-shared cores - jnc 0f + jnc 0f mov $AMD_MTRR_VARIABLE_BASE0, %ecx xor %eax, %eax xor %edx, %edx @@ -1344,20 +1344,20 @@ SetupStack: _WRMSR #.endif # End Is_Primary #.endif # End Stack_ReEntry - 0: + 0: # Clear IORRs (C001_0016-19) and TOM2(C001_001D) for all cores xor %eax, %eax xor %edx, %edx mov $IORR_BASE, %ecx # MSR:C001_0016 - 0019 #.while (cl != 1Ah) jmp 1f - 2: + 2: _WRMSR inc %cl #.endw - 1: + 1: cmp $0x1A, %cl - jne 2b + jne 2b mov $TOP_MEM2, %ecx # MSR:C001_001D _WRMSR @@ -1428,7 +1428,7 @@ SetupStack: mov %eax, %ebp #.endif 0: - + # Now set the MTRR. Add this to already existing settings (don't clear any MTRR) mov $WB_DRAM_TYPE, %edi # Load Cache type in 1st slot mov %bh, %cl # ShiftCount = ((slot# ... @@ -1584,7 +1584,7 @@ ClearTheStack: # Stack base is in SS, stack pointer is * Destroyed: * eax, ecx, edx, esp *****************************************************************************/ -.macro AMD_DISABLE_STACK +.macro AMD_DISABLE_STACK mov %ebx, %esp # Save return address

1 0

Re: [coreboot] porting asus l1n64
by Marc Jones 22 Mar '12

22 Mar '12

Hi Julian, On Thu, Mar 22, 2012 at 4:19 PM, Julian Shulika <hercares(a)gmail.com> wrote: > With two cpus > > coreboot-4.0-2135-gccee625-dirty Thu Mar 22 20:39:08 EDT 2012 starting... > > *sysinfo range: [000cf000,000cf730] > bsp_apicid=00 > Enabling routing table for node 00 done. > Enabling SMP settings > (0,1) link=02 > (1,0) link=01 > setup_remote_node: done > Renaming current temporary node to 01 done. > Enabling routing table for node 01 > This will take some debug effort on your part. The K8 coreboot code is fairly old and doesn't have a anyone doing a lot of maintenance on it. You will need to add debug information to the source to narrow down the problems. Marc > > 2012/3/22 Julian Shulika <hercares(a)gmail.com> >> >> Hi. Motherboard Asus L1N64 with Dual Socket 1207 and switched >> mcp55,ite8716f,amd k8 cpus >> I have log from serial,that's all. >> >> coreboot-4.0-2135-gccee625-dirty Thu Mar 22 19:21:00 EDT 2012 starting... >> *sysinfo range: [000cf000,000cf730] >> bsp_apicid=00 >> Enabling routing table for node 00 done. >> Enabling SMP settings >> 01 nodes initialized. >> Enabling UP settings >> coherent_ht_finalize >> done >> core0 started: >> >> I attached files from lspci,flashrom,superiotool and /proc/gpio >> /proc/ioports >> > > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot -- http://se-eng.com

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Re: [coreboot] porting asus l1n64
by Julian Shulika 22 Mar '12

22 Mar '12

With two cpus *coreboot-4.0-2135-gccee625-dirty Thu Mar 22 20:39:08 EDT 2012 starting... *sysinfo range: [000cf000,000cf730] bsp_apicid=00 Enabling routing table for node 00 done. Enabling SMP settings (0,1) link=02 (1,0) link=01 setup_remote_node: done Renaming current temporary node to 01 done. Enabling routing table for node 01* 2012/3/22 Julian Shulika <hercares(a)gmail.com> > Hi. Motherboard Asus L1N64 with Dual Socket 1207 and switched > mcp55,ite8716f,amd k8 cpus > I have log from serial,that's all. > > *coreboot-4.0-2135-gccee625-dirty Thu Mar 22 19:21:00 EDT 2012 starting... > *sysinfo range: [000cf000,000cf730] > bsp_apicid=00 > Enabling routing table for node 00 done. > Enabling SMP settings > 01 nodes initialized. > Enabling UP settings > coherent_ht_finalize > done > core0 started: * > > I attached files from lspci,flashrom,superiotool and /proc/gpio > /proc/ioports > >

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porting asus l1n64
by Julian Shulika 22 Mar '12

22 Mar '12

Hi. Motherboard Asus L1N64 with Dual Socket 1207 and switched mcp55,ite8716f,amd k8 cpus I have log from serial,that's all. *coreboot-4.0-2135-gccee625-dirty Thu Mar 22 19:21:00 EDT 2012 starting... *sysinfo range: [000cf000,000cf730] bsp_apicid=00 Enabling routing table for node 00 done. Enabling SMP settings 01 nodes initialized. Enabling UP settings coherent_ht_finalize done core0 started: * I attached files from lspci,flashrom,superiotool and /proc/gpio /proc/ioports

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coreboot March 2012