coreboot March 2012

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New patch to review for coreboot: e9bda83 Fix cleaning SeaBIOS from coreboot makefile
by Marc Jones 19 Mar '12

19 Mar '12

Marc Jones (marcj303(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/801 -gerrit commit e9bda83e277bceee880e3c79701f968e07f65673 Author: Marc Jones <marc.jones(a)se-eng.com> Date: Mon Mar 19 17:32:33 2012 -0600 Fix cleaning SeaBIOS from coreboot makefile The coreboot makefile didn't pass the OUT and CC variables to seabios, so the clean didn't clean anything. Change-Id: Ieaf0c417d6e5dfb9e0a11df70b03d6313919578b Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> --- Makefile.inc | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 86a072a..b4855d0 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -204,7 +204,7 @@ clean-for-update-target: rm -f $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc rm -f $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.* $(obj)/mainboard/$(MAINBOARDDIR)/dsdt.* rm -f $(obj)/cpu/x86/smm/smm_bin.c $(obj)/cpu/x86/smm/smm.* $(obj)/cpu/x86/smm/smm - $(MAKE) -C payloads/external/SeaBIOS -f Makefile.inc clean + $(MAKE) -C payloads/external/SeaBIOS -f Makefile.inc clean OUT=$(abspath $(obj)) HOSTCC="$(HOSTCC)" CC="$(CC)" LD="$(LD)" clean-target: rm -f $(obj)/coreboot*

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Patch set updated for coreboot: 5cf235c Fix chip name translations in sconfig
by Kyösti Mälkki 19 Mar '12

19 Mar '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/799 -gerrit commit 5cf235c001073d68e8b1427dd47e15b56e93097f Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Mar 18 20:19:28 2012 +0200 Fix chip name translations in sconfig Current bootblock initialisation functions do not have chip name in them. Fix sconfig behave the same way. Fix side-effects of name translation, treats original name as const. Change-Id: Iae26be8cefe7db11eeb8e62fce6f3b8bc9c1f4ed Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- util/sconfig/main.c | 41 +++++++++++++++++++++++++++++++---------- 1 files changed, 31 insertions(+), 10 deletions(-) diff --git a/util/sconfig/main.c b/util/sconfig/main.c index 181be38..4e3479b 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -37,6 +37,13 @@ typedef enum { static scan_t scan_mode = STATIC_MODE; +typedef enum { + UNSLASH, + SPLIT_1ST, + TO_LOWER, + TO_UPPER, +} translate_t; + static struct device root; static struct device mainboard = { .name = "mainboard", @@ -124,23 +131,31 @@ void postprocess_devtree(void) { } } -void translate_name(char *str, int uppercase) +char * translate_name(const char *str, translate_t mode) { - char *c; - for (c = str; *c; c++) { + char *b, *c; + b = c = strdup(str); + while (c && *c) { + if ((mode == SPLIT_1ST) && (*c == '/')) { + *c = 0; + break; + } if (*c == '/') *c = '_'; if (*c == '-') *c = '_'; - if (uppercase) + if (mode == TO_UPPER) *c = toupper(*c); + if (mode == TO_LOWER) + *c = tolower(*c); + c++; } + return b; } struct device *new_chip(struct device *parent, struct device *bus, char *path) { struct device *new_chip = new_dev(parent, bus); new_chip->chiph_exists = 1; new_chip->name = path; - new_chip->name_underscore = strdup(new_chip->name); - translate_name(new_chip->name_underscore, 0); + new_chip->name_underscore = translate_name(new_chip->name, UNSLASH); new_chip->type = chip; new_chip->chip = new_chip; @@ -580,8 +595,11 @@ int main(int argc, char** argv) { h = &headers; while (h->next) { h = h->next; - translate_name(h->name, 0); - fprintf(autogen, "\tinit_%s();\n", h->name); + char * buf = translate_name(h->name, SPLIT_1ST); + if (buf) { + fprintf(autogen, "\tbootblock_%s_init();\n", buf); + free(buf); + } } fprintf(autogen, "\treturn 0;\n}\n"); @@ -595,8 +613,11 @@ int main(int argc, char** argv) { h = &headers; while (h->next) { h = h->next; - translate_name(h->name, 1); - fprintf(autogen, "\tselect %s\n", h->name); + char * buf = translate_name(h->name, TO_UPPER); + if (buf) { + fprintf(autogen, "\tselect %s\n", buf); + free(buf); + } } }

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Patch set updated for coreboot: 6523bb2 Auto-generate bootblock initialisation
by Kyösti Mälkki 19 Mar '12

19 Mar '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/473 -gerrit commit 6523bb2539710b646b738844edd7b22b26a16599 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Mar 16 18:10:10 2012 +0200 Auto-generate bootblock initialisation A new init function called from bootblock is declared as: - unsigned long init_mainboard(int bsp_cpu) For BSP CPU bootblock calls init_mainboard(true). For AP CPUs bootblock calls init_mainboard(false). Usually AP CPU has nothing to do here. By default, build toolchain creates and includes an init_mainboard() function in file build/mainboard/x/x/bootblock_autogen.h that executes init functions from any bootblock.c files for all chips listed in mainboard/devtree.cb. Alternatively a mainboard/x/x/bootblock.c file is added in the bootblock build, if a Kconfig option HAS_MAINBOARD_BOOTBLOCK is set. One should copy the auto-generated init_mainboard() to this file, and optionally read various bootstrap signals or status bits from super-io and southbridge component to gain some control over the selection of romstage to boot via the return value. Samples of such (yet not implemented) controls for boot behaviour: - Reset CMOS to defaults on user request (jumper). - Use fallback prefix after power-button 4s override. - Refuse boot after intruder detection. - On remote wakeup, request network boot. Change-Id: Ib1d101cdd68993530c9c7a653ac000a01de52ac2 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/Kconfig | 7 ++----- src/arch/x86/Makefile.inc | 11 ++++++++--- src/arch/x86/include/bootblock_common.h | 17 +---------------- src/arch/x86/init/bootblock_normal.c | 8 ++++---- src/arch/x86/init/bootblock_simple.c | 10 +++++----- src/mainboard/hp/dl165_g6_fam10/Kconfig | 5 +---- src/mainboard/hp/dl165_g6_fam10/bootblock.c | 10 +++++++++- src/northbridge/amd/amdfam10/Kconfig | 4 ---- src/northbridge/amd/amdk8/Kconfig | 4 ---- src/southbridge/amd/amd8111/Kconfig | 4 ---- src/southbridge/amd/cimx/sb700/Kconfig | 3 --- src/southbridge/amd/cimx/sb800/Kconfig | 3 --- src/southbridge/amd/cimx/sb900/Kconfig | 3 --- src/southbridge/amd/sb600/Kconfig | 3 --- src/southbridge/amd/sb700/Kconfig | 4 ---- src/southbridge/amd/sb800/Kconfig | 5 ----- src/southbridge/broadcom/bcm5785/Kconfig | 4 ---- src/southbridge/intel/i82371eb/Kconfig | 5 ----- src/southbridge/intel/i82801gx/Kconfig | 5 ----- src/southbridge/nvidia/ck804/Kconfig | 4 ---- src/southbridge/nvidia/mcp55/Kconfig | 4 ---- src/southbridge/sis/sis966/Kconfig | 4 ---- src/southbridge/via/vt8237r/Kconfig | 4 ---- 23 files changed, 30 insertions(+), 101 deletions(-) diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index c5a0c0e..c9f2643 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -67,8 +67,8 @@ config PC80_SYSTEM bool default y -config BOOTBLOCK_NORTHBRIDGE_INIT - string +config HAS_MAINBOARD_BOOTBLOCK + def_bool n config HAVE_CMOS_DEFAULT def_bool n @@ -77,9 +77,6 @@ config CMOS_DEFAULT_FILE string depends on HAVE_CMOS_DEFAULT -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - config BIG_ENDIAN bool default n diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index d3dac11..ff6d692 100755 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -324,11 +324,16 @@ $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.s: $(obj)/bootblock/bootblock.S $(obj @printf " CC $(subst $(obj)/,,$(@))\n" $(CC) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -I$(obj)/bootblock -include $(obj)/build.h -include $(obj)/config.h -I. -I$(src) $< -o $@ -$(obj)/mainboard/$(MAINBOARDDIR)/bootblock.inc: $(src)/arch/x86/init/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(objutil)/romcc/romcc $(OPTION_TABLE_H) +$(obj)/mainboard/$(MAINBOARDDIR)/bootblock.inc: $(src)/arch/x86/init/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(obj)/mainboard/$(MAINBOARDDIR)/bootblock_autogen.h $(objutil)/romcc/romcc $(OPTION_TABLE_H) @printf " ROMCC $(subst $(obj)/,,$(@))\n" - $(CC) $(INCLUDES) -MM -MT$(obj)/mainboard/$(MAINBOARDDIR)/bootblock.inc \ + $(CC) $(INCLUDES) -I$(@D) -MM -MT$(obj)/mainboard/$(MAINBOARDDIR)/bootblock.inc \ $< > $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.inc.d - $(ROMCC) -c -S $(bootblock_romccflags) $(ROMCCFLAGS) -I. $(INCLUDES) $< -o $@ + $(ROMCC) -c -S $(bootblock_romccflags) $(ROMCCFLAGS) -I. $(INCLUDES) -I$(@D) $< -o $@ + +$(obj)/mainboard/$(MAINBOARDDIR)/bootblock_autogen.h: $(src)/mainboard/$(MAINBOARDDIR)/devicetree.cb $(objutil)/sconfig/sconfig + @printf " SCONFIG $(subst $(src)/,,$(<)) (bootblock)\n" + mkdir -p $(@D) + $(objutil)/sconfig/sconfig $(MAINBOARDDIR) $(@D) -b $(@F) $(obj)/bootblock.elf: $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.o $(obj)/bootblock/ldscript.ld @printf " LINK $(subst $(obj)/,,$(@))\n" diff --git a/src/arch/x86/include/bootblock_common.h b/src/arch/x86/include/bootblock_common.h index bd19682..69ab22c 100644 --- a/src/arch/x86/include/bootblock_common.h +++ b/src/arch/x86/include/bootblock_common.h @@ -1,22 +1,7 @@ #include <cpu/x86/lapic/boot_cpu.c> -#ifdef CONFIG_BOOTBLOCK_CPU_INIT -#include CONFIG_BOOTBLOCK_CPU_INIT -#else -static void bootblock_cpu_init(void) { } -#endif -#ifdef CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT -#include CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT -#else -static void bootblock_northbridge_init(void) { } -#endif -#ifdef CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT -#include CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT -#else -static void bootblock_southbridge_init(void) { } -#endif - #include <arch/cbfs.h> +#include "bootblock_autogen.h" #if CONFIG_USE_OPTION_TABLE #include <pc80/mc146818rtc.h> diff --git a/src/arch/x86/init/bootblock_normal.c b/src/arch/x86/init/bootblock_normal.c index 19b3d5a..ddfb436 100644 --- a/src/arch/x86/init/bootblock_normal.c +++ b/src/arch/x86/init/bootblock_normal.c @@ -9,14 +9,14 @@ static const char *get_fallback(const char *stagelist) { static void main(unsigned long bist) { unsigned long entry; + int bsp_cpu = boot_cpu(); int boot_mode; const char *default_filenames = "normal/romstage\0fallback/romstage"; - if (boot_cpu()) { - bootblock_northbridge_init(); - bootblock_southbridge_init(); - bootblock_cpu_init(); + /* Mainboard-specific early init. */ + init_mainboard(bsp_cpu); + if (bsp_cpu) { #if CONFIG_USE_OPTION_TABLE sanitize_cmos(); #endif diff --git a/src/arch/x86/init/bootblock_simple.c b/src/arch/x86/init/bootblock_simple.c index 41f73b4..f4e4bbf 100644 --- a/src/arch/x86/init/bootblock_simple.c +++ b/src/arch/x86/init/bootblock_simple.c @@ -2,15 +2,15 @@ static void main(unsigned long bist) { - if (boot_cpu()) { - bootblock_northbridge_init(); - bootblock_southbridge_init(); - bootblock_cpu_init(); + int bsp_cpu = boot_cpu(); + + /* Mainboard-specific early init. */ + init_mainboard(bsp_cpu); #if CONFIG_USE_OPTION_TABLE + if (bsp_cpu) sanitize_cmos(); #endif - } const char* target1 = "fallback/romstage"; unsigned long entry; diff --git a/src/mainboard/hp/dl165_g6_fam10/Kconfig b/src/mainboard/hp/dl165_g6_fam10/Kconfig index cdff24f..547cc21 100644 --- a/src/mainboard/hp/dl165_g6_fam10/Kconfig +++ b/src/mainboard/hp/dl165_g6_fam10/Kconfig @@ -15,6 +15,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_BUS_CONFIG select HAVE_PIRQ_TABLE select HAVE_MP_TABLE + select HAS_MAINBOARD_BOOTBLOCK select LIFT_BSP_APIC_ID select BOARD_ROMSIZE_KB_1024 select RAMINIT_SYSINFO @@ -90,10 +91,6 @@ config HEAP_SIZE hex default 0xc0000 -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "mainboard/hp/dl165_g6_fam10/bootblock.c" - config MMCONF_SUPPORT_DEFAULT bool default y diff --git a/src/mainboard/hp/dl165_g6_fam10/bootblock.c b/src/mainboard/hp/dl165_g6_fam10/bootblock.c index 2c56c4c..dfece95 100644 --- a/src/mainboard/hp/dl165_g6_fam10/bootblock.c +++ b/src/mainboard/hp/dl165_g6_fam10/bootblock.c @@ -18,6 +18,9 @@ static inline void shc4307_exit_ext_func_mode(device_t dev) #define DBG_DEV PNP_DEV(SCH4307_CONFIG_PORT, 0x3) #define REGS_DEV PNP_DEV(SCH4307_CONFIG_PORT, 0xa) +/* FIXME: This appears to be a super-io initialisation, + * placed in the mainboard directory. + */ void shc4307_init(void) { shc4307_enter_ext_func_mode(CMOS_DEV); @@ -43,6 +46,11 @@ void shc4307_init(void) shc4307_exit_ext_func_mode(CMOS_DEV); } -static void bootblock_southbridge_init(void) { +static unsigned long init_mainboard(int bsp_cpu) +{ + if (!bsp_cpu) return 0; + bootblock_northbridge_init(); + //bootblock_southbridge_init(); shc4307_init(); + return 0; } diff --git a/src/northbridge/amd/amdfam10/Kconfig b/src/northbridge/amd/amdfam10/Kconfig index a14339e..633d378 100644 --- a/src/northbridge/amd/amdfam10/Kconfig +++ b/src/northbridge/amd/amdfam10/Kconfig @@ -59,10 +59,6 @@ config MMCONF_BUS_NUMBER int default 256 -config BOOTBLOCK_NORTHBRIDGE_INIT - string - default "northbridge/amd/amdfam10/bootblock.c" - config SB_HT_CHAIN_UNITID_OFFSET_ONLY bool default n diff --git a/src/northbridge/amd/amdk8/Kconfig b/src/northbridge/amd/amdk8/Kconfig index 70e75e9..b94ef42 100644 --- a/src/northbridge/amd/amdk8/Kconfig +++ b/src/northbridge/amd/amdk8/Kconfig @@ -51,10 +51,6 @@ config HW_MEM_HOLE_SIZE_AUTO_INC bool default n -config BOOTBLOCK_NORTHBRIDGE_INIT - string - default "northbridge/amd/amdk8/bootblock.c" - config SB_HT_CHAIN_UNITID_OFFSET_ONLY bool default n diff --git a/src/southbridge/amd/amd8111/Kconfig b/src/southbridge/amd/amd8111/Kconfig index fd244c8..03d0f29 100644 --- a/src/southbridge/amd/amd8111/Kconfig +++ b/src/southbridge/amd/amd8111/Kconfig @@ -22,7 +22,3 @@ config SOUTHBRIDGE_AMD_AMD8111 select IOAPIC select HAVE_HARD_RESET -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/amd/amd8111/bootblock.c" - depends on SOUTHBRIDGE_AMD_AMD8111 diff --git a/src/southbridge/amd/cimx/sb700/Kconfig b/src/southbridge/amd/cimx/sb700/Kconfig index 27338fc..ea5adf3 100644 --- a/src/southbridge/amd/cimx/sb700/Kconfig +++ b/src/southbridge/amd/cimx/sb700/Kconfig @@ -47,9 +47,6 @@ config ACPI_SCI_IRQ default 0x9 help Set SCI IRQ to 9. -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/amd/cimx/sb700/bootblock.c" config REDIRECT_SBCIMX_TRACE_TO_SERIAL bool "Redirect AMD Southbridge CIMX Trace to serial console" diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig index 79624e0..fc15c42 100644 --- a/src/southbridge/amd/cimx/sb800/Kconfig +++ b/src/southbridge/amd/cimx/sb800/Kconfig @@ -24,9 +24,6 @@ config SOUTHBRIDGE_AMD_CIMX_SB800 select AMD_SB_CIMX if SOUTHBRIDGE_AMD_CIMX_SB800 -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/amd/cimx/sb800/bootblock.c" config ENABLE_IDE_COMBINED_MODE bool "Enable SATA IDE combined mode" diff --git a/src/southbridge/amd/cimx/sb900/Kconfig b/src/southbridge/amd/cimx/sb900/Kconfig index 253d73f..09edd1b 100755 --- a/src/southbridge/amd/cimx/sb900/Kconfig +++ b/src/southbridge/amd/cimx/sb900/Kconfig @@ -49,8 +49,5 @@ config ACPI_SCI_IRQ help Set SCI IRQ to 9. -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/amd/cimx/sb900/bootblock.c" endif #SOUTHBRIDGE_AMD_CIMX_SB900 diff --git a/src/southbridge/amd/sb600/Kconfig b/src/southbridge/amd/sb600/Kconfig index 8ec3967..d440212 100644 --- a/src/southbridge/amd/sb600/Kconfig +++ b/src/southbridge/amd/sb600/Kconfig @@ -24,9 +24,6 @@ config SOUTHBRIDGE_AMD_SB600 select HAVE_HARD_RESET if SOUTHBRIDGE_AMD_SB600 -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/amd/sb600/bootblock.c" config EHCI_BAR hex diff --git a/src/southbridge/amd/sb700/Kconfig b/src/southbridge/amd/sb700/Kconfig index 924e2df..b4c95c9 100644 --- a/src/southbridge/amd/sb700/Kconfig +++ b/src/southbridge/amd/sb700/Kconfig @@ -33,10 +33,6 @@ config SOUTHBRIDGE_AMD_SUBTYPE_SP5100 bool default n -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/amd/sb700/bootblock.c" - config SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT bool default n diff --git a/src/southbridge/amd/sb800/Kconfig b/src/southbridge/amd/sb800/Kconfig index 592f9a7..5490c56 100644 --- a/src/southbridge/amd/sb800/Kconfig +++ b/src/southbridge/amd/sb800/Kconfig @@ -23,11 +23,6 @@ config SOUTHBRIDGE_AMD_SB800 select HAVE_USBDEBUG select HAVE_HARD_RESET -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/amd/sb800/bootblock.c" - depends on SOUTHBRIDGE_AMD_SB800 - config SOUTHBRIDGE_AMD_SB800_SKIP_ISA_DMA_INIT bool default n diff --git a/src/southbridge/broadcom/bcm5785/Kconfig b/src/southbridge/broadcom/bcm5785/Kconfig index d72afd8..286c19b 100644 --- a/src/southbridge/broadcom/bcm5785/Kconfig +++ b/src/southbridge/broadcom/bcm5785/Kconfig @@ -2,7 +2,3 @@ config SOUTHBRIDGE_BROADCOM_BCM5785 bool select HAVE_HARD_RESET -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/broadcom/bcm5785/bootblock.c" - depends on SOUTHBRIDGE_BROADCOM_BCM5785 diff --git a/src/southbridge/intel/i82371eb/Kconfig b/src/southbridge/intel/i82371eb/Kconfig index 7e5109a..a5c5eb8 100644 --- a/src/southbridge/intel/i82371eb/Kconfig +++ b/src/southbridge/intel/i82371eb/Kconfig @@ -2,8 +2,3 @@ config SOUTHBRIDGE_INTEL_I82371EB bool select HAVE_ACPI_RESUME if HAVE_ACPI_TABLES -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/intel/i82371eb/bootblock.c" - depends on SOUTHBRIDGE_INTEL_I82371EB - diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig index 3550954..a50e0b1 100644 --- a/src/southbridge/intel/i82801gx/Kconfig +++ b/src/southbridge/intel/i82801gx/Kconfig @@ -38,10 +38,5 @@ config USBDEBUG_DEFAULT_PORT int default 1 -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/intel/i82801gx/bootblock.c" - depends on SOUTHBRIDGE_INTEL_I82801GX - endif diff --git a/src/southbridge/nvidia/ck804/Kconfig b/src/southbridge/nvidia/ck804/Kconfig index 97927d7..4405ad8 100644 --- a/src/southbridge/nvidia/ck804/Kconfig +++ b/src/southbridge/nvidia/ck804/Kconfig @@ -6,10 +6,6 @@ config SOUTHBRIDGE_NVIDIA_CK804 if SOUTHBRIDGE_NVIDIA_CK804 -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/nvidia/ck804/bootblock.c" - config EHCI_BAR hex default 0xfef00000 diff --git a/src/southbridge/nvidia/mcp55/Kconfig b/src/southbridge/nvidia/mcp55/Kconfig index cd6009d..2c29267 100644 --- a/src/southbridge/nvidia/mcp55/Kconfig +++ b/src/southbridge/nvidia/mcp55/Kconfig @@ -6,10 +6,6 @@ config SOUTHBRIDGE_NVIDIA_MCP55 if SOUTHBRIDGE_NVIDIA_MCP55 -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/nvidia/mcp55/bootblock.c" - config EHCI_BAR hex default 0xfef00000 diff --git a/src/southbridge/sis/sis966/Kconfig b/src/southbridge/sis/sis966/Kconfig index 03dd6b1..4ae16c6 100644 --- a/src/southbridge/sis/sis966/Kconfig +++ b/src/southbridge/sis/sis966/Kconfig @@ -4,10 +4,6 @@ config SOUTHBRIDGE_SIS_SIS966 select HAVE_USBDEBUG select HAVE_HARD_RESET -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/sis/sis966/bootblock.c" if SOUTHBRIDGE_SIS_SIS966 - config EHCI_BAR hex default 0xfef00000 if SOUTHBRIDGE_SIS_SIS966 diff --git a/src/southbridge/via/vt8237r/Kconfig b/src/southbridge/via/vt8237r/Kconfig index d0a6deb..9aa1b97 100644 --- a/src/southbridge/via/vt8237r/Kconfig +++ b/src/southbridge/via/vt8237r/Kconfig @@ -27,7 +27,3 @@ config EPIA_VT8237R_INIT default n depends on SOUTHBRIDGE_VIA_VT8237R -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/via/vt8237r/bootblock.c" - depends on SOUTHBRIDGE_VIA_VT8237R

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Trac reminder: list of new ticket(s)
by coreboot tracker 19 Mar '12

19 Mar '12

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Re: [coreboot] [RFC] Improve very early boot
by Kyösti Mälkki 19 Mar '12

19 Mar '12

On Sun, 2012-03-18 at 15:41 -0400, ron minnich wrote: > My only concern about this sort of change is that it adds in more > makefile magic, and I find that over time it confuses people. The > explicit reference to a file in a kconfig is arguably ugly, but I > worry a lot about things that hide what is going on. Ron, I switched cc back to list. I don't consider this as hiding any more than the ordinary source file inclusions with Makefile classes like ramstage-y+= etc. I would have used that method for bootblock too, but this needs to compile with ROMCC and the parent-first order of devicetree.cb is just right. One trouble is people abuse the freedom of Kconfig. You may notice in this patch the HP board; it overrides the southbridge init code with a super-io init code placed in the mainboard directory. Considering the original purpose of having southbridge code in bootblock (to access all of flash, not just the typical top 64/128 kB), I am left with suspicion if the HP even boots with tiny bootblock. Thanks, KM

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Re: [coreboot] Coreboot overwrites seabios .config at build time
by HighlyCaffeinated 18 Mar '12

18 Mar '12

>On 3/18/12, Patrick Georgi <patrick(a)georgi-clan.de> wrote: >> Am 18.03.2012 06:45, schrieb HighlyCaffeinated: >>> If any options are changed in Seabios - either via direct editing of >>> the .config file or by 'make menuconfig' in the build/seabios >>> directory, those changes are overwritten by coreboot during before >>> it begins the seabios build. How can this behavior be stopped such >>> that seabios configuration is possible? >> >> By not using the integrated seabios payload option, but the generic >> "ELF" option, using a separate seabios tree. >> >> >> Patrick >> >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> http://www.coreboot.org/mailman/listinfo/coreboot >> > >----- Original Message ----- >From: Darmawan Salihun <darmawan.salihun(a)gmail.com> >Subject: Re: [coreboot] Coreboot overwrites seabios .config at build time > >This might help: >http://bioshacking.blogspot.com/2011/10/pci-option-rom-debugging-with-seabi… > > >-- >-------------------------------------------------------------------- >-= Human knowledge belongs to the world =- > >-- >coreboot mailing list: coreboot(a)coreboot.org >http://www.coreboot.org/mailman/listinfo/coreboot > > That worked brilliantly. Thank you! -Todd

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CN700 raminit problem
by Christian 18 Mar '12

18 Mar '12

Hello, If I try to set DRAM Frequency greater than 100MHz in the set_register function in raminit.c for CN700, coreboot fails later in sdram_enable function. I have tried several settings and the machine stops between sdram_enable 1-3 Unfortanetly I can't find a datasheet for CN700. Is there any chance to change raminit.c in a way cx700 do the register settings. If yes, I will try it. Thanks for tips chris

1 0

Coreboot overwrites seabios .config at build time
by HighlyCaffeinated 18 Mar '12

18 Mar '12

If any options are changed in Seabios - either via direct editing of the .config file or by 'make menuconfig' in the build/seabios directory, those changes are overwritten by coreboot during before it begins the seabios build. How can this behavior be stopped such that seabios configuration is possible? Thanks, Todd

3 2

Re: [coreboot] BIOS Disassembly Ninjutsu PDF (part of giving back to the community)
by Guillaume Knispel 17 Mar '12

17 Mar '12

On Sat, 17 Mar 2012 23:36:08 +0700 Darmawan Salihun <darmawan.salihun(a)gmail.com> wrote: > I'm sorry if this is not really related to Coreboot. > I have yet to make active contribution to the project. > I have released the PDF version of my BIOS Disassembly Ninjutsu book. > Direct link: hxxp://www.4shared.com/office/k6ooEak2/BIOS_Disassembly_Ninjutsu_Unco.html > > two errata have been found so far: > hxxp://bioshacking.blogspot.com/2012/02/bios-disassembly-ninjutsu-uncovered… > > The development of the book back then was possible one way or another > due to flashrom and of course LinuxBIOS/Coreboot. So, this is one of my way to > give back. Feel free to host the book if you want. > > Anyway, I was looking for feedback actually because > I'm not as knowledgeable as you guys here. Great book which covers a lot! Thanks very much! -- Guillaume Knispel

1 0

BIOS Disassembly Ninjutsu PDF (part of giving back to the community)
by Darmawan Salihun 17 Mar '12

17 Mar '12

I'm sorry if this is not really related to Coreboot. I have yet to make active contribution to the project. I have released the PDF version of my BIOS Disassembly Ninjutsu book. Direct link: hxxp://www.4shared.com/office/k6ooEak2/BIOS_Disassembly_Ninjutsu_Unco.html two errata have been found so far: hxxp://bioshacking.blogspot.com/2012/02/bios-disassembly-ninjutsu-uncovered… The development of the book back then was possible one way or another due to flashrom and of course LinuxBIOS/Coreboot. So, this is one of my way to give back. Feel free to host the book if you want. Anyway, I was looking for feedback actually because I'm not as knowledgeable as you guys here. Kind Regards, Darmawan -- -------------------------------------------------------------------- -= Human knowledge belongs to the world =-

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coreboot March 2012