Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/797
-gerrit
commit 3337c803ce0e58b39ace923f8f92a54c9b84ba20
Author: Patrick Georgi <patrick(a)georgi-clan.de>
Date: Fri Mar 16 21:16:55 2012 +0100
ROMCC boards have no XIP limit
So set their XIP configuration to ROM_SIZE.
Change-Id: I6c1abccec3b1d7389c85df55343ff0fc68a61eec
Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de>
---
src/cpu/x86/Kconfig | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig
index 348f0ef..d2809f8 100644
--- a/src/cpu/x86/Kconfig
+++ b/src/cpu/x86/Kconfig
@@ -29,6 +29,7 @@ config TSC_CALIBRATE_WITH_IO
config XIP_ROM_SIZE
hex
+ default ROM_SIZE if ROMCC
default 0x10000
config CPU_ADDR_BITS
the following patch was just integrated into master:
commit cd48a8a2c968c711cc2aa61bc551f791c8e0d786
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Fri Feb 24 16:08:18 2012 +0200
Intel northbridge I945: Apply un-written naming rules
Use NORTHBRIDGE_INTEL_I945 to select the driver directory for build.
Use _SUBTYPE_945GC and _SUBTYPE_945GM to define at compile-time
which model of I945 the driver is built for.
Change-Id: I11b1e0998d0fc28f8946bad4f0989036a9b18af4
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Fri Mar 16 21:40:19 2012, giving +2
See http://review.coreboot.org/684 for details.
-gerrit
the following patch was just integrated into master:
commit 566d79fe66408df5df4bf27bac89480a5b25b90a
Author: Patrick Georgi <patrick(a)georgi-clan.de>
Date: Fri Mar 16 19:28:15 2012 +0100
Via Epia-N and C3: Set ioapic delivery type in Kconfig
The original comment says it's a Via C3 and not Epia requirement
to deliver IOAPIC interrupts on APIC serial bus.
Change-Id: I73c55755e0ec1ac5756b4ee7ccdfc8eb93184e4f
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de>
Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Fri Mar 16 20:39:36 2012, giving +2
See http://review.coreboot.org/435 for details.
-gerrit
the following patch was just integrated into master:
commit 03df38b15cd14ba6d08a206918416ca6be01bb06
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Sat Feb 25 17:14:20 2012 +0200
VIA southbridge K8T890: Apply un-written naming rules
Use separate Kconfig option to select a driver directory for
build and the specific type of southbridge to support.
Change-Id: I9482d4ea0f0234b9b7ff38144e45022ab95cf3f3
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Fri Mar 16 19:45:12 2012, giving +2
See http://review.coreboot.org/685 for details.
-gerrit
the following patch was just integrated into master:
commit a07402308b2c0060a15b4d97cdcbe0370ef3af41
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Mon Mar 5 09:25:12 2012 +0200
Fix address of IDT in real-mode entry
In a case of CS & 0x0fff != 0x0, lidt memory operand does not point
to nullidt, this can raise an exception and shutdown the CPU.
When an AP CPU receives 8-bit Start-Up IPI vector yzH, it starts
execute at physical address 000yz000H. Seems this translates to
either yz00:0000 or y000:z000 (CS:IP), depending of the CPU model.
With the change entry16.inc is relocatable as the commentary suggests
and can be used as ap_sipi_vector on SMP systems.
Change-Id: I885a2888179700ba6e2b11d4f2d6a64ddea4c2dc
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Fri Mar 16 19:32:41 2012, giving +2
See http://review.coreboot.org/707 for details.
-gerrit
the following patch was just integrated into master:
commit 2ce20b6a8ee97d62013a5c7bde3f237ef3614343
Author: Marc Jones <marc.jones(a)se-eng.com>
Date: Thu Mar 15 13:21:41 2012 -0600
Fix AMD Fam14 cbmen allocation
The Fam14 northbridge.c had hardcoded the cbmem size. It should use
in cbmem.h instead.
Change-Id: I910329fc98a4cf04dc81ef66f3aa05a1916f5b1d
Signed-off-by: Marc Jones <marc.jones(a)se-eng.com>
Build-Tested: build bot (Jenkins) at Fri Mar 16 19:26:45 2012, giving +1
Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Fri Mar 16 18:33:52 2012, giving +2
See http://review.coreboot.org/790 for details.
-gerrit
Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/435
-gerrit
commit 566d79fe66408df5df4bf27bac89480a5b25b90a
Author: Patrick Georgi <patrick(a)georgi-clan.de>
Date: Fri Mar 16 19:28:15 2012 +0100
Via Epia-N and C3: Set ioapic delivery type in Kconfig
The original comment says it's a Via C3 and not Epia requirement
to deliver IOAPIC interrupts on APIC serial bus.
Change-Id: I73c55755e0ec1ac5756b4ee7ccdfc8eb93184e4f
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de>
---
src/arch/x86/Kconfig | 8 ++++++++
src/arch/x86/lib/ioapic.c | 12 ++----------
src/cpu/via/c3/Kconfig | 1 +
3 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig
index e71d0f3..c5a0c0e 100644
--- a/src/arch/x86/Kconfig
+++ b/src/arch/x86/Kconfig
@@ -88,4 +88,12 @@ config LITTLE_ENDIAN
bool
default !BIG_ENDIAN
+config IOAPIC_INTERRUPTS_ON_FSB
+ bool
+ default y if !IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS
+
+config IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS
+ bool
+ default n
+
endmenu
diff --git a/src/arch/x86/lib/ioapic.c b/src/arch/x86/lib/ioapic.c
index 81d964c..e974d7c 100644
--- a/src/arch/x86/lib/ioapic.c
+++ b/src/arch/x86/lib/ioapic.c
@@ -89,15 +89,7 @@ void setup_ioapic(u32 ioapic_base, u8 ioapic_id)
ioapic_interrupts = 24;
printk(BIOS_DEBUG, "IOAPIC: %d interrupts\n", ioapic_interrupts);
-// XXX this decision should probably be made elsewhere, and
-// it's the C3, not the EPIA this depends on.
-#if CONFIG_EPIA_VT8237R_INIT
-#define IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS
-#else
-#define IOAPIC_INTERRUPTS_ON_FSB
-#endif
-
-#ifdef IOAPIC_INTERRUPTS_ON_FSB
+#ifdef CONFIG_IOAPIC_INTERRUPTS_ON_FSB
/*
* For the Pentium 4 and above APICs deliver their interrupts
* on the front side bus, enable that.
@@ -106,7 +98,7 @@ void setup_ioapic(u32 ioapic_base, u8 ioapic_id)
io_apic_write(ioapic_base, 0x03,
io_apic_read(ioapic_base, 0x03) | (1 << 0));
#endif
-#ifdef IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS
+#ifdef CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS
printk(BIOS_DEBUG, "IOAPIC: Enabling interrupts on APIC serial bus\n");
io_apic_write(ioapic_base, 0x03, 0);
#endif
diff --git a/src/cpu/via/c3/Kconfig b/src/cpu/via/c3/Kconfig
index a5b4f22..259a1f2 100644
--- a/src/cpu/via/c3/Kconfig
+++ b/src/cpu/via/c3/Kconfig
@@ -7,5 +7,6 @@ config CPU_SPECIFIC_OPTIONS
def_bool y
select UDELAY_TSC
select MMX
+ select IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS
endif # CPU_VIA_C3