coreboot March 2012

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Patch merged into coreboot/master: a47f09d AGESA family 12 changes to fix torpedo warnings
by gerrit＠coreboot.org 13 Mar '12

13 Mar '12

the following patch was just integrated into master: commit a47f09d8e723896eb63ae8437250c0ee7ce68da9 Author: Martin Roth <martin(a)se-eng.com> Date: Fri Feb 17 13:16:04 2012 -0700 AGESA family 12 changes to fix torpedo warnings Fixes the warnings generated in the torpedo mainboard build by AGESA. Removing broken tests. Change-Id: Ib444fa2bf4dd94cadb4ce33040eb5650d1c0325b Signed-off-by: Martin L Roth <martin(a)se-eng.com> Build-Tested: build bot (Jenkins) at Fri Feb 17 22:50:04 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Wed Feb 29 23:32:35 2012, giving +2 See http://review.coreboot.org/667 for details. -gerrit

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Re: [coreboot] Gsoc 12
by Marc Jones 13 Mar '12

13 Mar '12

Hi Jaspal, Welcome to coreboot. On Fri, Mar 9, 2012 at 11:54 AM, Jaspal Dhillon <jaspal.iiith(a)gmail.com> wrote: > Hello , > > I am currently a 4th year student ( B.Tech in CSE + MS ) in IIIT-H and > chosen field of study for MS is Virtualization. I have been using kvm , qemu > and the libvirt library primarily to experiment with cloud frameworks and > migration until now. > > I was going through the coreboot.org and I am definitely interested in it. > So wanted to ask couple of things. > I have not read the source code yet but tried it out in this way : > 1.Checked out latest version of coreboot on 32bit Fedora 15. make config > with settings as : > MainBoard Vendor : Emulation , Model : Qemu , ROM Size : 256KB , Payload : > SeaBIOS > make was successful . > Since my laptop is an old one and does not have hardware virtualization > support , I use a lab pc ( 64 bit Fedora 15 ) for some of my experiments. > > scp coreboot.rom root@Lab: ; ssh root@Lab > 2.qemu-img create disk.img 2500M > 3.mkfs.ext2 disk.img > 4.mkdir foo ; mv coreboot.rom foo/ ; cd foo ; ln -s coreboot.rom bios.bin > 5.Copy some of the other bios files needed by Qemu ( otherwise , Qemu throws > a file not found error and exits ): > cp -r > qemu_path/pc-bios/{keymaps,kvmapic.bin,pxe-e1000.rom,vgabios-cirrus.bin} > /root/foo/ > 6.qemu-system-x86_64 -L foo/ -hda disk.img -vnc 0:0 -m 512 -serial stdio > -cdrom ~/CentOS-5.5-i386-bin-DVD.iso > > Installation of CentOS ( Minimum installation ) was successful and at the > end , it asked me to reboot. When I clicked on reboot option , coreboot got > stuck in an infinite loop and I was getting this (in a loop) on the stdio : > > Changing serial settings was 0/0 now 3/0 > In resume (status=0) > In 32bit resume > Attempting a hard reboot > > I killed the process and started my vm again without the -cdrom option and > it booted up fine. > I am not sure if this is a bug or if I am doing something wrong. Can you > shed light on it ? I am not sure why the -cdrom issue is needed. it may be a seabios or qemu issue. > I have pasted the serial output at the end of email. ( There are some other > 'file not found' errors but qemu + coreboot worked fine without them ). > > I am absolutely new to coreboot and used it for the first time today but I > love and admire it's goal , to replace the proprietary BIOS. Always thought > , where's the code of BIOS ? > Could you give me some pointers as to where to begin for GSoC or some little > hacks that I should attempt out ? I am trying different payloads in the > meantime. > The initrd and vmlinuz of the CentOS I just installed have sizes of 3.2MB > and 1.8MB respectively. If I want to use them ( a kernel payload ) , how > should I ? I read about mkelfImage command and also tried it out but the > resultant size of linux.elf is ~5MB which exceeds the size of ROM chip , > declared in Qemu. Can I use a kernel payload ( any other OS ) without > hacking Qemu ? ( I think not but want to know , if yes , how ) . It sounds like you did this correctly and that the .elf is the correct size. You will need to increase the rom size in qemu. I'm not sure how it is done. Maybe someone else can answer? > > > Thanks , > Jaspal > Please join the #coreboot IRC channel. Then we can try to help you as you are working on these problems. Regards, Marc > The complete serial log : > > [root@divecloud2 jaspal]# qemu-system-x86_64 -L foo/ -hda disk.img -m 512 > -serial stdio -vnc 0:0 -cdrom ~/CentOS-5.5-i386-bin-DVD.iso > Could not open option rom 'vapic.bin': No such file or directory > qemu-system-x86_64: pci_add_option_rom: failed to find romfile > "pxe-rtl8139.rom" > > > coreboot-4.0-2087-gc5fc7db Fri Mar 9 04:04:49 IST 2012 starting... > Loading image. > Searching for fallback/coreboot_ram > Check cmos_layout.bin > Check fallback/romstage > Check fallback/coreboot_ram > Stage: loading fallback/coreboot_ram @ 0x100000 (147456 bytes), entry @ > 0x100000 > Stage: done loading. > Jumping to image. > coreboot-4.0-2087-gc5fc7db Fri Mar 9 04:04:49 IST 2012 booting... > Enumerating buses... > Show all devs...Before device enumeration. > Root Device: enabled 1 > PCI_DOMAIN: 0000: enabled 1 > PCI: 00:00.0: enabled 1 > PCI: 00:01.0: enabled 1 > PCI: 00:01.1: enabled 1 > Compare with tree... > Root Device: enabled 1 > PCI_DOMAIN: 0000: enabled 1 > PCI: 00:00.0: enabled 1 > PCI: 00:01.0: enabled 1 > PCI: 00:01.1: enabled 1 > scan_static_bus for Root Device > Finding PCI configuration type. > PCI: Using configuration type 1 > PCI_DOMAIN: 0000 enabled > PCI_DOMAIN: 0000 scanning... > PCI: pci_scan_bus for bus 00 > PCI: 00:00.0 [8086/1237] ops > PCI: 00:00.0 [8086/1237] enabled > PCI: 00:01.0 [8086/7000] bus ops > PCI: 00:01.0 [8086/7000] enabled > PCI: 00:01.1 [8086/7010] ops > PCI: 00:01.1 [8086/7010] enabled > PCI: 00:01.3 [8086/7113] bus ops > pwrmgt_enable: gpo default missing in devicetree.cb! > PCI: 00:01.3 [8086/7113] enabled > PCI: 00:02.0 [1013/00b8] ops > PCI: 00:02.0 [1013/00b8] enabled > PCI: 00:03.0 [10ec/8139] enabled > scan_static_bus for PCI: 00:01.0 > scan_static_bus for PCI: 00:01.0 done > scan_static_bus for PCI: 00:01.3 > scan_static_bus for PCI: 00:01.3 done > PCI: pci_scan_bus returning with max=000 > scan_static_bus for Root Device done > done > Setting up VGA for PCI: 00:02.0 > Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000 > Setting PCI_BRIDGE_CTL_VGA for bridge Root Device > Allocating resources... > Reading resources... > Root Device read_resources bus 0 link: 0 > PCI_DOMAIN: 0000 read_resources bus 0 link: 0 > PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done > Root Device read_resources bus 0 link: 0 done > Done reading resources. > Show resources in subtree (Root Device)...After reading. > Root Device child on link 0 PCI_DOMAIN: 0000 > PCI_DOMAIN: 0000 child on link 0 PCI: 00:00.0 > PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags > 40040100 index 10000000 > PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff > flags 40040200 index 10000100 > PCI_DOMAIN: 0000 resource base fec00000 size 100000 align 0 gran 0 limit > ffffffff flags e0000200 index 2 > PCI_DOMAIN: 0000 resource base fee00000 size 10000 align 0 gran 0 limit > ffffffff flags e0000200 index 3 > PCI: 00:00.0 > PCI: 00:01.0 > PCI: 00:01.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags > c0000100 index 1 > PCI: 00:01.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 > flags d0000200 index 2 > PCI: 00:01.1 > PCI: 00:01.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 > index 20 > PCI: 00:01.3 > PCI: 00:01.3 resource base e400 size 40 align 0 gran 0 limit ffff flags > d0000100 index 1 > PCI: 00:01.3 resource base f00 size 10 align 0 gran 0 limit ffff flags > d0000100 index 2 > PCI: 00:02.0 > PCI: 00:02.0 resource base 0 size 2000000 align 25 gran 25 limit ffffffff > flags 1200 index 10 > PCI: 00:02.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff > flags 200 index 14 > PCI: 00:02.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff > flags 2200 index 30 > PCI: 00:03.0 > PCI: 00:03.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 > index 10 > PCI: 00:03.0 resource base 0 size 100 align 8 gran 8 limit ffffffff flags > 200 index 14 > PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 > limit: ffff > PCI: 00:03.0 10 * [0x0 - 0xff] io > PCI: 00:01.1 20 * [0x400 - 0x40f] io > PCI_DOMAIN: 0000 compute_resources_io: base: 410 size: 410 align: 8 gran: 0 > limit: ffff done > PCI_DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 > limit: ffffffff > PCI: 00:02.0 10 * [0x0 - 0x1ffffff] prefmem > PCI: 00:02.0 30 * [0x2000000 - 0x200ffff] mem > PCI: 00:02.0 14 * [0x2010000 - 0x2010fff] mem > PCI: 00:03.0 14 * [0x2011000 - 0x20110ff] mem > PCI_DOMAIN: 0000 compute_resources_mem: base: 2011100 size: 2011100 align: > 25 gran: 0 limit: ffffffff done > avoid_fixed_resources: PCI_DOMAIN: 0000 > avoid_fixed_resources:@PCI_DOMAIN: 0000 10000000 limit 0000ffff > avoid_fixed_resources:@PCI_DOMAIN: 0000 10000100 limit ffffffff > constrain_resources: PCI_DOMAIN: 0000 > constrain_resources: PCI: 00:00.0 > constrain_resources: PCI: 00:01.0 > constrain_resources: PCI: 00:01.1 > constrain_resources: PCI: 00:01.3 > constrain_resources: PCI: 00:02.0 > constrain_resources: PCI: 00:03.0 > avoid_fixed_resources2: PCI_DOMAIN: 0000@10000000 limit 0000ffff > lim->base 00001000 lim->limit 0000e3ff > avoid_fixed_resources2: PCI_DOMAIN: 0000@10000100 limit ffffffff > lim->base 00000000 lim->limit febfffff > Setting resources... > PCI_DOMAIN: 0000 allocate_resources_io: base:1000 size:410 align:8 gran:0 > limit:e3ff > Assigned: PCI: 00:03.0 10 * [0x1000 - 0x10ff] io > Assigned: PCI: 00:01.1 20 * [0x1400 - 0x140f] io > PCI_DOMAIN: 0000 allocate_resources_io: next_base: 1410 size: 410 align: 8 > gran: 0 done > PCI_DOMAIN: 0000 allocate_resources_mem: base:fc000000 size:2011100 align:25 > gran:0 limit:febfffff > Assigned: PCI: 00:02.0 10 * [0xfc000000 - 0xfdffffff] prefmem > Assigned: PCI: 00:02.0 30 * [0xfe000000 - 0xfe00ffff] mem > Assigned: PCI: 00:02.0 14 * [0xfe010000 - 0xfe010fff] mem > Assigned: PCI: 00:03.0 14 * [0xfe011000 - 0xfe0110ff] mem > PCI_DOMAIN: 0000 allocate_resources_mem: next_base: fe011100 size: 2011100 > align: 25 gran: 0 done > Root Device assign_resources, bus 0 link: 0 > Detected 524288 Kbytes (512 MiB) RAM. > PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 > PCI: 00:01.1 20 <- [0x0000001400 - 0x000000140f] size 0x00000010 gran 0x04 > io > PCI: 00:02.0 10 <- [0x00fc000000 - 0x00fdffffff] size 0x02000000 gran 0x19 > prefmem > PCI: 00:02.0 14 <- [0x00fe010000 - 0x00fe010fff] size 0x00001000 gran 0x0c > mem > PCI: 00:02.0 30 <- [0x00fe000000 - 0x00fe00ffff] size 0x00010000 gran 0x10 > romem > PCI: 00:03.0 10 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 > io > PCI: 00:03.0 14 <- [0x00fe011000 - 0x00fe0110ff] size 0x00000100 gran 0x08 > mem > PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 > Root Device assign_resources, bus 0 link: 0 > Done setting resources. > Show resources in subtree (Root Device)...After assigning values. > Root Device child on link 0 PCI_DOMAIN: 0000 > PCI_DOMAIN: 0000 child on link 0 PCI: 00:00.0 > PCI_DOMAIN: 0000 resource base 1000 size 410 align 8 gran 0 limit e3ff > flags 40040100 index 10000000 > PCI_DOMAIN: 0000 resource base fc000000 size 2011100 align 25 gran 0 limit > febfffff flags 40040200 index 10000100 > PCI_DOMAIN: 0000 resource base fec00000 size 100000 align 0 gran 0 limit > ffffffff flags e0000200 index 2 > PCI_DOMAIN: 0000 resource base fee00000 size 10000 align 0 gran 0 limit > ffffffff flags e0000200 index 3 > PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags > e0004200 index a > PCI_DOMAIN: 0000 resource base c0000 size 1ff40000 align 0 gran 0 limit 0 > flags e0004200 index b > PCI: 00:00.0 > PCI: 00:01.0 > PCI: 00:01.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags > c0000100 index 1 > PCI: 00:01.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 > flags d0000200 index 2 > PCI: 00:01.1 > PCI: 00:01.1 resource base 1400 size 10 align 4 gran 4 limit e3ff flags > 60000100 index 20 > PCI: 00:01.3 > PCI: 00:01.3 resource base e400 size 40 align 0 gran 0 limit ffff flags > d0000100 index 1 > PCI: 00:01.3 resource base f00 size 10 align 0 gran 0 limit ffff flags > d0000100 index 2 > PCI: 00:02.0 > PCI: 00:02.0 resource base fc000000 size 2000000 align 25 gran 25 limit > febfffff flags 60001200 index 10 > PCI: 00:02.0 resource base fe010000 size 1000 align 12 gran 12 limit > febfffff flags 60000200 index 14 > PCI: 00:02.0 resource base fe000000 size 10000 align 16 gran 16 limit > febfffff flags 60002200 index 30 > PCI: 00:03.0 > PCI: 00:03.0 resource base 1000 size 100 align 8 gran 8 limit e3ff flags > 60000100 index 10 > PCI: 00:03.0 resource base fe011000 size 100 align 8 gran 8 limit > febfffff flags 60000200 index 14 > Done allocating resources. > Enabling resources... > PCI: 00:00.0 cmd <- 00 > PCI: 00:01.0 cmd <- 00 > PCI: 00:01.1 cmd <- 01 > PCI: 00:01.3 cmd <- 00 > PCI: 00:02.0 cmd <- 03 > PCI: 00:03.0 cmd <- 03 > done. > Initializing devices... > Root Device init > PCI: 00:00.0 init > Keyboard init... > setting ethernet > Assigning IRQ 11 to 0:3.0 > i8259_configure_irq_trigger: current interrupts are 0x0 > i8259_configure_irq_trigger: try to set interrupts 0x800 > PCI: 00:01.0 init > RTC Init > PCI: 00:01.1 init > IDE: Primary IDE interface: on > IDE: Secondary IDE interface: on > IDE: Access to legacy IDE ports: off > PCI: 00:02.0 init > Searching for pci1013,00b8.rom > Check cmos_layout.bin > Check fallback/romstage > Check fallback/coreboot_ram > Check fallback/payload > Check config > Check > Could not find file 'pci1013,00b8.rom'. > On card, ROM address for PCI: 00:02.0 = fe000000 > PCI expansion ROM, signature 0xaa55, INIT size 0x8c00, data ptr 0x0038 > PCI ROM image, vendor ID 1013, device ID 00b8, > PCI ROM image, Class Code 030000, Code Type 00 > Copying VGA ROM Image from fe000000 to 0xc0000, 0x8c00 bytes > Real mode stub @00000600: 862 bytes > Calling Option ROM... > ... Option ROM returned. > PCI: 00:03.0 init > Searching for pci10ec,8139.rom > Check cmos_layout.bin > Check fallback/romstage > Check fallback/coreboot_ram > Check fallback/payload > Check config > Check > Could not find file 'pci10ec,8139.rom'. > Devices initialized > Show all devs...After init. > Root Device: enabled 1 > PCI_DOMAIN: 0000: enabled 1 > PCI: 00:00.0: enabled 1 > PCI: 00:01.0: enabled 1 > PCI: 00:01.1: enabled 1 > PCI: 00:01.3: enabled 1 > PCI: 00:02.0: enabled 1 > PCI: 00:03.0: enabled 1 > Initializing CBMEM area to 0x1fff0000 (65536 bytes) > Adding CBMEM entry as no. 1 > Moving GDT to 1fff0200...ok > High Tables Base is 1fff0000. > Copying Interrupt Routing Table to 0x000f0000... done. > Adding CBMEM entry as no. 2 > Copying Interrupt Routing Table to 0x1fff0400... done. > PIRQ table: 128 bytes. > Adding CBMEM entry as no. 3 > smbios_write_tables: 1fff1400 > Root Device (QEMU Mainboard) > PCI_DOMAIN: 0000 (QEMU Northbridge) > PCI: 00:00.0 (QEMU Northbridge) > PCI: 00:01.0 (Intel 82371FB/SB/MX/AB/EB/MB Southbridge) > PCI: 00:01.1 (Intel 82371FB/SB/MX/AB/EB/MB Southbridge) > PCI: 00:01.3 () > PCI: 00:02.0 () > PCI: 00:03.0 () > SMBIOS tables: 357 bytes. > Adding CBMEM entry as no. 4 > Writing high table forward entry at 0x00000500 > Wrote coreboot table at: 00000500 - 00000518 checksum c3df > New low_table_end: 0x00000518 > Now going to write high coreboot table at 0x1fff1c00 > rom_table_end = 0x1fff1c00 > Adjust low_table_end from 0x00000518 to 0x00001000 > Adjust rom_table_end from 0x1fff1c00 to 0x20000000 > Adding high table area > coreboot memory table: > 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES > 1. 0000000000001000-000000000009ffff: RAM > 2. 00000000000c0000-000000001ffeffff: RAM > 3. 000000001fff0000-000000001fffffff: CONFIGURATION TABLES > 4. 00000000ff800000-00000000ffffffff: RESERVED > Wrote coreboot table at: 1fff1c00 - 1fff1dd0 checksum fe3d > coreboot table: 464 bytes. > Multiboot Information structure has been written. > 0. FREE SPACE 1fff3c00 0000c400 > 1. GDT 1fff0200 00000200 > 2. IRQ TABLE 1fff0400 00001000 > 3. SMBIOS 1fff1400 00000800 > 4. COREBOOT 1fff1c00 00002000 > Searching for fallback/payload > Check cmos_layout.bin > Check fallback/romstage > Check fallback/coreboot_ram > Check fallback/payload > Got a payload > Loading segment from rom address 0xfffc99b8 > code (compression=1) > New segment dstaddr 0xe7e04 memsize 0x181fc srcaddr 0xfffc99f0 filesize > 0xc21c > (cleaned up) New segment addr 0xe7e04 size 0x181fc offset 0xfffc99f0 > filesize 0xc21c > Loading segment from rom address 0xfffc99d4 > Entry Point 0x00000000 > Loading Segment: addr: 0x00000000000e7e04 memsz: 0x00000000000181fc filesz: > 0x000000000000c21c > lb: [0x0000000000100000, 0x0000000000124000) > Post relocation: addr: 0x00000000000e7e04 memsz: 0x00000000000181fc filesz: > 0x000000000000c21c > using LZMA > [ 0x000e7e04, 00100000, 0x00100000) <- fffc99f0 > dest 000e7e04, end 00100000, bouncebuffer 1ffa8000 > Loaded segments > Jumping to boot code at fc8b9 > entry = 0x000fc8b9 > lb_start = 0x00100000 > lb_size = 0x00024000 > adjust = 0x1fecc000 > buffer = 0x1ffa8000 > elf_boot_notes = 0x00110538 > adjusted_boot_notes = 0x1ffdc538 > Start bios (version 1.6.3-20120309_040510-redevil) > Found mainboard Emulation QEMU x86 > Found CBFS header at 0xfffffc90 > Ram Size=0x1fff0000 (0x0000000000000000 high) > Relocating init from 0x000e8450 to 0x1ffd57a0 (size 42812) > CPU Mhz=2936 > Found 6 PCI devices (max PCI bus is 00) > Found 1 cpu(s) max supported 1 cpu(s) > Copying PIR from 0x1fff0400 to 0x000fdb70 > Copying SMBIOS entry point from 0x1fff1400 to 0x000fdb50 > Scan for VGA option rom > Running option rom at c000:0003 > Turning on vga text mode console > SeaBIOS (version 1.6.3-20120309_040510-redevil) > > Found 1 lpt ports > Found 1 serial ports > ATA controller 1 at 1f0/3f4/0 (irq 14 dev 9) > ATA controller 2 at 170/374/0 (irq 15 dev 9) > ata0-0: QEMU HARDDISK ATA-7 Hard-Disk (2500 MiBytes) > Searching bootorder for: /pci@i0cf8/*@1,1/drive@0/disk@0 > DVD/CD [ata1-0: QEMU DVD-ROM ATAPI-4 DVD/CD] > Searching bootorder for: /pci@i0cf8/*@1,1/drive@1/disk@0 > PS2 keyboard initialized > All threads complete. > Scan for option roms > Press F12 for boot menu. > > drive 0x000fdb00: PCHS=5079/16/63 translation=large LCHS=634/128/63 > s=5120000 > ebda moved from 9fc00 to 9f400 > Returned 65536 bytes of ZoneHigh > e820 map has 6 items: > 0: 0000000000000000 - 000000000009f400 = 1 RAM > 1: 000000000009f400 - 00000000000a0000 = 2 RESERVED > 2: 00000000000f0000 - 0000000000100000 = 2 RESERVED > 3: 0000000000100000 - 000000001fff0000 = 1 RAM > 4: 000000001fff0000 - 0000000020000000 = 2 RESERVED > 5: 00000000ff800000 - 0000000100000000 = 2 RESERVED > enter handle_19: > NULL > Booting from DVD/CD... > 3991MB medium detected > Booting from 0000:7c00 > Changing serial settings was 0/0 now 3/0 > In resume (status=0) > In 32bit resume > Attempting a hard reboot > Changing serial settings was 0/0 now 3/0 > In resume (status=0) > In 32bit resume > Attempting a hard reboot > Changing serial settings was 0/0 now 3/0 > In resume (status=0) > In 32bit resume > Attempting a hard reboot > Changing serial settings was 0/0 now 3/0 > In resume (status=0) > In 32bit resume > Attempting a hard reboot > > > > > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot -- http://se-eng.com

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Patch merged into coreboot/master: 48bb35f Union Station: Fixes to turn on HDMI
by gerrit＠coreboot.org 13 Mar '12

13 Mar '12

the following patch was just integrated into master: commit 48bb35f2f03fe624324123eef5adfe61b996d922 Author: Frank Vibrans <frank.vibrans(a)se-eng.com> Date: Tue Mar 13 11:02:04 2012 -0600 Union Station: Fixes to turn on HDMI This commit includes the changes to enable the HDMI on Union Station. The changes switch the output from the display port to the HDMI. Change-Id: I4e15ff6db7d056f156791ff1406d4bae35ff2767 Signed-off-by: Frank Vibrans <frank.vibrans(a)se-eng.com> Build-Tested: build bot (Jenkins) at Tue Mar 13 18:37:43 2012, giving +1 Reviewed-By: Peter Stuge <peter(a)stuge.se> at Tue Mar 13 18:39:30 2012, giving +2 See http://review.coreboot.org/788 for details. -gerrit

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Patch merged into coreboot/master: e75774b Union Station: Remove SIO support
by gerrit＠coreboot.org 13 Mar '12

13 Mar '12

the following patch was just integrated into master: commit e75774b6154c1ed5d19710364c4641c41672e5e2 Author: Frank Vibrans <frank.vibrans(a)se-eng.com> Date: Tue Mar 13 10:57:49 2012 -0600 Union Station: Remove SIO support Because the Union Station platform doesn't have an SIO chip, this commit removes the Fintek SIO support. Change-Id: Idba4222ce136821dee2530a72d1630eb5ad613a2 Signed-off-by: Frank Vibrans <frank.vibrans(a)se-eng.com> Build-Tested: build bot (Jenkins) at Tue Mar 13 18:24:29 2012, giving +1 Reviewed-By: Peter Stuge <peter(a)stuge.se> at Tue Mar 13 18:02:18 2012, giving +2 See http://review.coreboot.org/787 for details. -gerrit

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New patch to review for coreboot: 48bb35f Union Station: Fixes to turn on HDMI
by Frank Vibrans III 13 Mar '12

13 Mar '12

Frank Vibrans III (frank.vibrans(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/788 -gerrit commit 48bb35f2f03fe624324123eef5adfe61b996d922 Author: Frank Vibrans <frank.vibrans(a)se-eng.com> Date: Tue Mar 13 11:02:04 2012 -0600 Union Station: Fixes to turn on HDMI This commit includes the changes to enable the HDMI on Union Station. The changes switch the output from the display port to the HDMI. Change-Id: I4e15ff6db7d056f156791ff1406d4bae35ff2767 Signed-off-by: Frank Vibrans <frank.vibrans(a)se-eng.com> --- src/mainboard/amd/union_station/PlatformGnbPcie.c | 4 ++-- src/mainboard/amd/union_station/buildOpts.c | 2 +- src/mainboard/amd/union_station/dsdt.asl | 7 ++++--- 3 files changed, 7 insertions(+), 6 deletions(-) diff --git a/src/mainboard/amd/union_station/PlatformGnbPcie.c b/src/mainboard/amd/union_station/PlatformGnbPcie.c index b0389b8..f1f06a8 100644 --- a/src/mainboard/amd/union_station/PlatformGnbPcie.c +++ b/src/mainboard/amd/union_station/PlatformGnbPcie.c @@ -95,14 +95,14 @@ PCIe_DDI_DESCRIPTOR DdiList [] = { 0, //Descriptor flags PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) - {ConnectorTypeDP, Aux1, Hdp1} + {ConnectorTypeHDMI, Aux1, Hdp1} }, // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) { DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) - {ConnectorTypeDP, Aux2, Hdp2} + {ConnectorTypeHDMI, Aux2, Hdp2} } }; diff --git a/src/mainboard/amd/union_station/buildOpts.c b/src/mainboard/amd/union_station/buildOpts.c index 20d667d..f87522c 100644 --- a/src/mainboard/amd/union_station/buildOpts.c +++ b/src/mainboard/amd/union_station/buildOpts.c @@ -176,7 +176,7 @@ //#define BLDCFG_SET_HTCRC_SYNC_FLOOD FALSE //#define BLDCFG_USE_UNIT_ID_CLUMPING FALSE //#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP 0 -#define BLDCFG_CFG_GNB_HD_AUDIO FALSE//TRUE +#define BLDCFG_CFG_GNB_HD_AUDIO TRUE //#define BLDCFG_CFG_ABM_SUPPORT FALSE //#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE 0 //#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 0 diff --git a/src/mainboard/amd/union_station/dsdt.asl b/src/mainboard/amd/union_station/dsdt.asl index 5c8b661..fb2cfe8 100644 --- a/src/mainboard/amd/union_station/dsdt.asl +++ b/src/mainboard/amd/union_station/dsdt.asl @@ -1166,13 +1166,14 @@ DefinitionBlock ( } /* end AMRT */ /* The internal GFX bridge */ - Device(AGPB) { + Device(HDMI) { Name(_ADR, 0x00010000) Name(_PRW, Package() {0x18, 4}) Method(_PRT,0) { - Return (APR1) + If(PMOD){ Return(APR1) } /* APIC mode */ + Return (PR1) /* PIC Mode */ } - } /* end AGPB */ + } /* end HDMI */ /* The external GFX bridge */ Device(PBR2) {

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New patch to review for coreboot: e75774b Union Station: Remove SIO support
by Frank Vibrans III 13 Mar '12

13 Mar '12

Frank Vibrans III (frank.vibrans(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/787 -gerrit commit e75774b6154c1ed5d19710364c4641c41672e5e2 Author: Frank Vibrans <frank.vibrans(a)se-eng.com> Date: Tue Mar 13 10:57:49 2012 -0600 Union Station: Remove SIO support Because the Union Station platform doesn't have an SIO chip, this commit removes the Fintek SIO support. Change-Id: Idba4222ce136821dee2530a72d1630eb5ad613a2 Signed-off-by: Frank Vibrans <frank.vibrans(a)se-eng.com> --- src/mainboard/amd/union_station/Kconfig | 1 - src/mainboard/amd/union_station/devicetree.cb | 24 ------------------------ src/mainboard/amd/union_station/romstage.c | 2 -- 3 files changed, 0 insertions(+), 27 deletions(-) diff --git a/src/mainboard/amd/union_station/Kconfig b/src/mainboard/amd/union_station/Kconfig index 194a39d..cc2e300 100644 --- a/src/mainboard/amd/union_station/Kconfig +++ b/src/mainboard/amd/union_station/Kconfig @@ -26,7 +26,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AGESA_FAMILY14_ROOT_COMPLEX select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 - select SUPERIO_FINTEK_F81865F select BOARD_HAS_FADT select HAVE_BUS_CONFIG select HAVE_OPTION_TABLE diff --git a/src/mainboard/amd/union_station/devicetree.cb b/src/mainboard/amd/union_station/devicetree.cb index f0b471a..857bc02 100644 --- a/src/mainboard/amd/union_station/devicetree.cb +++ b/src/mainboard/amd/union_station/devicetree.cb @@ -56,30 +56,6 @@ chip northbridge/amd/agesa/family14/root_complex device pci 14.1 on end # IDE 0x439c device pci 14.2 on end # HDA 0x4383 device pci 14.3 on # LPC 0x439d - chip superio/fintek/f81865f - device pnp 4e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 4e.3 off end # Parallel Port - device pnp 4e.4 off end # Hardware Monitor - device pnp 4e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 4e.6 off end # GPIO - device pnp 4e.a off end # PME - device pnp 4e.10 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 4e.11 off # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - end # f81865f end #LPC device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} device pci 14.5 on end # USB 2 diff --git a/src/mainboard/amd/union_station/romstage.c b/src/mainboard/amd/union_station/romstage.c index 26a05e8..f79e5ff 100644 --- a/src/mainboard/amd/union_station/romstage.c +++ b/src/mainboard/amd/union_station/romstage.c @@ -32,7 +32,6 @@ #include <console/loglevel.h> #include "agesawrapper.h" #include "cpu/x86/bist.h" -#include "superio/fintek/f81865f/f81865f_early_serial.c" #include "cpu/x86/lapic/boot_cpu.c" #include "sb_cimx.h" #include "SBPLATFORM.h" @@ -55,7 +54,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb_Poweron_Init(); post_code(0x31); - f81865f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); }

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Re: [coreboot] GSoC project ideas
by Peter Stuge 13 Mar '12

13 Mar '12

Hi Svetoslav, Svetoslav Trochev wrote: > I know the theory how those things are working, but I have zero > experience. Do you think I can be useful even if it is outside the > GSoC program? For sure you can. And right now it's still only March, so if you have spent some time on these things you may certainly be qualified to mentor a student come time for SoC. What exactly would you like to work on? //Peter

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ASRock E350M1 video option ROM?
by HighlyCaffeinated 13 Mar '12

13 Mar '12

I was wondering if anyone on the list had a copy of a functional video option ROM from the ASRock E350M1 board. As it uses an UEFI BIOS, bios_extract doesn't recognize it. I do not yet have the board in hand (still enroute) to extract it from the factory ROM in Linux, though I have read that it is possible from a previous thread. I'd much prefer starting with a known good ROM as opposed to troubleshooting my own ineptitude. I am sure I will have plenty of opportunities with that elsewhere in the process! On a side note, I was unable to entice coreboot to build in Ubuntu 11.10 due to the broken linker, but was also further unable to build with the crossgcc toolchain. I sidestepped by loading 10.10 on an unused machine (which appears to have been successful), but thought it should be mentioned. Logs available for the interested parties. Thanks, Todd

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GSoC project ideas
by Carl-Daniel Hailfinger 13 Mar '12

13 Mar '12

Hi, given the lack of affordable and available hardware tools for coreboot development, I propose to look for a different set of projects this year: Tools which would help developers, and which are usable especially with current hardware. A list of ideas follows. - Flash ICE device with SPI support. - Flash ICE device with LPC/FWH support. - Serial emulation for LPC buses on a configurable I/O port with USB output on the other side. - Dual serial emulation for two LPC buses either on the same device or with two identical devices and a fast bus in between. - Serial emulation for PCI buses (i.e. PCI/serial card). The reason for the flash ICE devices is obvious: Avoid external reflashing while you're developing. The serial emulation or similar POST code port emulation is meant to provide a serial console, a SerialICE connection and/or some POST code output channel. This is especially important for laptops where debugging can be a pain and where you usually have a LPC bus available in the MiniPCIe slot. The dual serial emulation for two LPC buses would work as a fast PC-to-PC connection for SerialICE and other purposes where you need low latency, not necessarily high throughput. The serial emulation for PCI buses would complement the serial emulation for LPC to provide an easy way to connect to a SerialICE instance on the other side. As a basis for all those ideas I'd propose the Openbench logic sniffer. It has a fast FPGA, enough gates and roughly 32 kByte RAM. The FPGA is fast enough and big enough to accommodate the necessary logic, and we could easily attach a fast (66+ MHz) SPI flash chip to it. And with $50 incl. shipping the OLS is not extremely cheap, but worth its price and easily available. Fast flash chips are also available for reasonable prices. All of those projects would not result in any coreboot code, but they would make development easier, and that's a value in itself, especially now that we're porting coreboot to laptops where a LPC bus may be the only easily available bus at startup. Comments? Do we have mentors who can review VHDL/Verilog? Regards, Carl-Daniel

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Re: [coreboot] GSoC project ideas
by Oliver Schinagl 12 Mar '12

12 Mar '12

On 03/12/12 19:07, Svetoslav Trochev wrote: > Hi Carl-Daniel, > > I don't qualify as GSoC student (too old ;) ). For sure I can't be I don't think age matters, as long as you are an student at a recognized school, google approves. > mentor because I am absolute newbie here, but I am interested to find > out If I can help with one of those projects. I know the theory how > those things are working, but I have zero experience. Do you think I > can be useful even if it is outside the GSoC program? > > Thanks, > Svetoslav Trochev > > On Sat, Mar 10, 2012 at 12:27 PM, Carl-Daniel Hailfinger > <c-d.hailfinger.devel.2006(a)gmx.net> wrote: >> Hi, >> >> given the lack of affordable and available hardware tools for coreboot >> development, I propose to look for a different set of projects this >> year: Tools which would help developers, and which are usable especially >> with current hardware. A list of ideas follows. >> >> - Flash ICE device with SPI support. >> - Flash ICE device with LPC/FWH support. >> - Serial emulation for LPC buses on a configurable I/O port with USB >> output on the other side. >> - Dual serial emulation for two LPC buses either on the same device or >> with two identical devices and a fast bus in between. >> - Serial emulation for PCI buses (i.e. PCI/serial card). >> >> The reason for the flash ICE devices is obvious: Avoid external >> reflashing while you're developing. >> >> The serial emulation or similar POST code port emulation is meant to >> provide a serial console, a SerialICE connection and/or some POST code >> output channel. This is especially important for laptops where debugging >> can be a pain and where you usually have a LPC bus available in the >> MiniPCIe slot. >> >> The dual serial emulation for two LPC buses would work as a fast >> PC-to-PC connection for SerialICE and other purposes where you need low >> latency, not necessarily high throughput. >> >> The serial emulation for PCI buses would complement the serial emulation >> for LPC to provide an easy way to connect to a SerialICE instance on the >> other side. >> >> As a basis for all those ideas I'd propose the Openbench logic sniffer. >> It has a fast FPGA, enough gates and roughly 32 kByte RAM. The FPGA is >> fast enough and big enough to accommodate the necessary logic, and we >> could easily attach a fast (66+ MHz) SPI flash chip to it. And with $50 >> incl. shipping the OLS is not extremely cheap, but worth its price and >> easily available. Fast flash chips are also available for reasonable prices. >> >> All of those projects would not result in any coreboot code, but they >> would make development easier, and that's a value in itself, especially >> now that we're porting coreboot to laptops where a LPC bus may be the >> only easily available bus at startup. >> >> Comments? Do we have mentors who can review VHDL/Verilog? >> >> Regards, >> Carl-Daniel >> >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> http://www.coreboot.org/mailman/listinfo/coreboot

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coreboot March 2012