coreboot March 2012

coreboot@coreboot.org

58 participants
718 discussions

New patch to review for coreboot: 02390cb Fix AMD Fam15 CBMEM allocation
by Stefan Reinauer 16 Mar '12

16 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/796 -gerrit commit 02390cb08094fe175a76bba51d5586d29b4d7ad2 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Fri Mar 16 10:31:37 2012 -0700 Fix AMD Fam15 CBMEM allocation The Fam15 northbridge.c had hardcoded the CBMEM size. It should use the one in cbmem.h instead. Change-Id: I8a00e05884bdb1d1a4a012433b0adfbb9eb22983 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/northbridge/amd/agesa/family15/northbridge.c | 20 +++++++++----------- 1 files changed, 9 insertions(+), 11 deletions(-) diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index b0fc91d..d1a322c 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -28,6 +28,7 @@ #include <string.h> #include <bitops.h> #include <cpu/cpu.h> +#include <cbmem.h> #include <cpu/x86/lapic.h> @@ -624,10 +625,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) return mem_hole; } #endif -#if CONFIG_WRITE_HIGH_TABLES==1 -#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB -extern uint64_t high_tables_base, high_tables_size; -#endif + #if CONFIG_GFXUMA == 1 extern uint64_t uma_memory_base, uma_memory_size; static void add_uma_resource(struct device *dev, int index) @@ -779,13 +777,13 @@ static void domain_set_resources(device_t dev) if (high_tables_base==0) { /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA == 1 - high_tables_base = uma_memory_base - (HIGH_TABLES_SIZE * 1024); + high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; #else - high_tables_base = (mmio_basek - HIGH_TABLES_SIZE) * 1024; + high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE; #endif - high_tables_size = HIGH_TABLES_SIZE * 1024; + high_tables_size = HIGH_MEMORY_SIZE; printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", - HIGH_TABLES_SIZE, high_tables_base); + (u32)(high_tables_size / 1024), high_tables_base); } #endif } @@ -813,11 +811,11 @@ static void domain_set_resources(device_t dev) if (high_tables_base==0) { /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA == 1 - high_tables_base = uma_memory_base - (HIGH_TABLES_SIZE * 1024); + high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; #else - high_tables_base = (limitk - HIGH_TABLES_SIZE) * 1024; + high_tables_base = (limitk * 1024) - HIGH_MEMORY_SIZE; #endif - high_tables_size = HIGH_TABLES_SIZE * 1024; + high_tables_size = HIGH_MEMORY_SIZE; } #endif }

1 0

New patch to review for coreboot: 4ba35db Fix AMD Fam12 CBMEM allocation
by Stefan Reinauer 16 Mar '12

16 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/795 -gerrit commit 4ba35db13d4a33721e4a8b333428926edd997b69 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Fri Mar 16 10:26:39 2012 -0700 Fix AMD Fam12 CBMEM allocation The Fam12 northbridge.c had hardcoded the CBMEM size. It should use the one in cbmem.h instead. Change-Id: I1eca18e21fa59ae32e802d8452e42e8b7a3575cf Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/northbridge/amd/agesa/family12/northbridge.c | 21 +++++++++------------ 1 files changed, 9 insertions(+), 12 deletions(-) diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index 2c039d2..a3afecb 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -28,6 +28,7 @@ #include <string.h> #include <bitops.h> #include <cpu/cpu.h> +#include <cbmem.h> #include <cpu/x86/lapic.h> @@ -337,11 +338,6 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) } #endif -#if CONFIG_WRITE_HIGH_TABLES==1 -#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB -extern uint64_t high_tables_base, high_tables_size; -#endif - #if CONFIG_GFXUMA == 1 extern uint64_t uma_memory_base, uma_memory_size; @@ -719,12 +715,13 @@ printk(BIOS_DEBUG, "adsr: mmio_basek=%08x, basek=%08x, limitk=%08x\n", mmio_bas if (high_tables_base==0) { /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA == 1 - high_tables_base = uma_memory_base - (HIGH_TABLES_SIZE * 1024); + high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; #else - high_tables_base = (mmio_basek - HIGH_TABLES_SIZE) * 1024; + high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE; #endif - high_tables_size = HIGH_TABLES_SIZE * 1024; - printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", HIGH_TABLES_SIZE, + high_tables_size = HIGH_MEMORY_SIZE; + printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", + (u32)(high_tables_size / 1024), high_tables_base); } #endif @@ -749,12 +746,12 @@ printk(BIOS_DEBUG, "adsr: mmio_basek=%08x, basek=%08x, limitk=%08x\n", mmio_bas if (high_tables_base==0) { /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA == 1 - high_tables_base = uma_memory_base - (HIGH_TABLES_SIZE * 1024); + high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; printk(BIOS_DEBUG, " adsr - uma_memory_base = %x.\n",uma_memory_base); #else - high_tables_base = (limitk - HIGH_TABLES_SIZE) * 1024; + high_tables_base = (limitk * 1024) - HIGH_MEMORY_SIZE; #endif - high_tables_size = HIGH_TABLES_SIZE * 1024; + high_tables_size = HIGH_MEMORY_SIZE; } #endif }

1 0

New patch to review for coreboot: b3d4024 Fix AMD Fam10 CBMEM allocation
by Stefan Reinauer 16 Mar '12

16 Mar '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/794 -gerrit commit b3d402464addf9daa3af5af98df9c6735a08acb6 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Fri Mar 16 10:19:51 2012 -0700 Fix AMD Fam10 CBMEM allocation The Fam10 northbridge.c had hardcoded the CBMEM size. It should use the one in cbmem.h instead. Change-Id: Id6c4128d8f5f6a417f83daa3a39b2bfc8e810f8a Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/northbridge/amd/agesa/family10/northbridge.c | 22 +++++++++------------- 1 files changed, 9 insertions(+), 13 deletions(-) diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index b3e4c63..ee02f0d 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -29,6 +29,7 @@ #include <bitops.h> #include <cpu/cpu.h> #include <cpu/x86/lapic.h> +#include <cbmem.h> #if CONFIG_LOGICAL_CPUS==1 #include <pc80/mc146818rtc.h> @@ -907,11 +908,6 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) } #endif -#if CONFIG_WRITE_HIGH_TABLES==1 -#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB -extern uint64_t high_tables_base, high_tables_size; -#endif - #if CONFIG_GFXUMA == 1 extern uint64_t uma_memory_base, uma_memory_size; @@ -1062,13 +1058,13 @@ static void amdfam10_domain_set_resources(device_t dev) if (high_tables_base==0) { /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA == 1 - high_tables_base = uma_memory_base - (HIGH_TABLES_SIZE * 1024); + high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; #else - high_tables_base = (mmio_basek - HIGH_TABLES_SIZE) * 1024; + high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE; #endif - high_tables_size = HIGH_TABLES_SIZE * 1024; - printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", HIGH_TABLES_SIZE, - high_tables_base); + high_tables_size = HIGH_MEMORY_SIZE; + printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", + (u32)(high_tables_size / 1024), high_tables_base); } #endif } @@ -1096,11 +1092,11 @@ static void amdfam10_domain_set_resources(device_t dev) if (high_tables_base==0) { /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA == 1 - high_tables_base = uma_memory_base - (HIGH_TABLES_SIZE * 1024); + high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; #else - high_tables_base = (limitk - HIGH_TABLES_SIZE) * 1024; + high_tables_base = (limitk * 1024) - HIGH_MEMORY_SIZE; #endif - high_tables_size = HIGH_TABLES_SIZE * 1024; + high_tables_size = HIGH_MEMORY_SIZE; } #endif }

1 0

Patch set updated for coreboot: b2c3e16 Fix AMD Agesa leaking Kconfig
by Kyösti Mälkki 16 Mar '12

16 Mar '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/773 -gerrit commit b2c3e16815c00ea9465d476dc161d9d8f0b277f9 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Mar 16 15:15:20 2012 +0200 Fix AMD Agesa leaking Kconfig Kconfig leaked XIP_ROM_SIZE to other platforms and also defined obsolete option XIP_ROM_BASE. Alias AMD_AGESA as NORTHBRIDGE_AMD_AGESA. Break the circular dependency with family15 Kconfig. Change-Id: Ic7891012220e1bef758a5a39002b66971d5206e3 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/agesa/Kconfig | 8 +++++--- src/cpu/amd/agesa/family15/Kconfig | 5 ----- src/northbridge/amd/Makefile.inc | 2 +- src/northbridge/amd/agesa/Kconfig | 7 +++++++ 4 files changed, 13 insertions(+), 9 deletions(-) diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index 631724b..f8a8c3f 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -19,11 +19,10 @@ config AMD_AGESA bool + default y if CPU_AMD_AGESA_FAMILY15 default n -config XIP_ROM_BASE - hex - default 0xfff00000 +if AMD_AGESA config XIP_ROM_SIZE hex @@ -40,3 +39,6 @@ source src/cpu/amd/agesa/family10/Kconfig source src/cpu/amd/agesa/family12/Kconfig source src/cpu/amd/agesa/family14/Kconfig source src/cpu/amd/agesa/family15/Kconfig + +endif # AMD_AGESA + diff --git a/src/cpu/amd/agesa/family15/Kconfig b/src/cpu/amd/agesa/family15/Kconfig index 0f2f920..c1528f6 100644 --- a/src/cpu/amd/agesa/family15/Kconfig +++ b/src/cpu/amd/agesa/family15/Kconfig @@ -20,7 +20,6 @@ config CPU_AMD_AGESA_FAMILY15 bool select PCI_IO_CFG_EXT - select AMD_AGESA if CPU_AMD_AGESA_FAMILY15 @@ -58,10 +57,6 @@ config CDB hex default 0x18 -config XIP_ROM_BASE - hex - default 0xfff80000 - config XIP_ROM_SIZE hex default 0x80000 diff --git a/src/northbridge/amd/Makefile.inc b/src/northbridge/amd/Makefile.inc index c438473..7e85d08 100644 --- a/src/northbridge/amd/Makefile.inc +++ b/src/northbridge/amd/Makefile.inc @@ -3,6 +3,6 @@ subdirs-$(CONFIG_NORTHBRIDGE_AMD_AMDK8) += amdk8 subdirs-$(CONFIG_NORTHBRIDGE_AMD_GX1) += gx1 subdirs-$(CONFIG_NORTHBRIDGE_AMD_GX2) += gx2 subdirs-$(CONFIG_NORTHBRIDGE_AMD_LX) += lx +subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA) += agesa -subdirs-$(CONFIG_AMD_AGESA) += agesa subdirs-$(CONFIG_AMD_NB_CIMX) += cimx diff --git a/src/northbridge/amd/agesa/Kconfig b/src/northbridge/amd/agesa/Kconfig index 2ed9fd5..8c0e7ab 100644 --- a/src/northbridge/amd/agesa/Kconfig +++ b/src/northbridge/amd/agesa/Kconfig @@ -17,6 +17,12 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # +config NORTHBRIDGE_AMD_AGESA + bool + default AMD_AGESA + +if NORTHBRIDGE_AMD_AGESA + config CONSOLE_VGA_MULTI bool default n @@ -26,3 +32,4 @@ source src/northbridge/amd/agesa/family12/Kconfig source src/northbridge/amd/agesa/family14/Kconfig source src/northbridge/amd/agesa/family15/Kconfig +endif # NORTHBRIDGE_AMD_AGESA

1 0

New patch to review for coreboot: 35c0887 AMD Agesa: delete no-op bootblock files
by Kyösti Mälkki 16 Mar '12

16 Mar '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/793 -gerrit commit 35c0887e0affdb4c7f6a4ef053271dfb25c012af Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Mar 16 15:54:18 2012 +0200 AMD Agesa: delete no-op bootblock files Removes files: src/northbridge/amd/agesa/family10/bootblock.c src/northbridge/amd/agesa/family12/bootblock.c src/northbridge/amd/agesa/family14/bootblock.c src/northbridge/amd/agesa/family15/bootblock.c Change-Id: Ic3617a673b38d065ca272c4de8ef765ecd3f98b1 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/amd/agesa/family10/Kconfig | 3 -- src/northbridge/amd/agesa/family10/bootblock.c | 29 ------------------------ src/northbridge/amd/agesa/family12/Kconfig | 4 --- src/northbridge/amd/agesa/family12/bootblock.c | 29 ------------------------ src/northbridge/amd/agesa/family14/Kconfig | 4 --- src/northbridge/amd/agesa/family14/bootblock.c | 29 ------------------------ src/northbridge/amd/agesa/family15/Kconfig | 3 -- src/northbridge/amd/agesa/family15/bootblock.c | 25 -------------------- 8 files changed, 0 insertions(+), 126 deletions(-) diff --git a/src/northbridge/amd/agesa/family10/Kconfig b/src/northbridge/amd/agesa/family10/Kconfig index 62a6cd4..0bb16d9 100755 --- a/src/northbridge/amd/agesa/family10/Kconfig +++ b/src/northbridge/amd/agesa/family10/Kconfig @@ -41,9 +41,6 @@ config MMCONF_BASE_ADDRESS config MMCONF_BUS_NUMBER int default 256 -config BOOTBLOCK_NORTHBRIDGE_INIT - string - default "northbridge/amd/agesa/family10/bootblock.c" endif #NORTHBRIDGE_AMD_AGESA_FAMILY10 source "src/northbridge/amd/agesa/family10/root_complex/Kconfig" diff --git a/src/northbridge/amd/agesa/family10/bootblock.c b/src/northbridge/amd/agesa/family10/bootblock.c deleted file mode 100644 index f6ae8be..0000000 --- a/src/northbridge/amd/agesa/family10/bootblock.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - ***************************************************************************** - * - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * *************************************************************************** - * - */ - -#include <arch/io.h> -#include <arch/romcc_io.h> -#include <device/pci_def.h> - -static void bootblock_northbridge_init(void) { -} diff --git a/src/northbridge/amd/agesa/family12/Kconfig b/src/northbridge/amd/agesa/family12/Kconfig index fc3c436..8ab5de8 100755 --- a/src/northbridge/amd/agesa/family12/Kconfig +++ b/src/northbridge/amd/agesa/family12/Kconfig @@ -73,7 +73,3 @@ if DIMM_DDR3 endif endif -config BOOTBLOCK_NORTHBRIDGE_INIT - string - default "northbridge/amd/agesa/family12/bootblock.c" - depends on NORTHBRIDGE_AMD_AGESA_FAMILY12 diff --git a/src/northbridge/amd/agesa/family12/bootblock.c b/src/northbridge/amd/agesa/family12/bootblock.c deleted file mode 100644 index f6ae8be..0000000 --- a/src/northbridge/amd/agesa/family12/bootblock.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - ***************************************************************************** - * - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * *************************************************************************** - * - */ - -#include <arch/io.h> -#include <arch/romcc_io.h> -#include <device/pci_def.h> - -static void bootblock_northbridge_init(void) { -} diff --git a/src/northbridge/amd/agesa/family14/Kconfig b/src/northbridge/amd/agesa/family14/Kconfig index 44f93c1..e462153 100644 --- a/src/northbridge/amd/agesa/family14/Kconfig +++ b/src/northbridge/amd/agesa/family14/Kconfig @@ -39,8 +39,4 @@ config MMCONF_BUS_NUMBER int default 16 -config BOOTBLOCK_NORTHBRIDGE_INIT - string - default "northbridge/amd/agesa/family14/bootblock.c" - endif diff --git a/src/northbridge/amd/agesa/family14/bootblock.c b/src/northbridge/amd/agesa/family14/bootblock.c deleted file mode 100644 index f6ae8be..0000000 --- a/src/northbridge/amd/agesa/family14/bootblock.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - ***************************************************************************** - * - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * *************************************************************************** - * - */ - -#include <arch/io.h> -#include <arch/romcc_io.h> -#include <device/pci_def.h> - -static void bootblock_northbridge_init(void) { -} diff --git a/src/northbridge/amd/agesa/family15/Kconfig b/src/northbridge/amd/agesa/family15/Kconfig index 52f7a1e..382c1af 100644 --- a/src/northbridge/amd/agesa/family15/Kconfig +++ b/src/northbridge/amd/agesa/family15/Kconfig @@ -41,9 +41,6 @@ config MMCONF_BASE_ADDRESS config MMCONF_BUS_NUMBER int default 64 -config BOOTBLOCK_NORTHBRIDGE_INIT - string - default "northbridge/amd/agesa/family15/bootblock.c" endif #NORTHBRIDGE_AMD_AGESA_FAMILY15 source "src/northbridge/amd/agesa/family15/root_complex/Kconfig" diff --git a/src/northbridge/amd/agesa/family15/bootblock.c b/src/northbridge/amd/agesa/family15/bootblock.c deleted file mode 100644 index fc62c3e..0000000 --- a/src/northbridge/amd/agesa/family15/bootblock.c +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <arch/io.h> -#include <arch/romcc_io.h> -#include <device/pci_def.h> - -static void bootblock_northbridge_init(void) { -}

1 0

New patch to review for coreboot: bb5e0c2 Rename AMD_AGESA to CPU_AMD_AGESA
by Kyösti Mälkki 16 Mar '12

16 Mar '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/792 -gerrit commit bb5e0c247059617f80f7454900b1d9148ca3b35a Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Mar 16 15:40:56 2012 +0200 Rename AMD_AGESA to CPU_AMD_AGESA Also any CPU_AMD_AGESA_FAMILYxx selects CPU_AMD_AGESA, so remove the explicit selects from the mainboards. Change-Id: I4d71726bccd446b0f4db4e26448b5c91e406a641 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/init/bootblock.ld | 2 +- src/cpu/amd/Makefile.inc | 2 +- src/cpu/amd/agesa/Kconfig | 9 ++++++--- src/mainboard/advansus/a785e-i/Makefile.inc | 2 +- src/mainboard/amd/inagua/Kconfig | 4 ---- src/mainboard/amd/persimmon/Kconfig | 4 ---- src/mainboard/amd/south_station/Kconfig | 4 ---- src/mainboard/amd/torpedo/Kconfig | 4 ---- src/mainboard/amd/union_station/Kconfig | 4 ---- src/mainboard/asrock/e350m1/Kconfig | 4 ---- src/mainboard/asus/m5a88-v/Makefile.inc | 2 +- src/mainboard/avalue/eax-785e/Makefile.inc | 2 +- src/northbridge/amd/agesa/Kconfig | 2 +- 13 files changed, 12 insertions(+), 33 deletions(-) diff --git a/src/arch/x86/init/bootblock.ld b/src/arch/x86/init/bootblock.ld index bde0430..fd4d3db 100644 --- a/src/arch/x86/init/bootblock.ld +++ b/src/arch/x86/init/bootblock.ld @@ -51,5 +51,5 @@ SECTIONS *(.eh_frame); } - _bogus = ASSERT((SIZEOF(.bss) + SIZEOF(.data)) == 0 || CONFIG_AMD_AGESA, "Do not use global variables in romstage"); + _bogus = ASSERT((SIZEOF(.bss) + SIZEOF(.data)) == 0 || CONFIG_CPU_AMD_AGESA, "Do not use global variables in romstage"); } diff --git a/src/cpu/amd/Makefile.inc b/src/cpu/amd/Makefile.inc index 2ea376a..6663d14 100644 --- a/src/cpu/amd/Makefile.inc +++ b/src/cpu/amd/Makefile.inc @@ -14,4 +14,4 @@ subdirs-$(CONFIG_CPU_AMD_GEODE_LX) += geode_lx subdirs-$(CONFIG_CPU_AMD_SC520) += sc520 subdirs-$(CONFIG_CPU_AMD_SOCKET_S1G1) += socket_S1G1 -subdirs-$(CONFIG_AMD_AGESA) += agesa +subdirs-$(CONFIG_CPU_AMD_AGESA) += agesa diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index f8a8c3f..18f74e8 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -17,12 +17,15 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # -config AMD_AGESA +config CPU_AMD_AGESA bool + default y if CPU_AMD_AGESA_FAMILY10 + default y if CPU_AMD_AGESA_FAMILY12 + default y if CPU_AMD_AGESA_FAMILY14 default y if CPU_AMD_AGESA_FAMILY15 default n -if AMD_AGESA +if CPU_AMD_AGESA config XIP_ROM_SIZE hex @@ -40,5 +43,5 @@ source src/cpu/amd/agesa/family12/Kconfig source src/cpu/amd/agesa/family14/Kconfig source src/cpu/amd/agesa/family15/Kconfig -endif # AMD_AGESA +endif # CPU_AMD_AGESA diff --git a/src/mainboard/advansus/a785e-i/Makefile.inc b/src/mainboard/advansus/a785e-i/Makefile.inc index 737bb1c..d69a9bf 100755 --- a/src/mainboard/advansus/a785e-i/Makefile.inc +++ b/src/mainboard/advansus/a785e-i/Makefile.inc @@ -3,7 +3,7 @@ ramstage-y += reset.c #SB800 CIMx share AGESA V5 lib code -ifneq ($(CONFIG_AMD_AGESA),y) +ifneq ($(CONFIG_CPU_AMD_AGESA),y) AGESA_ROOT ?= src/vendorcode/amd/agesa/f14 romstage-y += ../../../../$(AGESA_ROOT)/Lib/amdlib.c ramstage-y += ../../../../$(AGESA_ROOT)/Lib/amdlib.c diff --git a/src/mainboard/amd/inagua/Kconfig b/src/mainboard/amd/inagua/Kconfig index a5920af..bd8a184 100644 --- a/src/mainboard/amd/inagua/Kconfig +++ b/src/mainboard/amd/inagua/Kconfig @@ -43,10 +43,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ENABLE_APIC_EXT_ID select GFXUMA -config AMD_AGESA - bool - default y - config MAINBOARD_DIR string default amd/inagua diff --git a/src/mainboard/amd/persimmon/Kconfig b/src/mainboard/amd/persimmon/Kconfig index e01e101..9212e20 100644 --- a/src/mainboard/amd/persimmon/Kconfig +++ b/src/mainboard/amd/persimmon/Kconfig @@ -42,10 +42,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_4096 select GFXUMA -config AMD_AGESA - bool - default y - config MAINBOARD_DIR string default amd/persimmon diff --git a/src/mainboard/amd/south_station/Kconfig b/src/mainboard/amd/south_station/Kconfig index fb41cec..2853978 100644 --- a/src/mainboard/amd/south_station/Kconfig +++ b/src/mainboard/amd/south_station/Kconfig @@ -43,10 +43,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select GFXUMA select UDELAY_LAPIC -config AMD_AGESA - bool - default y - config MAINBOARD_DIR string default amd/south_station diff --git a/src/mainboard/amd/torpedo/Kconfig b/src/mainboard/amd/torpedo/Kconfig index f368279..bc4030c 100755 --- a/src/mainboard/amd/torpedo/Kconfig +++ b/src/mainboard/amd/torpedo/Kconfig @@ -45,10 +45,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ENABLE_APIC_EXT_ID select GFXUMA -config AMD_AGESA - bool - default y - config MAINBOARD_DIR string default amd/torpedo diff --git a/src/mainboard/amd/union_station/Kconfig b/src/mainboard/amd/union_station/Kconfig index cc2e300..b67736b 100644 --- a/src/mainboard/amd/union_station/Kconfig +++ b/src/mainboard/amd/union_station/Kconfig @@ -42,10 +42,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select GFXUMA select UDELAY_LAPIC -config AMD_AGESA - bool - default y - config MAINBOARD_DIR string default amd/union_station diff --git a/src/mainboard/asrock/e350m1/Kconfig b/src/mainboard/asrock/e350m1/Kconfig index 8324fa4..edeae21 100644 --- a/src/mainboard/asrock/e350m1/Kconfig +++ b/src/mainboard/asrock/e350m1/Kconfig @@ -43,10 +43,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_4096 select GFXUMA -config AMD_AGESA - bool - default y - config MAINBOARD_DIR string default asrock/e350m1 diff --git a/src/mainboard/asus/m5a88-v/Makefile.inc b/src/mainboard/asus/m5a88-v/Makefile.inc index b55a0c7..35b2043 100644 --- a/src/mainboard/asus/m5a88-v/Makefile.inc +++ b/src/mainboard/asus/m5a88-v/Makefile.inc @@ -1,7 +1,7 @@ ramstage-y += reset.c #SB800 CIMx share AGESA V5 lib code -ifneq ($(CONFIG_AMD_AGESA),y) +ifneq ($(CONFIG_CPU_AMD_AGESA),y) AGESA_ROOT ?= src/vendorcode/amd/agesa/f14 romstage-y += ../../../../$(AGESA_ROOT)/Lib/amdlib.c ramstage-y += ../../../../$(AGESA_ROOT)/Lib/amdlib.c diff --git a/src/mainboard/avalue/eax-785e/Makefile.inc b/src/mainboard/avalue/eax-785e/Makefile.inc index 737bb1c..d69a9bf 100644 --- a/src/mainboard/avalue/eax-785e/Makefile.inc +++ b/src/mainboard/avalue/eax-785e/Makefile.inc @@ -3,7 +3,7 @@ ramstage-y += reset.c #SB800 CIMx share AGESA V5 lib code -ifneq ($(CONFIG_AMD_AGESA),y) +ifneq ($(CONFIG_CPU_AMD_AGESA),y) AGESA_ROOT ?= src/vendorcode/amd/agesa/f14 romstage-y += ../../../../$(AGESA_ROOT)/Lib/amdlib.c ramstage-y += ../../../../$(AGESA_ROOT)/Lib/amdlib.c diff --git a/src/northbridge/amd/agesa/Kconfig b/src/northbridge/amd/agesa/Kconfig index 8c0e7ab..2ee921b 100644 --- a/src/northbridge/amd/agesa/Kconfig +++ b/src/northbridge/amd/agesa/Kconfig @@ -19,7 +19,7 @@ config NORTHBRIDGE_AMD_AGESA bool - default AMD_AGESA + default CPU_AMD_AGESA if NORTHBRIDGE_AMD_AGESA

1 0

New patch to review for coreboot: 0a3613c Makefile: XIP_ROM_SIZE error is not fatal
by Kyösti Mälkki 16 Mar '12

16 Mar '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/791 -gerrit commit 0a3613c109beaa5038a43b8bc146720c80aa249b Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Mar 16 07:37:41 2012 +0200 Makefile: XIP_ROM_SIZE error is not fatal Romstage size exceeds XIP_ROM_SIZE on following boards: intel/truxton intel/xe7501devkit via/epia-n This marks the complete Jenkins build as failed. XIP_ROM_SIZE should be increased on these platforms, but only after testing on real hardware that they have sufficient cache. As a workaround, complete such builds with an unaligned placement of romstage in the flash image binary. These should execute, but very slowly. Change-Id: I4d7c791958e3d518051207ab97deef5890dac6cf Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/Makefile.inc | 7 ++++++- 1 files changed, 6 insertions(+), 1 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 75546f1..da49373 100755 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -109,6 +109,7 @@ ifeq ($(CONFIG_INCLUDE_CONFIG_FILE),y) endif mv $@.tmp $@ @printf " CBFSPRINT $(subst $(obj)/,,$(@))\n\n" + if [ -f $(obj)/no_xip ]; then echo "The romstage is larger than XIP size. Please expand the CONFIG_XIP_ROM_SIZE.\n" ; fi $(CBFSTOOL) $@ print stripped_vgabios_id = $(call strip_quotes,$(CONFIG_VGA_BIOS_ID)) @@ -346,7 +347,11 @@ $(obj)/coreboot.romstage: $(obj)/coreboot.pre1 $$(romstage-objs) $(obj)/romstage $(CC) -nostdlib -nostartfiles -static -o $(obj)/romstage.elf -L$(obj) -T $(obj)/romstage/ldscript.ld $(romstage-objs) $(OBJCOPY) -O binary $(obj)/romstage.elf $(obj)/romstage.bin printf "CONFIG_ROMBASE = 0x" > $(obj)/location.ld - $(CBFSTOOL) $(obj)/coreboot.pre1 locate $(obj)/romstage.bin $(CONFIG_CBFS_PREFIX)/romstage $(CONFIG_XIP_ROM_SIZE) > $(obj)/location.txt || { echo "The romstage is larger than XIP size. Please expand the CONFIG_XIP_ROM_SIZE" ; exit 1; } + rm -f $(obj)/no_xip + $(CBFSTOOL) $(obj)/coreboot.pre1 locate $(obj)/romstage.bin $(CONFIG_CBFS_PREFIX)/romstage $(CONFIG_XIP_ROM_SIZE) > $(obj)/location.txt || touch $(obj)/no_xip + if [ -f $(obj)/no_xip ]; then \ + $(CBFSTOOL) $(obj)/coreboot.pre1 locate $(obj)/romstage.bin $(CONFIG_CBFS_PREFIX)/romstage $(CONFIG_ROM_SIZE) > $(obj)/location.txt || exit 1 ; \ + fi cat $(obj)/location.txt >> $(obj)/location.ld printf ';\n' >> $(obj)/location.ld $(CC) -nostdlib -nostartfiles -static -o $(obj)/romstage.elf -L$(obj) -T $(obj)/romstage/ldscript.ld $(romstage-objs)

1 0

Re: [coreboot] coreboot Digest, Vol 85, Issue 68
by manasa gv 16 Mar '12

16 Mar '12

Thanks for suggestions..I will go through the provided link. On Thu, Mar 15, 2012 at 11:12 PM, <coreboot-request(a)coreboot.org> wrote: > Send coreboot mailing list submissions to > coreboot(a)coreboot.org > > To subscribe or unsubscribe via the World Wide Web, visit > http://www.coreboot.org/mailman/listinfo/coreboot > or, via email, send a message with subject or body 'help' to > coreboot-request(a)coreboot.org > > You can reach the person managing the list at > coreboot-owner(a)coreboot.org > > When replying, please edit your Subject line so it is more specific > than "Re: Contents of coreboot digest..." > > > Today's Topics: > > 1. Patch merged into coreboot/master: a47f09d AGESA family 12 > changes to fix torpedo warnings (gerrit(a)coreboot.org) > 2. Re: SMP stop_this_cpu and AP_IN_SIPI_WAIT (ron minnich) > 3. Re: Problems with Winnet G270 Board / Igel Thin Client 3210 > need help (Christian) > 4. Patch merged into coreboot/master: 8cc685b Since cbfs_core.h > provides a macro that uses ntohl, make sure ntohl is available > (gerrit(a)coreboot.org) > 5. Fwd: kindly requesting to assign work on coreboot (manasa gv) > 6. Fwd: kindly requesting to assign work on coreboot (manasa gv) > 7. [RFC] Improve very early boot (Ky?sti M?lkki) > 8. Re: Fwd: kindly requesting to assign work on coreboot > (Paul Menzel) > 9. kindly requestig to assign work on coreboot (manasa gv) > 10. Re: [RFC] Improve very early boot (Patrick Georgi) > > > ---------------------------------------------------------------------- > > Message: 1 > Date: Wed, 14 Mar 2012 00:57:57 +0100 > From: gerrit(a)coreboot.org > To: coreboot(a)coreboot.org > Subject: [coreboot] Patch merged into coreboot/master: a47f09d AGESA > family 12 changes to fix torpedo warnings > Message-ID: <E1S7bbJ-0007ag-Gr(a)ra.coresystems.de> > Content-Type: text/plain; charset="UTF-8" > > the following patch was just integrated into master: > commit a47f09d8e723896eb63ae8437250c0ee7ce68da9 > Author: Martin Roth <martin(a)se-eng.com> > Date: Fri Feb 17 13:16:04 2012 -0700 > > AGESA family 12 changes to fix torpedo warnings > > Fixes the warnings generated in the torpedo mainboard build by AGESA. > Removing broken tests. > > Change-Id: Ib444fa2bf4dd94cadb4ce33040eb5650d1c0325b > Signed-off-by: Martin L Roth <martin(a)se-eng.com> > > Build-Tested: build bot (Jenkins) at Fri Feb 17 22:50:04 2012, giving +1 > Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Wed Feb 29 > 23:32:35 2012, giving +2 > See http://review.coreboot.org/667 for details. > > -gerrit > > > > ------------------------------ > > Message: 2 > Date: Tue, 13 Mar 2012 19:40:41 -0700 > From: ron minnich <rminnich(a)gmail.com> > To: Ky?sti M?lkki <kyosti.malkki(a)gmail.com> > Cc: Coreboot <coreboot(a)coreboot.org> > Subject: Re: [coreboot] SMP stop_this_cpu and AP_IN_SIPI_WAIT > Message-ID: > > <CAP6exYJZxNY+8SxEFKUW7pYa_j_sUsVCt1Huf-iYB5HC70cjGg(a)mail.gmail.com> > Content-Type: text/plain; charset=ISO-8859-1 > > On Tue, Mar 13, 2012 at 1:13 PM, Ky?sti M?lkki <kyosti.malkki(a)gmail.com> > wrote: > >> Seems like the patch just appeared and was merged without any >> discussion. It would have been nice to describe the circumstances under >> which Intel Core Duo failed... > > Assuming one is allowed to. Keep in mind that there are changes that > go in that people can't talk about because they are under some sort of > NDA. This may have been one of them. I do not know. > > ron > > > > ------------------------------ > > Message: 3 > Date: Wed, 14 Mar 2012 19:22:06 +0100 > From: Christian <christian.suehs(a)online.de> > To: coreboot(a)coreboot.org > Subject: Re: [coreboot] Problems with Winnet G270 Board / Igel Thin > Client 3210 need help > Message-ID: <1331749326.5272.4.camel(a)dance-or-die3.athome.de> > Content-Type: text/plain; charset="UTF-8" > > >> >> For Via Model A Eden I have to change the >> >> static int c7a_speed_translation[] = { >> // LFM HFM > 0x0409, 0x0609 // 400MHz, 844mV --> 600MHz, 844mV Eden > insert this line for Via Eden 600MHz CPU >> 0x0409, 0x0f13, // 400MHz, 844mV --> 1500MHz, 1.004V >> C7-M >> 0x0409, 0x1018, // 400MHz, 844mV --> 1600MHz, 1.084V >> 0x0409, 0x0c18, // 533MHz, 844mV --> 1600MHz, 1.084V >> 0x0409, 0x121c, // 400MHz, 844mV --> 1800MHz, 1.148V >> 0x0409, 0x0e1c, // 533MHz, 844mV --> 1860MHz, 1.148V >> 0x0409, 0x141f, // 400MHz, 844mV --> 2000MHz, 1.196V >> 0x0409, 0x0f1f, // 533MHz, 844mV --> 2000MHz, 1.196V >> 0x0406, 0x0a06, // 400MHz, 796mV --> 1000MHz, 796mV >> C7-M ULV >> 0x0406, 0x0a09, // 400MHz, 796mV --> 1000MHz, 844mV >> 0x0406, 0x0c09, // 400MHz, 796mV --> 1200MHz, 844mV >> 0x0406, 0x0f10, // 400MHz, 796mV --> 1500MHz, 956mV >> }; > > I`m not sure about DRAM Frequency Loading the kernel is a little bit > slower as with factoy Bios, should be 266MHZ. > >> >> > > chris >> >> > > > > > > ------------------------------ > > Message: 4 > Date: Wed, 14 Mar 2012 23:00:27 +0100 > From: gerrit(a)coreboot.org > To: coreboot(a)coreboot.org > Subject: [coreboot] Patch merged into coreboot/master: 8cc685b Since > cbfs_core.h provides a macro that uses ntohl, make sure ntohl is > available > Message-ID: <E1S7wF9-0000ut-MO(a)ra.coresystems.de> > Content-Type: text/plain; charset="UTF-8" > > the following patch was just integrated into master: > commit 8cc685b2e006f3756dd26885b834fb198fa1f137 > Author: Gabe Black <gabeblack(a)google.com> > Date: Fri Sep 16 02:24:03 2011 -0700 > > Since cbfs_core.h provides a macro that uses ntohl, make sure ntohl is > available > > Since cbfs_core.h provides a macro that uses ntohl, make sure ntohl is > available by > including byteorder.h > > Change-Id: I9ab8cb51bd680e861b28d5130d09547bb9ab3b1f > Signed-off-by: Gabe Black <gabeblack(a)google.com> > > Build-Tested: build bot (Jenkins) at Fri Mar 9 05:43:36 2012, giving +1 > Reviewed-By: Peter Stuge <peter(a)stuge.se> at Wed Mar 14 23:00:25 2012, > giving +2 > See http://review.coreboot.org/709 for details. > > -gerrit > > > > ------------------------------ > > Message: 5 > Date: Thu, 15 Mar 2012 15:39:31 +0530 > From: manasa gv <manasa671989(a)gmail.com> > To: coreboot(a)coreboot.org > Subject: [coreboot] Fwd: kindly requesting to assign work on coreboot > Message-ID: > > <CALYtimq4egNViWtXoh4etfz8HFV686hCB20bmfuQaFKhO5WhHA(a)mail.gmail.com> > Content-Type: text/plain; charset="iso-8859-1" > > ---------- Forwarded message ---------- > From: manasa gv <manasa671989(a)gmail.com> > Date: Thu, Mar 15, 2012 at 3:27 PM > Subject: kindly requesting to assign work on coreboot > To: kirantpatil(a)gmail.com > > > Respected sir, > > > I am Manasa, a graduate engineer intersted to work on > coreboot..I have gone through the coreboot website, flashrom,supported > mother boards,chipsets,bios savior and all those things.and also gone > through opencompute.org site to understand regarding mother board and bus > architecture..am new and interested to work on coreboot..so please > assign > some work related to coreboot.. > > > Regards & Thanks, > Manasa >

1 0

[RFC] Improve very early boot
by Kyösti Mälkki 16 Mar '12

16 Mar '12

Hi On selected boards, some hardware initialisation is placed in the bootblock. The source files and directories are currently hard-coded in Kconfigs, which is sort of ugly. A few months ago I put together changeset [1], which hasn't drawn much review or interest. One benefit of my changeset is that it can be extended to move superio and console initialisation to bootblock. Serial-line IO can then be used to switch between fallback/normal romstage and early POSTs could go to serial too. Thanks for any comments. KM [1] http://review.coreboot.org/#/c/473/

2 2

Patch merged into coreboot/master: 36e0e8b Clean up whitespace in fam14 northbridge.c
by gerrit＠coreboot.org 15 Mar '12

15 Mar '12

the following patch was just integrated into master: commit 36e0e8bedfbc3c5a981de88eec62c992973b628a Author: Marc Jones <marc.jones(a)se-eng.com> Date: Thu Mar 15 12:55:26 2012 -0600 Clean up whitespace in fam14 northbridge.c Change-Id: Id7947d7f3c67fdda67861065b1bc7a519b97208f Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Build-Tested: build bot (Jenkins) at Thu Mar 15 21:01:14 2012, giving +1 Reviewed-By: Peter Stuge <peter(a)stuge.se> at Thu Mar 15 21:27:20 2012, giving +2 See http://review.coreboot.org/789 for details. -gerrit

1 0

← Newer
1
...
26
27
28
29
30
31
32
...
72
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot March 2012