coreboot March 2012

coreboot@coreboot.org

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718 discussions

Re: [coreboot] [SerialICE] [ANNOUNCE] libhwremote 0.1
by Carl-Daniel Hailfinger 10 Mar '12

10 Mar '12

Am 10.03.2012 17:52 schrieb Idwer Vollering: > 2012/3/10 Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net>: >> I'm glad to announce libhwremote 0.1, a library which forwards hardware >> accesses over a serial line to a machine running SerialICE. No QEMU needed! >> All you have to do to run lspci/superiotool/... against a remote >> SerialICE target is to compile those tools against libhwremote, and then >> just run them like you would run them natively. >> >> libhwremote is an early prototype. Due to that it has quite a few quirks: >> - Each run of a libhwremote enabled application requires the application >> to be started before SerialICE prints its banner, i.e. start the >> application, then hit reset on the SerialICE target. The reason is the >> init code which expects "newline,serialice_banner,newline" to do >> anything useful. If that banner is not there, the results are undefined. >> - The error handling is mostly working but not really nice. >> - /dev/ttyUSB0 is hardcoded for serial line access, you may want to >> change that. >> - MMIO functions are totally untested, I didn't find any code which >> needed it (except for flashrom, but probing for flash chips might >> interfere with SerialICE functionality if SerialICE runs from ROM). >> - The pciutils patch is totally untested, but I expect it to work. >> >> A big THANK YOU goes to Idwer Vollering who tested a dozen iterations of >> this code until I had figured out the very surprising and unique >> properties of the SerialICE protocol. >> >> Another big THANK YOU goes to Ron Minnich who sent a mail titled >> "[SerialICE] an idea" which motivated me to start this little project: >> http://serialice.com/pipermail/serialice/2009-November/000043.html >> >> This code sat unfinished on my disk since December 2009, and it's about >> time I finished it enough to be usable. >> >> Notes:: >> - superiotool support is tested and stable >> - pciutils (lspci/setpci/...) support is untested, but should work. >> >> Please fetch latest superiotool from the coreboot git tree and latest >> pciutils from the pciutils git tree to apply the patches. > git clone'd from git://git.kernel.org/pub/scm/utils/pciutils/pciutils.git > >> libhwremote is available at: >> http://ra.openbios.org/~carldani/libhwremote-0.1.tar.gz >> >> superiotool patch is available at: >> http://ra.openbios.org/~carldani/superiotool_hwremote.diff >> >> pciutils patch is available at: >> http://ra.openbios.org/~carldani/pciutils_hwremote.diff >> >> I plan to check this code into a source code repository really soon, but >> for now a tarball and separate patch downloads have to suffice. >> >> Tests and bug reports appreciated. > Where is i386-io-libhwremote.h? > > $ make distclean ; make > [...] > gcc -O2 -Wall -W -Wno-parentheses -Wstrict-prototypes > -Wmissing-prototypes -c -o i386-ports.o i386-ports.c > i386-ports.c:30:33: fatal error: i386-io-libhwremote.h: No such file > or directory Ouch. I forgot to git add that file. Please download the updated http://ra.openbios.org/~carldani/pciutils_hwremote.diff Regards, Carl-Daniel -- http://www.hailfinger.org/

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[ANNOUNCE] libhwremote 0.1
by Carl-Daniel Hailfinger 10 Mar '12

10 Mar '12

I'm glad to announce libhwremote 0.1, a library which forwards hardware accesses over a serial line to a machine running SerialICE. No QEMU needed! All you have to do to run lspci/superiotool/... against a remote SerialICE target is to compile those tools against libhwremote, and then just run them like you would run them natively. libhwremote is an early prototype. Due to that it has quite a few quirks: - Each run of a libhwremote enabled application requires the application to be started before SerialICE prints its banner, i.e. start the application, then hit reset on the SerialICE target. The reason is the init code which expects "newline,serialice_banner,newline" to do anything useful. If that banner is not there, the results are undefined. - The error handling is mostly working but not really nice. - /dev/ttyUSB0 is hardcoded for serial line access, you may want to change that. - MMIO functions are totally untested, I didn't find any code which needed it (except for flashrom, but probing for flash chips might interfere with SerialICE functionality if SerialICE runs from ROM). - The pciutils patch is totally untested, but I expect it to work. A big THANK YOU goes to Idwer Vollering who tested a dozen iterations of this code until I had figured out the very surprising and unique properties of the SerialICE protocol. Another big THANK YOU goes to Ron Minnich who sent a mail titled "[SerialICE] an idea" which motivated me to start this little project: http://serialice.com/pipermail/serialice/2009-November/000043.html This code sat unfinished on my disk since December 2009, and it's about time I finished it enough to be usable. Notes:: - superiotool support is tested and stable - pciutils (lspci/setpci/...) support is untested, but should work. Please fetch latest superiotool from the coreboot git tree and latest pciutils from the pciutils git tree to apply the patches. libhwremote is available at: http://ra.openbios.org/~carldani/libhwremote-0.1.tar.gz superiotool patch is available at: http://ra.openbios.org/~carldani/superiotool_hwremote.diff pciutils patch is available at: http://ra.openbios.org/~carldani/pciutils_hwremote.diff I plan to check this code into a source code repository really soon, but for now a tarball and separate patch downloads have to suffice. Tests and bug reports appreciated. Regards, Carl-Daniel -- http://www.hailfinger.org/

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Re: [coreboot] A bit of help needed
by Patrick Georgi 10 Mar '12

10 Mar '12

Am 10.03.2012 11:49, schrieb Jaspal Dhillon: > I was going through the coreboot.org <http://coreboot.org/> and I am > definitely interested in it. Welcome to coreboot, then! > So wanted to ask couple of things. > I have not read the source code yet but tried it out in this way : > 1.Checked out latest version of coreboot on 32bit Fedora 15. make > config with settings as : > MainBoard Vendor : Emulation , Model : Qemu , ROM Size : 256KB , > Payload : SeaBIOS > make was successful . > Since my laptop is a old one and does not have hardware virtualization > support , I use a lab pc ( 64 bit Fedora 15 ) for some of my experiments. qemu requires no hardware virtualization extensions (only kvm does, which is an extended version), and for basic tests it's usually fast enough. > Installation of CentOS ( Minimum installation ) was successful and at > the end , it asked me to reboot. When I clicked on reboot option , > coreboot got stuck in an infinite loop and I was getting this (in a > loop) on the stdio : > > Changing serial settings was 0/0 now 3/0 > In resume (status=0) > In 32bit resume > Attempting a hard reboot These are seabios messages, so its reboot handler doesn't seem to work correctly. Unfortunately, there are ~6 different ways of rebooting an x86 machine (not all of which are available on any given system), so it's possible that CentOS triggered the "wrong" one in seabios, which in turn tries to use a method not supported by qemu (or something like that). > Could you give me some pointers as to where to begin for GSoC or some > little hacks that I should attempt out ? I am trying different > payloads in the meantime. Different payloads is a good start. Ultimately, there so much you could do, that it's better if you specify what area you're most interested in. > I read about mkelfImage command and also tried it out but the > resultant size of linux.elf is ~5MB which exceeds the size of ROM chip > , declared in Qemu. Can I use a kernel payload ( any other ) without > hacking Qemu ? ( I think not but want to know , if yes , how ) . Only by reducing the kernel size - kernel images are usually already compressed, so there's not much we can do. Fortunately, when putting the kernel in flash, you usually know rather well what kind of hardware you're running it on - so you can reduce kernel/initrd to just the drivers required to access the disk, and go from there. I think current qemu versions are more tolerant with flash sizes - you probably can't go above 4MB, but that should be enough to contain an optimized kernel. Regards, Patrick

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Patch merged into coreboot/master: 1b6872f Portability improvement
by gerrit＠coreboot.org 10 Mar '12

10 Mar '12

the following patch was just integrated into master: commit 1b6872f126f99e82c26fb67bb09478f9fa7747e6 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Fri Mar 9 23:02:09 2012 +0100 Portability improvement Makefile.inc uses $( ) syntax on the shell. That's isn't as universal as one would like. Change-Id: I9a8fd511eef7fefc1458d5bae2cd7ef5475b7392 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Sat Mar 10 14:20:42 2012, giving +2 See http://review.coreboot.org/777 for details. -gerrit

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Patch merged into coreboot/master: 8519ed4 Make libpayload alloc() memory pointers volatile
by gerrit＠coreboot.org 10 Mar '12

10 Mar '12

the following patch was just integrated into master: commit 8519ed434a743f7706c1644dba48bdbd90e0245c Author: Marc Jones <marc.jones(a)se-eng.com> Date: Thu Mar 1 16:12:11 2012 -0700 Make libpayload alloc() memory pointers volatile gcc4.6.2 was optimizing the libpayload alloc() function and failing to reload a pointer after the memory had been manipulated by a pointer in the inlined function setup(). Change the pointer type to volatile and now pass it to the setup() function. Also clean up the declaration so that it isn't cast a bunch times in the function. Change-Id: I1637bd7bd5d9cf82ac88925cbfe76d319aa3cd82 Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Sat Mar 10 14:19:42 2012, giving +2 See http://review.coreboot.org/705 for details. -gerrit

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Patch set updated for coreboot: 8519ed4 Make libpayload alloc() memory pointers volatile
by Patrick Georgi 10 Mar '12

10 Mar '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/705 -gerrit commit 8519ed434a743f7706c1644dba48bdbd90e0245c Author: Marc Jones <marc.jones(a)se-eng.com> Date: Thu Mar 1 16:12:11 2012 -0700 Make libpayload alloc() memory pointers volatile gcc4.6.2 was optimizing the libpayload alloc() function and failing to reload a pointer after the memory had been manipulated by a pointer in the inlined function setup(). Change the pointer type to volatile and now pass it to the setup() function. Also clean up the declaration so that it isn't cast a bunch times in the function. Change-Id: I1637bd7bd5d9cf82ac88925cbfe76d319aa3cd82 Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> --- payloads/libpayload/libc/malloc.c | 25 +++++++++++-------------- 1 files changed, 11 insertions(+), 14 deletions(-) diff --git a/payloads/libpayload/libc/malloc.c b/payloads/libpayload/libc/malloc.c index 6389fc9..9412cab 100644 --- a/payloads/libpayload/libc/malloc.c +++ b/payloads/libpayload/libc/malloc.c @@ -73,11 +73,9 @@ static int heap_initialized = 0; static int minimal_free = 0; #endif -static void setup(void) +static void setup(hdrtype_t volatile *start, int size) { - int size = (unsigned int)(&_eheap - &_heap) - HDRSIZE; - - *((hdrtype_t *) hstart) = FREE_BLOCK(size); + *start = FREE_BLOCK(size); #ifdef CONFIG_DEBUG_MALLOC heap_initialized = 1; @@ -88,7 +86,7 @@ static void setup(void) static void *alloc(int len) { hdrtype_t header; - void *ptr = hstart; + hdrtype_t volatile *ptr = (hdrtype_t volatile *) hstart; /* Align the size. */ len = (len + 3) & ~3; @@ -97,12 +95,12 @@ static void *alloc(int len) return (void *)NULL; /* Make sure the region is setup correctly. */ - if (!HAS_MAGIC(*((hdrtype_t *) ptr))) - setup(); + if (!HAS_MAGIC(*ptr)) + setup(ptr, len); /* Find some free space. */ do { - header = *((hdrtype_t *) ptr); + header = *ptr; int size = SIZE(header); if (!HAS_MAGIC(header) || size == 0) { @@ -114,7 +112,7 @@ static void *alloc(int len) if (header & FLAG_FREE) { if (len <= size) { - void *nptr = ptr + (HDRSIZE + len); + hdrtype_t volatile *nptr = ptr + (HDRSIZE + len); int nsize = size - (HDRSIZE + len); /* If there is still room in this block, @@ -124,14 +122,13 @@ static void *alloc(int len) if (nsize > 0) { /* Mark the block as used. */ - *((hdrtype_t *) ptr) = USED_BLOCK(len); + *ptr = USED_BLOCK(len); /* Create a new free block. */ - *((hdrtype_t *) nptr) = - FREE_BLOCK(nsize); + *nptr = FREE_BLOCK(nsize); } else { /* Mark the block as used. */ - *((hdrtype_t *) ptr) = USED_BLOCK(size); + *ptr = USED_BLOCK(size); } return (void *)(ptr + HDRSIZE); @@ -140,7 +137,7 @@ static void *alloc(int len) ptr += HDRSIZE + size; - } while (ptr < hend); + } while (ptr < (hdrtype_t *) hend); /* Nothing available. */ return (void *)NULL;

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A bit of help needed
by Jaspal Dhillon 10 Mar '12

10 Mar '12

Hello , I am currently a 4th year student ( B.Tech in CSE + MS ) in IIIT-H<http://iiit.ac.in/>and chosen field of study for MS is Virtualization. I have been using kvm , qemu and the libvirt library primarily to experiment with cloud frameworks and migration until now. I was going through the coreboot.org and I am definitely interested in it. So wanted to ask couple of things. I have not read the source code yet but tried it out in this way : 1.Checked out latest version of coreboot on 32bit Fedora 15. make config with settings as : MainBoard Vendor : Emulation , Model : Qemu , ROM Size : 256KB , Payload : SeaBIOS make was successful . Since my laptop is a old one and does not have hardware virtualization support , I use a lab pc ( 64 bit Fedora 15 ) for some of my experiments. scp coreboot.rom root@Lab: ; ssh root@Lab 2.qemu-img create disk.img 2500M 3.mkfs.ext2 disk.img 4.mkdir foo ; mv coreboot.rom foo/ ; cd foo ; ln -s coreboot.rom bios.bin 5.Copy some of the other bios files needed by Qemu ( otherwise , Qemu throws a file not found error and exits ): cp -r qemu_path/pc-bios/{keymaps, kvmapic.bin,pxe-e1000.rom,vgabios-cirrus.bin} /root/foo/ 6.qemu-system-x86_64 -L foo/ -hda disk.img -vnc 0:0 -m 512 -serial stdio -cdrom ~/CentOS-5.5-i386-bin-DVD.iso Installation of CentOS ( Minimum installation ) was successful and at the end , it asked me to reboot. When I clicked on reboot option , coreboot got stuck in an infinite loop and I was getting this (in a loop) on the stdio : Changing serial settings was 0/0 now 3/0 In resume (status=0) In 32bit resume Attempting a hard reboot I killed the process and started my vm again without the -cdrom option and it booted up fine. I am not sure if this is a bug or if I am doing something wrong. Can you shed light on it ? I have pasted the serial output at the end of email. ( There are some other 'file not found' errors but qemu + coreboot worked fine without them ). I am absolutely new to coreboot and used it for the first time yesterday but I love and admire it's goal , to replace the proprietary BIOS. Always thought , where's the code of BIOS ? Could you give me some pointers as to where to begin for GSoC or some little hacks that I should attempt out ? I am trying different payloads in the meantime. The initrd and vmlinuz of the CentOS I just installed have sizes of 3.2MB and 1.8MB respectively. If I want to use them ( a kernel payload ) , how should I ? I read about mkelfImage command and also tried it out but the resultant size of linux.elf is ~5MB which exceeds the size of ROM chip , declared in Qemu. Can I use a kernel payload ( any other ) without hacking Qemu ? ( I think not but want to know , if yes , how ) . Thanks , Jaspal PS : Sorry for the duplicate mail. The serial log : [root@divecloud2 jaspal]# qemu-system-x86_64 -L foo/ -hda disk.img -m 512 -serial stdio -vnc 0:0 -cdrom ~/CentOS-5.5-i386-bin-DVD.iso Could not open option rom 'vapic.bin': No such file or directory qemu-system-x86_64: pci_add_option_rom: failed to find romfile "pxe-rtl8139.rom" coreboot-4.0-2087-gc5fc7db Fri Mar 9 04:04:49 IST 2012 starting... Loading image. Searching for fallback/coreboot_ram Check cmos_layout.bin Check fallback/romstage Check fallback/coreboot_ram Stage: loading fallback/coreboot_ram @ 0x100000 (147456 bytes), entry @ 0x100000 Stage: done loading. Jumping to image. coreboot-4.0-2087-gc5fc7db Fri Mar 9 04:04:49 IST 2012 booting... Enumerating buses... Show all devs...Before device enumeration. Root Device: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:01.1: enabled 1 Compare with tree... Root Device: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:01.1: enabled 1 scan_static_bus for Root Device Finding PCI configuration type. PCI: Using configuration type 1 PCI_DOMAIN: 0000 enabled PCI_DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 PCI: 00:00.0 [8086/1237] ops PCI: 00:00.0 [8086/1237] enabled PCI: 00:01.0 [8086/7000] bus ops PCI: 00:01.0 [8086/7000] enabled PCI: 00:01.1 [8086/7010] ops PCI: 00:01.1 [8086/7010] enabled PCI: 00:01.3 [8086/7113] bus ops pwrmgt_enable: gpo default missing in devicetree.cb! PCI: 00:01.3 [8086/7113] enabled PCI: 00:02.0 [1013/00b8] ops PCI: 00:02.0 [1013/00b8] enabled PCI: 00:03.0 [10ec/8139] enabled scan_static_bus for PCI: 00:01.0 scan_static_bus for PCI: 00:01.0 done scan_static_bus for PCI: 00:01.3 scan_static_bus for PCI: 00:01.3 done PCI: pci_scan_bus returning with max=000 scan_static_bus for Root Device done done Setting up VGA for PCI: 00:02.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 PCI_DOMAIN: 0000 read_resources bus 0 link: 0 PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 PCI_DOMAIN: 0000 PCI_DOMAIN: 0000 child on link 0 PCI: 00:00.0 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 PCI_DOMAIN: 0000 resource base fec00000 size 100000 align 0 gran 0 limit ffffffff flags e0000200 index 2 PCI_DOMAIN: 0000 resource base fee00000 size 10000 align 0 gran 0 limit ffffffff flags e0000200 index 3 PCI: 00:00.0 PCI: 00:01.0 PCI: 00:01.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags c0000100 index 1 PCI: 00:01.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags d0000200 index 2 PCI: 00:01.1 PCI: 00:01.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 PCI: 00:01.3 PCI: 00:01.3 resource base e400 size 40 align 0 gran 0 limit ffff flags d0000100 index 1 PCI: 00:01.3 resource base f00 size 10 align 0 gran 0 limit ffff flags d0000100 index 2 PCI: 00:02.0 PCI: 00:02.0 resource base 0 size 2000000 align 25 gran 25 limit ffffffff flags 1200 index 10 PCI: 00:02.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14 PCI: 00:02.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 2200 index 30 PCI: 00:03.0 PCI: 00:03.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10 PCI: 00:03.0 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 14 PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff PCI: 00:03.0 10 * [0x0 - 0xff] io PCI: 00:01.1 20 * [0x400 - 0x40f] io PCI_DOMAIN: 0000 compute_resources_io: base: 410 size: 410 align: 8 gran: 0 limit: ffff done PCI_DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff PCI: 00:02.0 10 * [0x0 - 0x1ffffff] prefmem PCI: 00:02.0 30 * [0x2000000 - 0x200ffff] mem PCI: 00:02.0 14 * [0x2010000 - 0x2010fff] mem PCI: 00:03.0 14 * [0x2011000 - 0x20110ff] mem PCI_DOMAIN: 0000 compute_resources_mem: base: 2011100 size: 2011100 align: 25 gran: 0 limit: ffffffff done avoid_fixed_resources: PCI_DOMAIN: 0000 avoid_fixed_resources:@PCI_DOMAIN: 0000 10000000 limit 0000ffff avoid_fixed_resources:@PCI_DOMAIN: 0000 10000100 limit ffffffff constrain_resources: PCI_DOMAIN: 0000 constrain_resources: PCI: 00:00.0 constrain_resources: PCI: 00:01.0 constrain_resources: PCI: 00:01.1 constrain_resources: PCI: 00:01.3 constrain_resources: PCI: 00:02.0 constrain_resources: PCI: 00:03.0 avoid_fixed_resources2: PCI_DOMAIN: 0000@10000000 limit 0000ffff lim->base 00001000 lim->limit 0000e3ff avoid_fixed_resources2: PCI_DOMAIN: 0000@10000100 limit ffffffff lim->base 00000000 lim->limit febfffff Setting resources... PCI_DOMAIN: 0000 allocate_resources_io: base:1000 size:410 align:8 gran:0 limit:e3ff Assigned: PCI: 00:03.0 10 * [0x1000 - 0x10ff] io Assigned: PCI: 00:01.1 20 * [0x1400 - 0x140f] io PCI_DOMAIN: 0000 allocate_resources_io: next_base: 1410 size: 410 align: 8 gran: 0 done PCI_DOMAIN: 0000 allocate_resources_mem: base:fc000000 size:2011100 align:25 gran:0 limit:febfffff Assigned: PCI: 00:02.0 10 * [0xfc000000 - 0xfdffffff] prefmem Assigned: PCI: 00:02.0 30 * [0xfe000000 - 0xfe00ffff] mem Assigned: PCI: 00:02.0 14 * [0xfe010000 - 0xfe010fff] mem Assigned: PCI: 00:03.0 14 * [0xfe011000 - 0xfe0110ff] mem PCI_DOMAIN: 0000 allocate_resources_mem: next_base: fe011100 size: 2011100 align: 25 gran: 0 done Root Device assign_resources, bus 0 link: 0 Detected 524288 Kbytes (512 MiB) RAM. PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 PCI: 00:01.1 20 <- [0x0000001400 - 0x000000140f] size 0x00000010 gran 0x04 io PCI: 00:02.0 10 <- [0x00fc000000 - 0x00fdffffff] size 0x02000000 gran 0x19 prefmem PCI: 00:02.0 14 <- [0x00fe010000 - 0x00fe010fff] size 0x00001000 gran 0x0c mem PCI: 00:02.0 30 <- [0x00fe000000 - 0x00fe00ffff] size 0x00010000 gran 0x10 romem PCI: 00:03.0 10 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io PCI: 00:03.0 14 <- [0x00fe011000 - 0x00fe0110ff] size 0x00000100 gran 0x08 mem PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device child on link 0 PCI_DOMAIN: 0000 PCI_DOMAIN: 0000 child on link 0 PCI: 00:00.0 PCI_DOMAIN: 0000 resource base 1000 size 410 align 8 gran 0 limit e3ff flags 40040100 index 10000000 PCI_DOMAIN: 0000 resource base fc000000 size 2011100 align 25 gran 0 limit febfffff flags 40040200 index 10000100 PCI_DOMAIN: 0000 resource base fec00000 size 100000 align 0 gran 0 limit ffffffff flags e0000200 index 2 PCI_DOMAIN: 0000 resource base fee00000 size 10000 align 0 gran 0 limit ffffffff flags e0000200 index 3 PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index a PCI_DOMAIN: 0000 resource base c0000 size 1ff40000 align 0 gran 0 limit 0 flags e0004200 index b PCI: 00:00.0 PCI: 00:01.0 PCI: 00:01.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags c0000100 index 1 PCI: 00:01.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags d0000200 index 2 PCI: 00:01.1 PCI: 00:01.1 resource base 1400 size 10 align 4 gran 4 limit e3ff flags 60000100 index 20 PCI: 00:01.3 PCI: 00:01.3 resource base e400 size 40 align 0 gran 0 limit ffff flags d0000100 index 1 PCI: 00:01.3 resource base f00 size 10 align 0 gran 0 limit ffff flags d0000100 index 2 PCI: 00:02.0 PCI: 00:02.0 resource base fc000000 size 2000000 align 25 gran 25 limit febfffff flags 60001200 index 10 PCI: 00:02.0 resource base fe010000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 14 PCI: 00:02.0 resource base fe000000 size 10000 align 16 gran 16 limit febfffff flags 60002200 index 30 PCI: 00:03.0 PCI: 00:03.0 resource base 1000 size 100 align 8 gran 8 limit e3ff flags 60000100 index 10 PCI: 00:03.0 resource base fe011000 size 100 align 8 gran 8 limit febfffff flags 60000200 index 14 Done allocating resources. Enabling resources... PCI: 00:00.0 cmd <- 00 PCI: 00:01.0 cmd <- 00 PCI: 00:01.1 cmd <- 01 PCI: 00:01.3 cmd <- 00 PCI: 00:02.0 cmd <- 03 PCI: 00:03.0 cmd <- 03 done. Initializing devices... Root Device init PCI: 00:00.0 init Keyboard init... setting ethernet Assigning IRQ 11 to 0:3.0 i8259_configure_irq_trigger: current interrupts are 0x0 i8259_configure_irq_trigger: try to set interrupts 0x800 PCI: 00:01.0 init RTC Init PCI: 00:01.1 init IDE: Primary IDE interface: on IDE: Secondary IDE interface: on IDE: Access to legacy IDE ports: off PCI: 00:02.0 init Searching for pci1013,00b8.rom Check cmos_layout.bin Check fallback/romstage Check fallback/coreboot_ram Check fallback/payload Check config Check Could not find file 'pci1013,00b8.rom'. On card, ROM address for PCI: 00:02.0 = fe000000 PCI expansion ROM, signature 0xaa55, INIT size 0x8c00, data ptr 0x0038 PCI ROM image, vendor ID 1013, device ID 00b8, PCI ROM image, Class Code 030000, Code Type 00 Copying VGA ROM Image from fe000000 to 0xc0000, 0x8c00 bytes Real mode stub @00000600: 862 bytes Calling Option ROM... ... Option ROM returned. PCI: 00:03.0 init Searching for pci10ec,8139.rom Check cmos_layout.bin Check fallback/romstage Check fallback/coreboot_ram Check fallback/payload Check config Check Could not find file 'pci10ec,8139.rom'. Devices initialized Show all devs...After init. Root Device: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:01.1: enabled 1 PCI: 00:01.3: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:03.0: enabled 1 Initializing CBMEM area to 0x1fff0000 (65536 bytes) Adding CBMEM entry as no. 1 Moving GDT to 1fff0200...ok High Tables Base is 1fff0000. Copying Interrupt Routing Table to 0x000f0000... done. Adding CBMEM entry as no. 2 Copying Interrupt Routing Table to 0x1fff0400... done. PIRQ table: 128 bytes. Adding CBMEM entry as no. 3 smbios_write_tables: 1fff1400 Root Device (QEMU Mainboard) PCI_DOMAIN: 0000 (QEMU Northbridge) PCI: 00:00.0 (QEMU Northbridge) PCI: 00:01.0 (Intel 82371FB/SB/MX/AB/EB/MB Southbridge) PCI: 00:01.1 (Intel 82371FB/SB/MX/AB/EB/MB Southbridge) PCI: 00:01.3 () PCI: 00:02.0 () PCI: 00:03.0 () SMBIOS tables: 357 bytes. Adding CBMEM entry as no. 4 Writing high table forward entry at 0x00000500 Wrote coreboot table at: 00000500 - 00000518 checksum c3df New low_table_end: 0x00000518 Now going to write high coreboot table at 0x1fff1c00 rom_table_end = 0x1fff1c00 Adjust low_table_end from 0x00000518 to 0x00001000 Adjust rom_table_end from 0x1fff1c00 to 0x20000000 Adding high table area coreboot memory table: 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM 2. 00000000000c0000-000000001ffeffff: RAM 3. 000000001fff0000-000000001fffffff: CONFIGURATION TABLES 4. 00000000ff800000-00000000ffffffff: RESERVED Wrote coreboot table at: 1fff1c00 - 1fff1dd0 checksum fe3d coreboot table: 464 bytes. Multiboot Information structure has been written. 0. FREE SPACE 1fff3c00 0000c400 1. GDT 1fff0200 00000200 2. IRQ TABLE 1fff0400 00001000 3. SMBIOS 1fff1400 00000800 4. COREBOOT 1fff1c00 00002000 Searching for fallback/payload Check cmos_layout.bin Check fallback/romstage Check fallback/coreboot_ram Check fallback/payload Got a payload Loading segment from rom address 0xfffc99b8 code (compression=1) New segment dstaddr 0xe7e04 memsize 0x181fc srcaddr 0xfffc99f0 filesize 0xc21c (cleaned up) New segment addr 0xe7e04 size 0x181fc offset 0xfffc99f0 filesize 0xc21c Loading segment from rom address 0xfffc99d4 Entry Point 0x00000000 Loading Segment: addr: 0x00000000000e7e04 memsz: 0x00000000000181fc filesz: 0x000000000000c21c lb: [0x0000000000100000, 0x0000000000124000) Post relocation: addr: 0x00000000000e7e04 memsz: 0x00000000000181fc filesz: 0x000000000000c21c using LZMA [ 0x000e7e04, 00100000, 0x00100000) <- fffc99f0 dest 000e7e04, end 00100000, bouncebuffer 1ffa8000 Loaded segments Jumping to boot code at fc8b9 entry = 0x000fc8b9 lb_start = 0x00100000 lb_size = 0x00024000 adjust = 0x1fecc000 buffer = 0x1ffa8000 elf_boot_notes = 0x00110538 adjusted_boot_notes = 0x1ffdc538 Start bios (version 1.6.3-20120309_040510-redevil) Found mainboard Emulation QEMU x86 Found CBFS header at 0xfffffc90 Ram Size=0x1fff0000 (0x0000000000000000 high) Relocating init from 0x000e8450 to 0x1ffd57a0 (size 42812) CPU Mhz=2936 Found 6 PCI devices (max PCI bus is 00) Found 1 cpu(s) max supported 1 cpu(s) Copying PIR from 0x1fff0400 to 0x000fdb70 Copying SMBIOS entry point from 0x1fff1400 to 0x000fdb50 Scan for VGA option rom Running option rom at c000:0003 Turning on vga text mode console SeaBIOS (version 1.6.3-20120309_040510-redevil) Found 1 lpt ports Found 1 serial ports ATA controller 1 at 1f0/3f4/0 (irq 14 dev 9) ATA controller 2 at 170/374/0 (irq 15 dev 9) ata0-0: QEMU HARDDISK ATA-7 Hard-Disk (2500 MiBytes) Searching bootorder for: /pci@i0cf8/*@1,1/drive@0/disk@0 DVD/CD [ata1-0: QEMU DVD-ROM ATAPI-4 DVD/CD] Searching bootorder for: /pci@i0cf8/*@1,1/drive@1/disk@0 PS2 keyboard initialized All threads complete. Scan for option roms Press F12 for boot menu. drive 0x000fdb00: PCHS=5079/16/63 translation=large LCHS=634/128/63 s=5120000 ebda moved from 9fc00 to 9f400 Returned 65536 bytes of ZoneHigh e820 map has 6 items: 0: 0000000000000000 - 000000000009f400 = 1 RAM 1: 000000000009f400 - 00000000000a0000 = 2 RESERVED 2: 00000000000f0000 - 0000000000100000 = 2 RESERVED 3: 0000000000100000 - 000000001fff0000 = 1 RAM 4: 000000001fff0000 - 0000000020000000 = 2 RESERVED 5: 00000000ff800000 - 0000000100000000 = 2 RESERVED enter handle_19: NULL Booting from DVD/CD... 3991MB medium detected Booting from 0000:7c00 Changing serial settings was 0/0 now 3/0 In resume (status=0) In 32bit resume Attempting a hard reboot Changing serial settings was 0/0 now 3/0 In resume (status=0) In 32bit resume Attempting a hard reboot Changing serial settings was 0/0 now 3/0 In resume (status=0) In 32bit resume Attempting a hard reboot Changing serial settings was 0/0 now 3/0 In resume (status=0) In 32bit resume Attempting a hard reboot

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Patch set updated for coreboot: 316c124 Unify IO APIC address specification
by Patrick Georgi 10 Mar '12

10 Mar '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/677 -gerrit commit 316c124a98f563fe16721f37f98440b68491a249 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Thu Feb 16 18:54:37 2012 +0100 Unify IO APIC address specification Some places still hardcoded the address instead of using IO_APIC_ADDR. Change-Id: I3941c1ff62972ce56a5bc466eab7134f901773d3 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/arch/x86/include/arch/ioapic.h | 2 +- src/mainboard/amd/torpedo/platform_cfg.h | 2 +- src/mainboard/iwave/iWRainbowG6/mptable.c | 2 +- src/northbridge/intel/i945/acpi/hostbridge.asl | 3 ++- src/northbridge/intel/sch/acpi/hostbridge.asl | 3 ++- src/southbridge/amd/cimx/sb700/lpc.c | 5 +++-- src/southbridge/amd/cimx/sb800/lpc.c | 5 +++-- src/southbridge/amd/cimx/sb900/lpc.c | 5 +++-- src/southbridge/amd/sb800/lpc.c | 4 ++-- src/southbridge/amd/sb800/sm.c | 8 +++----- src/southbridge/intel/sch/lpc.c | 5 +++-- 11 files changed, 24 insertions(+), 20 deletions(-) diff --git a/src/arch/x86/include/arch/ioapic.h b/src/arch/x86/include/arch/ioapic.h index 5d7e196..01fd753 100644 --- a/src/arch/x86/include/arch/ioapic.h +++ b/src/arch/x86/include/arch/ioapic.h @@ -23,6 +23,7 @@ #define IO_APIC_ADDR 0xfec00000 #define IO_APIC_INTERRUPTS 24 +#ifndef __ACPI__ #define ALL (0xff << 24) #define NONE (0) #define DISABLED (1 << 16) @@ -38,7 +39,6 @@ #define SMI (2 << 8) #define INT (1 << 8) -#ifndef __ACPI__ void setup_ioapic(u32 ioapic_base, u8 ioapic_id); void clear_ioapic(u32 ioapic_base); #endif diff --git a/src/mainboard/amd/torpedo/platform_cfg.h b/src/mainboard/amd/torpedo/platform_cfg.h index d97d034..cf31c6a 100644 --- a/src/mainboard/amd/torpedo/platform_cfg.h +++ b/src/mainboard/amd/torpedo/platform_cfg.h @@ -137,7 +137,7 @@ * @section WatchDogTimerBase */ // #ifndef WATCHDOG_TIMER_BASE_ADDRESS -// #define WATCHDOG_TIMER_BASE_ADDRESS 0xFEC00000 +// #define WATCHDOG_TIMER_BASE_ADDRESS IO_APIC_ADDR // #endif /** diff --git a/src/mainboard/iwave/iWRainbowG6/mptable.c b/src/mainboard/iwave/iWRainbowG6/mptable.c index 953f16a..87de022 100644 --- a/src/mainboard/iwave/iWRainbowG6/mptable.c +++ b/src/mainboard/iwave/iWRainbowG6/mptable.c @@ -34,7 +34,7 @@ void *smp_write_config_table(void *v) smp_write_processors(mc); mptable_write_buses(mc, NULL, &isa_bus); - smp_write_ioapic(mc, 2, 0x20, 0xfec00000); + smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR); { device_t dev; struct resource *res; diff --git a/src/northbridge/intel/i945/acpi/hostbridge.asl b/src/northbridge/intel/i945/acpi/hostbridge.asl index a76d8e2..8dcadd7 100644 --- a/src/northbridge/intel/i945/acpi/hostbridge.asl +++ b/src/northbridge/intel/i945/acpi/hostbridge.asl @@ -19,6 +19,7 @@ * MA 02110-1301 USA */ +#include <arch/ioapic.h> Name(_HID,EISAID("PNP0A08")) // PCIe Name(_CID,EISAID("PNP0A03")) // PCI @@ -211,7 +212,7 @@ Method (_CRS, 0, Serialized) DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x00000000, 0xfebfffff, 0x00000000, - 0xfec00000,,, PM01) + IO_APIC_ADDR,,, PM01) // TPM Area (0xfed40000-0xfed44fff) DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, diff --git a/src/northbridge/intel/sch/acpi/hostbridge.asl b/src/northbridge/intel/sch/acpi/hostbridge.asl index 7e92a0e..44a8be0 100644 --- a/src/northbridge/intel/sch/acpi/hostbridge.asl +++ b/src/northbridge/intel/sch/acpi/hostbridge.asl @@ -19,6 +19,7 @@ * MA 02110-1301 USA */ +#include <arch/ioapic.h> Name(_HID,EISAID("PNP0A08")) // PCIe Name(_CID,EISAID("PNP0A03")) // PCI @@ -211,7 +212,7 @@ Method (_CRS, 0, Serialized) DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x00000000, 0xfebfffff, 0x00000000, - 0xfec00000,,, PM01) + IO_APIC_ADDR,,, PM01) // TPM Area (0xfed40000-0xfed44fff) DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, diff --git a/src/southbridge/amd/cimx/sb700/lpc.c b/src/southbridge/amd/cimx/sb700/lpc.c index e43193a..7157a55 100644 --- a/src/southbridge/amd/cimx/sb700/lpc.c +++ b/src/southbridge/amd/cimx/sb700/lpc.c @@ -21,6 +21,7 @@ #include "lpc.h" #include <bitops.h> #include <arch/io.h> +#include <arch/ioapic.h> #include <console/console.h> /* printk */ #include <cbmem.h> @@ -61,8 +62,8 @@ void lpc_read_resources(device_t dev) res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - res = new_resource(dev, 3); /* IOAPIC */ - res->base = 0xfec00000; + res = new_resource(dev, 3); + res->base = IO_APIC_ADDR; res->size = 0x00001000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; diff --git a/src/southbridge/amd/cimx/sb800/lpc.c b/src/southbridge/amd/cimx/sb800/lpc.c index bc643b5..856b8b3 100644 --- a/src/southbridge/amd/cimx/sb800/lpc.c +++ b/src/southbridge/amd/cimx/sb800/lpc.c @@ -19,6 +19,7 @@ #include <console/console.h> #include <device/pci.h> +#include <arch/ioapic.h> #include "lpc.h" @@ -45,8 +46,8 @@ void lpc_read_resources(device_t dev) res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - res = new_resource(dev, 3); /* IOAPIC */ - res->base = 0xfec00000; + res = new_resource(dev, 3); + res->base = IO_APIC_ADDR; res->size = 0x00001000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; diff --git a/src/southbridge/amd/cimx/sb900/lpc.c b/src/southbridge/amd/cimx/sb900/lpc.c index 48bfe36..9873d37 100644 --- a/src/southbridge/amd/cimx/sb900/lpc.c +++ b/src/southbridge/amd/cimx/sb900/lpc.c @@ -20,6 +20,7 @@ #include <device/pci.h> #include "lpc.h" #include <console/console.h> /* printk */ +#include <arch/ioapic.h> void lpc_read_resources(device_t dev) @@ -45,8 +46,8 @@ void lpc_read_resources(device_t dev) res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - res = new_resource(dev, 3); /* IOAPIC */ - res->base = 0xfec00000; + res = new_resource(dev, 3); + res->base = IO_APIC_ADDR; res->size = 0x00001000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; diff --git a/src/southbridge/amd/sb800/lpc.c b/src/southbridge/amd/sb800/lpc.c index 6b72a62..4e2031f 100644 --- a/src/southbridge/amd/sb800/lpc.c +++ b/src/southbridge/amd/sb800/lpc.c @@ -91,8 +91,8 @@ static void sb800_lpc_read_resources(device_t dev) res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - //res = new_resource(dev, 3); /* IOAPIC */ - //res->base = 0xfec00000; + //res = new_resource(dev, 3); + //res->base = IO_APIC_ADDR; //res->size = 0x00001000; //res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; diff --git a/src/southbridge/amd/sb800/sm.c b/src/southbridge/amd/sb800/sm.c index 9347c42..50a8f0b 100644 --- a/src/southbridge/amd/sb800/sm.c +++ b/src/southbridge/amd/sb800/sm.c @@ -84,16 +84,14 @@ static void sm_init(device_t dev) { u8 byte; - u32 ioapic_base; printk(BIOS_INFO, "sm_init().\n"); - ioapic_base = 0xFEC00000;//pci_read_config32(dev, 0x74) & (0xffffffe0); /* some like mem resource, but does not have enable bit */ /* Don't rename APIC ID */ /* TODO: We should call setup_ioapic() here. But kernel hangs if cpu is K8. * We need to check out why and change back. */ - clear_ioapic(ioapic_base); - //setup_ioapic(ioapic_base, 0); + clear_ioapic(IO_APIC_ADDR); + //setup_ioapic(IO_APIC_ADDR, 0); /* enable serial irq */ byte = pm_ioread(0x54); @@ -277,7 +275,7 @@ static void sb800_sm_read_resources(device_t dev) /* apic */ res = new_resource(dev, 0x74); - res->base = 0xfec00000; + res->base = IO_APIC_ADDR; res->size = 256 * 0x10; res->limit = 0xFEFFFFFUL; /* res->base + res->size -1; */ res->align = 8; diff --git a/src/southbridge/intel/sch/lpc.c b/src/southbridge/intel/sch/lpc.c index ab180bb..977e01b 100644 --- a/src/southbridge/intel/sch/lpc.c +++ b/src/southbridge/intel/sch/lpc.c @@ -23,6 +23,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <arch/io.h> +#include <arch/ioapic.h> #include "chip.h" /* SCH LPC defines */ @@ -164,8 +165,8 @@ static void sch_lpc_read_resources(device_t dev) res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - res = new_resource(dev, 3); /* IOAPIC */ - res->base = 0xfec00000; + res = new_resource(dev, 3); + res->base = IO_APIC_ADDR; res->size = 0x00001000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; }

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Patch merged into coreboot/master: 2fd6df0 If the memory mapped UART isn't present, leave it out of the cb tables.
by gerrit＠coreboot.org 10 Mar '12

10 Mar '12

the following patch was just integrated into master: commit 2fd6df0f261f0f9d587de15cb9e5861c3ff6811a Author: Gabe Black <gabeblack(a)google.com> Date: Wed Oct 5 01:57:03 2011 -0700 If the memory mapped UART isn't present, leave it out of the cb tables. This way u-boot won't try to use a UART that isn't plugged in. Change-Id: I9a3a0d074dd03add8afbd4dad836c4c6a05abe6f Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Fri Mar 9 09:59:02 2012, giving +2 See http://review.coreboot.org/729 for details. -gerrit

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Patch merged into coreboot/master: c7dc9bc tell superiotool about the ITE 8772
by gerrit＠coreboot.org 10 Mar '12

10 Mar '12

the following patch was just integrated into master: commit c7dc9bcbbc96dd7ef0f28cc6bdec4c4c4057dc9c Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Oct 25 17:12:53 2011 +0000 tell superiotool about the ITE 8772 no dumping yet Change-Id: I4e687ca816c8d6d1c95255b0abf6a19513e23f86 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> See http://review.coreboot.org/734 for details. -gerrit

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coreboot March 2012