coreboot March 2012

coreboot@coreboot.org

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Patch merged into coreboot/master: 7e4ae17 Add helper function to find a Local APIC by ID in the device tree.
by gerrit＠coreboot.org 09 Mar '12

09 Mar '12

the following patch was just integrated into master: commit 7e4ae17266e087e02ba9cdd4a3d909549b518a91 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Jul 18 10:41:36 2011 -0700 Add helper function to find a Local APIC by ID in the device tree. Change-Id: Ie2d7d8e1f647a0c92d2de09e32454fbea688b1e7 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Build-Tested: build bot (Jenkins) at Fri Mar 9 08:29:25 2012, giving +1 See http://review.coreboot.org/695 for details. -gerrit

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Patch merged into coreboot/master: 74cc92c Don't try to compute I/O for empty sub buses.
by gerrit＠coreboot.org 09 Mar '12

09 Mar '12

the following patch was just integrated into master: commit 74cc92c58451be4592219e5e70b894484a1f761e Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed May 11 15:57:07 2011 -0700 Don't try to compute I/O for empty sub buses. I am not sure if the sub bus being 0 is a problem, or if the assumption there has to be at least one non empty link is just wrong. It certainly does not hurt to add a small consistency check in either case. Change-Id: I098446deef96a8baae26a7ca1ddd96e626a06dc5 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Build-Tested: build bot (Jenkins) at Fri Mar 9 09:00:47 2012, giving +1 See http://review.coreboot.org/693 for details. -gerrit

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Re: [coreboot] Coreboot support for ASUS M5 A99X EVO ?
by Marc Jones 09 Mar '12

09 Mar '12

Hi Bernhard, Sorry for the late reply, I had missed this email chain. On Wed, Feb 22, 2012 at 4:51 AM, Bernhard Urban <lewurm(a)gmail.com> wrote: > hi, > > so finally, I spent some time on porting coreboot to the asus board > "m5a99x evo". http://www.asus.com/Motherboards/AMD_AM3Plus/M5A99X_EVO/ > I was equipped with three DIP chips and decided to use my target > machine also for developing. I had also set up a quite complicated > configuration for serial debugging, as I didn't own a second machine > with a rs232 board. Although the first try (just flash the "m5a88-v" > configuration) showed some output :-) ( http://tinyurl.com/89a33m5 ), > the build cycle was a pain in the ass. > (0) building coreboot (takes some seconds...) > (1) flashing the chip (~30seconds, without verifying) > (2) reboot (~20sec) > (3) starting coreboot and analyse the output (between 1sec and some minutes ;-)) > (4) switch chip with vendor bios on it (some seconds) > (5) booting vendor bios and linux (35sec + 11sec. yes, the vendor > firmware takes three times longer than linux + x11. BOAR ;-)) > (6) switch chip again. > > So I was looking for alternatives. I remembered the ft2232 stuff by > Uwe. I had it anyway on my "order it some day"-list, so it was the > right time ;-) > In the meanwhile, I refit my old machine with a new hdd and a > reasoneable graphic card. Luckily, it has also a serial port :-) > I was a bit afraid of building a programmer (the ft2232 thingy) as I'm > not really the hardware guy. However, the first dump was successful. > Writing was working too. I was impressed :-) Thanks to Uwe at this > point! > > So the build cycle is more convenient now: > (0) building coreboot (takes longer than on my new machine, but it's okay ;-)) using " make -j n", where n is the number of cores will speed up the build. > (1) flash the chip with the ft2232 thingy (~30 seconds, without verifying) > (2) put the chip onto the mainboard > (3) start machine and watch serial output > > all in all, it take like one minute to test one build. nice! > This is good progress! > > So, now I was able to do some serious coreboot hacking. I started from > the "m5a88-v" port. What I did: > - Changed the southbridge from "SB800" to "SB900" > - Adapted some compile-breaks due to this change. > - hardcoded some pci device instead of locating it @ early.c -> ohai > ramstage :-) > - again, some pci related change/hack (aborting the enumeration > earlier). I didn't really understand what I did here, I just figured > out it hangs here (could be related with the quirk below). After that > -> OHAI SEABIOS! > > I was very happy ;) However, SeaBIOS itself hang somewhere. > In the meanwhile, Kerry pushed RD890 patches, which seemed to be more > appropriate for my board (i used RS780 code so far, hence the ugly > hacks mentioned above I guess). So I used them, and it felt much > cleaner immediately. The payload was still loading -> nice. > > After that, I investigated a bit what the problem is with SeaBIOS. At > this moment, it hanged after printing "Relocating init from 0x000e8450 > to 0xcffd57a0 (size 42812)" (see http://tinyurl.com/78evzex ). I > looked into the SeaBIOS code and found out, that you can disable > relocation. So I did. > > The result was a bit more confusing. http://tinyurl.com/7uh8xty > The output get distorted (which seems not to be deterministically, > http://tinyurl.com/6opakzl ) and something issues a soft reset (but > not everytime...). Eventually I gave up at this point (had to do other > stuff anyway). I guess it is something wrong with RAM initialization > as relocation in higher memory regions doesn't work. Also, the graphic > card isn't found on the pci bus as the RD890 code inlcudes a quirk > which "disable all pcie bridges" aka > `sr56x0_rd890_disable_pcie_bridge()'. According to `lspci' (with > vendor bios), the graphic card is on bus 1, so this seem reasonably. > @Kerry: is there some way to enable it again after "early"? > > > my WIP branch is available here (please tell me if you pull from it, > because atm I'm rebasing stuff on it and using `git push -f' to > overwrite it...): > http://wien.tomnetworks.com/gitweb/?p=coreboot.git;a=shortlog;h=refs/heads/… > > full logs (including config and rom images) are available here: > http://wien.tomnetworks.com/gitweb/?p=cbimages.git;a=tree > > > Some questions: > - What does "CIMX" stands for? I grep'd my #coreboot logs for it. One > guy asked that already, but he didn't get an answer :-/ CIMx is the AMD southbridge vendor code. It is similar to AGESA, and has wrappers in coreboot that call into it. > - What's the best/easiest way to verify if RAM init was successful? RAM is mostly working iouf you get this far into SeaBIOS. You can run a RAM test, but you probably just want to check that the top of memory is where you expect and test reads and writes there. > - I think it would be nice to have an entry on the wiki page for this > board. How I get an account? Stefan? :-) This would be great. Catch Stepan or other admins in #coreboot, or email him directly. > > I appreciate any comment, I know resources are short :-( > anyways, it was fun and exciting so far :-) thanks! > > regards, > bernhard > It sounds like you are making very good progress. You are hitting normal system porting issues. I see that you are using the "old" AMD fam10 init code. There is no problem with that, but it isn't being actively developed. You might consider switching to the new AGESA wrappers. Take a look at the supermicro/h8scm and other AGESA mainboards in the amd directory to see the new wrappers. Marc > On Wed, Nov 23, 2011 at 10:29 PM, Bernhard Urban <lewurm(a)gmail.com> wrote: >> Hi Chris, >> >> I reported flashrom compatibility here: >> http://www.flashrom.org/pipermail/flashrom/2011-October/008152.html >> >> Regarding coreboot support: I'll try to port coreboot to this board. I >> already have two additional flashchips and at the moment I'm waiting >> for a serial port connector. I don't know how long it'll talke to port >> it, but don't except anything useful in less than three months, since >> I'm new to coreboot (and lazy :-)) >> >> >> Bernhard >> >> On Sat, Nov 19, 2011 at 6:33 PM, Christopher Huang-Leaver >> <zeonglow(a)googlemail.com> wrote: >>> Hello, >>> I noticed earlier versions of this board are fully supported, but not this >>> one. >>> I have attached the output of, lspci, flashrom and dmidecode, if that is >>> any use to anyone. >>> The spec sheet is easy to find by typing ASUS M5 A99X into Google. The >>> board does have a neat feature of being able to flash the BIOS from within >>> the BIOS menu, which I have already used to update it. >>> Many thanks >>> Chris > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot -- http://se-eng.com

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Patch merged into coreboot/master: a2eaa4f OXPCIe: Reinitialize UART after pci_dev_set_resources()
by gerrit＠coreboot.org 09 Mar '12

09 Mar '12

the following patch was just integrated into master: commit a2eaa4fb7bb98f171d54523f9af06a0794f14013 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue May 10 12:54:56 2011 -0700 OXPCIe: Reinitialize UART after pci_dev_set_resources() ... and only pull in early init code if the OXPCIe is used for console. Change-Id: I01feca3b9e8376a75c17554ba1bd200d523dff8d Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Build-Tested: build bot (Jenkins) at Fri Mar 9 08:47:32 2012, giving +1 See http://review.coreboot.org/692 for details. -gerrit

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Patch merged into coreboot/master: fa84bc2 move console includes to central console/console.h
by gerrit＠coreboot.org 09 Mar '12

09 Mar '12

the following patch was just integrated into master: commit fa84bc28c757a27cf768989db805e5636219366c Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue May 10 10:46:41 2011 -0700 move console includes to central console/console.h Because it's included everywhere anyways. Change-Id: I99a9e6edac08df57c50ef3a706fdbd395cad0abc Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Build-Tested: build bot (Jenkins) at Fri Mar 2 23:45:56 2012, giving +1 See http://review.coreboot.org/691 for details. -gerrit

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Patch merged into coreboot/master: e3d53a2 Add support for the Startech PEX1XS1PMINI
by gerrit＠coreboot.org 09 Mar '12

09 Mar '12

the following patch was just integrated into master: commit e3d53a2242c3c6dd522c58ad05a74847be80fa84 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon May 9 15:19:29 2011 -0700 Add support for the Startech PEX1XS1PMINI It has a smaller footprint than the already supported MPEX2S952 Change-Id: Ie36b67f9628882d516ca34ff164f0e8918955a5b Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Tested-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-by: Duncan Laurie <dlaurie(a)google.com> Build-Tested: build bot (Jenkins) at Fri Mar 2 23:30:41 2012, giving +1 See http://review.coreboot.org/690 for details. -gerrit

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Patch merged into coreboot/master: 463a858 Don't run any Option ROMs stored outside of the system flash
by gerrit＠coreboot.org 09 Mar '12

09 Mar '12

the following patch was just integrated into master: commit 463a8587844cb9efd236c4e7b3bb52e94756d0c8 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Oct 6 16:47:51 2011 -0700 Don't run any Option ROMs stored outside of the system flash Right now coreboot only executes VGA Option ROMs. However, this is not good enough. For security reasons we want to execute only Option ROMs stored in our r/o CBFS. This patch adds a new option to disable execution of arbitrary Option ROMs. Also fix the capitalization of Option ROM in src/devices/Kconfig Change-Id: I485291c06ec5cd1f875357401831fe32ccfc5f2f Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Build-Tested: build bot (Jenkins) at Fri Mar 9 17:25:23 2012, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Fri Mar 9 18:33:10 2012, giving +2 Reviewed-By: Mathias Krause <minipli(a)googlemail.com> at Fri Mar 9 20:01:31 2012, giving +2 See http://review.coreboot.org/730 for details. -gerrit

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Patch merged into coreboot/master: daf3d89 Add an implementation for the memchr library function
by gerrit＠coreboot.org 09 Mar '12

09 Mar '12

the following patch was just integrated into master: commit daf3d89987751a461bc8d1db86e13644acc46047 Author: Gabe Black <gabeblack(a)google.com> Date: Fri Sep 16 02:18:56 2011 -0700 Add an implementation for the memchr library function Change-Id: Icded479d246f7cce8a3d2154c69f75178fa513e1 Signed-off-by: Gabe Black <gabeblack(a)google.com> Build-Tested: build bot (Jenkins) at Fri Mar 9 06:35:33 2012, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Thu Mar 8 22:37:07 2012, giving +1 Reviewed-By: Mathias Krause <minipli(a)googlemail.com> at Fri Mar 9 20:00:53 2012, giving +2 See http://review.coreboot.org/708 for details. -gerrit

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Gsoc 12
by Jaspal Dhillon 09 Mar '12

09 Mar '12

Hello , I am currently a 4th year student ( B.Tech in CSE + MS ) in IIIT-H<http://iiit.ac.in/>and chosen field of study for MS is Virtualization. I have been using kvm , qemu and the libvirt library primarily to experiment with cloud frameworks and migration until now. I was going through the coreboot.org and I am definitely interested in it. So wanted to ask couple of things. I have not read the source code yet but tried it out in this way : 1.Checked out latest version of coreboot on 32bit Fedora 15. make config with settings as : MainBoard Vendor : Emulation , Model : Qemu , ROM Size : 256KB , Payload : SeaBIOS make was successful . Since my laptop is an old one and does not have hardware virtualization support , I use a lab pc ( 64 bit Fedora 15 ) for some of my experiments. scp coreboot.rom root@Lab: ; ssh root@Lab 2.qemu-img create disk.img 2500M 3.mkfs.ext2 disk.img 4.mkdir foo ; mv coreboot.rom foo/ ; cd foo ; ln -s coreboot.rom bios.bin 5.Copy some of the other bios files needed by Qemu ( otherwise , Qemu throws a file not found error and exits ): cp -r qemu_path/pc-bios/{keymaps,kvmapic.bin,pxe-e1000.rom,vgabios-cirrus.bin} /root/foo/ 6.qemu-system-x86_64 -L foo/ -hda disk.img -vnc 0:0 -m 512 -serial stdio -cdrom ~/CentOS-5.5-i386-bin-DVD.iso Installation of CentOS ( Minimum installation ) was successful and at the end , it asked me to reboot. When I clicked on reboot option , coreboot got stuck in an infinite loop and I was getting this (in a loop) on the stdio : Changing serial settings was 0/0 now 3/0 In resume (status=0) In 32bit resume Attempting a hard reboot I killed the process and started my vm again without the -cdrom option and it booted up fine. I am not sure if this is a bug or if I am doing something wrong. Can you shed light on it ? I have pasted the serial output at the end of email. ( There are some other 'file not found' errors but qemu + coreboot worked fine without them ). I am absolutely new to coreboot and used it for the first time today but I love and admire it's goal , to replace the proprietary BIOS. Always thought , where's the code of BIOS ? Could you give me some pointers as to where to begin for GSoC or some little hacks that I should attempt out ? I am trying different payloads in the meantime. The initrd and vmlinuz of the CentOS I just installed have sizes of 3.2MB and 1.8MB respectively. If I want to use them ( a kernel payload ) , how should I ? I read about mkelfImage command and also tried it out but the resultant size of linux.elf is ~5MB which exceeds the size of ROM chip , declared in Qemu. Can I use a kernel payload ( any other OS ) without hacking Qemu ? ( I think not but want to know , if yes , how ) . Thanks , Jaspal The complete serial log : [root@divecloud2 jaspal]# qemu-system-x86_64 -L foo/ -hda disk.img -m 512 -serial stdio -vnc 0:0 -cdrom ~/CentOS-5.5-i386-bin-DVD.iso Could not open option rom 'vapic.bin': No such file or directory qemu-system-x86_64: pci_add_option_rom: failed to find romfile "pxe-rtl8139.rom" coreboot-4.0-2087-gc5fc7db Fri Mar 9 04:04:49 IST 2012 starting... Loading image. Searching for fallback/coreboot_ram Check cmos_layout.bin Check fallback/romstage Check fallback/coreboot_ram Stage: loading fallback/coreboot_ram @ 0x100000 (147456 bytes), entry @ 0x100000 Stage: done loading. Jumping to image. coreboot-4.0-2087-gc5fc7db Fri Mar 9 04:04:49 IST 2012 booting... Enumerating buses... Show all devs...Before device enumeration. Root Device: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:01.1: enabled 1 Compare with tree... Root Device: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:01.1: enabled 1 scan_static_bus for Root Device Finding PCI configuration type. PCI: Using configuration type 1 PCI_DOMAIN: 0000 enabled PCI_DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 PCI: 00:00.0 [8086/1237] ops PCI: 00:00.0 [8086/1237] enabled PCI: 00:01.0 [8086/7000] bus ops PCI: 00:01.0 [8086/7000] enabled PCI: 00:01.1 [8086/7010] ops PCI: 00:01.1 [8086/7010] enabled PCI: 00:01.3 [8086/7113] bus ops pwrmgt_enable: gpo default missing in devicetree.cb! PCI: 00:01.3 [8086/7113] enabled PCI: 00:02.0 [1013/00b8] ops PCI: 00:02.0 [1013/00b8] enabled PCI: 00:03.0 [10ec/8139] enabled scan_static_bus for PCI: 00:01.0 scan_static_bus for PCI: 00:01.0 done scan_static_bus for PCI: 00:01.3 scan_static_bus for PCI: 00:01.3 done PCI: pci_scan_bus returning with max=000 scan_static_bus for Root Device done done Setting up VGA for PCI: 00:02.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 PCI_DOMAIN: 0000 read_resources bus 0 link: 0 PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 PCI_DOMAIN: 0000 PCI_DOMAIN: 0000 child on link 0 PCI: 00:00.0 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 PCI_DOMAIN: 0000 resource base fec00000 size 100000 align 0 gran 0 limit ffffffff flags e0000200 index 2 PCI_DOMAIN: 0000 resource base fee00000 size 10000 align 0 gran 0 limit ffffffff flags e0000200 index 3 PCI: 00:00.0 PCI: 00:01.0 PCI: 00:01.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags c0000100 index 1 PCI: 00:01.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags d0000200 index 2 PCI: 00:01.1 PCI: 00:01.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 PCI: 00:01.3 PCI: 00:01.3 resource base e400 size 40 align 0 gran 0 limit ffff flags d0000100 index 1 PCI: 00:01.3 resource base f00 size 10 align 0 gran 0 limit ffff flags d0000100 index 2 PCI: 00:02.0 PCI: 00:02.0 resource base 0 size 2000000 align 25 gran 25 limit ffffffff flags 1200 index 10 PCI: 00:02.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14 PCI: 00:02.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 2200 index 30 PCI: 00:03.0 PCI: 00:03.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10 PCI: 00:03.0 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 14 PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff PCI: 00:03.0 10 * [0x0 - 0xff] io PCI: 00:01.1 20 * [0x400 - 0x40f] io PCI_DOMAIN: 0000 compute_resources_io: base: 410 size: 410 align: 8 gran: 0 limit: ffff done PCI_DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff PCI: 00:02.0 10 * [0x0 - 0x1ffffff] prefmem PCI: 00:02.0 30 * [0x2000000 - 0x200ffff] mem PCI: 00:02.0 14 * [0x2010000 - 0x2010fff] mem PCI: 00:03.0 14 * [0x2011000 - 0x20110ff] mem PCI_DOMAIN: 0000 compute_resources_mem: base: 2011100 size: 2011100 align: 25 gran: 0 limit: ffffffff done avoid_fixed_resources: PCI_DOMAIN: 0000 avoid_fixed_resources:@PCI_DOMAIN: 0000 10000000 limit 0000ffff avoid_fixed_resources:@PCI_DOMAIN: 0000 10000100 limit ffffffff constrain_resources: PCI_DOMAIN: 0000 constrain_resources: PCI: 00:00.0 constrain_resources: PCI: 00:01.0 constrain_resources: PCI: 00:01.1 constrain_resources: PCI: 00:01.3 constrain_resources: PCI: 00:02.0 constrain_resources: PCI: 00:03.0 avoid_fixed_resources2: PCI_DOMAIN: 0000@10000000 limit 0000ffff lim->base 00001000 lim->limit 0000e3ff avoid_fixed_resources2: PCI_DOMAIN: 0000@10000100 limit ffffffff lim->base 00000000 lim->limit febfffff Setting resources... PCI_DOMAIN: 0000 allocate_resources_io: base:1000 size:410 align:8 gran:0 limit:e3ff Assigned: PCI: 00:03.0 10 * [0x1000 - 0x10ff] io Assigned: PCI: 00:01.1 20 * [0x1400 - 0x140f] io PCI_DOMAIN: 0000 allocate_resources_io: next_base: 1410 size: 410 align: 8 gran: 0 done PCI_DOMAIN: 0000 allocate_resources_mem: base:fc000000 size:2011100 align:25 gran:0 limit:febfffff Assigned: PCI: 00:02.0 10 * [0xfc000000 - 0xfdffffff] prefmem Assigned: PCI: 00:02.0 30 * [0xfe000000 - 0xfe00ffff] mem Assigned: PCI: 00:02.0 14 * [0xfe010000 - 0xfe010fff] mem Assigned: PCI: 00:03.0 14 * [0xfe011000 - 0xfe0110ff] mem PCI_DOMAIN: 0000 allocate_resources_mem: next_base: fe011100 size: 2011100 align: 25 gran: 0 done Root Device assign_resources, bus 0 link: 0 Detected 524288 Kbytes (512 MiB) RAM. PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 PCI: 00:01.1 20 <- [0x0000001400 - 0x000000140f] size 0x00000010 gran 0x04 io PCI: 00:02.0 10 <- [0x00fc000000 - 0x00fdffffff] size 0x02000000 gran 0x19 prefmem PCI: 00:02.0 14 <- [0x00fe010000 - 0x00fe010fff] size 0x00001000 gran 0x0c mem PCI: 00:02.0 30 <- [0x00fe000000 - 0x00fe00ffff] size 0x00010000 gran 0x10 romem PCI: 00:03.0 10 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io PCI: 00:03.0 14 <- [0x00fe011000 - 0x00fe0110ff] size 0x00000100 gran 0x08 mem PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device child on link 0 PCI_DOMAIN: 0000 PCI_DOMAIN: 0000 child on link 0 PCI: 00:00.0 PCI_DOMAIN: 0000 resource base 1000 size 410 align 8 gran 0 limit e3ff flags 40040100 index 10000000 PCI_DOMAIN: 0000 resource base fc000000 size 2011100 align 25 gran 0 limit febfffff flags 40040200 index 10000100 PCI_DOMAIN: 0000 resource base fec00000 size 100000 align 0 gran 0 limit ffffffff flags e0000200 index 2 PCI_DOMAIN: 0000 resource base fee00000 size 10000 align 0 gran 0 limit ffffffff flags e0000200 index 3 PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index a PCI_DOMAIN: 0000 resource base c0000 size 1ff40000 align 0 gran 0 limit 0 flags e0004200 index b PCI: 00:00.0 PCI: 00:01.0 PCI: 00:01.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags c0000100 index 1 PCI: 00:01.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags d0000200 index 2 PCI: 00:01.1 PCI: 00:01.1 resource base 1400 size 10 align 4 gran 4 limit e3ff flags 60000100 index 20 PCI: 00:01.3 PCI: 00:01.3 resource base e400 size 40 align 0 gran 0 limit ffff flags d0000100 index 1 PCI: 00:01.3 resource base f00 size 10 align 0 gran 0 limit ffff flags d0000100 index 2 PCI: 00:02.0 PCI: 00:02.0 resource base fc000000 size 2000000 align 25 gran 25 limit febfffff flags 60001200 index 10 PCI: 00:02.0 resource base fe010000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 14 PCI: 00:02.0 resource base fe000000 size 10000 align 16 gran 16 limit febfffff flags 60002200 index 30 PCI: 00:03.0 PCI: 00:03.0 resource base 1000 size 100 align 8 gran 8 limit e3ff flags 60000100 index 10 PCI: 00:03.0 resource base fe011000 size 100 align 8 gran 8 limit febfffff flags 60000200 index 14 Done allocating resources. Enabling resources... PCI: 00:00.0 cmd <- 00 PCI: 00:01.0 cmd <- 00 PCI: 00:01.1 cmd <- 01 PCI: 00:01.3 cmd <- 00 PCI: 00:02.0 cmd <- 03 PCI: 00:03.0 cmd <- 03 done. Initializing devices... Root Device init PCI: 00:00.0 init Keyboard init... setting ethernet Assigning IRQ 11 to 0:3.0 i8259_configure_irq_trigger: current interrupts are 0x0 i8259_configure_irq_trigger: try to set interrupts 0x800 PCI: 00:01.0 init RTC Init PCI: 00:01.1 init IDE: Primary IDE interface: on IDE: Secondary IDE interface: on IDE: Access to legacy IDE ports: off PCI: 00:02.0 init Searching for pci1013,00b8.rom Check cmos_layout.bin Check fallback/romstage Check fallback/coreboot_ram Check fallback/payload Check config Check Could not find file 'pci1013,00b8.rom'. On card, ROM address for PCI: 00:02.0 = fe000000 PCI expansion ROM, signature 0xaa55, INIT size 0x8c00, data ptr 0x0038 PCI ROM image, vendor ID 1013, device ID 00b8, PCI ROM image, Class Code 030000, Code Type 00 Copying VGA ROM Image from fe000000 to 0xc0000, 0x8c00 bytes Real mode stub @00000600: 862 bytes Calling Option ROM... ... Option ROM returned. PCI: 00:03.0 init Searching for pci10ec,8139.rom Check cmos_layout.bin Check fallback/romstage Check fallback/coreboot_ram Check fallback/payload Check config Check Could not find file 'pci10ec,8139.rom'. Devices initialized Show all devs...After init. Root Device: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:01.1: enabled 1 PCI: 00:01.3: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:03.0: enabled 1 Initializing CBMEM area to 0x1fff0000 (65536 bytes) Adding CBMEM entry as no. 1 Moving GDT to 1fff0200...ok High Tables Base is 1fff0000. Copying Interrupt Routing Table to 0x000f0000... done. Adding CBMEM entry as no. 2 Copying Interrupt Routing Table to 0x1fff0400... done. PIRQ table: 128 bytes. Adding CBMEM entry as no. 3 smbios_write_tables: 1fff1400 Root Device (QEMU Mainboard) PCI_DOMAIN: 0000 (QEMU Northbridge) PCI: 00:00.0 (QEMU Northbridge) PCI: 00:01.0 (Intel 82371FB/SB/MX/AB/EB/MB Southbridge) PCI: 00:01.1 (Intel 82371FB/SB/MX/AB/EB/MB Southbridge) PCI: 00:01.3 () PCI: 00:02.0 () PCI: 00:03.0 () SMBIOS tables: 357 bytes. Adding CBMEM entry as no. 4 Writing high table forward entry at 0x00000500 Wrote coreboot table at: 00000500 - 00000518 checksum c3df New low_table_end: 0x00000518 Now going to write high coreboot table at 0x1fff1c00 rom_table_end = 0x1fff1c00 Adjust low_table_end from 0x00000518 to 0x00001000 Adjust rom_table_end from 0x1fff1c00 to 0x20000000 Adding high table area coreboot memory table: 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM 2. 00000000000c0000-000000001ffeffff: RAM 3. 000000001fff0000-000000001fffffff: CONFIGURATION TABLES 4. 00000000ff800000-00000000ffffffff: RESERVED Wrote coreboot table at: 1fff1c00 - 1fff1dd0 checksum fe3d coreboot table: 464 bytes. Multiboot Information structure has been written. 0. FREE SPACE 1fff3c00 0000c400 1. GDT 1fff0200 00000200 2. IRQ TABLE 1fff0400 00001000 3. SMBIOS 1fff1400 00000800 4. COREBOOT 1fff1c00 00002000 Searching for fallback/payload Check cmos_layout.bin Check fallback/romstage Check fallback/coreboot_ram Check fallback/payload Got a payload Loading segment from rom address 0xfffc99b8 code (compression=1) New segment dstaddr 0xe7e04 memsize 0x181fc srcaddr 0xfffc99f0 filesize 0xc21c (cleaned up) New segment addr 0xe7e04 size 0x181fc offset 0xfffc99f0 filesize 0xc21c Loading segment from rom address 0xfffc99d4 Entry Point 0x00000000 Loading Segment: addr: 0x00000000000e7e04 memsz: 0x00000000000181fc filesz: 0x000000000000c21c lb: [0x0000000000100000, 0x0000000000124000) Post relocation: addr: 0x00000000000e7e04 memsz: 0x00000000000181fc filesz: 0x000000000000c21c using LZMA [ 0x000e7e04, 00100000, 0x00100000) <- fffc99f0 dest 000e7e04, end 00100000, bouncebuffer 1ffa8000 Loaded segments Jumping to boot code at fc8b9 entry = 0x000fc8b9 lb_start = 0x00100000 lb_size = 0x00024000 adjust = 0x1fecc000 buffer = 0x1ffa8000 elf_boot_notes = 0x00110538 adjusted_boot_notes = 0x1ffdc538 Start bios (version 1.6.3-20120309_040510-redevil) Found mainboard Emulation QEMU x86 Found CBFS header at 0xfffffc90 Ram Size=0x1fff0000 (0x0000000000000000 high) Relocating init from 0x000e8450 to 0x1ffd57a0 (size 42812) CPU Mhz=2936 Found 6 PCI devices (max PCI bus is 00) Found 1 cpu(s) max supported 1 cpu(s) Copying PIR from 0x1fff0400 to 0x000fdb70 Copying SMBIOS entry point from 0x1fff1400 to 0x000fdb50 Scan for VGA option rom Running option rom at c000:0003 Turning on vga text mode console SeaBIOS (version 1.6.3-20120309_040510-redevil) Found 1 lpt ports Found 1 serial ports ATA controller 1 at 1f0/3f4/0 (irq 14 dev 9) ATA controller 2 at 170/374/0 (irq 15 dev 9) ata0-0: QEMU HARDDISK ATA-7 Hard-Disk (2500 MiBytes) Searching bootorder for: /pci@i0cf8/*@1,1/drive@0/disk@0 DVD/CD [ata1-0: QEMU DVD-ROM ATAPI-4 DVD/CD] Searching bootorder for: /pci@i0cf8/*@1,1/drive@1/disk@0 PS2 keyboard initialized All threads complete. Scan for option roms Press F12 for boot menu. drive 0x000fdb00: PCHS=5079/16/63 translation=large LCHS=634/128/63 s=5120000 ebda moved from 9fc00 to 9f400 Returned 65536 bytes of ZoneHigh e820 map has 6 items: 0: 0000000000000000 - 000000000009f400 = 1 RAM 1: 000000000009f400 - 00000000000a0000 = 2 RESERVED 2: 00000000000f0000 - 0000000000100000 = 2 RESERVED 3: 0000000000100000 - 000000001fff0000 = 1 RAM 4: 000000001fff0000 - 0000000020000000 = 2 RESERVED 5: 00000000ff800000 - 0000000100000000 = 2 RESERVED enter handle_19: NULL Booting from DVD/CD... 3991MB medium detected Booting from 0000:7c00 Changing serial settings was 0/0 now 3/0 In resume (status=0) In 32bit resume Attempting a hard reboot Changing serial settings was 0/0 now 3/0 In resume (status=0) In 32bit resume Attempting a hard reboot Changing serial settings was 0/0 now 3/0 In resume (status=0) In 32bit resume Attempting a hard reboot Changing serial settings was 0/0 now 3/0 In resume (status=0) In 32bit resume Attempting a hard reboot

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Flip bits, not burgers! - coreboot GSoC 2012
by Marc Jones 09 Mar '12

09 Mar '12

corebooters, Flip bits, not burgers! coreboot is applying for Google Summer of Code 2012. We are currently looking for mentors, project ideas, and prospective students. Please visit the coreboot GSoC page: http://www.coreboot.org/GSoC Students: Prospective students should join the email list and join #coreboot to get familiar with coreboot. Please forward any potential GSoC students to the coreboot GSoC page. Projects: We are interested in all types of projects that support coreboot, including payload and infrastructure projects. If you have project ideas please post them here: http://www.coreboot.org/Project_Ideas Mentors: We need mentors! The more qualified mentors we have registered, the more GSoC projects/students we can support. We will match students with mentors once the proposal phase is done. If you might like to be a mentor, please register with google and add yourself to the mentor list on the wiki.: http://www.google-melange.com/gsoc/homepage/google/gsoc2012 Please feel free to contact me by email or in IRC #coreboot if you have questions. Regards, Marc -- http://se-eng.com

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coreboot March 2012