coreboot March 2012

coreboot@coreboot.org

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718 discussions

Patch set updated for coreboot: f8511a6 Fix libpayload alloc()i size and gcc pointer optimization problems.
by Marc Jones 21 Mar '12

21 Mar '12

Marc Jones (marcj303(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/804 -gerrit commit f8511a62286311cd337821e3700bbf1a9b351266 Author: Marc Jones <marc.jones(a)se-eng.com> Date: Tue Mar 20 16:53:44 2012 -0600 Fix libpayload alloc()i size and gcc pointer optimization problems. The previous commit was incomplete and missed setting the entire alloc area. There are also additional problems with gcc optimizations of the pointer math. The "auto" casting by gcc wouldn't return warnings, but it was causing the optimization to be incorrect. We are now very explicit in the casting in the pointer math. Change-Id: I020808c8d1dda544fe862b9efb0e5345eeab5aab Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> --- payloads/libpayload/libc/malloc.c | 10 +++++----- 1 files changed, 5 insertions(+), 5 deletions(-) diff --git a/payloads/libpayload/libc/malloc.c b/payloads/libpayload/libc/malloc.c index 9412cab..3c5a3fd 100644 --- a/payloads/libpayload/libc/malloc.c +++ b/payloads/libpayload/libc/malloc.c @@ -96,7 +96,7 @@ static void *alloc(int len) /* Make sure the region is setup correctly. */ if (!HAS_MAGIC(*ptr)) - setup(ptr, len); + setup(ptr, (int)((&_eheap - &_heap) - HDRSIZE)); /* Find some free space. */ do { @@ -112,7 +112,7 @@ static void *alloc(int len) if (header & FLAG_FREE) { if (len <= size) { - hdrtype_t volatile *nptr = ptr + (HDRSIZE + len); + hdrtype_t volatile *nptr = (hdrtype_t volatile *)((int)ptr + HDRSIZE + len); int nsize = size - (HDRSIZE + len); /* If there is still room in this block, @@ -131,11 +131,11 @@ static void *alloc(int len) *ptr = USED_BLOCK(size); } - return (void *)(ptr + HDRSIZE); + return (void *)((int)ptr + HDRSIZE); } } - ptr += HDRSIZE + size; + ptr = (hdrtype_t volatile *)((int)ptr + HDRSIZE + size); } while (ptr < (hdrtype_t *) hend); @@ -422,7 +422,7 @@ void print_malloc_map(void) if (free_memory && (minimal_free > free_memory)) minimal_free = free_memory; - printf("Maximum memory consumption: %d bytes", + printf("Maximum memory consumption: %d bytes\n", (unsigned int)(&_eheap - &_heap) - HDRSIZE - minimal_free); } #endif

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New patch to review for coreboot: f6d3985 Fix libpayload alloc function.
by Marc Jones 20 Mar '12

20 Mar '12

Marc Jones (marcj303(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/804 -gerrit commit f6d3985879b45a2cb05279bfa7ebaba0779a56bb Author: Marc Jones <marc.jones(a)se-eng.com> Date: Tue Mar 20 16:53:44 2012 -0600 Fix libpayload alloc function. The previous commit was incomplete and missed setting the complete of the alloc area. There are also additional problems with gcc optimizations of the pointer math. The "auto" casting by gcc wouldn't return warnings, but it was causing the optimization to be incorrect. We are now very explicit in the casting in the pointer math. Change-Id: I020808c8d1dda544fe862b9efb0e5345eeab5aab Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> --- payloads/libpayload/libc/malloc.c | 10 +++++----- 1 files changed, 5 insertions(+), 5 deletions(-) diff --git a/payloads/libpayload/libc/malloc.c b/payloads/libpayload/libc/malloc.c index 9412cab..3c5a3fd 100644 --- a/payloads/libpayload/libc/malloc.c +++ b/payloads/libpayload/libc/malloc.c @@ -96,7 +96,7 @@ static void *alloc(int len) /* Make sure the region is setup correctly. */ if (!HAS_MAGIC(*ptr)) - setup(ptr, len); + setup(ptr, (int)((&_eheap - &_heap) - HDRSIZE)); /* Find some free space. */ do { @@ -112,7 +112,7 @@ static void *alloc(int len) if (header & FLAG_FREE) { if (len <= size) { - hdrtype_t volatile *nptr = ptr + (HDRSIZE + len); + hdrtype_t volatile *nptr = (hdrtype_t volatile *)((int)ptr + HDRSIZE + len); int nsize = size - (HDRSIZE + len); /* If there is still room in this block, @@ -131,11 +131,11 @@ static void *alloc(int len) *ptr = USED_BLOCK(size); } - return (void *)(ptr + HDRSIZE); + return (void *)((int)ptr + HDRSIZE); } } - ptr += HDRSIZE + size; + ptr = (hdrtype_t volatile *)((int)ptr + HDRSIZE + size); } while (ptr < (hdrtype_t *) hend); @@ -422,7 +422,7 @@ void print_malloc_map(void) if (free_memory && (minimal_free > free_memory)) minimal_free = free_memory; - printf("Maximum memory consumption: %d bytes", + printf("Maximum memory consumption: %d bytes\n", (unsigned int)(&_eheap - &_heap) - HDRSIZE - minimal_free); } #endif

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Asus M5A88-v evo
by Jonathan Bennett 20 Mar '12

20 Mar '12

I bought an M5A88-v Motherboard ( http://www.newegg.com/Product/Product.aspx?Item=N82E16813131733&Tpk=m5a88-v ) and an amd FX-4170 ( http://www.newegg.com/Product/Product.aspx?Item=N82E16819106009 ) I use Fedora 16 on this machine. Compiled coreboot with a vga bios from my board, flashed it, and in doing managed to brick the board. I have another computer I was able to use to flash a vendor bios onto the rom chip. Compiled again without video bios, and used a pci-express graphics card. Still no luck. I'm running the machine with stock firmware, but I'd love to be able to try out coreboot and seabios. With Coreboot on it, The machine powered on and the fans spun up. That's about it. No HD activity beyond power being applied. Ethernet port never powered, screen never came out of power save. Seems to have been bricked. Any ideas? Jonathan Bennett

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Re: [coreboot] New patch to review for coreboot: 995c74c Rename bootblock init functions
by Kyösti Mälkki 20 Mar '12

20 Mar '12

On Mon, 2012-03-19 at 16:39 -0700, ron minnich wrote: > we made a decision in the early days to NOT include the chip part name > in the function names. This was not a mistake or omission, it was a > deliberate design choice. > > The reason to name things this way is because a board is composed of a > set of parts, and the partname is in the file name path. Hence, the > board can be constructed of files calling functions with generic > names, and the generic functions are provided by files chosen in the > config. In some cases, it has proven trivial to port a mainboard to a > new chipset by changing only the config to use a different chip. The > fact that the function name did not include the chipname made this > trivial. I agree with this design. It works as the file-specific functions are accessed only via the chip-specific _ops structure. And those structures do have the chip name in them. > If we think that we really need the chip name in the function, ok, but > it's a change in the way we designed the build process. Maybe it's a > change we have to make. I am not yet convinced. Bootblock is special, probably for simplicity the chip objects were dropped. BTW: There are boards with two super-ios. KM

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Patch merged into coreboot/master: ad487c1 Avoid using CPUID in SMBIOS tables. Check for CPUID otherwise claim 486 class cpu.
by gerrit＠coreboot.org 20 Mar '12

20 Mar '12

the following patch was just integrated into master: commit ad487c1984683a4626490d65642b8fcd9ba2a081 Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Sat Feb 25 23:51:12 2012 +0100 Avoid using CPUID in SMBIOS tables. Check for CPUID otherwise claim 486 class cpu. Change-Id: Ic7c4452a1b55bae0cefee118003540ec39ef9fd4 Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Build-Tested: build bot (Jenkins) at Tue Mar 20 14:51:15 2012, giving +1 Reviewed-By: Peter Stuge <peter(a)stuge.se> at Tue Mar 20 15:13:07 2012, giving +2 See http://review.coreboot.org/683 for details. -gerrit

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New patch to review for coreboot: 9361e55 Makefile: split romstage linking to separate rules
by Kyösti Mälkki 20 Mar '12

20 Mar '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/803 -gerrit commit 9361e5572c4597a7e2509f17a79fd62370dd6caa Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Mar 19 19:40:01 2012 +0200 Makefile: split romstage linking to separate rules After change it is more clear how romstage is linked twice and with what scripts. Also with the change, it is easier to add some object of static size that need to be re-compiled for the 2nd link. One such object could be md5sum of executable. Change-Id: Ib34d1876071a51345c5c7319a0ed937868817fd1 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/Makefile.inc | 35 +++++++++++++++++++++++------------ 1 files changed, 23 insertions(+), 12 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index fc3cd14..46b5e3c 100755 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -272,8 +272,7 @@ $(obj)/coreboot.pre: $(obj)/coreboot.romstage $(obj)/coreboot.pre1 $(CBFSTOOL) rm -f $@ cp $(obj)/coreboot.pre1 $@ $(CBFSTOOL) $@ add-stage $(obj)/romstage.elf \ - $(CONFIG_CBFS_PREFIX)/romstage x 0x$(shell cat $(obj)/location.txt) -#FIXME: location.txt might require an offset of header size + $(CONFIG_CBFS_PREFIX)/romstage x $(shell cat $(obj)/location.txt) ####################################################################### # Build the bootblock @@ -340,26 +339,38 @@ $(obj)/bootblock.elf: $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.o $(obj)/bootbl ####################################################################### # Build the romstage -$(obj)/coreboot.romstage: $(obj)/coreboot.pre1 $$(romstage-objs) $(obj)/romstage/ldscript.ld + +$(obj)/romstage.bin: $$(romstage-objs) $(obj)/romstage/link1st.ld @printf " LINK $(subst $(obj)/,,$(@))\n" - printf "ROMSTAGE_BASE = 0x0;\n" > $(obj)/location.ld - $(CC) -nostdlib -nostartfiles -static -o $(obj)/romstage.elf -L$(obj) -T $(obj)/romstage/ldscript.ld $(romstage-objs) + $(CC) -nostdlib -nostartfiles -static -o $(obj)/romstage.elf -L$(obj) -T $(obj)/romstage/link1st.ld $(romstage-objs) $(OBJCOPY) -O binary $(obj)/romstage.elf $(obj)/romstage.bin - printf "ROMSTAGE_BASE = 0x" > $(obj)/location.ld - $(CBFSTOOL) $(obj)/coreboot.pre1 locate $(obj)/romstage.bin $(CONFIG_CBFS_PREFIX)/romstage $(CONFIG_XIP_ROM_SIZE) > $(obj)/location.txt || { echo "The romstage is larger than XIP size. Please expand the CONFIG_XIP_ROM_SIZE" ; exit 1; } - cat $(obj)/location.txt >> $(obj)/location.ld - printf ';\n' >> $(obj)/location.ld - $(CC) -nostdlib -nostartfiles -static -o $(obj)/romstage.elf -L$(obj) -T $(obj)/romstage/ldscript.ld $(romstage-objs) + +$(obj)/coreboot.romstage: $$(romstage-objs) $(obj)/romstage/link2nd.ld + @printf " LINK $(subst $(obj)/,,$(@))\n" + $(CC) -nostdlib -nostartfiles -static -o $(obj)/romstage.elf -L$(obj) -T $(obj)/romstage/link2nd.ld $(romstage-objs) $(NM) -n $(obj)/romstage.elf | sort > $(obj)/romstage.map $(OBJCOPY) --only-keep-debug $(obj)/romstage.elf $(obj)/romstage.debug $(OBJCOPY) --strip-debug $(obj)/romstage.elf $(OBJCOPY) --add-gnu-debuglink=$(obj)/romstage.debug $(obj)/romstage.elf $(OBJCOPY) -O binary $(obj)/romstage.elf $@ -$(obj)/romstage/ldscript.ld: $$(ldscripts) $(obj)/ldoptions +$(obj)/romstage/link1st.ld: $$(ldscripts) $(obj)/ldoptions @printf " GEN $(subst $(obj)/,,$(@))\n" mkdir -p $(obj)/romstage - printf '$(foreach ldscript,ldoptions location.ld $(ldscripts),INCLUDE "$(ldscript:$(obj)/%=%)"\n)' > $@ + printf "ROMSTAGE_BASE = 0x0;\n" > $@ + printf '$(foreach ldscript,ldoptions $(ldscripts),INCLUDE "$(ldscript:$(obj)/%=%)"\n)' >> $@ + +$(obj)/romstage/link2nd.ld: $(obj)/romstage/link1st.ld $(obj)/location.txt + @printf " GEN $(subst $(obj)/,,$(@))\n" + sed -e 's/^/ROMSTAGE_BASE = /g' -e 's/$$/;/g' $(obj)/location.txt > $@ + sed -e '/ROMSTAGE_BASE/d' $(obj)/romstage/link1st.ld >> $@ + +$(obj)/location.txt: $(obj)/coreboot.pre1 $(obj)/romstage.bin + rm -f $@ + $(CBFSTOOL) $(obj)/coreboot.pre1 locate $(obj)/romstage.bin $(CONFIG_CBFS_PREFIX)/romstage $(CONFIG_XIP_ROM_SIZE) > $@.tmp \ + || { echo "The romstage is larger than XIP size. Please expand the CONFIG_XIP_ROM_SIZE" ; exit 1; } + sed -i -e 's/^/0x/g' $@.tmp + mv $@.tmp $@ $(obj)/romstage/crt0.S: $$(crt0s) @printf " GEN $(subst $(obj)/,,$(@))\n"

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New patch to review for coreboot: c82896d Makefile: rename linker intermediate variable
by Kyösti Mälkki 20 Mar '12

20 Mar '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/802 -gerrit commit c82896d576c16c91eab36be06743f57ea3d8bc0b Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Mar 19 19:12:49 2012 +0200 Makefile: rename linker intermediate variable Renamed CONFIG_ROMBASE to ROMSTAGE_BASE and removed it from Kconfig. Removed no-op calculation in ldscript. Change-Id: I53d39b60f07db76c8537b3133e59360687b9d4a7 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/Kconfig | 4 ---- src/arch/x86/Makefile.inc | 4 ++-- src/arch/x86/init/bootblock.ld | 7 +------ 3 files changed, 3 insertions(+), 12 deletions(-) diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index c5a0c0e..314646f 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -8,10 +8,6 @@ config AP_IN_SIPI_WAIT default n depends on ARCH_X86 -config ROMBASE - hex - default 0xffff0000 - config RAMBASE hex default 0x100000 diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index d3dac11..fc3cd14 100755 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -342,10 +342,10 @@ $(obj)/bootblock.elf: $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.o $(obj)/bootbl # Build the romstage $(obj)/coreboot.romstage: $(obj)/coreboot.pre1 $$(romstage-objs) $(obj)/romstage/ldscript.ld @printf " LINK $(subst $(obj)/,,$(@))\n" - printf "CONFIG_ROMBASE = 0x0;\n" > $(obj)/location.ld + printf "ROMSTAGE_BASE = 0x0;\n" > $(obj)/location.ld $(CC) -nostdlib -nostartfiles -static -o $(obj)/romstage.elf -L$(obj) -T $(obj)/romstage/ldscript.ld $(romstage-objs) $(OBJCOPY) -O binary $(obj)/romstage.elf $(obj)/romstage.bin - printf "CONFIG_ROMBASE = 0x" > $(obj)/location.ld + printf "ROMSTAGE_BASE = 0x" > $(obj)/location.ld $(CBFSTOOL) $(obj)/coreboot.pre1 locate $(obj)/romstage.bin $(CONFIG_CBFS_PREFIX)/romstage $(CONFIG_XIP_ROM_SIZE) > $(obj)/location.txt || { echo "The romstage is larger than XIP size. Please expand the CONFIG_XIP_ROM_SIZE" ; exit 1; } cat $(obj)/location.txt >> $(obj)/location.ld printf ';\n' >> $(obj)/location.ld diff --git a/src/arch/x86/init/bootblock.ld b/src/arch/x86/init/bootblock.ld index fd4d3db..27d718f 100644 --- a/src/arch/x86/init/bootblock.ld +++ b/src/arch/x86/init/bootblock.ld @@ -25,13 +25,8 @@ OUTPUT_ARCH(i386) TARGET(binary) SECTIONS { - . = CONFIG_ROMBASE; + . = ROMSTAGE_BASE; - /* cut _start into last 64k */ - _x = .; - . = (_x < CONFIG_ROMBASE) ? (CONFIG_ROMBASE) : _x; - - /* This section might be better named .setup */ .rom . : { _rom = .; *(.rom.text);

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Patch set updated for coreboot: ad487c1 Avoid using CPUID in SMBIOS tables. Check for CPUID otherwise claim 486 class cpu.
by Rudolf Marek 20 Mar '12

20 Mar '12

Rudolf Marek (r.marek(a)assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/683 -gerrit commit ad487c1984683a4626490d65642b8fcd9ba2a081 Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Sat Feb 25 23:51:12 2012 +0100 Avoid using CPUID in SMBIOS tables. Check for CPUID otherwise claim 486 class cpu. Change-Id: Ic7c4452a1b55bae0cefee118003540ec39ef9fd4 Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> --- src/arch/x86/boot/smbios.c | 49 ++++++++++++++++++++++++-------------- src/arch/x86/include/arch/cpu.h | 1 + src/arch/x86/lib/cpu.c | 9 +++---- 3 files changed, 36 insertions(+), 23 deletions(-) diff --git a/src/arch/x86/boot/smbios.c b/src/arch/x86/boot/smbios.c index e5156d9..2bd00c4 100644 --- a/src/arch/x86/boot/smbios.c +++ b/src/arch/x86/boot/smbios.c @@ -76,34 +76,41 @@ int smbios_string_table_len(char *start) static int smbios_cpu_vendor(char *start) { - char tmp[13]; + char tmp[13] = "Unknown"; u32 *_tmp = (u32 *)tmp; - struct cpuid_result res = cpuid(0); + struct cpuid_result res; - _tmp[0] = res.ebx; - _tmp[1] = res.edx; - _tmp[2] = res.ecx; - tmp[12] = '\0'; - return smbios_add_string(start, tmp); + if (cpu_have_cpuid()) { + res = cpuid(0); + _tmp[0] = res.ebx; + _tmp[1] = res.edx; + _tmp[2] = res.ecx; + tmp[12] = '\0'; + } + return smbios_add_string(start, tmp); } static int smbios_processor_name(char *start) { - char tmp[49]; + char tmp[49] = "Unknown Processor Name"; u32 *_tmp = (u32 *)tmp; struct cpuid_result res; int i; - for (i = 0; i < 3; i++) { - res = cpuid(0x80000002 + i); - _tmp[i * 4 + 0] = res.eax; - _tmp[i * 4 + 1] = res.ebx; - _tmp[i * 4 + 2] = res.ecx; - _tmp[i * 4 + 3] = res.edx; + if (cpu_have_cpuid()) { + res = cpuid(0x80000000); + if (res.eax >= 0x80000004) { + for (i = 0; i < 3; i++) { + res = cpuid(0x80000002 + i); + _tmp[i * 4 + 0] = res.eax; + _tmp[i * 4 + 1] = res.ebx; + _tmp[i * 4 + 2] = res.ecx; + _tmp[i * 4 + 3] = res.edx; + } + tmp[48] = 0; + } } - - tmp[48] = 0; return smbios_add_string(start, tmp); } @@ -184,7 +191,13 @@ static int smbios_write_type4(unsigned long *current, int handle) struct smbios_type4 *t = (struct smbios_type4 *)*current; int len = sizeof(struct smbios_type4); - res = cpuid(1); + /* Provide sane defaults even for CPU without CPUID */ + res.eax = res.edx = 0; + res.ebx = 0x10000; + + if (cpu_have_cpuid()) { + res = cpuid(1); + } memset(t, 0, sizeof(struct smbios_type4)); t->type = SMBIOS_PROCESSOR_INFORMATION; @@ -194,7 +207,7 @@ static int smbios_write_type4(unsigned long *current, int handle) t->processor_id[1] = res.edx; t->processor_manufacturer = smbios_cpu_vendor(t->eos); t->processor_version = smbios_processor_name(t->eos); - t->processor_family = 0x0c; + t->processor_family = (res.eax > 0) ? 0x0c : 0x6; t->processor_type = 3; /* System Processor */ t->processor_upgrade = 0x06; t->core_count = (res.ebx >> 16) & 0xff; diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 85357d7..2dfcd72 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -109,6 +109,7 @@ static inline unsigned int cpuid_edx(unsigned int op) #include <device/device.h> int cpu_phys_address_size(void); +int cpu_have_cpuid(void); struct cpu_device_id { unsigned vendor; diff --git a/src/arch/x86/lib/cpu.c b/src/arch/x86/lib/cpu.c index a7f7b32..fac523f 100644 --- a/src/arch/x86/lib/cpu.c +++ b/src/arch/x86/lib/cpu.c @@ -31,9 +31,8 @@ static inline int flag_is_changeable_p(uint32_t flag) return ((f1^f2) & flag) != 0; } - /* Probe for the CPUID instruction */ -static int have_cpuid_p(void) +int cpu_have_cpuid(void) { return flag_is_changeable_p(X86_EFLAGS_ID); } @@ -141,7 +140,7 @@ static int cpu_cpuid_extended_level(void) int cpu_phys_address_size(void) { - if (!(have_cpuid_p())) + if (!(cpu_have_cpuid())) return 32; if (cpu_cpuid_extended_level() >= 0x80000008) @@ -159,7 +158,7 @@ static void identify_cpu(struct device *cpu) vendor_name[0] = '\0'; /* Unset */ /* Find the id and vendor_name */ - if (!have_cpuid_p()) { + if (!cpu_have_cpuid()) { /* Its a 486 if we can modify the AC flag */ if (flag_is_changeable_p(X86_EFLAGS_AC)) { cpu->device = 0x00000400; /* 486 */ @@ -175,7 +174,7 @@ static void identify_cpu(struct device *cpu) memcpy(vendor_name, "NexGenDriven", 13); } } - if (have_cpuid_p()) { + if (cpu_have_cpuid()) { int cpuid_level; struct cpuid_result result; result = cpuid(0x00000000);

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Patch set updated for coreboot: bd403a1 Avoid using CPUID in SMBIOS tables. Check for CPUID otherwise claim 486 class cpu.
by Rudolf Marek 20 Mar '12

20 Mar '12

Rudolf Marek (r.marek(a)assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/683 -gerrit commit bd403a108322ca1201fc45a49fba372cc639879b Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Sat Feb 25 23:51:12 2012 +0100 Avoid using CPUID in SMBIOS tables. Check for CPUID otherwise claim 486 class cpu. Change-Id: Ic7c4452a1b55bae0cefee118003540ec39ef9fd4 Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> --- src/arch/x86/boot/smbios.c | 49 ++++++++++++++++++++++++-------------- src/arch/x86/include/arch/cpu.h | 29 +++++++++++++++++++++++ src/arch/x86/lib/cpu.c | 29 ----------------------- 3 files changed, 60 insertions(+), 47 deletions(-) diff --git a/src/arch/x86/boot/smbios.c b/src/arch/x86/boot/smbios.c index e5156d9..0575044 100644 --- a/src/arch/x86/boot/smbios.c +++ b/src/arch/x86/boot/smbios.c @@ -76,34 +76,41 @@ int smbios_string_table_len(char *start) static int smbios_cpu_vendor(char *start) { - char tmp[13]; + char tmp[13] = "Unknown"; u32 *_tmp = (u32 *)tmp; - struct cpuid_result res = cpuid(0); + struct cpuid_result res; - _tmp[0] = res.ebx; - _tmp[1] = res.edx; - _tmp[2] = res.ecx; - tmp[12] = '\0'; - return smbios_add_string(start, tmp); + if (have_cpuid_p()) { + res = cpuid(0); + _tmp[0] = res.ebx; + _tmp[1] = res.edx; + _tmp[2] = res.ecx; + tmp[12] = '\0'; + } + return smbios_add_string(start, tmp); } static int smbios_processor_name(char *start) { - char tmp[49]; + char tmp[49] = "Unknown Processor Name"; u32 *_tmp = (u32 *)tmp; struct cpuid_result res; int i; - for (i = 0; i < 3; i++) { - res = cpuid(0x80000002 + i); - _tmp[i * 4 + 0] = res.eax; - _tmp[i * 4 + 1] = res.ebx; - _tmp[i * 4 + 2] = res.ecx; - _tmp[i * 4 + 3] = res.edx; + if (have_cpuid_p()) { + res = cpuid(0x80000000); + if (res.eax >= 0x80000004) { + for (i = 0; i < 3; i++) { + res = cpuid(0x80000002 + i); + _tmp[i * 4 + 0] = res.eax; + _tmp[i * 4 + 1] = res.ebx; + _tmp[i * 4 + 2] = res.ecx; + _tmp[i * 4 + 3] = res.edx; + } + tmp[48] = 0; + } } - - tmp[48] = 0; return smbios_add_string(start, tmp); } @@ -184,7 +191,13 @@ static int smbios_write_type4(unsigned long *current, int handle) struct smbios_type4 *t = (struct smbios_type4 *)*current; int len = sizeof(struct smbios_type4); - res = cpuid(1); + /* Provide sane defaults even for CPU without CPUID */ + res.eax = res.edx = 0; + res.ebx = 0x10000; + + if (have_cpuid_p()) { + res = cpuid(1); + } memset(t, 0, sizeof(struct smbios_type4)); t->type = SMBIOS_PROCESSOR_INFORMATION; @@ -194,7 +207,7 @@ static int smbios_write_type4(unsigned long *current, int handle) t->processor_id[1] = res.edx; t->processor_manufacturer = smbios_cpu_vendor(t->eos); t->processor_version = smbios_processor_name(t->eos); - t->processor_family = 0x0c; + t->processor_family = (res.eax > 0) ? 0x0c : 0x6; t->processor_type = 3; /* System Processor */ t->processor_upgrade = 0x06; t->core_count = (res.ebx >> 16) & 0xff; diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 85357d7..4f395ce 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -29,6 +29,35 @@ struct cpuid_result { uint32_t edx; }; +/* Standard macro to see if a specific flag is changeable */ +static inline int flag_is_changeable_p(uint32_t flag) +{ + uint32_t f1, f2; + + asm( + "pushfl\n\t" + "pushfl\n\t" + "popl %0\n\t" + "movl %0,%1\n\t" + "xorl %2,%0\n\t" + "pushl %0\n\t" + "popfl\n\t" + "pushfl\n\t" + "popl %0\n\t" + "popfl\n\t" + : "=&r" (f1), "=&r" (f2) + : "ir" (flag)); + return ((f1^f2) & flag) != 0; +} + + +/* Probe for the CPUID instruction */ +static int have_cpuid_p(void) +{ + return flag_is_changeable_p(X86_EFLAGS_ID); +} + + /* * Generic CPUID function */ diff --git a/src/arch/x86/lib/cpu.c b/src/arch/x86/lib/cpu.c index a7f7b32..072a241 100644 --- a/src/arch/x86/lib/cpu.c +++ b/src/arch/x86/lib/cpu.c @@ -9,35 +9,6 @@ #include <device/path.h> #include <device/device.h> #include <smp/spinlock.h> - -/* Standard macro to see if a specific flag is changeable */ -static inline int flag_is_changeable_p(uint32_t flag) -{ - uint32_t f1, f2; - - asm( - "pushfl\n\t" - "pushfl\n\t" - "popl %0\n\t" - "movl %0,%1\n\t" - "xorl %2,%0\n\t" - "pushl %0\n\t" - "popfl\n\t" - "pushfl\n\t" - "popl %0\n\t" - "popfl\n\t" - : "=&r" (f1), "=&r" (f2) - : "ir" (flag)); - return ((f1^f2) & flag) != 0; -} - - -/* Probe for the CPUID instruction */ -static int have_cpuid_p(void) -{ - return flag_is_changeable_p(X86_EFLAGS_ID); -} - /* * Cyrix CPUs without cpuid or with cpuid not yet enabled can be detected * by the fact that they preserve the flags across the division of 5/2.

1 0

New patch to review for coreboot: 995c74c Rename bootblock init functions
by Kyösti Mälkki 19 Mar '12

19 Mar '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/800 -gerrit commit 995c74c88e546bbff6b625860d82fddcf60275c2 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Mar 16 20:39:10 2012 +0200 Rename bootblock init functions The following chip-specific functions were renamed to include chip name in the function: - bootblock_northbridge_init - bootblock_southbridge_init Change-Id: I54620a32d0799ef420b8b18772426f8d8082d4ca Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/hp/dl165_g6_fam10/bootblock.c | 4 ++-- src/northbridge/amd/amdfam10/bootblock.c | 2 +- src/northbridge/amd/amdk8/bootblock.c | 2 +- src/southbridge/amd/amd8111/bootblock.c | 2 +- src/southbridge/amd/cimx/sb700/bootblock.c | 2 +- src/southbridge/amd/cimx/sb800/bootblock.c | 2 +- src/southbridge/amd/cimx/sb900/bootblock.c | 2 +- src/southbridge/amd/sb600/bootblock.c | 2 +- src/southbridge/amd/sb700/bootblock.c | 2 +- src/southbridge/amd/sb800/bootblock.c | 2 +- src/southbridge/broadcom/bcm5785/bootblock.c | 2 +- src/southbridge/intel/i82371eb/bootblock.c | 2 +- src/southbridge/intel/i82801gx/bootblock.c | 2 +- src/southbridge/nvidia/ck804/bootblock.c | 2 +- src/southbridge/nvidia/mcp55/bootblock.c | 2 +- src/southbridge/sis/sis966/bootblock.c | 2 +- src/southbridge/via/vt8237r/bootblock.c | 2 +- util/sconfig/main.c | 4 ++-- 18 files changed, 20 insertions(+), 20 deletions(-) diff --git a/src/mainboard/hp/dl165_g6_fam10/bootblock.c b/src/mainboard/hp/dl165_g6_fam10/bootblock.c index dfece95..e7c0680 100644 --- a/src/mainboard/hp/dl165_g6_fam10/bootblock.c +++ b/src/mainboard/hp/dl165_g6_fam10/bootblock.c @@ -49,8 +49,8 @@ void shc4307_init(void) static unsigned long init_mainboard(int bsp_cpu) { if (!bsp_cpu) return 0; - bootblock_northbridge_init(); - //bootblock_southbridge_init(); + init_northbridge_amd_amdfam10(); + //init_southbridge_broadcom_bcm5785(); shc4307_init(); return 0; } diff --git a/src/northbridge/amd/amdfam10/bootblock.c b/src/northbridge/amd/amdfam10/bootblock.c index 612004a..328e9ad 100644 --- a/src/northbridge/amd/amdfam10/bootblock.c +++ b/src/northbridge/amd/amdfam10/bootblock.c @@ -3,7 +3,7 @@ #include <device/pci_def.h> #include "northbridge/amd/amdfam10/early_ht.c" -static void bootblock_northbridge_init(void) { +static void init_northbridge_amd_amdfam10(void) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ /* mov bsp to bus 0xff when > 8 nodes */ diff --git a/src/northbridge/amd/amdk8/bootblock.c b/src/northbridge/amd/amdk8/bootblock.c index b5395bb..8afd507 100644 --- a/src/northbridge/amd/amdk8/bootblock.c +++ b/src/northbridge/amd/amdk8/bootblock.c @@ -3,6 +3,6 @@ #include <device/pci_def.h> #include "northbridge/amd/amdk8/early_ht.c" -static void bootblock_northbridge_init(void) { +static void init_northbridge_amd_amdk8(void) { enumerate_ht_chain(); } diff --git a/src/southbridge/amd/amd8111/bootblock.c b/src/southbridge/amd/amd8111/bootblock.c index 3009c0b..d4660de 100644 --- a/src/southbridge/amd/amd8111/bootblock.c +++ b/src/southbridge/amd/amd8111/bootblock.c @@ -41,7 +41,7 @@ static void amd8111_enable_rom(void) pci_io_write_config8(dev, 0x43, byte); } -static void bootblock_southbridge_init(void) +static void init_southbridge_amd_amd8111(void) { amd8111_enable_rom(); } diff --git a/src/southbridge/amd/cimx/sb700/bootblock.c b/src/southbridge/amd/cimx/sb700/bootblock.c index 401c039..657fbdd 100644 --- a/src/southbridge/amd/cimx/sb700/bootblock.c +++ b/src/southbridge/amd/cimx/sb700/bootblock.c @@ -90,7 +90,7 @@ static void sb700_enable_rom(void) pci_io_write_config16(dev, 0x6c, word); } -static void bootblock_southbridge_init(void) +static void init_southbridge_amd_cimx_sb700(void) { /* Setup the rom access for 2M */ sb700_enable_rom(); diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c index 0a339b0..9e00219 100644 --- a/src/southbridge/amd/cimx/sb800/bootblock.c +++ b/src/southbridge/amd/cimx/sb800/bootblock.c @@ -104,7 +104,7 @@ static void enable_clocks(void) *acpi_mmio = reg32; } -static void bootblock_southbridge_init(void) +static void init_southbridge_amd_cimx_sb800(void) { /* Setup the rom access for 2M */ enable_rom(); diff --git a/src/southbridge/amd/cimx/sb900/bootblock.c b/src/southbridge/amd/cimx/sb900/bootblock.c index e84743b..f3b53d0 100644 --- a/src/southbridge/amd/cimx/sb900/bootblock.c +++ b/src/southbridge/amd/cimx/sb900/bootblock.c @@ -90,7 +90,7 @@ static void sb900_enable_rom(void) pci_io_write_config16(dev, 0x6c, word); } -static void bootblock_southbridge_init(void) +static void init_southbridge_amd_cimx_sb900(void) { /* Setup the rom access for 2M */ sb900_enable_rom(); diff --git a/src/southbridge/amd/sb600/bootblock.c b/src/southbridge/amd/sb600/bootblock.c index 45991ee..0184f73 100644 --- a/src/southbridge/amd/sb600/bootblock.c +++ b/src/southbridge/amd/sb600/bootblock.c @@ -64,7 +64,7 @@ static void sb600_enable_rom(void) pci_io_write_config16(dev, 0x6e, 0xffff); } -static void bootblock_southbridge_init(void) +static void init_southbridge_amd_sb600(void) { sb600_enable_rom(); } diff --git a/src/southbridge/amd/sb700/bootblock.c b/src/southbridge/amd/sb700/bootblock.c index 370cff9..b4bb686 100644 --- a/src/southbridge/amd/sb700/bootblock.c +++ b/src/southbridge/amd/sb700/bootblock.c @@ -64,7 +64,7 @@ static void sb700_enable_rom(void) pci_io_write_config16(dev, 0x6e, 0xffff); } -static void bootblock_southbridge_init(void) +static void init_southbridge_amd_sb700(void) { sb700_enable_rom(); } diff --git a/src/southbridge/amd/sb800/bootblock.c b/src/southbridge/amd/sb800/bootblock.c index 30d6ac6..6245dca 100644 --- a/src/southbridge/amd/sb800/bootblock.c +++ b/src/southbridge/amd/sb800/bootblock.c @@ -62,7 +62,7 @@ static void sb800_enable_rom(void) pci_io_write_config16(dev, 0x6e, 0xffff); } -static void bootblock_southbridge_init(void) +static void init_southbridge_amd_sb800(void) { sb800_enable_rom(); } diff --git a/src/southbridge/broadcom/bcm5785/bootblock.c b/src/southbridge/broadcom/bcm5785/bootblock.c index cadda53..e1e5f31 100644 --- a/src/southbridge/broadcom/bcm5785/bootblock.c +++ b/src/southbridge/broadcom/bcm5785/bootblock.c @@ -38,7 +38,7 @@ static void bcm5785_enable_rom(void) pci_write_config8(dev, 0x41, byte); } -static void bootblock_southbridge_init(void) +static void init_southbridge_broadcom_bcm5785(void) { bcm5785_enable_rom(); } diff --git a/src/southbridge/intel/i82371eb/bootblock.c b/src/southbridge/intel/i82371eb/bootblock.c index 07fa0bc..a875723 100644 --- a/src/southbridge/intel/i82371eb/bootblock.c +++ b/src/southbridge/intel/i82371eb/bootblock.c @@ -48,7 +48,7 @@ static void i82371eb_enable_rom(void) pci_write_config16(dev, XBCS, reg16); } -static void bootblock_southbridge_init(void) +static void init_southbridge_intel_i82371eb(void) { i82371eb_enable_rom(); } diff --git a/src/southbridge/intel/i82801gx/bootblock.c b/src/southbridge/intel/i82801gx/bootblock.c index 39b0bd4..a0f73b3 100644 --- a/src/southbridge/intel/i82801gx/bootblock.c +++ b/src/southbridge/intel/i82801gx/bootblock.c @@ -33,7 +33,7 @@ static void enable_spi_prefetch(void) pci_write_config8(dev, 0xdc, reg8); } -static void bootblock_southbridge_init(void) +static void init_southbridge_intel_i82801gx(void) { enable_spi_prefetch(); } diff --git a/src/southbridge/nvidia/ck804/bootblock.c b/src/southbridge/nvidia/ck804/bootblock.c index 29c10c8..3175606 100644 --- a/src/southbridge/nvidia/ck804/bootblock.c +++ b/src/southbridge/nvidia/ck804/bootblock.c @@ -42,7 +42,7 @@ static void ck804_enable_rom(void) pci_write_config8(addr, 0x88, byte); } -static void bootblock_southbridge_init(void) +static void init_southbridge_nvidia_ck804(void) { ck804_enable_rom(); } diff --git a/src/southbridge/nvidia/mcp55/bootblock.c b/src/southbridge/nvidia/mcp55/bootblock.c index affb025..6fb6dbb 100644 --- a/src/southbridge/nvidia/mcp55/bootblock.c +++ b/src/southbridge/nvidia/mcp55/bootblock.c @@ -53,7 +53,7 @@ static void mcp55_enable_rom(void) pci_write_config16(addr, 0x90, word); } -static void bootblock_southbridge_init(void) +static void init_southbridge_nvidia_mcp55(void) { mcp55_enable_rom(); } diff --git a/src/southbridge/sis/sis966/bootblock.c b/src/southbridge/sis/sis966/bootblock.c index 1ff3cda..45ab81b 100644 --- a/src/southbridge/sis/sis966/bootblock.c +++ b/src/southbridge/sis/sis966/bootblock.c @@ -41,7 +41,7 @@ static void sis966_enable_rom(void) pci_write_config8(addr, 0x40, pci_read_config8(addr, 0x40) | 0x11); } -static void bootblock_southbridge_init(void) +static void init_southbridge_sis_sis966(void) { sis966_enable_rom(); } diff --git a/src/southbridge/via/vt8237r/bootblock.c b/src/southbridge/via/vt8237r/bootblock.c index 8df37aa..0ca0533 100644 --- a/src/southbridge/via/vt8237r/bootblock.c +++ b/src/southbridge/via/vt8237r/bootblock.c @@ -21,7 +21,7 @@ #include <arch/romcc_io.h> #include <device/pci_ids.h> -static void bootblock_southbridge_init(void) +static void init_southbridge_via_vt8237r(void) { device_t dev; /* don't walk other busses, HT is not enabled */ diff --git a/util/sconfig/main.c b/util/sconfig/main.c index 4e3479b..21105f4 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -595,9 +595,9 @@ int main(int argc, char** argv) { h = &headers; while (h->next) { h = h->next; - char * buf = translate_name(h->name, SPLIT_1ST); + char * buf = translate_name(h->name, TO_LOWER); if (buf) { - fprintf(autogen, "\tbootblock_%s_init();\n", buf); + fprintf(autogen, "\tinit_%s();\n", buf); free(buf); } }

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coreboot March 2012