coreboot February 2012

coreboot@coreboot.org

34 participants
348 discussions

Trinity Support
by gary sheppard 06 Feb '12

06 Feb '12

Hello everyone, Recently AMD has stepped up their Trinity awareness. Many of us potential users are looking at Trinity very hard, as the hardware looks quite promising. If the community were to get together on 1 or 2 of the more interesting Trinity powered designs to offer substantial donations, would you the Dev community be interested in getting a couple of Trinity designs fully up and running? I for one do *NOT* want anything to do with UEFI ! Thank you for your consideration, Gary Sheppard

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Trac reminder: list of new ticket(s)
by coreboot tracker 06 Feb '12

06 Feb '12

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Re: [coreboot] How to port core boot
by Patrick Georgi 06 Feb '12

06 Feb '12

Am 05.02.2012 13:50, schrieb ali hagigat: > My motherboard is Pentium III, Intel 82815 and ICH2. I want to port > the Coreboot to this motherboard and I already have an assembly > routine which initializes the RAM modules. Where is that assembly routine from? Regards, Patrick

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Re: [coreboot] coreboot is being stopped!! help
by Kyösti Mälkki 06 Feb '12

06 Feb '12

On Sun, 2012-02-05 at 18:25 +0330, ali hagigat wrote: > My motherboard is: Pentium III, 82815, ICH2. > > I configured coreboot for Intel, d810e2cb motherboard. The coreboot > stops printing the following lines on the serial port: > > coreboot-4.0-1959-g950f20a-dirty Sun Feb 5 17:52:27 IRST 2012 starting... > SMBus controller enabled > No DIMM found in slot 0 > No DIMM found in slot 1 > DRP calculated to 0x00 > BUFF_SC calculated to 0x0000 > Loading image. > Searching for fallback/coreboot_ram > Check fallback/romstage > Check fallback/coreboot_ram > Stage: loading fallback/coreboot_ram @ 0x100000 (180224 bytes), entry @ 0x100000 > Stage: done loading. > Jumping to image. > > Where is the problem. I just replaced sdram_enable() with a routine > which I am sure that it initializes RAM correctly. The rest is the > pure Coreboot code. > Hi Enable most verbose logging (8 ?) and post new logs. Also readers on the list have currently no clue how You obtained and modified your local copy of Coreboot. Your posted serial log appears exactly as from the coreboot sources. Double-check you have really changed the call to sdram_enable(), recompiled, flashed correctly etc. If you are running closed-source assembly code copy-pasted and mixed within coreboot, don't expect much assistance until you have convinced us that at the minimum ram_check() passes without errors after sdram_enable() :) The following patch contains a replacement ram_check() that I consider more reliable or thorough: http://review.coreboot.org/294 Thanks, KM

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New patch to review for coreboot: 81d14b7 Auto-generate directory layouts within Kconfig files
by Kyösti Mälkki 06 Feb '12

06 Feb '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/608 -gerrit commit 81d14b7fe2ed4c7d0557c2dbd58618509f44f102 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Feb 6 11:49:52 2012 +0200 Auto-generate directory layouts within Kconfig files Goal of this patch is to remove some redundancy in the way compile directories are defined between Kconfig files and the devicetree.cb file. The script util/config-rules/autogen-kconfig.sh examines and operates recursively on selected subdirectories of src/ and creates temporary files under build/. For mainboard vendor and board directories the necessary choice entries are created with texts extracted from Kconfig files placed under the child directories. For results see: build/mainboard/Kconfig.autogen build/mainboard/vendor/Kconfig.autogen For the mainboard/vendor/board directory, devicetree.cb is parsed to generate select directives to include sources for all chip components. Few select directives will need to be renamed if this is taken into real use. For results see: build/mainboard/vendor/board/Kconfig.autogen Change-Id: Iaeededc70c771d478883d5f8f9a438ddfccc1df8 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- util/config-rules/autogen-kconfig.sh | 159 ++++++++++++++++++++++++++++++++++ util/config-rules/extract_choice | 15 +++ 2 files changed, 174 insertions(+), 0 deletions(-) diff --git a/util/config-rules/autogen-kconfig.sh b/util/config-rules/autogen-kconfig.sh new file mode 100755 index 0000000..a0068f8 --- /dev/null +++ b/util/config-rules/autogen-kconfig.sh @@ -0,0 +1,159 @@ +#! /bin/sh +# +# Auto-generates Kconfig sections for coreboot directory layout +# +# For mainboard vendor and board directories the necessary choice +# entries are created with texts extracted from Kconfig files +# placed under the child directories. +# +# For the mainboard/vendor/board directory, devicetree.cb is parsed to +# generate select directives to include sources for all chip components. + +sedpath=`dirname $0` +choice_field=$sedpath/extract_choice + +autogen_sub() +{ + kconfig_in=$1/$2/Kconfig + + if test -s $kconfig_in ; then + echo 'source "'${kconfig_in}'"' >> $sub_source + fi + + if test "$spath" = "mainboard" -o "$spath" = "mainboard_vendor" ; then + sed -f $choice_field $kconfig_in >> $sub_choice + fi +} + +autogen_cfg() +{ +# bootblock generation triggered from Makefile +# bcfg="bootblock_autogen.h" +# build/util/sconfig/sconfig $2/$3 $1 -b $bcfg + + kcfg="Kconfig.sdep" + build/util/sconfig/sconfig $2/$3 $1 -k $kcfg + cat $1/$kcfg >> $this_sconfig + rm -f $1/$kcfg + +} + + +output_sub_choice() +{ + if test ! -s $sub_choice ; then return ; fi + + if test "$spath" = "mainboard" ; then + echo '\nchoice\n\tprompt "Mainboard vendor"\n\tdefault VENDOR_EMULATION\n' >> $Kconfig_out + cat $sub_choice >> $Kconfig_out + echo 'endchoice\n' >> $Kconfig_out + elif test "$spath" = "mainboard_vendor" ; then + echo 'choice\n\tprompt "Mainboard model"\n' >> $Kconfig_out + cat $sub_choice >> $Kconfig_out + echo 'endchoice\n' >> $Kconfig_out + else + cat $sub_choice >> $Kconfig_out + echo >> $Kconfig_out + fi +} + +output_sub_source() +{ + if test ! -s $sub_source ; then return ; fi + + cat $sub_source >> $Kconfig_out + echo >> $Kconfig_out +} + +output_this_sconfig() +{ + if test ! -s $this_sconfig ; then return ; fi + + cat $this_sconfig >> $Kconfig_out + echo >> $Kconfig_out +} + + +# splits $root to $spath/$vendor/$part +# sets $subirs to list of $root subdirectories +split_parent_directory() +{ + sdir=$(echo $parent | tr "/" " ") + lvl=-1 + spath=none + + for i in $sdir ; do + if test $lvl -eq -1 -a $i = src ; then + lvl=0 + subdirs="cpu mainboard northbridge southbridge superio" + elif test $lvl -eq 0 ; then + spath=${i} + lvl=1 + elif test $lvl -eq 1 ; then + spath=${spath}_vendor + vendor=${i} + lvl=2 + else + spath=${spath}_part + part=${i} + fi + done + if test $lvl -gt 0 ; then + subdirs=`find $parent -mindepth 1 -maxdepth 1 -type d -printf "%f\n" | sort` + fi +} + +output_parent() +{ + Kconfig_out=$objd/Kconfig.autogen + sub_source=`mktemp -p $objd` + sub_choice=`mktemp -p $objd` + this_sconfig=`mktemp -p $objd` + + # sets spath, vendor, part, subdirs + split_parent_directory + + # generate sub-directory includes + for subd in $subdirs ; do + echo $parent/$subd >> nextdirs.tmp + autogen_sub $parent $subd + done + + # generate mainboard devicetree.cb configs + if test "$spath" = "mainboard_vendor_part" ; then + autogen_cfg $objd $vendor $part + fi + + if test -s $sub_source -o -s $sub_choice -o -s $this_sconfig ; then + echo '## begin Kconfig.autogen\n' > $Kconfig_out + output_this_sconfig + output_sub_choice + output_sub_source + echo '## end Kconfig.autogen' >> $Kconfig_out + fi + rm -f $sub_source $sub_choice $this_sconfig +} + +# main + +find ./build -name Kconfig.autogen -delete +find ./build -name bootblock_autogen.h -delete + +roots=src +while test -n "$roots" ; do + rm -f nextdirs.tmp + + for parent in $roots ; do + objd=`echo $parent | sed -e "s/^src/build/g"` + mkdir -p $objd + output_parent + done + + if test -s nextdirs.tmp ; then + roots=`cat nextdirs.tmp` + else + roots= + fi + +done + diff --git a/util/config-rules/extract_choice b/util/config-rules/extract_choice new file mode 100644 index 0000000..7582778 --- /dev/null +++ b/util/config-rules/extract_choice @@ -0,0 +1,15 @@ +/if VENDOR_/ b choice +/if BOARD_/ b choice +/config MAINBOARD_VENDOR/,+3b name +/config MAINBOARD_PART_NUMBER/,+3b name +/^/ D +: choice +{ +s/if/config/ p +/^/ D +} +: name +{ +s/default/bool/ p +/^/ D +}

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Patch merged into coreboot/master: 22d10e9 SIO: condition compile Nuvoton WPCM450 early_init.c
by gerrit＠coreboot.org 05 Feb '12

05 Feb '12

the following patch was just integrated into master: commit 22d10e91dec3aefb162cba777f32815bd745a295 Author: Kerry Sheh <shekairui(a)gmail.com> Date: Wed Feb 1 13:59:00 2012 +0800 SIO: condition compile Nuvoton WPCM450 early_init.c Compile Nuvoton WPCM450 early_init.c when CONFIG_SUPERIO_NUVOTON_WPCM450 Change-Id: Ie31b8ae6aa45d6f77efa2b61e215ba0987abf878 Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Sun Feb 5 17:45:08 2012, giving +2 See http://review.coreboot.org/566 for details. -gerrit

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coreboot is being stopped!! help
by ali hagigat 05 Feb '12

05 Feb '12

My motherboard is: Pentium III, 82815, ICH2. I configured coreboot for Intel, d810e2cb motherboard. The coreboot stops printing the following lines on the serial port: coreboot-4.0-1959-g950f20a-dirty Sun Feb 5 17:52:27 IRST 2012 starting... SMBus controller enabled No DIMM found in slot 0 No DIMM found in slot 1 DRP calculated to 0x00 BUFF_SC calculated to 0x0000 Loading image. Searching for fallback/coreboot_ram Check fallback/romstage Check fallback/coreboot_ram Stage: loading fallback/coreboot_ram @ 0x100000 (180224 bytes), entry @ 0x100000 Stage: done loading. Jumping to image. Where is the problem. I just replaced sdram_enable() with a routine which I am sure that it initializes RAM correctly. The rest is the pure Coreboot code.

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How to port core boot
by ali hagigat 05 Feb '12

05 Feb '12

My motherboard is Pentium III, Intel 82815 and ICH2. I want to port the Coreboot to this motherboard and I already have an assembly routine which initializes the RAM modules. Considering that what files i should alter exactly to get it done? I know that ASUS, MEW-AM is close to my board and it can be used as a start...

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Re: [coreboot] Asus m2n-e mcp55 won't boot
by Julian Shulika 03 Feb '12

03 Feb '12

I tried,there are some changes if I use 3th and 4th memory slots, last POST code is 66 and turns off coreboot-4.0-1980-gcc16cca-dirty Thu Feb 2 10:32:46 EST 2012 starting... *sysinfo range: [000cf000,000cf730] bsp_apicid=0x00 Enabling routing table for node 00 done. Enabling UP settings Disabling read/write/fill probes for UP... done. coherent_ht_finalize done core0 started: started ap apicid: SBLink=00 NC node|link=00 entering optimize_link_incoherent_ht sysinfo->link_pair_num=0x1 entering ht_optimize_link pos=0x8a, unfiltered freq_cap=0x8075 pos=0x8a, filtered freq_cap=0x75 pos=0x52, unfiltered freq_cap=0x807f pos=0x52, filtered freq_cap=0x7f freq_cap1=0x75, freq_cap2=0x7f dev1 old_freq=0x0, freq=0x6, needs_reset=0x1 dev2 old_freq=0x0, freq=0x6, needs_reset=0x1 width_cap1=0x11, width_cap2=0x11 dev1 input ln_width1=0x4, ln_width2=0x4 dev1 input width=0x1 dev1 output ln_width1=0x4, ln_width2=0x4 dev1 input|output width=0x11 old dev1 input|output width=0x11 dev2 input|output width=0x11 old dev2 input|output width=0x11 after ht_optimize_link for link pair 0, reset_needed=0x1 after optimize_link_read_pointers_chain, reset_needed=0x1 mcp55_num:01 ht reset - coreboot-4.0-1980-gcc16cca-dirty Thu Feb 2 10:32:46 EST 2012 starting... *sysinfo range: [000cf000,000cf730] bsp_apicid=0x00 Enabling routing table for node 00 done. Enabling UP settings Disabling read/write/fill probes for UP... done. coherent_ht_finalize done core0 started: started ap apicid: SBLink=00 NC node|link=00 entering optimize_link_incoherent_ht sysinfo->link_pair_num=0x1 entering ht_optimize_link pos=0x8a, unfiltered freq_cap=0x8075 pos=0x8a, filtered freq_cap=0x75 pos=0x52, unfiltered freq_cap=0x7f pos=0x52, filtered freq_cap=0x7f freq_cap1=0x75, freq_cap2=0x7f dev1 old_freq=0x6, freq=0x6, needs_reset=0x0 dev2 old_freq=0x6, freq=0x6, needs_reset=0x0 width_cap1=0x11, width_cap2=0x11 dev1 input ln_width1=0x4, ln_width2=0x4 dev1 input width=0x1 dev1 output ln_width1=0x4, ln_width2=0x4 dev1 input|output width=0x11 old dev1 input|output width=0x11 dev2 input|output width=0x11 old dev2 input|output width=0x11 after ht_optimize_link for link pair 0, reset_needed=0x0 after optimize_link_read_pointers_chain, reset_needed=0x0 mcp55_num:01 Ram1.00 setting up CPU 00 northbridge registers done. Ram2.00 sdram_set_spd_registers: paramx :000cef20 Unbuffered 333MHz 333MHz Interleaving disabled RAM end at 0x00080000 kB Ram3 Initializing memory: done Setting variable MTRR 2, base: 0MB, range: 512MB, type WB set DQS timing:RcvrEn:Pass1: 00 CTLRMaxDelay=0e done set DQS timing:DQSPos: 00 TrainDQSRdWrPos: buf_a:000ce9f0 TrainDQSPos: MutualCSPassW[48] :000ce8c8 TrainDQSPos: MutualCSPassW[48] :000ce8c8 TrainDQSPos: MutualCSPassW[48] :000ce8c8 TrainDQSPos: MutualCSPassW[48] :000ce8d8 done set DQS timing:RcvrEn:Pass2: 00 CTLRMaxDelay=57 done Total DQS Training : tsc [00]=000000001287da11 Total DQS Training : tsc [01]=000000001302b830 Total DQS Training : tsc [02]=00000000188e7b94 Total DQS Training : tsc [03]=00000000195ea260 Ram4 v_esp=000cef68 testx = 5a5a5a5a Copying data from cache to RAM -- switching to use RAM as stack... Done testx = 5a5a5a5a Disabling cache as ram now Clearing initial memory region: Done Loading image. Searching for fallback/coreboot_ram Check cmos_layout.bin Check fallback/romstage Check fallback/coreboot_ram Stage: loading fallback/coreboot_ram @ 0x100000 (245760 bytes), entry @ 0x100000 Stage: done loading. Jumping to image. coreboot-4.0-1980-gcc16cca-dirty Thu Feb 2 10:32:46 EST 2012 booting... Enumerating buses... Show all devs...Before device enumeration. Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:01.0: enabled 1 PNP: 002e.0: enabled 1 PNP: 002e.1: enabled 1 PNP: 002e.2: enabled 0 PNP: 002e.3: enabled 1 PNP: 002e.4: enabled 1 PNP: 002e.5: enabled 1 PNP: 002e.6: enabled 1 PNP: 002e.7: enabled 0 PNP: 002e.8: enabled 0 PNP: 002e.9: enabled 0 PNP: 002e.a: enabled 0 PCI: 00:01.1: enabled 1 I2C: 00:50: enabled 1 I2C: 00:51: enabled 1 I2C: 00:52: enabled 1 I2C: 00:53: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:02.1: enabled 1 PCI: 00:04.0: enabled 1 PCI: 00:05.0: enabled 1 PCI: 00:05.1: enabled 1 PCI: 00:05.2: enabled 1 PCI: 00:06.0: enabled 1 PCI: 00:06.1: enabled 1 PCI: 00:08.0: enabled 1 PCI: 00:09.0: enabled 0 PCI: 00:0a.0: enabled 1 PCI: 00:0b.0: enabled 0 PCI: 00:0c.0: enabled 1 PCI: 00:0d.0: enabled 1 PCI: 00:0e.0: enabled 0 PCI: 00:0f.0: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 Compare with tree... Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:01.0: enabled 1 PNP: 002e.0: enabled 1 PNP: 002e.1: enabled 1 PNP: 002e.2: enabled 0 PNP: 002e.3: enabled 1 PNP: 002e.4: enabled 1 PNP: 002e.5: enabled 1 PNP: 002e.6: enabled 1 PNP: 002e.7: enabled 0 PNP: 002e.8: enabled 0 PNP: 002e.9: enabled 0 PNP: 002e.a: enabled 0 PCI: 00:01.1: enabled 1 I2C: 00:50: enabled 1 I2C: 00:51: enabled 1 I2C: 00:52: enabled 1 I2C: 00:53: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:02.1: enabled 1 PCI: 00:04.0: enabled 1 PCI: 00:05.0: enabled 1 PCI: 00:05.1: enabled 1 PCI: 00:05.2: enabled 1 PCI: 00:06.0: enabled 1 PCI: 00:06.1: enabled 1 PCI: 00:08.0: enabled 1 PCI: 00:09.0: enabled 0 PCI: 00:0a.0: enabled 1 PCI: 00:0b.0: enabled 0 PCI: 00:0c.0: enabled 1 PCI: 00:0d.0: enabled 1 PCI: 00:0e.0: enabled 0 PCI: 00:0f.0: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 scan_static_bus for Root Device APIC_CLUSTER: 0 enabled PCI_DOMAIN: 0000 enabled APIC_CLUSTER: 0 scanning... PCI: 00:18.3 siblings=0 CPU: APIC: 00 enabled PCI_DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 PCI: 00:18.0 [1022/1100] bus ops PCI: 00:18.0 [1022/1100] enabled PCI: 00:18.1 [1022/1101] enabled PCI: 00:18.2 [1022/1102] enabled PCI: 00:18.3 [1022/1103] ops PCI: 00:18.3 [1022/1103] enabled PCI: Using configuration type 1 PCI: 00:00.0 [10de/0369] ops PCI: 00:00.0 [10de/0369] enabled Capability: type 0x08 @ 0x44 flags: 0x01e0 PCI: 00:00.0 count: 000f static_count: 0010 PCI: 00:00.0 [10de/0369] enabled next_unitid: 0010 PCI: pci_scan_bus for bus 00 PCI: 00:00.0 [10de/0369] enabled PCI: 00:01.0 [10de/0360] bus ops PCI: 00:01.0 [10de/0360] enabled PCI: 00:01.1 [10de/0368] bus ops PCI: 00:01.1 [10de/0368] enabled PCI: 00:01.2 [10de/036a] enabled PCI: 00:01.3 [10de/036b] enabled PCI: 00:02.0 [10de/036c] ops PCI: 00:02.0 [10de/036c] enabled PCI: 00:02.1 [10de/036d] ops PCI: 00:02.1 [10de/036d] enabled PCI: 00:04.0 [10de/036e] ops PCI: 00:04.0 [10de/036e] enabled PCI: 00:05.0 [10de/037f] ops PCI: 00:05.0 [10de/037f] enabled PCI: 00:05.1 [10de/037f] ops PCI: 00:05.1 [10de/037f] enabled PCI: 00:05.2 [10de/037f] ops PCI: 00:05.2 [10de/037f] enabled PCI: 00:06.0 [10de/0370] bus ops PCI: 00:06.0 [10de/0370] enabled PCI: 00:06.1 [10de/0371] ops PCI: 00:06.1 [10de/0371] enabled PCI: 00:08.0 [10de/0373] ops PCI: 00:08.0 [10de/0373] enabled PCI: 00:0a.0 [10de/0376] bus ops PCI: 00:0a.0 [10de/0376] enabled PCI: 00:0c.0 [10de/0374] bus ops PCI: 00:0c.0 [10de/0374] enabled PCI: 00:0d.0 [10de/0378] bus ops PCI: 00:0d.0 [10de/0378] enabled PCI: 00:0f.0 [10de/0377] bus ops PCI: 00:0f.0 [10de/0377] enabled scan_static_bus for PCI: 00:01.0 PNP: 002e.0 enabled PNP: 002e.1 enabled PNP: 002e.2 disabled PNP: 002e.3 enabled PNP: 002e.4 enabled PNP: 002e.5 enabled PNP: 002e.6 enabled PNP: 002e.7 disabled PNP: 002e.8 disabled PNP: 002e.9 disabled PNP: 002e.a disabled scan_static_bus for PCI: 00:01.0 done scan_static_bus for PCI: 00:01.1 smbus: PCI: 00:01.1[0]->I2C: 01:50 enabled smbus: PCI: 00:01.1[0]->I2C: 01:51 enabled smbus: PCI: 00:01.1[0]->I2C: 01:52 enabled smbus: PCI: 00:01.1[0]->I2C: 01:53 enabled scan_static_bus for PCI: 00:01.1 done do_pci_scan_bridge for PCI: 00:06.0 PCI: pci_scan_bus for bus 01 PCI: pci_scan_bus returning with max=001 do_pci_scan_bridge returns max 1 do_pci_scan_bridge for PCI: 00:0a.0 PCI: pci_scan_bus for bus 02 PCI: pci_scan_bus returning with max=002 do_pci_scan_bridge returns max 2 do_pci_scan_bridge for PCI: 00:0c.0 PCI: pci_scan_bus for bus 03 PCI: pci_scan_bus returning with max=003 do_pci_scan_bridge returns max 3 do_pci_scan_bridge for PCI: 00:0d.0 PCI: pci_scan_bus for bus 04 PCI: pci_scan_bus returning with max=004 do_pci_scan_bridge returns max 4 do_pci_scan_bridge for PCI: 00:0f.0 PCI: pci_scan_bus for bus 05 PCI: pci_scan_bus returning with max=005 do_pci_scan_bridge returns max 5 PCI: pci_scan_bus returning with max=005 PCI: pci_scan_bus returning with max=005 PCI_DOMAIN: 0000 passpw: enabled scan_static_bus for Root Device done done Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 APIC_CLUSTER: 0 read_resources bus 0 link: 0 APIC: 00 missing read_resources APIC_CLUSTER: 0 read_resources bus 0 link: 0 done PCI_DOMAIN: 0000 read_resources bus 0 link: 0 PCI: 00:18.0 read_resources bus 0 link: 0 PCI: 00:01.0 read_resources bus 0 link: 0 PCI: 00:01.0 read_resources bus 0 link: 0 done PCI: 00:01.1 read_resources bus 1 link: 0 I2C: 01:50 missing read_resources I2C: 01:51 missing read_resources I2C: 01:52 missing read_resources I2C: 01:53 missing read_resources PCI: 00:01.1 read_resources bus 1 link: 0 done PCI: 00:06.0 read_resources bus 1 link: 0 PCI: 00:06.0 read_resources bus 1 link: 0 done PCI: 00:0a.0 read_resources bus 2 link: 0 PCI: 00:0a.0 read_resources bus 2 link: 0 done PCI: 00:0c.0 read_resources bus 3 link: 0 PCI: 00:0c.0 read_resources bus 3 link: 0 done PCI: 00:0d.0 read_resources bus 4 link: 0 PCI: 00:0d.0 read_resources bus 4 link: 0 done PCI: 00:0f.0 read_resources bus 5 link: 0 PCI: 00:0f.0 read_resources bus 5 link: 0 done PCI: 00:18.0 read_resources bus 0 link: 0 done PCI: 00:18.0 read_resources bus 0 link: 1 PCI: 00:18.0 read_resources bus 0 link: 1 done PCI: 00:18.0 read_resources bus 0 link: 2 PCI: 00:18.0 read_resources bus 0 link: 2 done PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 APIC_CLUSTER: 0 APIC_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 PCI_DOMAIN: 0000 child on link 0 PCI: 00:18.0 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 400400 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40 PCI: 00:18.0 child on link 0 PCI: 00:00.0 PCI: 00:18.0 resource base 33 size 0 align 0 gran 0 limit 3000 flags 1 index0 PCI: 00:18.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80100 0 PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 2 PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 801 PCI: 00:00.0 PCI: 00:01.0 child on link 0 PNP: 002e.0 PCI: 00:01.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flag4 PCI: 00:01.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 PCI: 00:01.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flag0 PCI: 00:01.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags 3 PNP: 002e.0 PNP: 002e.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags c000010 PNP: 002e.0 resource base 6 size 1 align 0 gran 0 limit 0 flags c0000400 i0 PNP: 002e.0 resource base 2 size 1 align 0 gran 0 limit 0 flags c0000800 i4 PNP: 002e.1 PNP: 002e.1 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c000010 PNP: 002e.1 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 i0 PNP: 002e.2 PNP: 002e.2 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 inde0 PNP: 002e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 0 PNP: 002e.3 PNP: 002e.3 resource base 378 size 8 align 3 gran 3 limit 7ff flags c000010 PNP: 002e.3 resource base 0 size 0 align 0 gran 0 limit 0 flags c0000100 i2 PNP: 002e.3 resource base 7 size 1 align 0 gran 0 limit 0 flags c0000400 i0 PNP: 002e.3 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000800 i4 PNP: 002e.4 PNP: 002e.4 resource base 290 size 8 align 3 gran 3 limit 7ff flags c000010 PNP: 002e.4 resource base 0 size 8 align 3 gran 3 limit 7ff flags c00001002 PNP: 002e.4 resource base 0 size 1 align 0 gran 0 limit 0 flags c0000400 i0 PNP: 002e.5 PNP: 002e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags c00 PNP: 002e.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags c02 PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags c0000400 i0 PNP: 002e.6 PNP: 002e.6 resource base c size 1 align 0 gran 0 limit 0 flags c0000400 i0 PNP: 002e.7 PNP: 002e.7 resource base 0 size 0 align 0 gran 0 limit 0 flags c0000100 i0 PNP: 002e.7 resource base 800 size 8 align 3 gran 3 limit 7ff flags c000012 PNP: 002e.7 resource base 0 size 8 align 3 gran 3 limit 7ff flags c00001004 PNP: 002e.8 PNP: 002e.8 resource base 0 size 2 align 1 gran 1 limit 7ff flags 100 inde0 PNP: 002e.8 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 0 PNP: 002e.9 PNP: 002e.9 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 1000 PNP: 002e.a PCI: 00:01.1 child on link 0 I2C: 01:50 PCI: 00:01.1 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 in0 PCI: 00:01.1 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 in0 PCI: 00:01.1 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 in4 PCI: 00:01.1 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 i0 PCI: 00:01.1 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 i4 PCI: 00:01.1 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 i8 I2C: 01:50 I2C: 01:51 I2C: 01:52 I2C: 01:53 PCI: 00:01.2 PCI: 00:01.3 PCI: 00:01.3 resource base 0 size 40000 align 18 gran 18 limit ffffffff fla0 PCI: 00:02.0 PCI: 00:02.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flag0 PCI: 00:02.1 PCI: 00:02.1 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 20 PCI: 00:04.0 PCI: 00:04.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 in0 PCI: 00:05.0 PCI: 00:05.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 ind0 PCI: 00:05.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 ind4 PCI: 00:05.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 ind8 PCI: 00:05.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 indc PCI: 00:05.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 in0 PCI: 00:05.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flag4 PCI: 00:05.1 PCI: 00:05.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 ind0 PCI: 00:05.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 ind4 PCI: 00:05.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 ind8 PCI: 00:05.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 indc PCI: 00:05.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 in0 PCI: 00:05.1 resource base 0 size 1000 align 12 gran 12 limit ffffffff flag4 PCI: 00:05.2 PCI: 00:05.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 ind0 PCI: 00:05.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 ind4 PCI: 00:05.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 ind8 PCI: 00:05.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 indc PCI: 00:05.2 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 in0 PCI: 00:05.2 resource base 0 size 1000 align 12 gran 12 limit ffffffff flag4 PCI: 00:06.0 PCI: 00:06.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102c PCI: 00:06.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 84 PCI: 00:06.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80 PCI: 00:06.1 PCI: 00:06.1 resource base 0 size 4000 align 14 gran 14 limit ffffffff flag0 PCI: 00:08.0 PCI: 00:08.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flag0 PCI: 00:08.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 ind4 PCI: 00:08.0 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 28 PCI: 00:08.0 resource base 0 size 10 align 4 gran 4 limit ffffffff flags 20c PCI: 00:09.0 PCI: 00:0a.0 PCI: 00:0a.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 8c PCI: 00:0a.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff4 PCI: 00:0a.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80 PCI: 00:0b.0 PCI: 00:0c.0 PCI: 00:0c.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 8c PCI: 00:0c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff4 PCI: 00:0c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80 PCI: 00:0d.0 PCI: 00:0d.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 8c PCI: 00:0d.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff4 PCI: 00:0d.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80 PCI: 00:0e.0 PCI: 00:0f.0 PCI: 00:0f.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 8c PCI: 00:0f.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff4 PCI: 00:0f.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80 PCI: 00:18.1 PCI: 00:18.2 PCI: 00:18.3 PCI: 00:18.3 resource base 0 size 4000000 align 26 gran 26 limit ffffffff fl4 PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: f PCI: 00:18.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: fff PCI: 00:06.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: fff PCI: 00:06.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffe PCI: 00:0a.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: fff PCI: 00:0a.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffe PCI: 00:0c.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: fff PCI: 00:0c.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffe PCI: 00:0d.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: fff PCI: 00:0d.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffe PCI: 00:0f.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: fff PCI: 00:0f.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffe PCI: 00:01.1 60 * [0x0 - 0xff] io PCI: 00:01.1 64 * [0x400 - 0x4ff] io PCI: 00:01.1 68 * [0x800 - 0x8ff] io PCI: 00:01.1 10 * [0xc00 - 0xc3f] io PCI: 00:01.1 20 * [0xc40 - 0xc7f] io PCI: 00:01.1 24 * [0xc80 - 0xcbf] io PCI: 00:04.0 20 * [0xcc0 - 0xccf] io PCI: 00:05.0 20 * [0xcd0 - 0xcdf] io PCI: 00:05.1 20 * [0xce0 - 0xcef] io PCI: 00:05.2 20 * [0xcf0 - 0xcff] io PCI: 00:05.0 10 * [0x1000 - 0x1007] io PCI: 00:05.0 18 * [0x1008 - 0x100f] io PCI: 00:05.1 10 * [0x1010 - 0x1017] io PCI: 00:05.1 18 * [0x1018 - 0x101f] io PCI: 00:05.2 10 * [0x1020 - 0x1027] io PCI: 00:05.2 18 * [0x1028 - 0x102f] io PCI: 00:08.0 14 * [0x1030 - 0x1037] io PCI: 00:05.0 14 * [0x1038 - 0x103b] io PCI: 00:05.0 1c * [0x103c - 0x103f] io PCI: 00:05.1 14 * [0x1040 - 0x1043] io PCI: 00:05.1 1c * [0x1044 - 0x1047] io PCI: 00:05.2 14 * [0x1048 - 0x104b] io PCI: 00:05.2 1c * [0x104c - 0x104f] io PCI: 00:18.0 compute_resources_io: base: 1050 size: 2000 align: 12 gran: 12 lime PCI: 00:18.0 00 * [0x0 - 0x1fff] io PCI_DOMAIN: 0000 compute_resources_io: base: 2000 size: 2000 align: 12 gran: 0 e PCI_DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit:f PCI: 00:18.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limif PCI: 00:06.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limif PCI: 00:06.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limie PCI: 00:0a.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limif PCI: 00:0a.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limie PCI: 00:0c.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limif PCI: 00:0c.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limie PCI: 00:0d.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limif PCI: 00:0d.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limie PCI: 00:0f.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limif PCI: 00:0f.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limie PCI: 00:18.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limie PCI: 00:18.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ff PCI: 00:06.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ff PCI: 00:06.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: fe PCI: 00:0a.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ff PCI: 00:0a.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: fe PCI: 00:0c.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ff PCI: 00:0c.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: fe PCI: 00:0d.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ff PCI: 00:0d.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: fe PCI: 00:0f.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ff PCI: 00:0f.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: fe PCI: 00:01.3 10 * [0x0 - 0x3ffff] mem PCI: 00:06.1 10 * [0x40000 - 0x43fff] mem PCI: 00:01.0 14 * [0x44000 - 0x44fff] mem PCI: 00:02.0 10 * [0x45000 - 0x45fff] mem PCI: 00:05.0 24 * [0x46000 - 0x46fff] mem PCI: 00:05.1 24 * [0x47000 - 0x47fff] mem PCI: 00:05.2 24 * [0x48000 - 0x48fff] mem PCI: 00:08.0 10 * [0x49000 - 0x49fff] mem PCI: 00:02.1 10 * [0x4a000 - 0x4a0ff] mem PCI: 00:08.0 18 * [0x4a100 - 0x4a1ff] mem PCI: 00:08.0 1c * [0x4a200 - 0x4a20f] mem PCI: 00:18.0 compute_resources_mem: base: 4a210 size: 100000 align: 20 gran: 20e PCI: 00:18.3 94 * [0x0 - 0x3ffffff] mem PCI: 00:18.0 01 * [0x4000000 - 0x40fffff] mem PCI_DOMAIN: 0000 compute_resources_mem: base: 4100000 size: 4100000 align: 26 ge avoid_fixed_resources: PCI_DOMAIN: 0000 avoid_fixed_resources:@PCI_DOMAIN: 0000 10000000 limit 0000ffff avoid_fixed_resources:@PCI_DOMAIN: 0000 10000100 limit ffffffff constrain_resources: PCI_DOMAIN: 0000 constrain_resources: PCI: 00:18.0 constrain_resources: PCI: 00:00.0 constrain_resources: PCI: 00:01.0 constrain_resources: PNP: 002e.0 constrain_resources: PNP: 002e.1 constrain_resources: PNP: 002e.3 skipping PNP: 002e.3@62 fixed resource, size=0! constrain_resources: PNP: 002e.4 constrain_resources: PNP: 002e.5 constrain_resources: PNP: 002e.6 constrain_resources: PCI: 00:01.1 constrain_resources: I2C: 01:50 constrain_resources: I2C: 01:51 constrain_resources: I2C: 01:52 constrain_resources: I2C: 01:53 constrain_resources: PCI: 00:01.2 constrain_resources: PCI: 00:01.3 constrain_resources: PCI: 00:02.0 constrain_resources: PCI: 00:02.1 constrain_resources: PCI: 00:04.0 constrain_resources: PCI: 00:05.0 constrain_resources: PCI: 00:05.1 constrain_resources: PCI: 00:05.2 constrain_resources: PCI: 00:06.0 constrain_resources: PCI: 00:06.1 constrain_resources: PCI: 00:08.0 constrain_resources: PCI: 00:0a.0 constrain_resources: PCI: 00:0c.0 constrain_resources: PCI: 00:0d.0 constrain_resources: PCI: 00:0f.0 constrain_resources: PCI: 00:18.1 constrain_resources: PCI: 00:18.2 constrain_resources: PCI: 00:18.3 avoid_fixed_resources2: PCI_DOMAIN: 0000@10000000 limit 0000ffff lim->base 00001000 lim->limit 0000ffff avoid_fixed_resources2: PCI_DOMAIN: 0000@10000100 limit ffffffff lim->base 00000000 lim->limit febfffff Setting resources... PCI_DOMAIN: 0000 allocate_resources_io: base:1000 size:2000 align:12 gran:0 limf Assigned: PCI: 00:18.0 00 * [0x1000 - 0x2fff] io PCI_DOMAIN: 0000 allocate_resources_io: next_base: 3000 size: 2000 align: 12 gre PCI: 00:18.0 allocate_resources_io: base:1000 size:2000 align:12 gran:12 limit:f Assigned: PCI: 00:01.1 60 * [0x1000 - 0x10ff] io Assigned: PCI: 00:01.1 64 * [0x1400 - 0x14ff] io Assigned: PCI: 00:01.1 68 * [0x1800 - 0x18ff] io Assigned: PCI: 00:01.1 10 * [0x1c00 - 0x1c3f] io Assigned: PCI: 00:01.1 20 * [0x1c40 - 0x1c7f] io Assigned: PCI: 00:01.1 24 * [0x1c80 - 0x1cbf] io Assigned: PCI: 00:04.0 20 * [0x1cc0 - 0x1ccf] io Assigned: PCI: 00:05.0 20 * [0x1cd0 - 0x1cdf] io Assigned: PCI: 00:05.1 20 * [0x1ce0 - 0x1cef] io Assigned: PCI: 00:05.2 20 * [0x1cf0 - 0x1cff] io Assigned: PCI: 00:05.0 10 * [0x2000 - 0x2007] io Assigned: PCI: 00:05.0 18 * [0x2008 - 0x200f] io Assigned: PCI: 00:05.1 10 * [0x2010 - 0x2017] io Assigned: PCI: 00:05.1 18 * [0x2018 - 0x201f] io Assigned: PCI: 00:05.2 10 * [0x2020 - 0x2027] io Assigned: PCI: 00:05.2 18 * [0x2028 - 0x202f] io Assigned: PCI: 00:08.0 14 * [0x2030 - 0x2037] io Assigned: PCI: 00:05.0 14 * [0x2038 - 0x203b] io Assigned: PCI: 00:05.0 1c * [0x203c - 0x203f] io Assigned: PCI: 00:05.1 14 * [0x2040 - 0x2043] io Assigned: PCI: 00:05.1 1c * [0x2044 - 0x2047] io Assigned: PCI: 00:05.2 14 * [0x2048 - 0x204b] io Assigned: PCI: 00:05.2 1c * [0x204c - 0x204f] io PCI: 00:18.0 allocate_resources_io: next_base: 2050 size: 2000 align: 12 gran: e PCI: 00:06.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:06.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 e PCI: 00:0a.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:0a.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 e PCI: 00:0c.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:0c.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 e PCI: 00:0d.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:0d.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 e PCI: 00:0f.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:0f.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 e PCI_DOMAIN: 0000 allocate_resources_mem: base:f8000000 size:4100000 align:26 grf Assigned: PCI: 00:18.3 94 * [0xf8000000 - 0xfbffffff] mem Assigned: PCI: 00:18.0 01 * [0xfc000000 - 0xfc0fffff] mem PCI_DOMAIN: 0000 allocate_resources_mem: next_base: fc100000 size: 4100000 alige PCI: 00:18.0 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 f PCI: 00:18.0 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 e PCI: 00:06.0 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 f PCI: 00:06.0 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 e PCI: 00:0a.0 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 f PCI: 00:0a.0 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 e PCI: 00:0c.0 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 f PCI: 00:0c.0 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 e PCI: 00:0d.0 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 f PCI: 00:0d.0 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 e PCI: 00:0f.0 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 f PCI: 00:0f.0 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 e PCI: 00:18.0 allocate_resources_mem: base:fc000000 size:100000 align:20 gran:20f Assigned: PCI: 00:01.3 10 * [0xfc000000 - 0xfc03ffff] mem Assigned: PCI: 00:06.1 10 * [0xfc040000 - 0xfc043fff] mem Assigned: PCI: 00:01.0 14 * [0xfc044000 - 0xfc044fff] mem Assigned: PCI: 00:02.0 10 * [0xfc045000 - 0xfc045fff] mem Assigned: PCI: 00:05.0 24 * [0xfc046000 - 0xfc046fff] mem Assigned: PCI: 00:05.1 24 * [0xfc047000 - 0xfc047fff] mem Assigned: PCI: 00:05.2 24 * [0xfc048000 - 0xfc048fff] mem Assigned: PCI: 00:08.0 10 * [0xfc049000 - 0xfc049fff] mem Assigned: PCI: 00:02.1 10 * [0xfc04a000 - 0xfc04a0ff] mem Assigned: PCI: 00:08.0 18 * [0xfc04a100 - 0xfc04a1ff] mem Assigned: PCI: 00:08.0 1c * [0xfc04a200 - 0xfc04a20f] mem PCI: 00:18.0 allocate_resources_mem: next_base: fc04a210 size: 100000 align: 20e PCI: 00:06.0 allocate_resources_mem: base:febfffff size:0 align:20 gran:20 limif PCI: 00:06.0 allocate_resources_mem: next_base: febfffff size: 0 align: 20 grane PCI: 00:0a.0 allocate_resources_mem: base:febfffff size:0 align:20 gran:20 limif PCI: 00:0a.0 allocate_resources_mem: next_base: febfffff size: 0 align: 20 grane PCI: 00:0c.0 allocate_resources_mem: base:febfffff size:0 align:20 gran:20 limif PCI: 00:0c.0 allocate_resources_mem: next_base: febfffff size: 0 align: 20 grane PCI: 00:0d.0 allocate_resources_mem: base:febfffff size:0 align:20 gran:20 limif PCI: 00:0d.0 allocate_resources_mem: next_base: febfffff size: 0 align: 20 grane PCI: 00:0f.0 allocate_resources_mem: base:febfffff size:0 align:20 gran:20 limif PCI: 00:0f.0 allocate_resources_mem: next_base: febfffff size: 0 align: 20 grane Root Device assign_resources, bus 0 link: 0 0: mmio_basek=003e0000, basek=00000300, limitk=00080000 PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 PCI: 00:18.0 1c0 <- [0x0000001000 - 0x0000002fff] size 0x00002000 gran 0x0c io > PCI: 00:18.0 1b8 <- [0x00fc000000 - 0x00fc0fffff] size 0x00100000 gran 0x14 mem> PCI: 00:18.0 assign_resources, bus 0 link: 0 PCI: 00:01.0 14 <- [0x00fc044000 - 0x00fc044fff] size 0x00001000 gran 0x0c mem PCI: 00:01.0 assign_resources, bus 0 link: 0 PNP: 002e.0 60 <- [0x00000003f0 - 0x00000003f7] size 0x00000008 gran 0x03 io PNP: 002e.0 70 <- [0x0000000006 - 0x0000000006] size 0x00000001 gran 0x00 irq PNP: 002e.0 74 <- [0x0000000002 - 0x0000000002] size 0x00000001 gran 0x00 drq PNP: 002e.1 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io PNP: 002e.1 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq PNP: 002e.3 60 <- [0x0000000378 - 0x000000037f] size 0x00000008 gran 0x03 io PNP: 002e.3 62 <- [0x0000000000 - 0xffffffffffffffff] size 0x00000000 gran 0x00o PNP: 002e.3 70 <- [0x0000000007 - 0x0000000007] size 0x00000001 gran 0x00 irq PNP: 002e.3 74 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 drq PNP: 002e.4 60 <- [0x0000000290 - 0x0000000297] size 0x00000008 gran 0x03 io PNP: 002e.4 62 <- [0x0000000000 - 0x0000000007] size 0x00000008 gran 0x03 io PNP: 002e.4 70 <- [0x0000000000 - 0x0000000000] size 0x00000001 gran 0x00 irq PNP: 002e.5 60 <- [0x0000000060 - 0x0000000060] size 0x00000001 gran 0x00 io PNP: 002e.5 62 <- [0x0000000064 - 0x0000000064] size 0x00000001 gran 0x00 io PNP: 002e.5 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00 irq PNP: 002e.6 70 <- [0x000000000c - 0x000000000c] size 0x00000001 gran 0x00 irq PCI: 00:01.0 assign_resources, bus 0 link: 0 PCI: 00:01.1 10 <- [0x0000001c00 - 0x0000001c3f] size 0x00000040 gran 0x06 io PCI: 00:01.1 20 <- [0x0000001c40 - 0x0000001c7f] size 0x00000040 gran 0x06 io PCI: 00:01.1 24 <- [0x0000001c80 - 0x0000001cbf] size 0x00000040 gran 0x06 io PCI: 00:01.1 60 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io PCI: 00:01.1 64 <- [0x0000001400 - 0x00000014ff] size 0x00000100 gran 0x08 io PCI: 00:01.1 68 <- [0x0000001800 - 0x00000018ff] size 0x00000100 gran 0x08 io PCI: 00:01.1 assign_resources, bus 1 link: 0 PCI: 00:01.1 assign_resources, bus 1 link: 0 PCI: 00:01.3 10 <- [0x00fc000000 - 0x00fc03ffff] size 0x00040000 gran 0x12 mem PCI: 00:02.0 10 <- [0x00fc045000 - 0x00fc045fff] size 0x00001000 gran 0x0c mem PCI: 00:02.1 10 <- [0x00fc04a000 - 0x00fc04a0ff] size 0x00000100 gran 0x08 mem PCI: 00:04.0 20 <- [0x0000001cc0 - 0x0000001ccf] size 0x00000010 gran 0x04 io PCI: 00:05.0 10 <- [0x0000002000 - 0x0000002007] size 0x00000008 gran 0x03 io PCI: 00:05.0 14 <- [0x0000002038 - 0x000000203b] size 0x00000004 gran 0x02 io PCI: 00:05.0 18 <- [0x0000002008 - 0x000000200f] size 0x00000008 gran 0x03 io PCI: 00:05.0 1c <- [0x000000203c - 0x000000203f] size 0x00000004 gran 0x02 io PCI: 00:05.0 20 <- [0x0000001cd0 - 0x0000001cdf] size 0x00000010 gran 0x04 io PCI: 00:05.0 24 <- [0x00fc046000 - 0x00fc046fff] size 0x00001000 gran 0x0c mem PCI: 00:05.1 10 <- [0x0000002010 - 0x0000002017] size 0x00000008 gran 0x03 io PCI: 00:05.1 14 <- [0x0000002040 - 0x0000002043] size 0x00000004 gran 0x02 io PCI: 00:05.1 18 <- [0x0000002018 - 0x000000201f] size 0x00000008 gran 0x03 io PCI: 00:05.1 1c <- [0x0000002044 - 0x0000002047] size 0x00000004 gran 0x02 io PCI: 00:05.1 20 <- [0x0000001ce0 - 0x0000001cef] size 0x00000010 gran 0x04 io PCI: 00:05.1 24 <- [0x00fc047000 - 0x00fc047fff] size 0x00001000 gran 0x0c mem PCI: 00:05.2 10 <- [0x0000002020 - 0x0000002027] size 0x00000008 gran 0x03 io PCI: 00:05.2 14 <- [0x0000002048 - 0x000000204b] size 0x00000004 gran 0x02 io PCI: 00:05.2 18 <- [0x0000002028 - 0x000000202f] size 0x00000008 gran 0x03 io PCI: 00:05.2 1c <- [0x000000204c - 0x000000204f] size 0x00000004 gran 0x02 io PCI: 00:05.2 20 <- [0x0000001cf0 - 0x0000001cff] size 0x00000010 gran 0x04 io PCI: 00:05.2 24 <- [0x00fc048000 - 0x00fc048fff] size 0x00001000 gran 0x0c mem PCI: 00:06.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus o PCI: 00:06.0 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus m PCI: 00:06.0 20 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus m PCI: 00:06.1 10 <- [0x00fc040000 - 0x00fc043fff] size 0x00004000 gran 0x0e mem PCI: 00:08.0 10 <- [0x00fc049000 - 0x00fc049fff] size 0x00001000 gran 0x0c mem PCI: 00:08.0 14 <- [0x0000002030 - 0x0000002037] size 0x00000008 gran 0x03 io PCI: 00:08.0 18 <- [0x00fc04a100 - 0x00fc04a1ff] size 0x00000100 gran 0x08 mem PCI: 00:08.0 1c <- [0x00fc04a200 - 0x00fc04a20f] size 0x00000010 gran 0x04 mem PCI: 00:0a.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus o PCI: 00:0a.0 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus m PCI: 00:0a.0 20 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus m PCI: 00:0c.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus o PCI: 00:0c.0 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus m PCI: 00:0c.0 20 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus m PCI: 00:0d.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus o PCI: 00:0d.0 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus m PCI: 00:0d.0 20 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus m PCI: 00:0f.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus o PCI: 00:0f.0 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus m PCI: 00:0f.0 20 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus m PCI: 00:18.0 assign_resources, bus 0 link: 0 PCI: 00:18.3 94 <- [0x00f8000000 - 0x00fbffffff] size 0x04000000 gran 0x1a mem > PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device child on link 0 APIC_CLUSTER: 0 APIC_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 PCI_DOMAIN: 0000 child on link 0 PCI: 00:18.0 PCI_DOMAIN: 0000 resource base 1000 size 2000 align 12 gran 0 limit ffff flag0 PCI_DOMAIN: 0000 resource base f8000000 size 4100000 align 26 gran 0 limit fe0 PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0000 PCI_DOMAIN: 0000 resource base 2012/1/30 Julian Shulika <hercares(a)gmail.com> > Hi. I compiled coreboot image for Asus m2n-e (mcp55,ite 8716f). This board > turns off after few seconds > The log from serial > > Welcome to minicom 2.5 > > OPTIONS: > > Compiled on Dec 4 2011, > 11:23:38. > Port > /dev/ttyS0 > > > Press CTRL-A Z for help on special > keys > > > > > > > coreboot-4.0-1980-gcc16cca-dirty Sat Jan 28 15:06:08 EST 2012 > starting... > *sysinfo range: > [000cf000,000cf730] > bsp_apicid=0x00 > > Enabling routing table for node 00 done. > Enabling UP settings > Disabling read/write/fill probes for UP... done. > coherent_ht_finalize > done > core0 started: > started ap apicid: > SBLink=00 > NC node|link=00 > entering > optimize_link_incoherent_ht > sysinfo->link_pair_num=0x1 > > entering > ht_optimize_link > pos=0x8a, unfiltered > freq_cap=0x8075 > pos=0x8a, filtered > freq_cap=0x75 > pos=0x52, unfiltered > freq_cap=0x807f > pos=0x52, filtered > freq_cap=0x7f > freq_cap1=0x75, > freq_cap2=0x7f > dev1 old_freq=0x0, freq=0x6, > needs_reset=0x1 > dev2 old_freq=0x0, freq=0x6, > needs_reset=0x1 > width_cap1=0x11, > width_cap2=0x11 > dev1 input ln_width1=0x4, > ln_width2=0x4 > dev1 input > width=0x1 > dev1 output ln_width1=0x4, > ln_width2=0x4 > dev1 input|output > width=0x11 > old dev1 input|output > width=0x11 > dev2 input|output > width=0x11 > old dev2 input|output > width=0x11 > after ht_optimize_link for link pair 0, > reset_needed=0x1 > after optimize_link_read_pointers_chain, > reset_needed=0x1 > mcp55_num:01 > > ht reset > - > > > > > coreboot-4.0-1980-gcc16cca-dirty Sat Jan 28 15:06:08 EST 2012 > starting... > *sysinfo range: > [000cf000,000cf730] > bsp_apicid=0x00 > > Enabling routing table for node 00 > done. > Enabling UP > settings > Disabling read/write/fill probes for UP... > done. > coherent_ht_finalize > > done > > core0 > started: > started ap > apicid: > SBLink=00 > > NC > node|link=00 > > entering > optimize_link_incoherent_ht > sysinfo->link_pair_num=0x1 > > entering > ht_optimize_link > pos=0x8a, unfiltered > freq_cap=0x8075 > pos=0x8a, filtered > freq_cap=0x75 > pos=0x52, unfiltered > freq_cap=0x7f > pos=0x52, filtered > freq_cap=0x7f > freq_cap1=0x75, > freq_cap2=0x7f > dev1 old_freq=0x6, freq=0x6, > needs_reset=0x0 > dev2 old_freq=0x6, freq=0x6, > needs_reset=0x0 > width_cap1=0x11, > width_cap2=0x11 > dev1 input ln_width1=0x4, > ln_width2=0x4 > dev1 input > width=0x1 > dev1 output ln_width1=0x4, > ln_width2=0x4 > dev1 input|output > width=0x11 > old dev1 input|output > width=0x11 > dev2 input|output > width=0x11 > old dev2 input|output > width=0x11 > after ht_optimize_link for link pair 0, > reset_needed=0x0 > after optimize_link_read_pointers_chain, > reset_needed=0x0 > mcp55_num:01 > > Ram1.00 > > setting up CPU 00 northbridge > registers > done. > > Ram2.00 > > sdram_set_spd_registers: paramx > :000cef20 > Enable 64MuxMode & > BurstLength32 > Unbuffered > > 333MHz > > 333MHz > > set_ecc spd_device: > 0x51 > Interleaving > disabled > RAM end at 0x00080000 > kB > Ram3 > > ECC > enabled > Initializing memory: > done > Setting variable MTRR 2, base: 0MB, range: 512MB, type > WB > set DQS timing:RcvrEn:Pass1: > 00 > CTLRMaxDelay=03 > > done > > set DQS timing:DQSPos: > 00 > TrainDQSRdWrPos: > buf_a:000ce9f0 > TrainDQSPos: MutualCSPassW[48] > :000ce8c8 > TrainDQSPos: MutualCSPassW[48] > :000ce8c8 > TrainDQSPos: MutualCSPassW[48] > :000ce8c8 > TrainDQSPos: MutualCSPassW[48] > :000ce8d8 > done > > set DQS timing:RcvrEn:Pass2: > 00 > CTLRMaxDelay=58 > > done > > Total DQS Training : tsc > [00]=0000000012e40bef > Total DQS Training : tsc > [01]=000000001358f446 > Total DQS Training : tsc > [02]=0000000018d60c82 > Total DQS Training : tsc > [03]=0000000019771d46 > Ram4 > > v_esp=000cef68 > > testx = > 5a5a5a5a > > > > > > INIT detected from --- { APICID = 00 NODEID = 00 COREID = 00} > --- > > > Issuing > SOFT_RESET... > > > > > coreboot-4.0-1980-gcc16cca-dirty Sat Jan 28 15:06:08 EST 2012 > starting... > *sysinfo range: > [000cf000,000cf730] > bsp_apicid=0x00 > > Enabling routing table for node 00 > done. > Enabling UP > settings > Disabling read/write/fill probes for UP... > done. > coherent_ht_finalize > > done > > core0 > started: > started ap > apicid: > SBLink=00 > > NC > node|link=00 > > entering > optimize_link_incoherent_ht > sysinfo->link_pair_num=0x1 > > entering > ht_optimize_link > pos=0x8a, unfiltered > freq_cap=0x8075 > pos=0x8a, filtered > freq_cap=0x75 > pos=0x52, unfiltered > freq_cap=0x7f > pos=0x52, filtered > freq_cap=0x7f > freq_cap1=0x75, > freq_cap2=0x7f > dev1 old_freq=0x6, freq=0x6, > needs_reset=0x0 > dev2 old_freq=0x6, freq=0x6, > needs_reset=0x0 > width_cap1=0x11, > width_cap2=0x11 > dev1 input ln_width1=0x4, > ln_width2=0x4 > dev1 input > width=0x1 > dev1 output ln_width1=0x4, > ln_width2=0x4 > dev1 input|output > width=0x11 > old dev1 input|output > width=0x11 > dev2 input|output > width=0x11 > old dev2 input|output > width=0x11 > after ht_optimize_link for link pair 0, > reset_needed=0x0 > after optimize_link_read_pointers_chain, > reset_needed=0x0 > mcp55_num:01 > > Ram1.00 > > setting up CPU 00 northbridge > registers > done. > > Ram2.00 > > sdram_set_spd_registers: paramx > :000cef20 > Enable 64MuxMode & > BurstLength32 > Unbuffered > > 333MHz > > 333MHz > > set_ecc spd_device: > 0x51 > Interleaving > disabled > RAM end at 0x00080000 > kB > Ram3 > > ECC > enabled > Initializing memory: > done > Setting variable MTRR 2, base: 0MB, range: 512MB, type > WB > set DQS timing:RcvrEn:Pass1: > 00 > CTLRMaxDelay=03 > > done > > set DQS timing:DQSPos: > 00 > TrainDQSRdWrPos: > buf_a:000ce9f0 > TrainDQSPos: MutualCSPassW[48] > :000ce8c8 > TrainDQSPos: MutualCSPassW[48] > :000ce8c8 > TrainDQSPos: MutualCSPassW[48] > :000ce8c8 > TrainDQSPos: MutualCSPassW[48] > :000ce8d8 > done > > set DQS timing:RcvrEn:Pass2: > 00 > CTLRMaxDelay=58 > > done > > Total DQS Training : tsc > [00]=0000000012e3eacf > Total DQS Training : tsc > [01]=000000001358d326 > Total DQS Training : tsc > [02]=0000000018d97cfa > Total DQS Training : tsc > [03]=00000000197a8c56 > Ram4 > > v_esp=000cef68 > > testx = > 5a5a5a5a > Copying data from cache to RAM -- switching to use RAM as stack... > D > > > > > INIT detected from --- { APICID = 00 NODEID = 00 COREID = 00} > --- > > > Issuing > SOFT_RESET... > > > > > coreboot-4.0-1980-gcc16cca-dirty Sat Jan 28 15:06:08 EST 2012 > starting... > *sysinfo range: > [000cf000,000cf730] > bsp_apicid=0x00 > > Enabling routing table for node 00 > done. > Enabling UP > settings > Disabling read/write/fill probes for UP... > done. > coherent_ht_finalize > > done > > core0 > started: > started ap > apicid: > SBLink=00 > > NC > node|link=00 > > entering > optimize_link_incoherent_ht > sysinfo->link_pair_num=0x1 > > entering > ht_optimize_link > pos=0x8a, unfiltered > freq_cap=0x8075 > pos=0x8a, filtered > freq_cap=0x75 > pos=0x52, unfiltered > freq_cap=0x7f > pos=0x52, filtered > freq_cap=0x7f > freq_cap1=0x75, > freq_cap2=0x7f > dev1 old_freq=0x6, freq=0x6, > needs_reset=0x0 > dev2 old_freq=0x6, freq=0x6, > needs_reset=0x0 > width_cap1=0x11, > width_cap2=0x11 > dev1 input ln_width1=0x4, > ln_width2=0x4 > dev1 input > width=0x1 > dev1 output ln_width1=0x4, > ln_width2=0x4 > dev1 input|output > width=0x11 > old dev1 input|output > width=0x11 > dev2 input|output > width=0x11 > old dev2 input|output > width=0x11 > after ht_optimize_link for link pair 0, > reset_needed=0x0 > after optimize_link_read_pointers_chain, > reset_needed=0x0 > mcp55_num:01 > > Ram1.00 > > setting up CPU 00 northbridge > registers > done. > > Ram2.00 > > sdram_set_spd_registers: paramx > :000cef20 > Enable 64MuxMode & > BurstLength32 > Unbuffered > > 333MHz > > 333MHz > > set_ecc spd_device: > 0x51 > Interleaving > disabled > RAM end at 0x00080000 > kB > Ram3 > > ECC > enabled > Initializing memory: > done > Setting variable MTRR 2, base: 0MB, range: 512MB, type > WB > set DQS timing:RcvrEn:Pass1: > 00 > CTLRMaxDelay=03 > > done > > set DQS timing:DQSPos: > 00 > TrainDQSRdWrPos: > buf_a:000ce9f0 > TrainDQSPos: MutualCSPassW[48] > :000ce8c8 > TrainDQSPos: MutualCSPassW[48] > :000ce8c8 > TrainDQSPos: MutualCSPassW[48] > :000ce8c8 > TrainDQSPos: MutualCSPassW[48] > :000ce8d8 > done > > set DQS timing:RcvrEn:Pass2: > 00 > CTLRMaxDelay=58 > > done > > Total DQS Training : tsc > [00]=0000000012e3ed63 > Total DQS Training : tsc > [01]=000000001358f68a > Total DQS Training : tsc > [02]=0000000018d73a6a > Total DQS Training : tsc > [03]=0000000019784e5a > Ram4 > > v_esp=000cef68 > > testx = > 5a5a5a5a > Copying data from cache to RAM -- switching to use RAM as stack... > m > > > > > INIT detected from --- { APICID = 00 NODEID = 00 COREID = 00} > --- > > > Issuing > SOFT_RESET... > > > > > coreboot-4.0-1980-gcc16cca-dirty Sat Jan 28 15:06:08 EST 2012 > starting... > *sysinfo range: > [000cf000,000cf730] > bsp_apicid=0x00 > > Enabling routing table for node 00 > done. > Enabling UP > settings > Disabling read/write/fill probes for UP... > done. > coherent_ht_finalize > > done > > core0 > started: > started ap > apicid: > SBLink=00 > > NC > node|link=00 > > entering > optimize_link_incoherent_ht > sysinfo->link_pair_num=0x1 > > entering > ht_optimize_link > pos=0x8a, unfiltered > freq_cap=0x8075 > pos=0x8a, filtered > freq_cap=0x75 > pos=0x52, unfiltered > freq_cap=0x7f > pos=0x52, filtered > freq_cap=0x7f > freq_cap1=0x75, > freq_cap2=0x7f > dev1 old_freq=0x6, freq=0x6, > needs_reset=0x0 > dev2 old_freq=0x6, freq=0x6, > needs_reset=0x0 > width_cap1=0x11, > width_cap2=0x11 > dev1 input ln_width1=0x4, > ln_width2=0x4 > dev1 input > width=0x1 > dev1 output ln_width1=0x4, > ln_width2=0x4 > dev1 input|output > width=0x11 > old dev1 input|output > width=0x11 > dev2 input|output > width=0x11 > old dev2 input|output > width=0x11 > after ht_optimize_link for link pair 0, > reset_needed=0x0 > after optimize_link_read_pointers_chain, > reset_needed=0x0 > mcp55_num:01 > > Ram1.00 > > setting up CPU 00 northbridge > registers > done. > > Ram2.00 > > sdram_set_spd_registers: paramx > :000cef20 > Enable 64MuxMode & > BurstLength32 > Unbuffered > > 333MHz > > 333MHz > > set_ecc spd_device: > 0x51 > Interleaving > disabled > RAM end at 0x00080000 > kB > Ram3 > > ECC > enabled > Initializing memory: > done > Setting variable MTRR 2, base: 0MB, range: 512MB, type > WB > set DQS timing:RcvrEn:Pass1: > 00 > CTLRMaxDelay=03 > > done > > set DQS timing:DQSPos: > 00 > TrainDQSRdWrPos: > buf_a:000ce9f0 > TrainDQSPos: MutualCSPassW[48] > :000ce8c8 > TrainDQSPos: MutualCSPassW[48] > :000ce8c8 > TrainDQSPos: MutualCSPassW[48] > :000ce8c8 > TrainDQSPos: MutualCSPassW[48] > :000ce8d8 > done > > set DQS timing:RcvrEn:Pass2: > 00 > CTLRMaxDelay=58 > > done > > Total DQS Training : tsc > [00]=0000000012e4504b > Total DQS Training : tsc > [01]=0000000013593c4a > Total DQS Training : tsc > [02]=0000000018d6d4b2 > Total DQS Training : tsc > [03]=000000001977e9ce > Ram4 > > v_esp=000cef68 > > testx = > 5a5a5a5a > Copying data from cache to RAM -- switching to use RAM as stack... > >

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Patch merged into coreboot/master: 69470aa libpayload: Add iterators for CMOS variables
by gerrit＠coreboot.org 03 Feb '12

03 Feb '12

the following patch was just integrated into master: commit 69470aacda54a628fb7d6437198fc2eddb314009 Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Mon Jan 16 15:39:57 2012 +0100 libpayload: Add iterators for CMOS variables Provide functions that pick the first CMOS variable defined in the cmos layout, and from there, the next one. Change-Id: Ie98146de7f6273089fc6fc0b232a4b94337cf8a3 Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Fri Feb 3 13:22:47 2012, giving +2 See http://review.coreboot.org/587 for details. -gerrit

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coreboot February 2012