coreboot February 2012

coreboot@coreboot.org

34 participants
348 discussions

Patch set updated for coreboot: 44e8b03 SIO: Add smsc/sch4037 superio support
by Kerry Sheh 03 Feb '12

03 Feb '12

Kerry Sheh (shekairui(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/562 -gerrit commit 44e8b03e634c0b236dc7f252104c2399757c6145 Author: Kerry Sheh <shekairui(a)gmail.com> Date: Fri Feb 3 12:23:58 2012 +0800 SIO: Add smsc/sch4037 superio support Change-Id: I3b113a27541b8efd096f3bd44e6621344ec916a5 Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> --- src/superio/smsc/Kconfig | 3 + src/superio/smsc/Makefile.inc | 2 + src/superio/smsc/sch4037/Makefile.inc | 20 ++++ src/superio/smsc/sch4037/chip.h | 34 +++++++ src/superio/smsc/sch4037/sch4037.h | 34 +++++++ src/superio/smsc/sch4037/sch4037_early_init.c | 71 ++++++++++++++ src/superio/smsc/sch4037/superio.c | 123 +++++++++++++++++++++++++ 7 files changed, 287 insertions(+), 0 deletions(-) diff --git a/src/superio/smsc/Kconfig b/src/superio/smsc/Kconfig index 7378d18..ddd5b96 100644 --- a/src/superio/smsc/Kconfig +++ b/src/superio/smsc/Kconfig @@ -2,6 +2,7 @@ ## This file is part of the coreboot project. ## ## Copyright (C) 2009 Ronald G. Minnich +## Copyright (C) 2012 Advanced Micro Devices, Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -39,3 +40,5 @@ config SUPERIO_SMSC_KBC1100 bool config SUPERIO_SMSC_SMSCSUPERIO bool +config SUPERIO_SMSC_SCH4037 + bool diff --git a/src/superio/smsc/Makefile.inc b/src/superio/smsc/Makefile.inc index 68d4d56..bfdc68e 100644 --- a/src/superio/smsc/Makefile.inc +++ b/src/superio/smsc/Makefile.inc @@ -2,6 +2,7 @@ ## This file is part of the coreboot project. ## ## Copyright (C) 2009 Ronald G. Minnich +## Copyright (C) 2012 Advanced Micro Devices, Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -28,3 +29,4 @@ subdirs-y += lpc47n227 subdirs-y += sio10n268 subdirs-y += kbc1100 subdirs-y += smscsuperio +subdirs-y += sch4037 diff --git a/src/superio/smsc/sch4037/Makefile.inc b/src/superio/smsc/sch4037/Makefile.inc new file mode 100644 index 0000000..8f36f2a --- /dev/null +++ b/src/superio/smsc/sch4037/Makefile.inc @@ -0,0 +1,20 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +ramstage-$(CONFIG_SUPERIO_SMSC_SCH4037) += superio.c diff --git a/src/superio/smsc/sch4037/chip.h b/src/superio/smsc/sch4037/chip.h new file mode 100644 index 0000000..3223750 --- /dev/null +++ b/src/superio/smsc/sch4037/chip.h @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_SCH_4037_CHIP_H +#define SUPERIO_SCH_4037_CHIP_H + +#include <pc80/keyboard.h> +#include <uart8250.h> + +struct chip_operations; +extern struct chip_operations superio_smsc_sch4037_ops; + +struct superio_smsc_sch4037_config { + + struct pc_keyboard keyboard; +}; + +#endif //SUPERIO_SCH_4037_CHIP_H \ No newline at end of file diff --git a/src/superio/smsc/sch4037/sch4037.h b/src/superio/smsc/sch4037/sch4037.h new file mode 100644 index 0000000..8dff3b8 --- /dev/null +++ b/src/superio/smsc/sch4037/sch4037.h @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_SCH_4037_H +#define SUPERIO_SCH_4037_H + + +#define SCH4037_FDD 0 /* FDD */ +#define SCH4037_LPT 3 /* LPT */ +#define SMSCSUPERIO_SP1 4 /* Com1 */ +#define SMSCSUPERIO_SP2 5 /* Com2 */ +#define SCH4037_RTC 6 /* RTC */ +#define SCH4037_KBC 7 /* KBC */ +#define SCH4037_HWM 8 /* HWM */ +#define SCH4037_RUNTIME 0x0A /* Runtime */ +#define SCH4037_XBUS 0x0B /* X-BUS */ + +#endif //SUPERIO_SCH_4037_H diff --git a/src/superio/smsc/sch4037/sch4037_early_init.c b/src/superio/smsc/sch4037/sch4037_early_init.c new file mode 100644 index 0000000..392f229 --- /dev/null +++ b/src/superio/smsc/sch4037/sch4037_early_init.c @@ -0,0 +1,71 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Pre-RAM driver for the SMSC KBC1100 Super I/O chip */ + +#include <arch/romcc_io.h> +#include "sch4037.h" + +static inline void pnp_enter_conf_state(device_t dev) +{ + unsigned port = dev>>8; + outb(0x55, port); +} + +static void pnp_exit_conf_state(device_t dev) +{ + unsigned port = dev>>8; + outb(0xaa, port); +} + +static inline void sch4037_early_init(unsigned port) +{ + device_t dev; + + dev = PNP_DEV (port, SMSCSUPERIO_SP1); + pnp_enter_conf_state(dev); + + /*Auto power management*/ + pnp_write_config (dev, 0x22, 0x38); /* BIT3+BIT4+BIT5 */ + pnp_write_config (dev, 0x23, 0 ); + + /* Enable SMSC UART 0 */ + dev = PNP_DEV (port, SMSCSUPERIO_SP1); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + + pnp_set_iobase(dev, PNP_IDX_IO0, CONFIG_TTYS0_BASE); + pnp_set_irq(dev, PNP_IDX_IRQ0, 0x4); + + /* Enabled High speed, disabled MIDI support. */ + pnp_write_config (dev, 0xF0, 0x02); + pnp_set_enable(dev, 1); + + /* Enable keyboard */ + dev = PNP_DEV (port, SCH4037_KBC); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_irq(dev, 0x70, 1); /* IRQ 1 */ + pnp_set_irq(dev, 0x72, 12); /* IRQ 12 */ + pnp_set_enable(dev, 1); + + pnp_exit_conf_state(dev); + +} + diff --git a/src/superio/smsc/sch4037/superio.c b/src/superio/smsc/sch4037/superio.c new file mode 100644 index 0000000..af4040f --- /dev/null +++ b/src/superio/smsc/sch4037/superio.c @@ -0,0 +1,123 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* RAM driver for the SMSC KBC1100 Super I/O chip */ + +#include <arch/io.h> +#include <device/device.h> +#include <device/pnp.h> +#include <console/console.h> +#include <device/smbus.h> +#include <string.h> +#include <bitops.h> +#include <uart8250.h> +#include <pc80/keyboard.h> +#include <stdlib.h> +#include "chip.h" +#include "sch4037.h" + +/* Forward declarations */ +static void enable_dev(device_t dev); +static void sch4037_pnp_set_resources(device_t dev); +static void sch4037_pnp_enable_resources(device_t dev); +static void sch4037_pnp_enable(device_t dev); +static void sch4037_init(device_t dev); + +static void pnp_enter_conf_state(device_t dev); +static void pnp_exit_conf_state(device_t dev); + +struct chip_operations superio_smsc_sch4037_ops = { + CHIP_NAME("SMSC SCH4037 Super I/O") + .enable_dev = enable_dev, +}; + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = sch4037_pnp_set_resources, + .enable_resources = sch4037_pnp_enable_resources, + .enable = sch4037_pnp_enable, + .init = sch4037_init, +}; + +static struct pnp_info pnp_dev_info[] = { + { &ops, SCH4037_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, }, +}; + +static void enable_dev(device_t dev) +{ + printk(BIOS_EMERG, "file '%s',line %d, %s()\n", __FILE__, __LINE__, __func__); + pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +static void sch4037_pnp_set_resources(device_t dev) +{ + pnp_enter_conf_state(dev); + pnp_set_resources(dev); + pnp_exit_conf_state(dev); +} + +static void sch4037_pnp_enable_resources(device_t dev) +{ + pnp_enter_conf_state(dev); + pnp_enable_resources(dev); + pnp_exit_conf_state(dev); +} + +static void sch4037_pnp_enable(device_t dev) +{ + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + + if(dev->enabled) { + pnp_set_enable(dev, 1); + } + else { + pnp_set_enable(dev, 0); + } + pnp_exit_conf_state(dev); +} + +static void sch4037_init(device_t dev) +{ + struct superio_smsc_sch4037_config *conf = dev->chip_info; + struct resource *res0, *res1; + + if (!dev->enabled) { + return; + } + + switch(dev->path.pnp.device) { + + case SCH4037_KBC: + res0 = find_resource(dev, PNP_IDX_IO0); + res1 = find_resource(dev, PNP_IDX_IO1); + pc_keyboard_init(&conf->keyboard); + break; + } +} + +static void pnp_enter_conf_state(device_t dev) +{ + outb(0x55, dev->path.pnp.port); +} + +static void pnp_exit_conf_state(device_t dev) +{ + outb(0xaa, dev->path.pnp.port); +}

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Re: [coreboot] Trying to port abit A-S78H
by Prakash Punnoor 03 Feb '12

03 Feb '12

On Monday 23 January 2012 22:35:22 Scott Duplichan wrote: > Prakash Punnoor wrote: > ]So, I cannot make coreboot boot. On cold start it seems to hang in > ] > ]src/southbridge/amd/sb700/reset.c > ] > ]in soft_reset. set_bios_reset seems sucessful, but I get no post code after > > ]outb(0x06, 0x0cf9). Any idea, what I can try? > > Maybe the reset is just causing your port 80 routing to be lost. You need > to execute some port 80 enable and routing code as early as possible. > Is your port 80 card PCI or LPC? For the LPC type, I believe you only > have to set 'Port enable for IO port 80h' (bit 5 of pci config register 4Ah > on device 14h, function 3). To route port 80 to PCI, I think you have to set > 'IO Enable' (bit 0 of PCI config register 4 on device 14h, function 4). Sounds reasonable. It is a PCI port 80 card. I'll try that when I find time. BTW, could you explain what happens after soft_reset? Will coreboot run again from start? At least the following "die(...)" statement (romstage.c cache_as_ram_main) suggests that program flow should NOT get there. So, if coreboots runs again from start, why doesn't it enable port 80 again like it did initially? Thanks, Prakash

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Patch merged into coreboot/master: 3ff1453 libpayload: Add access to CMOS images in memory space
by gerrit＠coreboot.org 02 Feb '12

02 Feb '12

the following patch was just integrated into master: commit 3ff14530ac906ebc89f7300feb94694c49ccf34a Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Thu Feb 2 15:51:29 2012 +0100 libpayload: Add access to CMOS images in memory space Provide access to CMOS images in RAM or CBFS, such as cmos.defaults Change-Id: Ifa70dea6206d94c0c271caf9ae1152fc76b5d51a Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Thu Feb 2 17:48:05 2012, giving +2 See http://review.coreboot.org/584 for details. -gerrit

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Suggestion for (FOSDEM) talk to attract new contributors
by Paul Menzel 02 Feb '12

02 Feb '12

Dear Carl-Daniel and coreboot folks, to attract new developers from my (inexperienced) point of view possible contributors hesitate because they think doing coreboot development will be searching for and reading a lot of data sheets, do reverse engineering, bricking boards, etc.. So to attract contributors one could point out that there are more or less hardware unrelated tasks to do and that interested people also can do (easy) hardware related stuff and learn things by looking at the infrastructure projects Patrick listed at [1]. Additionally more “conventional” (software) programming is needed to get more payloads (configuration payload to for example set up RAM timing), create images that fit in a flash chip (for recovery maybe) and (graphical) configuration tools for example for `nvramtool`. But not knowing for sure the reasons people stay away from coreboot development this is of course just a suggestion and a guess. Thanks, Paul [1] http://www.coreboot.org/Infrastructure_Projects

2 1

Patch merged into coreboot/master: f81d7bd i3100: configure pci irqs
by gerrit＠coreboot.org 02 Feb '12

02 Feb '12

the following patch was just integrated into master: commit f81d7bd250944c585a0cdcdf614f4ba4878b22db Author: Sven Schnelle <svens(a)stackframe.org> Date: Wed Feb 1 11:47:29 2012 +0100 i3100: configure pci irqs without it, you can't boot from PCI devices like scsi controllers which require an interrupt set. So preconfigure all pci devices. Change-Id: I2cd781227701e8363d83bd90e0e36994359fc194 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> Build-Tested: build bot (Jenkins) at Wed Feb 1 12:06:48 2012, giving +1 Reviewed-By: Sven Schnelle <svens(a)stackframe.org> at Thu Feb 2 16:01:47 2012, giving +2 See http://review.coreboot.org/603 for details. -gerrit

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Patch set updated for coreboot: 3ff1453 libpayload: Add access to CMOS images in memory space
by Patrick Georgi 02 Feb '12

02 Feb '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/584 -gerrit commit 3ff14530ac906ebc89f7300feb94694c49ccf34a Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Thu Feb 2 15:51:29 2012 +0100 libpayload: Add access to CMOS images in memory space Provide access to CMOS images in RAM or CBFS, such as cmos.defaults Change-Id: Ifa70dea6206d94c0c271caf9ae1152fc76b5d51a Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> --- payloads/libpayload/drivers/options.c | 17 +++++++++++++++++ payloads/libpayload/include/libpayload.h | 3 ++- 2 files changed, 19 insertions(+), 1 deletions(-) diff --git a/payloads/libpayload/drivers/options.c b/payloads/libpayload/drivers/options.c index 61e6cc5..36d8a9b 100644 --- a/payloads/libpayload/drivers/options.c +++ b/payloads/libpayload/drivers/options.c @@ -30,11 +30,28 @@ #include <libpayload.h> #include <coreboot_tables.h> +u8 *mem_accessor_base; + +static u8 mem_read(u8 reg) +{ + return mem_accessor_base[reg]; +} + +static void mem_write(u8 val, u8 reg) +{ + mem_accessor_base[reg] = val; +} + struct nvram_accessor *use_nvram = &(struct nvram_accessor) { nvram_read, nvram_write }; +struct nvram_accessor *use_mem = &(struct nvram_accessor) { + mem_read, + mem_write +}; + struct cb_cmos_option_table *get_system_option_table(void) { return phys_to_virt(lib_sysinfo.option_table); diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h index 91156e5..308d95c 100644 --- a/payloads/libpayload/include/libpayload.h +++ b/payloads/libpayload/include/libpayload.h @@ -199,7 +199,8 @@ struct nvram_accessor { void (*write)(u8 val, u8 reg); }; -extern struct nvram_accessor *use_nvram; +extern u8 *mem_accessor_base; +extern struct nvram_accessor *use_nvram, *use_mem; struct cb_cmos_option_table *get_system_option_table(void); void fix_options_checksum_with(const struct nvram_accessor *nvram);

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Patch merged into coreboot/master: 0d44787 libpayload: Refactor highlevel CMOS access
by gerrit＠coreboot.org 02 Feb '12

02 Feb '12

the following patch was just integrated into master: commit 0d4478753226d92213f295b2cc72c2b098a5c279 Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Mon Jan 16 10:14:24 2012 +0100 libpayload: Refactor highlevel CMOS access This will allow using libpayload functions to access CMOS data in template files in RAM or CBFS. Change-Id: I323ed625e657cbdc1fae8c279a82ee578e83ad00 Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Thu Feb 2 15:48:27 2012, giving +2 See http://review.coreboot.org/583 for details. -gerrit

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Patch merged into coreboot/master: 425158e CIMX wrapper: remove redudant traversing sb800 and sb900 CIMX dir
by gerrit＠coreboot.org 02 Feb '12

02 Feb '12

the following patch was just integrated into master: commit 425158e483eb7ea8a5faf742742b42396ecd8fd4 Author: Kerry Sheh <shekairui(a)gmail.com> Date: Wed Feb 1 14:07:38 2012 +0800 CIMX wrapper: remove redudant traversing sb800 and sb900 CIMX dir AGESA and CIMX build changed from commit 2a830d0b, sb800 and sb900 CIMX dir already traversed in vendorcode Makefile. Change-Id: I5101b22e140725337bf5074b9170e582c8e3bf40 Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Thu Feb 2 15:10:05 2012, giving +2 See http://review.coreboot.org/602 for details. -gerrit

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Patch merged into coreboot/master: 33b60dd SB700 southbridge: AMD SB700/SP5100 southbridge CIMX code
by gerrit＠coreboot.org 02 Feb '12

02 Feb '12

the following patch was just integrated into master: commit 33b60ddb3d34150cd8d5a962758b02dcfd0e2127 Author: Kerry Sheh <shekairui(a)gmail.com> Date: Wed Feb 1 13:55:13 2012 +0800 SB700 southbridge: AMD SB700/SP5100 southbridge CIMX code Support AMD SB700 and SP5100 chipsets. Change-Id: I0955abf7f48a79483f624b46a61b22711315f888 Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Thu Feb 2 15:05:35 2012, giving +2 See http://review.coreboot.org/560 for details. -gerrit

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Patch merged into coreboot/master: ac36286 RD890 Northbridge: AMD RD890/SR56X0 Northbridge CIMX code
by gerrit＠coreboot.org 02 Feb '12

02 Feb '12

the following patch was just integrated into master: commit ac362862a3a19006e6d75471f1655f4aabc54dc9 Author: Kerry Sheh <shekairui(a)gmail.com> Date: Tue Jan 31 20:39:37 2012 +0800 RD890 Northbridge: AMD RD890/SR56X0 Northbridge CIMX code Change-Id: If9908ffeb5b707a660db38dc44f5118347cbcc06 Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Thu Feb 2 13:53:44 2012, giving +2 See http://review.coreboot.org/557 for details. -gerrit

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coreboot February 2012