coreboot February 2012

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Patch merged into coreboot/master: 7832515 Add Intel i5000 Memory Controller Hub
by gerrit＠coreboot.org 02 Feb '12

02 Feb '12

the following patch was just integrated into master: commit 783251547346ae2e61749e8750a95f52cd81eec9 Author: Sven Schnelle <svens(a)stackframe.org> Date: Wed Feb 1 22:06:45 2012 +0100 Add Intel i5000 Memory Controller Hub Change-Id: Ic169f3f61babfcfa2ddcb84fc0267ebcf8c5f3bb Signed-off-by: Sven Schnelle <svens(a)stackframe.org> Build-Tested: build bot (Jenkins) at Thu Feb 2 13:28:40 2012, giving +1 Reviewed-By: Sven Schnelle <svens(a)stackframe.org> at Thu Feb 2 13:49:32 2012, giving +2 See http://review.coreboot.org/491 for details. -gerrit

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Patch set updated for coreboot: 7832515 Add Intel i5000 Memory Controller Hub
by Sven Schnelle 02 Feb '12

02 Feb '12

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/491 -gerrit commit 783251547346ae2e61749e8750a95f52cd81eec9 Author: Sven Schnelle <svens(a)stackframe.org> Date: Wed Feb 1 22:06:45 2012 +0100 Add Intel i5000 Memory Controller Hub Change-Id: Ic169f3f61babfcfa2ddcb84fc0267ebcf8c5f3bb Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/northbridge/intel/Kconfig | 1 + src/northbridge/intel/Makefile.inc | 1 + src/northbridge/intel/i5000/Kconfig | 26 + src/northbridge/intel/i5000/Makefile.inc | 21 + src/northbridge/intel/i5000/chip.h | 23 + src/northbridge/intel/i5000/northbridge.c | 188 +++ src/northbridge/intel/i5000/raminit.c | 1770 +++++++++++++++++++++++++++++ src/northbridge/intel/i5000/raminit.h | 337 ++++++ src/northbridge/intel/i5000/udelay.c | 84 ++ 9 files changed, 2451 insertions(+), 0 deletions(-) diff --git a/src/northbridge/intel/Kconfig b/src/northbridge/intel/Kconfig index 1809d11..31afe6a 100644 --- a/src/northbridge/intel/Kconfig +++ b/src/northbridge/intel/Kconfig @@ -10,3 +10,4 @@ source src/northbridge/intel/i82830/Kconfig source src/northbridge/intel/i855/Kconfig source src/northbridge/intel/i945/Kconfig source src/northbridge/intel/sch/Kconfig +source src/northbridge/intel/i5000/Kconfig diff --git a/src/northbridge/intel/Makefile.inc b/src/northbridge/intel/Makefile.inc index 0d116d0..c599dab 100644 --- a/src/northbridge/intel/Makefile.inc +++ b/src/northbridge/intel/Makefile.inc @@ -11,3 +11,4 @@ subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I855) += i855 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I945GC) += i945 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I945GM) += i945 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SCH) += sch +subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I5000) += i5000 diff --git a/src/northbridge/intel/i5000/Kconfig b/src/northbridge/intel/i5000/Kconfig new file mode 100644 index 0000000..0595a57 --- /dev/null +++ b/src/northbridge/intel/i5000/Kconfig @@ -0,0 +1,26 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config NORTHBRIDGE_INTEL_I5000 + bool + select HAVE_DEBUG_RAM_SETUP + +config NORTHBRIDGE_INTEL_I5000_RAM_CHECK + bool + prompt "Run ramcheck after RAM initialization" diff --git a/src/northbridge/intel/i5000/Makefile.inc b/src/northbridge/intel/i5000/Makefile.inc new file mode 100644 index 0000000..a5623c0 --- /dev/null +++ b/src/northbridge/intel/i5000/Makefile.inc @@ -0,0 +1,21 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2007-2009 coresystems GmbH +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +driver-y += northbridge.c +romstage-y += raminit.c udelay.c diff --git a/src/northbridge/intel/i5000/chip.h b/src/northbridge/intel/i5000/chip.h new file mode 100644 index 0000000..a23be90 --- /dev/null +++ b/src/northbridge/intel/i5000/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +struct northbridge_intel_i5000_config { +}; + +extern struct chip_operations northbridge_intel_i5000_ops; diff --git a/src/northbridge/intel/i5000/northbridge.c b/src/northbridge/intel/i5000/northbridge.c new file mode 100644 index 0000000..3db755c --- /dev/null +++ b/src/northbridge/intel/i5000/northbridge.c @@ -0,0 +1,188 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <arch/io.h> +#include <stdint.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <stdlib.h> +#include <string.h> +#include <bitops.h> +#include <cpu/cpu.h> +#include <boot/tables.h> +#include <arch/acpi.h> +#include <cbmem.h> +#include "chip.h" + +static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + if (!vendor || !device) { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + pci_read_config32(dev, PCI_VENDOR_ID)); + } else { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + ((device & 0xffff) << 16) | (vendor & 0xffff)); + } +} + +static struct pci_operations intel_pci_ops = { + .set_subsystem = intel_set_subsystem, +}; + +static struct device_operations mc_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .scan_bus = 0, + .ops_pci = &intel_pci_ops, +}; + +static const struct pci_driver mc_driver __pci_driver = { + .ops = &mc_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x25d8, +}; + +static void cpu_bus_init(device_t dev) +{ + initialize_cpus(dev->link_list); +} + +static void cpu_bus_noop(device_t dev) +{ +} +static struct device_operations cpu_bus_ops = { + .read_resources = cpu_bus_noop, + .set_resources = cpu_bus_noop, + .enable_resources = cpu_bus_noop, + .init = cpu_bus_init, + .scan_bus = 0, +}; + +#if CONFIG_WRITE_HIGH_TABLES +#include <cbmem.h> +#endif + +static void pci_domain_set_resources(device_t dev) +{ + struct resource *resource; + uint32_t hecbase, amsize, tolm; + uint64_t ambase, memsize; + int idx = 0; + device_t dev16_0 = dev_find_slot(0, PCI_DEVFN(16, 0)); + device_t dev16_1 = dev_find_slot(0, PCI_DEVFN(16, 1)); + + tolm = pci_read_config16(dev_find_slot(0, PCI_DEVFN(16, 1)), 0x6c) << 16; + hecbase = pci_read_config16(dev16_0, 0x64) >> 12; + hecbase &= 0xffff; + + ambase = ((u64)pci_read_config32(dev16_0, 0x48) | + (u64)pci_read_config32(dev16_0, 0x4c) << 32); + + amsize = pci_read_config32(dev16_0, 0x50); + ambase &= 0x000000ffffff0000; + + printk(BIOS_DEBUG, "TOLM: 0x%08x AMBASE: 0x%016llx\n", tolm, ambase); + + /* Report the memory regions */ + ram_resource(dev, idx++, 0, 640); + ram_resource(dev, idx++, 768, ((tolm >> 10) - 768)); + + memsize = MAX(pci_read_config16(dev16_1, 0x80) & ~3, + pci_read_config16(dev16_1, 0x84) & ~3); + memsize = MAX(memsize, pci_read_config16(dev16_1, 0x88) & ~3); + + memsize <<= 24; + printk(BIOS_INFO, "MEMSIZE: %08llx\n", memsize); + if (memsize > 0xe0000000) { + memsize -= 0xe0000000; + printk(BIOS_INFO, "high memory: %lldMB\n", memsize / 1048576); + ram_resource(dev, idx++, 4096 * 1024, memsize / 1024); + } + + if (hecbase) { + printk(BIOS_DEBUG, "Adding PCIe config bar at 0x%016llx\n", (u64)hecbase << 28); + resource = new_resource(dev, idx++); + resource->base = (resource_t)(uint64_t)hecbase << 28; + resource->size = (resource_t)256 * 1024 * 1024; + resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + } + + resource = new_resource(dev, idx++); + resource->base = (resource_t)(uint64_t)0xffe00000; + resource->size = (resource_t)0x200000; + resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + + if (ambase && amsize) { + resource = new_resource(dev, idx++); + resource->base = (resource_t)ambase; + resource->size = (resource_t)amsize; + resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + } + + /* add resource for 0xfe6xxxxx range. This range is used by i5000 for + various fixed address registers (BOFL, SPAD, SPADS */ + resource = new_resource(dev, idx++); + resource->base = (resource_t)0xfe600000; + resource->size = (resource_t)0x00100000; + resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + + assign_resources(dev->link_list); + +#if CONFIG_WRITE_HIGH_TABLES + /* Leave some space for ACPI, PIRQ and MP tables */ + high_tables_base = tolm - HIGH_MEMORY_SIZE; + high_tables_size = HIGH_MEMORY_SIZE; + printk(BIOS_DEBUG, "high_tables_base: %08llx, size %lld\n", high_tables_base, high_tables_size); +#endif +} + +static struct device_operations pci_domain_ops = { + .read_resources = pci_domain_read_resources, + .set_resources = pci_domain_set_resources, + .enable_resources = NULL, + .init = NULL, + .scan_bus = pci_domain_scan_bus, +#if CONFIG_MMCONF_SUPPORT_DEFAULT + .ops_pci_bus = &pci_ops_mmconf, +#else + .ops_pci_bus = &pci_cf8_conf1, +#endif +}; + +static void enable_dev(device_t dev) +{ + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) { + dev->ops = &pci_domain_ops; + } else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) { + dev->ops = &cpu_bus_ops; + } +} + +struct chip_operations northbridge_intel_i5000_ops = { + CHIP_NAME("Intel i5000 Northbridge") + .enable_dev = enable_dev, +}; diff --git a/src/northbridge/intel/i5000/raminit.c b/src/northbridge/intel/i5000/raminit.c new file mode 100644 index 0000000..95610ce --- /dev/null +++ b/src/northbridge/intel/i5000/raminit.c @@ -0,0 +1,1770 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include "raminit.h" +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <cpu/x86/lapic.h> +#include <console/console.h> +#include <spd.h> +#include <types.h> +#include <southbridge/intel/i63xx/early_smbus.c> +#include <string.h> +#include <cbmem.h> +#include <stdlib.h> +#include <lib.h> +#include <delay.h> + +static int i5000_for_each_channel(struct i5000_fbd_branch *branch, + int (*cb)(struct i5000_fbd_channel *)) +{ + struct i5000_fbd_channel *c; + int ret; + + for(c = branch->channel; c < branch->channel + I5000_MAX_CHANNEL; c++) + if (c->used && (ret = cb(c))) + return ret; + return 0; +} + +static int i5000_for_each_branch(struct i5000_fbd_setup *setup, + int (*cb)(struct i5000_fbd_branch *)) +{ + struct i5000_fbd_branch *b; + int ret; + + for(b = setup->branch; b < setup->branch + I5000_MAX_BRANCH; b++) + if (b->used && (ret = cb(b))) + return ret; + return 0; +} + +static int i5000_for_each_dimm(struct i5000_fbd_setup *setup, + int (*cb)(struct i5000_fbdimm *)) +{ + struct i5000_fbdimm *d; + int ret, i; + + for(i = 0; i < I5000_MAX_DIMMS; i++) { + d = setup->dimms[i]; + if ((ret = cb(d))) { + return ret; + } + } + return 0; +} + +static int i5000_for_each_dimm_present(struct i5000_fbd_setup *setup, + int (*cb)(struct i5000_fbdimm *)) +{ + struct i5000_fbdimm *d; + int ret, i; + + for(i = 0; i < I5000_MAX_DIMMS; i++) { + d = setup->dimms[i]; + if (d->present && (ret = cb(d))) + return ret; + } + return 0; +} + +static int spd_read_byte(struct i5000_fbdimm *d, u8 addr, int count, u8 *out) +{ + u16 status; + device_t dev = d->branch->branchdev; + + int cmdreg = d->channel->num ? I5000_SPDCMD1 : I5000_SPDCMD0; + int stsreg = d->channel->num ? I5000_SPD1 : I5000_SPD0; + + while(count-- > 0) { + pci_write_config32(dev, cmdreg, 0xa8000000 | \ + (d->num & 0x03) << 24 | addr++ << 16); + + int timeout = 1000; + while((status = pci_read_config16(dev, stsreg)) & I5000_SPD_BUSY && timeout--) + udelay(10); + + if (status & I5000_SPD_SBE || !timeout) + return -1; + + if (status & I5000_SPD_RDO) { + *out = status & 0xff; + out++; + } + } + return 0; +} + +static void i5000_clear_fbd_errors(void) +{ + device_t dev16_1, dev16_2; + + dev16_1 = PCI_ADDR(0, 16, 1, 0); + dev16_2 = PCI_ADDR(0, 16, 2, 0); + + pci_mmio_write_config32(dev16_1, I5000_EMASK_FBD, + pci_mmio_read_config32(dev16_1, I5000_EMASK_FBD)); + + pci_mmio_write_config32(dev16_1, I5000_NERR_FAT_FBD, + pci_mmio_read_config32(dev16_1, I5000_NERR_FAT_FBD)); + + pci_mmio_write_config32(dev16_1, I5000_FERR_FAT_FBD, + pci_mmio_read_config32(dev16_1, I5000_FERR_FAT_FBD)); + + pci_mmio_write_config32(dev16_1, I5000_NERR_NF_FBD, + pci_mmio_read_config32(dev16_1, I5000_NERR_NF_FBD)); + + pci_mmio_write_config32(dev16_1, I5000_FERR_NF_FBD, + pci_mmio_read_config32(dev16_1, I5000_FERR_NF_FBD)); + + pci_mmio_write_config32(dev16_2, I5000_FERR_GLOBAL, + pci_mmio_read_config32(dev16_2, I5000_FERR_GLOBAL)); + + pci_mmio_write_config32(dev16_2, I5000_NERR_GLOBAL, + pci_mmio_read_config32(dev16_2, I5000_NERR_GLOBAL)); +} + +static int i5000_branch_reset(struct i5000_fbd_branch *b) +{ + device_t dev = b->branchdev; + + pci_write_config8(dev, I5000_FBDRST, 0x00); + + udelay(5000); + + pci_write_config8(dev, I5000_FBDRST, 0x05); + udelay(1); + pci_write_config8(dev, I5000_FBDRST, 0x04); + udelay(2); + pci_write_config8(dev, I5000_FBDRST, 0x05); + pci_write_config8(dev, I5000_FBDRST, 0x07); + return 0; +} + +static int delay_ns_to_clocks(struct i5000_fbdimm *d, int del) +{ + int div; + + switch (d->setup->ddr_speed) { + case DDR_533MHZ: + div = 375; + break; + + default: + printk(BIOS_ERR, "Invalid clock: %d, using 667MHz\n", + d->setup->ddr_speed); + + case DDR_667MHZ: + div = 300; + break; + } + + return (del * 100) / div; +} + +static int mtb2clks(struct i5000_fbdimm *d, int del) +{ + int val, div; + + switch (d->setup->ddr_speed) { + case DDR_533MHZ: + div = 375; + break; + default: + printk(BIOS_ERR, "Invalid clock: %d, using 667MHz\n", + d->setup->ddr_speed); + + case DDR_667MHZ: + div = 300; + break; + } + + val = (del * 1000 * d->mtb_dividend) / (d->mtb_divisor * div); + if ((val % 10) > 0) + val += 10; + return val / 10; +} + +static int i5000_read_spd_data(struct i5000_fbdimm *d) +{ + struct i5000_fbd_setup *s = d->setup; + u8 addr, val, org, ftb, cas, t_ras_rc_h, t_rtp, t_wtr; + u8 bb, bl, t_wr, t_rp, t_rcd, t_rc, t_ras, t_aa_min; + u8 cmd2data_addr; + int t_ck_min, dimmsize; + + if (spd_read_byte(d, SPD_MEMORY_TYPE, 1, &val)) { + printk(BIOS_DEBUG, "DIMM %d/%d/%d not present\n", + d->branch->num, d->channel->num, d->num); + return 0; // No FBDIMM present + } + + if (val != 0x09) + return -1; // SDRAM type not FBDIMM + + if (spd_read_byte(d, 0x65, 14, d->amb_personality_bytes)) + return -1; + + switch(s->ddr_speed) { + case DDR_533MHZ: + cmd2data_addr = FBDIMM_SPD_CMD2DATA_533; + break; + + case DDR_667MHZ: + cmd2data_addr = FBDIMM_SPD_CMD2DATA_667; + break; + + default: + printk(BIOS_ERR, "Unsupported FBDIMM clock\n"); + return -1; + } + + if (spd_read_byte(d, FBDIMM_SPD_SDRAM_ADDRESSING, 1, &addr) || + spd_read_byte(d, FBDIMM_SPD_MODULE_ORGANIZATION, 1, &org) || + spd_read_byte(d, FBDIMM_SPD_FTB, 1, &ftb) || + spd_read_byte(d, FBDIMM_SPD_MTB_DIVIDEND, 1, &d->mtb_dividend) || + spd_read_byte(d, FBDIMM_SPD_MTB_DIVISOR, 1, &d->mtb_divisor) || + spd_read_byte(d, FBDIMM_SPD_MIN_TCK, 1, &d->t_ck_min) || + spd_read_byte(d, FBDIMM_SPD_T_WR, 1, &t_wr) || + spd_read_byte(d, FBDIMM_SPD_T_RCD, 1, &t_rcd) || + spd_read_byte(d, FBDIMM_SPD_T_RRD, 1, &d->t_rrd) || + spd_read_byte(d, FBDIMM_SPD_T_RP, 1, &t_rp) || + spd_read_byte(d, FBDIMM_SPD_T_RAS_RC_MSB, 1, &t_ras_rc_h) || + spd_read_byte(d, FBDIMM_SPD_T_RAS, 1, (u8 *)&t_ras) || + spd_read_byte(d, FBDIMM_SPD_T_RC, 1, (u8 *)&t_rc) || + spd_read_byte(d, FBDIMM_SPD_T_RFC, 2, (u8 *)&d->t_rfc) || + spd_read_byte(d, FBDIMM_SPD_T_WTR, 1, &t_wtr) || + spd_read_byte(d, FBDIMM_SPD_T_RTP, 1, &t_rtp) || + spd_read_byte(d, FBDIMM_SPD_T_BB, 1, &bb) || + spd_read_byte(d, FBDIMM_SPD_BURST_LENGTHS_SUPPORTED, 1, &bl) || + spd_read_byte(d, FBDIMM_SPD_ODT, 1, &d->odt) || + spd_read_byte(d, FBDIMM_SPD_T_REFI, 1, &d->t_refi) || + spd_read_byte(d, FBDIMM_SPD_CAS_LATENCIES, 1, &cas) || + spd_read_byte(d, FBDIMM_SPD_CMD2DATA_533, 1, &d->cmd2datanxt[DDR_533MHZ]) || + spd_read_byte(d, FBDIMM_SPD_CMD2DATA_667, 1, &d->cmd2datanxt[DDR_667MHZ]) || + spd_read_byte(d, FBDIMM_SPD_CAS_MIN_LATENCY, 1, &t_aa_min)) { + printk(BIOS_ERR, "failed to read data from SPD\n"); + return 0; + } + + + t_ck_min = (d->t_ck_min * 100) / d->mtb_divisor; + if (t_ck_min <= 300) + d->speed = DDR_667MHZ; + else if (t_ck_min <= 375) + d->speed = DDR_533MHZ; + else { + printk(BIOS_ERR, "Unsupported t_ck_min: %d\n", t_ck_min); + return -1; + } + + d->sdram_width = org & 0x07; + if (d->sdram_width > 1) { + printk(BIOS_ERR, "SDRAM width %d not supported\n", d->sdram_width); + return -1; + } + + if (s->ddr_speed == DDR_667MHZ && d->speed == DDR_533MHZ) + s->ddr_speed = DDR_533MHZ; + + d->banks = 4 << (addr & 0x03); + d->columns = 9 + ((addr >> 2) & 0x03); + d->rows = 12 + ((addr >> 5) & 0x03); + d->ranks = (org >> 3) & 0x03; + d->min_cas_latency = cas & 0x0f; + + s->bl &= bl; + + if (!s->bl) { + printk(BIOS_ERR, "no compatible burst length found\n"); + return -1; + } + + s->t_rc = MAX(s->t_rc, mtb2clks(d, + t_rc | ((t_ras_rc_h & 0xf0) << 4))); + s->t_rrd = MAX(s->t_rrd, mtb2clks(d, d->t_rrd)); + s->t_rfc = MAX(s->t_rfc, mtb2clks(d, d->t_rfc)); + s->t_rcd = MAX(s->t_rcd, mtb2clks(d, t_rcd)); + s->t_cl = MAX(s->t_cl, mtb2clks(d, t_aa_min)); + s->t_wr = MAX(s->t_wr, mtb2clks(d, t_wr)); + s->t_rp = MAX(s->t_rp, mtb2clks(d, t_rp)); + s->t_rtp = MAX(s->t_rtp, mtb2clks(d, t_rtp)); + s->t_wtr = MAX(s->t_wtr, mtb2clks(d, t_wtr)); + s->t_ras = MAX(s->t_ras, mtb2clks(d, + t_ras | ((t_ras_rc_h & 0x0f) << 8))); + s->t_r2r = MAX(s->t_r2r, bb & 3); + s->t_r2w = MAX(s->t_r2w, (bb >> 4) & 3); + s->t_w2r = MAX(s->t_w2r, (bb >> 2) & 3); + + d->ranksize = (1 << (d->banks + d->columns + d->rows + 1)) >> 20; + dimmsize = d->ranksize * d->ranks; + d->branch->totalmem += dimmsize; + s->totalmem += dimmsize; + + d->channel->columns = d->columns; + d->channel->rows = d->rows; + d->channel->ranks = d->ranks; + d->channel->banks = d->banks; + d->channel->width = d->sdram_width; + + printk(BIOS_INFO, "DIMM %d/%d/%d %dMB: %d banks, " + "%d columns, %d rows, %d ranks\n", + d->branch->num, d->channel->num, d->num, dimmsize, + d->banks, d->columns, d->rows, d->ranks); + + d->present = 1; + d->branch->used |= 1; + d->channel->used |= 1; + d->channel->highest_amb = d->num; + return 0; +} + +static int i5000_amb_smbus_write(struct i5000_fbdimm *d, int byte1, int byte2) +{ + u16 status; + device_t dev = PCI_DEV(0, d->branch->num ? 22 : 21, 0); + int cmdreg = d->channel->num ? I5000_SPDCMD1 : I5000_SPDCMD0; + int stsreg = d->channel->num ? I5000_SPD1 : I5000_SPD0; + int timeout = 1000; + + pci_write_config32(dev, cmdreg, 0xb8000000 | ((d->num & 0x03) << 24) | + (byte1 << 16) | (byte2 << 8) | 1); + + while(((status = pci_read_config16(dev, stsreg)) & I5000_SPD_BUSY) && timeout--) + udelay(10); + + if (status & I5000_SPD_WOD && timeout) + return 0; + + printk(BIOS_ERR, "SMBus write failed: %d/%d/%d, byte1 %02x, byte2 %02x status %04x\n", + d->branch->num, d->channel->num, d->num, byte1, byte2, status); + for(;;); + return -1; +} + +static int i5000_amb_smbus_read(struct i5000_fbdimm *d, int byte1, u8 *out) +{ + u16 status; + device_t dev = PCI_DEV(0, d->branch->num ? 22 : 21, 0); + int cmdreg = d->channel->num ? I5000_SPDCMD1 : I5000_SPDCMD0; + int stsreg = d->channel->num ? I5000_SPD1 : I5000_SPD0; + int timeout = 1000; + + pci_write_config32(dev, cmdreg, 0xb8000000 | ((d->num & 0x03) << 24) | + (byte1 << 16)); + + while(((status = pci_read_config16(dev, stsreg)) & I5000_SPD_BUSY) && timeout--) + udelay(10); + + if ((status & I5000_SPD_RDO) && timeout) + *out = status & 0xff; + + if (status & I5000_SPD_SBE || !timeout) { + printk(BIOS_ERR, "SMBus write failed: %d/%d/%d, byte1 %02x status %04x\n", + d->branch->num, d->channel->num, d->num, byte1, status); + return -1; + } + return 0; + +} + +static int i5000_amb_smbus_write_config8(struct i5000_fbdimm *d, + int fn, int reg, u8 val) +{ + if (i5000_amb_smbus_write(d, 0x84, 00) || + i5000_amb_smbus_write(d, 0x04, fn) || + i5000_amb_smbus_write(d, 0x04, (reg >> 8) & 0xff) || + i5000_amb_smbus_write(d, 0x04, reg & 0xff) || + i5000_amb_smbus_write(d, 0x44, val)) { + printk(BIOS_ERR, "AMB SMBUS write failed\n"); + return 1; + } + return 0; +} + +static int i5000_amb_smbus_write_config16(struct i5000_fbdimm *d, + int fn, int reg, u16 val) +{ + if (i5000_amb_smbus_write(d, 0x88, 00) || + i5000_amb_smbus_write(d, 0x08, fn) || + i5000_amb_smbus_write(d, 0x08, (reg >> 8) & 0xff) || + i5000_amb_smbus_write(d, 0x08, reg & 0xff) || + i5000_amb_smbus_write(d, 0x08, (val >> 8) & 0xff) || + i5000_amb_smbus_write(d, 0x48, val & 0xff)) { + printk(BIOS_ERR, "AMB SMBUS write failed\n"); + return 1; + } + return 0; +} + +static int i5000_amb_smbus_write_config32(struct i5000_fbdimm *d, + int fn, int reg, u32 val) +{ + if (i5000_amb_smbus_write(d, 0x8c, 00) || + i5000_amb_smbus_write(d, 0x0c, fn) || + i5000_amb_smbus_write(d, 0x0c, (reg >> 8) & 0xff) || + i5000_amb_smbus_write(d, 0x0c, reg & 0xff) || + i5000_amb_smbus_write(d, 0x0c, (val >> 24) & 0xff) || + i5000_amb_smbus_write(d, 0x0c, (val >> 16) & 0xff) || + i5000_amb_smbus_write(d, 0x0c, (val >> 8) & 0xff) || + i5000_amb_smbus_write(d, 0x4c, val & 0xff)) { + printk(BIOS_ERR, "AMB SMBUS write failed\n"); + return 1; + } + return 0; +} + +static int i5000_amb_smbus_read_config32(struct i5000_fbdimm *d, + int fn, int reg, u32 *val) +{ + u8 byte3, byte2, byte1, byte0; + + if (i5000_amb_smbus_write(d, 0x80, 00) || + i5000_amb_smbus_write(d, 0x00, fn) || + i5000_amb_smbus_write(d, 0x00, (reg >> 8) & 0xff) || + i5000_amb_smbus_write(d, 0x40, reg & 0xff) || + i5000_amb_smbus_read(d, 0x80, &byte3) || + i5000_amb_smbus_read(d, 0x00, &byte3) || + i5000_amb_smbus_read(d, 0x00, &byte2) || + i5000_amb_smbus_read(d, 0x00, &byte1) || + i5000_amb_smbus_read(d, 0x40, &byte0)) { + printk(BIOS_ERR, "AMB SMBUS read failed\n"); + return 1; + } + *val = (byte3 << 24) | (byte2 << 16) | (byte1 << 8) | byte0; + return 0; +} + +static void i5000_amb_write_config8(struct i5000_fbdimm *d, + int fn, int reg, u32 val) +{ + write8(DEFAULT_AMBASE + AMB_ADDR(d->ambase, fn, reg), val); +} + +static void i5000_amb_write_config16(struct i5000_fbdimm *d, + int fn, int reg, u32 val) +{ + write16(DEFAULT_AMBASE + AMB_ADDR(d->ambase, fn, reg), val); +} + +static void i5000_amb_write_config32(struct i5000_fbdimm *d, + int fn, int reg, u32 val) +{ + write32(DEFAULT_AMBASE + AMB_ADDR(d->ambase, fn, reg), val); +} + +static u32 i5000_amb_read_config32(struct i5000_fbdimm *d, + int fn, int reg) +{ + return read32(DEFAULT_AMBASE + AMB_ADDR(d->ambase, fn, reg)); +} + +static int ddr_command(struct i5000_fbdimm *d, int rank, u32 addr, u32 command) +{ + u32 drc, status; + + printk(BIOS_SPEW, "DIMM %d/%d/%d: rank %d: sending command %x (addr %08x)...", + d->branch->num, d->channel->num, d->num, rank, command, addr); + + drc = i5000_amb_read_config32(d, 3, AMB_DRC); + drc &= ~((3 << 9) | (1 << 12)); + drc |= (rank << 9); + + command &= 0x0f; + command |= AMB_DCALCSR_START | (rank << 21); + + printk(BIOS_DEBUG, "%s: AMB_DCALADDR: %08x AMB_DCALCSR: %08x\n", __func__, addr, command); + i5000_amb_write_config32(d, 3, AMB_DRC, drc); + i5000_amb_write_config32(d, 4, AMB_DCALADDR, addr); + i5000_amb_write_config32(d, 4, AMB_DCALCSR, command); + + udelay(1000); + while((status = (i5000_amb_read_config32(d, 4, AMB_DCALCSR))) + & (1 << 31)); + + if (status & (1 << 30)) { + printk(BIOS_SPEW, "failed (status 0x%08x)\n", status); + return -1; + } + + printk(BIOS_SPEW, "done\n"); + return 0; +} + +static int i5000_ddr_calibration(struct i5000_fbdimm *d) +{ + u32 status; + + i5000_amb_write_config32(d, 3, AMB_MBADDR, 0); + i5000_amb_write_config32(d, 3, AMB_MBCSR, 0x80100050); + while((status = i5000_amb_read_config32(d, 3, AMB_MBCSR)) & (1 << 31)); + + i5000_amb_write_config32(d, 3, AMB_MBCSR, 0x80200050); + while((status = i5000_amb_read_config32(d, 3, AMB_MBCSR)) & (1 << 31)); + + if (ddr_command(d, d->ranks == 2 ? 3 : 1, 0, AMB_DCALCSR_OPCODE_RECV_ENABLE_CAL) || + ddr_command(d, d->ranks == 2 ? 3 : 1, 0, AMB_DCALCSR_OPCODE_DQS_DELAY_CAL)) + return -1; + return 0; +} + +static int i5000_ddr_init(struct i5000_fbdimm *d) +{ + + int rank; + u32 val; + u8 odt; + + for(rank = 0; rank < d->ranks; rank++) { + printk(BIOS_DEBUG, "%s: %d/%d/%d rank %d\n", __func__, + d->branch->num, d->channel->num, d->num, rank); + + if (ddr_command(d, 1 << rank, + 0, AMB_DCALCSR_OPCODE_NOP)) + return -1; + + if (ddr_command(d, 1 << rank, + 0x4000000, AMB_DCALCSR_OPCODE_PRECHARGE)) + return -1; + + /* EMRS(2) */ + if (ddr_command(d, 1 << rank, + 2, AMB_DCALCSR_OPCODE_MRS_EMRS)) + return -1; + + /* EMRS(3) */ + if (ddr_command(d, 1 << rank, + 3, AMB_DCALCSR_OPCODE_MRS_EMRS)) + return -1; + + /* EMRS(1) */ + if (ddr_command(d, 1 << rank, + 1, AMB_DCALCSR_OPCODE_MRS_EMRS)) + return -1; + + /* MRS: DLL reset */ + if (ddr_command(d, 1 << rank, + 0x1000000, AMB_DCALCSR_OPCODE_MRS_EMRS)) + return -1; + + udelay(20); + + if (ddr_command(d, 1 << rank, + 0x4000000, AMB_DCALCSR_OPCODE_PRECHARGE)) + return -1; + + if (ddr_command(d, 1 << rank, + 0, AMB_DCALCSR_OPCODE_REFRESH)) + return -1; + + if (ddr_command(d, 1 << rank, 0, + AMB_DCALCSR_OPCODE_REFRESH)) + return -1; + + /* burst length + cas latency */ + val = (((d->setup->bl & BL_BL8) ? 3 : 2) << 16) | + (1 << 19) /* interleaved burst */ | + (d->setup->t_cl << 20) | + (((d->setup->t_wr - 1) & 7) << 25); + + printk(BIOS_DEBUG, "MRS: 0x%08x\n", val); + if (ddr_command(d, 1 << rank, + val, AMB_DCALCSR_OPCODE_MRS_EMRS)) + return -1; + + /* OCD calibration default */ + if (ddr_command(d, 1 << rank, 0x03800001, + AMB_DCALCSR_OPCODE_MRS_EMRS)) + return -1; + + + odt = d->odt; + if (rank) + odt >>= 4; + + val = (d->setup->t_al << 19) | + ((odt & 1) << 18) | + ((odt & 2) << 21) | 1; + + printk(BIOS_DEBUG, "EMRS(1): 0x%08x\n", val); + + /* ODT, OCD exit, additive latency */ + if (ddr_command(d, 1 << rank, val, AMB_DCALCSR_OPCODE_MRS_EMRS)) + return -1; + } + return 0; +} + +static int i5000_amb_preinit(struct i5000_fbdimm *d) +{ + u32 *p32 = (u32 *)d->amb_personality_bytes; + u16 *p16 = (u16 *)d->amb_personality_bytes; + u32 id, drc, fbdsbcfg = 0x0909; + + printk(BIOS_DEBUG, "%s: %d/%d/%d\n", __func__, + d->branch->num, d->channel->num, d->num); + + i5000_amb_smbus_write_config32(d, 1, 0xb0, p32[0]); + i5000_amb_smbus_write_config16(d, 1, 0xb4, p16[2]); + + drc = (d->setup->t_al << 4) | (d->setup->t_cl); + printk(BIOS_SPEW, "DRC: %02X, CMD2DATANXT: %02x\n", drc, + d->cmd2datanxt[d->setup->ddr_speed]); + + switch(d->setup->ddr_speed) { + case DDR_533MHZ: + fbdsbcfg |= (1 << 16); + break; + case DDR_667MHZ: + fbdsbcfg |= (2 << 16); + break; + default: + return -1; + } + + printk(BIOS_DEBUG, "FBDSBCFGNXT: %08x\n", fbdsbcfg); + i5000_amb_smbus_write_config32(d, 1, AMB_FBDSBCFGNXT, fbdsbcfg); + i5000_amb_smbus_write_config32(d, 1, AMB_FBDLOCKTO, 0x1651); + i5000_amb_smbus_write_config8(d, 1, AMB_CMD2DATANXT, + d->cmd2datanxt[d->setup->ddr_speed]); + + i5000_amb_smbus_write_config8(d, 3, AMB_DRC, drc); + + if (!i5000_amb_smbus_read_config32(d, 0, 0, &id)) { + d->vendor = id & 0xffff; + d->device = id >> 16; + } + + pci_mmio_write_config8(d->branch->branchdev, + d->channel->num ? I5000_FBDSBTXCFG1 : I5000_FBDSBTXCFG0, 0x04); + return 0; +} + +static void i5000_fbd_next_state(struct i5000_fbd_branch *b, int state) +{ + int timeout = 10000; + device_t dev = b->branchdev; + + printk(BIOS_DEBUG, " FBD state branch %d: %02x,", b->num, state); + + pci_mmio_write_config8(dev, I5000_FBDHPC, state); + + printk(BIOS_DEBUG, "waiting for new state..."); + + while(pci_mmio_read_config8(dev, I5000_FBDST) != state && timeout--) + udelay(10); + + if (timeout) { + printk(BIOS_DEBUG, "done\n"); + return; + } + + printk(BIOS_ERR, "timeout while entering state %02x on branch %d\n", + state, b->num); +} + +static int i5000_wait_pattern_recognized(struct i5000_fbd_channel *c) +{ + int i = 10; + device_t dev = PCI_ADDR(0, c->branch->num ? 22 : 21, 0, + c->num ? I5000_FBDISTS1 : I5000_FBDISTS0); + + printk(BIOS_DEBUG, " waiting for pattern recognition..."); + while(pci_mmio_read_config16(dev, 0) != 0x1fff && --i > 0) + udelay(5000); + + printk(BIOS_DEBUG, i ? "done\n" : "failed\n"); + printk(BIOS_DEBUG, "%d/%d Round trip latency: %d\n", c->branch->num, c->num, + pci_mmio_read_config8(c->branch->branchdev, c->num ? I5000_FBDLVL1 : I5000_FBDLVL0) & 0x3f); + return !i; +} + +static const char *pattern_names[16] = { + "EI", "EI", "EI", "EI", + "EI", "EI", "EI", "EI", + "TS0", "TS1", "TS2", "TS3", + "RESERVED", "TS2 (merge disabled)", "TS2 (merge enabled)","All ones", +}; + +static int i5000_drive_pattern(struct i5000_fbd_channel *c, int pattern, int wait) +{ + device_t dev = PCI_ADDR(0, c->branch->num ? 22 : 21, 0, + c->num ? I5000_FBDICMD1 : I5000_FBDICMD0); + + printk(BIOS_DEBUG, " %d/%d driving pattern %s to AMB%d (%02x)\n", + c->branch->num, c->num, + pattern_names[(pattern >> 4) & 0xf], pattern & 3, pattern); + pci_mmio_write_config8(dev, 0, pattern); + + if (!wait) + return 0; + + return i5000_wait_pattern_recognized(c); +} + +static int i5000_set_ambpresent(struct i5000_fbd_channel *c) +{ + int i; + device_t branchdev = c->branch->branchdev; + u16 ambpresent = 0x8000; + + for(i = 0; i < I5000_MAX_DIMM_PER_CHANNEL; i++) { + if (c->dimm[i].present) + ambpresent |= (1 << i); + } + + printk(BIOS_DEBUG, "AMBPRESENT: %04x\n", ambpresent); + pci_write_config16(branchdev, + c->num ? + I5000_AMBPRESENT1 : \ + I5000_AMBPRESENT0, ambpresent); + + return 0; +} + + +static int i5000_drive_test_patterns(struct i5000_fbd_channel *c, int highest_amb, int mchpad) +{ + device_t branchdev = c->branch->branchdev; + int off = c->num ? 0x100 : 0; + u32 portctl; + int i, cnt = 1000; + + portctl = pci_mmio_read_config32(branchdev, I5000_FBD0IBPORTCTL + off); + portctl &= ~0x01000020; + if (mchpad) + portctl |= 0x00800000; + else + portctl &= ~0x00800000; + portctl &= ~0x01000020; + pci_mmio_write_config32(branchdev, I5000_FBD0IBPORTCTL + off, portctl); + + /* drive calibration patterns */ + if (i5000_drive_pattern(c, I5000_FBDICMD_TS0 | highest_amb, 1)) + return -1; + + if (i5000_drive_pattern(c, I5000_FBDICMD_TS1 | highest_amb, 1)) + return -1; + + while (!(pci_mmio_read_config32(branchdev, I5000_FBD0IBPORTCTL + off) & 4) && cnt--) + udelay(10); + + if (!cnt) { + printk(BIOS_ERR, "IBIST timeout\n"); + return -1; + } + + if (i5000_drive_pattern(c, I5000_FBDICMD_TS2 | highest_amb, 1)) + return -1; + + for(i = 0; i < highest_amb; i++) { + if ((i5000_drive_pattern(c, I5000_FBDICMD_TS2_NOMERGE | i, 1))) + return -1; + } + + if (i5000_drive_pattern(c, I5000_FBDICMD_TS2 | highest_amb, 1)) + return -1; + + if (i5000_drive_pattern(c, I5000_FBDICMD_TS3 | highest_amb, 1)) + return -1; + + if (i5000_set_ambpresent(c)) + return -1; + return 0; +} + +static int i5000_train_channel_idle(struct i5000_fbd_channel *c) +{ + int i; + u32 fbdsbcfg = 0x0b1b; + + switch(c->setup->ddr_speed) { + case DDR_533MHZ: + fbdsbcfg |= (1 << 16); + break; + case DDR_667MHZ: + fbdsbcfg |= (2 << 16); + break; + default: + return -1; + } + + pci_mmio_write_config8(c->branch->branchdev, + c->num ? I5000_FBDSBTXCFG1 : I5000_FBDSBTXCFG0, 0x05); + + for(i = 0; i < 4; i++) { + if (c->dimm[i].present) + i5000_amb_smbus_write_config32(c->dimm + i, 1, AMB_FBDSBCFGNXT, i ? (fbdsbcfg | 0x1000) : fbdsbcfg); + } + + return i5000_drive_pattern(c, I5000_FBDICMD_IDLE, 1); +} + +static int i5000_drive_test_patterns0(struct i5000_fbd_channel *c) +{ + if (i5000_train_channel_idle(c)) + return -1; + + return i5000_drive_test_patterns(c, c->highest_amb, 0); +} + +static int i5000_drive_test_patterns1(struct i5000_fbd_channel *c) +{ + if (i5000_train_channel_idle(c)) + return -1; + + return i5000_drive_test_patterns(c, c->highest_amb, 1); +} + +static int i5000_setup_channel(struct i5000_fbd_channel *c) +{ + device_t branchdev = c->branch->branchdev; + int off = c->branch->num ? 0x100 : 0; + u32 val; + + pci_mmio_write_config32(branchdev, I5000_FBD0IBTXPAT2EN + off, 0); + pci_mmio_write_config32(branchdev, I5000_FBD0IBTXPAT2EN + off, 0); + pci_mmio_write_config32(branchdev, I5000_FBD0IBTXMSK + off, 0x3ff); + pci_mmio_write_config32(branchdev, I5000_FBD0IBRXMSK + off, 0x1fff); + + pci_mmio_write_config16(branchdev, off + 0x0162, c->used ? 0x20db : 0x18db); + + /* unknown */ + val = pci_mmio_read_config32(branchdev, off + 0x0164); + val &= 0xfffbcffc; + val |= 0x4004; + pci_mmio_write_config32(branchdev, off + 0x164, val); + + pci_mmio_write_config32(branchdev, off + 0x15c, 0xff); + i5000_drive_pattern(c, I5000_FBDICMD_ALL_ONES, 0); + return 0; +} + +static int i5000_link_training0(struct i5000_fbd_branch *b) +{ + device_t branchdev = b->branchdev; + + pci_mmio_write_config8(branchdev, I5000_FBDPLLCTRL, b->used ? 0 : 1); + + if (i5000_for_each_channel(b, i5000_setup_channel)) + return -1; + + if (i5000_for_each_channel(b, i5000_train_channel_idle)) + return -1; + + i5000_fbd_next_state(b, I5000_FBDHPC_STATE_INIT); + + if (i5000_for_each_channel(b, i5000_drive_test_patterns0)) + return -1; + + i5000_fbd_next_state(b, I5000_FBDHPC_STATE_READY); + return 0; +} + +static int i5000_link_training1(struct i5000_fbd_branch *b) +{ + if (i5000_for_each_channel(b, i5000_train_channel_idle)) + return -1; + + i5000_fbd_next_state(b, I5000_FBDHPC_STATE_INIT); + + if (i5000_for_each_channel(b, i5000_drive_test_patterns1)) + return -1; + + i5000_fbd_next_state(b, I5000_FBDHPC_STATE_READY); + return 0; +} + + +static int i5000_amb_check(struct i5000_fbdimm *d) +{ + u32 id = i5000_amb_read_config32(d, 0, 0); + + printk(BIOS_DEBUG, "AMB %d/%d/%d ID: %04x:%04x\n", + d->branch->num, d->channel->num, d->num, + id & 0xffff, id >> 16); + + if ((id & 0xffff) != d->vendor || id >> 16 != d->device) { + printk(BIOS_ERR, "AMB mapping failed\n"); + return -1; + } + return 0; +} + +static int i5000_amb_postinit(struct i5000_fbdimm *d) +{ + u32 *p32 = (u32 *)d->amb_personality_bytes; + u16 *p16 = (u16 *)d->amb_personality_bytes; + + i5000_amb_write_config16(d, 1, 0xb6, p16[3]); + i5000_amb_write_config32(d, 1, 0xb8, p32[2]); + i5000_amb_write_config16(d, 1, 0xbc, p16[6]); + return 0; +} + +static int i5000_amb_dram_timing_init(struct i5000_fbdimm *d) +{ + struct i5000_fbd_setup *s; + u32 val, tref; + int refi; + + s = d->setup; + + printk(BIOS_DEBUG, "DIMM %d/%d/%d config:\n", + d->branch->num, d->channel->num, d->num); + + val = 0x44; + printk(BIOS_DEBUG, "\tDDR2ODTC: 0x%02x\n", val); + i5000_amb_write_config8(d, 4, AMB_DDR2ODTC, val); + + val = (0x0c << 24) | /* CLK control */ + (1 << 18) | /* ODTZ enabled */ + (((d->setup->bl & BL_BL8) ? 1 : 0) << 8) | /* 8 byte burst length supported */ + ((d->setup->t_al & 0x0f) << 4) | /* additive latency */ + (d->setup->t_cl & 0x0f); /* CAS latency */ + + if (d->ranks > 1) { + val |= (0x03 << 9); + } else { + val |= (0x01 << 9); + } + + printk(BIOS_DEBUG, "AMB_DRC: %08x\n", val); + i5000_amb_write_config32(d, 3, AMB_DRC, val); + + val = (d->sdram_width << 30) | + ((d->ranks == 2 ? 1 : 0) << 29) | + ((d->banks == 8 ? 1 : 0) << 28) | + ((d->rows - 13) << 26) | + ((d->columns - 10) << 24) | + (1 << 16) | /* Auto refresh exit */ + (0x27 << 8) | /* t_xsnr */ + (d->setup->t_rp << 4) | + (((d->t_ck_min * d->mtb_dividend) / d->mtb_divisor) & 0x0f); + + printk(BIOS_DEBUG, "\tAMB_DSREFTC: %08x\n", val); + i5000_amb_write_config32(d, 3, AMB_DSREFTC, val); + + tref = 15; + + switch(d->t_refi & 0x0f) { + case 0: + refi = 15625; + break; + case 1: + refi = 3900; + tref = 3; + break; + case 2: + refi = 7800; + tref = 7; + break; + case 3: + refi = 31250; + break; + case 4: + refi = 62500; + break; + case 5: + refi = 125000; + break; + default: + printk(BIOS_ERR, "unsupported t_refi value: %d, using 7.8us\n", + d->t_refi & 0x0f); + refi = 7800; + break; + } + + s->t_ref = tref; + val = delay_ns_to_clocks(d, refi) | (s->t_rfc << 16); + + printk(BIOS_DEBUG, "\tAMB_DAREFTC: %08x\n", val); + i5000_amb_write_config32(d, 3, AMB_DAREFTC, val); + + u8 t_r2w = ((s->bl & BL_BL8) ? 4 : 2) + + (((d->t_ck_min * d->mtb_dividend) / d->mtb_divisor)); + u8 t_w2r = (s->t_cl - 1) + ((s->bl & BL_BL8) ? 4 : 2) + s->t_wtr; + + val = ((6 - s->t_rp) << 8) | ((6 - s->t_rcd) << 10) | + ((26 - s->t_rc) << 12) | ((9 - s->t_wr) << 16) | + ((12 - t_w2r) << 20) | ((10 - t_r2w) << 24) | + ((s->t_rtp - 2) << 27); + + switch(s->t_ras) { + case 15: + val |= (1 << 29); + break; + case 12: + val |= (2 << 29); + break; + default: + break; + } + + printk(BIOS_DEBUG, "\tAMB_DRT: %08x\n", val); + i5000_amb_write_config32(d, 3, AMB_DRT, val); + return 0; +} + +static int i5000_do_amb_membist_start(struct i5000_fbdimm *d, int rank, int pattern) +{ + printk(BIOS_DEBUG, "DIMM %d/%d/%d rank %d pattern %d\n", + d->branch->num, d->channel->num, d->num, rank, pattern); + + i5000_amb_write_config32(d, 3, AMB_DAREFTC, + i5000_amb_read_config32(d, 3, AMB_DAREFTC) | 0x8000); + + i5000_amb_write_config32(d, 3, AMB_MBLFSRSED, 0x12345678); + i5000_amb_write_config32(d, 3, AMB_MBADDR, 0); + i5000_amb_write_config32(d, 3, AMB_MBCSR, 0x800000f0 | (rank << 20) | ((pattern & 3) << 8)); + return 0; +} + +static int i5000_do_amb_membist_status(struct i5000_fbdimm *d, int rank) +{ + int cnt = 1000; + u32 res; + + while((res = i5000_amb_read_config32(d, 3, AMB_MBCSR)) & (1 << 31) && cnt--) + udelay(1000); + + if (cnt && !(res & (1 << 30))) + return 0; + + printk(BIOS_ERR, "DIMM %d/%d/%d rank %d failed membist check\n", + d->branch->num, d->channel->num, d->num, rank); + return -1; +} + +static int i5000_amb_membist_zero1_start(struct i5000_fbdimm *d) +{ + if (i5000_do_amb_membist_start(d, 1, 0)) + return -1; + return 0; +} + +static int i5000_amb_membist_zero2_start(struct i5000_fbdimm *d) +{ + + if (d->ranks < 2) + return 0; + if (i5000_do_amb_membist_start(d, 2, 0)) + return -1; + return 0; +} + +static int i5000_amb_membist_status1(struct i5000_fbdimm *d) +{ + if (i5000_do_amb_membist_status(d, 1)) + return -1; + return 0; +} + +static int i5000_amb_membist_status2(struct i5000_fbdimm *d) +{ + if (d->ranks < 2) + return 0; + + if (i5000_do_amb_membist_status(d, 2)) + return -1; + return 0; +} + +static int i5000_amb_membist_end(struct i5000_fbdimm *d) +{ + printk(BIOS_DEBUG, "AMB_DRC MEMBIST: %08x\n", i5000_amb_read_config32(d, 3, AMB_DRC)); + return 0; +} + +static int i5000_membist(struct i5000_fbd_setup *setup) +{ + return i5000_for_each_dimm_present(setup, i5000_amb_membist_zero1_start) || + i5000_for_each_dimm_present(setup, i5000_amb_membist_status1) || + i5000_for_each_dimm_present(setup, i5000_amb_membist_zero2_start) || + i5000_for_each_dimm_present(setup, i5000_amb_membist_status2) || + i5000_for_each_dimm_present(setup, i5000_amb_membist_end); +} + +static int i5000_enable_mc_autorefresh(struct i5000_fbdimm *d) +{ + u32 tmp = i5000_amb_read_config32(d, 3, AMB_DSREFTC); + tmp &= ~(1 << 16); + printk(BIOS_DEBUG, "new AMB_DSREFTC: 0x%08x\n", tmp); + i5000_amb_write_config32(d, 3, AMB_DSREFTC, tmp); + return 0; +} + +static int i5000_amb_clear_error_status(struct i5000_fbdimm *d) +{ + i5000_amb_write_config32(d, 1, AMB_FERR, 9); + i5000_amb_write_config32(d, 1, AMB_NERR, 9); + i5000_amb_write_config32(d, 1, AMB_EMASK, 0xf2); + i5000_amb_write_config8(d, 3, 0x80, 0xcf); + i5000_amb_write_config8(d, 3, 0x81, 0xd3); + i5000_amb_write_config8(d, 3, 0x82, 0xf8); + return 0; +} + +static void i5000_program_mtr(struct i5000_fbd_channel *c, int mtr) +{ + u32 val; + + if (c->dimm[0].present || c->dimm[1].present) { + val = (((c->columns - 10) & 3) | + (((c->rows - 13) & 3) << 2) | + (((c->ranks == 2) ? 1 : 0) << 4) | + (((c->banks == 8) ? 1 : 0) << 5) | + ((c->width ? 1 : 0) << 6) | + (1 << 7) | /* Electrical Throttling enabled */ + (1 << 8)); /* DIMM present and compatible */ + printk(BIOS_DEBUG, "MTR0: %04x\n", val); + pci_mmio_write_config16(c->branch->branchdev, mtr, val); + } + + if (c->dimm[2].present || c->dimm[3].present) { + val = (((c->columns - 10) & 3) | + (((c->rows - 13) & 3) << 4) | + ((c->ranks ? 1 : 0) << 4) | + (((c->banks == 8) ? 1 : 0) << 5) | + ((c->width ? 1 : 0) << 6) | + (1 << 7) | /* Electrical Throttling enabled */ + (1 << 8)); /* DIMM present and compatible */ + printk(BIOS_DEBUG, "MTR1: %04x\n", val); + pci_mmio_write_config16(c->branch->branchdev, mtr+2, val); + } +} + +static int get_dmir(u8 *rankmap, int *_set, int limit) +{ + int i, dmir = 0, set = 0; + + for(i = 7; set < limit && i >= 0; i--) { + if (!(*rankmap & (1 << i))) + continue; + + *rankmap &= ~(1 << i); + + switch(limit) { + case 1: + dmir |= (i | + (i << 3) | + (i << 6) | + (i << 9)); + break; + case 2: + dmir |= (i << (set * 3)) | + (i << (6 + set * 3)); + break; + case 4: + dmir |= (i << (set * 3)); + break; + + default: + break; + } + set++; + } + *_set = set; + return dmir; +} + +static int i5000_setup_dmir(struct i5000_fbd_branch *b) +{ + struct i5000_fbdimm *d; + device_t dev = b->branchdev; + u8 rankmap = 0, dmir = 0; + u32 dmirval = 0; + int i, set, rankoffset = 0, ranksize = 0, ranks = 0; + + if (!b->used) + return 0; + + for(i = 0; i < I5000_MAX_DIMM_PER_CHANNEL; i++) { + rankmap >>= 2; + d = b->channel[0].dimm + i; + + if (!d->present) + continue; + + if (d->ranks == 2) { + rankmap |= 0xc0; + ranks += 2; + } else { + rankmap |= 0x40; + ranks++; + } + } + + printk(BIOS_DEBUG, "total ranks: %d, rankmap: %02x\n", ranks, rankmap); + + dmir = I5000_DMIR0; + + ranksize = b->channel[0].dimm[0].ranksize << 8; + + if (!b->setup->single_channel) + ranksize <<= 1; + + while(ranks) { + + if (ranks >= 4) + dmirval = get_dmir(&rankmap, &set, 4); + else if (ranks >= 2) + dmirval = get_dmir(&rankmap, &set, 2); + else + dmirval = get_dmir(&rankmap, &set, 1); + + ranks -= set; + + dmirval |= rankoffset + (set * ranksize); + + rankoffset += (set * ranksize); + + printk(BIOS_DEBUG, "DMIR%d: %08x\n", (dmir - I5000_DMIR0) >> 2, + dmirval); + pci_mmio_write_config32(dev, dmir, dmirval); + dmir += 4; + } + + for(; dmir <= I5000_DMIR4; dmir += 4) { + printk(BIOS_DEBUG, "DMIR%d: %08x\n", (dmir - I5000_DMIR0) >> 2, + dmirval); + pci_mmio_write_config32(dev, dmir, dmirval); + } + return rankoffset; +} + +static void i5000_setup_interleave(struct i5000_fbd_setup *setup) +{ + device_t dev16 = PCI_ADDR(0, 16, 1, 0); + u32 mir0, mir1, mir2, size0, size1, minsize, tmp; + + size0 = i5000_setup_dmir(&setup->branch[1]) >> 12; + size1 = i5000_setup_dmir(&setup->branch[0]) >> 12; + + minsize = MIN(size0, size1); + + if (size0 > size1) { + tmp = size1; + size1 = size0; + size0 = tmp; + } + + if (size0 == size1) { + mir0 = (size0 << 1) | 3; + mir1 = (size0 << 1); + mir2 = (size0 << 1); + } else if (!size0) { + mir0 = size1 | 1; + mir1 = size1; + mir2 = size1; + } else { + mir0 = (size0 << 1) | 3; + mir1 = (size1 + size0) | 1; + mir2 = size1 + size0; + } + + printk(BIOS_DEBUG, "MIR0: %04x\n", mir0); + printk(BIOS_DEBUG, "MIR1: %04x\n", mir1);; + printk(BIOS_DEBUG, "MIR2: %04x\n", mir2);; + + pci_mmio_write_config16(dev16, I5000_MIR0, mir0); + pci_mmio_write_config16(dev16, I5000_MIR1, mir1); + pci_mmio_write_config16(dev16, I5000_MIR2, mir2); +} + +static int i5000_dram_timing_init(struct i5000_fbd_setup *setup) +{ + device_t dev16 = PCI_ADDR(0, 16, 1, 0); + u32 tolm, drta, drtb, mc, mca; + int t_wrc, bl2; + + bl2 = (setup->bl & BL_BL8) ? 4 :2; + t_wrc = setup->t_rcd + (setup->t_cl - 1) + bl2 + + setup->t_wr + setup->t_rp; + + drta = (setup->t_ref & 0x0f) | + ((setup->t_rrd & 0x0f) << 4) | + ((setup->t_rfc & 0xff) << 8) | + ((setup->t_rc & 0x3f) << 16) | + ((t_wrc & 0x3f) << 22) | + (setup->t_al & 0x07) << 28; + + drtb = (bl2) | + (((1 + bl2 + setup->t_r2r) & 0x0f) << 4) | + (((setup->t_cl - 1 + bl2 + setup->t_wtr) & 0x0f) << 8) | + (((2 + bl2 + setup->t_r2w) & 0x0f) << 12) | + (((bl2 + setup->t_w2rdr) & 0x07) << 16); + + mc = (1 << 30) | /* enable retry */ + (3 << 25) | /* bad RAM threshold */ + (1 << 21) | /* INITDONE */ + (1 << 20) | /* FSB enable */ + /* Electrical throttling: 20 clocks */ + ((setup->ddr_speed == DDR_667MHZ ? 1 : 0) << 18) | + (1 << 8) | /* enhanced scrub mode */ + (1 << 7) | /* enable patrol scrub */ + (1 << 6) | /* enable demand scrubing */ + (1 << 5); /* enable northbound error detection */ + + printk(BIOS_DEBUG, "DRTA: 0x%08x DRTB: 0x%08x MC: 0x%08x\n", drta, drtb, mc); + pci_mmio_write_config32(dev16, I5000_DRTA, drta); + pci_mmio_write_config32(dev16, I5000_DRTB, drtb); + pci_mmio_write_config32(dev16, I5000_MC, mc); + + mca = pci_mmio_read_config32(dev16, I5000_MCA); + + mca |= (7 << 28); + if (setup->single_channel) + mca |= (1 << 14); + else + mca &= ~(1 << 14); + printk(BIOS_DEBUG, "MCA: 0x%08x\n", mca); + pci_mmio_write_config32(dev16, I5000_MCA, mca); + + pci_mmio_write_config32(dev16, I5000_ERRPERR, 0xffffffff); + + i5000_program_mtr(&setup->branch[0].channel[0], I5000_MTR0); + i5000_program_mtr(&setup->branch[0].channel[1], I5000_MTR1); + i5000_program_mtr(&setup->branch[1].channel[0], I5000_MTR0); + i5000_program_mtr(&setup->branch[1].channel[1], I5000_MTR1); + + i5000_setup_interleave(setup); + + if ((tolm = MIN(setup->totalmem, 0xe00)) > 0xe00) + tolm = 0xe00; + + tolm <<= 4; + printk(BIOS_DEBUG, "TOLM: 0x%04x\n", tolm); + pci_mmio_write_config16(dev16, I5000_TOLM, tolm); + return 0; +} + +static void i5000_init_setup(struct i5000_fbd_setup *setup) +{ + int branch, channel, dimm, i = 0; + struct i5000_fbdimm *d; + struct i5000_fbd_channel *c; + struct i5000_fbd_branch *b; + + setup->bl = 3; + /* default to highest memory frequency. If a module doesn't + support it, it will decrease this setting in spd_read */ + setup->ddr_speed = DDR_667MHZ; + + for(branch = 0; branch < I5000_MAX_BRANCH; branch++) { + b = setup->branch + branch; + b->branchdev = PCI_ADDR(0, branch ? 22 : 21, 0, 0); + b->setup = setup; + b->num = branch; + + for(channel = 0; channel < I5000_MAX_CHANNEL; channel++) { + c = b->channel + channel; + c->branch = b; + c->setup = setup; + c->num = channel; + + for(dimm = 0; dimm < I5000_MAX_DIMM_PER_CHANNEL; dimm++) { + d = c->dimm + dimm; + setup->dimms[i++] = d; + d->channel = c; + d->branch = b; + d->setup = setup; + d->num = dimm; + d->ambase = (b->num << 16) | (c->num << 15) | (dimm << 11); + } + } + } +} + +static void i5000_reserved_register_init(struct i5000_fbd_setup *setup) +{ + /* register write captured from vendor BIOS, but undocument by Intel */ + pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), I5000_PROCENABLE, 0x487f7c); + + pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), 0xf4, 0x1588106); + pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), 0xfc, 0x80); + pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), 0x5c, 0x08); + pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), 0x70, 0xfe2c08d); + pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), 0x78, 0xfe2c08d); + + pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), 0x140, 0x18000000); + pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), 0x440, 0x18000000); + pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x18c, 0x18000000); + pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), 0x180, 0x18000000); + pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x180, 0x87ffffff); + + pci_mmio_write_config32(PCI_ADDR(0, 0, 0, 0), 0x200, 0x18000000); + pci_mmio_write_config32(PCI_ADDR(0, 4, 0, 0), 0x200, 0x18000000); + pci_mmio_write_config32(PCI_ADDR(0, 0, 0, 0), 0x208, 0x18000000); + pci_mmio_write_config32(PCI_ADDR(0, 4, 0, 0), 0x208, 0x18000000); + + pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x184, 0x01249249); + pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x154, 0x00000000); + pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x158, 0x02492492); + pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x15c, 0x00000000); + pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x160, 0x00000000); + + pci_mmio_write_config16(PCI_ADDR(0, 19, 0, 0), 0x0090, 0x00000007); + pci_mmio_write_config16(PCI_ADDR(0, 19, 0, 0), 0x0092, 0x0000000f); + + pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x0154, 0x10); + pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x0454, 0x10); + + pci_mmio_write_config32(PCI_ADDR(0, 19, 0, 0), 0x007C, 0x00000001); + pci_mmio_write_config32(PCI_ADDR(0, 19, 0, 0), 0x007C, 0x00000000); + pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0108, 0x000003F0); + pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x010C, 0x00000042); + pci_mmio_write_config16(PCI_ADDR(0, 17, 0, 0), 0x0112, 0x0000); + pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0114, 0x00A0494C); + pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0118, 0x0002134C); + pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x013C, 0x0C008000); + pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0140, 0x0C008000); + pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0144, 0x00008000); + pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0148, 0x00008000); + pci_mmio_write_config32(PCI_ADDR(0, 19, 0, 0), 0x007C, 0x00000002); + pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), 0x01F4, 0x00000800); + + if (setup->branch[0].channel[0].used) + pci_mmio_write_config32(PCI_ADDR(0, 21, 0, 0), 0x010C, 0x004C0C10); + + if (setup->branch[0].channel[1].used) + pci_mmio_write_config32(PCI_ADDR(0, 21, 0, 0), 0x020C, 0x004C0C10); + + if (setup->branch[1].channel[0].used) + pci_mmio_write_config32(PCI_ADDR(0, 22, 0, 0), 0x010C, 0x004C0C10); + + if (setup->branch[1].channel[1].used) + pci_mmio_write_config32(PCI_ADDR(0, 22, 0, 0), 0x020C, 0x004C0C10); +} +static void i5000_dump_error_registers(void) +{ + device_t dev = PCI_ADDR(0, 16, 1, 0); + + printk(BIOS_ERR, "Dump of FBD error registers:\n" + "FERR_FAT_FBD: 0x%08x NERR_FAT_FBD: 0x%08x\n" + "FERR_NF_FBD: 0x%08x NERR_NF_FBD: 0x%08x\n" + "EMASK_FBD: 0x%08x\n" + "ERR0_FBD: 0x%08x\n" + "ERR1_FBD: 0x%08x\n" + "ERR2_FBD: 0x%08x\n" + "MC_ERR_FBD: 0x%08x\n", + pci_mmio_read_config32(dev, I5000_FERR_FAT_FBD), + pci_mmio_read_config32(dev, I5000_NERR_FAT_FBD), + pci_mmio_read_config32(dev, I5000_FERR_NF_FBD), + pci_mmio_read_config32(dev, I5000_NERR_NF_FBD), + pci_mmio_read_config32(dev, I5000_EMASK_FBD), + pci_mmio_read_config32(dev, I5000_ERR0_FBD), + pci_mmio_read_config32(dev, I5000_ERR1_FBD), + pci_mmio_read_config32(dev, I5000_ERR2_FBD), + pci_mmio_read_config32(dev, I5000_MCERR_FBD)); + + printk(BIOS_ERR, "Non recoverable error registers:\n" + "NRECMEMA: 0x%08x NRECMEMB: 0x%08x\n" + "NRECFGLOG: 0x%08x\n", + pci_mmio_read_config32(dev, I5000_NRECMEMA), + pci_mmio_read_config32(dev, I5000_NRECMEMB), + pci_mmio_read_config32(dev, I5000_NRECFGLOG)); + + printk(BIOS_ERR, "Packet data:\n" + "NRECFBDA: 0x%08x\n" + "NRECFBDB: 0x%08x\n" + "NRECFBDC: 0x%08x\n" + "NRECFBDD: 0x%08x\n" + "NRECFBDE: 0x%08x\n", + pci_mmio_read_config32(dev, I5000_NRECFBDA), + pci_mmio_read_config32(dev, I5000_NRECFBDB), + pci_mmio_read_config32(dev, I5000_NRECFBDC), + pci_mmio_read_config32(dev, I5000_NRECFBDD), + pci_mmio_read_config32(dev, I5000_NRECFBDE)); + + printk(BIOS_ERR, "recoverable error registers:\n" + "RECMEMA: 0x%08x RECMEMB: 0x%08x\n" + "RECFGLOG: 0x%08x\n", + pci_mmio_read_config32(dev, I5000_RECMEMA), + pci_mmio_read_config32(dev, I5000_RECMEMB), + pci_mmio_read_config32(dev, I5000_RECFGLOG)); + + printk(BIOS_ERR, "Packet data:\n" + "RECFBDA: 0x%08x\n" + "RECFBDB: 0x%08x\n" + "RECFBDC: 0x%08x\n" + "RECFBDD: 0x%08x\n" + "RECFBDE: 0x%08x\n", + pci_mmio_read_config32(dev, I5000_RECFBDA), + pci_mmio_read_config32(dev, I5000_RECFBDB), + pci_mmio_read_config32(dev, I5000_RECFBDC), + pci_mmio_read_config32(dev, I5000_RECFBDD), + pci_mmio_read_config32(dev, I5000_RECFBDE)); + +} + +static void i5000_try_restart(const char *msg) +{ + printk(BIOS_INFO, msg); + i5000_dump_error_registers(); +// outb(0x06, 0xcf9); + for(;;) asm volatile("hlt"); +} + +static void i5000_pam_setup(void) +{ + pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x59, 0x30); + pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5a, 0x33); + pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5b, 0x33); + pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5c, 0x33); + pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5d, 0x33); + pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5e, 0x33); + pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5f, 0x33); +} + +static int i5000_setup_clocking(struct i5000_fbd_setup *setup) +{ + int fbd, fsb, ddrfrq, ddrfrqnow; + msr_t msr; + device_t dev = PCI_ADDR(0, 16, 1, 0); + + switch(setup->ddr_speed) { + case DDR_667MHZ: + fbd = 667; + break; + case DDR_533MHZ: + fbd = 533; + break; + default: + printk(BIOS_ERR, "%s: unsupported FBD speed\n", __func__); + return 1; + } + + /* mainboard specific callback */ + if (mainboard_set_fbd_clock(fbd)) { + printk(BIOS_ERR, "%s: failed to set FBD speed\n", __func__); + return 1; + } + + msr = rdmsr(0xcd); + + switch(msr.lo & 7) { + case 1: + fsb = 533; + break; + case 4: + fsb = 667; + break; + default: + printk(BIOS_ERR, "%s: unsupported FSB speed: %d\n", __func__, msr.lo & 7); + return 1; + } + + + ddrfrq = pci_mmio_read_config8(PCI_ADDR(0, 16, 1, 0), 0x56); + ddrfrqnow = ddrfrq; + ddrfrq &= ~0x3; + + if (fsb < fbd) + ddrfrq |= 2; + else if (fsb > fbd) + ddrfrq |= 3; + + switch((ddrfrq >> 4) & 3) { + case 0: /* 1:1 mapping */ + pci_mmio_write_config32(dev, I5000_FBDTOHOSTGRCFG0, 0xffffffff); + pci_mmio_write_config32(dev, I5000_FBDTOHOSTGRCFG1, 0x00000000); + pci_mmio_write_config32(dev, I5000_HOSTTOFBDGRCFG, 0xffffffff); + pci_mmio_write_config8(dev, I5000_GRFBDLVLDCFG, 0x00); + pci_mmio_write_config8(dev, I5000_GRHOSTFULLCFG, 0x00); + pci_mmio_write_config8(dev, I5000_GRBUBBLECFG, 0x00); + pci_mmio_write_config8(dev, I5000_GRFBDTOHOSTDBLCFG, 0x00); + break; + case 2: /* 4:5 mapping */ + pci_mmio_write_config32(dev, I5000_FBDTOHOSTGRCFG0, 0x00002323); + pci_mmio_write_config32(dev, I5000_FBDTOHOSTGRCFG1, 0x00000400); + pci_mmio_write_config32(dev, I5000_HOSTTOFBDGRCFG, 0x23023); + pci_mmio_write_config8(dev, I5000_GRFBDLVLDCFG, 0x04); + pci_mmio_write_config8(dev, I5000_GRHOSTFULLCFG, 0x08); + pci_mmio_write_config8(dev, I5000_GRBUBBLECFG, 0x00); + pci_mmio_write_config8(dev, I5000_GRFBDTOHOSTDBLCFG, 0x04); + break; + case 3: + /* 5:4 mapping */ + pci_mmio_write_config32(dev, I5000_FBDTOHOSTGRCFG0, 0x00023230); + pci_mmio_write_config32(dev, I5000_FBDTOHOSTGRCFG1, 0x00000000); + pci_mmio_write_config32(dev, I5000_HOSTTOFBDGRCFG, 0x4323); + pci_mmio_write_config8(dev, I5000_GRFBDLVLDCFG, 0x00); + pci_mmio_write_config8(dev, I5000_GRHOSTFULLCFG, 0x02); + pci_mmio_write_config8(dev, I5000_GRBUBBLECFG, 0x10); + pci_mmio_write_config8(dev, I5000_GRFBDTOHOSTDBLCFG, 0x00); + break; + default: + printk(BIOS_DEBUG, "invalid DDRFRQ: %02x\n", ddrfrq); + return -1; + } + + if (ddrfrq != ddrfrqnow) { + printk(BIOS_DEBUG, "old DDRFRQ: 0x%02x new DDRFRQ: 0x%02x\n", + ddrfrqnow, ddrfrq); + pci_mmio_write_config8(PCI_ADDR(0, 16, 1, 0), 0x56, ddrfrq); + /* FSB:FBD mapping changed, needs hard reset */ + outb(0x06, 0xcf9); + for(;;) asm volatile("hlt"); + } + return 0; +} + +void i5000_fbdimm_init(void) +{ + struct i5000_fbd_setup setup; + u32 mca, mc; + + memset(&setup, 0, sizeof(setup)); + + pci_mmio_write_config16(PCI_ADDR(0, 0, 0, 0), 0x4, 0x144); + + i5000_init_setup(&setup); + + pci_write_config32(PCI_DEV(0, 16, 0), 0xf0, + pci_mmio_read_config32(PCI_ADDR(0, 16, 0, 0), 0xf0) | 0x8000); + + i5000_clear_fbd_errors(); + + printk(BIOS_INFO, "detecting memory modules\n"); + if (i5000_for_each_dimm(&setup, i5000_read_spd_data)) { + printk(BIOS_ERR, "%s: failed to read SPD data\n", __func__); + return; + } + + if (i5000_setup_clocking(&setup)) { + printk(BIOS_ERR, "%s: failed to set FBD clock\n", __func__); + return; + } + + /* posted CAS requires t_AL = t_RCD - 1 */ + setup.t_al = setup.t_rcd - 1; + + printk(BIOS_DEBUG, "global timing parameters:\n" + "CL: %d RAS: %d WRC: %d RC: %d RFC: %d RRD: %d REF: %d W2RDR: %d\n" + "R2W: %d W2R: %d R2R: %d W2W: %d WTR: %d RCD: %d RP %d WR: %d RTP: %d AL: %d\n", + setup.t_cl, setup.t_ras, setup.t_wrc, setup.t_rc, setup.t_rfc, + setup.t_rrd, setup.t_ref, setup.t_w2rdr, setup.t_r2w, setup.t_w2r, + setup.t_r2r, setup.t_w2w, setup.t_wtr, setup.t_rcd, + setup.t_rp, setup.t_wr, setup.t_rtp, setup.t_al); + + setup.single_channel = (!(setup.branch[0].channel[1].used || + setup.branch[1].channel[0].used || + setup.branch[1].channel[1].used)); + + pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), 0x019C, 0x8010c); + pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), 0x01F4, 0); + + /* enable or disable single channel mode */ + mca = pci_mmio_read_config32(PCI_ADDR(0, 16, 1, 0), I5000_MCA); + if (setup.single_channel) + mca |= (1 << 14); + else + mca &= ~(1 << 14); + pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), I5000_MCA, mca); + + /* + * i5000 supports burst length 8 only in single channel mode + * so strip BL_BL8 if we're operating in multichannel mode + */ + + if (!setup.single_channel) + setup.bl &= ~BL_BL8; + + if (!setup.bl) + die("No supported burst length found\n"); + + mc = pci_mmio_read_config32(PCI_ADDR(0, 16, 1, 0), I5000_MC); + /* disable error checking for training */ + pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), I5000_MC, mc & ~0x20); + + printk(BIOS_INFO, "performing fbd link initialization..."); + if (i5000_for_each_branch(&setup, i5000_branch_reset) || + i5000_for_each_dimm_present(&setup, i5000_amb_preinit) || + i5000_for_each_branch(&setup, i5000_link_training0) || + i5000_for_each_dimm_present(&setup, i5000_amb_check) || + i5000_for_each_dimm_present(&setup, i5000_amb_postinit) || + i5000_for_each_branch(&setup, i5000_link_training1)) { + i5000_try_restart("failed\n"); + } + printk(BIOS_INFO, "done\n"); + printk(BIOS_INFO, "initializing memory..."); + + if (i5000_for_each_dimm_present(&setup, i5000_ddr_init) || + i5000_for_each_dimm_present(&setup, i5000_amb_dram_timing_init) || + i5000_for_each_dimm_present(&setup, i5000_ddr_calibration)) { + i5000_try_restart("failed\n"); + } + printk(BIOS_INFO,"done\n"); + printk(BIOS_INFO, "clearing memory..."); + + if (i5000_membist(&setup)) + i5000_try_restart("failed\n"); + else + printk(BIOS_INFO, "done\n"); + + if (i5000_for_each_dimm_present(&setup, i5000_enable_mc_autorefresh)) + i5000_try_restart("failed to enable auto refresh\n"); + + i5000_fbd_next_state(&setup.branch[0], I5000_FBDHPC_STATE_INIT); + i5000_fbd_next_state(&setup.branch[1], I5000_FBDHPC_STATE_INIT); + + if (i5000_for_each_branch(&setup, i5000_link_training0)) + i5000_try_restart("Channel training failed\n"); + + if (setup.branch[0].used) + i5000_fbd_next_state(&setup.branch[0], I5000_FBDHPC_STATE_READY); + + if (setup.branch[1].used) + i5000_fbd_next_state(&setup.branch[1], I5000_FBDHPC_STATE_READY); + + i5000_clear_fbd_errors(); + + /* enable error checking */ + pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), I5000_MC, mc | 0x20); + + i5000_dram_timing_init(&setup); + + i5000_reserved_register_init(&setup); + + i5000_pam_setup(); + + if (i5000_for_each_dimm_present(&setup, i5000_amb_clear_error_status)) + i5000_try_restart("failed to clear error status\n"); + + if (setup.branch[0].used) + i5000_fbd_next_state(&setup.branch[0], I5000_FBDHPC_STATE_ACTIVE); + + if (setup.branch[1].used) + i5000_fbd_next_state(&setup.branch[1], I5000_FBDHPC_STATE_ACTIVE); + +#if CONFIG_NORTHBRIDGE_INTEL_I5000_RAM_CHECK + if (ram_check_nodie(0x000000, 0x0a0000) || + ram_check_nodie(0x100000, MIN(setup.totalmem * 1048576, 0xe0000000))) { + i5000_try_restart("RAM verification failed"); + + } +#endif + + printk(BIOS_INFO, "Memory initialization finished\n"); +} diff --git a/src/northbridge/intel/i5000/raminit.h b/src/northbridge/intel/i5000/raminit.h new file mode 100644 index 0000000..d3fa16a --- /dev/null +++ b/src/northbridge/intel/i5000/raminit.h @@ -0,0 +1,337 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef NORTHBRIDGE_I5000_RAMINIT_H +#define NORTHBRIDGE_I5000_RAMINIT_H + +#include <types.h> +#include <arch/io.h> +#include <arch/romcc_io.h> + +#define I5000_MAX_BRANCH 2 +#define I5000_MAX_CHANNEL 2 +#define I5000_MAX_DIMM_PER_CHANNEL 4 +#define I5000_MAX_DIMMS (I5000_MAX_BRANCH * I5000_MAX_CHANNEL * I5000_MAX_DIMM_PER_CHANNEL) + +#define I5000_FBDRST 0x53 + +#define I5000_SPD_BUSY (1 << 12) +#define I5000_SPD_SBE (1 << 13) +#define I5000_SPD_WOD (1 << 14) +#define I5000_SPD_RDO (1 << 15) + +#define I5000_SPD0 0x74 +#define I5000_SPD1 0x76 + +#define I5000_SPDCMD0 0x78 +#define I5000_SPDCMD1 0x7c + +#define I5000_FBDHPC 0x4f +#define I5000_FBDST 0x4b + +#define I5000_FBDHPC_STATE_RESET 0x00 +#define I5000_FBDHPC_STATE_INIT 0x10 +#define I5000_FBDHPC_STATE_READY 0x20 +#define I5000_FBDHPC_STATE_ACTIVE 0x30 + +#define I5000_FBDISTS0 0x58 +#define I5000_FBDISTS1 0x5a + +#define I5000_FBDLVL0 0x44 +#define I5000_FBDLVL1 0x45 + +#define I5000_FBDICMD0 0x46 +#define I5000_FBDICMD1 0x47 + +#define I5000_FBDICMD_IDLE 0x00 +#define I5000_FBDICMD_TS0 0x80 +#define I5000_FBDICMD_TS1 0x90 +#define I5000_FBDICMD_TS2 0xa0 +#define I5000_FBDICMD_TS3 0xb0 +#define I5000_FBDICMD_TS2_MERGE 0xd0 +#define I5000_FBDICMD_TS2_NOMERGE 0xe0 +#define I5000_FBDICMD_ALL_ONES 0xf0 + +#define I5000_AMBPRESENT0 0x64 +#define I5000_AMBPRESENT1 0x66 + +#define I5000_FBDSBTXCFG0 0xc0 +#define I5000_FBDSBTXCFG1 0xc1 + +#define I5000_PROCENABLE 0xf0 +#define I5000_FBD0IBPORTCTL 0x180 +#define I5000_FBD0IBTXPAT2EN 0x1a8 +#define I5000_FBD0IBRXPAT2EN 0x1ac + +#define I5000_FBD0IBTXMSK 0x18c +#define I5000_FBD0IBRXMSK 0x190 + +#define I5000_FBDPLLCTRL 0x1c0 + +/* dev 16, function 1 registers */ +#define I5000_MC 0x40 +#define I5000_DRTA 0x48 +#define I5000_DRTB 0x4c +#define I5000_ERRPERR 0x50 +#define I5000_MCA 0x58 +#define I5000_TOLM 0x6c +#define I5000_MIR0 0x80 +#define I5000_MIR1 0x84 +#define I5000_MIR2 0x88 +#define I5000_AMIR0 0x8c +#define I5000_AMIR1 0x90 +#define I5000_AMIR2 0x94 + +#define I5000_FERR_FAT_FBD 0x98 +#define I5000_NERR_FAT_FBD 0x9c +#define I5000_FERR_NF_FBD 0xa0 +#define I5000_NERR_NF_FBD 0xa4 +#define I5000_EMASK_FBD 0xa8 +#define I5000_ERR0_FBD 0xac +#define I5000_ERR1_FBD 0xb0 +#define I5000_ERR2_FBD 0xb4 +#define I5000_MCERR_FBD 0xb8 +#define I5000_NRECMEMA 0xbe +#define I5000_NRECMEMB 0xc0 +#define I5000_NRECFGLOG 0xc4 +#define I5000_NRECMEMA 0xbe +#define I5000_NRECFBDA 0xc8 +#define I5000_NRECFBDB 0xcc +#define I5000_NRECFBDC 0xd0 +#define I5000_NRECFBDD 0xd4 +#define I5000_NRECFBDE 0xd8 + +#define I5000_REDMEMB 0x7c +#define I5000_RECMEMA 0xe2 +#define I5000_RECMEMB 0xe4 +#define I5000_RECFGLOG 0xe8 +#define I5000_RECFBDA 0xec +#define I5000_RECFBDB 0xf0 +#define I5000_RECFBDC 0xf4 +#define I5000_RECFBDD 0xf8 +#define I5000_RECFBDE 0xfc + +#define I5000_FBDTOHOSTGRCFG0 0x160 +#define I5000_FBDTOHOSTGRCFG1 0x164 +#define I5000_HOSTTOFBDGRCFG 0x168 +#define I5000_GRFBDLVLDCFG 0x16c +#define I5000_GRHOSTFULLCFG 0x16d +#define I5000_GRBUBBLECFG 0x16e +#define I5000_GRFBDTOHOSTDBLCFG 0x16f + +/* dev 16, function 2 registers */ +#define I5000_FERR_GLOBAL 0x40 +#define I5000_NERR_GLOBAL 0x44 + +/* dev 21, function 0 registers */ +#define I5000_MTR0 0x80 +#define I5000_MTR1 0x84 +#define I5000_MTR2 0x88 +#define I5000_MTR3 0x8c +#define I5000_DMIR0 0x90 +#define I5000_DMIR1 0x94 +#define I5000_DMIR2 0x98 +#define I5000_DMIR3 0x9c +#define I5000_DMIR4 0xa0 + +#define DEFAULT_AMBASE 0xfe000000 + +/* AMB function 1 registers */ +#define AMB_FBDSBCFGNXT 0x54 +#define AMB_FBDLOCKTO 0x68 +#define AMB_EMASK 0x8c +#define AMB_FERR 0x90 +#define AMB_NERR 0x94 +#define AMB_CMD2DATANXT 0xe8 + +/* AMB function 3 registers */ +#define AMB_DAREFTC 0x70 +#define AMB_DSREFTC 0x74 +#define AMB_DRT 0x78 +#define AMB_DRC 0x7c + +#define AMB_MBCSR 0x40 +#define AMB_MBADDR 0x44 +#define AMB_MBLFSRSED 0xa4 + +/* AMB function 4 registers */ +#define AMB_DCALCSR 0x40 +#define AMB_DCALADDR 0x44 +#define AMB_DCALCSR_START (1 << 31) + +#define AMB_DCALCSR_OPCODE_NOP 0x00 +#define AMB_DCALCSR_OPCODE_REFRESH 0x01 +#define AMB_DCALCSR_OPCODE_PRECHARGE 0x02 +#define AMB_DCALCSR_OPCODE_MRS_EMRS 0x03 +#define AMB_DCALCSR_OPCODE_DQS_DELAY_CAL 0x05 +#define AMB_DCALCSR_OPCODE_RECV_ENABLE_CAL 0x0c +#define AMB_DCALCSR_OPCODE_SELF_REFRESH_ENTRY 0x0d + +#define AMB_DDR2ODTC 0xfc + +#define FBDIMM_SPD_SDRAM_ADDRESSING 0x04 +#define FBDIMM_SPD_MODULE_ORGANIZATION 0x07 +#define FBDIMM_SPD_FTB 0x08 +#define FBDIMM_SPD_MTB_DIVIDEND 0x09 +#define FBDIMM_SPD_MTB_DIVISOR 0x0a +#define FBDIMM_SPD_MIN_TCK 0x0b +#define FBDIMM_SPD_CAS_LATENCIES 0x0d +#define FBDIMM_SPD_CAS_MIN_LATENCY 0x0e +#define FBDIMM_SPD_T_WR 0x10 +#define FBDIMM_SPD_T_RCD 0x13 +#define FBDIMM_SPD_T_RRD 0x14 +#define FBDIMM_SPD_T_RP 0x15 +#define FBDIMM_SPD_T_RAS_RC_MSB 0x16 +#define FBDIMM_SPD_T_RAS 0x17 +#define FBDIMM_SPD_T_RC 0x18 +#define FBDIMM_SPD_T_RFC 0x19 +#define FBDIMM_SPD_T_WTR 0x1b +#define FBDIMM_SPD_T_RTP 0x1c +#define FBDIMM_SPD_BURST_LENGTHS_SUPPORTED 0x1d +#define FBDIMM_SPD_ODT 0x4f +#define FBDIMM_SPD_T_REFI 0x20 +#define FBDIMM_SPD_T_BB 0x83 +#define FBDIMM_SPD_CMD2DATA_800 0x54 +#define FBDIMM_SPD_CMD2DATA_667 0x55 +#define FBDIMM_SPD_CMD2DATA_533 0x56 + +void i5000_fbdimm_init(void); + +#define I5000_BURST4 0x01 +#define I5000_BURST8 0x02 +#define I5000_BURST_CHOP 0x80 + +#define I5000_ODT_50 4 +#define I5000_ODT_75 2 +#define I5000_ODT_150 1 + +enum ddr_speeds { + DDR_533MHZ, + DDR_667MHZ, + DDR_MAX, +}; + +struct i5000_fbdimm { + struct i5000_fbd_branch *branch; + struct i5000_fbd_channel *channel; + struct i5000_fbd_setup *setup; + enum ddr_speeds speed; + int num; + int present:1; + u32 ambase; + + /* SPD data */ + u8 amb_personality_bytes[14]; + u8 banks; + u8 rows; + u8 columns; + u8 ranks; + u8 odt; + u8 sdram_width; + u8 mtb_divisor; + u8 mtb_dividend; + u8 t_ck_min; + u8 min_cas_latency; + u8 t_rrd; + u16 t_rfc; + u8 t_wtr; + u8 t_refi; + u8 cmd2datanxt[DDR_MAX]; + + u16 vendor; + u16 device; + + /* memory rank size in MB */ + int ranksize; +}; + +struct i5000_fbd_channel { + struct i5000_fbdimm dimm[I5000_MAX_DIMM_PER_CHANNEL]; + struct i5000_fbd_branch *branch; + struct i5000_fbd_setup *setup; + int num; + int used; + int highest_amb; + int columns; + int rows; + int ranks; + int banks; + int width; + /* memory size in MB on this channel */ + int totalmem; +}; + +struct i5000_fbd_branch { + struct i5000_fbd_channel channel[I5000_MAX_CHANNEL]; + struct i5000_fbd_setup *setup; + device_t branchdev; + int num; + int used; + /* memory size in MB on this branch */ + int totalmem; +}; + +enum odt { + ODT_150OHM=1, + ODT_50OHM=4, + ODT_75OHM=2, +}; + +enum bl { + BL_BL4=1, + BL_BL8=2, +}; + +struct i5000_fbd_setup { + struct i5000_fbd_branch branch[I5000_MAX_BRANCH]; + struct i5000_fbdimm *dimms[I5000_MAX_DIMMS]; + enum bl bl; + enum ddr_speeds ddr_speed; + + int single_channel:1; + u32 tolm; + + /* global SDRAM timing parameters */ + u8 t_al; + u8 t_cl; + u8 t_ras; + u8 t_wrc; + u8 t_rc; + u8 t_rfc; + u8 t_rrd; + u8 t_ref; + u8 t_w2rdr; + u8 t_r2w; + u8 t_w2r; + u8 t_r2r; + u8 t_w2w; + u8 t_wtr; + u8 t_rcd; + u8 t_rp; + u8 t_wr; + u8 t_rtp; + /* memory size in MB */ + int totalmem; +}; + +int mainboard_set_fbd_clock(int); +#define AMB_ADDR(base, fn, reg) (base | ((fn & 7) << 8) | ((reg & 0xff))) +#endif diff --git a/src/northbridge/intel/i5000/udelay.c b/src/northbridge/intel/i5000/udelay.c new file mode 100644 index 0000000..6462fe0 --- /dev/null +++ b/src/northbridge/intel/i5000/udelay.c @@ -0,0 +1,84 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <delay.h> +#include <stdint.h> +#include <cpu/x86/tsc.h> +#include <cpu/x86/msr.h> +#include <console/console.h> +/** + * Intel Core(tm) cpus always run the TSC at the maximum possible CPU clock + */ + +void udelay(u32 us) +{ + u32 dword; + tsc_t tsc, tsc1, tscd; + msr_t msr; + u32 fsb = 0, divisor; + u32 d; /* ticks per us */ + u32 dn = 0x1000000 / 2; /* how many us before we need to use hi */ + + msr = rdmsr(0xcd); + switch (msr.lo & 0x07) { + case 5: + fsb = 400; + break; + case 1: + fsb = 533; + break; + case 3: + fsb = 667; + break; + case 2: + fsb = 800; + break; + case 0: + fsb = 1067; + break; + case 4: + fsb = 1333; + break; + case 6: + fsb = 1600; + break; + } + + msr = rdmsr(0x198); + divisor = (msr.hi >> 8) & 0x1f; + + d = fsb * divisor; + + tscd.hi = us / dn; + tscd.lo = (us - tscd.hi * dn) * d; + + tsc1 = rdtsc(); + dword = tsc1.lo + tscd.lo; + if ((dword < tsc1.lo) || (dword < tscd.lo)) { + tsc1.hi++; + } + tsc1.lo = dword; + tsc1.hi += tscd.hi; + + tsc = rdtsc(); + + do { + tsc = rdtsc(); + } while ((tsc.hi < tsc1.hi) || ((tsc.hi == tsc1.hi) && (tsc.lo < tsc1.lo))); +}

1 0

Patch set updated for coreboot: 90c2980 Add Intel i5000 Memory Controller Hub
by Sven Schnelle 01 Feb '12

01 Feb '12

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/491 -gerrit commit 90c2980b2e7902a4df6b0898fe64b3e3aa280735 Author: Sven Schnelle <svens(a)stackframe.org> Date: Wed Feb 1 22:06:45 2012 +0100 Add Intel i5000 Memory Controller Hub Change-Id: Ic169f3f61babfcfa2ddcb84fc0267ebcf8c5f3bb Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/northbridge/intel/Kconfig | 1 + src/northbridge/intel/Makefile.inc | 1 + src/northbridge/intel/i5000/Kconfig | 26 + src/northbridge/intel/i5000/Makefile.inc | 21 + src/northbridge/intel/i5000/chip.h | 23 + src/northbridge/intel/i5000/northbridge.c | 188 +++ src/northbridge/intel/i5000/raminit.c | 1771 +++++++++++++++++++++++++++++ src/northbridge/intel/i5000/raminit.h | 337 ++++++ src/northbridge/intel/i5000/udelay.c | 84 ++ 9 files changed, 2452 insertions(+), 0 deletions(-) diff --git a/src/northbridge/intel/Kconfig b/src/northbridge/intel/Kconfig index 1809d11..31afe6a 100644 --- a/src/northbridge/intel/Kconfig +++ b/src/northbridge/intel/Kconfig @@ -10,3 +10,4 @@ source src/northbridge/intel/i82830/Kconfig source src/northbridge/intel/i855/Kconfig source src/northbridge/intel/i945/Kconfig source src/northbridge/intel/sch/Kconfig +source src/northbridge/intel/i5000/Kconfig diff --git a/src/northbridge/intel/Makefile.inc b/src/northbridge/intel/Makefile.inc index 0d116d0..c599dab 100644 --- a/src/northbridge/intel/Makefile.inc +++ b/src/northbridge/intel/Makefile.inc @@ -11,3 +11,4 @@ subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I855) += i855 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I945GC) += i945 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I945GM) += i945 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SCH) += sch +subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I5000) += i5000 diff --git a/src/northbridge/intel/i5000/Kconfig b/src/northbridge/intel/i5000/Kconfig new file mode 100644 index 0000000..0595a57 --- /dev/null +++ b/src/northbridge/intel/i5000/Kconfig @@ -0,0 +1,26 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config NORTHBRIDGE_INTEL_I5000 + bool + select HAVE_DEBUG_RAM_SETUP + +config NORTHBRIDGE_INTEL_I5000_RAM_CHECK + bool + prompt "Run ramcheck after RAM initialization" diff --git a/src/northbridge/intel/i5000/Makefile.inc b/src/northbridge/intel/i5000/Makefile.inc new file mode 100644 index 0000000..a5623c0 --- /dev/null +++ b/src/northbridge/intel/i5000/Makefile.inc @@ -0,0 +1,21 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2007-2009 coresystems GmbH +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +driver-y += northbridge.c +romstage-y += raminit.c udelay.c diff --git a/src/northbridge/intel/i5000/chip.h b/src/northbridge/intel/i5000/chip.h new file mode 100644 index 0000000..a23be90 --- /dev/null +++ b/src/northbridge/intel/i5000/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +struct northbridge_intel_i5000_config { +}; + +extern struct chip_operations northbridge_intel_i5000_ops; diff --git a/src/northbridge/intel/i5000/northbridge.c b/src/northbridge/intel/i5000/northbridge.c new file mode 100644 index 0000000..3db755c --- /dev/null +++ b/src/northbridge/intel/i5000/northbridge.c @@ -0,0 +1,188 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <arch/io.h> +#include <stdint.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <stdlib.h> +#include <string.h> +#include <bitops.h> +#include <cpu/cpu.h> +#include <boot/tables.h> +#include <arch/acpi.h> +#include <cbmem.h> +#include "chip.h" + +static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + if (!vendor || !device) { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + pci_read_config32(dev, PCI_VENDOR_ID)); + } else { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + ((device & 0xffff) << 16) | (vendor & 0xffff)); + } +} + +static struct pci_operations intel_pci_ops = { + .set_subsystem = intel_set_subsystem, +}; + +static struct device_operations mc_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .scan_bus = 0, + .ops_pci = &intel_pci_ops, +}; + +static const struct pci_driver mc_driver __pci_driver = { + .ops = &mc_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x25d8, +}; + +static void cpu_bus_init(device_t dev) +{ + initialize_cpus(dev->link_list); +} + +static void cpu_bus_noop(device_t dev) +{ +} +static struct device_operations cpu_bus_ops = { + .read_resources = cpu_bus_noop, + .set_resources = cpu_bus_noop, + .enable_resources = cpu_bus_noop, + .init = cpu_bus_init, + .scan_bus = 0, +}; + +#if CONFIG_WRITE_HIGH_TABLES +#include <cbmem.h> +#endif + +static void pci_domain_set_resources(device_t dev) +{ + struct resource *resource; + uint32_t hecbase, amsize, tolm; + uint64_t ambase, memsize; + int idx = 0; + device_t dev16_0 = dev_find_slot(0, PCI_DEVFN(16, 0)); + device_t dev16_1 = dev_find_slot(0, PCI_DEVFN(16, 1)); + + tolm = pci_read_config16(dev_find_slot(0, PCI_DEVFN(16, 1)), 0x6c) << 16; + hecbase = pci_read_config16(dev16_0, 0x64) >> 12; + hecbase &= 0xffff; + + ambase = ((u64)pci_read_config32(dev16_0, 0x48) | + (u64)pci_read_config32(dev16_0, 0x4c) << 32); + + amsize = pci_read_config32(dev16_0, 0x50); + ambase &= 0x000000ffffff0000; + + printk(BIOS_DEBUG, "TOLM: 0x%08x AMBASE: 0x%016llx\n", tolm, ambase); + + /* Report the memory regions */ + ram_resource(dev, idx++, 0, 640); + ram_resource(dev, idx++, 768, ((tolm >> 10) - 768)); + + memsize = MAX(pci_read_config16(dev16_1, 0x80) & ~3, + pci_read_config16(dev16_1, 0x84) & ~3); + memsize = MAX(memsize, pci_read_config16(dev16_1, 0x88) & ~3); + + memsize <<= 24; + printk(BIOS_INFO, "MEMSIZE: %08llx\n", memsize); + if (memsize > 0xe0000000) { + memsize -= 0xe0000000; + printk(BIOS_INFO, "high memory: %lldMB\n", memsize / 1048576); + ram_resource(dev, idx++, 4096 * 1024, memsize / 1024); + } + + if (hecbase) { + printk(BIOS_DEBUG, "Adding PCIe config bar at 0x%016llx\n", (u64)hecbase << 28); + resource = new_resource(dev, idx++); + resource->base = (resource_t)(uint64_t)hecbase << 28; + resource->size = (resource_t)256 * 1024 * 1024; + resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + } + + resource = new_resource(dev, idx++); + resource->base = (resource_t)(uint64_t)0xffe00000; + resource->size = (resource_t)0x200000; + resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + + if (ambase && amsize) { + resource = new_resource(dev, idx++); + resource->base = (resource_t)ambase; + resource->size = (resource_t)amsize; + resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + } + + /* add resource for 0xfe6xxxxx range. This range is used by i5000 for + various fixed address registers (BOFL, SPAD, SPADS */ + resource = new_resource(dev, idx++); + resource->base = (resource_t)0xfe600000; + resource->size = (resource_t)0x00100000; + resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + + assign_resources(dev->link_list); + +#if CONFIG_WRITE_HIGH_TABLES + /* Leave some space for ACPI, PIRQ and MP tables */ + high_tables_base = tolm - HIGH_MEMORY_SIZE; + high_tables_size = HIGH_MEMORY_SIZE; + printk(BIOS_DEBUG, "high_tables_base: %08llx, size %lld\n", high_tables_base, high_tables_size); +#endif +} + +static struct device_operations pci_domain_ops = { + .read_resources = pci_domain_read_resources, + .set_resources = pci_domain_set_resources, + .enable_resources = NULL, + .init = NULL, + .scan_bus = pci_domain_scan_bus, +#if CONFIG_MMCONF_SUPPORT_DEFAULT + .ops_pci_bus = &pci_ops_mmconf, +#else + .ops_pci_bus = &pci_cf8_conf1, +#endif +}; + +static void enable_dev(device_t dev) +{ + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) { + dev->ops = &pci_domain_ops; + } else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) { + dev->ops = &cpu_bus_ops; + } +} + +struct chip_operations northbridge_intel_i5000_ops = { + CHIP_NAME("Intel i5000 Northbridge") + .enable_dev = enable_dev, +}; diff --git a/src/northbridge/intel/i5000/raminit.c b/src/northbridge/intel/i5000/raminit.c new file mode 100644 index 0000000..2a04c7e --- /dev/null +++ b/src/northbridge/intel/i5000/raminit.c @@ -0,0 +1,1771 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include "raminit.h" +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <cpu/x86/lapic.h> +#include <console/console.h> +#include <spd.h> +#include <types.h> +#include <southbridge/intel/i63xx/early_smbus.c> +#include <string.h> +#include <cbmem.h> +#include <stdlib.h> +#include <lib.h> +#include <delay.h> + +static int i5000_for_each_channel(struct i5000_fbd_branch *branch, + int (*cb)(struct i5000_fbd_channel *)) +{ + struct i5000_fbd_channel *c; + int ret; + + for(c = branch->channel; c < branch->channel + I5000_MAX_CHANNEL; c++) + if (c->used && (ret = cb(c))) + return ret; + return 0; +} + +static int i5000_for_each_branch(struct i5000_fbd_setup *setup, + int (*cb)(struct i5000_fbd_branch *)) +{ + struct i5000_fbd_branch *b; + int ret; + + for(b = setup->branch; b < setup->branch + I5000_MAX_BRANCH; b++) + if (b->used && (ret = cb(b))) + return ret; + return 0; +} + +static int i5000_for_each_dimm(struct i5000_fbd_setup *setup, + int (*cb)(struct i5000_fbdimm *)) +{ + struct i5000_fbdimm *d; + int ret, i; + + for(i = 0; i < I5000_MAX_DIMMS; i++) { + d = setup->dimms[i]; + if ((ret = cb(d))) { + return ret; + } + } + return 0; +} + +static int i5000_for_each_dimm_present(struct i5000_fbd_setup *setup, + int (*cb)(struct i5000_fbdimm *)) +{ + struct i5000_fbdimm *d; + int ret, i; + + for(i = 0; i < I5000_MAX_DIMMS; i++) { + d = setup->dimms[i]; + if (d->present && (ret = cb(d))) + return ret; + } + return 0; +} + +static int spd_read_byte(struct i5000_fbdimm *d, u8 addr, int count, u8 *out) +{ + u16 status; + device_t dev = d->branch->branchdev; + + int cmdreg = d->channel->num ? I5000_SPDCMD1 : I5000_SPDCMD0; + int stsreg = d->channel->num ? I5000_SPD1 : I5000_SPD0; + + while(count-- > 0) { + pci_write_config32(dev, cmdreg, 0xa8000000 | \ + (d->num & 0x03) << 24 | addr++ << 16); + + int timeout = 1000; + while((status = pci_read_config16(dev, stsreg)) & I5000_SPD_BUSY && timeout--) + udelay(10); + + if (status & I5000_SPD_SBE || !timeout) + return -1; + + if (status & I5000_SPD_RDO) { + *out = status & 0xff; + out++; + } + } + return 0; +} + +static void i5000_clear_fbd_errors(void) +{ + device_t dev16_1, dev16_2; + + dev16_1 = PCI_ADDR(0, 16, 1, 0); + dev16_2 = PCI_ADDR(0, 16, 2, 0); + + pci_mmio_write_config32(dev16_1, I5000_EMASK_FBD, + pci_mmio_read_config32(dev16_1, I5000_EMASK_FBD)); + + pci_mmio_write_config32(dev16_1, I5000_NERR_FAT_FBD, + pci_mmio_read_config32(dev16_1, I5000_NERR_FAT_FBD)); + + pci_mmio_write_config32(dev16_1, I5000_FERR_FAT_FBD, + pci_mmio_read_config32(dev16_1, I5000_FERR_FAT_FBD)); + + pci_mmio_write_config32(dev16_1, I5000_NERR_NF_FBD, + pci_mmio_read_config32(dev16_1, I5000_NERR_NF_FBD)); + + pci_mmio_write_config32(dev16_1, I5000_FERR_NF_FBD, + pci_mmio_read_config32(dev16_1, I5000_FERR_NF_FBD)); + + pci_mmio_write_config32(dev16_2, I5000_FERR_GLOBAL, + pci_mmio_read_config32(dev16_2, I5000_FERR_GLOBAL)); + + pci_mmio_write_config32(dev16_2, I5000_NERR_GLOBAL, + pci_mmio_read_config32(dev16_2, I5000_NERR_GLOBAL)); +} + +static int i5000_branch_reset(struct i5000_fbd_branch *b) +{ + device_t dev = b->branchdev; + + pci_write_config8(dev, I5000_FBDRST, 0x00); + + udelay(5000); + + pci_write_config8(dev, I5000_FBDRST, 0x05); + udelay(1); + pci_write_config8(dev, I5000_FBDRST, 0x04); + udelay(2); + pci_write_config8(dev, I5000_FBDRST, 0x05); + pci_write_config8(dev, I5000_FBDRST, 0x07); + return 0; +} + +static int delay_ns_to_clocks(struct i5000_fbdimm *d, int del) +{ + int div; + + switch (d->setup->ddr_speed) { + case DDR_533MHZ: + div = 375; + break; + + default: + printk(BIOS_ERR, "Invalid clock: %d, using 667MHz\n", + d->setup->ddr_speed); + + case DDR_667MHZ: + div = 300; + break; + } + + return (del * 100) / div; +} + +static int mtb2clks(struct i5000_fbdimm *d, int del) +{ + int val, div; + + switch (d->setup->ddr_speed) { + case DDR_533MHZ: + div = 375; + break; + default: + printk(BIOS_ERR, "Invalid clock: %d, using 667MHz\n", + d->setup->ddr_speed); + + case DDR_667MHZ: + div = 300; + break; + } + + val = (del * 1000 * d->mtb_dividend) / (d->mtb_divisor * div); + if ((val % 10) > 0) + val += 10; + return val / 10; +} + +static int i5000_read_spd_data(struct i5000_fbdimm *d) +{ + struct i5000_fbd_setup *s; + u8 addr, val, org, ftb, cas, t_ras_rc_h, t_rtp, t_wtr; + u8 bb, bl, t_wr, t_rp, t_rcd, t_rc, t_ras, t_aa_min; + u8 cmd2data_addr; + int t_ck_min, dimmsize; + + s = d->setup; + if (spd_read_byte(d, SPD_MEMORY_TYPE, 1, &val)) { + printk(BIOS_DEBUG, "DIMM %d/%d/%d not present\n", + d->branch->num, d->channel->num, d->num); + return 0; // No FBDIMM present + } + + if (val != 0x09) + return 0; // SDRAM type not FBDIMM + + if (spd_read_byte(d, 0x65, 14, d->amb_personality_bytes)) + return 0; + + switch(d->setup->ddr_speed) { + case DDR_533MHZ: + cmd2data_addr = FBDIMM_SPD_CMD2DATA_533; + break; + + case DDR_667MHZ: + cmd2data_addr = FBDIMM_SPD_CMD2DATA_667; + break; + + default: + printk(BIOS_ERR, "Unsupported FBDIMM clock\n"); + return -1; + } + + if (spd_read_byte(d, FBDIMM_SPD_SDRAM_ADDRESSING, 1, &addr) || + spd_read_byte(d, FBDIMM_SPD_MODULE_ORGANIZATION, 1, &org) || + spd_read_byte(d, FBDIMM_SPD_FTB, 1, &ftb) || + spd_read_byte(d, FBDIMM_SPD_MTB_DIVIDEND, 1, &d->mtb_dividend) || + spd_read_byte(d, FBDIMM_SPD_MTB_DIVISOR, 1, &d->mtb_divisor) || + spd_read_byte(d, FBDIMM_SPD_MIN_TCK, 1, &d->t_ck_min) || + spd_read_byte(d, FBDIMM_SPD_T_WR, 1, &t_wr) || + spd_read_byte(d, FBDIMM_SPD_T_RCD, 1, &t_rcd) || + spd_read_byte(d, FBDIMM_SPD_T_RRD, 1, &d->t_rrd) || + spd_read_byte(d, FBDIMM_SPD_T_RP, 1, &t_rp) || + spd_read_byte(d, FBDIMM_SPD_T_RAS_RC_MSB, 1, &t_ras_rc_h) || + spd_read_byte(d, FBDIMM_SPD_T_RAS, 1, (u8 *)&t_ras) || + spd_read_byte(d, FBDIMM_SPD_T_RC, 1, (u8 *)&t_rc) || + spd_read_byte(d, FBDIMM_SPD_T_RFC, 2, (u8 *)&d->t_rfc) || + spd_read_byte(d, FBDIMM_SPD_T_WTR, 1, &t_wtr) || + spd_read_byte(d, FBDIMM_SPD_T_RTP, 1, &t_rtp) || + spd_read_byte(d, FBDIMM_SPD_T_BB, 1, &bb) || + spd_read_byte(d, FBDIMM_SPD_BURST_LENGTHS_SUPPORTED, 1, &bl) || + spd_read_byte(d, FBDIMM_SPD_ODT, 1, &d->odt) || + spd_read_byte(d, FBDIMM_SPD_T_REFI, 1, &d->t_refi) || + spd_read_byte(d, FBDIMM_SPD_CAS_LATENCIES, 1, &cas) || + spd_read_byte(d, FBDIMM_SPD_CMD2DATA_533, 1, &d->cmd2datanxt[DDR_533MHZ]) || + spd_read_byte(d, FBDIMM_SPD_CMD2DATA_667, 1, &d->cmd2datanxt[DDR_667MHZ]) || + spd_read_byte(d, FBDIMM_SPD_CAS_MIN_LATENCY, 1, &t_aa_min)) { + printk(BIOS_ERR, "failed to read data from SPD\n"); + return 0; + } + + + t_ck_min = (d->t_ck_min * 100) / d->mtb_divisor; + if (t_ck_min <= 300) + d->speed = DDR_667MHZ; + else if (t_ck_min <= 375) + d->speed = DDR_533MHZ; + else { + printk(BIOS_ERR, "Unsupported t_ck_min: %d\n", t_ck_min); + return -1; + } + + d->sdram_width = org & 0x07; + if (d->sdram_width > 1) { + printk(BIOS_ERR, "SDRAM width %d not supported\n", d->sdram_width); + return 0; + } + + s->ddr_speed = MIN(s->ddr_speed, d->speed); + + d->banks = 4 << (addr & 0x03); + d->columns = 9 + ((addr >> 2) & 0x03); + d->rows = 12 + ((addr >> 5) & 0x03); + d->ranks = (org >> 3) & 0x03; + d->min_cas_latency = cas & 0x0f; + + d->setup->bl &= bl; + + if (!d->setup->bl) { + printk(BIOS_ERR, "no compatible burst length found\n"); + return -1; + } + + s->t_rc = MAX(s->t_rc, mtb2clks(d, + t_rc | ((t_ras_rc_h & 0xf0) << 4))); + s->t_rrd = MAX(s->t_rrd, mtb2clks(d, d->t_rrd)); + s->t_rfc = MAX(s->t_rfc, mtb2clks(d, d->t_rfc)); + s->t_rcd = MAX(s->t_rcd, mtb2clks(d, t_rcd)); + s->t_cl = MAX(s->t_cl, mtb2clks(d, t_aa_min)); + s->t_wr = MAX(s->t_wr, mtb2clks(d, t_wr)); + s->t_rp = MAX(s->t_rp, mtb2clks(d, t_rp)); + s->t_rtp = MAX(s->t_rtp, mtb2clks(d, t_rtp)); + s->t_wtr = MAX(s->t_wtr, mtb2clks(d, t_wtr)); + s->t_ras = MAX(s->t_ras, mtb2clks(d, + t_ras | ((t_ras_rc_h & 0x0f) << 8))); + s->t_r2r = MAX(s->t_r2r, bb & 3); + s->t_r2w = MAX(s->t_r2w, (bb >> 4) & 3); + s->t_w2r = MAX(s->t_w2r, (bb >> 2) & 3); + + d->ranksize = (1 << (d->banks + d->columns + d->rows + 1)) >> 20; + dimmsize = d->ranksize * d->ranks; + d->branch->totalmem += dimmsize; + s->totalmem += dimmsize; + + d->channel->columns = d->columns; + d->channel->rows = d->rows; + d->channel->ranks = d->ranks; + d->channel->banks = d->banks; + d->channel->width = d->sdram_width; + + printk(BIOS_INFO, "DIMM %d/%d/%d %dMB: %d banks, " + "%d columns, %d rows, %d ranks\n", + d->branch->num, d->channel->num, d->num, dimmsize, + d->banks, d->columns, d->rows, d->ranks); + + d->present = 1; + d->branch->used |= 1; + d->channel->used |= 1; + d->channel->highest_amb = d->num; + return 0; +} + +static int i5000_amb_smbus_write(struct i5000_fbdimm *d, int byte1, int byte2) +{ + u16 status; + device_t dev = PCI_DEV(0, d->branch->num ? 22 : 21, 0); + int cmdreg = d->channel->num ? I5000_SPDCMD1 : I5000_SPDCMD0; + int stsreg = d->channel->num ? I5000_SPD1 : I5000_SPD0; + int timeout = 1000; + + pci_write_config32(dev, cmdreg, 0xb8000000 | ((d->num & 0x03) << 24) | + (byte1 << 16) | (byte2 << 8) | 1); + + while(((status = pci_read_config16(dev, stsreg)) & I5000_SPD_BUSY) && timeout--) + udelay(10); + + if (status & I5000_SPD_WOD && timeout) + return 0; + + printk(BIOS_ERR, "SMBus write failed: %d/%d/%d, byte1 %02x, byte2 %02x status %04x\n", + d->branch->num, d->channel->num, d->num, byte1, byte2, status); + for(;;); + return -1; +} + +static int i5000_amb_smbus_read(struct i5000_fbdimm *d, int byte1, u8 *out) +{ + u16 status; + device_t dev = PCI_DEV(0, d->branch->num ? 22 : 21, 0); + int cmdreg = d->channel->num ? I5000_SPDCMD1 : I5000_SPDCMD0; + int stsreg = d->channel->num ? I5000_SPD1 : I5000_SPD0; + int timeout = 1000; + + pci_write_config32(dev, cmdreg, 0xb8000000 | ((d->num & 0x03) << 24) | + (byte1 << 16)); + + while(((status = pci_read_config16(dev, stsreg)) & I5000_SPD_BUSY) && timeout--) + udelay(10); + + if ((status & I5000_SPD_RDO) && timeout) + *out = status & 0xff; + + if (status & I5000_SPD_SBE || !timeout) { + printk(BIOS_ERR, "SMBus write failed: %d/%d/%d, byte1 %02x status %04x\n", + d->branch->num, d->channel->num, d->num, byte1, status); + for(;;); + return -1; + } + return 0; + +} + +static int i5000_amb_smbus_write_config8(struct i5000_fbdimm *d, + int fn, int reg, u8 val) +{ + if (i5000_amb_smbus_write(d, 0x84, 00) || + i5000_amb_smbus_write(d, 0x04, fn) || + i5000_amb_smbus_write(d, 0x04, (reg >> 8) & 0xff) || + i5000_amb_smbus_write(d, 0x04, reg & 0xff) || + i5000_amb_smbus_write(d, 0x44, val)) { + printk(BIOS_ERR, "AMB SMBUS write failed\n"); + return 1; + } + return 0; +} + +static int i5000_amb_smbus_write_config16(struct i5000_fbdimm *d, + int fn, int reg, u16 val) +{ + if (i5000_amb_smbus_write(d, 0x88, 00) || + i5000_amb_smbus_write(d, 0x08, fn) || + i5000_amb_smbus_write(d, 0x08, (reg >> 8) & 0xff) || + i5000_amb_smbus_write(d, 0x08, reg & 0xff) || + i5000_amb_smbus_write(d, 0x08, (val >> 8) & 0xff) || + i5000_amb_smbus_write(d, 0x48, val & 0xff)) { + printk(BIOS_ERR, "AMB SMBUS write failed\n"); + return 1; + } + return 0; +} + +static int i5000_amb_smbus_write_config32(struct i5000_fbdimm *d, + int fn, int reg, u32 val) +{ + if (i5000_amb_smbus_write(d, 0x8c, 00) || + i5000_amb_smbus_write(d, 0x0c, fn) || + i5000_amb_smbus_write(d, 0x0c, (reg >> 8) & 0xff) || + i5000_amb_smbus_write(d, 0x0c, reg & 0xff) || + i5000_amb_smbus_write(d, 0x0c, (val >> 24) & 0xff) || + i5000_amb_smbus_write(d, 0x0c, (val >> 16) & 0xff) || + i5000_amb_smbus_write(d, 0x0c, (val >> 8) & 0xff) || + i5000_amb_smbus_write(d, 0x4c, val & 0xff)) { + printk(BIOS_ERR, "AMB SMBUS write failed\n"); + return 1; + } + return 0; +} + +static int i5000_amb_smbus_read_config32(struct i5000_fbdimm *d, + int fn, int reg, u32 *val) +{ + u8 byte3, byte2, byte1, byte0; + + if (i5000_amb_smbus_write(d, 0x80, 00) || + i5000_amb_smbus_write(d, 0x00, fn) || + i5000_amb_smbus_write(d, 0x00, (reg >> 8) & 0xff) || + i5000_amb_smbus_write(d, 0x40, reg & 0xff) || + i5000_amb_smbus_read(d, 0x80, &byte3) || + i5000_amb_smbus_read(d, 0x00, &byte3) || + i5000_amb_smbus_read(d, 0x00, &byte2) || + i5000_amb_smbus_read(d, 0x00, &byte1) || + i5000_amb_smbus_read(d, 0x40, &byte0)) { + printk(BIOS_ERR, "AMB SMBUS read failed\n"); + return 1; + } + *val = (byte3 << 24) | (byte2 << 16) | (byte1 << 8) | byte0; + return 0; +} + +static void i5000_amb_write_config8(struct i5000_fbdimm *d, + int fn, int reg, u32 val) +{ + write8(DEFAULT_AMBASE + AMB_ADDR(d->ambase, fn, reg), val); +} + +static void i5000_amb_write_config16(struct i5000_fbdimm *d, + int fn, int reg, u32 val) +{ + write16(DEFAULT_AMBASE + AMB_ADDR(d->ambase, fn, reg), val); +} + +static void i5000_amb_write_config32(struct i5000_fbdimm *d, + int fn, int reg, u32 val) +{ + write32(DEFAULT_AMBASE + AMB_ADDR(d->ambase, fn, reg), val); +} + +static u32 i5000_amb_read_config32(struct i5000_fbdimm *d, + int fn, int reg) +{ + return read32(DEFAULT_AMBASE + AMB_ADDR(d->ambase, fn, reg)); +} + +static int ddr_command(struct i5000_fbdimm *d, int rank, u32 addr, u32 command) +{ + u32 drc, status; + + printk(BIOS_SPEW, "DIMM %d/%d/%d: rank %d: sending command %x (addr %08x)...", + d->branch->num, d->channel->num, d->num, rank, command, addr); + + drc = i5000_amb_read_config32(d, 3, AMB_DRC); + drc &= ~((3 << 9) | (1 << 12)); + drc |= (rank << 9); + + command &= 0x0f; + command |= AMB_DCALCSR_START | (rank << 21); + + printk(BIOS_DEBUG, "%s: AMB_DCALADDR: %08x AMB_DCALCSR: %08x\n", __func__, addr, command); + i5000_amb_write_config32(d, 3, AMB_DRC, drc); + i5000_amb_write_config32(d, 4, AMB_DCALADDR, addr); + i5000_amb_write_config32(d, 4, AMB_DCALCSR, command); + + udelay(1000); + while((status = (i5000_amb_read_config32(d, 4, AMB_DCALCSR))) + & (1 << 31)); + + if (status & (1 << 30)) { + printk(BIOS_SPEW, "failed (status 0x%08x)\n", status); + return -1; + } + + printk(BIOS_SPEW, "done\n"); + return 0; +} + +static int i5000_ddr_calibration(struct i5000_fbdimm *d) +{ + u32 status; + + i5000_amb_write_config32(d, 3, AMB_MBADDR, 0); + i5000_amb_write_config32(d, 3, AMB_MBCSR, 0x80100050); + while((status = i5000_amb_read_config32(d, 3, AMB_MBCSR)) & (1 << 31)); + + i5000_amb_write_config32(d, 3, AMB_MBCSR, 0x80200050); + while((status = i5000_amb_read_config32(d, 3, AMB_MBCSR)) & (1 << 31)); + + if (ddr_command(d, d->ranks == 2 ? 3 : 1, 0, AMB_DCALCSR_OPCODE_RECV_ENABLE_CAL) || + ddr_command(d, d->ranks == 2 ? 3 : 1, 0, AMB_DCALCSR_OPCODE_DQS_DELAY_CAL)) + return -1; + return 0; +} + +static int i5000_ddr_init(struct i5000_fbdimm *d) +{ + + int rank; + u32 val; + u8 odt; + + for(rank = 0; rank < d->ranks; rank++) { + printk(BIOS_DEBUG, "%s: %d/%d/%d rank %d\n", __func__, + d->branch->num, d->channel->num, d->num, rank); + + if (ddr_command(d, 1 << rank, + 0, AMB_DCALCSR_OPCODE_NOP)) + return -1; + + if (ddr_command(d, 1 << rank, + 0x4000000, AMB_DCALCSR_OPCODE_PRECHARGE)) + return -1; + + /* EMRS(2) */ + if (ddr_command(d, 1 << rank, + 2, AMB_DCALCSR_OPCODE_MRS_EMRS)) + return -1; + + /* EMRS(3) */ + if (ddr_command(d, 1 << rank, + 3, AMB_DCALCSR_OPCODE_MRS_EMRS)) + return -1; + + /* EMRS(1) */ + if (ddr_command(d, 1 << rank, + 1, AMB_DCALCSR_OPCODE_MRS_EMRS)) + return -1; + + /* MRS: DLL reset */ + if (ddr_command(d, 1 << rank, + 0x1000000, AMB_DCALCSR_OPCODE_MRS_EMRS)) + return -1; + + udelay(20); + + if (ddr_command(d, 1 << rank, + 0x4000000, AMB_DCALCSR_OPCODE_PRECHARGE)) + return -1; + + if (ddr_command(d, 1 << rank, + 0, AMB_DCALCSR_OPCODE_REFRESH)) + return -1; + + if (ddr_command(d, 1 << rank, 0, + AMB_DCALCSR_OPCODE_REFRESH)) + return -1; + + /* burst length + cas latency */ + val = (((d->setup->bl & BL_BL8) ? 3 : 2) << 16) | + (1 << 19) /* interleaved burst */ | + (d->setup->t_cl << 20) | + (((d->setup->t_wr - 1) & 7) << 25); + + printk(BIOS_DEBUG, "MRS: 0x%08x\n", val); + if (ddr_command(d, 1 << rank, + val, AMB_DCALCSR_OPCODE_MRS_EMRS)) + return -1; + + /* OCD calibration default */ + if (ddr_command(d, 1 << rank, 0x03800001, + AMB_DCALCSR_OPCODE_MRS_EMRS)) + return -1; + + + odt = d->odt; + if (rank) + odt >>= 4; + + val = (d->setup->t_al << 19) | + ((odt & 1) << 18) | + ((odt & 2) << 21) | 1; + + printk(BIOS_DEBUG, "EMRS(1): 0x%08x\n", val); + + /* ODT, OCD exit, additive latency */ + if (ddr_command(d, 1 << rank, val, AMB_DCALCSR_OPCODE_MRS_EMRS)) + return -1; + } + return 0; +} + +static int i5000_amb_preinit(struct i5000_fbdimm *d) +{ + u32 *p32 = (u32 *)d->amb_personality_bytes; + u16 *p16 = (u16 *)d->amb_personality_bytes; + u32 id, drc, fbdsbcfg = 0x0909; + + printk(BIOS_DEBUG, "%s: %d/%d/%d\n", __func__, + d->branch->num, d->channel->num, d->num); + + i5000_amb_smbus_write_config32(d, 1, 0xb0, p32[0]); + i5000_amb_smbus_write_config16(d, 1, 0xb4, p16[2]); + + drc = (d->setup->t_al << 4) | (d->setup->t_cl); + printk(BIOS_SPEW, "DRC: %02X, CMD2DATANXT: %02x\n", drc, + d->cmd2datanxt[d->setup->ddr_speed]); + + switch(d->setup->ddr_speed) { + case DDR_533MHZ: + fbdsbcfg |= (1 << 16); + break; + case DDR_667MHZ: + fbdsbcfg |= (2 << 16); + break; + default: + return -1; + } + + printk(BIOS_DEBUG, "FBDSBCFGNXT: %08x\n", fbdsbcfg); + i5000_amb_smbus_write_config32(d, 1, AMB_FBDSBCFGNXT, fbdsbcfg); + i5000_amb_smbus_write_config32(d, 1, AMB_FBDLOCKTO, 0x1651); + i5000_amb_smbus_write_config8(d, 1, AMB_CMD2DATANXT, + d->cmd2datanxt[d->setup->ddr_speed]); + + i5000_amb_smbus_write_config8(d, 3, AMB_DRC, drc); + + if (!i5000_amb_smbus_read_config32(d, 0, 0, &id)) { + d->vendor = id & 0xffff; + d->device = id >> 16; + } + + pci_mmio_write_config8(d->branch->branchdev, + d->channel->num ? I5000_FBDSBTXCFG1 : I5000_FBDSBTXCFG0, 0x04); + return 0; +} + +static void i5000_fbd_next_state(struct i5000_fbd_branch *b, int state) +{ + int timeout = 10000; + device_t dev = b->branchdev; + + printk(BIOS_DEBUG, " FBD state branch %d: %02x,", b->num, state); + + pci_mmio_write_config8(dev, I5000_FBDHPC, state); + + printk(BIOS_DEBUG, "waiting for new state..."); + + while(pci_mmio_read_config8(dev, I5000_FBDST) != state && timeout--) + udelay(10); + + if (timeout) { + printk(BIOS_DEBUG, "done\n"); + return; + } + + printk(BIOS_ERR, "timeout while entering state %02x on branch %d\n", + state, b->num); +} + +static int i5000_wait_pattern_recognized(struct i5000_fbd_channel *c) +{ + int i = 10; + device_t dev = PCI_ADDR(0, c->branch->num ? 22 : 21, 0, + c->num ? I5000_FBDISTS1 : I5000_FBDISTS0); + + printk(BIOS_DEBUG, " waiting for pattern recognition..."); + while(pci_mmio_read_config16(dev, 0) != 0x1fff && --i > 0) + udelay(5000); + + printk(BIOS_DEBUG, i ? "done\n" : "failed\n"); + printk(BIOS_DEBUG, "%d/%d Round trip latency: %d\n", c->branch->num, c->num, + pci_mmio_read_config8(c->branch->branchdev, c->num ? I5000_FBDLVL1 : I5000_FBDLVL0) & 0x3f); + return !i; +} + +static const char *pattern_names[16] = { + "EI", "EI", "EI", "EI", + "EI", "EI", "EI", "EI", + "TS0", "TS1", "TS2", "TS3", + "RESERVED", "TS2 (merge disabled)", "TS2 (merge enabled)","All ones", +}; + +static int i5000_drive_pattern(struct i5000_fbd_channel *c, int pattern, int wait) +{ + device_t dev = PCI_ADDR(0, c->branch->num ? 22 : 21, 0, + c->num ? I5000_FBDICMD1 : I5000_FBDICMD0); + + printk(BIOS_DEBUG, " %d/%d driving pattern %s to AMB%d (%02x)\n", + c->branch->num, c->num, + pattern_names[(pattern >> 4) & 0xf], pattern & 3, pattern); + pci_mmio_write_config8(dev, 0, pattern); + + if (!wait) + return 0; + + return i5000_wait_pattern_recognized(c); +} + +static int i5000_set_ambpresent(struct i5000_fbd_channel *c) +{ + int i; + device_t branchdev = c->branch->branchdev; + u16 ambpresent = 0x8000; + + for(i = 0; i < I5000_MAX_DIMM_PER_CHANNEL; i++) { + if (c->dimm[i].present) + ambpresent |= (1 << i); + } + + printk(BIOS_DEBUG, "AMBPRESENT: %04x\n", ambpresent); + pci_write_config16(branchdev, + c->num ? + I5000_AMBPRESENT1 : \ + I5000_AMBPRESENT0, ambpresent); + + return 0; +} + + +static int i5000_drive_test_patterns(struct i5000_fbd_channel *c, int highest_amb, int mchpad) +{ + device_t branchdev = c->branch->branchdev; + int off = c->num ? 0x100 : 0; + u32 portctl; + int i, cnt = 1000; + + portctl = pci_mmio_read_config32(branchdev, I5000_FBD0IBPORTCTL + off); + portctl &= ~0x01000020; + if (mchpad) + portctl |= 0x00800000; + else + portctl &= ~0x00800000; + portctl &= ~0x01000020; + pci_mmio_write_config32(branchdev, I5000_FBD0IBPORTCTL + off, portctl); + + /* drive calibration patterns */ + if (i5000_drive_pattern(c, I5000_FBDICMD_TS0 | highest_amb, 1)) + return -1; + + if (i5000_drive_pattern(c, I5000_FBDICMD_TS1 | highest_amb, 1)) + return -1; + + while (!(pci_mmio_read_config32(branchdev, I5000_FBD0IBPORTCTL + off) & 4) && cnt--) + udelay(10); + + if (!cnt) { + printk(BIOS_ERR, "IBIST timeout\n"); + return -1; + } + + if (i5000_drive_pattern(c, I5000_FBDICMD_TS2 | highest_amb, 1)) + return -1; + + for(i = 0; i < highest_amb; i++) { + if ((i5000_drive_pattern(c, I5000_FBDICMD_TS2_NOMERGE | i, 1))) + return -1; + } + + if (i5000_drive_pattern(c, I5000_FBDICMD_TS2 | highest_amb, 1)) + return -1; + + if (i5000_drive_pattern(c, I5000_FBDICMD_TS3 | highest_amb, 1)) + return -1; + + if (i5000_set_ambpresent(c)) + return -1; + return 0; +} + +static int i5000_train_channel_idle(struct i5000_fbd_channel *c) +{ + int i; + u32 fbdsbcfg = 0x0b1b; + + switch(c->setup->ddr_speed) { + case DDR_533MHZ: + fbdsbcfg |= (1 << 16); + break; + case DDR_667MHZ: + fbdsbcfg |= (2 << 16); + break; + default: + return -1; + } + + pci_mmio_write_config8(c->branch->branchdev, + c->num ? I5000_FBDSBTXCFG1 : I5000_FBDSBTXCFG0, 0x05); + + for(i = 0; i < 4; i++) { + if (c->dimm[i].present) + i5000_amb_smbus_write_config32(c->dimm + i, 1, AMB_FBDSBCFGNXT, i ? (fbdsbcfg | 0x1000) : fbdsbcfg); + } + + return i5000_drive_pattern(c, I5000_FBDICMD_IDLE, 1); +} + +static int i5000_drive_test_patterns0(struct i5000_fbd_channel *c) +{ + if (i5000_train_channel_idle(c)) + return -1; + + return i5000_drive_test_patterns(c, c->highest_amb, 0); +} + +static int i5000_drive_test_patterns1(struct i5000_fbd_channel *c) +{ + if (i5000_train_channel_idle(c)) + return -1; + + return i5000_drive_test_patterns(c, c->highest_amb, 1); +} + +static int i5000_setup_channel(struct i5000_fbd_channel *c) +{ + device_t branchdev = c->branch->branchdev; + int off = c->branch->num ? 0x100 : 0; + u32 val; + + pci_mmio_write_config32(branchdev, I5000_FBD0IBTXPAT2EN + off, 0); + pci_mmio_write_config32(branchdev, I5000_FBD0IBTXPAT2EN + off, 0); + pci_mmio_write_config32(branchdev, I5000_FBD0IBTXMSK + off, 0x3ff); + pci_mmio_write_config32(branchdev, I5000_FBD0IBRXMSK + off, 0x1fff); + + pci_mmio_write_config16(branchdev, off + 0x0162, c->used ? 0x20db : 0x18db); + + /* unknown */ + val = pci_mmio_read_config32(branchdev, off + 0x0164); + val &= 0xfffbcffc; + val |= 0x4004; + pci_mmio_write_config32(branchdev, off + 0x164, val); + + pci_mmio_write_config32(branchdev, off + 0x15c, 0xff); + i5000_drive_pattern(c, I5000_FBDICMD_ALL_ONES, 0); + return 0; +} + +static int i5000_link_training0(struct i5000_fbd_branch *b) +{ + device_t branchdev = b->branchdev; + + pci_mmio_write_config8(branchdev, I5000_FBDPLLCTRL, b->used ? 0 : 1); + + if (i5000_for_each_channel(b, i5000_setup_channel)) + return -1; + + if (i5000_for_each_channel(b, i5000_train_channel_idle)) + return -1; + + i5000_fbd_next_state(b, I5000_FBDHPC_STATE_INIT); + + if (i5000_for_each_channel(b, i5000_drive_test_patterns0)) + return -1; + + i5000_fbd_next_state(b, I5000_FBDHPC_STATE_READY); + return 0; +} + +static int i5000_link_training1(struct i5000_fbd_branch *b) +{ + if (i5000_for_each_channel(b, i5000_train_channel_idle)) + return -1; + + i5000_fbd_next_state(b, I5000_FBDHPC_STATE_INIT); + + if (i5000_for_each_channel(b, i5000_drive_test_patterns1)) + return -1; + + i5000_fbd_next_state(b, I5000_FBDHPC_STATE_READY); + return 0; +} + + +static int i5000_amb_check(struct i5000_fbdimm *d) +{ + u32 id = i5000_amb_read_config32(d, 0, 0); + + printk(BIOS_DEBUG, "AMB %d/%d/%d ID: %04x:%04x\n", + d->branch->num, d->channel->num, d->num, + id & 0xffff, id >> 16); + + if ((id & 0xffff) != d->vendor || id >> 16 != d->device) { + printk(BIOS_ERR, "AMB mapping failed\n"); + return -1; + } + return 0; +} + +static int i5000_amb_postinit(struct i5000_fbdimm *d) +{ + u32 *p32 = (u32 *)d->amb_personality_bytes; + u16 *p16 = (u16 *)d->amb_personality_bytes; + + i5000_amb_write_config16(d, 1, 0xb6, p16[3]); + i5000_amb_write_config32(d, 1, 0xb8, p32[2]); + i5000_amb_write_config16(d, 1, 0xbc, p16[6]); + return 0; +} + +static int i5000_amb_dram_timing_init(struct i5000_fbdimm *d) +{ + struct i5000_fbd_setup *s; + u32 val, tref; + int refi; + + s = d->setup; + + printk(BIOS_DEBUG, "DIMM %d/%d/%d config:\n", + d->branch->num, d->channel->num, d->num); + + val = 0x44; + printk(BIOS_DEBUG, "\tDDR2ODTC: 0x%02x\n", val); + i5000_amb_write_config8(d, 4, AMB_DDR2ODTC, val); + + val = (0x0c << 24) | /* CLK control */ + (1 << 18) | /* ODTZ enabled */ + (((d->setup->bl & BL_BL8) ? 1 : 0) << 8) | /* 8 byte burst length supported */ + ((d->setup->t_al & 0x0f) << 4) | /* additive latency */ + (d->setup->t_cl & 0x0f); /* CAS latency */ + + if (d->ranks > 1) { + val |= (0x03 << 9); + } else { + val |= (0x01 << 9); + } + + printk(BIOS_DEBUG, "AMB_DRC: %08x\n", val); + i5000_amb_write_config32(d, 3, AMB_DRC, val); + + val = (d->sdram_width << 30) | + ((d->ranks == 2 ? 1 : 0) << 29) | + ((d->banks == 8 ? 1 : 0) << 28) | + ((d->rows - 13) << 26) | + ((d->columns - 10) << 24) | + (1 << 16) | /* Auto refresh exit */ + (0x27 << 8) | /* t_xsnr */ + (d->setup->t_rp << 4) | + (((d->t_ck_min * d->mtb_dividend) / d->mtb_divisor) & 0x0f); + + printk(BIOS_DEBUG, "\tAMB_DSREFTC: %08x\n", val); + i5000_amb_write_config32(d, 3, AMB_DSREFTC, val); + + tref = 15; + + switch(d->t_refi & 0x0f) { + case 0: + refi = 15625; + break; + case 1: + refi = 3900; + tref = 3; + break; + case 2: + refi = 7800; + tref = 7; + break; + case 3: + refi = 31250; + break; + case 4: + refi = 62500; + break; + case 5: + refi = 125000; + break; + default: + printk(BIOS_ERR, "unsupported t_refi value: %d, using 7.8us\n", + d->t_refi & 0x0f); + refi = 7800; + break; + } + + s->t_ref = tref; + val = delay_ns_to_clocks(d, refi) | (s->t_rfc << 16); + + printk(BIOS_DEBUG, "\tAMB_DAREFTC: %08x\n", val); + i5000_amb_write_config32(d, 3, AMB_DAREFTC, val); + + u8 t_r2w = ((s->bl & BL_BL8) ? 4 : 2) + + (((d->t_ck_min * d->mtb_dividend) / d->mtb_divisor)); + u8 t_w2r = (s->t_cl - 1) + ((s->bl & BL_BL8) ? 4 : 2) + s->t_wtr; + + val = ((6 - s->t_rp) << 8) | ((6 - s->t_rcd) << 10) | + ((26 - s->t_rc) << 12) | ((9 - s->t_wr) << 16) | + ((12 - t_w2r) << 20) | ((10 - t_r2w) << 24) | + ((s->t_rtp - 2) << 27); + + switch(s->t_ras) { + case 15: + val |= (1 << 29); + break; + case 12: + val |= (2 << 29); + break; + default: + break; + } + + printk(BIOS_DEBUG, "\tAMB_DRT: %08x\n", val); + i5000_amb_write_config32(d, 3, AMB_DRT, val); + return 0; +} + +static int i5000_do_amb_membist_start(struct i5000_fbdimm *d, int rank, int pattern) +{ + printk(BIOS_DEBUG, "DIMM %d/%d/%d rank %d pattern %d\n", + d->branch->num, d->channel->num, d->num, rank, pattern); + + i5000_amb_write_config32(d, 3, AMB_DAREFTC, + i5000_amb_read_config32(d, 3, AMB_DAREFTC) | 0x8000); + + i5000_amb_write_config32(d, 3, AMB_MBLFSRSED, 0x12345678); + i5000_amb_write_config32(d, 3, AMB_MBADDR, 0); + i5000_amb_write_config32(d, 3, AMB_MBCSR, 0x800000f0 | (rank << 20) | ((pattern & 3) << 8)); + return 0; +} + +static int i5000_do_amb_membist_status(struct i5000_fbdimm *d, int rank) +{ + int cnt = 1000; + u32 res; + + while((res = i5000_amb_read_config32(d, 3, AMB_MBCSR)) & (1 << 31) && cnt--) + udelay(1000); + + if (cnt && !(res & (1 << 30))) + return 0; + + printk(BIOS_ERR, "DIMM %d/%d/%d rank %d failed membist check\n", + d->branch->num, d->channel->num, d->num, rank); + return -1; +} + +static int i5000_amb_membist_zero1_start(struct i5000_fbdimm *d) +{ + if (i5000_do_amb_membist_start(d, 1, 0)) + return -1; + return 0; +} + +static int i5000_amb_membist_zero2_start(struct i5000_fbdimm *d) +{ + + if (d->ranks < 2) + return 0; + if (i5000_do_amb_membist_start(d, 2, 0)) + return -1; + return 0; +} + +static int i5000_amb_membist_status1(struct i5000_fbdimm *d) +{ + if (i5000_do_amb_membist_status(d, 1)) + return -1; + return 0; +} + +static int i5000_amb_membist_status2(struct i5000_fbdimm *d) +{ + if (d->ranks < 2) + return 0; + + if (i5000_do_amb_membist_status(d, 2)) + return -1; + return 0; +} + +static int i5000_amb_membist_end(struct i5000_fbdimm *d) +{ + printk(BIOS_DEBUG, "AMB_DRC MEMBIST: %08x\n", i5000_amb_read_config32(d, 3, AMB_DRC)); + return 0; +} + +static int i5000_membist(struct i5000_fbd_setup *setup) +{ + return i5000_for_each_dimm_present(setup, i5000_amb_membist_zero1_start) || + i5000_for_each_dimm_present(setup, i5000_amb_membist_status1) || + i5000_for_each_dimm_present(setup, i5000_amb_membist_zero2_start) || + i5000_for_each_dimm_present(setup, i5000_amb_membist_status2) || + i5000_for_each_dimm_present(setup, i5000_amb_membist_end); +} + +static int i5000_enable_mc_autorefresh(struct i5000_fbdimm *d) +{ + u32 tmp = i5000_amb_read_config32(d, 3, AMB_DSREFTC); + tmp &= ~(1 << 16); + printk(BIOS_DEBUG, "new AMB_DSREFTC: 0x%08x\n", tmp); + i5000_amb_write_config32(d, 3, AMB_DSREFTC, tmp); + return 0; +} + +static int i5000_amb_clear_error_status(struct i5000_fbdimm *d) +{ + i5000_amb_write_config32(d, 1, AMB_FERR, 9); + i5000_amb_write_config32(d, 1, AMB_NERR, 9); + i5000_amb_write_config32(d, 1, AMB_EMASK, 0xf2); + i5000_amb_write_config8(d, 3, 0x80, 0xcf); + i5000_amb_write_config8(d, 3, 0x81, 0xd3); + i5000_amb_write_config8(d, 3, 0x82, 0xf8); + return 0; +} + +static void i5000_program_mtr(struct i5000_fbd_channel *c, int mtr) +{ + u32 val; + + if (c->dimm[0].present || c->dimm[1].present) { + val = (((c->columns - 10) & 3) | + (((c->rows - 13) & 3) << 2) | + (((c->ranks == 2) ? 1 : 0) << 4) | + (((c->banks == 8) ? 1 : 0) << 5) | + ((c->width ? 1 : 0) << 6) | + (1 << 7) | /* Electrical Throttling enabled */ + (1 << 8)); /* DIMM present and compatible */ + printk(BIOS_DEBUG, "MTR0: %04x\n", val); + pci_mmio_write_config16(c->branch->branchdev, mtr, val); + } + + if (c->dimm[2].present || c->dimm[3].present) { + val = (((c->columns - 10) & 3) | + (((c->rows - 13) & 3) << 4) | + ((c->ranks ? 1 : 0) << 4) | + (((c->banks == 8) ? 1 : 0) << 5) | + ((c->width ? 1 : 0) << 6) | + (1 << 7) | /* Electrical Throttling enabled */ + (1 << 8)); /* DIMM present and compatible */ + printk(BIOS_DEBUG, "MTR1: %04x\n", val); + pci_mmio_write_config16(c->branch->branchdev, mtr+2, val); + } +} + +static int get_dmir(u8 *rankmap, int *_set, int limit) +{ + int i, dmir = 0, set = 0; + + for(i = 7; set < limit && i >= 0; i--) { + if (!(*rankmap & (1 << i))) + continue; + + *rankmap &= ~(1 << i); + + switch(limit) { + case 1: + dmir |= (i | + (i << 3) | + (i << 6) | + (i << 9)); + break; + case 2: + dmir |= (i << (set * 3)) | + (i << (6 + set * 3)); + break; + case 4: + dmir |= (i << (set * 3)); + break; + + default: + break; + } + set++; + } + *_set = set; + return dmir; +} + +static int i5000_setup_dmir(struct i5000_fbd_branch *b) +{ + struct i5000_fbdimm *d; + device_t dev = b->branchdev; + u8 rankmap = 0, dmir = 0; + u32 dmirval = 0; + int i, set, rankoffset = 0, ranksize = 0, ranks = 0; + + if (!b->used) + return 0; + + for(i = 0; i < I5000_MAX_DIMM_PER_CHANNEL; i++) { + rankmap >>= 2; + d = b->channel[0].dimm + i; + + if (!d->present) + continue; + + if (d->ranks == 2) { + rankmap |= 0xc0; + ranks += 2; + } else { + rankmap |= 0x40; + ranks++; + } + } + + printk(BIOS_DEBUG, "total ranks: %d, rankmap: %02x\n", ranks, rankmap); + + dmir = I5000_DMIR0; + + ranksize = b->channel[0].dimm[0].ranksize << 8; + + if (!b->setup->single_channel) + ranksize <<= 1; + + while(ranks) { + + if (ranks >= 4) + dmirval = get_dmir(&rankmap, &set, 4); + else if (ranks >= 2) + dmirval = get_dmir(&rankmap, &set, 2); + else + dmirval = get_dmir(&rankmap, &set, 1); + + ranks -= set; + + dmirval |= rankoffset + (set * ranksize); + + rankoffset += (set * ranksize); + + printk(BIOS_DEBUG, "DMIR%d: %08x\n", (dmir - I5000_DMIR0) >> 2, + dmirval); + pci_mmio_write_config32(dev, dmir, dmirval); + dmir += 4; + } + + for(; dmir <= I5000_DMIR4; dmir += 4) { + printk(BIOS_DEBUG, "DMIR%d: %08x\n", (dmir - I5000_DMIR0) >> 2, + dmirval); + pci_mmio_write_config32(dev, dmir, dmirval); + } + return rankoffset; +} + +static void i5000_setup_interleave(struct i5000_fbd_setup *setup) +{ + device_t dev16 = PCI_ADDR(0, 16, 1, 0); + u32 mir0, mir1, mir2, size0, size1, minsize, tmp; + + size0 = i5000_setup_dmir(&setup->branch[1]) >> 12; + size1 = i5000_setup_dmir(&setup->branch[0]) >> 12; + + minsize = MIN(size0, size1); + + if (size0 > size1) { + tmp = size1; + size1 = size0; + size0 = tmp; + } + + if (size0 == size1) { + mir0 = (size0 << 1) | 3; + mir1 = (size0 << 1); + mir2 = (size0 << 1); + } else if (!size0) { + mir0 = size1 | 1; + mir1 = size1; + mir2 = size1; + } else { + mir0 = (size0 << 1) | 3; + mir1 = (size1 + size0) | 1; + mir2 = size1 + size0; + } + + printk(BIOS_DEBUG, "MIR0: %04x\n", mir0); + printk(BIOS_DEBUG, "MIR1: %04x\n", mir1);; + printk(BIOS_DEBUG, "MIR2: %04x\n", mir2);; + + pci_mmio_write_config16(dev16, I5000_MIR0, mir0); + pci_mmio_write_config16(dev16, I5000_MIR1, mir1); + pci_mmio_write_config16(dev16, I5000_MIR2, mir2); +} + +static int i5000_dram_timing_init(struct i5000_fbd_setup *setup) +{ + device_t dev16 = PCI_ADDR(0, 16, 1, 0); + u32 tolm, drta, drtb, mc, mca; + int t_wrc, bl2; + + bl2 = (setup->bl & BL_BL8) ? 4 :2; + t_wrc = setup->t_rcd + (setup->t_cl - 1) + bl2 + + setup->t_wr + setup->t_rp; + + drta = (setup->t_ref & 0x0f) | + ((setup->t_rrd & 0x0f) << 4) | + ((setup->t_rfc & 0xff) << 8) | + ((setup->t_rc & 0x3f) << 16) | + ((t_wrc & 0x3f) << 22) | + (setup->t_al & 0x07) << 28; + + drtb = (bl2) | + (((1 + bl2 + setup->t_r2r) & 0x0f) << 4) | + (((setup->t_cl - 1 + bl2 + setup->t_wtr) & 0x0f) << 8) | + (((2 + bl2 + setup->t_r2w) & 0x0f) << 12) | + (((bl2 + setup->t_w2rdr) & 0x07) << 16); + + mc = (1 << 30) | /* enable retry */ + (3 << 25) | /* bad RAM threshold */ + (1 << 21) | /* INITDONE */ + (1 << 20) | /* FSB enable */ + /* Electrical throttling: 20 clocks */ + ((setup->ddr_speed == DDR_667MHZ ? 1 : 0) << 18) | + (1 << 8) | /* enhanced scrub mode */ + (1 << 7) | /* enable patrol scrub */ + (1 << 6) | /* enable demand scrubing */ + (1 << 5); /* enable northbound error detection */ + + printk(BIOS_DEBUG, "DRTA: 0x%08x DRTB: 0x%08x MC: 0x%08x\n", drta, drtb, mc); + pci_mmio_write_config32(dev16, I5000_DRTA, drta); + pci_mmio_write_config32(dev16, I5000_DRTB, drtb); + pci_mmio_write_config32(dev16, I5000_MC, mc); + + mca = pci_mmio_read_config32(dev16, I5000_MCA); + + mca |= (7 << 28); + if (setup->single_channel) + mca |= (1 << 14); + else + mca &= ~(1 << 14); + printk(BIOS_DEBUG, "MCA: 0x%08x\n", mca); + pci_mmio_write_config32(dev16, I5000_MCA, mca); + + pci_mmio_write_config32(dev16, I5000_ERRPERR, 0xffffffff); + + i5000_program_mtr(&setup->branch[0].channel[0], I5000_MTR0); + i5000_program_mtr(&setup->branch[0].channel[1], I5000_MTR1); + i5000_program_mtr(&setup->branch[1].channel[0], I5000_MTR0); + i5000_program_mtr(&setup->branch[1].channel[1], I5000_MTR1); + + i5000_setup_interleave(setup); + + if ((tolm = MIN(setup->totalmem, 0xe00)) > 0xe00) + tolm = 0xe00; + + tolm <<= 4; + printk(BIOS_DEBUG, "TOLM: 0x%04x\n", tolm); + pci_mmio_write_config16(dev16, I5000_TOLM, tolm); + return 0; +} + +static void i5000_init_setup(struct i5000_fbd_setup *setup) +{ + int branch, channel, dimm, i = 0; + struct i5000_fbdimm *d; + struct i5000_fbd_channel *c; + struct i5000_fbd_branch *b; + + setup->bl = 3; + /* default to highest memory frequency. If a module doesn't + support it, it will decrease this setting in spd_read */ + setup->ddr_speed = DDR_667MHZ; + + for(branch = 0; branch < I5000_MAX_BRANCH; branch++) { + b = setup->branch + branch; + b->branchdev = PCI_ADDR(0, branch ? 22 : 21, 0, 0); + b->setup = setup; + b->num = branch; + + for(channel = 0; channel < I5000_MAX_CHANNEL; channel++) { + c = b->channel + channel; + c->branch = b; + c->setup = setup; + c->num = channel; + + for(dimm = 0; dimm < I5000_MAX_DIMM_PER_CHANNEL; dimm++) { + d = c->dimm + dimm; + setup->dimms[i++] = d; + d->channel = c; + d->branch = b; + d->setup = setup; + d->num = dimm; + d->ambase = (b->num << 16) | (c->num << 15) | (dimm << 11); + } + } + } +} + +static void i5000_reserved_register_init(struct i5000_fbd_setup *setup) +{ + /* register write captured from vendor BIOS, but undocument by Intel */ + pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), I5000_PROCENABLE, 0x487f7c); + + pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), 0xf4, 0x1588106); + pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), 0xfc, 0x80); + pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), 0x5c, 0x08); + pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), 0x70, 0xfe2c08d); + pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), 0x78, 0xfe2c08d); + + pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), 0x140, 0x18000000); + pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), 0x440, 0x18000000); + pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x18c, 0x18000000); + pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), 0x180, 0x18000000); + pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x180, 0x87ffffff); + + pci_mmio_write_config32(PCI_ADDR(0, 0, 0, 0), 0x200, 0x18000000); + pci_mmio_write_config32(PCI_ADDR(0, 4, 0, 0), 0x200, 0x18000000); + pci_mmio_write_config32(PCI_ADDR(0, 0, 0, 0), 0x208, 0x18000000); + pci_mmio_write_config32(PCI_ADDR(0, 4, 0, 0), 0x208, 0x18000000); + + pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x184, 0x01249249); + pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x154, 0x00000000); + pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x158, 0x02492492); + pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x15c, 0x00000000); + pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x160, 0x00000000); + + pci_mmio_write_config16(PCI_ADDR(0, 19, 0, 0), 0x0090, 0x00000007); + pci_mmio_write_config16(PCI_ADDR(0, 19, 0, 0), 0x0092, 0x0000000f); + + pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x0154, 0x10); + pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x0454, 0x10); + + pci_mmio_write_config32(PCI_ADDR(0, 19, 0, 0), 0x007C, 0x00000001); + pci_mmio_write_config32(PCI_ADDR(0, 19, 0, 0), 0x007C, 0x00000000); + pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0108, 0x000003F0); + pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x010C, 0x00000042); + pci_mmio_write_config16(PCI_ADDR(0, 17, 0, 0), 0x0112, 0x0000); + pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0114, 0x00A0494C); + pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0118, 0x0002134C); + pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x013C, 0x0C008000); + pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0140, 0x0C008000); + pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0144, 0x00008000); + pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0148, 0x00008000); + pci_mmio_write_config32(PCI_ADDR(0, 19, 0, 0), 0x007C, 0x00000002); + pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), 0x01F4, 0x00000800); + + if (setup->branch[0].channel[0].used) + pci_mmio_write_config32(PCI_ADDR(0, 21, 0, 0), 0x010C, 0x004C0C10); + + if (setup->branch[0].channel[1].used) + pci_mmio_write_config32(PCI_ADDR(0, 21, 0, 0), 0x020C, 0x004C0C10); + + if (setup->branch[1].channel[0].used) + pci_mmio_write_config32(PCI_ADDR(0, 22, 0, 0), 0x010C, 0x004C0C10); + + if (setup->branch[1].channel[1].used) + pci_mmio_write_config32(PCI_ADDR(0, 22, 0, 0), 0x020C, 0x004C0C10); +} +static void i5000_dump_error_registers(void) +{ + device_t dev = PCI_ADDR(0, 16, 1, 0); + + printk(BIOS_ERR, "Dump of FBD error registers:\n" + "FERR_FAT_FBD: 0x%08x NERR_FAT_FBD: 0x%08x\n" + "FERR_NF_FBD: 0x%08x NERR_NF_FBD: 0x%08x\n" + "EMASK_FBD: 0x%08x\n" + "ERR0_FBD: 0x%08x\n" + "ERR1_FBD: 0x%08x\n" + "ERR2_FBD: 0x%08x\n" + "MC_ERR_FBD: 0x%08x\n", + pci_mmio_read_config32(dev, I5000_FERR_FAT_FBD), + pci_mmio_read_config32(dev, I5000_NERR_FAT_FBD), + pci_mmio_read_config32(dev, I5000_FERR_NF_FBD), + pci_mmio_read_config32(dev, I5000_NERR_NF_FBD), + pci_mmio_read_config32(dev, I5000_EMASK_FBD), + pci_mmio_read_config32(dev, I5000_ERR0_FBD), + pci_mmio_read_config32(dev, I5000_ERR1_FBD), + pci_mmio_read_config32(dev, I5000_ERR2_FBD), + pci_mmio_read_config32(dev, I5000_MCERR_FBD)); + + printk(BIOS_ERR, "Non recoverable error registers:\n" + "NRECMEMA: 0x%08x NRECMEMB: 0x%08x\n" + "NRECFGLOG: 0x%08x\n", + pci_mmio_read_config32(dev, I5000_NRECMEMA), + pci_mmio_read_config32(dev, I5000_NRECMEMB), + pci_mmio_read_config32(dev, I5000_NRECFGLOG)); + + printk(BIOS_ERR, "Packet data:\n" + "NRECFBDA: 0x%08x\n" + "NRECFBDB: 0x%08x\n" + "NRECFBDC: 0x%08x\n" + "NRECFBDD: 0x%08x\n" + "NRECFBDE: 0x%08x\n", + pci_mmio_read_config32(dev, I5000_NRECFBDA), + pci_mmio_read_config32(dev, I5000_NRECFBDB), + pci_mmio_read_config32(dev, I5000_NRECFBDC), + pci_mmio_read_config32(dev, I5000_NRECFBDD), + pci_mmio_read_config32(dev, I5000_NRECFBDE)); + + printk(BIOS_ERR, "recoverable error registers:\n" + "RECMEMA: 0x%08x RECMEMB: 0x%08x\n" + "RECFGLOG: 0x%08x\n", + pci_mmio_read_config32(dev, I5000_RECMEMA), + pci_mmio_read_config32(dev, I5000_RECMEMB), + pci_mmio_read_config32(dev, I5000_RECFGLOG)); + + printk(BIOS_ERR, "Packet data:\n" + "RECFBDA: 0x%08x\n" + "RECFBDB: 0x%08x\n" + "RECFBDC: 0x%08x\n" + "RECFBDD: 0x%08x\n" + "RECFBDE: 0x%08x\n", + pci_mmio_read_config32(dev, I5000_RECFBDA), + pci_mmio_read_config32(dev, I5000_RECFBDB), + pci_mmio_read_config32(dev, I5000_RECFBDC), + pci_mmio_read_config32(dev, I5000_RECFBDD), + pci_mmio_read_config32(dev, I5000_RECFBDE)); + +} + +static void i5000_try_restart(const char *msg) +{ + printk(BIOS_INFO, msg); + i5000_dump_error_registers(); +// outb(0x06, 0xcf9); + for(;;) asm volatile("hlt"); +} + +static void i5000_pam_setup(void) +{ + pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x59, 0x30); + pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5a, 0x33); + pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5b, 0x33); + pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5c, 0x33); + pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5d, 0x33); + pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5e, 0x33); + pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5f, 0x33); +} + +static int i5000_setup_clocking(struct i5000_fbd_setup *setup) +{ + int fbd, fsb, ddrfrq, ddrfrqnow; + msr_t msr; + device_t dev = PCI_ADDR(0, 16, 1, 0); + + switch(setup->ddr_speed) { + case DDR_667MHZ: + fbd = 667; + break; + case DDR_533MHZ: + fbd = 533; + break; + default: + printk(BIOS_ERR, "%s: unsupported FBD speed\n", __func__); + return 1; + } + + /* mainboard specific callback */ + if (mainboard_set_fbd_clock(fbd)) { + printk(BIOS_ERR, "%s: failed to set FBD speed\n", __func__); + return 1; + } + + msr = rdmsr(0xcd); + + switch(msr.lo & 7) { + case 1: + fsb = 533; + break; + case 4: + fsb = 667; + break; + default: + printk(BIOS_ERR, "%s: unsupported FSB speed: %d\n", __func__, msr.lo & 7); + return 1; + } + + + ddrfrq = pci_mmio_read_config8(PCI_ADDR(0, 16, 1, 0), 0x56); + ddrfrqnow = ddrfrq; + ddrfrq &= ~0x3; + + if (fsb < fbd) + ddrfrq |= 2; + else if (fsb > fbd) + ddrfrq |= 3; + + switch((ddrfrq >> 4) & 3) { + case 0: /* 1:1 mapping */ + pci_mmio_write_config32(dev, I5000_FBDTOHOSTGRCFG0, 0xffffffff); + pci_mmio_write_config32(dev, I5000_FBDTOHOSTGRCFG1, 0x00000000); + pci_mmio_write_config32(dev, I5000_HOSTTOFBDGRCFG, 0xffffffff); + pci_mmio_write_config8(dev, I5000_GRFBDLVLDCFG, 0x00); + pci_mmio_write_config8(dev, I5000_GRHOSTFULLCFG, 0x00); + pci_mmio_write_config8(dev, I5000_GRBUBBLECFG, 0x00); + pci_mmio_write_config8(dev, I5000_GRFBDTOHOSTDBLCFG, 0x00); + break; + case 2: /* 4:5 mapping */ + pci_mmio_write_config32(dev, I5000_FBDTOHOSTGRCFG0, 0x00002323); + pci_mmio_write_config32(dev, I5000_FBDTOHOSTGRCFG1, 0x00000400); + pci_mmio_write_config32(dev, I5000_HOSTTOFBDGRCFG, 0x23023); + pci_mmio_write_config8(dev, I5000_GRFBDLVLDCFG, 0x04); + pci_mmio_write_config8(dev, I5000_GRHOSTFULLCFG, 0x08); + pci_mmio_write_config8(dev, I5000_GRBUBBLECFG, 0x00); + pci_mmio_write_config8(dev, I5000_GRFBDTOHOSTDBLCFG, 0x04); + break; + case 3: + /* 5:4 mapping */ + pci_mmio_write_config32(dev, I5000_FBDTOHOSTGRCFG0, 0x00023230); + pci_mmio_write_config32(dev, I5000_FBDTOHOSTGRCFG1, 0x00000000); + pci_mmio_write_config32(dev, I5000_HOSTTOFBDGRCFG, 0x4323); + pci_mmio_write_config8(dev, I5000_GRFBDLVLDCFG, 0x00); + pci_mmio_write_config8(dev, I5000_GRHOSTFULLCFG, 0x02); + pci_mmio_write_config8(dev, I5000_GRBUBBLECFG, 0x10); + pci_mmio_write_config8(dev, I5000_GRFBDTOHOSTDBLCFG, 0x00); + break; + default: + printk(BIOS_DEBUG, "invalid DDRFRQ: %02x\n", ddrfrq); + return -1; + } + + if (ddrfrq != ddrfrqnow) { + printk(BIOS_DEBUG, "old DDRFRQ: 0x%02x new DDRFRQ: 0x%02x\n", + ddrfrqnow, ddrfrq); + pci_mmio_write_config8(PCI_ADDR(0, 16, 1, 0), 0x56, ddrfrq); + /* FSB:FBD mapping changed, needs hard reset */ + outb(0x06, 0xcf9); + for(;;) asm volatile("hlt"); + } + return 0; +} + +void i5000_fbdimm_init(void) +{ + struct i5000_fbd_setup setup; + u32 mca, mc; + + memset(&setup, 0, sizeof(setup)); + + pci_mmio_write_config16(PCI_ADDR(0, 0, 0, 0), 0x4, 0x144); + + i5000_init_setup(&setup); + + pci_write_config32(PCI_DEV(0, 16, 0), 0xf0, + pci_mmio_read_config32(PCI_ADDR(0, 16, 0, 0), 0xf0) | 0x8000); + + i5000_clear_fbd_errors(); + + printk(BIOS_INFO, "detecting memory modules\n"); + if (i5000_for_each_dimm(&setup, i5000_read_spd_data)) { + printk(BIOS_ERR, "%s: failed to read SPD data\n", __func__); + return; + } + + if (i5000_setup_clocking(&setup)) { + printk(BIOS_ERR, "%s: failed to set FBD clock\n", __func__); + return; + } + + /* posted CAS requires t_AL = t_RCD - 1 */ + setup.t_al = setup.t_rcd - 1; + + printk(BIOS_DEBUG, "global timing parameters:\n" + "CL: %d RAS: %d WRC: %d RC: %d RFC: %d RRD: %d REF: %d W2RDR: %d\n" + "R2W: %d W2R: %d R2R: %d W2W: %d WTR: %d RCD: %d RP %d WR: %d RTP: %d AL: %d\n", + setup.t_cl, setup.t_ras, setup.t_wrc, setup.t_rc, setup.t_rfc, + setup.t_rrd, setup.t_ref, setup.t_w2rdr, setup.t_r2w, setup.t_w2r, + setup.t_r2r, setup.t_w2w, setup.t_wtr, setup.t_rcd, + setup.t_rp, setup.t_wr, setup.t_rtp, setup.t_al); + + setup.single_channel = (!(setup.branch[0].channel[1].used || + setup.branch[1].channel[0].used || + setup.branch[1].channel[1].used)); + + pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), 0x019C, 0x8010c); + pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), 0x01F4, 0); + + /* enable or disable single channel mode */ + mca = pci_mmio_read_config32(PCI_ADDR(0, 16, 1, 0), I5000_MCA); + if (setup.single_channel) + mca |= (1 << 14); + else + mca &= ~(1 << 14); + pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), I5000_MCA, mca); + + /* + * i5000 supports burst length 8 only in single channel mode + * so strip BL_BL8 if we're operating in multichannel mode + */ + + if (!setup.single_channel) + setup.bl &= ~BL_BL8; + + if (!setup.bl) + die("No supported burst length found\n"); + + mc = pci_mmio_read_config32(PCI_ADDR(0, 16, 1, 0), I5000_MC); + /* disable error checking for training */ + pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), I5000_MC, mc & ~0x20); + + printk(BIOS_INFO, "performing fbd link initialization..."); + if (i5000_for_each_branch(&setup, i5000_branch_reset) || + i5000_for_each_dimm_present(&setup, i5000_amb_preinit) || + i5000_for_each_branch(&setup, i5000_link_training0) || + i5000_for_each_dimm_present(&setup, i5000_amb_check) || + i5000_for_each_dimm_present(&setup, i5000_amb_postinit) || + i5000_for_each_branch(&setup, i5000_link_training1)) { + i5000_try_restart("failed\n"); + } + printk(BIOS_INFO, "done\n"); + printk(BIOS_INFO, "initializing memory..."); + + if (i5000_for_each_dimm_present(&setup, i5000_ddr_init) || + i5000_for_each_dimm_present(&setup, i5000_amb_dram_timing_init) || + i5000_for_each_dimm_present(&setup, i5000_ddr_calibration)) { + i5000_try_restart("failed\n"); + } + printk(BIOS_INFO,"done\n"); + printk(BIOS_INFO, "clearing memory..."); + + if (i5000_membist(&setup)) + i5000_try_restart("failed\n"); + else + printk(BIOS_INFO, "done\n"); + + if (i5000_for_each_dimm_present(&setup, i5000_enable_mc_autorefresh)) + i5000_try_restart("failed to enable auto refresh\n"); + + i5000_fbd_next_state(&setup.branch[0], I5000_FBDHPC_STATE_INIT); + i5000_fbd_next_state(&setup.branch[1], I5000_FBDHPC_STATE_INIT); + + if (i5000_for_each_branch(&setup, i5000_link_training0)) + i5000_try_restart("Channel training failed\n"); + + if (setup.branch[0].used) + i5000_fbd_next_state(&setup.branch[0], I5000_FBDHPC_STATE_READY); + + if (setup.branch[1].used) + i5000_fbd_next_state(&setup.branch[1], I5000_FBDHPC_STATE_READY); + + i5000_clear_fbd_errors(); + + /* enable error checking */ + pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), I5000_MC, mc | 0x20); + + i5000_dram_timing_init(&setup); + + i5000_reserved_register_init(&setup); + + i5000_pam_setup(); + + if (i5000_for_each_dimm_present(&setup, i5000_amb_clear_error_status)) + i5000_try_restart("failed to clear error status\n"); + + if (setup.branch[0].used) + i5000_fbd_next_state(&setup.branch[0], I5000_FBDHPC_STATE_ACTIVE); + + if (setup.branch[1].used) + i5000_fbd_next_state(&setup.branch[1], I5000_FBDHPC_STATE_ACTIVE); + +#if CONFIG_NORTHBRIDGE_INTEL_I5000_RAM_CHECK + if (ram_check_nodie(0x000000, 0x0a0000) || + ram_check_nodie(0x100000, MIN(setup.totalmem * 1048576, 0xe0000000))) { + i5000_try_restart("RAM verification failed"); + + } +#endif + + printk(BIOS_INFO, "Memory initialization finished\n"); +} diff --git a/src/northbridge/intel/i5000/raminit.h b/src/northbridge/intel/i5000/raminit.h new file mode 100644 index 0000000..d3fa16a --- /dev/null +++ b/src/northbridge/intel/i5000/raminit.h @@ -0,0 +1,337 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef NORTHBRIDGE_I5000_RAMINIT_H +#define NORTHBRIDGE_I5000_RAMINIT_H + +#include <types.h> +#include <arch/io.h> +#include <arch/romcc_io.h> + +#define I5000_MAX_BRANCH 2 +#define I5000_MAX_CHANNEL 2 +#define I5000_MAX_DIMM_PER_CHANNEL 4 +#define I5000_MAX_DIMMS (I5000_MAX_BRANCH * I5000_MAX_CHANNEL * I5000_MAX_DIMM_PER_CHANNEL) + +#define I5000_FBDRST 0x53 + +#define I5000_SPD_BUSY (1 << 12) +#define I5000_SPD_SBE (1 << 13) +#define I5000_SPD_WOD (1 << 14) +#define I5000_SPD_RDO (1 << 15) + +#define I5000_SPD0 0x74 +#define I5000_SPD1 0x76 + +#define I5000_SPDCMD0 0x78 +#define I5000_SPDCMD1 0x7c + +#define I5000_FBDHPC 0x4f +#define I5000_FBDST 0x4b + +#define I5000_FBDHPC_STATE_RESET 0x00 +#define I5000_FBDHPC_STATE_INIT 0x10 +#define I5000_FBDHPC_STATE_READY 0x20 +#define I5000_FBDHPC_STATE_ACTIVE 0x30 + +#define I5000_FBDISTS0 0x58 +#define I5000_FBDISTS1 0x5a + +#define I5000_FBDLVL0 0x44 +#define I5000_FBDLVL1 0x45 + +#define I5000_FBDICMD0 0x46 +#define I5000_FBDICMD1 0x47 + +#define I5000_FBDICMD_IDLE 0x00 +#define I5000_FBDICMD_TS0 0x80 +#define I5000_FBDICMD_TS1 0x90 +#define I5000_FBDICMD_TS2 0xa0 +#define I5000_FBDICMD_TS3 0xb0 +#define I5000_FBDICMD_TS2_MERGE 0xd0 +#define I5000_FBDICMD_TS2_NOMERGE 0xe0 +#define I5000_FBDICMD_ALL_ONES 0xf0 + +#define I5000_AMBPRESENT0 0x64 +#define I5000_AMBPRESENT1 0x66 + +#define I5000_FBDSBTXCFG0 0xc0 +#define I5000_FBDSBTXCFG1 0xc1 + +#define I5000_PROCENABLE 0xf0 +#define I5000_FBD0IBPORTCTL 0x180 +#define I5000_FBD0IBTXPAT2EN 0x1a8 +#define I5000_FBD0IBRXPAT2EN 0x1ac + +#define I5000_FBD0IBTXMSK 0x18c +#define I5000_FBD0IBRXMSK 0x190 + +#define I5000_FBDPLLCTRL 0x1c0 + +/* dev 16, function 1 registers */ +#define I5000_MC 0x40 +#define I5000_DRTA 0x48 +#define I5000_DRTB 0x4c +#define I5000_ERRPERR 0x50 +#define I5000_MCA 0x58 +#define I5000_TOLM 0x6c +#define I5000_MIR0 0x80 +#define I5000_MIR1 0x84 +#define I5000_MIR2 0x88 +#define I5000_AMIR0 0x8c +#define I5000_AMIR1 0x90 +#define I5000_AMIR2 0x94 + +#define I5000_FERR_FAT_FBD 0x98 +#define I5000_NERR_FAT_FBD 0x9c +#define I5000_FERR_NF_FBD 0xa0 +#define I5000_NERR_NF_FBD 0xa4 +#define I5000_EMASK_FBD 0xa8 +#define I5000_ERR0_FBD 0xac +#define I5000_ERR1_FBD 0xb0 +#define I5000_ERR2_FBD 0xb4 +#define I5000_MCERR_FBD 0xb8 +#define I5000_NRECMEMA 0xbe +#define I5000_NRECMEMB 0xc0 +#define I5000_NRECFGLOG 0xc4 +#define I5000_NRECMEMA 0xbe +#define I5000_NRECFBDA 0xc8 +#define I5000_NRECFBDB 0xcc +#define I5000_NRECFBDC 0xd0 +#define I5000_NRECFBDD 0xd4 +#define I5000_NRECFBDE 0xd8 + +#define I5000_REDMEMB 0x7c +#define I5000_RECMEMA 0xe2 +#define I5000_RECMEMB 0xe4 +#define I5000_RECFGLOG 0xe8 +#define I5000_RECFBDA 0xec +#define I5000_RECFBDB 0xf0 +#define I5000_RECFBDC 0xf4 +#define I5000_RECFBDD 0xf8 +#define I5000_RECFBDE 0xfc + +#define I5000_FBDTOHOSTGRCFG0 0x160 +#define I5000_FBDTOHOSTGRCFG1 0x164 +#define I5000_HOSTTOFBDGRCFG 0x168 +#define I5000_GRFBDLVLDCFG 0x16c +#define I5000_GRHOSTFULLCFG 0x16d +#define I5000_GRBUBBLECFG 0x16e +#define I5000_GRFBDTOHOSTDBLCFG 0x16f + +/* dev 16, function 2 registers */ +#define I5000_FERR_GLOBAL 0x40 +#define I5000_NERR_GLOBAL 0x44 + +/* dev 21, function 0 registers */ +#define I5000_MTR0 0x80 +#define I5000_MTR1 0x84 +#define I5000_MTR2 0x88 +#define I5000_MTR3 0x8c +#define I5000_DMIR0 0x90 +#define I5000_DMIR1 0x94 +#define I5000_DMIR2 0x98 +#define I5000_DMIR3 0x9c +#define I5000_DMIR4 0xa0 + +#define DEFAULT_AMBASE 0xfe000000 + +/* AMB function 1 registers */ +#define AMB_FBDSBCFGNXT 0x54 +#define AMB_FBDLOCKTO 0x68 +#define AMB_EMASK 0x8c +#define AMB_FERR 0x90 +#define AMB_NERR 0x94 +#define AMB_CMD2DATANXT 0xe8 + +/* AMB function 3 registers */ +#define AMB_DAREFTC 0x70 +#define AMB_DSREFTC 0x74 +#define AMB_DRT 0x78 +#define AMB_DRC 0x7c + +#define AMB_MBCSR 0x40 +#define AMB_MBADDR 0x44 +#define AMB_MBLFSRSED 0xa4 + +/* AMB function 4 registers */ +#define AMB_DCALCSR 0x40 +#define AMB_DCALADDR 0x44 +#define AMB_DCALCSR_START (1 << 31) + +#define AMB_DCALCSR_OPCODE_NOP 0x00 +#define AMB_DCALCSR_OPCODE_REFRESH 0x01 +#define AMB_DCALCSR_OPCODE_PRECHARGE 0x02 +#define AMB_DCALCSR_OPCODE_MRS_EMRS 0x03 +#define AMB_DCALCSR_OPCODE_DQS_DELAY_CAL 0x05 +#define AMB_DCALCSR_OPCODE_RECV_ENABLE_CAL 0x0c +#define AMB_DCALCSR_OPCODE_SELF_REFRESH_ENTRY 0x0d + +#define AMB_DDR2ODTC 0xfc + +#define FBDIMM_SPD_SDRAM_ADDRESSING 0x04 +#define FBDIMM_SPD_MODULE_ORGANIZATION 0x07 +#define FBDIMM_SPD_FTB 0x08 +#define FBDIMM_SPD_MTB_DIVIDEND 0x09 +#define FBDIMM_SPD_MTB_DIVISOR 0x0a +#define FBDIMM_SPD_MIN_TCK 0x0b +#define FBDIMM_SPD_CAS_LATENCIES 0x0d +#define FBDIMM_SPD_CAS_MIN_LATENCY 0x0e +#define FBDIMM_SPD_T_WR 0x10 +#define FBDIMM_SPD_T_RCD 0x13 +#define FBDIMM_SPD_T_RRD 0x14 +#define FBDIMM_SPD_T_RP 0x15 +#define FBDIMM_SPD_T_RAS_RC_MSB 0x16 +#define FBDIMM_SPD_T_RAS 0x17 +#define FBDIMM_SPD_T_RC 0x18 +#define FBDIMM_SPD_T_RFC 0x19 +#define FBDIMM_SPD_T_WTR 0x1b +#define FBDIMM_SPD_T_RTP 0x1c +#define FBDIMM_SPD_BURST_LENGTHS_SUPPORTED 0x1d +#define FBDIMM_SPD_ODT 0x4f +#define FBDIMM_SPD_T_REFI 0x20 +#define FBDIMM_SPD_T_BB 0x83 +#define FBDIMM_SPD_CMD2DATA_800 0x54 +#define FBDIMM_SPD_CMD2DATA_667 0x55 +#define FBDIMM_SPD_CMD2DATA_533 0x56 + +void i5000_fbdimm_init(void); + +#define I5000_BURST4 0x01 +#define I5000_BURST8 0x02 +#define I5000_BURST_CHOP 0x80 + +#define I5000_ODT_50 4 +#define I5000_ODT_75 2 +#define I5000_ODT_150 1 + +enum ddr_speeds { + DDR_533MHZ, + DDR_667MHZ, + DDR_MAX, +}; + +struct i5000_fbdimm { + struct i5000_fbd_branch *branch; + struct i5000_fbd_channel *channel; + struct i5000_fbd_setup *setup; + enum ddr_speeds speed; + int num; + int present:1; + u32 ambase; + + /* SPD data */ + u8 amb_personality_bytes[14]; + u8 banks; + u8 rows; + u8 columns; + u8 ranks; + u8 odt; + u8 sdram_width; + u8 mtb_divisor; + u8 mtb_dividend; + u8 t_ck_min; + u8 min_cas_latency; + u8 t_rrd; + u16 t_rfc; + u8 t_wtr; + u8 t_refi; + u8 cmd2datanxt[DDR_MAX]; + + u16 vendor; + u16 device; + + /* memory rank size in MB */ + int ranksize; +}; + +struct i5000_fbd_channel { + struct i5000_fbdimm dimm[I5000_MAX_DIMM_PER_CHANNEL]; + struct i5000_fbd_branch *branch; + struct i5000_fbd_setup *setup; + int num; + int used; + int highest_amb; + int columns; + int rows; + int ranks; + int banks; + int width; + /* memory size in MB on this channel */ + int totalmem; +}; + +struct i5000_fbd_branch { + struct i5000_fbd_channel channel[I5000_MAX_CHANNEL]; + struct i5000_fbd_setup *setup; + device_t branchdev; + int num; + int used; + /* memory size in MB on this branch */ + int totalmem; +}; + +enum odt { + ODT_150OHM=1, + ODT_50OHM=4, + ODT_75OHM=2, +}; + +enum bl { + BL_BL4=1, + BL_BL8=2, +}; + +struct i5000_fbd_setup { + struct i5000_fbd_branch branch[I5000_MAX_BRANCH]; + struct i5000_fbdimm *dimms[I5000_MAX_DIMMS]; + enum bl bl; + enum ddr_speeds ddr_speed; + + int single_channel:1; + u32 tolm; + + /* global SDRAM timing parameters */ + u8 t_al; + u8 t_cl; + u8 t_ras; + u8 t_wrc; + u8 t_rc; + u8 t_rfc; + u8 t_rrd; + u8 t_ref; + u8 t_w2rdr; + u8 t_r2w; + u8 t_w2r; + u8 t_r2r; + u8 t_w2w; + u8 t_wtr; + u8 t_rcd; + u8 t_rp; + u8 t_wr; + u8 t_rtp; + /* memory size in MB */ + int totalmem; +}; + +int mainboard_set_fbd_clock(int); +#define AMB_ADDR(base, fn, reg) (base | ((fn & 7) << 8) | ((reg & 0xff))) +#endif diff --git a/src/northbridge/intel/i5000/udelay.c b/src/northbridge/intel/i5000/udelay.c new file mode 100644 index 0000000..6462fe0 --- /dev/null +++ b/src/northbridge/intel/i5000/udelay.c @@ -0,0 +1,84 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <delay.h> +#include <stdint.h> +#include <cpu/x86/tsc.h> +#include <cpu/x86/msr.h> +#include <console/console.h> +/** + * Intel Core(tm) cpus always run the TSC at the maximum possible CPU clock + */ + +void udelay(u32 us) +{ + u32 dword; + tsc_t tsc, tsc1, tscd; + msr_t msr; + u32 fsb = 0, divisor; + u32 d; /* ticks per us */ + u32 dn = 0x1000000 / 2; /* how many us before we need to use hi */ + + msr = rdmsr(0xcd); + switch (msr.lo & 0x07) { + case 5: + fsb = 400; + break; + case 1: + fsb = 533; + break; + case 3: + fsb = 667; + break; + case 2: + fsb = 800; + break; + case 0: + fsb = 1067; + break; + case 4: + fsb = 1333; + break; + case 6: + fsb = 1600; + break; + } + + msr = rdmsr(0x198); + divisor = (msr.hi >> 8) & 0x1f; + + d = fsb * divisor; + + tscd.hi = us / dn; + tscd.lo = (us - tscd.hi * dn) * d; + + tsc1 = rdtsc(); + dword = tsc1.lo + tscd.lo; + if ((dword < tsc1.lo) || (dword < tscd.lo)) { + tsc1.hi++; + } + tsc1.lo = dword; + tsc1.hi += tscd.hi; + + tsc = rdtsc(); + + do { + tsc = rdtsc(); + } while ((tsc.hi < tsc1.hi) || ((tsc.hi == tsc1.hi) && (tsc.lo < tsc1.lo))); +}

1 0

Patch set updated for coreboot: cf962a0 Add cache_as_ram_ht.inc with hyper-threading CPU support
by Kyösti Mälkki 01 Feb '12

01 Feb '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/604 -gerrit commit cf962a0ff185cb8b1d04f4744a0bbd063d521cf5 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Feb 1 19:08:23 2012 +0200 Add cache_as_ram_ht.inc with hyper-threading CPU support This variant of cache_as_ram.inc starts the sibling CPU processors and clears the cache disable bits (CR0.CD) in case a hyper-threading CPU is detected. A secondary main (named main_no_xip) built into romstage can be executed with XIP cache disabled. On my test setup (Intel e7505) ECC scrub fails if run with XIP enabled. The code was developed for model_f25 from model_6ex. Some of the cache enable-disable logic seems spurious to me. Change-Id: Ieabb86a7c47afb3e178cc75bb89dee3efe0c3d18 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/intel/car/cache_as_ram_ht.inc | 192 +++++++++++++++++++++++++-------- 1 files changed, 149 insertions(+), 43 deletions(-) diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc index 18ada29..3961535 100644 --- a/src/cpu/intel/car/cache_as_ram_ht.inc +++ b/src/cpu/intel/car/cache_as_ram_ht.inc @@ -3,6 +3,7 @@ * * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich(a)gmail.com> * Copyright (C) 2007-2008 coresystems GmbH + * Copyright (C) 2012 Kyösti Mälkki <kyosti.malkki(a)gmail.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,22 +22,22 @@ #include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/post_code.h> +#include <cpu/x86/lapic_def.h> #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE - /* Save the BIST result. */ - movl %eax, %ebp +#define lapic(x) $(LAPIC_DEFAULT_BASE | LAPIC_ ## x) +#define START_IPI_VECTOR ((CONFIG_AP_SIPI_VECTOR >> 12) & 0xff) -cache_as_ram: - post_code(0x20) + .code32 - /* Send INIT IPI to all excluding ourself. */ - movl $0x000C4500, %eax - movl $0xFEE00300, %esi - movl %eax, (%esi) + /* Save the BIST result. */ + movl %eax, %ebp - /* Zero out all fixed range and variable range MTRRs. */ + /* Zero out all fixed range and variable range MTRRs. + * For hyper-threaded CPU MTRRs are shared so we actually + * clear them more than once, but we don't care. */ movl $mtrr_table, %esi movl $((mtrr_table_end - mtrr_table) / 2), %edi xorl %eax, %eax @@ -55,6 +56,98 @@ clear_mtrrs: andl $(~0x00000cff), %eax wrmsr + /* For a hyper-threading processor, cache must not be disabled + * on an AP on the same physical package with the BSP. + */ + movl $01, %eax + cpuid + btl $28, %edx + jnc cache_as_ram + bswapl %ebx + cmpb $01, %bh + jbe cache_as_ram + +hyper_threading_cpu: + /* Enable local apic. */ + movl $LAPIC_BASE_MSR, %ecx + rdmsr + andl $(~0x0F), %edx /* MAXPHYWID = 36 */ + andl $(~LAPIC_BASE_MSR_ADDR_MASK), %eax + orl $(LAPIC_DEFAULT_BASE | LAPIC_BASE_MSR_ENABLE), %eax + wrmsr + andl $LAPIC_BASE_MSR_BOOTSTRAP_PROCESSOR, %eax + jnz bsp_init + +ap_init: + /* Do not disable cache (so BSP can enable it). */ + movl %cr0, %eax + andl $(~((1 << 30) | (1 << 29))), %eax + movl %eax, %cr0 + + /* MTRR registers are shared between HT siblings. */ + movl $0x300, %ecx + rdmsr + inc %eax + wrmsr + +ap_halt: + cli +1: hlt + jnz 1b + + +bsp_init: + /* Send INIT IPI to all excluding ourself. */ + movl lapic(ICR), %edi + movl $(LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | LAPIC_DM_INIT), %eax +1: movl %eax, (%edi) + movl $0x30, %ecx +2: pause + dec %ecx + jnz 2b + movl (%edi), %ecx + andl $LAPIC_ICR_BUSY, %ecx + jnz 1b + + /* delay 10 ms */ + movl $10000, %ecx +1: inb $0x80, %al + dec %ecx + jnz 1b + + /* Send Start IPI to all excluding ourself. */ + movl lapic(ICR), %edi + movl $(LAPIC_DEST_ALLBUT | LAPIC_DM_STARTUP | START_IPI_VECTOR), %eax +1: movl %eax, (%edi) + movl $0x30, %ecx +2: pause + dec %ecx + jnz 2b + movl (%edi), %ecx + andl $LAPIC_ICR_BUSY, %ecx + jnz 1b + + /* delay 250 us */ + movl $250, %ecx +1: inb $0x80, %al + dec %ecx + jnz 1b + + /* Wait for sibling CPU to start. */ +1: movl $0x300, %ecx + rdmsr + andl %eax, %eax + jnz sipi_complete + + movl $0x30, %ecx +2: pause + dec %ecx + jnz 2b + jmp 1b + +sipi_complete: + +cache_as_ram: /* Set Cache-as-RAM base address. */ movl $(MTRRphysBase_MSR(0)), %ecx movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax @@ -67,36 +160,34 @@ clear_mtrrs: movl $0x0000000f, %edx wrmsr - /* Enable MTRR. */ + /* Enable variable MTRRs. */ movl $MTRRdefType_MSR, %ecx rdmsr orl $MTRRdefTypeEn, %eax wrmsr - /* Enable L2 cache. */ - movl $0x11e, %ecx - rdmsr - orl $(1 << 8), %eax - wrmsr - - /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ + /* Enable cache. */ movl %cr0, %eax andl $(~((1 << 30) | (1 << 29))), %eax invd movl %eax, %cr0 + invd - /* Clear the cache memory reagion. */ - movl $CACHE_AS_RAM_BASE, %esi - movl %esi, %edi - movl $(CACHE_AS_RAM_SIZE / 4), %ecx - // movl $0x23322332, %eax + /* Clear memory for stack. */ + cld xorl %eax, %eax + movl $(CACHE_AS_RAM_BASE), %edi + movl $(CACHE_AS_RAM_SIZE / 4), %ecx rep stosl +#if 0 /* Enable Cache-as-RAM mode by disabling cache. */ movl %cr0, %eax orl $(1 << 30), %eax + wbinvd movl %eax, %cr0 + wbinvd +#endif #if CONFIG_XIP_ROM_SIZE /* Enable cache for our code in Flash because we do XIP here */ @@ -117,32 +208,60 @@ clear_mtrrs: wrmsr #endif /* CONFIG_XIP_ROM_SIZE */ - /* Enable cache. */ - movl %cr0, %eax +#if 0 + /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ + movl %cr0, %eax andl $(~((1 << 30) | (1 << 29))), %eax movl %eax, %cr0 +#endif - /* Set up the stack pointer. */ #if CONFIG_USBDEBUG /* Leave some space for the struct ehci_debug_info. */ - movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %eax + movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 128), %esp #else - movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %eax + movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE), %esp #endif - movl %eax, %esp /* Restore the BIST result. */ movl %ebp, %eax movl %esp, %ebp pushl %eax - post_code(0x23) + post_code(0x23); - /* Call romstage.c main function. */ call main + addl $4, %esp post_code(0x2f) +#if CONFIG_MAIN_WITHOUT_XIP + /* With Intel e7505 memory controller, hardware ECC scrub + * halts and/or flushes call stack if run with XIP enabled. + */ + + /* Disable cache. */ + movl %cr0, %eax + orl $(1 << 30), %eax + movl %eax, %cr0 + + /* Disable Flash XIP. */ + movl $MTRRphysMask_MSR(1), %ecx + movl $0x0, %edx + movl $0x0, %eax + wrmsr + invd + + /* Enable cache. */ + movl %cr0, %eax + andl $~((1 << 30) | (1 << 29)), %eax + movl %eax, %cr0 + + pushl $0x0 + call main_no_xip + addl $4, %esp + movl %esp, %ebp +#endif + post_code(0x30) /* Disable cache. */ @@ -159,20 +278,7 @@ clear_mtrrs: wrmsr post_code(0x31) - invd -#if 0 - xorl %eax, %eax - xorl %edx, %edx - movl $MTRRphysBase_MSR(0), %ecx - wrmsr - movl $MTRRphysMask_MSR(0), %ecx - wrmsr - movl $MTRRphysBase_MSR(1), %ecx - wrmsr - movl $MTRRphysMask_MSR(1), %ecx - wrmsr -#endif post_code(0x33)

1 0

New patch to review for coreboot: d26740b Apply cache-as-ram conditionally on socket mPGA604
by Kyösti Mälkki 01 Feb '12

01 Feb '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/607 -gerrit commit d26740b827bcd4b3621200f8a9c911a107857022 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Feb 1 19:15:13 2012 +0200 Apply cache-as-ram conditionally on socket mPGA604 The socket mPGA604 is for P4 Xeon which to my knowledge is always HT-enabled. I assume the existing usage of car/cache_as_ram.inc on socket_mPGA604, namely the Tyan S2735, as broken. Existing car/cache_as_ram.inc has invalid SIPI vector and it does not initialise AP CPU's to activate L2 cache. Other mPGA604 boards are not affected, as they have not been converted to CAR. Change-Id: I7320589695c7f6a695b313a8d0b01b6b1cafbb04 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/Makefile.inc | 8 +------- src/cpu/intel/socket_mPGA604/Kconfig | 16 ++++++++++++++++ src/cpu/intel/socket_mPGA604/Makefile.inc | 2 ++ 3 files changed, 19 insertions(+), 7 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 36f9d3a..420378b 100755 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -190,13 +190,7 @@ crt0s += $(src)/cpu/x86/sse_enable.inc endif crt0s += $(cpu_incs) - -# -# FIXME move to CPU_INTEL_SOCKET_MPGA604 -# -ifeq ($(CONFIG_BOARD_TYAN_S2735),y) -crt0s += $(src)/cpu/intel/car/cache_as_ram.inc -endif +crt0s += $(cpu_incs-y) ifeq ($(CONFIG_LLSHELL),y) crt0s += $(src)/arch/x86/llshell/llshell.inc diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig index 2fc27cf..8f65a98 100644 --- a/src/cpu/intel/socket_mPGA604/Kconfig +++ b/src/cpu/intel/socket_mPGA604/Kconfig @@ -1,5 +1,10 @@ config CPU_INTEL_SOCKET_MPGA604 bool + +if CPU_INTEL_SOCKET_MPGA604 + +config SOCKET_SPECIFIC_OPTIONS # dummy + def_bool y select CPU_INTEL_MODEL_F2X select CPU_INTEL_MODEL_F3X select CPU_INTEL_MODEL_F4X @@ -14,3 +19,14 @@ config SSE2 bool default n depends on CPU_INTEL_SOCKET_MPGA604 + +config DCACHE_RAM_BASE + hex + default 0x0ffafc000 + +config DCACHE_RAM_SIZE + hex + default 0x4000 + +endif # CPU_INTEL_SOCKET_MPGA604 + diff --git a/src/cpu/intel/socket_mPGA604/Makefile.inc b/src/cpu/intel/socket_mPGA604/Makefile.inc index 1404e84..fb1cacd 100644 --- a/src/cpu/intel/socket_mPGA604/Makefile.inc +++ b/src/cpu/intel/socket_mPGA604/Makefile.inc @@ -10,3 +10,5 @@ subdirs-y += ../../x86/smm subdirs-y += ../microcode subdirs-y += ../hyperthreading +cpu_incs-$(CONFIG_CACHE_AS_RAM) += $(src)/cpu/intel/car/cache_as_ram_ht.inc +

1 0

New patch to review for coreboot: 5025489 Copy existing cache_as_ram code
by Kyösti Mälkki 01 Feb '12

01 Feb '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/606 -gerrit commit 50254890e9ce191ac7a5820ad45cb2f2bade02e6 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Feb 1 18:48:19 2012 +0200 Copy existing cache_as_ram code Use model_6ex/cache_as_ram.inc as a template for model_f2x with hyper-threading CPUs. Change-Id: I09619363e714b1ebf813932b0b22123c1d89010e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/intel/car/cache_as_ram_ht.inc | 265 +++++++++++++++++++++++++++++++++ 1 files changed, 265 insertions(+), 0 deletions(-) diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc new file mode 100644 index 0000000..18ada29 --- /dev/null +++ b/src/cpu/intel/car/cache_as_ram_ht.inc @@ -0,0 +1,265 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich(a)gmail.com> + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <cpu/x86/stack.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/post_code.h> + +#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE +#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE + + /* Save the BIST result. */ + movl %eax, %ebp + +cache_as_ram: + post_code(0x20) + + /* Send INIT IPI to all excluding ourself. */ + movl $0x000C4500, %eax + movl $0xFEE00300, %esi + movl %eax, (%esi) + + /* Zero out all fixed range and variable range MTRRs. */ + movl $mtrr_table, %esi + movl $((mtrr_table_end - mtrr_table) / 2), %edi + xorl %eax, %eax + xorl %edx, %edx +clear_mtrrs: + movw (%esi), %bx + movzx %bx, %ecx + wrmsr + add $2, %esi + dec %edi + jnz clear_mtrrs + + /* Configure the default memory type to uncacheable. */ + movl $MTRRdefType_MSR, %ecx + rdmsr + andl $(~0x00000cff), %eax + wrmsr + + /* Set Cache-as-RAM base address. */ + movl $(MTRRphysBase_MSR(0)), %ecx + movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax + xorl %edx, %edx + wrmsr + + /* Set Cache-as-RAM mask. */ + movl $(MTRRphysMask_MSR(0)), %ecx + movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax + movl $0x0000000f, %edx + wrmsr + + /* Enable MTRR. */ + movl $MTRRdefType_MSR, %ecx + rdmsr + orl $MTRRdefTypeEn, %eax + wrmsr + + /* Enable L2 cache. */ + movl $0x11e, %ecx + rdmsr + orl $(1 << 8), %eax + wrmsr + + /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ + movl %cr0, %eax + andl $(~((1 << 30) | (1 << 29))), %eax + invd + movl %eax, %cr0 + + /* Clear the cache memory reagion. */ + movl $CACHE_AS_RAM_BASE, %esi + movl %esi, %edi + movl $(CACHE_AS_RAM_SIZE / 4), %ecx + // movl $0x23322332, %eax + xorl %eax, %eax + rep stosl + + /* Enable Cache-as-RAM mode by disabling cache. */ + movl %cr0, %eax + orl $(1 << 30), %eax + movl %eax, %cr0 + +#if CONFIG_XIP_ROM_SIZE + /* Enable cache for our code in Flash because we do XIP here */ + movl $MTRRphysBase_MSR(1), %ecx + xorl %edx, %edx + /* + * IMPORTANT: The following calculation _must_ be done at runtime. See + * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html + */ + movl $copy_and_run, %eax + andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax + orl $MTRR_TYPE_WRBACK, %eax + wrmsr + + movl $MTRRphysMask_MSR(1), %ecx + movl $0x0000000f, %edx + movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax + wrmsr +#endif /* CONFIG_XIP_ROM_SIZE */ + + /* Enable cache. */ + movl %cr0, %eax + andl $(~((1 << 30) | (1 << 29))), %eax + movl %eax, %cr0 + + /* Set up the stack pointer. */ +#if CONFIG_USBDEBUG + /* Leave some space for the struct ehci_debug_info. */ + movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %eax +#else + movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %eax +#endif + movl %eax, %esp + + /* Restore the BIST result. */ + movl %ebp, %eax + movl %esp, %ebp + pushl %eax + + post_code(0x23) + + /* Call romstage.c main function. */ + call main + + post_code(0x2f) + + post_code(0x30) + + /* Disable cache. */ + movl %cr0, %eax + orl $(1 << 30), %eax + movl %eax, %cr0 + + post_code(0x31) + + /* Disable MTRR. */ + movl $MTRRdefType_MSR, %ecx + rdmsr + andl $(~MTRRdefTypeEn), %eax + wrmsr + + post_code(0x31) + + invd +#if 0 + xorl %eax, %eax + xorl %edx, %edx + movl $MTRRphysBase_MSR(0), %ecx + wrmsr + movl $MTRRphysMask_MSR(0), %ecx + wrmsr + movl $MTRRphysBase_MSR(1), %ecx + wrmsr + movl $MTRRphysMask_MSR(1), %ecx + wrmsr +#endif + + post_code(0x33) + + /* Enable cache. */ + movl %cr0, %eax + andl $~((1 << 30) | (1 << 29)), %eax + movl %eax, %cr0 + + post_code(0x36) + + /* Disable cache. */ + movl %cr0, %eax + orl $(1 << 30), %eax + movl %eax, %cr0 + + post_code(0x38) + + /* Enable Write Back and Speculative Reads for the first 1MB. */ + movl $MTRRphysBase_MSR(0), %ecx + movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax + xorl %edx, %edx + wrmsr + movl $MTRRphysMask_MSR(0), %ecx + movl $(~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid), %eax + movl $0x0000000f, %edx // 36bit address space + wrmsr + + /* Enable caching and Speculative Reads for the last 4MB. */ + movl $MTRRphysBase_MSR(1), %ecx + movl $(0xffc00000 | MTRR_TYPE_WRPROT), %eax + xorl %edx, %edx + wrmsr + movl $MTRRphysMask_MSR(1), %ecx + movl $(~(4 * 1024 * 1024 - 1) | MTRRphysMaskValid), %eax + movl $0x0000000f, %edx // 36bit address space + wrmsr + + post_code(0x39) + + /* And enable cache again after setting MTRRs. */ + movl %cr0, %eax + andl $~((1 << 30) | (1 << 29)), %eax + movl %eax, %cr0 + + post_code(0x3a) + + /* Enable MTRR. */ + movl $MTRRdefType_MSR, %ecx + rdmsr + orl $MTRRdefTypeEn, %eax + wrmsr + + post_code(0x3b) + + /* Invalidate the cache again. */ + invd + + post_code(0x3c) + + /* Clear boot_complete flag. */ + xorl %ebp, %ebp +__main: + post_code(POST_PREPARE_RAMSTAGE) + cld /* Clear direction flag. */ + + movl %ebp, %esi + + movl $ROMSTAGE_STACK, %esp + movl %esp, %ebp + pushl %esi + call copy_and_run + +.Lhlt: + post_code(POST_DEAD_CODE) + hlt + jmp .Lhlt + +mtrr_table: + /* Fixed MTRRs */ + .word 0x250, 0x258, 0x259 + .word 0x268, 0x269, 0x26A + .word 0x26B, 0x26C, 0x26D + .word 0x26E, 0x26F + /* Variable MTRRs */ + .word 0x200, 0x201, 0x202, 0x203 + .word 0x204, 0x205, 0x206, 0x207 + .word 0x208, 0x209, 0x20A, 0x20B + .word 0x20C, 0x20D, 0x20E, 0x20F +mtrr_table_end: +

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New patch to review for coreboot: 6ec51f8 romcc: kill gcc warnings and .gitignore generated files
by Bernhard Urban 01 Feb '12

01 Feb '12

Bernhard Urban (lewurm(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/605 -gerrit commit 6ec51f82110a88ffd5443c5fa6b8aa9ebad357b9 Author: Bernhard Urban <lewurm(a)gmail.com> Date: Wed Feb 1 16:30:30 2012 +0100 romcc: kill gcc warnings and .gitignore generated files don't remove calls to `flatten()' and `correct_coalesce_conflicts()', since they (probably) have side effects. Change-Id: I78fc4163b3f5f1f5f3c5153f9559c22e11e8344d Signed-off-by: Bernhard Urban <lewurm(a)gmail.com> --- .gitignore | 3 +++ util/romcc/romcc.c | 51 ++++++++++++++++++--------------------------------- 2 files changed, 21 insertions(+), 33 deletions(-) diff --git a/.gitignore b/.gitignore index a08cb12..8e259c7 100644 --- a/.gitignore +++ b/.gitignore @@ -44,3 +44,6 @@ util/msrtool/msrtool util/nvramtool/.dependencies util/nvramtool/nvramtool util/superiotool/superiotool +util/romcc/romcc +util/romcc/tests/*.S-O2-mmmx +util/romcc/tests/fail_test*.S diff --git a/util/romcc/romcc.c b/util/romcc/romcc.c index 7eced78..c7ef223 100644 --- a/util/romcc/romcc.c +++ b/util/romcc/romcc.c @@ -4080,12 +4080,10 @@ static void raw_next_token(struct compile_state *state, } /* string constants */ else if ((c == '"') || ((c == 'L') && (c1 == '"'))) { - int wchar, multiline; + int multiline; - wchar = 0; multiline = 0; if (c == 'L') { - wchar = 1; tokp = next_char(file, tokp, 1); } while((c = get_char(file, tokp)) != -1) { @@ -4113,12 +4111,10 @@ static void raw_next_token(struct compile_state *state, } /* character constants */ else if ((c == '\'') || ((c == 'L') && (c1 == '\''))) { - int wchar, multiline; + int multiline; - wchar = 0; multiline = 0; if (c == 'L') { - wchar = 1; tokp = next_char(file, tokp, 1); } while((c = get_char(file, tokp)) != -1) { @@ -4897,13 +4893,11 @@ static void raw_token(struct compile_state *state, struct token *tk) static void pp_token(struct compile_state *state, struct token *tk) { - struct file_state *file; int rescan; raw_token(state, tk); do { rescan = 0; - file = state->file; if (tk->tok == TOK_SPACE) { raw_token(state, tk); rescan = 1; @@ -7509,7 +7503,6 @@ static struct triple *write_expr( struct compile_state *state, struct triple *dest, struct triple *rval) { struct triple *def; - int op; def = 0; if (!rval) { @@ -7532,7 +7525,6 @@ static struct triple *write_expr( } /* Now figure out which assignment operator to use */ - op = -1; if (is_in_reg(state, dest)) { def = triple(state, OP_WRITE, dest->type, rval, dest); if (MISC(def, 0) != dest) { @@ -9168,8 +9160,10 @@ static struct triple *decompose_index(struct compile_state *state, static void decompose_compound_types(struct compile_state *state) { struct triple *ins, *next, *first; +#if DEBUG_DECOMPOSE_HIRES FILE *fp; fp = state->dbgout; +#endif first = state->first; ins = first; @@ -10462,7 +10456,7 @@ static void register_builtin_function(struct compile_state *state, const char *name, int op, struct type *rtype, ...) { struct type *ftype, *atype, *ctype, *crtype, *param, **next; - struct triple *def, *arg, *result, *work, *last, *first, *retvar, *ret; + struct triple *def, *result, *work, *first, *retvar, *ret; struct hash_entry *ident; struct file_state file; int parameters; @@ -10530,7 +10524,7 @@ static void register_builtin_function(struct compile_state *state, } else { atype = param; } - arg = flatten(state, first, variable(state, atype)); + flatten(state, first, variable(state, atype)); param = param->right; } work = new_triple(state, op, rtype, -1, parameters); @@ -10542,7 +10536,7 @@ static void register_builtin_function(struct compile_state *state, work = write_expr(state, deref_index(state, result, 1), work); } work = flatten(state, first, work); - last = flatten(state, first, label(state)); + flatten(state, first, label(state)); ret = flatten(state, first, ret); name_len = strlen(name); ident = lookup(state, name, name_len); @@ -13309,7 +13303,7 @@ static void resolve_branches(struct compile_state *state, struct triple *first) static struct triple *function_definition( struct compile_state *state, struct type *type) { - struct triple *def, *tmp, *first, *end, *retvar, *result, *ret; + struct triple *def, *tmp, *first, *end, *retvar, *ret; struct triple *fname; struct type *fname_type; struct hash_entry *ident; @@ -13365,7 +13359,7 @@ static struct triple *function_definition( /* Remove all type qualifiers from the return type */ new_type(TYPE_PRODUCT, ctype, clone_type(0, type->left)), 0); crtype->elements = 2; - result = flatten(state, end, variable(state, crtype)); + flatten(state, end, variable(state, crtype)); /* Allocate a variable for the return address */ retvar = flatten(state, end, variable(state, &void_ptr_type)); @@ -14326,8 +14320,7 @@ static void expand_function_call( struct triple *func, *func_first, *func_last, *retvar; struct triple *first; struct type *ptype, *rtype; - struct triple *jmp; - struct triple *ret_addr, *ret_loc, *ret_set; + struct triple *ret_addr, *ret_loc; struct triple_reg_set *enclose, *set; int closure_idx, pvals, i; @@ -14429,8 +14422,8 @@ static void expand_function_call( } ret_addr = flatten(state, ret_loc, ret_addr); - ret_set = flatten(state, ret_loc, write_expr(state, retvar, ret_addr)); - jmp = flatten(state, ret_loc, + flatten(state, ret_loc, write_expr(state, retvar, ret_addr)); + flatten(state, ret_loc, call(state, retvar, ret_addr, func_first, func_last)); /* Find the result */ @@ -14745,7 +14738,7 @@ struct triple *output_asm(struct compile_state *state) static void join_functions(struct compile_state *state) { - struct triple *jmp, *start, *end, *call, *in, *out, *func; + struct triple *start, *end, *call, *in, *out, *func; struct file_state file; struct type *pnext, *param; struct type *result_type, *args_type; @@ -14870,7 +14863,7 @@ static void join_functions(struct compile_state *state) walk_functions(state, insert_function, end); if (start->next != end) { - jmp = flatten(state, start, branch(state, end, 0)); + flatten(state, start, branch(state, end, 0)); } /* OK now the functions have been joined. */ @@ -17911,10 +17904,9 @@ static void awaken( static void eliminate_inefectual_code(struct compile_state *state) { - struct block *block; struct dead_triple *dtriple, *work_list, **work_list_tail, *dt; int triples, i; - struct triple *first, *final, *ins; + struct triple *first, *ins; if (!(state->compiler->flags & COMPILER_ELIMINATE_INEFECTUAL_CODE)) { return; @@ -17925,7 +17917,6 @@ static void eliminate_inefectual_code(struct compile_state *state) work_list_tail = &work_list; first = state->first; - final = state->first->prev; /* Count how many triples I have */ triples = count_triples(state); @@ -17935,7 +17926,6 @@ static void eliminate_inefectual_code(struct compile_state *state) ins = first; i = 1; - block = 0; do { dtriple[i].triple = ins; dtriple[i].block = block_of_triple(state, ins); @@ -18293,8 +18283,6 @@ static void print_interference_block( for(done = 0, ptr = block->first; !done; ptr = ptr->next) { struct live_range *lr; unsigned id; - int op; - op = ptr->op; done = (ptr == block->last); lr = rstate->lrd[ptr->id].lr; @@ -20085,7 +20073,6 @@ static void allocate_registers(struct compile_state *state) do { struct live_range **point, **next; - int conflicts; int tangles; int coalesced; @@ -20105,7 +20092,7 @@ static void allocate_registers(struct compile_state *state) rstate.blocks = compute_variable_lifetimes(state, &state->bb); /* Fix invalid mandatory live range coalesce conflicts */ - conflicts = correct_coalesce_conflicts(state, rstate.blocks); + correct_coalesce_conflicts(state, rstate.blocks); /* Fix two simultaneous uses of the same register. * In a few pathlogical cases a partial untangle moves @@ -23186,13 +23173,12 @@ struct reg_info arch_reg_rhs(struct compile_state *state, struct triple *ins, in static struct triple *mod_div(struct compile_state *state, struct triple *ins, int div_op, int index) { - struct triple *div, *piece0, *piece1; + struct triple *div, *piece1; /* Generate the appropriate division instruction */ div = post_triple(state, ins, div_op, ins->type, 0, 0); RHS(div, 0) = RHS(ins, 0); RHS(div, 1) = RHS(ins, 1); - piece0 = LHS(div, 0); piece1 = LHS(div, 1); div->template_id = TEMPLATE_DIV32; use_triple(RHS(div, 0), div); @@ -24393,11 +24379,10 @@ static void print_op_move(struct compile_state *state, if ((size_of(state, src->type) < size_of(state, dst->type)) && (is_signed(src->type))) { - int bits, reg_bits, shift_bits; + int reg_bits, shift_bits; int dst_reg; int dst_regcm; - bits = size_of(state, src->type); reg_bits = reg_size(state, dst); if (reg_bits > 32) { reg_bits = 32;

1 0

Patch set updated for coreboot: 480d5a0 Refactor and clean-up i82801 LPC codes
by Kyösti Mälkki 01 Feb '12

01 Feb '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/302 -gerrit commit 480d5a0e605800bba8725cc37a6b251ce309288d Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Jan 31 16:40:31 2012 +0200 Refactor and clean-up i82801 LPC codes Rewrite IOAPIC initialisation using global setup_ioapic() or setup_ioapic_novectors(). In my opinion, the _novectors() variant that is currently used is not sufficient to route IOAPIC interrupts on boot since Virtual Wire programming and/or vectors are not programmed. That takes further study and separate patch. Select Kconfig option IOAPIC as the southbridge has one and now requires that arch/x86/lib/ioapic.c is compiled in. Unify handling of ACPI BARs. Enable device resources during dev->ops->enable() and not during dev->ops->init(). Change-Id: I8ad80fdd0913995471269f33293c4a4b8cf1de83 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/include/arch/ioapic.h | 1 + src/arch/x86/lib/ioapic.c | 11 +++ src/southbridge/intel/i82801ax/Kconfig | 1 + src/southbridge/intel/i82801ax/lpc.c | 59 ++++++++++------ src/southbridge/intel/i82801bx/Kconfig | 1 + src/southbridge/intel/i82801bx/lpc.c | 58 +++++++++------ src/southbridge/intel/i82801cx/Kconfig | 1 + src/southbridge/intel/i82801cx/lpc.c | 107 ++++++++++++++++------------- src/southbridge/intel/i82801dx/i82801dx.h | 1 + src/southbridge/intel/i82801dx/lpc.c | 68 +++++++++++-------- src/southbridge/intel/i82801ex/i82801ex.h | 9 +++ src/southbridge/intel/i82801ex/lpc.c | 82 +++++++++++++++------- src/southbridge/intel/i82801gx/i82801gx.h | 1 + src/southbridge/intel/i82801gx/lpc.c | 77 ++++++++++++--------- 14 files changed, 297 insertions(+), 180 deletions(-) diff --git a/src/arch/x86/include/arch/ioapic.h b/src/arch/x86/include/arch/ioapic.h index 623f617..3eabcdc 100644 --- a/src/arch/x86/include/arch/ioapic.h +++ b/src/arch/x86/include/arch/ioapic.h @@ -40,5 +40,6 @@ void setup_ioapic(u32 ioapic_base, u8 ioapic_id); void clear_ioapic(u32 ioapic_base); +void setup_ioapic_novectors(u32 ioapic_base, u8 new_id); #endif diff --git a/src/arch/x86/lib/ioapic.c b/src/arch/x86/lib/ioapic.c index 5e17990..1d42658 100644 --- a/src/arch/x86/lib/ioapic.c +++ b/src/arch/x86/lib/ioapic.c @@ -203,3 +203,14 @@ void setup_ioapic(u32 ioapic_base, u8 new_id) load_vectors(ioapic_base, bsp_lapicid); } +void setup_ioapic_novectors(u32 ioapic_base, u8 new_id) +{ + u8 ioapic_dt = CONFIG_IOAPIC_DELIVERY_TYPE; + + printk(BIOS_DEBUG, "IOAPIC: Initializing IOAPIC at 0x%08x\n", + ioapic_base); + init_ioapic(ioapic_base, new_id, ioapic_dt); + + printk(BIOS_CRIT, "IOAPIC: Interrupt Vectors were not initialized\n"); +} + diff --git a/src/southbridge/intel/i82801ax/Kconfig b/src/southbridge/intel/i82801ax/Kconfig index 70734a7..71ae016 100644 --- a/src/southbridge/intel/i82801ax/Kconfig +++ b/src/southbridge/intel/i82801ax/Kconfig @@ -19,6 +19,7 @@ config SOUTHBRIDGE_INTEL_I82801AX bool + select IOAPIC select HAVE_HARD_RESET select USE_WATCHDOG_ON_BOOT diff --git a/src/southbridge/intel/i82801ax/lpc.c b/src/southbridge/intel/i82801ax/lpc.c index c9404ed..c6be112 100644 --- a/src/southbridge/intel/i82801ax/lpc.c +++ b/src/southbridge/intel/i82801ax/lpc.c @@ -70,17 +70,30 @@ typedef struct southbridge_intel_i82801ax_config config_t; * Use the defined IRQ values above or set mainboard * specific IRQ values in your devicetree.cb. */ -static void i82801ax_enable_apic(struct device *dev) -{ - u32 reg32; - volatile u32 *ioapic_index = (volatile u32 *)IO_APIC_ADDR; - volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10); + +/** + * Enable ACPI I/O range. + * + * @param dev PCI device with ACPI and PM BAR's + */ +static void i82801ax_enable_acpi(struct device *dev) +{ /* Set ACPI base address (I/O space). */ pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1)); /* Enable ACPI I/O range decode and ACPI power management. */ pci_write_config8(dev, ACPI_CNTL, ACPI_EN); +} + +/** + * Set miscellanous static southbridge features. + * + * @param dev PCI device with I/O APIC control registers + */ +static void i82801ax_general_cntl(struct device *dev) +{ + u32 reg32; reg32 = pci_read_config32(dev, GEN_CNTL); reg32 |= (1 << 13); /* Coprocessor error enable (COPR_ERR_EN) */ @@ -88,20 +101,8 @@ static void i82801ax_enable_apic(struct device *dev) reg32 |= (1 << 2); /* DMA collection buffer enable (DCB_EN) */ reg32 |= (1 << 1); /* Delayed transaction enable (DTE) */ pci_write_config32(dev, GEN_CNTL, reg32); - printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32); - - *ioapic_index = 0; - *ioapic_data = (1 << 25); + printk(BIOS_DEBUG, "Southbridge GEN_CNTL 0x%08x\n", reg32); - *ioapic_index = 0; - reg32 = *ioapic_data; - printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", reg32); - if (reg32 != (1 << 25)) - die("APIC Error\n"); - - /* TODO: From i82801ca, needed/useful on other ICH? */ - *ioapic_index = 3; /* Select Boot Configuration register. */ - *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */ } static void i82801ax_enable_serial_irqs(struct device *dev) @@ -216,11 +217,8 @@ static void i82801ax_lpc_decode_en(device_t dev) static void lpc_init(struct device *dev) { - /* Set the value for PCI command register. */ - pci_write_config16(dev, PCI_COMMAND, 0x000f); - /* IO APIC initialization. */ - i82801ax_enable_apic(dev); + setup_ioapic_novectors(IO_APIC_ADDR, 0x02); i82801ax_enable_serial_irqs(dev); @@ -272,10 +270,25 @@ static void i82801ax_lpc_read_resources(device_t dev) res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } +static void i82801ax_lpc_enable_resources(device_t dev) +{ + /* Enable the normal PCI resources. */ + pci_dev_enable_resources(dev); + + /* Enable ACPI and GPIO BARs. */ + i82801ax_enable_acpi(dev); + + /* Set features (most important: IOAPIC). */ + i82801ax_general_cntl(dev); + + /* Set the value for PCI command register. */ + pci_write_config16(dev, PCI_COMMAND, 0x000f); +} + static struct device_operations lpc_ops = { .read_resources = i82801ax_lpc_read_resources, .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, + .enable_resources = i82801ax_lpc_enable_resources, .init = lpc_init, .scan_bus = scan_static_bus, .enable = i82801ax_enable, diff --git a/src/southbridge/intel/i82801bx/Kconfig b/src/southbridge/intel/i82801bx/Kconfig index 00cb5bf..3d725d4 100644 --- a/src/southbridge/intel/i82801bx/Kconfig +++ b/src/southbridge/intel/i82801bx/Kconfig @@ -19,6 +19,7 @@ config SOUTHBRIDGE_INTEL_I82801BX bool + select IOAPIC select HAVE_HARD_RESET select USE_WATCHDOG_ON_BOOT diff --git a/src/southbridge/intel/i82801bx/lpc.c b/src/southbridge/intel/i82801bx/lpc.c index 0ff44e6..34eccf3 100644 --- a/src/southbridge/intel/i82801bx/lpc.c +++ b/src/southbridge/intel/i82801bx/lpc.c @@ -72,17 +72,29 @@ typedef struct southbridge_intel_i82801bx_config config_t; * Use the defined IRQ values above or set mainboard * specific IRQ values in your devicetree.cb. */ -static void i82801bx_enable_apic(struct device *dev) -{ - uint32_t reg32; - volatile uint32_t *ioapic_index = (volatile uint32_t *)IO_APIC_ADDR; - volatile uint32_t *ioapic_data = (volatile uint32_t *)(IO_APIC_ADDR + 0x10); +/** + * Enable ACPI I/O range. + * + * @param dev PCI device with ACPI and PM BAR's + */ +static void i82801bx_enable_acpi(struct device *dev) +{ /* Set ACPI base address (I/O space). */ pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1)); /* Enable ACPI I/O range decode and ACPI power management. */ pci_write_config8(dev, ACPI_CNTL, ACPI_EN); +} + +/** + * Set miscellanous static southbridge features. + * + * @param dev PCI device with I/O APIC control registers + */ +static void i82801bx_general_cntl(struct device *dev) +{ + u32 reg32; reg32 = pci_read_config32(dev, GEN_CNTL); reg32 |= (1 << 13); /* Coprocessor error enable (COPR_ERR_EN) */ @@ -90,20 +102,8 @@ static void i82801bx_enable_apic(struct device *dev) reg32 |= (1 << 2); /* DMA collection buffer enable (DCB_EN) */ reg32 |= (1 << 1); /* Delayed transaction enable (DTE) */ pci_write_config32(dev, GEN_CNTL, reg32); - printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32); - - *ioapic_index = 0; - *ioapic_data = (1 << 25); - - *ioapic_index = 0; - reg32 = *ioapic_data; - printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", reg32); - if (reg32 != (1 << 25)) - die("APIC Error\n"); + printk(BIOS_DEBUG, "Southbridge GEN_CNTL 0x%08x\n", reg32); - /* TODO: From i82801ca, needed/useful on other ICH? */ - *ioapic_index = 3; /* Select Boot Configuration register. */ - *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */ } static void i82801bx_enable_serial_irqs(struct device *dev) @@ -234,11 +234,8 @@ static void lpc_init(struct device *dev) { uint16_t ich_model = pci_read_config16(dev, PCI_DEVICE_ID); - /* Set the value for PCI command register. */ - pci_write_config16(dev, PCI_COMMAND, 0x000f); - /* IO APIC initialization. */ - i82801bx_enable_apic(dev); + setup_ioapic_novectors(IO_APIC_ADDR, 0x02); i82801bx_enable_serial_irqs(dev); @@ -290,10 +287,25 @@ static void i82801bx_lpc_read_resources(device_t dev) res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } +static void i82801bx_lpc_enable_resources(device_t dev) +{ + /* Enable the normal PCI resources. */ + pci_dev_enable_resources(dev); + + /* Enable ACPI and GPIO BARs. */ + i82801bx_enable_acpi(dev); + + /* Set features (most important: IOAPIC). */ + i82801bx_general_cntl(dev); + + /* Set the value for PCI command register. */ + pci_write_config16(dev, PCI_COMMAND, 0x000f); +} + static struct device_operations lpc_ops = { .read_resources = i82801bx_lpc_read_resources, .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, + .enable_resources = i82801bx_lpc_enable_resources, .init = lpc_init, .scan_bus = scan_static_bus, .enable = i82801bx_enable, diff --git a/src/southbridge/intel/i82801cx/Kconfig b/src/southbridge/intel/i82801cx/Kconfig index a0c775d..7534cbb 100644 --- a/src/southbridge/intel/i82801cx/Kconfig +++ b/src/southbridge/intel/i82801cx/Kconfig @@ -1,2 +1,3 @@ config SOUTHBRIDGE_INTEL_I82801CX bool + select IOAPIC diff --git a/src/southbridge/intel/i82801cx/lpc.c b/src/southbridge/intel/i82801cx/lpc.c index a1ffb8f..bacca48 100644 --- a/src/southbridge/intel/i82801cx/lpc.c +++ b/src/southbridge/intel/i82801cx/lpc.c @@ -24,34 +24,43 @@ #define MAINBOARD_POWER_ON 1 -static void i82801cx_enable_ioapic( struct device *dev) +/** + * Enable ACPI I/O range. + * + * @param dev PCI device with ACPI and PM BAR's + */ +static void i82801cx_enable_acpi(struct device *dev) +{ + // Set ACPI base address to 0x1100 (I/O space) + pci_write_config32(dev, PMBASE, 0x00001101); + + // Enable ACPI I/O and power management + pci_write_config8(dev, ACPI_CNTL, 0x10); + + // Set GPIO base address to 0x1180 (I/O space) + pci_write_config32(dev, GPIO_BASE, 0x00001181); + + // Enable GPIO + pci_write_config8(dev, GPIO_CNTL, 0x10); +} + +/** + * Set miscellanous static southbridge features. + * + * @param dev PCI device with I/O APIC control registers + */ +static void i82801cx_general_cntl(struct device *dev) { - uint32_t dword; - volatile uint32_t* ioapic_index = (volatile uint32_t*)IO_APIC_ADDR; - volatile uint32_t* ioapic_data = (volatile uint32_t*)(IO_APIC_ADDR + 0x10); - - dword = pci_read_config32(dev, GEN_CNTL); - dword |= (3 << 7); /* enable ioapic & disable SMBus interrupts */ - dword |= (1 <<13); /* coprocessor error enable */ - dword |= (1 << 1); /* delay transaction enable */ - dword |= (1 << 2); /* DMA collection buf enable */ - pci_write_config32(dev, GEN_CNTL, dword); - printk(BIOS_DEBUG, "ioapic southbridge enabled %x\n",dword); - - // Must program the APIC's ID before using it - - *ioapic_index = 0; // Select APIC ID register - *ioapic_data = (2<<24); - - // Hang if the ID didn't take (chip not present?) - *ioapic_index = 0; - dword = *ioapic_data; - printk(BIOS_DEBUG, "Southbridge apic id = %x\n", (dword>>24) & 0xF); - if(dword != (2<<24)) - die(""); - - *ioapic_index = 3; // Select Boot Configuration register - *ioapic_data = 1; // Use Processor System Bus to deliver interrupts + u32 reg32; + + reg32 = pci_read_config32(dev, GEN_CNTL); + reg32 |= (1 << 13); /* Coprocessor error enable (COPR_ERR_EN) */ + reg32 |= (3 << 7); /* IOAPIC enable (APIC_EN) */ + reg32 |= (1 << 2); /* DMA collection buffer enable (DCB_EN) */ + reg32 |= (1 << 1); /* Delayed transaction enable (DTE) */ + pci_write_config32(dev, GEN_CNTL, reg32); + printk(BIOS_DEBUG, "Southbridge GEN_CNTL 0x%08x\n", reg32); + } // This is how interrupts are received from the Super I/O chip @@ -118,20 +127,6 @@ static void i82801cx_rtc_init(struct device *dev) static void i82801cx_1f0_misc(struct device *dev) { - // Prevent LPC disabling, enable parity errors, and SERR# (System Error) - pci_write_config16(dev, PCI_COMMAND, 0x014f); - - // Set ACPI base address to 0x1100 (I/O space) - pci_write_config32(dev, PMBASE, 0x00001101); - - // Enable ACPI I/O and power management - pci_write_config8(dev, ACPI_CNTL, 0x10); - - // Set GPIO base address to 0x1180 (I/O space) - pci_write_config32(dev, GPIO_BASE, 0x00001181); - - // Enable GPIO - pci_write_config8(dev, GPIO_CNTL, 0x10); // Route PIRQA to IRQ11, PIRQB to IRQ3, PIRQC to IRQ5, PIRQD to IRQ10 pci_write_config32(dev, PIRQA_ROUT, 0x0A05030B); @@ -160,8 +155,9 @@ static void lpc_init(struct device *dev) int pwr_on=-1; int nmi_option; + i82801cx_general_cntl(dev); /* IO APIC initialization */ - i82801cx_enable_ioapic(dev); + setup_ioapic_novectors(IO_APIC_ADDR, 0x02); i82801cx_enable_serial_irqs(dev); @@ -229,13 +225,28 @@ static void i82801cx_lpc_read_resources(device_t dev) res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } +static void i82801cx_lpc_enable_resources(device_t dev) +{ + /* Enable the normal PCI resources. */ + pci_dev_enable_resources(dev); + + /* Enable ACPI and GPIO BARs. */ + i82801cx_enable_acpi(dev); + + /* Set features (most important: IOAPIC). */ + i82801cx_general_cntl(dev); + + /* Prevent LPC disabling, enable parity errors, and SERR# (System Error). */ + pci_write_config16(dev, PCI_COMMAND, 0x014f); +} + static struct device_operations lpc_ops = { - .read_resources = i82801cx_lpc_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = lpc_init, - .scan_bus = scan_static_bus, - .enable = 0, + .read_resources = i82801cx_lpc_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = i82801cx_lpc_enable_resources, + .init = lpc_init, + .scan_bus = scan_static_bus, + .enable = 0, }; static const struct pci_driver lpc_driver __pci_driver = { diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h index a38c793..2484eb1 100644 --- a/src/southbridge/intel/i82801dx/i82801dx.h +++ b/src/southbridge/intel/i82801dx/i82801dx.h @@ -86,6 +86,7 @@ extern void i82801dx_enable(device_t dev); #define PMBASE_ADDR 0x0400 #define DEFAULT_PMBASE PMBASE_ADDR #define ACPI_CNTL 0x44 +#define ACPI_EN (1 << 4) #define BIOS_CNTL 0x4E #define GPIO_BASE 0x58 #define GPIO_CNTL 0x5C diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c index 768e700..eec984d 100644 --- a/src/southbridge/intel/i82801dx/lpc.c +++ b/src/southbridge/intel/i82801dx/lpc.c @@ -36,37 +36,37 @@ typedef struct southbridge_intel_i82801dx_config config_t; -static void i82801dx_enable_ioapic(struct device *dev) +/** + * Enable ACPI I/O range. + * + * @param dev PCI device with ACPI and PM BAR's + */ +static void i82801dx_enable_acpi(struct device *dev) { - u32 reg32; - volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR); - volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10); - /* Set ACPI base address (I/O space). */ pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1)); - /* Enable ACPI I/O and power management. */ - pci_write_config8(dev, ACPI_CNTL, 0x10); + /* Enable ACPI I/O range decode and ACPI power management. */ + pci_write_config8(dev, ACPI_CNTL, ACPI_EN); +} + +/** + * Set miscellanous static southbridge features. + * + * @param dev PCI device with I/O APIC control registers + */ +static void i82801dx_general_cntl(struct device *dev) +{ + u32 reg32; reg32 = pci_read_config32(dev, GEN_CNTL); - reg32 |= (3 << 7); /* Enable IOAPIC */ - reg32 |= (1 << 13); /* Coprocessor error enable */ - reg32 |= (1 << 1); /* Delayed transaction enable */ - reg32 |= (1 << 2); /* DMA collection buffer enable */ + reg32 |= (1 << 13); /* Coprocessor error enable (COPR_ERR_EN) */ + reg32 |= (3 << 7); /* IOAPIC enable (APIC_EN) */ + reg32 |= (1 << 2); /* DMA collection buffer enable (DCB_EN) */ + reg32 |= (1 << 1); /* Delayed transaction enable (DTE) */ pci_write_config32(dev, GEN_CNTL, reg32); - printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32); - - *ioapic_index = 0; - *ioapic_data = (1 << 25); - - *ioapic_index = 0; - reg32 = *ioapic_data; - printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", reg32); - if (reg32 != (1 << 25)) - die("APIC Error\n"); + printk(BIOS_DEBUG, "Southbridge GEN_CNTL 0x%08x\n", reg32); - *ioapic_index = 3; /* Select Boot Configuration register. */ - *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */ } static void i82801dx_enable_serial_irqs(struct device *dev) @@ -264,11 +264,8 @@ static void enable_hpet(struct device *dev) static void lpc_init(struct device *dev) { - /* Set the value for PCI command register. */ - pci_write_config16(dev, PCI_COMMAND, 0x000f); - /* IO APIC initialization. */ - i82801dx_enable_ioapic(dev); + setup_ioapic_novectors(IO_APIC_ADDR, 0x02); i82801dx_enable_serial_irqs(dev); @@ -323,10 +320,25 @@ static void i82801dx_lpc_read_resources(device_t dev) res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } +static void i82801dx_lpc_enable_resources(device_t dev) +{ + /* Enable the normal PCI resources. */ + pci_dev_enable_resources(dev); + + /* Enable ACPI and GPIO BARs. */ + i82801dx_enable_acpi(dev); + + /* Set features (most important: IOAPIC). */ + i82801dx_general_cntl(dev); + + /* Set the value for PCI command register. */ + pci_write_config16(dev, PCI_COMMAND, 0x000f); +} + static struct device_operations lpc_ops = { .read_resources = i82801dx_lpc_read_resources, .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, + .enable_resources = i82801dx_lpc_enable_resources, .init = lpc_init, .scan_bus = scan_static_bus, .enable = i82801dx_enable, diff --git a/src/southbridge/intel/i82801ex/i82801ex.h b/src/southbridge/intel/i82801ex/i82801ex.h index 67fecdd..22a29f3 100644 --- a/src/southbridge/intel/i82801ex/i82801ex.h +++ b/src/southbridge/intel/i82801ex/i82801ex.h @@ -12,4 +12,13 @@ extern void i82801ex_enable(device_t dev); #define RTC_CONF 0xd8 #define GEN_PMCON_3 0xa4 + +#define PMBASE 0x40 +#define ACPI_CNTL 0x44 +#define ACPI_EN (1 << 4) +#define GPIO_BASE 0x58 +#define GPIO_CNTL 0x5C +#define GPIO_EN (1 << 4) + + #endif /* I82801EX_H */ diff --git a/src/southbridge/intel/i82801ex/lpc.c b/src/southbridge/intel/i82801ex/lpc.c index 998360c..81d8aef 100644 --- a/src/southbridge/intel/i82801ex/lpc.c +++ b/src/southbridge/intel/i82801ex/lpc.c @@ -12,8 +12,6 @@ #include <arch/ioapic.h> #include "i82801ex.h" -#define ACPI_BAR 0x40 -#define GPIO_BAR 0x58 #define NMI_OFF 0 #define MAINBOARD_POWER_OFF 0 @@ -23,6 +21,52 @@ #define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON #endif +typedef struct southbridge_intel_i82801ex_config config_t; + +/** + * Enable ACPI I/O range. + * + * @param dev PCI device with ACPI and PM BAR's + */ +static void i82801ex_enable_acpi(struct device *dev) +{ + u8 gpio_cntl; +#if 0 + /* many i82801's set pmbase here */ + /* Set ACPI base address (I/O space). */ + pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1)); +#endif + + /* Enable ACPI I/O range decode and ACPI power management. */ + pci_write_config8(dev, ACPI_CNTL, ACPI_EN); + + /* Enable the GPIO bar */ + gpio_cntl = pci_read_config8(dev, GPIO_CNTL); + gpio_cntl |= GPIO_EN; + pci_write_config8(dev, GPIO_CNTL, gpio_cntl); +} + +/** + * Set miscellanous static southbridge features. + * + * @param dev PCI device with I/O APIC configuration registers + */ +static void i82801ex_general_cntl(struct device *dev) +{ + u32 reg32; + + reg32 = pci_read_config32(dev, GEN_CNTL); + reg32 |= (3 << 7); /* IOAPIC enable (APIC_EN) */ + reg32 |= (1 << 1); /* Delayed transaction enable (DTE) */ + pci_write_config32(dev, GEN_CNTL, reg32); + printk(BIOS_DEBUG, "Southbridge GEN_CNTL 0x%08x\n", reg32); + + reg32 = pci_read_config32(dev, GEN_STS); + reg32 |= (1<<1); + pci_write_config32(dev, GEN_STS, reg32); + +} + #define SERIRQ_CNTL 0x64 static void i82801ex_enable_serial_irqs(device_t dev) { @@ -45,7 +89,6 @@ static void i82801ex_enable_lpc(device_t dev) pci_write_config8(dev, LPC_EN, 0x0d); } -typedef struct southbridge_intel_i82801ex_config config_t; static void set_i82801ex_gpio_use_sel( device_t dev, struct resource *res, config_t *config) @@ -193,7 +236,7 @@ static void i82801ex_gpio_init(device_t dev) /* Get the chip configuration */ config = dev->chip_info; /* Find the GPIO bar */ - res = find_resource(dev, GPIO_BAR); + res = find_resource(dev, GPIO_BASE); if (!res) { return; } @@ -239,17 +282,10 @@ static void enable_hpet(struct device *dev) static void lpc_init(struct device *dev) { uint8_t byte; - uint32_t value; int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; - /* IO APIC initialization */ - value = pci_read_config32(dev, 0xd0); - value |= (1 << 8)|(1<<7)|(1<<1); - pci_write_config32(dev, 0xd0, value); - value = pci_read_config32(dev, 0xd4); - value |= (1<<1); - pci_write_config32(dev, 0xd4, value); - setup_ioapic(IO_APIC_ADDR, 0); // Don't rename IO APIC ID. + /* IO APIC initialization. */ + setup_ioapic(IO_APIC_ADDR, 0); /* No APIC ID ?? */ i82801ex_enable_serial_irqs(dev); @@ -295,10 +331,10 @@ static void i82801ex_lpc_read_resources(device_t dev) pci_dev_read_resources(dev); /* Add the ACPI BAR */ - res = pci_get_resource(dev, ACPI_BAR); + res = pci_get_resource(dev, PMBASE); /* Add the GPIO BAR */ - res = pci_get_resource(dev, GPIO_BAR); + res = pci_get_resource(dev, GPIO_BASE); /* Add an extra subtractive resource for both memory and I/O. */ res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); @@ -321,20 +357,14 @@ static void i82801ex_lpc_read_resources(device_t dev) static void i82801ex_lpc_enable_resources(device_t dev) { - uint8_t acpi_cntl, gpio_cntl; - - /* Enable the normal pci resources */ + /* Enable the normal PCI resources. */ pci_dev_enable_resources(dev); - /* Enable the ACPI bar */ - acpi_cntl = pci_read_config8(dev, 0x44); - acpi_cntl |= (1 << 4); - pci_write_config8(dev, 0x44, acpi_cntl); + /* Enable ACPI and GPIO BARs. */ + i82801ex_enable_acpi(dev); - /* Enable the GPIO bar */ - gpio_cntl = pci_read_config8(dev, 0x5c); - gpio_cntl |= (1 << 4); - pci_write_config8(dev, 0x5c, gpio_cntl); + /* Set features (most important: IOAPIC). */ + i82801ex_general_cntl(dev); } static struct pci_operations lops_pci = { diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index 8fb5b92..7b93cbd 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -81,6 +81,7 @@ int smbus_read_byte(unsigned device, unsigned address); #define PMBASE 0x40 #define ACPI_CNTL 0x44 +#define ACPI_EN (1 << 7) /* NOTE: was 1<<4 until ICH7 */ #define BIOS_CNTL 0xDC #define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */ #define GPIO_CNTL 0x4C /* LPC GPIO Control Register */ diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index c6b76d3..882fafe 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -39,37 +39,38 @@ typedef struct southbridge_intel_i82801gx_config config_t; -static void i82801gx_enable_apic(struct device *dev) +/** + * Enable ACPI I/O range. + * + * @param dev PCI device with ACPI and PM BAR's + */ +static void i82801gx_enable_acpi(struct device *dev) { - int i; - u32 reg32; - volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR); - volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10); +#if 0 + /* many i82801's set pmbase here */ + /* Set ACPI base address (I/O space). */ + pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1)); +#endif - /* Enable ACPI I/O and power management. - * Set SCI IRQ to IRQ9 + /* Enable ACPI I/O range decode and ACPI power management. + * Select SCI IRQ as IRQ9. */ - pci_write_config8(dev, ACPI_CNTL, 0x80); - - *ioapic_index = 0; - *ioapic_data = (1 << 25); - - *ioapic_index = 0; - reg32 = *ioapic_data; - printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f); - if (reg32 != (1 << 25)) - die("APIC Error\n"); - - printk(BIOS_SPEW, "Dumping IOAPIC registers\n"); - for (i=0; i<3; i++) { - *ioapic_index = i; - printk(BIOS_SPEW, " reg 0x%04x:", i); - reg32 = *ioapic_data; - printk(BIOS_SPEW, " 0x%08x\n", reg32); - } + pci_write_config8(dev, ACPI_CNTL, ACPI_EN); +} + +/** + * Set miscellanous static southbridge features. + * + * @param dev PCI device with I/O APIC configuration registers + */ +static void i82801gx_general_cntl(struct device *dev) +{ + u32 reg32 = 0xABADBEEF; + + /* FIXME: Who sets OIC register @ 0x3155 ?? + */ + printk(BIOS_DEBUG, "Southbridge OIC 0x%08x.\n", reg32); - *ioapic_index = 3; /* Select Boot Configuration register. */ - *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */ } static void i82801gx_enable_serial_irqs(struct device *dev) @@ -418,11 +419,8 @@ static void lpc_init(struct device *dev) { printk(BIOS_DEBUG, "i82801gx: lpc_init\n"); - /* Set the value for PCI command register. */ - pci_write_config16(dev, PCI_COMMAND, 0x000f); - /* IO APIC initialization. */ - i82801gx_enable_apic(dev); + setup_ioapic_novectors(IO_APIC_ADDR, 0x02); i82801gx_enable_serial_irqs(dev); @@ -502,6 +500,21 @@ static void set_subsystem(device_t dev, unsigned vendor, unsigned device) } } +static void i82801gx_lpc_enable_resources(device_t dev) +{ + /* Enable the normal PCI resources. */ + pci_dev_enable_resources(dev); + + /* Enable ACPI and GPIO BARs. */ + i82801gx_enable_acpi(dev); + + /* Set features (most important: IOAPIC). */ + i82801gx_general_cntl(dev); + + /* Set the value for PCI command register. */ + pci_write_config16(dev, PCI_COMMAND, 0x000f); +} + static struct pci_operations pci_ops = { .set_subsystem = set_subsystem, }; @@ -509,7 +522,7 @@ static struct pci_operations pci_ops = { static struct device_operations device_ops = { .read_resources = i82801gx_lpc_read_resources, .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, + .enable_resources = i82801gx_lpc_enable_resources, .init = lpc_init, .scan_bus = scan_static_bus, .enable = i82801gx_enable,

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Patch set updated for coreboot: fbfb272 IOAPIC: Divide setup_ioapic() in two parts.
by Kyösti Mälkki 01 Feb '12

01 Feb '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/300 -gerrit commit fbfb2728b181dadd6d0d9ecb5b1f52d033e04cf1 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Jan 31 17:24:12 2012 +0200 IOAPIC: Divide setup_ioapic() in two parts. Currently some southbridge codes implement the init_ioapic() part locally and do not implement the load_vectors() part at all. I suspect that load_vectors() should always be called to enable IOAPIC interrupt routes before OS. Revised init_ioapic() to log on a critical level if one tries to change an already assigned (non-zero) APIC ID, or when the APIC ID is not assigned. Change-Id: Ic5e860b9b669ecd1e9ddac4bbb92d80bdb9c2fca Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/lib/ioapic.c | 151 +++++++++++++++++++++++++++++++++----------- 1 files changed, 113 insertions(+), 38 deletions(-) diff --git a/src/arch/x86/lib/ioapic.c b/src/arch/x86/lib/ioapic.c index 81d964c..7d166b9 100644 --- a/src/arch/x86/lib/ioapic.c +++ b/src/arch/x86/lib/ioapic.c @@ -34,6 +34,11 @@ static void io_apic_write(u32 ioapic_base, u32 reg, u32 value) write32(ioapic_base + 0x10, value); } +/** + * Clear all IOAPIC vectors. + * + * @param ioapic_base IOAPIC base address + */ void clear_ioapic(u32 ioapic_base) { u32 low, high; @@ -64,24 +69,84 @@ void clear_ioapic(u32 ioapic_base) } } -void setup_ioapic(u32 ioapic_base, u8 ioapic_id) +/** + * Assign IOAPIC with an ID and set delivery type. + * + * @param ioapic_base IOAPIC base address + * @param new_id If non-zero (1-15), assign new apic ID. + * If zero, use previously assigned apic ID. + * @param delivery If 0x0, deliver interrupts on APIC serial bus + * If 0x1, deliver interrupts on FSB + */ +static void init_ioapic(u32 ioapic_base, u8 new_id, u8 delivery) { - u32 bsp_lapicid = lapicid(); - u32 low, high; - u32 i, ioapic_interrupts; + u8 loud = 0; + u8 active_id; + u32 reg32; - printk(BIOS_DEBUG, "IOAPIC: Initializing IOAPIC at 0x%08x\n", - ioapic_base); - printk(BIOS_DEBUG, "IOAPIC: Bootstrap Processor Local APIC = 0x%02x\n", - bsp_lapicid); + reg32 = io_apic_read(ioapic_base, 0x00); + active_id = (reg32 >> 24) & 0xf; + + /* Changing a previously assigned ID and attempting + * to use ID=0 here are logged at a critical level. + */ + if ( ((active_id && new_id) && (active_id != new_id)) || + !(active_id || new_id)) + loud = 1; + + if (!new_id) { + printk(loud ? BIOS_CRIT : BIOS_DEBUG, + "IOAPIC: 0x%08x using old ID = %d\n", + ioapic_base, active_id); + + } else { + reg32 &= 0xf0ffffff; + reg32 |= (new_id & 0xf) << 24; + io_apic_write(ioapic_base, 0x00, reg32); + + printk(loud ? BIOS_CRIT : BIOS_DEBUG, + "IOAPIC: 0x%08x changing ID = %d->%d\n", + ioapic_base, active_id, new_id); + + reg32 = io_apic_read(ioapic_base, 0x00); + active_id = (reg32 >> 24) & 0xf; + if (active_id != new_id) + printk(BIOS_CRIT, + "IOAPIC: 0x%08x changing ID failed (%d!=%d)\n", + ioapic_base, active_id, new_id); + } - if (ioapic_id) { - printk(BIOS_DEBUG, "IOAPIC: ID = 0x%02x\n", ioapic_id); - /* Set IOAPIC ID if it has been specified. */ - io_apic_write(ioapic_base, 0x00, - (io_apic_read(ioapic_base, 0x00) & 0xf0ffffff) | - (ioapic_id << 24)); + /* Assign interrupt delivery type. */ + reg32 = io_apic_read(ioapic_base, 0x03); + switch (delivery) { + case 0: + printk(BIOS_DEBUG, "IOAPIC: Delivery is on APIC serial bus\n"); + reg32 = 0x00; + break; + case 1: + printk(BIOS_DEBUG, "IOAPIC: Delivery is on FSB\n"); + reg32 = 0x01; + break; + default: + printk(BIOS_CRIT, "IOAPIC: Delivery is reverted to FSB\n"); + reg32 = 0x01; + break; } + io_apic_write(ioapic_base, 0x03, reg32); +} + +/** + * Fill IOAPIC vectors all targeting the same processor. + * Virtual Wire Mode on vector 0 is enabled, others remain disabled. + * + * + * @param ioapic_base IOAPIC base address + * @param bsp_lapicid APIC ID of a CPU to receive the interrupts + */ +static void load_vectors(u32 ioapic_base, u8 bsp_lapicid) +{ + u32 low, high; + u32 i, ioapic_interrupts; /* Read the available number of interrupts. */ ioapic_interrupts = (io_apic_read(ioapic_base, 0x01) >> 16) & 0xff; @@ -89,28 +154,6 @@ void setup_ioapic(u32 ioapic_base, u8 ioapic_id) ioapic_interrupts = 24; printk(BIOS_DEBUG, "IOAPIC: %d interrupts\n", ioapic_interrupts); -// XXX this decision should probably be made elsewhere, and -// it's the C3, not the EPIA this depends on. -#if CONFIG_EPIA_VT8237R_INIT -#define IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS -#else -#define IOAPIC_INTERRUPTS_ON_FSB -#endif - -#ifdef IOAPIC_INTERRUPTS_ON_FSB - /* - * For the Pentium 4 and above APICs deliver their interrupts - * on the front side bus, enable that. - */ - printk(BIOS_DEBUG, "IOAPIC: Enabling interrupts on FSB\n"); - io_apic_write(ioapic_base, 0x03, - io_apic_read(ioapic_base, 0x03) | (1 << 0)); -#endif -#ifdef IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS - printk(BIOS_DEBUG, "IOAPIC: Enabling interrupts on APIC serial bus\n"); - io_apic_write(ioapic_base, 0x03, 0); -#endif - /* Enable Virtual Wire Mode. */ low = ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT; high = bsp_lapicid << (56 - 32); @@ -125,10 +168,8 @@ void setup_ioapic(u32 ioapic_base, u8 ioapic_id) printk(BIOS_SPEW, "IOAPIC: reg 0x%08x value 0x%08x 0x%08x\n", 0, high, low); - low = DISABLED; high = NONE; - for (i = 1; i < ioapic_interrupts; i++) { io_apic_write(ioapic_base, i * 2 + 0x10, low); io_apic_write(ioapic_base, i * 2 + 0x11, high); @@ -137,3 +178,37 @@ void setup_ioapic(u32 ioapic_base, u8 ioapic_id) i, high, low); } } + +// XXX this decision should probably be made elsewhere, and +// it's the C3, not the EPIA this depends on. + +#if CONFIG_EPIA_VT8237R_INIT +#define CONFIG_IOAPIC_DELIVERY_TYPE 0 +#else +#define CONFIG_IOAPIC_DELIVERY_TYPE 1 +#endif + +/** + * Assign IOAPIC with an ID + * + * Compile-time options from mainboard Kconfig can affect the + * chosen IOAPIC operational mode. + * + * @param ioapic_base IOAPIC base address + * @param new_id If non-zero (1-15), assign new apic ID. + * If zero, use previously assigned apic ID. + */ +void setup_ioapic(u32 ioapic_base, u8 new_id) +{ + u8 bsp_lapicid = lapicid(); + u8 ioapic_dt = CONFIG_IOAPIC_DELIVERY_TYPE; + + printk(BIOS_DEBUG, "IOAPIC: Initializing IOAPIC at 0x%08x\n", + ioapic_base); + init_ioapic(ioapic_base, new_id, ioapic_dt); + + printk(BIOS_DEBUG, "IOAPIC: Bootstrap Processor Local APIC ID = %d\n", + bsp_lapicid); + load_vectors(ioapic_base, bsp_lapicid); +} +

1 0

Patch set updated for coreboot: 4b6a312 Via Epia-N and C3: Set ioapic delivery type in Kconfig
by Kyösti Mälkki 01 Feb '12

01 Feb '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/435 -gerrit commit 4b6a3125c4366bdc00f1afa0a174fa5665c410d1 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Nov 21 19:12:50 2011 +0200 Via Epia-N and C3: Set ioapic delivery type in Kconfig The original comment says it's a Via C3 and not Epia requirement to deliver IOAPIC interrupts on APIC serial bus. If someone can confirm this, set delivery type under cpu/via/model_c3 instead. Change-Id: I73c55755e0ec1ac5756b4ee7ccdfc8eb93184e4f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/Kconfig | 5 +++++ src/arch/x86/lib/ioapic.c | 9 --------- src/mainboard/via/epia-n/Kconfig | 5 +++++ 3 files changed, 10 insertions(+), 9 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 64c359e..7e91144 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -239,6 +239,11 @@ config IOAPIC bool default n +# Boards with CPU_VIA_C3 may need to override delivery type. +config IOAPIC_DELIVERY_TYPE + int + default 1 + # TODO: Can probably be removed once all chipsets have kconfig options for it. config VIDEO_MB int diff --git a/src/arch/x86/lib/ioapic.c b/src/arch/x86/lib/ioapic.c index 7d166b9..5e17990 100644 --- a/src/arch/x86/lib/ioapic.c +++ b/src/arch/x86/lib/ioapic.c @@ -179,15 +179,6 @@ static void load_vectors(u32 ioapic_base, u8 bsp_lapicid) } } -// XXX this decision should probably be made elsewhere, and -// it's the C3, not the EPIA this depends on. - -#if CONFIG_EPIA_VT8237R_INIT -#define CONFIG_IOAPIC_DELIVERY_TYPE 0 -#else -#define CONFIG_IOAPIC_DELIVERY_TYPE 1 -#endif - /** * Assign IOAPIC with an ID * diff --git a/src/mainboard/via/epia-n/Kconfig b/src/mainboard/via/epia-n/Kconfig index 4806753..5a88f6a 100644 --- a/src/mainboard/via/epia-n/Kconfig +++ b/src/mainboard/via/epia-n/Kconfig @@ -28,4 +28,9 @@ config IRQ_SLOT_COUNT int default 7 +# IRQ delivery on APIC bus may be a Via C3 CPU requirement. +config IOAPIC_DELIVERY_TYPE + int + default 0 + endif # BOARD_VIA_EPIA_N

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coreboot February 2012