coreboot February 2012

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Patch set updated for coreboot: 13ac7a9 Add support for RAM-less multi-processor init
by Kyösti Mälkki 01 Feb '12

01 Feb '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/454 -gerrit commit 13ac7a9e4ed6cba54a049f584a87aabfa82756bc Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Feb 1 15:33:39 2012 +0200 Add support for RAM-less multi-processor init For a hyper-threading processor, enabling cache requires that both the BSP and AP CPU clear CR0.CD (Cache Disable) bit. For a Cache-As-Ram implementation, partial multi-processor initialisation precedes raminit and AP CPUs' 16bit entry must be run from ROM. The AP CPU can only start execute real-mode code at a 4kB aligned address below 1MB. The protected mode entry code for AP is identical with the BSP code, which is already located at the top of bootblock. This patch takes the simplest approach and aligns the bootblock 16 bit entry at highest possible 4kB boundary below 1MB. The symbol ap_sipi_vector is exported as CONFIG_AP_SIPI_VECTOR and will be used by a cache_as_ram.inc with hyper-threading support. Change-Id: I82e4edbf208c9ba863f51a64e50cd92871c528ef Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/Makefile.inc | 9 +++++++-- src/arch/x86/init/ldscript_failover.lb | 12 ++++++++---- 2 files changed, 15 insertions(+), 6 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index cbe38dd..36f9d3a 100755 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -338,6 +338,11 @@ $(obj)/bootblock.elf: $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.o $(obj)/bootbl $(OBJCOPY) --strip-debug $@ $(OBJCOPY) --add-gnu-debuglink=$(obj)/bootblock.debug $@ +$(obj)/bootblock_map.h: $(obj)/bootblock.elf + printf '#define CONFIG_AP_SIPI_VECTOR 0x' > $@ + grep ap_sipi_vector $(obj)/bootblock.map | colrm 9 >> $@ + printf '\n' >> $@ + ####################################################################### # Build the romstage $(obj)/coreboot.romstage: $(obj)/coreboot.pre1 $$(romstage-objs) $(obj)/romstage/ldscript.ld @@ -370,9 +375,9 @@ $(obj)/mainboard/$(MAINBOARDDIR)/crt0.romstage.o: $(obj)/mainboard/$(MAINBOARDDI @printf " CC $(subst $(obj)/,,$(@))\n" $(CC) -I$(obj) -Wa,-acdlns -c -o $@ $< > $(dir $(a))/crt0.disasm -$(obj)/mainboard/$(MAINBOARDDIR)/crt0.s: $(obj)/romstage/crt0.S $(obj)/config.h $(obj)/build.h +$(obj)/mainboard/$(MAINBOARDDIR)/crt0.s: $(obj)/romstage/crt0.S $(obj)/config.h $(obj)/build.h $(obj)/bootblock_map.h @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -I$(obj)/romstage -include $(obj)/config.h -include $(obj)/build.h -I. -I$(src) $< -o $@ + $(CC) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -I$(obj)/romstage -include $(obj)/config.h -include $(obj)/build.h -include $(obj)/bootblock_map.h -I. -I$(src) $< -o $@ seabios: $(MAKE) -C payloads/external/SeaBIOS -f Makefile.inc \ diff --git a/src/arch/x86/init/ldscript_failover.lb b/src/arch/x86/init/ldscript_failover.lb index 83e5eb3..052e0c5 100644 --- a/src/arch/x86/init/ldscript_failover.lb +++ b/src/arch/x86/init/ldscript_failover.lb @@ -29,17 +29,18 @@ MEMORY { TARGET(binary) SECTIONS { - /* Align .rom to next 4 byte boundary so no pad byte appears - * between _rom and _start. + /* Symbol ap_sipi_vector must be aligned to 4kB to start AP CPUs + * with Startup IPI message without RAM. */ .bogus ROMLOC_MIN : { - . = ALIGN(4); + . = ALIGN(4096); ROMLOC = .; } >rom = 0xff /* This section might be better named .setup */ .rom ROMLOC : { _rom = .; + ap_sipi_vector = .; *(.rom.text); *(.rom.data); *(.rom.data.*); @@ -51,7 +52,10 @@ SECTIONS * may cause the total size of a section to change when the start * address gets applied. */ - ROMLOC_MIN = 0xffffff00 - (_erom - _rom + 16); + ROMLOC_MIN = 0xffffff00 - (_erom - _rom + 16) - 4096; + + /* Post-check proper SIPI vector. */ + _bogus = ASSERT(((ap_sipi_vector & 0x0fff) == 0x0), "Bad SIPI vector alignment"); /DISCARD/ : { *(.comment)

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New patch to review for coreboot: 162b984 Add cache_as_ram.inc with hyper-threading CPU support
by Kyösti Mälkki 01 Feb '12

01 Feb '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/604 -gerrit commit 162b984fbc02c230175e431135e5d50d057c9f2f Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Feb 1 15:55:54 2012 +0200 Add cache_as_ram.inc with hyper-threading CPU support This variant of cache_as_ram.inc starts the sibling CPU processors and clears the cache disable bits (CR0.CD) in case a hyper-threading CPU is detected. A secondary main (named main_no_xip) built into romstage can be executed with XIP cache disabled. On my test setup (Intel e7505) ECC scrub fails if run with XIP enabled. The code was developed for model_f25 on socket_mPGA604, but probably should be placed under cpu/intel/car/ instead. Some of the cache enable-disable logic seems spurious to me. Change-Id: Ieabb86a7c47afb3e178cc75bb89dee3efe0c3d18 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/Makefile.inc | 8 +- src/cpu/Kconfig | 4 + src/cpu/intel/model_f2x/Kconfig | 4 + src/cpu/intel/model_f2x/Makefile.inc | 3 + src/cpu/intel/model_f2x/cache_as_ram.inc | 372 ++++++++++++++++++++++++++++++ src/cpu/intel/socket_mPGA604/Kconfig | 17 ++- 6 files changed, 400 insertions(+), 8 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 36f9d3a..420378b 100755 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -190,13 +190,7 @@ crt0s += $(src)/cpu/x86/sse_enable.inc endif crt0s += $(cpu_incs) - -# -# FIXME move to CPU_INTEL_SOCKET_MPGA604 -# -ifeq ($(CONFIG_BOARD_TYAN_S2735),y) -crt0s += $(src)/cpu/intel/car/cache_as_ram.inc -endif +crt0s += $(cpu_incs-y) ifeq ($(CONFIG_LLSHELL),y) crt0s += $(src)/arch/x86/llshell/llshell.inc diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index 6e65186..93b132d 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -9,6 +9,10 @@ config CACHE_AS_RAM bool default !ROMCC +config CACHE_AS_RAM_TEST + bool + default n + config DCACHE_RAM_BASE hex diff --git a/src/cpu/intel/model_f2x/Kconfig b/src/cpu/intel/model_f2x/Kconfig index 50cac79..7eafb4a 100644 --- a/src/cpu/intel/model_f2x/Kconfig +++ b/src/cpu/intel/model_f2x/Kconfig @@ -1,3 +1,7 @@ config CPU_INTEL_MODEL_F2X bool select SMP + select UDELAY_TSC +# select UDELAY_LAPIC +# select AP_IN_SIPI_WAIT + diff --git a/src/cpu/intel/model_f2x/Makefile.inc b/src/cpu/intel/model_f2x/Makefile.inc index c393343..a1e5463 100644 --- a/src/cpu/intel/model_f2x/Makefile.inc +++ b/src/cpu/intel/model_f2x/Makefile.inc @@ -1 +1,4 @@ driver-y += model_f2x_init.c + +cpu_incs-$(CONFIG_CACHE_AS_RAM) += $(src)/cpu/intel/model_f2x/cache_as_ram.inc + diff --git a/src/cpu/intel/model_f2x/cache_as_ram.inc b/src/cpu/intel/model_f2x/cache_as_ram.inc new file mode 100644 index 0000000..bdd7e1a --- /dev/null +++ b/src/cpu/intel/model_f2x/cache_as_ram.inc @@ -0,0 +1,372 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich(a)gmail.com> + * Copyright (C) 2007-2008 coresystems GmbH + * Copyright (C) 2012 Kyösti Mälkki <kyosti.malkki(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <cpu/x86/stack.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/post_code.h> +#include <cpu/x86/lapic_def.h> + + +#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE +#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE + +#define lapic(x) $(LAPIC_DEFAULT_BASE | LAPIC_ ## x) +#define START_IPI_VECTOR ((CONFIG_AP_SIPI_VECTOR >> 12) & 0xff) + + .code32 + + /* Save the BIST result. */ + movl %eax, %ebp + + /* Zero out all fixed range and variable range MTRRs. + * For hyper-threaded CPU MTRRs are shared so we actually + * clear them more than once, but we don't care. */ + movl $mtrr_table, %esi + movl $((mtrr_table_end - mtrr_table) / 2), %edi + xorl %eax, %eax + xorl %edx, %edx +clear_mtrrs: + movw (%esi), %bx + movzx %bx, %ecx + wrmsr + add $2, %esi + dec %edi + jnz clear_mtrrs + + /* Configure the default memory type to uncacheable. */ + movl $MTRRdefType_MSR, %ecx + rdmsr + andl $(~0x00000cff), %eax + wrmsr + + /* For a hyper-threading processor, cache must not be disabled + * on an AP on the same physical package with the BSP. + */ + movl $01, %eax + cpuid + btl $28, %edx + jnc cache_as_ram + bswapl %ebx + cmpb $01, %bh + jbe cache_as_ram + +hyper_threading_cpu: + /* Enable local apic. */ + movl $LAPIC_BASE_MSR, %ecx + rdmsr + andl $(~0x0F), %edx /* MAXPHYWID = 36 */ + andl $(~LAPIC_BASE_MSR_ADDR_MASK), %eax + orl $(LAPIC_DEFAULT_BASE | LAPIC_BASE_MSR_ENABLE), %eax + wrmsr + andl $LAPIC_BASE_MSR_BOOTSTRAP_PROCESSOR, %eax + jnz bsp_init + +ap_init: + /* Do not disable cache (so BSP can enable it). */ + movl %cr0, %eax + andl $(~((1 << 30) | (1 << 29))), %eax + movl %eax, %cr0 + + /* MTRR registers are shared between HT siblings. */ + movl $0x300, %ecx + rdmsr + inc %eax + wrmsr + +ap_halt: + cli +1: hlt + jnz 1b + + +bsp_init: + /* Send INIT IPI to all excluding ourself. */ + movl lapic(ICR), %edi + movl $(LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | LAPIC_DM_INIT), %eax +1: movl %eax, (%edi) + movl $0x30, %ecx +2: pause + dec %ecx + jnz 2b + movl (%edi), %ecx + andl $LAPIC_ICR_BUSY, %ecx + jnz 1b + + /* delay 10 ms */ + movl $10000, %ecx +1: inb $0x80, %al + dec %ecx + jnz 1b + + /* Send Start IPI to all excluding ourself. */ + movl lapic(ICR), %edi + movl $(LAPIC_DEST_ALLBUT | LAPIC_DM_STARTUP | START_IPI_VECTOR), %eax +1: movl %eax, (%edi) + movl $0x30, %ecx +2: pause + dec %ecx + jnz 2b + movl (%edi), %ecx + andl $LAPIC_ICR_BUSY, %ecx + jnz 1b + + /* delay 250 us */ + movl $250, %ecx +1: inb $0x80, %al + dec %ecx + jnz 1b + + /* Wait for sibling CPU to start. */ +1: movl $0x300, %ecx + rdmsr + andl %eax, %eax + jnz sipi_complete + + movl $0x30, %ecx +2: pause + dec %ecx + jnz 2b + jmp 1b + +sipi_complete: + +cache_as_ram: + /* Set Cache-as-RAM base address. */ + movl $(MTRRphysBase_MSR(0)), %ecx + movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax + xorl %edx, %edx + wrmsr + + /* Set Cache-as-RAM mask. */ + movl $(MTRRphysMask_MSR(0)), %ecx + movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax + movl $0x0000000f, %edx + wrmsr + + /* Enable variable MTRRs. */ + movl $MTRRdefType_MSR, %ecx + rdmsr + orl $MTRRdefTypeEn, %eax + wrmsr + + /* Enable cache. */ + movl %cr0, %eax + andl $(~((1 << 30) | (1 << 29))), %eax + invd + movl %eax, %cr0 + invd + + /* Clear memory for stack. */ + cld + xorl %eax, %eax + movl $(CACHE_AS_RAM_BASE), %edi + movl $(CACHE_AS_RAM_SIZE / 4), %ecx + rep stosl + +#if 0 + /* Enable Cache-as-RAM mode by disabling cache. */ + movl %cr0, %eax + orl $(1 << 30), %eax + wbinvd + movl %eax, %cr0 + wbinvd +#endif + +#if CONFIG_XIP_ROM_SIZE + /* Enable cache for our code in Flash because we do XIP here */ + movl $MTRRphysBase_MSR(1), %ecx + xorl %edx, %edx + /* + * IMPORTANT: The following calculation _must_ be done at runtime. See + * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html + */ + movl $copy_and_run, %eax + andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax + orl $MTRR_TYPE_WRBACK, %eax + wrmsr + + movl $MTRRphysMask_MSR(1), %ecx + movl $0x0000000f, %edx + movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax + wrmsr +#endif /* CONFIG_XIP_ROM_SIZE */ + +#if 0 + /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ + movl %cr0, %eax + andl $(~((1 << 30) | (1 << 29))), %eax + movl %eax, %cr0 +#endif + +#if CONFIG_USBDEBUG + /* Leave some space for the struct ehci_debug_info. */ + movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 128), %esp +#else + movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE), %esp +#endif + + /* Restore the BIST result. */ + movl %ebp, %eax + movl %esp, %ebp + pushl %eax + + post_code(0x23); + + call main + addl $4, %esp + + post_code(0x2f) + +#if CONFIG_MAIN_WITHOUT_XIP + /* With Intel e7505 memory controller, hardware ECC scrub + * halts and/or flushes call stack if run with XIP enabled. + */ + + /* Disable cache. */ + movl %cr0, %eax + orl $(1 << 30), %eax + movl %eax, %cr0 + + /* Disable Flash XIP. */ + movl $MTRRphysMask_MSR(1), %ecx + movl $0x0, %edx + movl $0x0, %eax + wrmsr + invd + + /* Enable cache. */ + movl %cr0, %eax + andl $~((1 << 30) | (1 << 29)), %eax + movl %eax, %cr0 + + pushl $0x0 + call main_no_xip + addl $4, %esp + movl %esp, %ebp +#endif + + post_code(0x30) + + /* Disable cache. */ + movl %cr0, %eax + orl $(1 << 30), %eax + movl %eax, %cr0 + + post_code(0x31) + + /* Disable MTRR. */ + movl $MTRRdefType_MSR, %ecx + rdmsr + andl $(~MTRRdefTypeEn), %eax + wrmsr + + post_code(0x31) + invd + + post_code(0x33) + + /* Enable cache. */ + movl %cr0, %eax + andl $~((1 << 30) | (1 << 29)), %eax + movl %eax, %cr0 + + post_code(0x36) + + /* Disable cache. */ + movl %cr0, %eax + orl $(1 << 30), %eax + movl %eax, %cr0 + + post_code(0x38) + + /* Enable Write Back and Speculative Reads for the first 1MB. */ + movl $MTRRphysBase_MSR(0), %ecx + movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax + xorl %edx, %edx + wrmsr + movl $MTRRphysMask_MSR(0), %ecx + movl $(~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid), %eax + movl $0x0000000f, %edx // 36bit address space + wrmsr + + /* Enable caching and Speculative Reads for the last 4MB. */ + movl $MTRRphysBase_MSR(1), %ecx + movl $(0xffc00000 | MTRR_TYPE_WRPROT), %eax + xorl %edx, %edx + wrmsr + movl $MTRRphysMask_MSR(1), %ecx + movl $(~(4 * 1024 * 1024 - 1) | MTRRphysMaskValid), %eax + movl $0x0000000f, %edx // 36bit address space + wrmsr + + post_code(0x39) + + /* And enable cache again after setting MTRRs. */ + movl %cr0, %eax + andl $~((1 << 30) | (1 << 29)), %eax + movl %eax, %cr0 + + post_code(0x3a) + + /* Enable MTRR. */ + movl $MTRRdefType_MSR, %ecx + rdmsr + orl $MTRRdefTypeEn, %eax + wrmsr + + post_code(0x3b) + + /* Invalidate the cache again. */ + invd + + post_code(0x3c) + + /* Clear boot_complete flag. */ + xorl %ebp, %ebp +__main: + post_code(POST_PREPARE_RAMSTAGE) + cld /* Clear direction flag. */ + + movl %ebp, %esi + + movl $ROMSTAGE_STACK, %esp + movl %esp, %ebp + pushl %esi + call copy_and_run + +.Lhlt: + post_code(POST_DEAD_CODE) + hlt + jmp .Lhlt + +mtrr_table: + /* Fixed MTRRs */ + .word 0x250, 0x258, 0x259 + .word 0x268, 0x269, 0x26A + .word 0x26B, 0x26C, 0x26D + .word 0x26E, 0x26F + /* Variable MTRRs */ + .word 0x200, 0x201, 0x202, 0x203 + .word 0x204, 0x205, 0x206, 0x207 + .word 0x208, 0x209, 0x20A, 0x20B + .word 0x20C, 0x20D, 0x20E, 0x20F +mtrr_table_end: + diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig index 2fc27cf..d8ea23a 100644 --- a/src/cpu/intel/socket_mPGA604/Kconfig +++ b/src/cpu/intel/socket_mPGA604/Kconfig @@ -1,11 +1,15 @@ config CPU_INTEL_SOCKET_MPGA604 bool + +if CPU_INTEL_SOCKET_MPGA604 + +config SOCKET_SPECIFIC_OPTIONS # dummy + def_bool y select CPU_INTEL_MODEL_F2X select CPU_INTEL_MODEL_F3X select CPU_INTEL_MODEL_F4X select MMX select SSE - select UDELAY_TSC # mPGA604 are usually Intel Netburst CPUs which should have SSE2 # but the ramtest.c code on the Dell S1850 seems to choke on @@ -14,3 +18,14 @@ config SSE2 bool default n depends on CPU_INTEL_SOCKET_MPGA604 + +config DCACHE_RAM_BASE + hex + default 0x0ffafc000 + +config DCACHE_RAM_SIZE + hex + default 0x4000 + +endif # CPU_INTEL_SOCKET_MPGA604 +

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Patch set updated for coreboot: c924cbe H8QGI: Increase xip size of supermicro/h8qgi from 512K to 1M Bytes.
by Kerry Sheh 01 Feb '12

01 Feb '12

Kerry Sheh (shekairui(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/568 -gerrit commit c924cbee830691c4a776465c09029575d0197c90 Author: Kerry Sheh <shekairui(a)gmail.com> Date: Wed Feb 1 16:05:50 2012 +0800 H8QGI: Increase xip size of supermicro/h8qgi from 512K to 1M Bytes. For mainboard using AMD AGESA framework, lots of AGESA code will be compiled into romstage, so romstage becomes larger, especially for mainboard support 2 or more processor families. H8QGI support both f10 and f15 CPUs, 512K default xip size is not enough, so increase to 1M Bytes. Change-Id: I1fb1aaad68aed8b41253a02cc0bc151c239b0dbe Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> --- src/mainboard/supermicro/h8qgi/Kconfig | 14 ++++++++++++++ 1 files changed, 14 insertions(+), 0 deletions(-) diff --git a/src/mainboard/supermicro/h8qgi/Kconfig b/src/mainboard/supermicro/h8qgi/Kconfig index e900ea8..201df45 100644 --- a/src/mainboard/supermicro/h8qgi/Kconfig +++ b/src/mainboard/supermicro/h8qgi/Kconfig @@ -123,5 +123,19 @@ config VGA_BIOS_ID depends on VGA_BIOS default "102b,0532" +config XIP_ROM_BASE + hex + default 0xfff00000 + +config XIP_ROM_SIZE + hex + default 0x100000 + help + Overwride the default write through caching size as 1M Bytes. + On some AMD paltform, one socket support 2 kinds of processor family, + Compiling 2 cpu families agesa code will increase the romstage size. + In order to execute romstage in place on the flash rom, + more space is required to be set as write through caching. + endif # BOARD_SUPERMICRO_H8QGI

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Patch set updated for coreboot: 52ae40f HWM: Nuvoton W83795G/ADG HWM support
by Kerry Sheh 01 Feb '12

01 Feb '12

Kerry Sheh (shekairui(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/569 -gerrit commit 52ae40f1de1b2e7c637858cbc80561a3a26de7da Author: Kerry Sheh <shekairui(a)gmail.com> Date: Wed Feb 1 19:43:52 2012 +0800 HWM: Nuvoton W83795G/ADG HWM support Supermicro H8QGI-F 1 Unit Chassis contain 9 system Fans, they are controled by a separate W83795G Hardware Monitor chip. This patch adds Nuvoton W83795G/ADG HWM support. Change-Id: I8756f5ed02dc2fa0884cde36e51451fd8aacee27 Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> --- src/drivers/i2c/Kconfig | 1 + src/drivers/i2c/Makefile.inc | 1 + src/drivers/i2c/w83795/Kconfig | 2 + src/drivers/i2c/w83795/Makefile.inc | 1 + src/drivers/i2c/w83795/chip.h | 4 + src/drivers/i2c/w83795/w83795.c | 276 ++++++++++++++++++++++++++ src/drivers/i2c/w83795/w83795.h | 73 +++++++ src/mainboard/supermicro/h8qgi/Kconfig | 1 + src/mainboard/supermicro/h8qgi/devicetree.cb | 8 +- src/mainboard/supermicro/h8qgi/romstage.c | 6 + 10 files changed, 371 insertions(+), 2 deletions(-) diff --git a/src/drivers/i2c/Kconfig b/src/drivers/i2c/Kconfig index 91ad025..09c306b 100644 --- a/src/drivers/i2c/Kconfig +++ b/src/drivers/i2c/Kconfig @@ -4,3 +4,4 @@ source src/drivers/i2c/adt7463/Kconfig source src/drivers/i2c/i2cmux/Kconfig source src/drivers/i2c/i2cmux2/Kconfig source src/drivers/i2c/lm63/Kconfig +source src/drivers/i2c/w83795/Kconfig diff --git a/src/drivers/i2c/Makefile.inc b/src/drivers/i2c/Makefile.inc index d462b69..97e9729 100644 --- a/src/drivers/i2c/Makefile.inc +++ b/src/drivers/i2c/Makefile.inc @@ -4,3 +4,4 @@ subdirs-y += adt7463 subdirs-y += i2cmux subdirs-y += i2cmux2 subdirs-y += lm63 +subdirs-y += w83795 diff --git a/src/drivers/i2c/w83795/Kconfig b/src/drivers/i2c/w83795/Kconfig new file mode 100644 index 0000000..80856e2 --- /dev/null +++ b/src/drivers/i2c/w83795/Kconfig @@ -0,0 +1,2 @@ +config DRIVERS_I2C_W83795 + bool diff --git a/src/drivers/i2c/w83795/Makefile.inc b/src/drivers/i2c/w83795/Makefile.inc new file mode 100644 index 0000000..708a170 --- /dev/null +++ b/src/drivers/i2c/w83795/Makefile.inc @@ -0,0 +1 @@ +driver-$(CONFIG_DRIVERS_I2C_W83795) += w83795.c diff --git a/src/drivers/i2c/w83795/chip.h b/src/drivers/i2c/w83795/chip.h new file mode 100644 index 0000000..2900636 --- /dev/null +++ b/src/drivers/i2c/w83795/chip.h @@ -0,0 +1,4 @@ +extern struct chip_operations drivers_i2c_w83795_ops; + +struct drivers_i2c_w83795_config { +}; diff --git a/src/drivers/i2c/w83795/w83795.c b/src/drivers/i2c/w83795/w83795.c new file mode 100644 index 0000000..cf2a97e --- /dev/null +++ b/src/drivers/i2c/w83795/w83795.c @@ -0,0 +1,276 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <arch/cpu.h> +#include <console/console.h> +#include <device/device.h> +#include "southbridge/amd/cimx/sb700/smbus.h" /*SMBUS_IO_BASE*/ +#include "w83795.h" + +static u32 w83795_set_bank(u8 bank) +{ + return do_smbus_write_byte(SMBUS_IO_BASE, W83795_DEV, W83795_REG_BANKSEL, bank); +} + +static u8 w83795_read(u16 reg) +{ + u32 ret; + + ret = w83795_set_bank(reg >> 8); + if (ret < 0) { + printk(BIOS_DEBUG, "read faild to set bank %x\n", reg >> 8); + return -1; + } + + ret = do_smbus_read_byte(SMBUS_IO_BASE, W83795_DEV, reg & 0xff); + return ret; +} + +static u8 w83795_write(u16 reg, u8 value) +{ + u32 err; + + err = w83795_set_bank(reg >> 8); + if (err < 0) { + printk(BIOS_DEBUG, "write faild to set bank %x\n", reg >> 8); + return -1; + } + + err = do_smbus_write_byte(SMBUS_IO_BASE, W83795_DEV, reg & 0xff, value); + return err; +} + +#if 0 +static void w83795_set_speed(void) +{ + +} + +static void w83795_set_ttti(void)//KR it works +{ + u32 i; + for (i = 0; i < 6; i++) { + //w83795_write(W83795_REG_TTTI(i), 0xa);//10 degree, default 40 + //w83795_write(W83795_REG_CTFS(i), 0x20);//32 degree, default 80 + } +} +#endif + +/* + * Enable Digital Temperature Sensor + */ +static void w83795_dts_enable(u8 dts_src) +{ + u8 val; + + /* DIS */ + val = w83795_read(W83795_REG_DTSC); + val |= (dts_src & 0x01); + w83795_write(W83795_REG_DTSC, val); + + /* DTSE */ + val = w83795_read(W83795_REG_DTSE); + val |= 0xFF; + w83795_write(W83795_REG_DTSE, val); + + /* store bank3 regs first before enable DTS */ + + /* + * TD/TR1-4 termal diode by default + * 0x00 Disable + * 0x01 thermistors on motherboard + * 0x10 different mode voltage + * 0x11 CPU internal thermal diode output + * + * TR5-6 thermistors by default TRn + */ + val = 0x55; /* thermal diode */ + w83795_write(W83795_REG_TEMP_CTRL2, val); + + /* Enable Digital Temperature Sensor */ + val = w83795_read(W83795_REG_TEMP_CTRL1); + val |= W83795_REG_TEMP_CTRL1_EN_DTS; /* EN_DTS */ + w83795_write(W83795_REG_TEMP_CTRL1, val); +} + +static void w83795_set_tfmr(w83795_fan_mode_t mode) +{ + u8 val; + u8 i; + + if ((mode == SMART_FAN_MODE) || (mode == THERMAL_CRUISE_MODE)) { + val = 0xFF; + } else { + val = 0x00; + } + + for (i = 0; i < 6; i++) + w83795_write(W83795_REG_TFMR(i), val); +} + +static u32 w83795_set_fan_mode(w83795_fan_mode_t mode) +{ + if (mode == SPEED_CRUISE_MODE) { + w83795_write(W83795_REG_FCMS1, 0xFF); + printk(BIOS_INFO, "W83795G/ADG work in Speed Cruise Mode\n"); + } else { + w83795_write(W83795_REG_FCMS1, 0x00); + if (mode == THERMAL_CRUISE_MODE) { + w83795_write(W83795_REG_FCMS2, 0x00); + printk(BIOS_INFO, "W83795G/ADG work in Thermal Cruise Mode\n"); + } else if (mode == SMART_FAN_MODE) { + w83795_write(W83795_REG_FCMS2, 0x3F); + printk(BIOS_INFO, "W83795G/ADG work in Smart Fan Mode\n"); + } else { + printk(BIOS_INFO, "W83795G/ADG work in Manual Mode\n"); + return -1; + } + } + + return 0; +} + +static void w83795_set_tss(void) +{ + u8 val; + + val = 0x00; + w83795_write(W83795_REG_TSS(0), val); /* Temp1, 2 */ + w83795_write(W83795_REG_TSS(1), val); /* Temp3, 4 */ + w83795_write(W83795_REG_TSS(2), val); /* Temp5, 6 */ +} + +static void w83795_set_fan(w83795_fan_mode_t mode) +{ + u8 i; + + /* select temperature sensor (TSS)*/ + w83795_set_tss(); + + /* select Temperature to Fan mapping Relationships (TFMR)*/ + w83795_set_tfmr(mode); + + /* set fan output controlled mode (FCMS)*/ + w83795_set_fan_mode(mode); + + /* Set Critical Temperature to Full Speed all fan (CTFS) */ + for (i = 0; i < 6; i++) { + w83795_write(W83795_REG_CTFS(i), 0x50); /* default 80 celsius degree */ + } + + if (mode == THERMAL_CRUISE_MODE) { + /* Set Target Temperature of Temperature Inputs (TTTI) */ + for (i = 0; i < 6; i++) { + w83795_write(W83795_REG_TTTI(i), 0x28); /* default 40 celsius degree */ + } + } else if (mode == SMART_FAN_MODE) { + /* Set the Relative Register-at SMART FAN IV Control Mode Table */ + //SFIV TODO + } + + /* Set Hystersis of Temperature (HT) */ +} + +static void w83795_init(w83795_fan_mode_t mode, u8 dts_src) +{ + u8 i; + u8 val; + + if (do_smbus_read_byte(SMBUS_IO_BASE, W83795_DEV, 0x00) < 0) { + printk(BIOS_ERR, "W83795G/ADG Nuvoton H/W Monitor not found\n"); + return; + } + val = w83795_read(W83795_REG_CONFIG); + if ((val & W83795_REG_CONFIG_CONFIG48) == 0) + printk(BIOS_INFO, "Found 64 pin W83795G Nuvoton H/W Monitor\n"); + else if ((val & W83795_REG_CONFIG_CONFIG48) == 1) + printk(BIOS_INFO, "Found 48 pin W83795ADG Nuvoton H/W Monitor\n"); + + /* Reset */ + val |= W83795_REG_CONFIG_INIT; + w83795_write(W83795_REG_CONFIG, val); + + /* Fan monitoring setting */ + val = 0xFF; /* FAN1-FAN8 */ + w83795_write(W83795_REG_FANIN_CTRL1, val); + val = 0x3F; /* FAN9-FAN14 */ + w83795_write(W83795_REG_FANIN_CTRL2, val); + + /* enable monitoring operations */ + val = w83795_read(W83795_REG_CONFIG); + val |= W83795_REG_CONFIG_START; + w83795_write(W83795_REG_CONFIG, val); + + w83795_dts_enable(dts_src); + w83795_set_fan(mode); + + printk(BIOS_INFO, "Fan CTFS(celsius) TTTI(celsius)\n"); + for (i = 0; i < 6; i++) { + val = w83795_read(W83795_REG_CTFS(i)); + printk(BIOS_INFO, " %x %d", i, val); + val = w83795_read(W83795_REG_TTTI(i)); + printk(BIOS_INFO, " %d\n", val); + } + + /* Temperature ReadOut */ + for (i = 0; i < 9; i++) { + val = w83795_read(W83795_REG_DTS(i)); + printk(BIOS_DEBUG, "DTS%x ReadOut=%x \n", i, val); + } +} + +static void w83795_hwm_init(device_t dev) +{ + struct device *cpu; + struct cpu_info *info; + + info = cpu_info(); + cpu = info->cpu; + if (!cpu) + die("CPU: missing cpu device structure"); + + if (cpu->vendor == X86_VENDOR_AMD) + w83795_init(THERMAL_CRUISE_MODE, DTS_SRC_AMD_SBTSI); + else if (cpu->vendor == X86_VENDOR_INTEL) + w83795_init(THERMAL_CRUISE_MODE, DTS_SRC_INTEL_PECI); + else + printk(BIOS_ERR, "Neither AMD nor INTEL CPU detected\n"); +} + +static void w83795_noop(device_t dummy) +{ +} + +static struct device_operations w83795_operations = { + .read_resources = w83795_noop, + .set_resources = w83795_noop, + .enable_resources = w83795_noop, + .init = w83795_hwm_init, +}; + +static void enable_dev(device_t dev) +{ + dev->ops = &w83795_operations; +} + +struct chip_operations drivers_i2c_w83795_ops = { + CHIP_NAME("Nuvoton W83795G/ADG Hardware Monitor") + .enable_dev = enable_dev, +}; diff --git a/src/drivers/i2c/w83795/w83795.h b/src/drivers/i2c/w83795/w83795.h new file mode 100644 index 0000000..de0a554 --- /dev/null +++ b/src/drivers/i2c/w83795/w83795.h @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _W83795_H_ +#define _W83795_H_ + +#define W83795_DEV 0x2F /* Host I2c Addr (strap to addr1 addr0 1 1, 0x5E) */ + +#define W83795_REG_I2C_ADDR 0xFC +#define W83795_REG_BANKSEL 0x00 +#define W83795_REG_CONFIG 0x01 +#define W83795_REG_CONFIG_START 0x01 +#define W83795_REG_CONFIG_CONFIG48 0x04 +#define W83795_REG_CONFIG_INIT 0x80 + +#define W83795_REG_TEMP_CTRL1 0x04 /* Temperature Monitoring Control Register */ +#define W83795_REG_TEMP_CTRL2 0x05 /* Temperature Monitoring Control Register */ +#define W83795_REG_FANIN_CTRL1 0x06 +#define W83795_REG_FANIN_CTRL2 0x07 +#define W83795_REG_TEMP_CTRL1_EN_DTS 0x20 /* Enable DTS (Digital Temperature Sensor) interface from INTEL PECI or AMD SB-TSI. */ +#define DTS_SRC_INTEL_PECI (0 << 0) +#define DTS_SRC_AMD_SBTSI (1 << 0) + +#define W83795_REG_TSS(n) (0x209 + (n)) /* Temperature Source Selection Register */ +#define W83795_REG_TTTI(n) (0x260 + (n)) /* tarrget temperature W83795G/ADG will try to tune the fan output to keep */ +#define W83795_REG_CTFS(n) (0x268 + (n)) /* Critical Temperature to Full Speed all fan */ +#define W83795_REG_HT(n) (0x270 + (n)) /* Hystersis of Temperature */ +#define W83795_REG_DTSC 0x301 /* Digital Temperature Sensor Configuration */ + +#define W83795_REG_DTSE 0x302 /* Digital Temperature Sensor Enable */ +#define W83795_REG_DTS(n) (0x26 + (n)) +#define W83795_REG_VRLSB 0x3C + +#define W83795_TEMP_REG_TR1 0x21 +#define W83795_TEMP_REG_TR2 0x22 +#define W83795_TEMP_REG_TR3 0x23 +#define W83795_TEMP_REG_TR4 0x24 +#define W83795_TEMP_REG_TR5 0x1F +#define W83795_TEMP_REG_TR6 0x20 + +#define W83795_REG_FCMS1 0x201 +#define W83795_REG_FCMS2 0x208 +#define W83795_REG_TFMR(n) (0x202 + (n)) /*temperature to fam mappig*/ +#define W83795_REG_DFSP 0x20C + +#define W83795_REG_FTSH(n) (0x240 + (n) * 2) +#define W83795_REG_FTSL(n) (0x241 + (n) * 2) +#define W83795_REG_TFTS 0x250 + +typedef enum w83795_fan_mode { + SPEED_CRUISE_MODE, ///< Fan Speed Cruise mode keeps the fan speed in a specified range + THERMAL_CRUISE_MODE, ///< Thermal Cruise mode is an algorithm to control the fan speed to keep the temperature source around the TTTI + SMART_FAN_MODE, ///< Smart Fan mode offers 6 slopes to control the fan speed + MANUAL_MODE, ///< control manually +} w83795_fan_mode_t; + +#endif diff --git a/src/mainboard/supermicro/h8qgi/Kconfig b/src/mainboard/supermicro/h8qgi/Kconfig index 201df45..31b16b6 100644 --- a/src/mainboard/supermicro/h8qgi/Kconfig +++ b/src/mainboard/supermicro/h8qgi/Kconfig @@ -30,6 +30,7 @@ config BOARD_SPECIFIC_OPTIONS select SOUTHBRIDGE_AMD_CIMX_SB700 select SUPERIO_WINBOND_W83627DHG select SUPERIO_NUVOTON_WPCM450 + select DRIVERS_I2C_W83795 select UDELAY_TSC select BOARD_HAS_FADT select HAVE_BUS_CONFIG diff --git a/src/mainboard/supermicro/h8qgi/devicetree.cb b/src/mainboard/supermicro/h8qgi/devicetree.cb index 9d77a73..8ecf968 100644 --- a/src/mainboard/supermicro/h8qgi/devicetree.cb +++ b/src/mainboard/supermicro/h8qgi/devicetree.cb @@ -84,8 +84,8 @@ chip northbridge/amd/agesa/family15/root_complex irq 0x70 = 0x01 #keyboard irq 0x72 = 0x0C #mouse end - #device pnp 2e.6 off # SPI - #end + device pnp 2e.6 off # SPI + end device pnp 2e.307 off # GPIO6 end device pnp 2e.8 off # WDTO#, PLED @@ -106,6 +106,10 @@ chip northbridge/amd/agesa/family15/root_complex device pnp 2e.c off # PECI, SST end end #superio/winbond/w83627dhg + chip drivers/i2c/w83795 + device pnp 5e on #hwm + end + end #drivers/i2c/w83795 end # LPC device pci 14.4 on end # PCI 0x4384 device pci 14.5 on end # USB 3 diff --git a/src/mainboard/supermicro/h8qgi/romstage.c b/src/mainboard/supermicro/h8qgi/romstage.c index 119593e..77bf144 100644 --- a/src/mainboard/supermicro/h8qgi/romstage.c +++ b/src/mainboard/supermicro/h8qgi/romstage.c @@ -119,6 +119,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } post_code(0x3C); + /* W83627DHG pin89,90 function select is RSTOUT3#, RSTOUT2# by default. + * In order to access W83795G/ADG HWM using I2C protocol, + * we select function to SDA, SCL function (or GP33, GP32 function). + */ + w83627dhg_enable_i2c(PNP_DEV(0x2E, W83627DHG_SPI)); + nb_Ht_Init(); post_code(0x3D); /* Reset for HT, FIDVID, PLL and ucode patch(errata) changes to take affect. */

1 0

Patch set updated for coreboot: f301c1b Mainboard: Supermicro/h8qgi mainboard update
by Kerry Sheh 01 Feb '12

01 Feb '12

Kerry Sheh (shekairui(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/567 -gerrit commit f301c1ba962ca7f87190ae10d1af654583e4cf39 Author: Kerry Sheh <shekairui(a)gmail.com> Date: Wed Feb 1 16:05:47 2012 +0800 Mainboard: Supermicro/h8qgi mainboard update 1. Supermicro H8QGI mainboard update to support both family10 Revison D processor and family15 model 00-0fh processor in one binary image. 2. RD890/SR56X0 IO hub CIMX wrapper support. 3. SP5100/SB700 southbridge CIMX wrapper support. Both 8 cores and 16 Cores InterLagos Opteron Processor are tested on this platform. Debian Linux 5.0 and Windows Server 2008 R2 Statdard are tested. Change-Id: Iaad8c9b08310813441188deee6797b3f6dd37d6d Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> --- src/mainboard/supermicro/h8qgi/BiosCallOuts.c | 2 +- src/mainboard/supermicro/h8qgi/BiosCallOuts.h | 2 +- src/mainboard/supermicro/h8qgi/Kconfig | 20 +- src/mainboard/supermicro/h8qgi/Makefile.inc | 18 ++- src/mainboard/supermicro/h8qgi/OptionsIds.h | 2 +- src/mainboard/supermicro/h8qgi/acpi/cpstate.asl | 2 +- src/mainboard/supermicro/h8qgi/acpi/ide.asl | 2 +- src/mainboard/supermicro/h8qgi/acpi/routing.asl | 2 +- src/mainboard/supermicro/h8qgi/acpi/sata.asl | 2 +- src/mainboard/supermicro/h8qgi/acpi/usb.asl | 2 +- src/mainboard/supermicro/h8qgi/acpi_tables.c | 95 +++++--- src/mainboard/supermicro/h8qgi/agesawrapper.c | 147 ++++++++----- src/mainboard/supermicro/h8qgi/agesawrapper.h | 2 +- src/mainboard/supermicro/h8qgi/buildOpts.c | 124 +++++++++-- src/mainboard/supermicro/h8qgi/chip.h | 2 +- src/mainboard/supermicro/h8qgi/cmos.layout | 2 +- src/mainboard/supermicro/h8qgi/devicetree.cb | 86 ++------ src/mainboard/supermicro/h8qgi/dimmSpd.c | 85 ++++---- src/mainboard/supermicro/h8qgi/dsdt.asl | 217 +++++++----------- src/mainboard/supermicro/h8qgi/fadt.c | 61 ++---- src/mainboard/supermicro/h8qgi/get_bus_conf.c | 30 +-- src/mainboard/supermicro/h8qgi/irq_tables.c | 8 +- src/mainboard/supermicro/h8qgi/mainboard.c | 40 +++-- src/mainboard/supermicro/h8qgi/mptable.c | 59 +++--- src/mainboard/supermicro/h8qgi/platform_cfg.h | 54 +++++ src/mainboard/supermicro/h8qgi/platform_oem.c | 4 +- src/mainboard/supermicro/h8qgi/platform_oem.h | 29 --- src/mainboard/supermicro/h8qgi/rd890_cfg.c | 274 +++++++++++++++++++++++ src/mainboard/supermicro/h8qgi/rd890_cfg.h | 174 ++++++++++++++ src/mainboard/supermicro/h8qgi/reset.c | 66 ++++++ src/mainboard/supermicro/h8qgi/romstage.c | 79 +++++-- src/mainboard/supermicro/h8qgi/sb700_cfg.c | 142 ++++++++++++ src/mainboard/supermicro/h8qgi/sb700_cfg.h | 237 ++++++++++++++++++++ 33 files changed, 1524 insertions(+), 547 deletions(-) diff --git a/src/mainboard/supermicro/h8qgi/BiosCallOuts.c b/src/mainboard/supermicro/h8qgi/BiosCallOuts.c index b7f0124..e83d1f0 100644 --- a/src/mainboard/supermicro/h8qgi/BiosCallOuts.c +++ b/src/mainboard/supermicro/h8qgi/BiosCallOuts.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/supermicro/h8qgi/BiosCallOuts.h b/src/mainboard/supermicro/h8qgi/BiosCallOuts.h index 24a05fb..aa2d451 100644 --- a/src/mainboard/supermicro/h8qgi/BiosCallOuts.h +++ b/src/mainboard/supermicro/h8qgi/BiosCallOuts.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/supermicro/h8qgi/Kconfig b/src/mainboard/supermicro/h8qgi/Kconfig old mode 100755 new mode 100644 index 5df0bb4..e900ea8 --- a/src/mainboard/supermicro/h8qgi/Kconfig +++ b/src/mainboard/supermicro/h8qgi/Kconfig @@ -1,7 +1,7 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. +# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -22,13 +22,15 @@ if BOARD_SUPERMICRO_H8QGI config BOARD_SPECIFIC_OPTIONS def_bool y select ARCH_X86 - select CPU_AMD_AGESA_FAMILY10 - select NORTHBRIDGE_AMD_AGESA_FAMILY10_ROOT_COMPLEX - select NORTHBRIDGE_AMD_AGESA_FAMILY10 - select SOUTHBRIDGE_AMD_SR5650 - select SOUTHBRIDGE_AMD_SP5100 + select CPU_AMD_AGESA_FAMILY15 + select CPU_AMD_SOCKET_G34 + select NORTHBRIDGE_AMD_AGESA_FAMILY15_ROOT_COMPLEX + select NORTHBRIDGE_AMD_AGESA_FAMILY15 + select NORTHBRIDGE_AMD_CIMX_RD890 + select SOUTHBRIDGE_AMD_CIMX_SB700 select SUPERIO_WINBOND_W83627DHG select SUPERIO_NUVOTON_WPCM450 + select UDELAY_TSC select BOARD_HAS_FADT select HAVE_BUS_CONFIG select HAVE_OPTION_TABLE @@ -36,15 +38,11 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_MP_TABLE select HAVE_HARD_RESET select SERIAL_CPU_INIT - select AMDMCT select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_2048 + select TINY_BOOTBLOCK #select MMCONF_SUPPORT_DEFAULT #TODO enable it to resolve Multicore IO conflict -config AMD_AGESA - bool - default y - config MAINBOARD_DIR string default supermicro/h8qgi diff --git a/src/mainboard/supermicro/h8qgi/Makefile.inc b/src/mainboard/supermicro/h8qgi/Makefile.inc old mode 100755 new mode 100644 index b09c5ca..82264a4 --- a/src/mainboard/supermicro/h8qgi/Makefile.inc +++ b/src/mainboard/supermicro/h8qgi/Makefile.inc @@ -1,7 +1,7 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. +# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -17,15 +17,31 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # +romstage-$(CONFIG_NORTHBRIDGE_AMD_CIMX_RD890) += rd890_cfg.c +romstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += sb700_cfg.c +romstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += reset.c romstage-y += buildOpts.c romstage-y += agesawrapper.c romstage-y += dimmSpd.c romstage-y += BiosCallOuts.c romstage-y += platform_oem.c +ramstage-$(CONFIG_NORTHBRIDGE_AMD_CIMX_RD890) += rd890_cfg.c +ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += sb700_cfg.c +ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += reset.c ramstage-y += buildOpts.c ramstage-y += agesawrapper.c ramstage-y += dimmSpd.c ramstage-y += BiosCallOuts.c ramstage-y += platform_oem.c +AGESA_PREFIX ?= $(src)/vendorcode/amd/agesa +CIMX_PREFIX ?= $(src)/vendorcode/amd/cimx +AGESA_ROOT ?= $(AGESA_PREFIX)/f15 +NB_CIMX_ROOT ?= $(CIMX_PREFIX)/rd890 +SB_CIMX_ROOT ?= $(CIMX_PREFIX)/sb700 + +subdirs-y += ../../../../$(AGESA_ROOT) +#subdirs-y += ../../../../$(NB_CIMX_ROOT) +#subdirs-y += ../../../../$(SB_CIMX_ROOT) + diff --git a/src/mainboard/supermicro/h8qgi/OptionsIds.h b/src/mainboard/supermicro/h8qgi/OptionsIds.h index eb756df..c4441e9 100644 --- a/src/mainboard/supermicro/h8qgi/OptionsIds.h +++ b/src/mainboard/supermicro/h8qgi/OptionsIds.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/supermicro/h8qgi/acpi/cpstate.asl b/src/mainboard/supermicro/h8qgi/acpi/cpstate.asl old mode 100755 new mode 100644 index 5eca9cc..2cb7aeb --- a/src/mainboard/supermicro/h8qgi/acpi/cpstate.asl +++ b/src/mainboard/supermicro/h8qgi/acpi/cpstate.asl @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/supermicro/h8qgi/acpi/ide.asl b/src/mainboard/supermicro/h8qgi/acpi/ide.asl old mode 100755 new mode 100644 index c79c18c..45303c0 --- a/src/mainboard/supermicro/h8qgi/acpi/ide.asl +++ b/src/mainboard/supermicro/h8qgi/acpi/ide.asl @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/supermicro/h8qgi/acpi/routing.asl b/src/mainboard/supermicro/h8qgi/acpi/routing.asl old mode 100755 new mode 100644 index 8bc06f6..817f0f7 --- a/src/mainboard/supermicro/h8qgi/acpi/routing.asl +++ b/src/mainboard/supermicro/h8qgi/acpi/routing.asl @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/supermicro/h8qgi/acpi/sata.asl b/src/mainboard/supermicro/h8qgi/acpi/sata.asl old mode 100755 new mode 100644 index bd4acf0..9ce8650 --- a/src/mainboard/supermicro/h8qgi/acpi/sata.asl +++ b/src/mainboard/supermicro/h8qgi/acpi/sata.asl @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/supermicro/h8qgi/acpi/usb.asl b/src/mainboard/supermicro/h8qgi/acpi/usb.asl old mode 100755 new mode 100644 index 81ea9a2..099e7ac --- a/src/mainboard/supermicro/h8qgi/acpi/usb.asl +++ b/src/mainboard/supermicro/h8qgi/acpi/usb.asl @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/supermicro/h8qgi/acpi_tables.c b/src/mainboard/supermicro/h8qgi/acpi_tables.c index b8ce0b0..7314283 100644 --- a/src/mainboard/supermicro/h8qgi/acpi_tables.c +++ b/src/mainboard/supermicro/h8qgi/acpi_tables.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -20,6 +20,7 @@ #include <console/console.h> #include <string.h> #include <arch/acpi.h> +#include <arch/acpigen.h> #include <arch/ioapic.h> #include <arch/io.h> #include <device/pci.h> @@ -48,7 +49,6 @@ static void dump_mem(u32 start, u32 end) #endif extern const unsigned char AmlCode[]; -extern const unsigned char AmlCode_ssdt[]; unsigned long acpi_fill_mcfg(unsigned long current) @@ -77,7 +77,7 @@ unsigned long acpi_fill_madt(unsigned long current) #else apicid_sp5100 = CONFIG_MAX_CPUS + 1 #endif - apicid_sr5650 = apicid_sp5100 + 1; + apicid_sr5650 = apicid_sp5100 + 1; /* create all subtables for processors */ current = acpi_create_madt_lapics(current); @@ -89,18 +89,18 @@ unsigned long acpi_fill_madt(unsigned long current) 0 ); - /* IOAPIC on rs5690 */ - gsi_base += IO_APIC_INTERRUPTS; /* SP5100 has 24 IOAPIC entries. */ - dev = dev_find_slot(0, PCI_DEVFN(0, 0)); - if (dev) { - pci_write_config32(dev, 0xF8, 0x1); - dword = pci_read_config32(dev, 0xFC) & 0xfffffff0; + /* IOAPIC on rs5690 */ + gsi_base += IO_APIC_INTERRUPTS; /* SP5100 has 24 IOAPIC entries. */ + dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + if (dev) { + pci_write_config32(dev, 0xF8, 0x1); + dword = pci_read_config32(dev, 0xFC) & 0xfffffff0; current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, apicid_sr5650, dword, gsi_base ); - } + } current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, //BUS @@ -134,6 +134,29 @@ unsigned long acpi_fill_srat(unsigned long current) return current; } +unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) +{ + int lens; + msr_t msr; + char pscope[] = "\\_SB.PCI0"; + + lens = acpigen_write_scope(pscope); + msr = rdmsr(TOP_MEM); + lens += acpigen_write_name_dword("TOM1", msr.lo); + msr = rdmsr(TOP_MEM2); + /* + * Since XP only implements parts of ACPI 2.0, we can't use a qword + * here. + * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt + * slide 22ff. + * Shift value right by 20 bit to make it fit into 32bit, + * giving us 1MB granularity and a limit of almost 4Exabyte of memory. + */ + lens += acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20); + acpigen_patch_len(lens - 1); + return (unsigned long) (acpigen_get_current()); +} + unsigned long write_acpi_tables(unsigned long start) { unsigned long current; @@ -146,7 +169,9 @@ unsigned long write_acpi_tables(unsigned long start) acpi_fadt_t *fadt; acpi_facs_t *facs; acpi_header_t *dsdt; - //acpi_header_t *ssdt; + acpi_header_t *ssdt; + acpi_header_t *ssdt2; + acpi_header_t *alib; get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ @@ -234,38 +259,38 @@ unsigned long write_acpi_tables(unsigned long start) } /* SSDT */ - /* NOTE: we not update_ssdt, so ssdt only contain initialize value from ssdt.asl */ -#ifdef UNUSED_CODE - current = ( current + 0x0f) & -0x10; - printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); - ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); - if (ssdt != NULL) { - memcpy(current, ssdt, ssdt->length); + current = (current + 0x0f) & -0x10; + printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current); + alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); + if (alib != NULL) { + memcpy((void *)current, alib, alib->length); ssdt = (acpi_header_t *) current; - current += ssdt->length; + current += alib->length; + acpi_add_table(rsdp,alib); + } else { + printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); } - else { + +#if 0 // The DSDT needs additional work for the AGESA SSDT Pstate table + current = ( current + 0x0f) & -0x10; + printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current); + ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); + if (ssdt != NULL) { + memcpy((void *)current, ssdt, ssdt->length); ssdt = (acpi_header_t *) current; - memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t)); current += ssdt->length; - memcpy(ssdt, &AmlCode_ssdt, ssdt->length); - /* recalculate checksum */ - ssdt->checksum = 0; - ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length); + } else { + printk(BIOS_DEBUG, " AGESA SSDT table NULL. Skipping.\n"); } acpi_add_table(rsdp,ssdt); - - printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); #endif - /* DSDT */ - current = ( current + 0x07) & -0x08; - printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current); - dsdt = (acpi_header_t *)current; // it will used by fadt - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - current += dsdt->length; - memcpy(dsdt, &AmlCode, dsdt->length); - printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); + current = ( current + 0x0f) & -0x10; + printk(BIOS_DEBUG, "ACPI: * coreboot TOM SSDT2 at %lx\n", current); + ssdt2 = (acpi_header_t *) current; + acpi_create_ssdt_generator(ssdt2, ACPI_TABLE_CREATOR); + current += ssdt2->length; + acpi_add_table(rsdp,ssdt2); #if DUMP_ACPI_TABLES == 1 printk(BIOS_DEBUG, "rsdp\n"); diff --git a/src/mainboard/supermicro/h8qgi/agesawrapper.c b/src/mainboard/supermicro/h8qgi/agesawrapper.c index 5bb4a9d..dbdd9d7 100644 --- a/src/mainboard/supermicro/h8qgi/agesawrapper.c +++ b/src/mainboard/supermicro/h8qgi/agesawrapper.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -34,7 +34,6 @@ #include "Dispatcher.h" #include "cpuCacheInit.h" #include "amdlib.h" -#include "platform_oem.h" #include "Filecode.h" #include "heapManager.h" #include <cpuFamilyTranslation.h> /* CPU_SPECIFIC_SERVICES */ @@ -54,7 +53,7 @@ VOID *AcpiSlit = NULL; VOID *AcpiWheaMce = NULL; VOID *AcpiWheaCmc = NULL; -//VOID *AcpiAlib = NULL; +VOID *AcpiAlib = NULL; /*---------------------------------------------------------------------------------------- @@ -76,6 +75,7 @@ VOID *AcpiWheaCmc = NULL; * L O C A L F U N C T I O N S *--------------------------------------------------------------------------------------- */ +extern VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly); static UINT32 agesawrapper_amdinitcpuio(VOID) { @@ -87,6 +87,7 @@ static UINT32 agesawrapper_amdinitcpuio(VOID) UINT32 node; UINT32 sblink; UINT32 i; + UINT32 TOM; /* get the number of coherent nodes in the system */ PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x60); @@ -130,12 +131,13 @@ static UINT32 agesawrapper_amdinitcpuio(VOID) PciData = 0x00000A03; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - /* Set F0000000-FFFFFFFF to Node0 sbLink. */ + /* Set TOM1-FFFFFFFF to Node0 sbLink. */ PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x8C); PciData = 0x00FFFF00; PciData |= sblink << 4; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciData = 0x00F00000 | 0x03; + TOM = (UINT32)MsrRead(TOP_MEM); + PciData = (TOM >> 8) | 0x03; PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x88); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); @@ -155,13 +157,13 @@ static UINT32 agesawrapper_amdinitcpuio(VOID) LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - /* Start to set IO 0x9000-0xEFFF to Node0 sbLink with ISA&VGA set. */ + /* Set PCIO: 0x0 - 0xFFF000 to Node0 sbLink and enabled VGA IO*/ PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC4); - PciData = 0x0000E000; + PciData = 0x00FFF000; PciData |= sblink << 4; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC0); - PciData = 0x00009033; + PciData = 0x00000033; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); } @@ -190,9 +192,9 @@ UINT32 agesawrapper_amdinitmmio(VOID) LibAmdMsrWrite(0xC001001F, &MsrReg, &StdHeader); /* Set ROM cache onto WP to decrease post time */ - MsrReg = (0x0100000000ull - CONFIG_ROM_SIZE) | 5; + MsrReg = (0x0100000000 - CONFIG_ROM_SIZE) | 5; LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); - MsrReg = (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800; + MsrReg = (0x1000000000 - CONFIG_ROM_SIZE) | 0x800; LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader); Status = AGESA_SUCCESS; @@ -223,7 +225,10 @@ UINT32 agesawrapper_amdinitreset(VOID) AmdParamStruct.StdHeader.CalloutPtr = NULL; AmdParamStruct.StdHeader.Func = 0; AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct(&AmdParamStruct); + status = AmdCreateStruct(&AmdParamStruct); + if (status != AGESA_SUCCESS) { + return (UINT32)status; + } AmdResetParams.HtConfig.Depth = 0; //MARG34PI disabled AGESA_ENTRY_INIT_RESET by default @@ -257,16 +262,19 @@ UINT32 agesawrapper_amdinitearly(VOID) AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; AmdParamStruct.StdHeader.Func = 0; AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct(&AmdParamStruct); + status = AmdCreateStruct(&AmdParamStruct); + if (status != AGESA_SUCCESS) { + return (UINT32)status; + } AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr; OemCustomizeInitEarly(AmdEarlyParamsPtr); - status = AmdInitEarly((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr); + status = AmdInitEarly(AmdEarlyParamsPtr); if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); - GetCpuServicesOfCurrentCore(&FamilySpecificServices, &AmdParamStruct.StdHeader); + GetCpuServicesOfCurrentCore((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &AmdParamStruct.StdHeader); FamilySpecificServices->GetTscRate(FamilySpecificServices, &TscRateInMhz, &AmdParamStruct.StdHeader); printk(BIOS_DEBUG, "BSP Frequency: %luMHz\n", TscRateInMhz); @@ -280,6 +288,7 @@ UINT32 agesawrapper_amdinitpost(VOID) UINT16 i; UINT32 *HeadPtr; AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_POST_PARAMS *PostParams; BIOS_HEAP_MANAGER *BiosManagerPtr; UINT32 TscRateInMhz; CPU_SPECIFIC_SERVICES *FamilySpecificServices; @@ -296,10 +305,15 @@ UINT32 agesawrapper_amdinitpost(VOID) AmdParamStruct.StdHeader.Func = 0; AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct(&AmdParamStruct); - status = AmdInitPost((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) - agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); + status = AmdCreateStruct(&AmdParamStruct); + if (status != AGESA_SUCCESS) { + return (UINT32)status; + } + PostParams = (AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr; + status = AmdInitPost(PostParams); + if (status != AGESA_SUCCESS) { + agesawrapper_amdreadeventlog(PostParams->StdHeader.HeapStatus); + } AmdReleaseStruct(&AmdParamStruct); /* Initialize heap space */ @@ -313,7 +327,7 @@ UINT32 agesawrapper_amdinitpost(VOID) BiosManagerPtr->StartOfAllocatedNodes = 0; BiosManagerPtr->StartOfFreedNodes = 0; - GetCpuServicesOfCurrentCore (&FamilySpecificServices, &AmdParamStruct.StdHeader); + GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &AmdParamStruct.StdHeader); FamilySpecificServices->GetTscRate (FamilySpecificServices, &TscRateInMhz, &AmdParamStruct.StdHeader); printk(BIOS_DEBUG, "BSP Frequency: %luMHz\n", TscRateInMhz); @@ -324,6 +338,7 @@ UINT32 agesawrapper_amdinitenv(VOID) { AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_ENV_PARAMS *EnvParams; LibAmdMemFill(&AmdParamStruct, 0, @@ -336,10 +351,15 @@ UINT32 agesawrapper_amdinitenv(VOID) AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; AmdParamStruct.StdHeader.Func = 0; AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct(&AmdParamStruct); - status = AmdInitEnv((AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr); + + status = AmdCreateStruct(&AmdParamStruct); + if (status != AGESA_SUCCESS) { + return (UINT32)status; + } + EnvParams = (AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr; + status = AmdInitEnv(EnvParams); if (status != AGESA_SUCCESS) - agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); + agesawrapper_amdreadeventlog(EnvParams->StdHeader.HeapStatus); AmdReleaseStruct(&AmdParamStruct); return (UINT32)status; @@ -363,10 +383,8 @@ VOID * agesawrapper_getlateinitptr(int pick) return AcpiWheaMce; case PICK_WHEA_CMC: return AcpiWheaCmc; -/* case PICK_ALIB: return AcpiAlib; -*/ default: return NULL; } @@ -394,7 +412,10 @@ UINT32 agesawrapper_amdinitmid(VOID) AmdParamStruct.StdHeader.Func = 0; AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct(&AmdParamStruct); + status = AmdCreateStruct(&AmdParamStruct); + if (status != AGESA_SUCCESS) { + return (UINT32)status; + } status = AmdInitMid((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr); if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); @@ -405,34 +426,49 @@ UINT32 agesawrapper_amdinitmid(VOID) UINT32 agesawrapper_amdinitlate(VOID) { - AGESA_STATUS Status; - AMD_LATE_PARAMS AmdLateParams; + AGESA_STATUS Status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_LATE_PARAMS *AmdLateParamsPtr; - LibAmdMemFill(&AmdLateParams, - 0, - sizeof(AMD_LATE_PARAMS), - &(AmdLateParams.StdHeader)); + LibAmdMemFill(&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); - AmdLateParams.StdHeader.AltImageBasePtr = 0; - AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdLateParams.StdHeader.Func = 0; - AmdLateParams.StdHeader.ImageBasePtr = 0; - AmdLateParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; + AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; - Status = AmdInitLate(&AmdLateParams); + AmdCreateStruct (&AmdParamStruct); + AmdLateParamsPtr = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr; + + printk(BIOS_DEBUG, "agesawrapper_amdinitlate: AmdLateParamsPtr = %X\n", (u32)AmdLateParamsPtr); + + Status = AmdInitLate(AmdLateParamsPtr); if (Status != AGESA_SUCCESS) { - agesawrapper_amdreadeventlog(AmdLateParams.StdHeader.HeapStatus); + agesawrapper_amdreadeventlog(AmdLateParamsPtr->StdHeader.HeapStatus); ASSERT(Status == AGESA_SUCCESS); } - - DmiTable = AmdLateParams.DmiTable; - AcpiPstate = AmdLateParams.AcpiPState; - AcpiSrat = AmdLateParams.AcpiSrat; - AcpiSlit = AmdLateParams.AcpiSlit; - - AcpiWheaMce = AmdLateParams.AcpiWheaMce; - AcpiWheaCmc = AmdLateParams.AcpiWheaCmc; - //AcpiAlib = AmdLateParams.AcpiAlib; + DmiTable = AmdLateParamsPtr->DmiTable; + AcpiPstate = AmdLateParamsPtr->AcpiPState; + AcpiSrat = AmdLateParamsPtr->AcpiSrat; + AcpiSlit = AmdLateParamsPtr->AcpiSlit; + AcpiWheaMce = AmdLateParamsPtr->AcpiWheaMce; + AcpiWheaCmc = AmdLateParamsPtr->AcpiWheaCmc; + AcpiAlib = AmdLateParamsPtr->AcpiAlib; + + printk(BIOS_DEBUG, "In %s, AGESA generated ACPI tables:\n" + " DmiTable:%p\n AcpiPstate: %p\n AcpiSrat:%p\n AcpiSlit:%p\n" + " Mce:%p\n Cmc:%p\n Alib:%p\n", + __func__, DmiTable, AcpiPstate, AcpiSrat, AcpiSlit, + AcpiWheaMce, AcpiWheaCmc, AcpiAlib); + + /* Don't release the structure until coreboot has copied the ACPI tables. + * AmdReleaseStruct (&AmdLateParams); + */ return (UINT32)Status; } @@ -464,15 +500,6 @@ UINT32 agesawrapper_amdlaterunaptask(UINT32 Data, VOID *ConfigPtr) ASSERT(Status <= AGESA_UNSUPPORTED); } - DmiTable = AmdLateParams.DmiTable; - AcpiPstate = AmdLateParams.AcpiPState; - AcpiSrat = AmdLateParams.AcpiSrat; - AcpiSlit = AmdLateParams.AcpiSlit; - - AcpiWheaMce = AmdLateParams.AcpiWheaMce; - AcpiWheaCmc = AmdLateParams.AcpiWheaCmc; - // AcpiAlib = AmdLateParams.AcpiAlib; - return (UINT32)Status; } @@ -784,9 +811,9 @@ static void agesa_error(EVENT_PARAMS *event) printk(BIOS_DEBUG, "Small DQS Position window for WR DQS\n"); break; - case MEM_ERROR_ECC_DIS: - printk(BIOS_DEBUG, "ECC has been disabled as a result of an internal issue\n"); - break; +// case MEM_ERROR_ECC_DIS: +// printk(BIOS_DEBUG, "ECC has been disabled as a result of an internal issue\n"); +// break; case MEM_ERROR_DIMM_SPARING_NOT_ENABLED: printk(BIOS_DEBUG, "DIMM sparing has not been enabled for an internal issues\n"); @@ -1141,6 +1168,7 @@ static void interpret_agesa_eventlog(EVENT_PARAMS *event) */ UINT32 agesawrapper_amdreadeventlog(UINT8 HeapStatus) { + printk(BIOS_DEBUG, "enter in %s\n", __func__); AGESA_STATUS Status; EVENT_PARAMS AmdEventParams; @@ -1164,6 +1192,7 @@ UINT32 agesawrapper_amdreadeventlog(UINT8 HeapStatus) Status = AmdReadEventLog(&AmdEventParams); } + printk(BIOS_DEBUG, "exit %s \n", __func__); return (UINT32)Status; } diff --git a/src/mainboard/supermicro/h8qgi/agesawrapper.h b/src/mainboard/supermicro/h8qgi/agesawrapper.h index 43c7d10..c1eb012 100644 --- a/src/mainboard/supermicro/h8qgi/agesawrapper.h +++ b/src/mainboard/supermicro/h8qgi/agesawrapper.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/supermicro/h8qgi/buildOpts.c b/src/mainboard/supermicro/h8qgi/buildOpts.c index 02cf79b..480c7b6 100644 --- a/src/mainboard/supermicro/h8qgi/buildOpts.c +++ b/src/mainboard/supermicro/h8qgi/buildOpts.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -70,7 +70,10 @@ ////#define BLDOPT_REMOVE_SLIT TRUE //#define BLDOPT_REMOVE_WHEA TRUE //#define BLDOPT_REMOVE_DMI TRUE -//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE + +/*f15 Rev A1 ucode patch CpuF15OrMicrocodePatch0600011F */ +#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE + //#define BLDOPT_REMOVE_HT_ASSIST TRUE //#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE //#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE @@ -107,7 +110,7 @@ #define BLDCFG_ONLINE_SPARE FALSE #define BLDCFG_BANK_SWIZZLE TRUE #define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO -#define BLDCFG_MEMORY_CLOCK_SELECT DDR800_FREQUENCY +#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY //DDR800_FREQUENCY #define BLDCFG_DQS_TRAINING_CONTROL TRUE #define BLDCFG_IGNORE_SPD_CHECKSUM FALSE #define BLDCFG_USE_BURST_MODE FALSE @@ -297,6 +300,27 @@ CONST CPU_HT_DEEMPHASIS_LEVEL ROMDATA h8qgi_deemphasis_list[] = {0, 2, HT_FREQUENCY_2400M, HT_FREQUENCY_2400M, DeemphasisLevelMinus8, DcvLevelMinus7}, {0, 2, HT_FREQUENCY_2600M, HT_FREQUENCY_2600M, DeemphasisLevelMinus11pre8, DcvLevelMinus9}, + {1, 2, HT3_FREQUENCY_MIN, HT_FREQUENCY_1600M, DeemphasisLevelNone, DcvLevelNone}, + {1, 2, HT_FREQUENCY_1800M, HT_FREQUENCY_1800M, DeemphasisLevelMinus3, DcvLevelMinus5}, + {1, 2, HT_FREQUENCY_2000M, HT_FREQUENCY_2000M, DeemphasisLevelMinus6, DcvLevelMinus5}, + {1, 2, HT_FREQUENCY_2200M, HT_FREQUENCY_2200M, DeemphasisLevelMinus6, DcvLevelMinus7}, + {1, 2, HT_FREQUENCY_2400M, HT_FREQUENCY_2400M, DeemphasisLevelMinus8, DcvLevelMinus7}, + {1, 2, HT_FREQUENCY_2600M, HT_FREQUENCY_2600M, DeemphasisLevelMinus11pre8, DcvLevelMinus9}, + + {2, 0, HT3_FREQUENCY_MIN, HT_FREQUENCY_1600M, DeemphasisLevelNone, DcvLevelNone}, + {2, 0, HT_FREQUENCY_1800M, HT_FREQUENCY_1800M, DeemphasisLevelMinus3, DcvLevelMinus5}, + {2, 0, HT_FREQUENCY_2000M, HT_FREQUENCY_2000M, DeemphasisLevelMinus6, DcvLevelMinus5}, + {2, 0, HT_FREQUENCY_2200M, HT_FREQUENCY_2200M, DeemphasisLevelMinus6, DcvLevelMinus7}, + {2, 0, HT_FREQUENCY_2400M, HT_FREQUENCY_2400M, DeemphasisLevelMinus8, DcvLevelMinus7}, + {2, 0, HT_FREQUENCY_2600M, HT_FREQUENCY_2600M, DeemphasisLevelMinus11pre8, DcvLevelMinus9}, + + {3, 0, HT3_FREQUENCY_MIN, HT_FREQUENCY_1600M, DeemphasisLevelNone, DcvLevelNone}, + {3, 0, HT_FREQUENCY_1800M, HT_FREQUENCY_1800M, DeemphasisLevelMinus3, DcvLevelMinus5}, + {3, 0, HT_FREQUENCY_2000M, HT_FREQUENCY_2000M, DeemphasisLevelMinus6, DcvLevelMinus5}, + {3, 0, HT_FREQUENCY_2200M, HT_FREQUENCY_2200M, DeemphasisLevelMinus6, DcvLevelMinus7}, + {3, 0, HT_FREQUENCY_2400M, HT_FREQUENCY_2400M, DeemphasisLevelMinus8, DcvLevelMinus7}, + {3, 0, HT_FREQUENCY_2600M, HT_FREQUENCY_2600M, DeemphasisLevelMinus11pre8, DcvLevelMinus9}, + /* Coherent link deemphasis. */ {HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT3_FREQUENCY_MIN, HT_FREQUENCY_1600M, DeemphasisLevelNone, DcvLevelNone}, {HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_1800M, HT_FREQUENCY_1800M, DeemphasisLevelMinus3, DcvLevelMinus3}, @@ -373,22 +397,21 @@ CONST SYSTEM_PHYSICAL_SOCKET_MAP ROMDATA h8qgi_socket_map[] = {HT_SOCKET3, HT_LINK1B, HT_SOCKET0}, {HT_SOCKET3, HT_LINK3A, HT_SOCKET0}, {HT_SOCKET3, HT_LINK3B, HT_SOCKET2}, - }; CONST AP_MTRR_SETTINGS ROMDATA h8qgi_ap_mtrr_list[] = { - {AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull}, - {AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull}, - {AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull}, - {AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000ull}, - {AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000ull}, - {AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000ull}, - {AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000ull}, - {AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818ull}, - {AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818ull}, - {AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818ull}, - {AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818ull}, + {AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E}, + {AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E}, + {AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000}, + {AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000}, + {AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000}, + {AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000}, + {AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000}, + {AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818}, + {AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818}, + {AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818}, + {AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818}, {CPU_LIST_TERMINAL} }; @@ -403,7 +426,7 @@ CONST AP_MTRR_SETTINGS ROMDATA h8qgi_ap_mtrr_list[] = /* Process the options... * This file include MUST occur AFTER the user option selection settings */ -#define AGESA_ENTRY_INIT_RESET FALSE//TRUE +#define AGESA_ENTRY_INIT_RESET TRUE//FALSE #define AGESA_ENTRY_INIT_RECOVERY FALSE #define AGESA_ENTRY_INIT_EARLY TRUE #define AGESA_ENTRY_INIT_POST TRUE @@ -415,7 +438,16 @@ CONST AP_MTRR_SETTINGS ROMDATA h8qgi_ap_mtrr_list[] = #define AGESA_ENTRY_INIT_LATE_RESTORE TRUE #define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE -#include "GnbInterface.h" /*prototype for GnbInterfaceStub*/ +/* +#if (CONFIG_CPU_AMD_AGESA_FAMILY15 == 1) + #define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE +#endif +#if (CONFIG_CPU_AMD_AGESA_FAMILY10 == 1) + #define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE +#endif +*/ + +//#include "GnbInterface.h" /*prototype for GnbInterfaceStub*/ #include "MaranelloInstall.h" /*---------------------------------------------------------------------------------------- @@ -423,6 +455,16 @@ CONST AP_MTRR_SETTINGS ROMDATA h8qgi_ap_mtrr_list[] = *---------------------------------------------------------------------------------------- */ +//reference BKDG Table87: works +#define F15_WL_SEED 0x3B //family15 BKDG recommand 3B RDIMM, 1A UDIMM. +#define SEED_A 0x54 +#define SEED_B 0x4D +#define SEED_C 0x45 +#define SEED_D 0x40 + +#define F10_WL_SEED 0x3B //family10 BKDG recommand 3B RDIMM, 1A UDIMM. +//4B 41 51 + /* * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable @@ -486,6 +528,53 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { // Byte6Seed, Byte7Seed, ByteEccSeed) // Specifies the write leveling seed for a channel of a socket. // +#if 0//CONFIG_CPU_AMD_AGESA_FAMILY10 + /* Specifies the write leveling seed for a channel of a socket. + * WRITE_LEVELING_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed, + * Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, + * Byte6Seed, Byte7Seed, ByteEccSeed) + */ + WRITE_LEVELING_SEED( + ANY_SOCKET, ANY_CHANNEL, F10_WL_SEED, F10_WL_SEED, + F10_WL_SEED, F10_WL_SEED, F10_WL_SEED, F10_WL_SEED, + F10_WL_SEED, F10_WL_SEED, F10_WL_SEED), +#endif + +#if 0 //CONFIG_CPU_AMD_AGESA_FAMILY15 + /* Specifies the write leveling seed for a channel of a socket. + * WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID, + * Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, + * Byte4Seed, Byte5Seed, Byte6Seed, Byte7Seed, + * ByteEccSeed) + */ + WRITE_LEVELING_SEED( + ANY_SOCKET, ANY_CHANNEL, ALL_DIMMS, + F15_WL_SEED, F15_WL_SEED, F15_WL_SEED, F15_WL_SEED, + F15_WL_SEED, F15_WL_SEED, F15_WL_SEED, F15_WL_SEED, + F15_WL_SEED), + + /* HW_RXEN_SEED(SocketID, ChannelID, DimmID, + * Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, + * Byte4Seed, Byte5Seed, Byte6Seed, Byte7Seed, ByteEccSeed) + */ + HW_RXEN_SEED( + ANY_SOCKET, CHANNEL_A, ALL_DIMMS, + SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, + SEED_A), + HW_RXEN_SEED( + ANY_SOCKET, CHANNEL_B, ALL_DIMMS, + SEED_B, SEED_B, SEED_B, SEED_B, SEED_B, SEED_B, SEED_B, SEED_B, + SEED_B), + HW_RXEN_SEED( + ANY_SOCKET, CHANNEL_C, ALL_DIMMS, + SEED_C, SEED_C, SEED_C, SEED_C, SEED_C, SEED_C, SEED_C, SEED_C, + SEED_C), + HW_RXEN_SEED( + ANY_SOCKET, CHANNEL_D, ALL_DIMMS, + SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, + SEED_D), +#endif + NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), //max 3 PSO_END }; @@ -493,7 +582,6 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { /* * These tables are optional and may be used to adjust memory timing settings */ - //HY Customer table UINT8 AGESA_MEM_TABLE_HY[][sizeof (MEM_TABLE_ALIAS)] = { diff --git a/src/mainboard/supermicro/h8qgi/chip.h b/src/mainboard/supermicro/h8qgi/chip.h index a252705..1181130 100644 --- a/src/mainboard/supermicro/h8qgi/chip.h +++ b/src/mainboard/supermicro/h8qgi/chip.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/supermicro/h8qgi/cmos.layout b/src/mainboard/supermicro/h8qgi/cmos.layout old mode 100755 new mode 100644 index 3b98cbb..0fd4708 --- a/src/mainboard/supermicro/h8qgi/cmos.layout +++ b/src/mainboard/supermicro/h8qgi/cmos.layout @@ -2,7 +2,7 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. +# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/supermicro/h8qgi/devicetree.cb b/src/mainboard/supermicro/h8qgi/devicetree.cb old mode 100755 new mode 100644 index 9afaac7..9d77a73 --- a/src/mainboard/supermicro/h8qgi/devicetree.cb +++ b/src/mainboard/supermicro/h8qgi/devicetree.cb @@ -1,7 +1,7 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. +# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -16,20 +16,18 @@ # along with this program; if not, write to the Free Software # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # -chip northbridge/amd/agesa/family10/root_complex +chip northbridge/amd/agesa/family15/root_complex device lapic_cluster 0 on - chip cpu/amd/agesa/family10 - device lapic 0x10 on end + chip cpu/amd/agesa/family15 + device lapic 0x20 on end #f15 + #device lapic 0x10 on end #f10 end end device pci_domain 0 on subsystemid 0x15d9 0xab11 inherit #SuperMicro - chip northbridge/amd/agesa/family10 # CPU side of HT root complex - device pci 18.0 on end # link 0 - device pci 18.0 on end # link 1 - device pci 18.0 on end # link 2 - device pci 18.0 on # link3 SB on socket0 link 2, on internal Node0 Link 3 - chip southbridge/amd/sr5650 # Southbridge PCI side of HT Root complex + chip northbridge/amd/agesa/family15 # CPU side of HT root complex + device pci 18.0 on # Put IO-HUB at link_num 0, Instead of HT Link topology + chip northbridge/amd/cimx/rd890 # Southbridge PCI side of HT Root complex device pci 0.0 on end # HT Root Complex 0x9600 device pci 0.1 off end # CLKCONFIG device pci 2.0 on end # GPP1 Port0 x16 SLOT4, 0x5A16 @@ -46,11 +44,10 @@ chip northbridge/amd/agesa/family10/root_complex device pci d.0 on end # GPP3b Port0 (Not for sr5650/sr5670) 0x5A1E, Intel 82576 register "gpp1_configuration" = "0" # Configuration 16:0 default register "gpp2_configuration" = "1" # Configuration 8:8 - register "gpp3a_configuration" = "2" # Configuration 4:1:1:0:0:0 - #register "gpp3a_configuration" = "11" # Configuration 1:1:1:1:1:1 + register "gpp3a_configuration" = "2" # 2 Configuration 4:1:1:0:0:0, 11 Configuration 1:1:1:1:1:1 register "port_enable" = "0x2104" - end #southbridge/amd/sr5650 - chip southbridge/amd/sp5100 # it is under NB/SB Link, but on the same pci bus + end #northbridge/amd/cimx/rd890 + chip southbridge/amd/cimx/sb700 # it is under NB/SB Link, but on the same pci bus device pci 11.0 on end # SATA device pci 12.0 on end # USB1 device pci 12.1 on end # USB1 @@ -59,8 +56,8 @@ chip northbridge/amd/agesa/family10/root_complex device pci 13.1 on end # USB2 device pci 13.2 on end # USB2 device pci 14.0 on end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 off end # HDA 0x4383, h8qgi doesnt have codec. + device pci 14.1 off end # IDE 0x439c + device pci 14.2 off end # HDA 0x4383, h8qgi not have codec. device pci 14.3 on # LPC 0x439d chip superio/winbond/w83627dhg device pnp 2e.0 off # Floppy @@ -113,64 +110,15 @@ chip northbridge/amd/agesa/family10/root_complex device pci 14.4 on end # PCI 0x4384 device pci 14.5 on end # USB 3 register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end # southbridge/amd/sp5100 + end # southbridge/amd/cimx/sb700 end # device pci 18.0 device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end device pci 18.4 on end - - device pci 19.0 on end - device pci 19.1 on end - device pci 19.2 on end - device pci 19.3 on end - device pci 19.4 on end - - - device pci 1a.0 on end - device pci 1a.0 on end - device pci 1a.0 on end - device pci 1a.0 on # another 56x0 on socket 1 Link 2, internal Node0 link 3 - end - device pci 1a.1 on end - device pci 1a.2 on end - device pci 1a.3 on end - device pci 1a.4 on end - - device pci 1b.0 on end - device pci 1b.1 on end - device pci 1b.2 on end - device pci 1b.3 on end - device pci 1b.4 on end - - - device pci 1c.0 on end - device pci 1c.1 on end - device pci 1c.2 on end - device pci 1c.3 on end - device pci 1c.4 on end - - device pci 1d.0 on end - device pci 1d.1 on end - device pci 1d.2 on end - device pci 1d.3 on end - device pci 1d.4 on end - - - device pci 1e.0 on end - device pci 1e.1 on end - device pci 1e.2 on end - device pci 1e.3 on end - device pci 1e.4 on end - - device pci 1f.0 on end - device pci 1f.1 on end - device pci 1f.2 on end - device pci 1f.3 on end - device pci 1f.4 on end - - end #chip northbridge/amd/agesa/family10 # CPU side of HT root complex + device pci 18.5 on end #f15 + end #chip northbridge/amd/agesa/family15 # CPU side of HT root complex end #pci_domain -end #northbridge/amd/agesa/family10/root_complex +end #northbridge/amd/agesa/family15/root_complex diff --git a/src/mainboard/supermicro/h8qgi/dimmSpd.c b/src/mainboard/supermicro/h8qgi/dimmSpd.c index 4ff21ee..db7d6b7 100644 --- a/src/mainboard/supermicro/h8qgi/dimmSpd.c +++ b/src/mainboard/supermicro/h8qgi/dimmSpd.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -35,17 +35,27 @@ AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PA * @param reg -GPIO Cntrl Register * @param out -GPIO bitmap * @param out -GPIO enable bitmap + * @return old setting */ -static void sp5100_set_gpio(u8 reg, u8 out, u8 enable) +static u8 sp5100_set_gpio(u8 reg, u8 out, u8 enable) { - u8 value; - device_t sm_dev = PCI_DEV(0, 0x14, 0); //SMBUS - - value = pci_read_config8(sm_dev, reg); - value &= ~(enable); - value |= out; - value &= ~(enable << 4); - pci_write_config8(sm_dev, reg, value); + u8 value, ret; + device_t sm_dev = PCI_DEV(0, 0x14, 0); //SMBUS + + value = pci_read_config8(sm_dev, reg); + ret = value; + value &= ~(enable); + value |= out; + value &= ~(enable << 4); + pci_write_config8(sm_dev, reg, value); + + return ret; +} + +static void sp5100_restore_gpio(u8 reg, u8 value) +{ + device_t sm_dev = PCI_DEV(0, 0x14, 0); + pci_write_config8(sm_dev, reg, value); } /*----------------------------------------------------------------------------- @@ -55,31 +65,31 @@ static void sp5100_set_gpio(u8 reg, u8 out, u8 enable) static const UINT8 spdAddressLookup [8] [4] [2] = { // socket, channel, dimm /* socket 0 */ { - {0xAE, 0xAC}, - {0xAA, 0xA8}, - {0xA6, 0xA4}, - {0xA2, 0xA0}, + {0xAC, 0xAE}, + {0xA8, 0xAA}, + {0xA4, 0xA6}, + {0xA0, 0xA2}, }, /* socket 1 */ { - {0xAE, 0xAC}, - {0xAA, 0xA8}, - {0xA6, 0xA4}, - {0xA2, 0xA0}, + {0xAC, 0xAE}, + {0xA8, 0xAA}, + {0xA4, 0xA6}, + {0xA0, 0xA2}, }, /* socket 2 */ { - {0xAE, 0xAC}, - {0xAA, 0xA8}, - {0xA6, 0xA4}, - {0xA2, 0xA0}, + {0xAC, 0xAE}, + {0xA8, 0xAA}, + {0xA4, 0xA6}, + {0xA0, 0xA2}, }, /* socket 3 */ { - {0xAE, 0xAC}, - {0xAA, 0xA8}, - {0xA6, 0xA4}, - {0xA2, 0xA0}, + {0xAC, 0xAE}, + {0xA8, 0xAA}, + {0xA4, 0xA6}, + {0xA0, 0xA2}, }, }; @@ -177,25 +187,17 @@ static int readspd (int iobase, int SmbusSlaveAddress, char *buffer, int count) return 0; } -static void writePmReg (int reg, int data) -{ - outb(reg, 0xCD6); - outb(data, 0xCD7); -} - static void setupFch (int ioBase) { - writePmReg (0x2D, ioBase >> 8); - writePmReg (0x2C, ioBase | 1); - writePmReg (0x29, 0x80); - writePmReg (0x28, 0x61); - outb(66000000 / 400000 / 4, ioBase + 0x0E); // set SMBus clock to 400 KHz + outb(66000000 / 400000 / 4, ioBase + 0x0E); /* set SMBus clock to 400 KHz */ } AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info) { + AGESA_STATUS status; int spdAddress, ioBase; u8 i2c_channel; + u8 backup; device_t sm_dev; if (info->SocketId >= DIMENSION (spdAddressLookup )) return AGESA_ERROR; @@ -211,7 +213,7 @@ AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PA * 1 0 channel 3 (Socket3) * 1 1 channel 4 (Socket4) */ - sp5100_set_gpio(SP5100_GPIO53_56, i2c_channel, 0x03); + backup = sp5100_set_gpio(SP5100_GPIO53_56, i2c_channel, 0x03); spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId]; if (spdAddress == 0) @@ -219,11 +221,14 @@ AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PA /* * SMBus Base Address was set during southbridge early setup. - * e.g. sb700 IO mapped SMBUS_IO_BASE 0x6000 + * e.g. sb700 IO mapped SMBUS_IO_BASE 0x6000, CIMX using 0xB00 as default */ sm_dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SB700_SM), 0); ioBase = pci_read_config32(sm_dev, 0x90) & (0xFFFFFFF0); setupFch(ioBase); - return readspd(ioBase, spdAddress, (void *)info->Buffer, 256); + status = readspd(ioBase, spdAddress, (void *)info->Buffer, 256); + sp5100_restore_gpio(SP5100_GPIO53_56, backup); + + return status; } diff --git a/src/mainboard/supermicro/h8qgi/dsdt.asl b/src/mainboard/supermicro/h8qgi/dsdt.asl old mode 100755 new mode 100644 index ebdb1eb..3f10012 --- a/src/mainboard/supermicro/h8qgi/dsdt.asl +++ b/src/mainboard/supermicro/h8qgi/dsdt.asl @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include "../../../arch/x86/acpi/debug.asl"*/ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -988,73 +988,58 @@ DefinitionBlock ( Scope(\_GPE) { /* Start Scope GPE */ /* General event 0 */ - /* Method(_L00) { - * DBGO("\\_GPE\\_L00\n") - * } - */ + Method(_L00) { + //DBGO("\\_GPE\\_L00\n") + } /* General event 1 */ - /* Method(_L01) { - * DBGO("\\_GPE\\_L00\n") - * } - */ + Method(_L01) { + //DBGO("\\_GPE\\_L01\n") + } /* General event 2 */ - /* Method(_L02) { - * DBGO("\\_GPE\\_L00\n") - * } - */ + Method(_L02) { + //DBGO("\\_GPE\\_L02\n") + } /* General event 3 */ Method(_L03) { - /* DBGO("\\_GPE\\_L00\n") */ + //DBGO("\\_GPE\\_L00\n") Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* General event 4 */ - /* Method(_L04) { - * DBGO("\\_GPE\\_L00\n") - * } - */ + Method(_L04) { + //DBGO("\\_GPE\\_L04\n") + } /* General event 5 */ - /* Method(_L05) { - * DBGO("\\_GPE\\_L00\n") - * } - */ - - /* General event 6 - Used for GPM6, moved to USB.asl */ - /* Method(_L06) { - * DBGO("\\_GPE\\_L00\n") - * } - */ + Method(_L05) { + //DBGO("\\_GPE\\_L05\n") + } - /* General event 7 - Used for GPM7, moved to USB.asl */ - /* Method(_L07) { - * DBGO("\\_GPE\\_L07\n") - * } - */ + /* _L06 General event 6 - Used for GPM6, moved to USB.asl */ + /* _L07 General event 7 - Used for GPM7, moved to USB.asl */ /* Legacy PM event */ Method(_L08) { - /* DBGO("\\_GPE\\_L08\n") */ + //DBGO("\\_GPE\\_L08\n") } /* Temp warning (TWarn) event */ Method(_L09) { - /* DBGO("\\_GPE\\_L09\n") */ + //DBGO("\\_GPE\\_L09\n") Notify (\_TZ.TZ00, 0x80) } /* Reserved */ - /* Method(_L0A) { - * DBGO("\\_GPE\\_L0A\n") - * } - */ + Method(_L0A) { + //DBGO("\\_GPE\\_L0A\n") + } /* USB controller PME# */ Method(_L0B) { - /* DBGO("\\_GPE\\_L0B\n") */ + //DBGO("\\_GPE\\_L0B\n") Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ @@ -1065,126 +1050,81 @@ DefinitionBlock ( } /* AC97 controller PME# */ - /* Method(_L0C) { - * DBGO("\\_GPE\\_L0C\n") - * } - */ + Method(_L0C) { + //DBGO("\\_GPE\\_L0C\n") + } /* OtherTherm PME# */ - /* Method(_L0D) { - * DBGO("\\_GPE\\_L0D\n") - * } - */ + Method(_L0D) { + //DBGO("\\_GPE\\_L0D\n") + } - /* GPM9 SCI event - Moved to USB.asl */ - /* Method(_L0E) { - * DBGO("\\_GPE\\_L0E\n") - * } - */ + /* _L0E GPM9 SCI event - Moved to USB.asl */ /* PCIe HotPlug event */ - /* Method(_L0F) { - * DBGO("\\_GPE\\_L0F\n") - * } - */ + Method(_L0F) { + //DBGO("\\_GPE\\_L0F\n") + } /* ExtEvent0 SCI event */ Method(_L10) { - /* DBGO("\\_GPE\\_L10\n") */ + //DBGO("\\_GPE\\_L10\n") } /* ExtEvent1 SCI event */ Method(_L11) { - /* DBGO("\\_GPE\\_L11\n") */ + //DBGO("\\_GPE\\_L11\n") } /* PCIe PME# event */ - /* Method(_L12) { - * DBGO("\\_GPE\\_L12\n") - * } - */ - - /* GPM0 SCI event - Moved to USB.asl */ - /* Method(_L13) { - * DBGO("\\_GPE\\_L13\n") - * } - */ - - /* GPM1 SCI event - Moved to USB.asl */ - /* Method(_L14) { - * DBGO("\\_GPE\\_L14\n") - * } - */ - - /* GPM2 SCI event - Moved to USB.asl */ - /* Method(_L15) { - * DBGO("\\_GPE\\_L15\n") - * } - */ - - /* GPM3 SCI event - Moved to USB.asl */ - /* Method(_L16) { - * DBGO("\\_GPE\\_L16\n") - * } - */ + Method(_L12) { + //DBGO("\\_GPE\\_L12\n") + } - /* GPM8 SCI event - Moved to USB.asl */ - /* Method(_L17) { - * DBGO("\\_GPE\\_L17\n") - * } - */ + /* _L13 GPM0 SCI event - Moved to USB.asl */ + /* _L14 GPM1 SCI event - Moved to USB.asl */ + /* _L15 GPM2 SCI event - Moved to USB.asl */ + /* _L16 GPM3 SCI event - Moved to USB.asl */ + /* _L17 GPM8 SCI event - Moved to USB.asl */ /* GPIO0 or GEvent8 event */ Method(_L18) { - /* DBGO("\\_GPE\\_L18\n") */ + //DBGO("\\_GPE\\_L18\n") Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBRb, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBRc, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBRd, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } - /* GPM4 SCI event - Moved to USB.asl */ - /* Method(_L19) { - * DBGO("\\_GPE\\_L19\n") - * } - */ - - /* GPM5 SCI event - Moved to USB.asl */ - /* Method(_L1A) { - * DBGO("\\_GPE\\_L1A\n") - * } - */ + /* _L19 GPM4 SCI event - Moved to USB.asl */ + /* _L1A GPM5 SCI event - Moved to USB.asl */ /* Azalia SCI event */ Method(_L1B) { - /* DBGO("\\_GPE\\_L1B\n") */ + //DBGO("\\_GPE\\_L1B\n") Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* GPM6 SCI event - Reassigned to _L06 */ - /* Method(_L1C) { - * DBGO("\\_GPE\\_L1C\n") - * } - */ + Method(_L1C) { + //DBGO("\\_GPE\\_L1C\n") + } /* GPM7 SCI event - Reassigned to _L07 */ - /* Method(_L1D) { - * DBGO("\\_GPE\\_L1D\n") - * } - */ + Method(_L1D) { + //DBGO("\\_GPE\\_L1D\n") + } /* GPIO2 or GPIO66 SCI event */ - /* Method(_L1E) { - * DBGO("\\_GPE\\_L1E\n") - * } - */ + Method(_L1E) { + //DBGO("\\_GPE\\_L1E\n") + } - /* SATA SCI event - Moved to sata.asl */ - /* Method(_L1F) { - * DBGO("\\_GPE\\_L1F\n") - * } - */ + /* _L1F SATA SCI event - Moved to sata.asl */ } /* End Scope GPE */ @@ -1569,7 +1509,7 @@ DefinitionBlock ( 0x0CF8, // Range Maximum 0x01, // Alignment 0x08, // Length - ) + ) WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, 0x0000, // Granularity @@ -1602,10 +1542,10 @@ DefinitionBlock ( ,, , TypeStatic) WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, 0x0000, // Granularity - 0x9000, // Range Minimum - 0xefff, // Range Maximum + 0x0D00, // Range Minimum + 0xFFFF, // Range Maximum 0x0000, // Translation Offset - 0x6000, // Length + 0xF300, // Length ,, , TypeStatic) Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) // VGA memory space @@ -1613,21 +1553,26 @@ DefinitionBlock ( 0xE0000000, // Address Base 0x10000000, // Address Length, (1MB each Bus, 256 Buses by default) MMIO) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00000000, // Granularity - 0xF0000000, // Range Minimum - 0xFFFFFFFF, // Range Maximum - 0x00000000, // Translation Offset - 0x10000000, // Length - ,, , AddressRangeMemory, TypeStatic) }) Method (_CRS, 0, NotSerialized) { CreateDWordField (CRS, \_SB.PCI0.MMIO._BAS, BAS1) CreateDWordField (CRS, \_SB.PCI0.MMIO._LEN, LEN1) - Store (PCBA, BAS1) - Store (PCLN, LEN1) + + /* + * Declare memory between TOM1 and 4GB as available + * for PCI MMIO. + * Use ShiftLeft to avoid 64bit constant (for XP). + * This will work even if the OS does 32bit arithmetic, as + * 32bit (0x00000000 - TOM1) will wrap and give the same + * result as 64bit (0x100000000 - TOM1). + */ + Store(TOM1, BAS1) + ShiftLeft(0x10000000, 4, Local0) + Subtract(Local0, TOM1, Local0) + Store(Local0, LEN1) + //DBGO(TOM1) Return (CRS) } diff --git a/src/mainboard/supermicro/h8qgi/fadt.c b/src/mainboard/supermicro/h8qgi/fadt.c index c2f714d..0c63162 100644 --- a/src/mainboard/supermicro/h8qgi/fadt.c +++ b/src/mainboard/supermicro/h8qgi/fadt.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -28,21 +28,17 @@ #include <arch/acpi.h> #include <arch/io.h> #include <device/device.h> -#include "southbridge/amd/sb700/sb700.h" +#include "Platform.h" /*sb700 platform header*/ -u16 pm_base = SB700_ACPI_IO_BASE; -/* pm_base should be set in sb acpi */ -/* pm_base should be got from bar2 of sb700. Here I compact ACPI - * registers into 32 bytes limit. - * */ +#ifndef ACPI_BLK_BASE + #define ACPI_BLK_BASE PM1_EVT_BLK_ADDRESS +#endif void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) { acpi_header_t *header = &(fadt->header); - pm_base &= 0xFFFF; - printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base); - + printk(BIOS_DEBUG, "ACPI_BLK_BASE: 0x%04x\n", ACPI_BLK_BASE); /* Prepare the header */ memset((void *)fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); @@ -65,38 +61,15 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->s4bios_req = 0x0; fadt->pstate_cnt = 0xe2; - pm_iowrite(0x60, ACPI_PM_EVT_BLK & 0xFF); - pm_iowrite(0x61, ACPI_PM_EVT_BLK >> 8); - pm_iowrite(0x62, ACPI_PM1_CNT_BLK & 0xFF); - pm_iowrite(0x63, ACPI_PM1_CNT_BLK >> 8); - pm_iowrite(0x64, ACPI_PM_TMR_BLK & 0xFF); - pm_iowrite(0x65, ACPI_PM_TMR_BLK >> 8); - pm_iowrite(0x68, ACPI_GPE0_BLK & 0xFF); - pm_iowrite(0x69, ACPI_GPE0_BLK >> 8); - - /* CpuControl is in \_PR.CPU0, 6 bytes */ - pm_iowrite(0x66, ACPI_CPU_CONTROL & 0xFF); - pm_iowrite(0x67, ACPI_CPU_CONTROL >> 8); - - pm_iowrite(0x6A, 0); /* AcpiSmiCmdLo */ - pm_iowrite(0x6B, 0); /* AcpiSmiCmdHi */ - - pm_iowrite(0x6C, ACPI_PMA_CNT_BLK & 0xFF); - pm_iowrite(0x6D, ACPI_PMA_CNT_BLK >> 8); - - pm_iowrite(0x74, 1<<0 | 1<<1 | 1<<4 | 1<<2); /* AcpiDecodeEnable, When set, SB uses - * the contents of the PM registers at - * index 60-6B to decode ACPI I/O address. - * AcpiSmiEn & SmiCmdEn*/ /* RTC_En_En, TMR_En_En, GBL_EN_EN */ - outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */ - fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; + outl(0x1, PM1_CNT_BLK_ADDRESS); /* set SCI_EN */ + fadt->pm1a_evt_blk = PM1_EVT_BLK_ADDRESS; fadt->pm1b_evt_blk = 0x0000; - fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK; + fadt->pm1a_cnt_blk = PM1_CNT_BLK_ADDRESS; fadt->pm1b_cnt_blk = 0x0000; - fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK; - fadt->pm_tmr_blk = ACPI_PM_TMR_BLK; - fadt->gpe0_blk = ACPI_GPE0_BLK; + fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK_ADDRESS; + fadt->pm_tmr_blk = PM1_TMR_BLK_ADDRESS; + fadt->gpe0_blk = GPE0_BLK_ADDRESS; fadt->gpe1_blk = 0x0000; /* we dont have gpe1 block, do we? */ fadt->pm1_evt_len = 4; @@ -139,7 +112,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->x_pm1a_evt_blk.bit_width = 32; fadt->x_pm1a_evt_blk.bit_offset = 0; fadt->x_pm1a_evt_blk.resv = 0; - fadt->x_pm1a_evt_blk.addrl = ACPI_PM_EVT_BLK; + fadt->x_pm1a_evt_blk.addrl = PM1_EVT_BLK_ADDRESS; fadt->x_pm1a_evt_blk.addrh = 0x0; fadt->x_pm1b_evt_blk.space_id = 1; @@ -154,7 +127,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->x_pm1a_cnt_blk.bit_width = 16; fadt->x_pm1a_cnt_blk.bit_offset = 0; fadt->x_pm1a_cnt_blk.resv = 0; - fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK; + fadt->x_pm1a_cnt_blk.addrl = PM1_CNT_BLK_ADDRESS; fadt->x_pm1a_cnt_blk.addrh = 0x0; fadt->x_pm1b_cnt_blk.space_id = 1; @@ -169,7 +142,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->x_pm2_cnt_blk.bit_width = 0; fadt->x_pm2_cnt_blk.bit_offset = 0; fadt->x_pm2_cnt_blk.resv = 0; - fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK; + fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK_ADDRESS; fadt->x_pm2_cnt_blk.addrh = 0x0; @@ -177,7 +150,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->x_pm_tmr_blk.bit_width = 32; fadt->x_pm_tmr_blk.bit_offset = 0; fadt->x_pm_tmr_blk.resv = 0; - fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK; + fadt->x_pm_tmr_blk.addrl = PM1_TMR_BLK_ADDRESS; fadt->x_pm_tmr_blk.addrh = 0x0; @@ -185,7 +158,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->x_gpe0_blk.bit_width = 32; fadt->x_gpe0_blk.bit_offset = 0; fadt->x_gpe0_blk.resv = 0; - fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK; + fadt->x_gpe0_blk.addrl = GPE0_BLK_ADDRESS; fadt->x_gpe0_blk.addrh = 0x0; diff --git a/src/mainboard/supermicro/h8qgi/get_bus_conf.c b/src/mainboard/supermicro/h8qgi/get_bus_conf.c index 14e6bca..8c31cbf 100644 --- a/src/mainboard/supermicro/h8qgi/get_bus_conf.c +++ b/src/mainboard/supermicro/h8qgi/get_bus_conf.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -23,8 +23,10 @@ #include <string.h> #include <stdint.h> #include <stdlib.h> -#include <cpu/amd/amdfam10_sysconf.h> #include "agesawrapper.h" +#if CONFIG_AMD_SB_CIMX +#include <sb_cimx.h> +#endif /* Global variables for MB layouts and these will be shared by irqtable mptable @@ -34,22 +36,6 @@ u8 bus_isa; u8 bus_sp5100[2]; u8 bus_sr5650[14]; -/* - * Here you only need to set value in pci1234 for HT-IO that could be installed or not - * You may need to preset pci1234 for HTIO board, - * please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail - */ -u32 pci1234x[] = { - 0x0000ff0, -}; - -/* - * HT Chain device num, actually it is unit id base of every ht device in chain, - * assume every chain only have 4 ht device at most - */ -u32 hcdnx[] = { - 0x20202020, -}; u32 bus_type[256]; @@ -106,8 +92,7 @@ void get_bus_conf(void) bus_type[0] = 1; /* pci */ - bus_sr5650[0] = (pci1234x[0] >> 16) & 0xff; - // bus_sp5100[0] = (sysconf.pci1234[0] >> 16) & 0xff; + bus_sr5650[0] = 0; bus_sp5100[0] = bus_sr5650[0]; /* sp5100 */ @@ -151,4 +136,9 @@ void get_bus_conf(void) /* I/O APICs: APIC ID Version State Address */ bus_isa = 10; + +#if CONFIG_AMD_SB_CIMX + sb_After_Pci_Init(); + sb_Late_Post(); +#endif } diff --git a/src/mainboard/supermicro/h8qgi/irq_tables.c b/src/mainboard/supermicro/h8qgi/irq_tables.c index 640a0a6..11e5256 100644 --- a/src/mainboard/supermicro/h8qgi/irq_tables.c +++ b/src/mainboard/supermicro/h8qgi/irq_tables.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -27,9 +27,9 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, - u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, - u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, - u8 slot, u8 rfu) + u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, + u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, + u8 slot, u8 rfu) { pirq_info->bus = bus; pirq_info->devfn = devfn; diff --git a/src/mainboard/supermicro/h8qgi/mainboard.c b/src/mainboard/supermicro/h8qgi/mainboard.c index f00b5a0..675c87f 100644 --- a/src/mainboard/supermicro/h8qgi/mainboard.c +++ b/src/mainboard/supermicro/h8qgi/mainboard.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -25,36 +25,48 @@ #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> #include <device/pci_def.h> -#include "southbridge/amd/sr5650/cmn.h" +#include <NbPlatform.h> #include "chip.h" -void set_pcie_dereset(void); -void set_pcie_reset(void); +void set_pcie_dereset(void *nbconfig); +void set_pcie_reset(void *nbconfig); /** * */ -void set_pcie_reset(void) +void set_pcie_reset(void *nbconfig) { } /** + * Mainboard specific RD890 CIMx callback * Release Resets to PCIe Links - * PCIE_RESET_GPIO1,2,4,5 + * For Both SR56X0 chips, PCIE_RESET_GPIO1 to reset pcie */ -void set_pcie_dereset(void) +void set_pcie_dereset(void *nbconfig) { - device_t pcie_core_dev; + //u32 nb_dev = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0); + u32 i; + u32 val; + u32 nb_addr; - pcie_core_dev = dev_find_slot(0, PCI_DEVFN(0, 0)); - set_htiu_enable_bits(pcie_core_dev, 0xA8, 0x07000707, 0x07000707); - set_htiu_enable_bits(pcie_core_dev, 0xA9, 0x00000007, 0x00000007); + val = 0x00000007UL; + AMD_NB_CONFIG_BLOCK *pConfig = (AMD_NB_CONFIG_BLOCK*)nbconfig; + for (i = 0; i < MAX_NB_COUNT; i ++) { + nb_addr = pConfig->Northbridges[i].NbPciAddress.AddressValue | NB_HTIU_INDEX; + LibNbPciIndexRMW(nb_addr, + NB_HTIU_REGA8, + AccessS3SaveWidth32, + ~val, + val, + &(pConfig->Northbridges[i])); + } } /************************************************* -* enable the dedicated function in h8qgi board. -*************************************************/ + * enable the dedicated function in h8qgi board. + *************************************************/ static void h8qgi_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); @@ -69,5 +81,5 @@ int add_mainboard_resources(struct lb_memory *mem) struct chip_operations mainboard_ops = { CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard") - .enable_dev = h8qgi_enable, + .enable_dev = h8qgi_enable, }; diff --git a/src/mainboard/supermicro/h8qgi/mptable.c b/src/mainboard/supermicro/h8qgi/mptable.c index 5c01994..92771bd 100644 --- a/src/mainboard/supermicro/h8qgi/mptable.c +++ b/src/mainboard/supermicro/h8qgi/mptable.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -33,17 +33,16 @@ extern u8 bus_sp5100[2]; extern u32 bus_type[256]; extern u32 sbdn_sr5650; extern u32 sbdn_sp5100; +extern u8 bus_isa; static void *smp_write_config_table(void *v) { struct mp_config_table *mc; - int bus_isa; u32 apicid_sp5100; u32 apicid_sr5650; device_t dev; u32 dword; - u8 byte; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mptable_init(mc, LAPIC_ADDR); @@ -62,17 +61,18 @@ static void *smp_write_config_table(void *v) #if CONFIG_MAX_CPUS >= 16 apicid_sp5100 = 0x0; #else - apicid_sp5100 = CONFIG_MAX_CPUS + 1; + apicid_sp5100 = CONFIG_MAX_CPUS + 1 #endif apicid_sr5650 = apicid_sp5100 + 1; - //bus_sp5100[0], TODO: why bus_sp5100[0] use same value of bus_sr5650[0] assigned by get_pci1234(), instead of 0. dev = dev_find_slot(0, PCI_DEVFN(sbdn_sp5100 + 0x14, 0)); if (dev) { /* Set SP5100 IOAPIC ID */ dword = pci_read_config32(dev, 0x74) & 0xfffffff0; smp_write_ioapic(mc, apicid_sp5100, 0x20, dword); +#ifdef UNUSED_CODE + u8 byte; /* Initialize interrupt mapping */ /* aza */ byte = pci_read_config8(dev, 0x63); @@ -85,6 +85,7 @@ static void *smp_write_config_table(void *v) dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */ /* dword |= 1<<22; PIC and APIC co exists */ pci_write_config32(dev, 0xAC, dword); +#endif /* * 00:12.0: PROG SATA : INT F @@ -102,11 +103,11 @@ static void *smp_write_config_table(void *v) /* Set RS5650 IOAPIC ID */ dev = dev_find_slot(0, PCI_DEVFN(0, 0)); - if (dev) { - pci_write_config32(dev, 0xF8, 0x1); - dword = pci_read_config32(dev, 0xFC) & 0xfffffff0; - smp_write_ioapic(mc, apicid_sr5650, 0x20, dword); - } + if (dev) { + pci_write_config32(dev, 0xF8, 0x1); + dword = pci_read_config32(dev, 0xFC) & 0xfffffff0; + smp_write_ioapic(mc, apicid_sr5650, 0x20, dword); + } } @@ -155,27 +156,27 @@ static void *smp_write_config_table(void *v) * PCI_INT(bus_sr5650[0x7], 0x0, 0x0, 0x13); */ - //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((13)<<2)|(0)), apicid_sr5650, 28); /* dev d */ - //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sr5650[13], (((0)<<2)|(1)), apicid_sr5650, 0); /* card behind dev13 */ + //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((13)<<2)|(0)), apicid_sr5650, 28); /* dev d */ + //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sr5650[13], (((0)<<2)|(1)), apicid_sr5650, 0); /* card behind dev13 */ /* PCI slots */ - /* PCI_SLOT 0. */ - PCI_INT(bus_sp5100[1], 0x5, 0x0, 0x14); - PCI_INT(bus_sp5100[1], 0x5, 0x1, 0x15); - PCI_INT(bus_sp5100[1], 0x5, 0x2, 0x16); - PCI_INT(bus_sp5100[1], 0x5, 0x3, 0x17); - - /* PCI_SLOT 1. */ - PCI_INT(bus_sp5100[1], 0x6, 0x0, 0x15); - PCI_INT(bus_sp5100[1], 0x6, 0x1, 0x16); - PCI_INT(bus_sp5100[1], 0x6, 0x2, 0x17); - PCI_INT(bus_sp5100[1], 0x6, 0x3, 0x14); - - /* PCI_SLOT 2. */ - PCI_INT(bus_sp5100[1], 0x7, 0x0, 0x16); - PCI_INT(bus_sp5100[1], 0x7, 0x1, 0x17); - PCI_INT(bus_sp5100[1], 0x7, 0x2, 0x14); - PCI_INT(bus_sp5100[1], 0x7, 0x3, 0x15); + /* PCI_SLOT 0. */ + PCI_INT(bus_sp5100[1], 0x5, 0x0, 0x14); + PCI_INT(bus_sp5100[1], 0x5, 0x1, 0x15); + PCI_INT(bus_sp5100[1], 0x5, 0x2, 0x16); + PCI_INT(bus_sp5100[1], 0x5, 0x3, 0x17); + + /* PCI_SLOT 1. */ + PCI_INT(bus_sp5100[1], 0x6, 0x0, 0x15); + PCI_INT(bus_sp5100[1], 0x6, 0x1, 0x16); + PCI_INT(bus_sp5100[1], 0x6, 0x2, 0x17); + PCI_INT(bus_sp5100[1], 0x6, 0x3, 0x14); + + /* PCI_SLOT 2. */ + PCI_INT(bus_sp5100[1], 0x7, 0x0, 0x16); + PCI_INT(bus_sp5100[1], 0x7, 0x1, 0x17); + PCI_INT(bus_sp5100[1], 0x7, 0x2, 0x14); + PCI_INT(bus_sp5100[1], 0x7, 0x3, 0x15); /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ diff --git a/src/mainboard/supermicro/h8qgi/platform_cfg.h b/src/mainboard/supermicro/h8qgi/platform_cfg.h new file mode 100644 index 0000000..bbc4ad7 --- /dev/null +++ b/src/mainboard/supermicro/h8qgi/platform_cfg.h @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _PLATFORM_CFG_H_ +#define _PLATFORM_CFG_H_ + + +/* northbridge customize options */ +/** + * Max number of northbridges in the system + */ +#define MAX_NB_COUNT 1 //TODO: only 1 NB tested + +/** + * Enable check for PCIe endpoint to be ready for PCI enumeration. + * + */ +//#define EPREADY_WORKAROUND_DISABLED + +/** + * Enable IOMMU support. Initialize IOMMU subsystem, generate IVRS ACPI table. + * + */ +#define IOMMU_SUPPORT_DISABLE //TODO: enable it + +/** + * Disable server PCIe hotplug support. + */ + +//#define HOTPLUG_SUPPORT_DISABLED + +/** + * Disable support for device number remapping for PCIe portsserver PCIe hotplug support. + */ + +//#define DEVICE_REMAP_DISABLE + +#endif //_PLATFORM_CFG_H_ diff --git a/src/mainboard/supermicro/h8qgi/platform_oem.c b/src/mainboard/supermicro/h8qgi/platform_oem.c index f36b0d8..883cad1 100644 --- a/src/mainboard/supermicro/h8qgi/platform_oem.c +++ b/src/mainboard/supermicro/h8qgi/platform_oem.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,7 +21,6 @@ #include "amdlib.h" #include "Ids.h" #include "heapManager.h" -#include "platform_oem.h" #include "Filecode.h" #define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE @@ -43,6 +42,7 @@ * **/ /*---------------------------------------------------------------------------------------*/ +VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly); VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly) { //InitEarly->PlatformConfig.CoreLevelingMode = CORE_LEVEL_TWO; diff --git a/src/mainboard/supermicro/h8qgi/platform_oem.h b/src/mainboard/supermicro/h8qgi/platform_oem.h deleted file mode 100644 index ab0d6df..0000000 --- a/src/mainboard/supermicro/h8qgi/platform_oem.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef _PLATFORM_OEM_H_ -#define _PLATFORM_OEM_H_ - -#include "Porting.h" -#include "AGESA.h" -#include "amdlib.h" - -VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly); - -#endif //_PLATFORM_OEM_H_ diff --git a/src/mainboard/supermicro/h8qgi/rd890_cfg.c b/src/mainboard/supermicro/h8qgi/rd890_cfg.c new file mode 100644 index 0000000..7a947b3 --- /dev/null +++ b/src/mainboard/supermicro/h8qgi/rd890_cfg.c @@ -0,0 +1,274 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "NbPlatform.h" +#include "rd890_cfg.h" +#include "northbridge/amd/cimx/rd890/chip.h" +#include "nbInitializer.h" +#include <string.h> +#include <arch/ioapic.h> + +#ifndef __PRE_RAM__ +#include <device/device.h> +extern void set_pcie_reset(void *config); +extern void set_pcie_dereset(void *config); + +/** + * Platform dependent configuration at ramstage + */ +static void nb_platform_config(device_t nb_dev, AMD_NB_CONFIG *NbConfigPtr) +{ + u16 i; + PCIE_CONFIG *pPcieConfig = NbConfigPtr->pPcieConfig; + //AMD_NB_CONFIG_BLOCK *ConfigPtr = GET_BLOCK_CONFIG_PTR(NbConfigPtr); + struct northbridge_amd_cimx_rd890_config *rd890_info = NULL; + DEFAULT_PLATFORM_CONFIG(platform_config); + + /* update the platform depentent configuration by devicetree */ + rd890_info = nb_dev->chip_info; + platform_config.PortEnableMap = rd890_info->port_enable; + if (rd890_info->gpp1_configuration == 0) { + platform_config.Gpp1Config = GFX_CONFIG_AAAA; + } else if (rd890_info->gpp1_configuration == 1) { + platform_config.Gpp1Config = GFX_CONFIG_AABB; + } + if (rd890_info->gpp2_configuration == 0) { + platform_config.Gpp2Config = GFX_CONFIG_AAAA; + } else if (rd890_info->gpp2_configuration == 1) { + platform_config.Gpp2Config = GFX_CONFIG_AABB; + } + platform_config.Gpp3aConfig = rd890_info->gpp3a_configuration; + + if (platform_config.Gpp1Config != 0) { + pPcieConfig->CoreConfiguration[0] = platform_config.Gpp1Config; + } + if (platform_config.Gpp2Config != 0) { + pPcieConfig->CoreConfiguration[1] = platform_config.Gpp2Config; + } + if (platform_config.Gpp3aConfig != 0) { + pPcieConfig->CoreConfiguration[2] = platform_config.Gpp3aConfig; + } + + pPcieConfig->TempMmioBaseAddress = (UINT16)(platform_config.TemporaryMmio >> 20); + for (i = 0; i <= MAX_CORE_ID; i++) { + NbConfigPtr->pPcieConfig->CoreSetting[i].SkipConfiguration = OFF; + NbConfigPtr->pPcieConfig->CoreSetting[i].PerformanceMode = OFF; + } + for (i = MIN_PORT_ID; i <= MAX_PORT_ID; i++) { + NbConfigPtr->pPcieConfig->PortConfiguration[i].PortLinkMode = PcieLinkModeGen2; + } + + for (i = MIN_PORT_ID; i <= MAX_PORT_ID; i++) { + if ((platform_config.PortEnableMap & (1 << i)) != 0) { + pPcieConfig->PortConfiguration[i].PortPresent = ON; + if ((platform_config.PortGen1Map & (1 << i)) != 0) { + pPcieConfig->PortConfiguration[i].PortLinkMode = PcieLinkModeGen1; + } + if ((platform_config.PortHotplugMap & (1 << i)) != 0) { + u16 j; + pPcieConfig->PortConfiguration[j].PortHotplug = ON; /* Enable Hotplug */ + /* Set Hotplug descriptor info */ + for (j = 0; j < 8; j++) { + u32 PortDescriptor; + PortDescriptor = platform_config.PortHotplugDescriptors[j]; + if ((PortDescriptor & 0xF) == j) { + pPcieConfig->ExtPortConfiguration[j].PortHotplugDevMap = (PortDescriptor >> 4) & 3; + pPcieConfig->ExtPortConfiguration[j].PortHotplugByteMap = (PortDescriptor >> 6) & 1; + break; + } + } + } + } + } +} +#endif // __PRE_RAM__ + +/** + * @brief Entry point of Northbridge CIMx callout/CallBack + * + * prototype AGESA_STATUS (*CALLOUT_ENTRY) (UINT32 Param1, UINTN Param2, VOID* ConfigPtr); + * + * @param[in] u32 func Northbridge CIMx CallBackId + * @param[in] u32 data Northbridge Input Data. + * @param[in] AMD_NB_CONFIG *config Northbridge configuration structure pointer. + * + */ +static u32 rd890_callout_entry(u32 func, u32 data, void *config) +{ + u32 ret = 0; +#ifndef __PRE_RAM__ + device_t nb_dev = (device_t)data; +#endif + AMD_NB_CONFIG *nbConfigPtr = (AMD_NB_CONFIG*)config; + + switch (func) { + case PHCB_AmdPortTrainingCompleted: + break; + + case PHCB_AmdPortResetDeassert: +#ifndef __PRE_RAM__ + set_pcie_dereset(config); +#endif + break; + + case PHCB_AmdPortResetAssert: +#ifndef __PRE_RAM__ + set_pcie_reset(config); +#endif + break; + + case PHCB_AmdPortResetSupported: + break; + case PHCB_AmdGeneratePciReset: + break; + case PHCB_AmdGetExclusionTable: + break; + case PHCB_AmdAllocateBuffer: + break; + case PHCB_AmdUpdateApicInterruptMapping: + break; + case PHCB_AmdFreeBuffer: + break; + case PHCB_AmdLocateBuffer: + break; + case PHCB_AmdReportEvent: + break; + case PHCB_AmdPcieAsmpInfo: + break; + + case CB_AmdSetNbPorConfig: + break; + case CB_AmdSetHtConfig: + /*TODO: different HT path and deempasis for each NB */ + nbConfigPtr->pHtConfig->NbTransmitterDeemphasis = DEFAULT_HT_DEEMPASIES; + + break; + case CB_AmdSetPcieEarlyConfig: +#ifndef __PRE_RAM__ + nb_platform_config(nb_dev, nbConfigPtr); +#endif + break; + + case CB_AmdSetEarlyPostConfig: + break; + + case CB_AmdSetMidPostConfig: + nbConfigPtr->pNbConfig->IoApicBaseAddress = IO_APIC_ADDR; +#ifndef IOMMU_SUPPORT_DISABLE //TODO enable iommu + /* SBIOS must alloc 16K memory for IOMMU MMIO */ + UINT32 MmcfgBarAddress; //using default IOmmuBaseAddress + LibNbPciRead(nbConfigPtr->NbPciAddress.AddressValue | 0x1C, + AccessWidth32, + &MmcfgBarAddress, + nbConfigPtr); + MmcfgBarAddress &= ~0xf; + if (MmcfgBarAddress != 0) { + nbConfigPtr->IommuBaseAddress = MmcfgBarAddress; + } + nbConfigPtr->IommuBaseAddress = 0; //disable iommu +#endif + break; + + case CB_AmdSetLatePostConfig: + break; + + case CB_AmdSetRecoveryConfig: + break; + } + + return ret; +} + + +/** + * @brief North Bridge CIMx configuration + * + * should be called before exeucte CIMx function. + * this function will be called in romstage and ramstage. + */ +void rd890_cimx_config(AMD_NB_CONFIG_BLOCK *pConfig, NB_CONFIG *nbConfig, HT_CONFIG *htConfig, PCIE_CONFIG *pcieConfig) +{ + u16 i = 0; + PCI_ADDR PciAddress; + u32 val, sbNode, sbLink; + + if (!pConfig) { + return; + } + + memset(pConfig, 0, sizeof(AMD_NB_CONFIG_BLOCK)); + for (i = 0; i < MAX_NB_COUNT; i++) { + pConfig->Northbridges[i].pNbConfig = &nbConfig[i]; + pConfig->Northbridges[i].pHtConfig = &htConfig[i]; + pConfig->Northbridges[i].pPcieConfig = &pcieConfig[i]; + pConfig->Northbridges[i].ConfigPtr = &pConfig; + } + + /* Initialize all NB structures */ + AmdInitializer(pConfig); + + pConfig->NumberOfNorthbridges = MAX_NB_COUNT - 1; /* Support limited to primary NB only located at 0:0:0 */ + //pConfig->StandardHeader.ImageBasePtr = CIMX_B2_IMAGE_BASE_ADDRESS; + pConfig->StandardHeader.PcieBasePtr = (VOID *)PCIEX_BASE_ADDRESS; + pConfig->StandardHeader.CalloutPtr = &rd890_callout_entry; + + /* + * PCI Address to Access NB. Depends on HT topology and configuration for multi NB platform. + * Always 0:0:0 on single NB platform. + */ + pConfig->Northbridges[0].NbPciAddress.AddressValue = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0); + + /* Set HT path to NB by SbNode and SbLink */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x60); + LibNbPciRead(PciAddress.AddressValue, AccessWidth32, &val, &(pConfig->Northbridges[0])); + sbNode = (val >> 8) & 0x07; + PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x64); + LibNbPciRead(PciAddress.AddressValue, AccessWidth32, &val, &(pConfig->Northbridges[0])); + sbLink = (val >> 8) & 0x07; //assum ganged + pConfig->Northbridges[0].NbHtPath.NodeID = sbNode; + pConfig->Northbridges[0].NbHtPath.LinkID = sbLink; + //TODO: other NBs + +#ifndef __PRE_RAM__ + /* If temporrary MMIO enable set up CPU MMIO */ + for (i = 0; i <= pConfig->NumberOfNorthbridges; i++) { + UINT32 MmioBase; + UINT32 LinkId; + UINT32 SubLinkId; + MmioBase = pConfig->Northbridges[i].pPcieConfig->TempMmioBaseAddress; + if (MmioBase != 0) { + LinkId = pConfig->Northbridges[i].NbHtPath.LinkID & 0xf; + SubLinkId = ((pConfig->Northbridges[i].NbHtPath.LinkID & 0xF0) == 0x20) ? 1 : 0; + /* Set Limit */ + LibNbPciRMW(MAKE_SBDFO (0, 0, 0x18, 0x1, (i * 4) + 0x84), + AccessWidth32, + 0x0, + ((MmioBase << 12) + 0xF00) | (LinkId << 4) | (SubLinkId << 6), + &(pConfig->Northbridges[i])); + /* Set Base */ + LibNbPciRMW(MAKE_SBDFO (0, 0, 0x18, 0x1, (i * 4) + 0x80), + AccessWidth32, + 0x0, + (MmioBase << 12) | 0x3, + &(pConfig->Northbridges[i])); + } + } +#endif +} + diff --git a/src/mainboard/supermicro/h8qgi/rd890_cfg.h b/src/mainboard/supermicro/h8qgi/rd890_cfg.h new file mode 100644 index 0000000..8f45019 --- /dev/null +++ b/src/mainboard/supermicro/h8qgi/rd890_cfg.h @@ -0,0 +1,174 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _RD890_CFG_H_ +#define _RD890_CFG_H_ + +#include "NbPlatform.h" + +/* platform dependent configuration default value */ + +/** + * Path from CPU to NB + * [0..7] - Node (0..8) + * [8..11] - Link (0..3) + * [12..15] - Sublink (1..2), If NB connected to full link than Sublink should be set to 0. + */ +#ifndef DEFAULT_HT_PATH +#if CONFIG_CPU_AMD_AGESA_FAMILY10 == 1 +#define DEFAULT_HT_PATH {0x0, 0x3} +#endif +#if CONFIG_CPU_AMD_AGESA_FAMILY15 == 1 +#define DEFAULT_HT_PATH {0x0, 0x1} +#endif +#endif + +/** + * Bitmap of enabled ports on NB #0/1/2/3 + * Bit[0] - Reserved + * Bit[1] - Reserved + * Bit[2] - Enable PCIe port 2 + * Bit[3] - Enable PCIe port 3 + * Bit[4] - Enable PCIe port 4 + * Bit[5] - Enable PCIe port 5 + * Bit[6] - Enable PCIe port 2 + * Bit[7] - Enable PCIe port 7 + * Bit[8] - Reserved + * Bit[9] - Enable PCIe port 9 + * Bit[10]- Enable PCIe port 10 + * Bit[11]- Enable PCIe port 11 + * Bit[12]- Enable PCIe port 12 + * Bit[13]- Enable PCIe port 13 + * Example: + * port_enable = 0x14 + * Port 2 and 4 enabled for training/initialization + */ +#ifndef DEFAULT_PORT_ENABLE_MAP +#define DEFAULT_PORT_ENABLE_MAP 0x0014 +#endif + +/** + * Bitmap of ports that have slot or onboard device connected. + * Example force PCIe Gen1 supporton port 2 and 4 (DEFAULT_PORT_ENABLE_MAP = BIT2 | BIT4) + * #define DEFAULT_PORT_FORCE_GEN1 0x604 + */ +#ifndef DEFAULT_PORT_FORCE_GEN1 +#define DEFAULT_PORT_FORCE_GEN1 0x0 +#endif + +/** + * Bitmap of ports that have server hotplug support + */ +#ifndef DEFAULT_HOTPLUG_SUPPORT +#define DEFAULT_HOTPLUG_SUPPORT 0x0 +#endif + +#ifndef DEFAULT_HOTPLUG_DESCRIPTOR +#define DEFAULT_HOTPLUG_DESCRIPTOR {0, 0, 0, 0, 0, 0, 0, 0} +#endif + +#ifndef DEFAULT_TEMPMMIO_BASE_ADDRESS +#define DEFAULT_TEMPMMIO_BASE_ADDRESS 0xD0000000 +#endif + +/** + * Default GPP1 core configuraton on NB #0/1/2/3. + * 2 x8 slot, GFX_CONFIG_AABB + * 1 x16 slot, GFX_CONFIG_AAAA + */ +#ifndef DEFAULT_GPP1_CONFIG +#define DEFAULT_GPP1_CONFIG GFX_CONFIG_AABB +#endif + +/** + * Default GPP2 core configuraton on NB #0/1/2/3. + * 2 x8 slot, GFX_CONFIG_AABB + * 1 x16 slot, GFX_CONFIG_AAAA + */ +#ifndef DEFAULT_GPP2_CONFIG +#define DEFAULT_GPP2_CONFIG GFX_CONFIG_AABB +#endif + +/** + * Default GPP3a core configuraton on NB #0/1/2/3. + * 4:2:0:0:0:0 - GPP_CONFIG_GPP420000, 0x1 + * 4:1:1:0:0:0 - GPP_CONFIG_GPP411000, 0x2 + * 2:2:2:0:0:0 - GPP_CONFIG_GPP222000, 0x3 + * 2:2:1:1:0:0 - GPP_CONFIG_GPP221100, 0x4 + * 2:1:1:1:1:0 - GPP_CONFIG_GPP211110, 0x5 + * 1:1:1:1:1:1 - GPP_CONFIG_GPP111111, 0x6 + */ +#ifndef DEFAULT_GPP3A_CONFIG +#define DEFAULT_GPP3A_CONFIG GPP_CONFIG_GPP111111 +#endif + + +/** + * Default HT Transmitter de-emphasis setting + */ +#ifndef DEFAULT_HT_DEEMPASIES +#define DEFAULT_HT_DEEMPASIES 0x3 +#endif + +/** + * Default APIC nterrupt base for IOAPIC + */ +#ifndef DEFAULT_APIC_INTERRUPT_BASE +#define DEFAULT_APIC_INTERRUPT_BASE 24 +#endif + + +#define DEFAULT_PLATFORM_CONFIG(name) \ + NB_PLATFORM_CONFIG name = { \ + DEFAULT_PORT_ENABLE_MAP, \ + DEFAULT_PORT_FORCE_GEN1, \ + DEFAULT_HOTPLUG_SUPPORT, \ + DEFAULT_HOTPLUG_DESCRIPTOR, \ + DEFAULT_TEMPMMIO_BASE_ADDRESS, \ + DEFAULT_GPP1_CONFIG, \ + DEFAULT_GPP2_CONFIG, \ + DEFAULT_GPP3A_CONFIG, \ + DEFAULT_HT_DEEMPASIES, \ + /*DEFAULT_HT_PATH,*/ \ + DEFAULT_APIC_INTERRUPT_BASE, \ + } + +/** + * Platform configuration + */ +typedef struct { + UINT16 PortEnableMap; ///< Bitmap of enabled ports + UINT16 PortGen1Map; ///< Bitmap of ports to disable Gen2 + UINT16 PortHotplugMap; ///< Bitmap of ports support hotplug + UINT8 PortHotplugDescriptors[8];///< Ports Hotplug descriptors + UINT32 TemporaryMmio; ///< Temporary MMIO + UINT32 Gpp1Config; ///< Default PCIe GFX core configuration + UINT32 Gpp2Config; ///< Default PCIe GPP2 core configuration + UINT32 Gpp3aConfig; ///< Default PCIe GPP3a core configuration + UINT8 NbTransmitterDeemphasis; ///< HT transmitter de-emphasis level + // HT_PATH NbHtPath; ///< HT path to NB + UINT8 GlobalApicInterruptBase; ///< Global APIC interrupt base that is used in MADT table for IO APIC. +} NB_PLATFORM_CONFIG; + +/** + * Bridge CIMx configuration + */ +void rd890_cimx_config(AMD_NB_CONFIG_BLOCK *pConfig, NB_CONFIG *nbConfig, HT_CONFIG *htConfig, PCIE_CONFIG *pcieConfig); + +#endif //_RD890_CFG_H_ diff --git a/src/mainboard/supermicro/h8qgi/reset.c b/src/mainboard/supermicro/h8qgi/reset.c new file mode 100644 index 0000000..68a39f2 --- /dev/null +++ b/src/mainboard/supermicro/h8qgi/reset.c @@ -0,0 +1,66 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include <reset.h> +#include <arch/io.h> /*inb, outb*/ +#include <arch/romcc_io.h> /*pci_read_config32, device_t, PCI_DEV*/ + +#define HT_INIT_CONTROL 0x6C +#define HTIC_BIOSR_Detect (1<<5) + +#if CONFIG_MAX_PHYSICAL_CPUS > 32 +#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) +#else +#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) +#endif + +static inline void set_bios_reset(void) +{ + u32 nodes; + u32 htic; + device_t dev; + int i; + + nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; + for(i = 0; i < nodes; i++) { + dev = NODE_PCI(i, 0); + htic = pci_read_config32(dev, HT_INIT_CONTROL); + htic &= ~HTIC_BIOSR_Detect; + pci_write_config32(dev, HT_INIT_CONTROL, htic); + } +} + +void hard_reset(void) +{ + set_bios_reset(); + /* Try rebooting through port 0xcf9 */ + /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ + outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); + outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); +} + +//SbReset(); +void soft_reset(void) +{ + set_bios_reset(); + /* link reset */ + outb(0x06, 0x0cf9); +} + diff --git a/src/mainboard/supermicro/h8qgi/romstage.c b/src/mainboard/supermicro/h8qgi/romstage.c index 08b0eb2..119593e 100644 --- a/src/mainboard/supermicro/h8qgi/romstage.c +++ b/src/mainboard/supermicro/h8qgi/romstage.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -29,34 +29,54 @@ #include "cpu/x86/lapic/boot_cpu.c" #include "agesawrapper.h" #include "northbridge/amd/agesa/family10/reset_test.h" -#include "southbridge/amd/sr5650/sr5650.h" -#include "southbridge/amd/sb700/sb700.h" +#include <nb_cimx.h> +#include <sb_cimx.h> #include "superio/nuvoton/wpcm450/wpcm450.h" +#include "superio/winbond/w83627dhg/w83627dhg.h" extern void disable_cache_as_ram(void); /* cache_as_ram.inc */ +//TODO: should not put here +static void sb7xx_51xx_enable_wideio(u8 wio_index, u16 base) +{ + /* TODO: Now assume wio_index=0 */ + device_t dev; + u8 reg8; + + //dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */ + dev = PCI_DEV(0, 0x14, 3); /* LPC Controller */ + pci_write_config32(dev, 0x64, base); + reg8 = pci_read_config8(dev, 0x48); + reg8 |= 1 << 2; + pci_write_config8(dev, 0x48, reg8); +} + +static void sb7xx_51xx_disable_wideio(u8 wio_index) +{ + /* TODO: Now assume wio_index=0 */ + device_t dev; + u8 reg8; + + //dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */ + dev = PCI_DEV(0, 0x14, 3); /* LPC Controller */ + pci_write_config32(dev, 0x64, 0); + reg8 = pci_read_config8(dev, 0x48); + reg8 &= ~(1 << 2); + pci_write_config8(dev, 0x48, reg8); +} + void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; + post_code(0x30); agesawrapper_amdinitmmio(); - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - /* SR56x0 pcie bridges block pci_locate_device() before pcie training. - * disable all pcie bridges on SR56x0 to work around it - */ - sr5650_disable_pcie_bridge(); - post_code(0x31); - sb7xx_51xx_lpc_port80(); - post_code(0x32); - } + post_code(0x31); /* Halt if there was a built in self test failure */ post_code(0x33); report_bist_failure(bist); - enable_sr5650_dev8(); - sb7xx_51xx_lpc_init(); sb7xx_51xx_enable_wideio(0, 0x1600); /* though UARTs are on the NUVOTON BMC */ wpcm450_enable_dev(WPCM450_SP1, CONFIG_SIO_PORT, CONFIG_TTYS0_BASE); sb7xx_51xx_disable_wideio(0); @@ -78,7 +98,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "agesawrapper_amdinitreset passed\n"); } - post_code(0x38); + if (!cpu_init_detectedx && boot_cpu()) { + post_code(0x38); + /* + * SR5650/5670/5690 RD890 chipset, read pci config space hang at POR, + * Disable all Pcie Bridges to work around It. + */ + sr56x0_rd890_disable_pcie_bridge(); + post_code(0x39); + nb_Poweron_Init(); + post_code(0x3A); + sb_Poweron_Init(); + } + post_code(0x3B); val = agesawrapper_amdinitearly(); if(val) { printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val); @@ -86,12 +118,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "agesawrapper_amdinitearly passed\n"); } - sr5650_early_setup(); - post_code(0x39); - - sb7xx_51xx_early_setup(); - sr5650_htinit(); - /* Reset for HT, FIDVID, PLL and errata changes to take affect. */ + post_code(0x3C); + nb_Ht_Init(); + post_code(0x3D); + /* Reset for HT, FIDVID, PLL and ucode patch(errata) changes to take affect. */ if (!warm_reset_detect(0)) { print_info("...WARM RESET...\n\n\n"); distinguish_cpu_resets(0); @@ -103,8 +133,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) val = agesawrapper_amdinitpost(); if (val) { printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val); + } else { + printk(BIOS_DEBUG, "agesawrapper_amdinitpost passed\n"); } - printk(BIOS_DEBUG, "agesawrapper_amdinitpost passed\n"); post_code(0x41); val = agesawrapper_amdinitenv(); @@ -114,8 +145,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "agesawrapper_amdinitenv passed\n"); post_code(0x42); - sr5650_before_pci_init(); - sb7xx_51xx_before_pci_init(); post_code(0x50); print_debug("Disabling cache as ram "); diff --git a/src/mainboard/supermicro/h8qgi/sb700_cfg.c b/src/mainboard/supermicro/h8qgi/sb700_cfg.c new file mode 100644 index 0000000..4cbb8ca --- /dev/null +++ b/src/mainboard/supermicro/h8qgi/sb700_cfg.c @@ -0,0 +1,142 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include <string.h> +#include <console/console.h> /* printk */ +#include "Platform.h" +#include "sb700_cfg.h" + + +/** + * @brief South Bridge CIMx configuration + * + * should be called before exeucte CIMx function. + * this function will be called in romstage and ramstage. + */ +void sb700_cimx_config(AMDSBCFG *sb_config) +{ + if (!sb_config) { + printk(BIOS_DEBUG, "SB700 - Cfg.c - sb700_cimx_config - No sb_config.\n"); + return; + } + printk(BIOS_DEBUG, "SB700 - Cfg.c - sb700_cimx_config - Start.\n"); + memset(sb_config, 0, sizeof(AMDSBCFG)); + + /* SB_POWERON_INIT */ + sb_config->StdHeader.Func = SB_POWERON_INIT; + + /* header */ + sb_config->StdHeader.pPcieBase = PCIEX_BASE_ADDRESS; + + /* static Build Parameters */ + sb_config->BuildParameters.BiosSize = BIOS_SIZE; + sb_config->BuildParameters.LegacyFree = LEGACY_FREE; + sb_config->BuildParameters.EcKbd = 0; + sb_config->BuildParameters.EcChannel0 = 0; + sb_config->BuildParameters.Smbus0BaseAddress = SMBUS0_BASE_ADDRESS; + sb_config->BuildParameters.Smbus1BaseAddress = SMBUS1_BASE_ADDRESS; + sb_config->BuildParameters.SioPmeBaseAddress = SIO_PME_BASE_ADDRESS; + sb_config->BuildParameters.WatchDogTimerBase = WATCHDOG_TIMER_BASE_ADDRESS; + sb_config->BuildParameters.SpiRomBaseAddress = SPI_BASE_ADDRESS; + + sb_config->BuildParameters.AcpiPm1EvtBlkAddr = PM1_EVT_BLK_ADDRESS; + sb_config->BuildParameters.AcpiPm1CntBlkAddr = PM1_CNT_BLK_ADDRESS; + sb_config->BuildParameters.AcpiPmTmrBlkAddr = PM1_TMR_BLK_ADDRESS; + sb_config->BuildParameters.CpuControlBlkAddr = CPU_CNT_BLK_ADDRESS; + sb_config->BuildParameters.AcpiGpe0BlkAddr = GPE0_BLK_ADDRESS; + sb_config->BuildParameters.SmiCmdPortAddr = SMI_CMD_PORT; + sb_config->BuildParameters.AcpiPmaCntBlkAddr = ACPI_PMA_CNT_BLK_ADDRESS; + + sb_config->BuildParameters.SataIDESsid = SATA_IDE_MODE_SSID; + sb_config->BuildParameters.SataRAIDSsid = SATA_RAID_MODE_SSID; + sb_config->BuildParameters.SataRAID5Ssid = SATA_RAID5_MODE_SSID; + sb_config->BuildParameters.SataAHCISsid = SATA_AHCI_SSID; + sb_config->BuildParameters.Ohci0Ssid = OHCI0_SSID; + sb_config->BuildParameters.Ohci1Ssid = OHCI1_SSID; + sb_config->BuildParameters.Ohci2Ssid = OHCI2_SSID; + sb_config->BuildParameters.Ohci3Ssid = OHCI3_SSID; + sb_config->BuildParameters.Ohci4Ssid = OHCI4_SSID; + sb_config->BuildParameters.Ehci0Ssid = EHCI0_SSID; + sb_config->BuildParameters.Ehci1Ssid = EHCI1_SSID; + sb_config->BuildParameters.SmbusSsid = SMBUS_SSID; + sb_config->BuildParameters.IdeSsid = IDE_SSID; + sb_config->BuildParameters.AzaliaSsid = AZALIA_SSID; + sb_config->BuildParameters.LpcSsid = LPC_SSID; + + sb_config->BuildParameters.HpetBase = HPET_BASE_ADDRESS; + + /* General */ + sb_config->Spi33Mhz = 1; + sb_config->SpreadSpectrum = 0; + sb_config->PciClk5 = 0; + sb_config->PciClks = 0x1F; + sb_config->ResetCpuOnSyncFlood = 1; // Do not reset CPU on sync flood + sb_config->TimerClockSource = 2; // Auto + sb_config->S3Resume = 0; + sb_config->RebootRequired = 0; + + /* HPET */ + sb_config->HpetTimer = HPET_TIMER; + + /* USB */ + sb_config->UsbIntClock = 0; // Use external clock + sb_config->Usb1Ohci0 = 1; //0:disable 1:enable Bus 0 Dev 18 Func0 + sb_config->Usb1Ohci1 = 1; //0:disable 1:enable Bus 0 Dev 18 Func1 + sb_config->Usb1Ehci = 1; //0:disable 1:enable Bus 0 Dev 18 Func2 + sb_config->Usb2Ohci0 = 1; //0:disable 1:enable Bus 0 Dev 19 Func0 + sb_config->Usb2Ohci1 = 1; //0:disable 1:enable Bus 0 Dev 19 Func1 + sb_config->Usb2Ehci = 1; //0:disable 1:enable Bus 0 Dev 19 Func2 + sb_config->Usb3Ohci = 1; //0:disable 1:enable Bus 0 Dev 20 Func5 + sb_config->UsbOhciLegacyEmulation = 1; //0:Enable 1:Disable + + sb_config->AcpiS1Supported = 1; + + /* SATA */ + sb_config->SataController = 1; + sb_config->SataClass = CONFIG_SATA_CONTROLLER_MODE; //0 native, 1 raid, 2 ahci + sb_config->SataSmbus = 0; + sb_config->SataAggrLinkPmCap = 1; + sb_config->SataPortMultCap = 1; + sb_config->SataClkAutoOff = 1; + sb_config->SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary, 1 -IDE as secondary. + //TODO: set to secondary not take effect. + sb_config->SataIdeCombinedMode = 0; //1 IDE controlor exposed and combined mode enabled, 0 disabled + sb_config->SataEspPort = 0; + sb_config->SataClkAutoOffAhciMode = 1; + sb_config->SataHpcpButNonESP = 0; + sb_config->SataHideUnusedPort = 0; + + /* Azalia HDA */ + sb_config->AzaliaController = AZALIA_CONTROLLER; + sb_config->AzaliaPinCfg = AZALIA_PIN_CONFIG; + sb_config->AzaliaSdin0 = AZALIA_SDIN_PIN; + sb_config->pAzaliaOemCodecTablePtr = NULL; + +#ifndef __PRE_RAM__ + /* ramstage cimx config here */ + if (!sb_config->StdHeader.pCallBack) { + sb_config->StdHeader.pCallBack = sb700_callout_entry; + } + + //sb_config-> +#endif //!__PRE_RAM__ + printk(BIOS_DEBUG, "SB700 - Cfg.c - sb700_cimx_config - End.\n"); +} + diff --git a/src/mainboard/supermicro/h8qgi/sb700_cfg.h b/src/mainboard/supermicro/h8qgi/sb700_cfg.h new file mode 100644 index 0000000..aac61ec --- /dev/null +++ b/src/mainboard/supermicro/h8qgi/sb700_cfg.h @@ -0,0 +1,237 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#ifndef _SB700_CFG_H_ +#define _SB700_CFG_H_ + +#include <stdint.h> + + +/** + * @def BIOS_SIZE_1M + * @def BIOS_SIZE_2M + * @def BIOS_SIZE_4M + * @def BIOS_SIZE_8M + */ +#define BIOS_SIZE_1M 0 +#define BIOS_SIZE_2M 1 +#define BIOS_SIZE_4M 3 +#define BIOS_SIZE_8M 7 + +/* In SB700, default ROM size is 1M Bytes, if your platform ROM + * bigger than 1M you have to set the ROM size outside CIMx module and + * before AGESA module get call. + */ +#ifndef BIOS_SIZE +#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1 +#define BIOS_SIZE BIOS_SIZE_1M +#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1 +#define BIOS_SIZE BIOS_SIZE_2M +#elif CONFIG_COREBOOT_ROMSIZE_KB_4096 == 1 +#define BIOS_SIZE BIOS_SIZE_4M +#elif CONFIG_COREBOOT_ROMSIZE_KB_8192 == 1 +#define BIOS_SIZE BIOS_SIZE_8M +#endif +#endif + +/** + * @def SPREAD_SPECTRUM + * @brief + * 0 - Disable Spread Spectrum function + * 1 - Enable Spread Spectrum function + */ +#define SPREAD_SPECTRUM 0 + +/** + * @def SB_HPET_TIMER + * @breif + * 0 - Disable hpet + * 1 - Enable hpet + */ +#define HPET_TIMER 1 + +/** + * @def USB_CONFIG + * @brief bit[0-6] used to control USB + * 0 - Disable + * 1 - Enable + * Usb Ohci1 Contoller (Bus 0 Dev 18 Func0) is define at BIT0 + * Usb Ehci1 Contoller (Bus 0 Dev 18 Func2) is define at BIT1 + * Usb Ohci2 Contoller (Bus 0 Dev 19 Func0) is define at BIT2 + * Usb Ehci2 Contoller (Bus 0 Dev 19 Func2) is define at BIT3 + * Usb Ohci3 Contoller (Bus 0 Dev 22 Func0) is define at BIT4 + * Usb Ehci3 Contoller (Bus 0 Dev 22 Func2) is define at BIT5 + * Usb Ohci4 Contoller (Bus 0 Dev 20 Func5) is define at BIT6 + */ +#define USB_CINFIG 0x7F + +/** + * @def PCI_CLOCK_CTRL + * @breif bit[0-4] used for PCI Slots Clock Control, + * 0 - disable + * 1 - enable + * PCI SLOT 0 define at BIT0 + * PCI SLOT 1 define at BIT1 + * PCI SLOT 2 define at BIT2 + * PCI SLOT 3 define at BIT3 + * PCI SLOT 4 define at BIT4 + */ +#define PCI_CLOCK_CTRL 0x1F + +/** + * @def SATA_CONTROLLER + * @breif INCHIP Sata Controller + */ +#ifndef SATA_CONTROLLER +#define SATA_CONTROLLER 1 +#endif + +/** + * @def SATA_MODE + * @breif INCHIP Sata Controller Mode + * NOTE: DO NOT ALLOW SATA & IDE use same mode + */ +#ifndef SATA_MODE +#define SATA_MODE NATIVE_IDE_MODE +#endif + +/** + * @breif INCHIP Sata IDE Controller Mode + */ +#define IDE_LEGACY_MODE 0 +#define IDE_NATIVE_MODE 1 + +/** + * @def SATA_IDE_MODE + * @breif INCHIP Sata IDE Controller Mode + * NOTE: DO NOT ALLOW SATA & IDE use same mode + */ +#ifndef SATA_IDE_MODE +#define SATA_IDE_MODE IDE_LEGACY_MODE +#endif + +/** + * @def EXTERNAL_CLOCK + * @brief 00/10: Reference clock from crystal oscillator via + * PAD_XTALI and PAD_XTALO + * + * @def INTERNAL_CLOCK + * @brief 01/11: Reference clock from internal clock through + * CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL + */ +#define EXTERNAL_CLOCK 0x00 +#define INTERNAL_CLOCK 0x01 + +#define SATA_CLOCK_SOURCE EXTERNAL_CLOCK + +/** + * @def SATA_PORT_MULT_CAP_RESERVED + * @brief 1 ON, 0 0FF + */ +#define SATA_PORT_MULT_CAP_RESERVED 1 + + +/** + * @def AZALIA_AUTO + * @brief Detect Azalia controller automatically. + * + * @def AZALIA_DISABLE + * @brief Disable Azalia controller. + + * @def AZALIA_ENABLE + * @brief Enable Azalia controller. + */ +#define AZALIA_AUTO 0 +#define AZALIA_DISABLE 1 +#define AZALIA_ENABLE 2 + +/** + * @breif INCHIP HDA controller + */ +#ifndef AZALIA_CONTROLLER +#define AZALIA_CONTROLLER AZALIA_AUTO +#endif + +/** + * @def AZALIA_PIN_CONFIG + * @brief + * 0 - disable + * 1 - enable + */ +#ifndef AZALIA_PIN_CONFIG +#define AZALIA_PIN_CONFIG 1 +#endif + +/** + * @def AZALIA_SDIN_PIN + * @brief + * SDIN0 is define at BIT0 & BIT1 + * 00 - GPIO PIN + * 01 - Reserved + * 10 - As a Azalia SDIN pin + * SDIN1 is define at BIT2 & BIT3 + * SDIN2 is define at BIT4 & BIT5 + * SDIN3 is define at BIT6 & BIT7 + */ +#ifndef AZALIA_SDIN_PIN +//#define AZALIA_SDIN_PIN 0xAA +#define AZALIA_SDIN_PIN 0x2A +#endif + +/** + * @def GPP_CONTROLLER + */ +#ifndef GPP_CONTROLLER +#define GPP_CONTROLLER 1 +#endif + +/** + * @def GPP_CFGMODE + * @brief GPP Link Configuration + * four possible configuration: + * GPP_CFGMODE_X4000 + * GPP_CFGMODE_X2200 + * GPP_CFGMODE_X2110 + * GPP_CFGMODE_X1111 + */ +#ifndef GPP_CFGMODE +#define GPP_CFGMODE GPP_CFGMODE_X1111 +#endif + + +/** + * @brief South Bridge CIMx configuration + * + */ +void sb700_cimx_config(AMDSBCFG *sb_cfg); + +/** + * @brief Entry point of Southbridge CIMx callout + * + * prototype UINT32 (*SBCIM_HOOK_ENTRY)(UINT32 Param1, UINT32 Param2, void* pConfig) + * + * @param[in] func Southbridge CIMx Function ID. + * @param[in] data Southbridge Input Data. + * @param[in] sb_cfg Southbridge configuration structure pointer. + * + */ +u32 sb700_callout_entry(u32 func, u32 data, void* sb_cfg); + +#endif //_SB700_CFG_H_

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New patch to review for coreboot: f81d7bd i3100: configure pci irqs
by Sven Schnelle 01 Feb '12

01 Feb '12

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/603 -gerrit commit f81d7bd250944c585a0cdcdf614f4ba4878b22db Author: Sven Schnelle <svens(a)stackframe.org> Date: Wed Feb 1 11:47:29 2012 +0100 i3100: configure pci irqs without it, you can't boot from PCI devices like scsi controllers which require an interrupt set. So preconfigure all pci devices. Change-Id: I2cd781227701e8363d83bd90e0e36994359fc194 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/southbridge/intel/i3100/lpc.c | 46 +++++++++++++++++++++++++++++++++--- 1 files changed, 42 insertions(+), 4 deletions(-) diff --git a/src/southbridge/intel/i3100/lpc.c b/src/southbridge/intel/i3100/lpc.c index 1544ecd..2dcdb04 100644 --- a/src/southbridge/intel/i3100/lpc.c +++ b/src/southbridge/intel/i3100/lpc.c @@ -28,6 +28,7 @@ #include <device/pci_ops.h> #include <pc80/mc146818rtc.h> #include <pc80/isa-dma.h> +#include <pc80/i8259.h> #include <arch/io.h> #include <arch/ioapic.h> #include "i3100.h" @@ -196,17 +197,51 @@ static void set_i3100_gpio_inv( static void i3100_pirq_init(device_t dev) { + device_t irq_dev; config_t *config; /* Get the chip configuration */ config = dev->chip_info; - if(config->pirq_a_d) { + if(config->pirq_a_d) pci_write_config32(dev, 0x60, config->pirq_a_d); - } - if(config->pirq_e_h) { + + if(config->pirq_e_h) pci_write_config32(dev, 0x68, config->pirq_e_h); - } + + for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { + u8 int_pin=0, int_line=0; + + if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) + continue; + + int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); + switch (int_pin) { + case 1: /* INTA# */ + int_line = config->pirq_a_d & 0xff; + break; + + case 2: /* INTB# */ + int_line = (config->pirq_a_d >> 8) & 0xff; + break; + + case 3: /* INTC# */ + int_line = (config->pirq_a_d >> 16) & 0xff; + break; + + case 4: /* INTD# */ + int_line = (config->pirq_a_d >> 24) & 0xff; + break; + } + + if (!int_line) + continue; + + printk(BIOS_DEBUG, "%s: irq pin %d, irq line %d\n", dev_path(irq_dev), int_pin, int_line); + pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line); + } + + } static void i3100_power_options(device_t dev) { @@ -343,6 +378,9 @@ static void lpc_init(struct device *dev) /* Initialize isa dma */ isa_dma_init(); + + setup_i8259(); + i8259_configure_irq_trigger(9, 1); } static void i3100_lpc_read_resources(device_t dev)

1 0

Patch set updated for coreboot: 924ba67 H8QGI: Increase xip size of supermicro/h8qgi from 512K to 1M Bytes.
by Kerry Sheh 31 Jan '12

31 Jan '12

Kerry Sheh (shekairui(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/568 -gerrit commit 924ba67980e3674deca16d39b960198357ebabbc Author: Kerry Sheh <shekairui(a)gmail.com> Date: Wed Feb 1 13:59:30 2012 +0800 H8QGI: Increase xip size of supermicro/h8qgi from 512K to 1M Bytes. For mainboard using AMD AGESA framework, lots of AGESA code will be compiled into romstage, so romstage becomes larger, especially for mainboard support 2 or more processor families. H8QGI support both f10 and f15 CPUs, 512K default xip size is not enough, so increase to 1M Bytes. Change-Id: I1fb1aaad68aed8b41253a02cc0bc151c239b0dbe Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> --- src/mainboard/supermicro/h8qgi/Kconfig | 14 ++++++++++++++ 1 files changed, 14 insertions(+), 0 deletions(-) diff --git a/src/mainboard/supermicro/h8qgi/Kconfig b/src/mainboard/supermicro/h8qgi/Kconfig index e900ea8..201df45 100644 --- a/src/mainboard/supermicro/h8qgi/Kconfig +++ b/src/mainboard/supermicro/h8qgi/Kconfig @@ -123,5 +123,19 @@ config VGA_BIOS_ID depends on VGA_BIOS default "102b,0532" +config XIP_ROM_BASE + hex + default 0xfff00000 + +config XIP_ROM_SIZE + hex + default 0x100000 + help + Overwride the default write through caching size as 1M Bytes. + On some AMD paltform, one socket support 2 kinds of processor family, + Compiling 2 cpu families agesa code will increase the romstage size. + In order to execute romstage in place on the flash rom, + more space is required to be set as write through caching. + endif # BOARD_SUPERMICRO_H8QGI

1 0

Patch set updated for coreboot: c298afa HWM: Nuvoton W83795G/ADG HWM support
by Kerry Sheh 31 Jan '12

31 Jan '12

Kerry Sheh (shekairui(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/569 -gerrit commit c298afadb883e6738cca4feca92e18e32a0ee335 Author: Kerry Sheh <shekairui(a)gmail.com> Date: Wed Feb 1 13:59:31 2012 +0800 HWM: Nuvoton W83795G/ADG HWM support Supermicro H8QGI-F 1 Unit Chassis contain 9 system Fans, they are controled by a separate W83795G Hardware Monitor chip. This patch adds Nuvoton W83795G/ADG HWM support. Change-Id: I8756f5ed02dc2fa0884cde36e51451fd8aacee27 Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> --- src/mainboard/supermicro/h8qgi/Makefile.inc | 1 + src/mainboard/supermicro/h8qgi/romstage.c | 9 + src/mainboard/supermicro/h8qgi/w83795.c | 236 +++++++++++++++++++++++++++ src/mainboard/supermicro/h8qgi/w83795.h | 75 +++++++++ 4 files changed, 321 insertions(+), 0 deletions(-) diff --git a/src/mainboard/supermicro/h8qgi/Makefile.inc b/src/mainboard/supermicro/h8qgi/Makefile.inc index 82264a4..ef81caf 100644 --- a/src/mainboard/supermicro/h8qgi/Makefile.inc +++ b/src/mainboard/supermicro/h8qgi/Makefile.inc @@ -17,6 +17,7 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # +romstage-y += w83795.c romstage-$(CONFIG_NORTHBRIDGE_AMD_CIMX_RD890) += rd890_cfg.c romstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += sb700_cfg.c romstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += reset.c diff --git a/src/mainboard/supermicro/h8qgi/romstage.c b/src/mainboard/supermicro/h8qgi/romstage.c index 119593e..4d48474 100644 --- a/src/mainboard/supermicro/h8qgi/romstage.c +++ b/src/mainboard/supermicro/h8qgi/romstage.c @@ -33,6 +33,7 @@ #include <sb_cimx.h> #include "superio/nuvoton/wpcm450/wpcm450.h" #include "superio/winbond/w83627dhg/w83627dhg.h" +#include "w83795.h" extern void disable_cache_as_ram(void); /* cache_as_ram.inc */ @@ -119,6 +120,14 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } post_code(0x3C); + /* W83627DHG pin89,90 function select is RSTOUT3#, RSTOUT2# by default. + * In order to access W83795G/ADG HWM using I2C protocol, + * we select function to SDA, SCL function (or GP33, GP32 function). + */ + w83627dhg_enable_i2c(PNP_DEV(0x2E, W83627DHG_SPI)); + w83795_init(THERMAL_CRUISE_MODE, DTS_SRC_AMD_SBTSI); + w83627dhg_enable_serial(PNP_DEV(0x2E, W83627DHG_SP1), CONFIG_TTYS0_BASE); + nb_Ht_Init(); post_code(0x3D); /* Reset for HT, FIDVID, PLL and ucode patch(errata) changes to take affect. */ diff --git a/src/mainboard/supermicro/h8qgi/w83795.c b/src/mainboard/supermicro/h8qgi/w83795.c new file mode 100644 index 0000000..22828db --- /dev/null +++ b/src/mainboard/supermicro/h8qgi/w83795.c @@ -0,0 +1,236 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <console/console.h> +#include "southbridge/amd/cimx/sb700/smbus.h" /*SMBUS_IO_BASE*/ +#include "w83795.h" + +static u32 w83795_set_bank(u8 bank) +{ + return do_smbus_write_byte(SMBUS_IO_BASE, W83795_DEV, W83795_REG_BANKSEL, bank); +} + +static u8 w83795_read(u16 reg) +{ + u32 ret; + + ret = w83795_set_bank(reg >> 8); + if (ret < 0) { + printk(BIOS_DEBUG, "read faild to set bank %x\n", reg >> 8); + return -1; + } + + ret = do_smbus_read_byte(SMBUS_IO_BASE, W83795_DEV, reg & 0xff); + return ret; +} + +static u8 w83795_write(u16 reg, u8 value) +{ + u32 err; + + err = w83795_set_bank(reg >> 8); + if (err < 0) { + printk(BIOS_DEBUG, "write faild to set bank %x\n", reg >> 8); + return -1; + } + + err = do_smbus_write_byte(SMBUS_IO_BASE, W83795_DEV, reg & 0xff, value); + return err; +} + +#if 0 +static void w83795_set_speed(void) +{ + +} + +static void w83795_set_ttti(void)//KR it works +{ + u32 i; + for (i = 0; i < 6; i++) { + //w83795_write(W83795_REG_TTTI(i), 0xa);//10 degree, default 40 + //w83795_write(W83795_REG_CTFS(i), 0x20);//32 degree, default 80 + } +} +#endif + +/* + * Enable Digital Temperature Sensor + */ +static void w83795_dts_enable(u8 dts_src) +{ + u8 val; + + /* DIS */ + val = w83795_read(W83795_REG_DTSC); + val |= (dts_src & 0x01); + w83795_write(W83795_REG_DTSC, val); + + /* DTSE */ + val = w83795_read(W83795_REG_DTSE); + val |= 0xFF; + w83795_write(W83795_REG_DTSE, val); + + /* store bank3 regs first before enable DTS */ + + /* + * TD/TR1-4 termal diode by default + * 0x00 Disable + * 0x01 thermistors on motherboard + * 0x10 different mode voltage + * 0x11 CPU internal thermal diode output + * + * TR5-6 thermistors by default TRn + */ + val = 0x55; /* thermal diode */ + w83795_write(W83795_REG_TEMP_CTRL2, val); + + /* Enable Digital Temperature Sensor */ + val = w83795_read(W83795_REG_TEMP_CTRL1); + val |= W83795_REG_TEMP_CTRL1_EN_DTS; /* EN_DTS */ + w83795_write(W83795_REG_TEMP_CTRL1, val); +} + +static void w83795_set_tfmr(w83795_fan_mode_t mode) +{ + u8 val; + u8 i; + + if ((mode == SMART_FAN_MODE) || (mode == THERMAL_CRUISE_MODE)) { + val = 0xFF; + } else { + val = 0x00; + } + + for (i = 0; i < 6; i++) + w83795_write(W83795_REG_TFMR(i), val); +} + +static u32 w83795_set_fan_mode(w83795_fan_mode_t mode) +{ + if (mode == SPEED_CRUISE_MODE) { + w83795_write(W83795_REG_FCMS1, 0xFF); + printk(BIOS_INFO, "W83795G/ADG work in Speed Cruise Mode\n"); + } else { + w83795_write(W83795_REG_FCMS1, 0x00); + if (mode == THERMAL_CRUISE_MODE) { + w83795_write(W83795_REG_FCMS2, 0x00); + printk(BIOS_INFO, "W83795G/ADG work in Thermal Cruise Mode\n"); + } else if (mode == SMART_FAN_MODE) { + w83795_write(W83795_REG_FCMS2, 0x3F); + printk(BIOS_INFO, "W83795G/ADG work in Smart Fan Mode\n"); + } else { + printk(BIOS_INFO, "W83795G/ADG work in Manual Mode\n"); + return -1; + } + } + + return 0; +} + +static void w83795_set_tss(void) +{ + u8 val; + + val = 0x00; + w83795_write(W83795_REG_TSS(0), val); /* Temp1, 2 */ + w83795_write(W83795_REG_TSS(1), val); /* Temp3, 4 */ + w83795_write(W83795_REG_TSS(2), val); /* Temp5, 6 */ +} + +static void w83795_set_fan(w83795_fan_mode_t mode) +{ + u8 i; + + /* select temperature sensor (TSS)*/ + w83795_set_tss(); + + /* select Temperature to Fan mapping Relationships (TFMR)*/ + w83795_set_tfmr(mode); + + /* set fan output controlled mode (FCMS)*/ + w83795_set_fan_mode(mode); + + /* Set Critical Temperature to Full Speed all fan (CTFS) */ + for (i = 0; i < 6; i++) { + w83795_write(W83795_REG_CTFS(i), 0x50); /* default 80 celsius degree */ + } + + if (mode == THERMAL_CRUISE_MODE) { + /* Set Target Temperature of Temperature Inputs (TTTI) */ + for (i = 0; i < 6; i++) { + w83795_write(W83795_REG_TTTI(i), 0x28); /* default 40 celsius degree */ + } + } else if (mode == SMART_FAN_MODE) { + /* Set the Relative Register-at SMART FAN IV Control Mode Table */ + //SFIV TODO + } + + /* Set Hystersis of Temperature (HT) */ +} + +void w83795_init(w83795_fan_mode_t mode, u8 dts_src) +{ + u8 i; + u8 val; + + if (do_smbus_read_byte(SMBUS_IO_BASE, W83795_DEV, 0x00) < 0) { + printk(BIOS_INFO, "W83795G/ADG Nuvoton H/W Monitor not found\n"); + return; + } + val = w83795_read(W83795_REG_CONFIG); + if ((val & W83795_REG_CONFIG_CONFIG48) == 0) + printk(BIOS_INFO, "Found 64 pin W83795G Nuvoton H/W Monitor\n"); + else if ((val & W83795_REG_CONFIG_CONFIG48) == 1) + printk(BIOS_INFO, "Found 48 pin W83795ADG Nuvoton H/W Monitor\n"); + + /* Reset */ + val |= W83795_REG_CONFIG_INIT; + w83795_write(W83795_REG_CONFIG, val); + + /* Fan monitoring setting */ + val = 0xFF; /* FAN1-FAN8 */ + w83795_write(W83795_REG_FANIN_CTRL1, val); + val = 0x3F; /* FAN9-FAN14 */ + w83795_write(W83795_REG_FANIN_CTRL2, val); + + /* enable monitoring operations */ + val = w83795_read(W83795_REG_CONFIG); + val |= W83795_REG_CONFIG_START; + w83795_write(W83795_REG_CONFIG, val); + + w83795_dts_enable(dts_src); + w83795_set_fan(mode); + + printk(BIOS_INFO, "Fan CTFS(celsius) TTTI(celsius)\n"); + for (i = 0; i < 6; i++) { + val = w83795_read(W83795_REG_CTFS(i)); + printk(BIOS_INFO, " %x %d", i, val); + val = w83795_read(W83795_REG_TTTI(i)); + printk(BIOS_INFO, " %d\n", val); + } + + /* Temperature ReadOut */ + for (i = 0; i < 9; i++) { + val = w83795_read(W83795_REG_DTS(i)); + printk(BIOS_DEBUG, "DTS%x ReadOut=%x \n", i, val); + } +} + diff --git a/src/mainboard/supermicro/h8qgi/w83795.h b/src/mainboard/supermicro/h8qgi/w83795.h new file mode 100644 index 0000000..abc4d62 --- /dev/null +++ b/src/mainboard/supermicro/h8qgi/w83795.h @@ -0,0 +1,75 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _W83795_H_ +#define _W83795_H_ + +#define W83795_DEV 0x2F /* Host I2c Addr (strap to addr1 addr0 1 1, 0x5E) */ + +#define W83795_REG_I2C_ADDR 0xFC +#define W83795_REG_BANKSEL 0x00 +#define W83795_REG_CONFIG 0x01 +#define W83795_REG_CONFIG_START 0x01 +#define W83795_REG_CONFIG_CONFIG48 0x04 +#define W83795_REG_CONFIG_INIT 0x80 + +#define W83795_REG_TEMP_CTRL1 0x04 /* Temperature Monitoring Control Register */ +#define W83795_REG_TEMP_CTRL2 0x05 /* Temperature Monitoring Control Register */ +#define W83795_REG_FANIN_CTRL1 0x06 +#define W83795_REG_FANIN_CTRL2 0x07 +#define W83795_REG_TEMP_CTRL1_EN_DTS 0x20 /* Enable DTS (Digital Temperature Sensor) interface from INTEL PECI or AMD SB-TSI. */ +#define DTS_SRC_INTEL_PECI (0 << 0) +#define DTS_SRC_AMD_SBTSI (1 << 0) + +#define W83795_REG_TSS(n) (0x209 + (n)) /* Temperature Source Selection Register */ +#define W83795_REG_TTTI(n) (0x260 + (n)) /* tarrget temperature W83795G/ADG will try to tune the fan output to keep */ +#define W83795_REG_CTFS(n) (0x268 + (n)) /* Critical Temperature to Full Speed all fan */ +#define W83795_REG_HT(n) (0x270 + (n)) /* Hystersis of Temperature */ +#define W83795_REG_DTSC 0x301 /* Digital Temperature Sensor Configuration */ + +#define W83795_REG_DTSE 0x302 /* Digital Temperature Sensor Enable */ +#define W83795_REG_DTS(n) (0x26 + (n)) +#define W83795_REG_VRLSB 0x3C + +#define W83795_TEMP_REG_TR1 0x21 +#define W83795_TEMP_REG_TR2 0x22 +#define W83795_TEMP_REG_TR3 0x23 +#define W83795_TEMP_REG_TR4 0x24 +#define W83795_TEMP_REG_TR5 0x1F +#define W83795_TEMP_REG_TR6 0x20 + +#define W83795_REG_FCMS1 0x201 +#define W83795_REG_FCMS2 0x208 +#define W83795_REG_TFMR(n) (0x202 + (n)) /*temperature to fam mappig*/ +#define W83795_REG_DFSP 0x20C + +#define W83795_REG_FTSH(n) (0x240 + (n) * 2) +#define W83795_REG_FTSL(n) (0x241 + (n) * 2) +#define W83795_REG_TFTS 0x250 + +typedef enum w83795_fan_mode { + SPEED_CRUISE_MODE, ///< Fan Speed Cruise mode keeps the fan speed in a specified range + THERMAL_CRUISE_MODE, ///< Thermal Cruise mode is an algorithm to control the fan speed to keep the temperature source around the TTTI + SMART_FAN_MODE, ///< Smart Fan mode offers 6 slopes to control the fan speed + MANUAL_MODE, ///< control manually +} w83795_fan_mode_t; + +void w83795_init(w83795_fan_mode_t mode, u8 dts_src); + +#endif

1 0

Patch set updated for coreboot: 4b5a0b1 RD890: AMD RD890/SR56X0 CIMX wrapper
by Kerry Sheh 31 Jan '12

31 Jan '12

Kerry Sheh (shekairui(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/559 -gerrit commit 4b5a0b16088db08659d5d7176b33977f7538b5f6 Author: Kerry Sheh <shekairui(a)gmail.com> Date: Wed Feb 1 13:55:12 2012 +0800 RD890: AMD RD890/SR56X0 CIMX wrapper Support AMD RD890 CIMX support AMD RD890TV, RX780, RD780, SR56x0, RD890 and 990FX chipsets. Change-Id: I39dc5fc316fbb465808bac48a13a49b7d867f04f Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> --- src/northbridge/amd/Kconfig | 1 + src/northbridge/amd/Makefile.inc | 1 + src/northbridge/amd/cimx/Kconfig | 24 ++ src/northbridge/amd/cimx/Makefile.inc | 20 ++ src/northbridge/amd/cimx/rd890/Kconfig | 33 +++ src/northbridge/amd/cimx/rd890/Makefile.inc | 25 ++ src/northbridge/amd/cimx/rd890/NbPlatform.h | 147 ++++++++++ src/northbridge/amd/cimx/rd890/amd.h | 385 +++++++++++++++++++++++++++ src/northbridge/amd/cimx/rd890/cbtypes.h | 71 +++++ src/northbridge/amd/cimx/rd890/chip.h | 38 +++ src/northbridge/amd/cimx/rd890/early.c | 113 ++++++++ src/northbridge/amd/cimx/rd890/late.c | 269 +++++++++++++++++++ src/northbridge/amd/cimx/rd890/nb_cimx.h | 44 +++ 13 files changed, 1171 insertions(+), 0 deletions(-) diff --git a/src/northbridge/amd/Kconfig b/src/northbridge/amd/Kconfig index 4a120ca..33e19c2 100644 --- a/src/northbridge/amd/Kconfig +++ b/src/northbridge/amd/Kconfig @@ -4,6 +4,7 @@ source src/northbridge/amd/gx2/Kconfig source src/northbridge/amd/amdfam10/Kconfig source src/northbridge/amd/lx/Kconfig source src/northbridge/amd/agesa/Kconfig +source src/northbridge/amd/cimx/Kconfig menu "HyperTransport setup" #could be implemented for K8 (NORTHBRIDGE_AMD_AMDK8) depends on (NORTHBRIDGE_AMD_AMDFAM10) && EXPERT diff --git a/src/northbridge/amd/Makefile.inc b/src/northbridge/amd/Makefile.inc index bf96b80..c438473 100644 --- a/src/northbridge/amd/Makefile.inc +++ b/src/northbridge/amd/Makefile.inc @@ -5,3 +5,4 @@ subdirs-$(CONFIG_NORTHBRIDGE_AMD_GX2) += gx2 subdirs-$(CONFIG_NORTHBRIDGE_AMD_LX) += lx subdirs-$(CONFIG_AMD_AGESA) += agesa +subdirs-$(CONFIG_AMD_NB_CIMX) += cimx diff --git a/src/northbridge/amd/cimx/Kconfig b/src/northbridge/amd/cimx/Kconfig new file mode 100644 index 0000000..6751bd4 --- /dev/null +++ b/src/northbridge/amd/cimx/Kconfig @@ -0,0 +1,24 @@ +# +# This file is part of the coreboot project. +# +#Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +config AMD_NB_CIMX + bool + default n + +source src/northbridge/amd/cimx/rd890/Kconfig diff --git a/src/northbridge/amd/cimx/Makefile.inc b/src/northbridge/amd/cimx/Makefile.inc new file mode 100644 index 0000000..80844c8 --- /dev/null +++ b/src/northbridge/amd/cimx/Makefile.inc @@ -0,0 +1,20 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +subdirs-$(CONFIG_NORTHBRIDGE_AMD_CIMX_RD890) += rd890 diff --git a/src/northbridge/amd/cimx/rd890/Kconfig b/src/northbridge/amd/cimx/rd890/Kconfig new file mode 100644 index 0000000..6731b60 --- /dev/null +++ b/src/northbridge/amd/cimx/rd890/Kconfig @@ -0,0 +1,33 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +config NORTHBRIDGE_AMD_CIMX_RD890 + bool + default n + select AMD_NB_CIMX + +config REDIRECT_NBCIMX_TRACE_TO_SERIAL + bool "Redirect AMD Northbridge CIMX Trace to serial console" + default n + depends on NORTHBRIDGE_AMD_CIMX_RD890 + help + This Option allows you to redirect the AMD Northbridge CIMX + Trace debug information to the serial console. + + Warning: Only enable this option when debuging or tracing AMD CIMX code. diff --git a/src/northbridge/amd/cimx/rd890/Makefile.inc b/src/northbridge/amd/cimx/rd890/Makefile.inc new file mode 100644 index 0000000..5eaefd1 --- /dev/null +++ b/src/northbridge/amd/cimx/rd890/Makefile.inc @@ -0,0 +1,25 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + + +# RD890 Platform Files +romstage-y += early.c + +ramstage-y += late.c + diff --git a/src/northbridge/amd/cimx/rd890/NbPlatform.h b/src/northbridge/amd/cimx/rd890/NbPlatform.h new file mode 100644 index 0000000..824057a --- /dev/null +++ b/src/northbridge/amd/cimx/rd890/NbPlatform.h @@ -0,0 +1,147 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _NB_PLATFORM_H_ +#define _NB_PLATFORM_H_ + +#define SERIAL_OUT_SUPPORT //enable serial output +#define CIMX_DEBUG + +#ifdef CIMX_DEBUG +#define CIMX_TRACE_SUPPORT +#define CIMX_ASSERT_SUPPORT +#endif + +#ifdef CIMX_TRACE_SUPPORT + #define CIMX_INIT_TRACE(Arguments) + #if CONFIG_REDIRECT_NBCIMX_TRACE_TO_SERIAL + #define TRACE_DATA(Ptr, Level) BIOS_DEBUG //always enable + #define CIMX_TRACE(Argument) do {do_printk Argument;} while (0) + #else + #define TRACE_DATA(Ptr, Level) + #define CIMX_TRACE(Argument) + #endif +#else + #define CIMX_TRACE(Argument) + #define CIMX_INIT_TRACE(Arguments) +#endif + +#ifdef CIMX_ASSERT_SUPPORT + #ifdef ASSERT + #undef ASSERT + #define ASSERT CIMX_ASSERT + #endif + #ifdef CIMX_TRACE_SUPPORT + #define CIMX_ASSERT(x) if(!(x)) {\ + LibAmdTraceDebug (CIMX_TRACE_ALL, (CHAR8 *)"ASSERT !!! "__FILE__" - line %d\n", __LINE__); \ + /*__asm {jmp $}; */\ + } + //#define IDS_HDT_CONSOLE(s, args...) do_printk(BIOS_DEBUG, s, ##args) + #else + #define CIMX_ASSERT(x) if(!(x)) {\ + /*__asm {jmp $}; */\ + } + #endif +#else + #define CIMX_ASSERT(x) +#endif + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +//#define STALL(Ptr, TimeUs, Flag) LibAmdSbStall(TimeUs) +#define STALL(Ptr, TimeUs, Flag) LibAmdSbStall(TimeUs, Ptr) + +#ifdef B2_IMAGE +#define REPORT_EVENT(Class, Info, Param1, Param2, Param3, Param4, CfgPtr) LibNbEventLog(Class, Info, Param1, Param2, Param3, Param4, CfgPtr) +#else +#define REPORT_EVENT(Class, Info, Param1, Param2, Param3, Param4, CfgPtr) +#endif + + + +// CIMX configuration parameters +//#define CIMX_B2_IMAGE_BASE_ADDRESS 0xFFF40000 +/** + * PCIEX_BASE_ADDRESS - Define PCIE base address + * + * @param[Option] MOVE_PCIEBAR_TO_F0000000 Set PCIe base address to 0xF7000000 + */ +#ifdef MOVE_PCIEBAR_TO_F0000000 +#define PCIEX_BASE_ADDRESS 0xF7000000 +#else +#define PCIEX_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS +#endif + + + +#define CIMX_S3_SAVE 1 +#include "cbtypes.h" +#include <console/console.h> + +#include "amd.h" //cimx typedef +#include <amdlib.h> +#include "amdAcpiLib.h" +#include "amdAcpiMadt.h" +#include "amdAcpiIvrs.h" +#include "amdSbLib.h" +#include "nbPcie.h" + +//must put before the nbType.h +#include "platform_cfg.h" /*platform dependented configuration */ +#include "nbType.h" + +#include "nbLib.h" +#include "nbDef.h" +#include "nbInit.h" +#include "nbHtInit.h" +#include "nbIommu.h" +#include "nbEventLog.h" +#include "nbRegisters.h" +#include "nbPcieAspm.h" +#include "nbPcieLinkWidth.h" +#include "nbPcieHotplug.h" +#include "nbPciePortRemap.h" +#include "nbPcieWorkarounds.h" +#include "nbPcieCplBuffers.h" +#include "nbPciePllControl.h" +#include "nbMiscInit.h" +#include "nbIoApic.h" +#include "nbPcieSb.h" +#include "nbRecovery.h" +#include "nbMaskedMemoryInit.h" + + +#define FIX_PTR_ADDR(x, y) x + +#define TRACE_ALWAYS 0xffffffff + +#define AmdNbDispatcher NULL + +#define CIMX_TRACE_ALL 0xFFFFFFFF +#define CIMX_NBPOR_TRACE 0xFFFFFFFF +#define CIMX_NBHT_TRACE 0xFFFFFFFF +#define CIMX_NBPCIE_TRACE 0xFFFFFFFF +#define CIMX_NB_TRACE 0xFFFFFFFF +#define CIMX_NBPCIE_MISC 0xFFFFFFFF + +#endif + diff --git a/src/northbridge/amd/cimx/rd890/amd.h b/src/northbridge/amd/cimx/rd890/amd.h new file mode 100644 index 0000000..d99f90f --- /dev/null +++ b/src/northbridge/amd/cimx/rd890/amd.h @@ -0,0 +1,385 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _AMD_H_ +#define _AMD_H_ + +#include "cbtypes.h" + + +#define VOLATILE volatile +#define CALLCONV +#define ROMDATA +#define CIMXAPI EFIAPI + +// +// +// AGESA Types and Definitions +// +// +#ifndef NULL + #define NULL 0 +#endif + + +#define LAST_ENTRY 0xFFFFFFFF +#define IOCF8 0xCF8 +#define IOCFC 0xCFC +#define IN +#define OUT +#define IMAGE_SIGNATURE 'DMA$' + +typedef UINTN AGESA_STATUS; + + +#define AGESA_SUCCESS ((AGESA_STATUS) 0x0) +#define AGESA_ALERT ((AGESA_STATUS) 0x40000000) +#define AGESA_WARNING ((AGESA_STATUS) 0x40000001) +#define AGESA_UNSUPPORTED ((AGESA_STATUS) 0x80000003) +#define AGESA_ERROR ((AGESA_STATUS) 0xC0000001) +#define AGESA_CRITICAL ((AGESA_STATUS) 0xC0000002) +#define AGESA_FATAL ((AGESA_STATUS) 0xC0000003) + +typedef AGESA_STATUS (*CALLOUT_ENTRY) (UINT32 Param1, UINTN Param2, VOID* ConfigPtr); +typedef AGESA_STATUS (*IMAGE_ENTRY) (IN OUT VOID* ConfigPtr); +typedef AGESA_STATUS (*MODULE_ENTRY) (IN OUT VOID* ConfigPtr); + +///This allocation type is used by the AmdCreateStruct entry point +typedef enum { + PreMemHeap = 0, ///< Create heap in cache. + PostMemDram, ///< Create heap in memory. + ByHost ///< Create heap by Host. +} ALLOCATION_METHOD; + +/// These width descriptors are used by the library function, and others, to specify the data size +typedef enum ACCESS_WIDTH { + AccessWidth8 = 1, ///< Access width is 8 bits. + AccessWidth16, ///< Access width is 16 bits. + AccessWidth32, ///< Access width is 32 bits. + AccessWidth64, ///< Access width is 64 bits. + + AccessS3SaveWidth8 = 0x81, ///< Save 8 bits data. + AccessS3SaveWidth16, ///< Save 16 bits data. + AccessS3SaveWidth32, ///< Save 32 bits data. + AccessS3SaveWidth64, ///< Save 64 bits data. +} ACCESS_WIDTH; + + +// AGESA Structures +/// The standard header AMD NB UEFI drivers +typedef struct _AMD_CONFIG_PARAMS { + VOID **PeiServices; ///< Pointer to PEI service table + VOID *StallPpi; ///< Pointer to Stall PPI +// UINT32 Func; + VOID *PcieBasePtr; ///< TBD + CALLOUT_ENTRY CalloutPtr; ///<pointer to local driver callback function + CALLOUT_ENTRY InterfaceCalloutPtr; ///<pointer to external interface driver callback function +} AMD_CONFIG_PARAMS; + + +/// AGESA Binary module header structure +typedef struct _AMD_IMAGE_HEADER { + IN UINT32 Signature; ///< Binary Signature + IN CHAR8 CreatorID[8]; ///< 8 characters ID + IN CHAR8 Version[12]; ///< 12 characters version + IN UINT32 ModuleInfoOffset; ///< Offset of module + IN UINT32 EntryPointAddress; ///< Entry address + IN UINT32 ImageBase; ///< Image base + IN UINT32 RelocTableOffset; ///< Relocate Table offset + IN UINT32 ImageSize; ///< Size + IN UINT16 Checksum; ///< Checksum + IN UINT8 ImageType; ///< Type + IN UINT8 V_Reserved; ///< Reserved +} AMD_IMAGE_HEADER; + + +/// AGESA Binary module header structure +typedef struct _AMD_MODULE_HEADER { + IN UINT32 ModuleHeaderSignature; ///< Module signature + IN CHAR8 ModuleIdentifier[8]; ///< 8 characters ID + IN CHAR8 ModuleVersion[12]; ///< 12 characters version + IN MODULE_ENTRY ModuleDispatcherPtr; ///< A pointer point to dispatcher + IN struct _AMD_MODULE_HEADER *NextBlockPtr; ///< Next module header link +} AMD_MODULE_HEADER; + +/// Extended PCI address format +typedef struct { + IN OUT UINT32 Register:12; ///< Register offset + IN OUT UINT32 Function:3; ///< Function number + IN OUT UINT32 Device:5; ///< Device number + IN OUT UINT32 Bus:8; ///< Bus number + IN OUT UINT32 Segment:4; ///< Segment +} EXT_PCI_ADDR; + +/// Union type for PCI address +typedef union _PCI_ADDR { + IN UINT32 AddressValue; ///< Formal address + IN EXT_PCI_ADDR Address; ///< Extended address +} PCI_ADDR; + +#define FUNC_0 0 // bit-placed for PCI address creation +#define FUNC_1 1 +#define FUNC_2 2 +#define FUNC_3 3 +#define FUNC_4 4 +#define FUNC_5 5 +#define FUNC_6 6 +#define FUNC_7 7 + +// SBDFO - Segment Bus Device Function Offset +// 31:28 Segment (4-bits) +// 27:20 Bus (8-bits) +// 19:15 Device (5-bits) +// 14:12 Function(3-bits) +// 11:00 Offset (12-bits) + +#define MAKE_SBDFO(Seg, Bus, Dev, Fun, Off) ((((UINT32) (Seg)) << 28) | (((UINT32) (Bus)) << 20) | \ + (((UINT32)(Dev)) << 15) | (((UINT32)(Fun)) << 12) | ((UINT32)(Off))) +#define ILLEGAL_SBDFO 0xFFFFFFFF + +/// CPUID data received registers format +typedef struct _CPUID_DATA { + IN OUT UINT32 EAX_Reg; ///< CPUID instruction result in EAX + IN OUT UINT32 EBX_Reg; ///< CPUID instruction result in EBX + IN OUT UINT32 ECX_Reg; ///< CPUID instruction result in ECX + IN OUT UINT32 EDX_Reg; ///< CPUID instruction result in EDX +} CPUID_DATA; + +#define WARM_RESET 1 +#define COLD_RESET 2 + +/// HT frequency for external callbacks +typedef enum { + HT_FREQUENCY_200M = 0, ///< HT speed 200 for external callbacks + HT_FREQUENCY_400M = 2, ///< HT speed 400 for external callbacks + HT_FREQUENCY_600M = 4, ///< HT speed 600 for external callbacks + HT_FREQUENCY_800M = 5, ///< HT speed 800 for external callbacks + HT_FREQUENCY_1000M = 6, ///< HT speed 1000 for external callbacks + HT_FREQUENCY_1200M = 7, ///< HT speed 1200 for external callbacks + HT_FREQUENCY_1400M = 8, ///< HT speed 1400 for external callbacks + HT_FREQUENCY_1600M = 9, ///< HT speed 1600 for external callbacks + HT_FREQUENCY_1800M = 10, ///< HT speed 1800 for external callbacks + HT_FREQUENCY_2000M = 11, ///< HT speed 2000 for external callbacks + HT_FREQUENCY_2200M = 12, ///< HT speed 2200 for external callbacks + HT_FREQUENCY_2400M = 13, ///< HT speed 2400 for external callbacks + HT_FREQUENCY_2600M = 14, ///< HT speed 2600 for external callbacks + HT_FREQUENCY_2800M = 17, ///< HT speed 2800 for external callbacks + HT_FREQUENCY_3000M = 18, ///< HT speed 3000 for external callbacks + HT_FREQUENCY_3200M = 19 ///< HT speed 3200 for external callbacks +} HT_FREQUENCIES; + +#ifndef BIT0 + #define BIT0 0x0000000000000001ull +#endif +#ifndef BIT1 + #define BIT1 0x0000000000000002ull +#endif +#ifndef BIT2 + #define BIT2 0x0000000000000004ull +#endif +#ifndef BIT3 + #define BIT3 0x0000000000000008ull +#endif +#ifndef BIT4 + #define BIT4 0x0000000000000010ull +#endif +#ifndef BIT5 + #define BIT5 0x0000000000000020ull +#endif +#ifndef BIT6 + #define BIT6 0x0000000000000040ull +#endif +#ifndef BIT7 + #define BIT7 0x0000000000000080ull +#endif +#ifndef BIT8 + #define BIT8 0x0000000000000100ull +#endif +#ifndef BIT9 + #define BIT9 0x0000000000000200ull +#endif +#ifndef BIT10 + #define BIT10 0x0000000000000400ull +#endif +#ifndef BIT11 + #define BIT11 0x0000000000000800ull +#endif +#ifndef BIT12 + #define BIT12 0x0000000000001000ull +#endif +#ifndef BIT13 + #define BIT13 0x0000000000002000ull +#endif +#ifndef BIT14 + #define BIT14 0x0000000000004000ull +#endif +#ifndef BIT15 + #define BIT15 0x0000000000008000ull +#endif +#ifndef BIT16 + #define BIT16 0x0000000000010000ull +#endif +#ifndef BIT17 + #define BIT17 0x0000000000020000ull +#endif +#ifndef BIT18 + #define BIT18 0x0000000000040000ull +#endif +#ifndef BIT19 + #define BIT19 0x0000000000080000ull +#endif +#ifndef BIT20 + #define BIT20 0x0000000000100000ull +#endif +#ifndef BIT21 + #define BIT21 0x0000000000200000ull +#endif +#ifndef BIT22 + #define BIT22 0x0000000000400000ull +#endif +#ifndef BIT23 + #define BIT23 0x0000000000800000ull +#endif +#ifndef BIT24 + #define BIT24 0x0000000001000000ull +#endif +#ifndef BIT25 + #define BIT25 0x0000000002000000ull +#endif +#ifndef BIT26 + #define BIT26 0x0000000004000000ull +#endif +#ifndef BIT27 + #define BIT27 0x0000000008000000ull +#endif +#ifndef BIT28 + #define BIT28 0x0000000010000000ull +#endif +#ifndef BIT29 + #define BIT29 0x0000000020000000ull +#endif +#ifndef BIT30 + #define BIT30 0x0000000040000000ull +#endif +#ifndef BIT31 + #define BIT31 0x0000000080000000ull +#endif +#ifndef BIT32 + #define BIT32 0x0000000100000000ull +#endif +#ifndef BIT33 + #define BIT33 0x0000000200000000ull +#endif +#ifndef BIT34 + #define BIT34 0x0000000400000000ull +#endif +#ifndef BIT35 + #define BIT35 0x0000000800000000ull +#endif +#ifndef BIT36 + #define BIT36 0x0000001000000000ull +#endif +#ifndef BIT37 + #define BIT37 0x0000002000000000ull +#endif +#ifndef BIT38 + #define BIT38 0x0000004000000000ull +#endif +#ifndef BIT39 + #define BIT39 0x0000008000000000ull +#endif +#ifndef BIT40 + #define BIT40 0x0000010000000000ull +#endif +#ifndef BIT41 + #define BIT41 0x0000020000000000ull +#endif +#ifndef BIT42 + #define BIT42 0x0000040000000000ull +#endif +#ifndef BIT43 + #define BIT43 0x0000080000000000ull +#endif +#ifndef BIT44 + #define BIT44 0x0000100000000000ull +#endif +#ifndef BIT45 + #define BIT45 0x0000200000000000ull +#endif +#ifndef BIT46 + #define BIT46 0x0000400000000000ull +#endif +#ifndef BIT47 + #define BIT47 0x0000800000000000ull +#endif +#ifndef BIT48 + #define BIT48 0x0001000000000000ull +#endif +#ifndef BIT49 + #define BIT49 0x0002000000000000ull +#endif +#ifndef BIT50 + #define BIT50 0x0004000000000000ull +#endif +#ifndef BIT51 + #define BIT51 0x0008000000000000ull +#endif +#ifndef BIT52 + #define BIT52 0x0010000000000000ull +#endif +#ifndef BIT53 + #define BIT53 0x0020000000000000ull +#endif +#ifndef BIT54 + #define BIT54 0x0040000000000000ull +#endif +#ifndef BIT55 + #define BIT55 0x0080000000000000ull +#endif +#ifndef BIT56 + #define BIT56 0x0100000000000000ull +#endif +#ifndef BIT57 + #define BIT57 0x0200000000000000ull +#endif +#ifndef BIT58 + #define BIT58 0x0400000000000000ull +#endif +#ifndef BIT59 + #define BIT59 0x0800000000000000ull +#endif +#ifndef BIT60 + #define BIT60 0x1000000000000000ull +#endif +#ifndef BIT61 + #define BIT61 0x2000000000000000ull +#endif +#ifndef BIT62 + #define BIT62 0x4000000000000000ull +#endif +#ifndef BIT63 + #define BIT63 0x8000000000000000ull +#endif + +#ifdef ASSERT + #undef ASSERT + #define ASSERT(x) +#endif + +#endif diff --git a/src/northbridge/amd/cimx/rd890/cbtypes.h b/src/northbridge/amd/cimx/rd890/cbtypes.h new file mode 100644 index 0000000..ade55d7 --- /dev/null +++ b/src/northbridge/amd/cimx/rd890/cbtypes.h @@ -0,0 +1,71 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 - 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _CBTYPES_H_ +#define _CBTYPES_H_ + +//#include <stdint.h> + +/* +typedef int64_t __int64; +typedef void VOID; +typedef uint32_t UINTN;// +typedef int8_t CHAR8; +typedef uint8_t UINT8; +typedef uint16_t UINT16; +typedef uint32_t UINT32; +typedef uint64_t UINT64; +*/ +typedef signed long long __int64; +typedef void VOID; +typedef unsigned int UINTN;// +typedef signed char CHAR8; +typedef unsigned char UINT8; +typedef unsigned short UINT16; +typedef unsigned int UINT32; +typedef signed int INT32; +typedef unsigned long long UINT64; + +#define TRUE 1 +#define FALSE 0 +typedef unsigned char BOOLEAN; + +#ifndef VOLATILE +#define VOLATILE volatile +#endif + +#ifndef IN +#define IN +#endif +#ifndef OUT +#define OUT +#endif + +//porting.h +#ifndef CONST +#define CONST const +#endif +#ifndef STATIC +#define STATIC static +#endif +#ifndef VOLATILE +#define VOLATILE volatile +#endif + +#endif diff --git a/src/northbridge/amd/cimx/rd890/chip.h b/src/northbridge/amd/cimx/rd890/chip.h new file mode 100644 index 0000000..c2f985b --- /dev/null +++ b/src/northbridge/amd/cimx/rd890/chip.h @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#ifndef _CIMX_RD890_CHIP_H_ +#define _CIMX_RD890_CHIP_H_ + +extern struct chip_operations northbridge_amd_cimx_rd890_ops; + +/** + * RD890 specific device configuration + */ +struct northbridge_amd_cimx_rd890_config +{ + u8 gpp1_configuration; + u8 gpp2_configuration; + u8 gpp3a_configuration; + u16 port_enable; +}; + +#endif /* _CIMX_RD890_CHIP_H_ */ + diff --git a/src/northbridge/amd/cimx/rd890/early.c b/src/northbridge/amd/cimx/rd890/early.c new file mode 100644 index 0000000..8008223 --- /dev/null +++ b/src/northbridge/amd/cimx/rd890/early.c @@ -0,0 +1,113 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include "NbPlatform.h" +#include "rd890_cfg.h" +#include "nb_cimx.h" + + +/** + * @brief disable GPP1 Port0,1, GPP2, GPP3a Port0,1,2,3,4,5, GPP3b + * + * SR5650/5670/5690 RD890 chipset, read pci config space hang at POR, + * Disable all Pcie Bridges to work around It. + */ +void sr56x0_rd890_disable_pcie_bridge(void) +{ + u32 nb_dev; + u32 mask; + u32 val; + AMD_NB_CONFIG_BLOCK cfg_block; + AMD_NB_CONFIG_BLOCK *cfg_ptr = &cfg_block; + AMD_NB_CONFIG *nb_cfg = &(cfg_block.Northbridges[0]); + + nb_cfg->ConfigPtr = &cfg_ptr; + nb_dev = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0); + val = (1 << 2) | (1 << 3); /*GPP1*/ + val |= (1 << 4) | (1 << 5) | (1 << 6) | (1 << 7) | (1 << 16) | (1 << 17); /*GPP3a*/ + val |= (1 << 18) | (1 << 19); /*GPP2*/ + val |= (1 << 20); /*GPP3b*/ + mask = ~val; + LibNbPciIndexRMW(nb_dev | NB_MISC_INDEX, NB_MISC_REG0C, + AccessS3SaveWidth32, + mask, + val, + nb_cfg); +} + + +/** + * @brief South Bridge CIMx romstage entry, + * wrapper of AmdPowerOnResetInit entry point. + */ +void nb_Poweron_Init(void) +{ + NB_CONFIG nb_cfg[MAX_NB_COUNT]; + HT_CONFIG ht_cfg[MAX_NB_COUNT]; + PCIE_CONFIG pcie_cfg[MAX_NB_COUNT]; + AMD_NB_CONFIG_BLOCK gConfig; + AMD_NB_CONFIG_BLOCK *ConfigPtr = &gConfig; + AGESA_STATUS status; + + printk(BIOS_DEBUG, "cimx/rd890 early.c %s() Start\n", __func__); + CIMX_INIT_TRACE(); + CIMX_TRACE((BIOS_DEBUG, "NbPowerOnResetInit entry\n")); + rd890_cimx_config(&gConfig, &nb_cfg[0], &ht_cfg[0], &pcie_cfg[0]); + + if (ConfigPtr->StandardHeader.CalloutPtr != NULL) { + ConfigPtr->StandardHeader.CalloutPtr(CB_AmdSetNbPorConfig, 0, &gConfig); + } + + status = AmdPowerOnResetInit(&gConfig); + printk(BIOS_DEBUG, "cimx/rd890 early.c %s() End. return status=%x\n", __func__, status); +} + +/** + * @brief South Bridge CIMx romstage entry, + * wrapper of AmdHtInit entry point. + */ +void nb_Ht_Init(void) +{ + AGESA_STATUS status; + NB_CONFIG nb_cfg[MAX_NB_COUNT]; + HT_CONFIG ht_cfg[MAX_NB_COUNT]; + PCIE_CONFIG pcie_cfg[MAX_NB_COUNT]; + AMD_NB_CONFIG_BLOCK gConfig; + AMD_NB_CONFIG_BLOCK *ConfigPtr = &gConfig; + u32 i; + + rd890_cimx_config(&gConfig, &nb_cfg[0], &ht_cfg[0], &pcie_cfg[0]); + + //Initialize HT structure + LibSystemApiCall(AmdHtInitializer, &gConfig); + for (i = 0; i < MAX_NB_COUNT; i ++) { + if (ConfigPtr->StandardHeader.CalloutPtr != NULL) { + ConfigPtr->StandardHeader.CalloutPtr(CB_AmdSetHtConfig, 0, (VOID*)&(gConfig.Northbridges[i])); + } + } + + status = LibSystemApiCall(AmdHtInit, &gConfig); + printk(BIOS_DEBUG, "AmdHtInit status: %x\n", status); +} + +void nb_S3_Init(void) +{ + //TODO +} diff --git a/src/northbridge/amd/cimx/rd890/late.c b/src/northbridge/amd/cimx/rd890/late.c new file mode 100644 index 0000000..62a842a --- /dev/null +++ b/src/northbridge/amd/cimx/rd890/late.c @@ -0,0 +1,269 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <console/console.h> +#include <device/device.h> +#include <arch/ioapic.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include "NbPlatform.h" +#include "nb_cimx.h" +#include "rd890_cfg.h" + + +/** + * Global RD890 CIMX Configuration structure + */ +static NB_CONFIG nb_cfg[MAX_NB_COUNT]; +static HT_CONFIG ht_cfg[MAX_NB_COUNT]; +static PCIE_CONFIG pcie_cfg[MAX_NB_COUNT]; +static AMD_NB_CONFIG_BLOCK gConfig; + + +/** + * Reset PCIE Cores, Training the Ports selected by port_enable of devicetree + * After this call EP are fully operational on particular NB + */ +void nb_Pcie_Early_Init(void) +{ + LibSystemApiCall(AmdPcieEarlyInit, &gConfig); //AmdPcieEarlyInit(&gConfig); +} + +void nb_Pcie_Late_Init(void) +{ + LibSystemApiCall(AmdPcieLateInit, &gConfig); +} + +void nb_Early_Post_Init(void) +{ + LibSystemApiCall(AmdEarlyPostInit, &gConfig); +} + +void nb_Mid_Post_Init(void) +{ + LibSystemApiCall(AmdMidPostInit, &gConfig); +} + +void nb_Late_Post_Init(void) +{ + LibSystemApiCall(AmdLatePostInit, &gConfig); +} + +static void rd890_enable(device_t dev) +{ + u32 address = 0; + u32 mask; + u32 val; + u32 devfn; + u32 port; + AMD_NB_CONFIG *NbConfigPtr = NULL; + + u8 nb_index = 0; /* The first IO Hub, TODO: other NBs */ + address = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0); + NbConfigPtr = &(gConfig.Northbridges[nb_index]); + + devfn = dev->path.pci.devfn; + port = devfn >> 3; + printk(BIOS_INFO, "rd890_enable "); + printk(BIOS_INFO, "Bus-%x Dev-%X Fun-%X, enable=%x\n", + 0, (devfn >> 3), (devfn & 0x07), dev->enabled); + if (port != 0) { + if (dev->enabled) { + NbConfigPtr->pPcieConfig->PortConfiguration[port].ForcePortDisable = OFF; + } else { + NbConfigPtr->pPcieConfig->PortConfiguration[port].ForcePortDisable = ON; + } + } + + switch (port) { + case 0x0: /* Root Complex, and ClkConfig */ + + if ((devfn & 0x07) == 1) { /* skip dev-0 fun-1 */ + break; + } + + /* CIMX configuration defualt initialize */ + rd890_cimx_config(&gConfig, &nb_cfg[0], &ht_cfg[0], &pcie_cfg[0]); + if (gConfig.StandardHeader.CalloutPtr != NULL) { + /* NOTE: not use LibNbCallBack */ + gConfig.StandardHeader.CalloutPtr(CB_AmdSetPcieEarlyConfig, (u32)dev, (VOID*)NbConfigPtr); + } + /* Reset PCIE Cores, Training the Ports selected by port_enable of devicetree + * After this call EP are fully operational on particular NB + */ + nb_Pcie_Early_Init(); + break; + + case 0x2: /* Gpp1 Port0 */ + case 0x3: /* Gpp1 Port1 */ + mask = ~(1 << port); + val = (dev->enabled ? 0 : 1) << port; + LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr); + break; + + case 0x4: /* Gpp3a Port0 */ + case 0x5: /* Gpp3a Port1 */ + case 0x6: /* Gpp3a Port2 */ + case 0x7: /* Gpp3a Port3 */ + mask = ~(1 << port); + val = (dev->enabled ? 0 : 1) << port; + LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr); + break; + + case 0x8: /* SB ALink */ + mask = ~(1 << 6); + val = (dev->enabled ? 1 : 0) << 6; + LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr); + break; + + case 0x9: /* Gpp3a Port4 */ + case 0xa: /* Gpp3a Port5 */ + mask = ~(1 << (7 + port)); + val = (dev->enabled ? 0 : 1) << (7 + port); + LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr); + break; + + case 0xb: /* Gpp2 Port0 */ + case 0xc: /* Gpp2 Port1 */ + mask = ~(1 << (7 + port)); + val = (dev->enabled ? 0 : 1) << (7 + port); + LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr); + break; + + case 0xd: /* Gpp3b */ + mask = ~(1 << (7 + port)); + val = (dev->enabled ? 0 : 1) << (7 + port); + LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr); + + /* Init NB at Early Post */ + if (gConfig.StandardHeader.CalloutPtr != NULL) { + gConfig.StandardHeader.CalloutPtr(CB_AmdSetEarlyPostConfig, 0, (VOID*)NbConfigPtr); + } + nb_Early_Post_Init();// + if (gConfig.StandardHeader.CalloutPtr != NULL) { + gConfig.StandardHeader.CalloutPtr(CB_AmdSetMidPostConfig, 0, (VOID*)NbConfigPtr); + } + nb_Mid_Post_Init(); + nb_Pcie_Late_Init(); + if (gConfig.StandardHeader.CalloutPtr != NULL) { + gConfig.StandardHeader.CalloutPtr(CB_AmdSetLatePostConfig, 0, (VOID*)NbConfigPtr); + } + nb_Late_Post_Init(); + break; + + default: + printk(BIOS_INFO, "Buggy Device Tree\n"); + break; + } +} + +struct chip_operations northbridge_amd_cimx_rd890_ops = { + CHIP_NAME("ATI rd890") + .enable_dev = rd890_enable, +}; + + +static void ioapic_init(struct device *dev) +{ + u32 ioapic_base; + + pci_write_config32(dev, 0xF8, 0x1); + ioapic_base = pci_read_config32(dev, 0xFC) & 0xfffffff0; + setup_ioapic(ioapic_base, 1); +} + +static void rd890_read_resource(struct device *dev) +{ + pci_dev_read_resources(dev); + + /* rpr6.2.(1). Write the Base Address Register (BAR) */ + pci_write_config32(dev, 0xF8, 0x1); /* set IOAPIC's index as 1 and make sure no one changes it. */ + pci_get_resource(dev, 0xFC); /* APIC located in sr5690 */ + + compact_resources(dev); +} + +/* If IOAPIC's index changes, we should replace the pci_dev_set_resource(). */ +static void rd890_set_resources(struct device *dev) +{ + pci_write_config32(dev, 0xF8, 0x1); /* set IOAPIC's index as 1 and make sure no one changes it. */ + pci_dev_set_resources(dev); +} + +static struct pci_operations lops_pci = { + .set_subsystem = pci_dev_set_subsystem, +}; + +static struct device_operations ht_ops = { + .read_resources = rd890_read_resource, + .set_resources = rd890_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = ioapic_init, + .scan_bus = 0, + .ops_pci = &lops_pci, +}; + +static const struct pci_driver ht_driver_sr5690 __pci_driver = { + .ops = &ht_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_AMD_SR5690_HT, +}; + +static const struct pci_driver ht_driver_sr5670 __pci_driver = { + .ops = &ht_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_AMD_SR5670_HT, +}; + +static const struct pci_driver ht_driver_sr5650 __pci_driver = { + .ops = &ht_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_AMD_SR5650_HT, +}; + +static const struct pci_driver ht_driver_rd890tv __pci_driver = { + .ops = &ht_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_AMD_RD890TV_HT, +}; + +static const struct pci_driver ht_driver_rx780 __pci_driver = { + .ops = &ht_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_AMD_RX780_HT, +}; + +static const struct pci_driver ht_driver_rd780 __pci_driver = { + .ops = &ht_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_AMD_RD780_HT, +}; + +static const struct pci_driver ht_driver_rd890 __pci_driver = { + .ops = &ht_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_AMD_RD890_HT, +}; + +static const struct pci_driver ht_driver_990fx __pci_driver = { + .ops = &ht_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_AMD_990FX_HT, +}; diff --git a/src/northbridge/amd/cimx/rd890/nb_cimx.h b/src/northbridge/amd/cimx/rd890/nb_cimx.h new file mode 100644 index 0000000..a6f77db --- /dev/null +++ b/src/northbridge/amd/cimx/rd890/nb_cimx.h @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _NB_CIMX_H_ +#define _NB_CIMX_H_ + +/** + * @brief disable GPP1 Port0,1, GPP2, GPP3a Port0,1,2,3,4,5, GPP3b + * + * SR5650/5670/5690 RD890 chipset, read pci config space hang at POR, + * Disable all Pcie Bridges to work around It. + */ +void sr56x0_rd890_disable_pcie_bridge(void); + +/** + * Northbridge CIMX entries point + */ +void nb_Poweron_Init(void); +void nb_Ht_Init(void); +void nb_S3_Init(void); +void nb_Early_Post_Init(void); +void nb_Mid_Post_Init(void); +void nb_Late_Post_Init(void); +void nb_Pcie_Early_Init(void); +void nb_Pcie_Late_Init(void); + +#endif//_RD890_EARLY_H_ +

1 0

Patch set updated for coreboot: 33b60dd SB700 southbridge: AMD SB700/SP5100 southbridge CIMX code
by Kerry Sheh 31 Jan '12

31 Jan '12

Kerry Sheh (shekairui(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/560 -gerrit commit 33b60ddb3d34150cd8d5a962758b02dcfd0e2127 Author: Kerry Sheh <shekairui(a)gmail.com> Date: Wed Feb 1 13:55:13 2012 +0800 SB700 southbridge: AMD SB700/SP5100 southbridge CIMX code Support AMD SB700 and SP5100 chipsets. Change-Id: I0955abf7f48a79483f624b46a61b22711315f888 Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> --- src/vendorcode/amd/cimx/Makefile.inc | 1 + src/vendorcode/amd/cimx/sb700/ACPILIB.c | 120 ++++ src/vendorcode/amd/cimx/sb700/ACPILIB.h | 61 ++ src/vendorcode/amd/cimx/sb700/AMDLIB.c | 434 ++++++++++++ src/vendorcode/amd/cimx/sb700/AMDSBLIB.c | 276 ++++++++ src/vendorcode/amd/cimx/sb700/AZALIA.c | 304 ++++++++ src/vendorcode/amd/cimx/sb700/DEBUG.c | 169 +++++ src/vendorcode/amd/cimx/sb700/DISPATCHER.c | 208 ++++++ src/vendorcode/amd/cimx/sb700/EC.c | 132 ++++ src/vendorcode/amd/cimx/sb700/FLASH.c | 58 ++ src/vendorcode/amd/cimx/sb700/LEGACY.c | 38 + src/vendorcode/amd/cimx/sb700/Makefile.inc | 77 ++ src/vendorcode/amd/cimx/sb700/OEM.h | 87 +++ src/vendorcode/amd/cimx/sb700/SATA.c | 453 ++++++++++++ src/vendorcode/amd/cimx/sb700/SB700.h | 1028 ++++++++++++++++++++++++++++ src/vendorcode/amd/cimx/sb700/SBCMN.c | 572 ++++++++++++++++ src/vendorcode/amd/cimx/sb700/SBCMNLIB.c | 108 +++ src/vendorcode/amd/cimx/sb700/SBCMNLIB.h | 89 +++ src/vendorcode/amd/cimx/sb700/SBDEF.h | 166 +++++ src/vendorcode/amd/cimx/sb700/SBMAIN.c | 289 ++++++++ src/vendorcode/amd/cimx/sb700/SBPOR.c | 441 ++++++++++++ src/vendorcode/amd/cimx/sb700/SBTYPE.h | 249 +++++++ src/vendorcode/amd/cimx/sb700/SMM.c | 91 +++ src/vendorcode/amd/cimx/sb700/USB.c | 187 +++++ src/vendorcode/amd/cimx/sb700/sbAMDLIB.h | 196 ++++++ 25 files changed, 5834 insertions(+), 0 deletions(-) diff --git a/src/vendorcode/amd/cimx/Makefile.inc b/src/vendorcode/amd/cimx/Makefile.inc index 3622312..7051ea2 100644 --- a/src/vendorcode/amd/cimx/Makefile.inc +++ b/src/vendorcode/amd/cimx/Makefile.inc @@ -1,3 +1,4 @@ +subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += sb700 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += sb800 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += sb900 subdirs-$(CONFIG_NORTHBRIDGE_AMD_CIMX_RD890) += rd890 diff --git a/src/vendorcode/amd/cimx/sb700/ACPILIB.c b/src/vendorcode/amd/cimx/sb700/ACPILIB.c new file mode 100644 index 0000000..807b166 --- /dev/null +++ b/src/vendorcode/amd/cimx/sb700/ACPILIB.c @@ -0,0 +1,120 @@ +/***************************************************************************** + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + ***************************************************************************/ + + +#include "Platform.h" + +/*++ + +Routine Description: + + Locate ACPI table + +Arguments: + + Signature - table signature + +Returns: + + pointer to ACPI table + +--*/ +void* ACPI_LocateTable( + UINT32 Signature +) +{ + UINT32 i; + UINT32* RsdPtr = (UINT32*)0xe0000; + UINT32* Rsdt = NULL; + DESCRIPTION_HEADER* CurrentTable; + do{ +// if (*RsdPtr == ' DSR' && *(RsdPtr+1) == ' RTP'){ + if ((*RsdPtr == Int32FromChar ('R', 'S', 'D', ' ')) && (*(RsdPtr+1) == Int32FromChar ('R', 'T', 'P', ' '))){ + Rsdt = (UINT32*)((RSDP*)RsdPtr)->RsdtAddress; + break; + } + RsdPtr+=4; + }while (RsdPtr <= (UINT32*)0xffff0); + if(Rsdt != NULL && ACPI_GetTableChecksum(Rsdt)==0){ + for (i = 0;i < (((DESCRIPTION_HEADER*)Rsdt)->Length - sizeof(DESCRIPTION_HEADER))/4;i++){ + CurrentTable = (DESCRIPTION_HEADER*)*(UINT32*)((UINT8*)Rsdt + sizeof(DESCRIPTION_HEADER) + i*4); + if (CurrentTable->Signature == Signature) return CurrentTable; + } + } + return NULL; +} + +/*++ + +Routine Description: + + Update table checksum + +Arguments: + + TablePtr - table pointer + +Returns: + + none + +--*/ +void ACPI_SetTableChecksum( + void* TablePtr +) +{ + UINT8 Checksum = 0; + ((DESCRIPTION_HEADER*)TablePtr)->Checksum = 0; + Checksum = ACPI_GetTableChecksum(TablePtr); + ((DESCRIPTION_HEADER*)TablePtr)->Checksum = 0x100 - Checksum; +} + +/*++ + +Routine Description: + + Get table checksum + +Arguments: + + TablePtr - table pointer + +Returns: + + none + +--*/ +UINT8 ACPI_GetTableChecksum( + void* TablePtr +) +{ + return GetByteSum(TablePtr,((DESCRIPTION_HEADER*)TablePtr)->Length); +} + diff --git a/src/vendorcode/amd/cimx/sb700/ACPILIB.h b/src/vendorcode/amd/cimx/sb700/ACPILIB.h new file mode 100644 index 0000000..5f2734f --- /dev/null +++ b/src/vendorcode/amd/cimx/sb700/ACPILIB.h @@ -0,0 +1,61 @@ +/*;******************************************************************************** +; +; Copyright (C) 2012 Advanced Micro Devices, Inc. +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; * Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; * Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution. +; * Neither the name of Advanced Micro Devices, Inc. nor the names of +; its contributors may be used to endorse or promote products derived +; from this software without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;*********************************************************************************/ + +#ifndef _AMD_ACPILIB_H_ +#define _AMD_ACPILIB_H_ + +typedef struct _RSDP{ + UINT64 Signature; + UINT8 Checksum; + UINT8 OEMID[6]; + UINT8 Revision; + UINT32 RsdtAddress; + UINT32 Length; + UINT64 XsdtAddress; + UINT8 ExtendedChecksum; + UINT8 Reserved[3]; +}RSDP; + +typedef struct _DESCRIPTION_HEADER{ + UINT32 Signature; + UINT32 Length; + UINT8 Revision; + UINT8 Checksum; + UINT8 OEMID[6]; + UINT8 OEMTableID[8]; + UINT32 OEMRevision; + UINT32 CreatorID; + UINT32 CreatorRevision; +}DESCRIPTION_HEADER; + +void* ACPI_LocateTable(UINT32 Signature); +void ACPI_SetTableChecksum(void* TablePtr); +UINT8 ACPI_GetTableChecksum(void* TablePtr); + +#endif //ifndef _AMD_ACPILIB_H_ diff --git a/src/vendorcode/amd/cimx/sb700/AMDLIB.c b/src/vendorcode/amd/cimx/sb700/AMDLIB.c new file mode 100644 index 0000000..b233259 --- /dev/null +++ b/src/vendorcode/amd/cimx/sb700/AMDLIB.c @@ -0,0 +1,434 @@ +/***************************************************************************** + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + ***************************************************************************/ + + + +#include "Platform.h" + +VOID +ReadIO ( + IN UINT16 Address, + IN UINT8 OpFlag, + IN VOID* Value + ) +{ + OpFlag = OpFlag & 0x7f; + switch ( OpFlag ) { + case AccWidthUint8: + *(UINT8*)Value = ReadIo8 (Address); + break; + case AccWidthUint16: + *(UINT16*)Value = ReadIo16 (Address); + break; + case AccWidthUint32: + *(UINT32*)Value = ReadIo32 (Address); + break; + default: + break; + } +} + +VOID +WriteIO ( + IN UINT16 Address, + IN UINT8 OpFlag, + IN VOID* Value + ) +{ + OpFlag = OpFlag & 0x7f; + switch ( OpFlag ) { + case AccWidthUint8: + WriteIo8 (Address, *(UINT8*)Value); + break; + case AccWidthUint16: + WriteIo16 (Address, *(UINT16*)Value); + break; + case AccWidthUint32: + WriteIo32 (Address, *(UINT32*)Value); + break; + default: + break; + } +} + +VOID +RWIO ( + IN UINT16 Address, + IN UINT8 OpFlag, + IN UINT32 Mask, + IN UINT32 Data + ) +{ + UINT32 Result; + ReadIO (Address, OpFlag, &Result); + Result = (Result & Mask) | Data; + WriteIO (Address, OpFlag, &Result); +} + + +VOID +ReadPCI ( + IN UINT32 Address, + IN UINT8 OpFlag, + IN VOID* Value + ) +{ + OpFlag = OpFlag & 0x7f; + + if ( (UINT16)Address < 0xff ) { + //Normal Config Access + UINT32 AddrCf8; + AddrCf8 = (1 << 31) + ((Address >> 8) & 0x0FFFF00) + (Address & 0xFC); + WriteIO (0xCf8, AccWidthUint32, &AddrCf8); + ReadIO ((UINT16) (0xCfC + (Address & 0x3)), OpFlag, Value); + } +} + +VOID +WritePCI ( + IN UINT32 Address, + IN UINT8 OpFlag, + IN VOID* Value + ) +{ + OpFlag = OpFlag & 0x7f; + if ( (UINT16)Address < 0xff ) { + //Normal Config Access + UINT32 AddrCf8; + AddrCf8 = (1 << 31) + ((Address >> 8)&0x0FFFF00) + (Address & 0xFC); + WriteIO (0xCf8, AccWidthUint32, &AddrCf8); + WriteIO ((UINT16) (0xCfC + (Address & 0x3)), OpFlag, Value); + } +} + +VOID +RWPCI ( + IN UINT32 Address, + IN UINT8 OpFlag, + IN UINT32 Mask, + IN UINT32 Data + ) +{ + UINT32 Result; + Result = 0; + OpFlag = OpFlag & 0x7f; + ReadPCI (Address, OpFlag, &Result); + Result = (Result & Mask) | Data; + WritePCI (Address, OpFlag, &Result); +} + +void +ReadIndexPCI32 ( +UINT32 PciAddress, +UINT32 IndexAddress, +void* Value +) +{ + WritePCI(PciAddress,AccWidthUint32,&IndexAddress); + ReadPCI(PciAddress+4,AccWidthUint32,Value); +} + +void +WriteIndexPCI32 ( +UINT32 PciAddress, +UINT32 IndexAddress, +UINT8 OpFlag, +void* Value +) +{ + + WritePCI(PciAddress,AccWidthUint32 | (OpFlag & 0x80),&IndexAddress); + WritePCI(PciAddress+4,AccWidthUint32 | (OpFlag & 0x80) ,Value); +} + +void +RWIndexPCI32 ( +UINT32 PciAddress, +UINT32 IndexAddress, +UINT8 OpFlag, +UINT32 Mask, +UINT32 Data +) +{ + UINT32 Result; + ReadIndexPCI32(PciAddress,IndexAddress,&Result); + Result = (Result & Mask)| Data; + WriteIndexPCI32(PciAddress,IndexAddress,(OpFlag & 0x80),&Result); + +} + +void +ReadMEM ( +UINT32 Address, +UINT8 OpFlag, +void* Value +) +{ + OpFlag = OpFlag & 0x7f; + switch (OpFlag){ + case AccWidthUint8 : *((UINT8*)Value)=*((UINT8*)Address);break; + case AccWidthUint16: *((UINT16*)Value)=*((UINT16*)Address);break; + case AccWidthUint32: *((UINT32*)Value)=*((UINT32*)Address);break; + } +} + +void +WriteMEM ( +UINT32 Address, +UINT8 OpFlag, +void* Value +) +{ + OpFlag = OpFlag & 0x7f; + switch (OpFlag){ + case AccWidthUint8 : *((UINT8*)Address)=*((UINT8*)Value);break; + case AccWidthUint16: *((UINT16*)Address)=*((UINT16*)Value);break; + case AccWidthUint32: *((UINT32*)Address)=*((UINT32*)Value);break; + } +} + +void +RWMEM ( +UINT32 Address, +UINT8 OpFlag, +UINT32 Mask, +UINT32 Data +) +{ + UINT32 Result; + ReadMEM(Address,OpFlag,&Result); + Result = (Result & Mask)| Data; + WriteMEM(Address,OpFlag,&Result); +} + + +void +RWMSR( +UINT32 Address, +UINT64 Mask, +UINT64 Value +) +{ + MsrWrite(Address,(MsrRead(Address)& Mask)|Value); +} + +UINT32 +IsFamily10() +{ + CPUID_DATA Cpuid; + CpuidRead(0x1,(CPUID_DATA *)&Cpuid); + + return Cpuid.REG_EAX & 0xff00000; +} + + +UINT8 GetNumberOfCpuCores(void) +{ + UINT8 Result=1; + Result=ReadNumberOfCpuCores(); + return Result; +} + + +void +Stall( +UINT32 uSec +) +{ + UINT16 timerAddr; + UINT32 startTime, elapsedTime; + ReadPMIO(SB_PMIO_REG24, AccWidthUint16, &timerAddr); + + if (timerAddr ==0){ + uSec = uSec/2; + while (uSec!=0){ + ReadIO(0x80,AccWidthUint8,(UINT8 *)(&startTime)); + uSec--; + } + } + else{ + ReadIO(timerAddr, AccWidthUint32,&startTime); + while (1){ + ReadIO(timerAddr, AccWidthUint32,&elapsedTime); + if (elapsedTime < startTime) + elapsedTime = elapsedTime+0xFFFFFFFF-startTime; + else + elapsedTime = elapsedTime-startTime; + if ((elapsedTime*28/100)>uSec) + break; + } + } +} + + +void +Reset( +) +{ + RWIO(0xcf9,AccWidthUint8,0x0,0x06); +} + + +CIM_STATUS +RWSMBUSBlock( +UINT8 Controller, +UINT8 Address, +UINT8 Offset, +UINT8 BufferSize, +UINT8* BufferPrt +) +{ + UINT16 SmbusPort; + UINT8 i; + UINT8 Status; + ReadPCI(PCI_ADDRESS(0,0x14,0,Controller?0x58:0x10),AccWidthUint16,&SmbusPort); + SmbusPort &= 0xfffe; + RWIO(SmbusPort + 0,AccWidthUint8,0x0,0xff); + RWIO(SmbusPort + 4,AccWidthUint8,0x0,Address); + RWIO(SmbusPort + 3,AccWidthUint8,0x0,Offset); + RWIO(SmbusPort + 2,AccWidthUint8,0x0,0x14); + RWIO(SmbusPort + 5,AccWidthUint8,0x0,BufferSize); + if(!(Address & 0x1)){ + for (i = 0 ;i < BufferSize;i++){ + WriteIO(SmbusPort + 7,AccWidthUint8,&BufferPrt[i]); + } + } + RWIO(SmbusPort + 2,AccWidthUint8,0x0,0x54); + do{ + ReadIO(SmbusPort + 0,AccWidthUint8,&Status); + if (Status & 0x1C) return CIM_ERROR; + if (Status & 0x02) break; + }while(!(Status & 0x1)); + + do{ + ReadIO(SmbusPort + 0,AccWidthUint8,&Status); + }while(Status & 0x1); + + if(Address & 0x1){ + for (i = 0 ;i < BufferSize;i++){ + ReadIO(SmbusPort + 7,AccWidthUint8,&BufferPrt[i]); + } + } + return CIM_SUCCESS; +} + + + +void outPort80(UINT32 pcode) +{ + WriteIO(0x80, AccWidthUint8, &pcode); + return; +} + + +UINT8 +GetByteSum( + void* pData, + UINT32 Length +) +{ + UINT32 i; + UINT8 Checksum = 0; + for (i = 0;i < Length;i++){ + Checksum += *((UINT8*)pData+i); + } + return Checksum; +} + + +UINT32 +readAlink( + UINT32 Index +){ + UINT32 Data; + WriteIO(ALINK_ACCESS_INDEX, AccWidthUint32, &Index); + ReadIO(ALINK_ACCESS_DATA, AccWidthUint32, &Data); + //Clear Index + Index=0; + WriteIO(ALINK_ACCESS_INDEX, AccWidthUint32, &Index); + return Data; +} + + +void +writeAlink( + UINT32 Index, + UINT32 Data +){ + WriteIO(ALINK_ACCESS_INDEX, AccWidthUint32, &Index); + WriteIO(ALINK_ACCESS_DATA, AccWidthUint32, &Data); + //Clear Index + Index=0; + WriteIO(ALINK_ACCESS_INDEX, AccWidthUint32, &Index); + +} + + +/** + * + * IsServer - Determine if southbridge type is SP5100 (server) or SB7x0 (non-server) + * + * A SP5100 is determined when both following two items are true: + * 1) Revision >= A14; + * 2) A server north bridge chipset is detected; + * + * A list of server north bridge chipset: + * + * Family DeviceID + * ---------------------- + * SR5690 0x5A10 + * SR5670 0x5A12 + * SR5650 0x5A13 + * + */ +UINT8 +IsServer (void){ + UINT16 DevID; + + if (getRevisionID () < SB700_A14) { + return 0; + } + ReadPCI ((NB_BDF << 16) + 2, AccWidthUint16, &DevID); + return ((DevID == 0x5a10) || (DevID == 0x5a12) || (DevID == 0x5a13))? 1: 0; +} + +/** + * + * IsLS2Mode - Determine if LS2 mode is enabled or not in northbridge. + * + */ +UINT8 +IsLs2Mode (void) +{ + UINT32 HT3LinkTraining0; + + ReadPCI ((NB_BDF << 16) + 0xAC, AccWidthUint32, &HT3LinkTraining0); + return ( HT3LinkTraining0 & 0x100 )? 1: 0; +} diff --git a/src/vendorcode/amd/cimx/sb700/AMDSBLIB.c b/src/vendorcode/amd/cimx/sb700/AMDSBLIB.c new file mode 100644 index 0000000..bf4f06a --- /dev/null +++ b/src/vendorcode/amd/cimx/sb700/AMDSBLIB.c @@ -0,0 +1,276 @@ +/***************************************************************************** + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + ***************************************************************************/ + + +#include "Platform.h" + + +void +ReadPMIO ( +UINT8 Address, +UINT8 OpFlag, +void* Value +) +{ + UINT8 i; + + OpFlag = OpFlag & 0x7f; + if (OpFlag == 0x02) OpFlag = 0x03; + for (i=0;i<=OpFlag;i++){ + WriteIO(0xCD6, AccWidthUint8, &Address); // SB_IOMAP_REGCD6 + Address++; + ReadIO(0xCD7, AccWidthUint8, (UINT8 *)Value+i); // SB_IOMAP_REGCD7 + } +} + + +void +WritePMIO ( +UINT8 Address, +UINT8 OpFlag, +void* Value +) +{ + UINT8 i; + + OpFlag = OpFlag & 0x7f; + if (OpFlag == 0x02) OpFlag = 0x03; + for (i=0;i<=OpFlag;i++){ + WriteIO(0xCD6, AccWidthUint8, &Address); // SB_IOMAP_REGCD6 + Address++; + WriteIO(0xCD7, AccWidthUint8, (UINT8 *)Value+i); // SB_IOMAP_REGCD7 + } +} + + +void +RWPMIO ( +UINT8 Address, +UINT8 OpFlag, +UINT32 AndMask, +UINT32 OrMask +) +{ + UINT32 Result; + + OpFlag = OpFlag & 0x7f; + ReadPMIO(Address,OpFlag,&Result); + Result = (Result & AndMask)| OrMask; + WritePMIO(Address,OpFlag,&Result); +} + + +void +ReadPMIO2 ( +UINT8 Address, +UINT8 OpFlag, +void* Value +) +{ + UINT8 i; + + OpFlag = OpFlag & 0x7f; + if (OpFlag == 0x02) OpFlag = 0x03; + for (i=0;i<=OpFlag;i++){ + WriteIO(0xCD0, AccWidthUint8, &Address); // SB_IOMAP_REGCD0 + Address++; + ReadIO(0xCD1, AccWidthUint8, (UINT8 *)Value+i); // SB_IOMAP_REGCD1 + } +} + + +void +WritePMIO2 ( +UINT8 Address, +UINT8 OpFlag, +void* Value +) +{ + UINT8 i; + + OpFlag = OpFlag & 0x7f; + if (OpFlag == 0x02) OpFlag = 0x03; + for (i=0;i<=OpFlag;i++){ + WriteIO(0xCD0, AccWidthUint8, &Address); // SB_IOMAP_REGCD0 + Address++; + WriteIO(0xCD1, AccWidthUint8, (UINT8 *)Value+i); // SB_IOMAP_REGCD1 + } +} + + +void +RWPMIO2 ( +UINT8 Address, +UINT8 OpFlag, +UINT32 AndMask, +UINT32 OrMask +) +{ + UINT32 Result; + + OpFlag = OpFlag & 0x7f; + ReadPMIO2(Address,OpFlag,&Result); + Result = (Result & AndMask)| OrMask; + WritePMIO2(Address,OpFlag,&Result); +} + + +void +EnterEcConfig() +{ + UINT16 dwEcIndexPort; + + ReadPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4, AccWidthUint16 | S3_SAVE, &dwEcIndexPort); + dwEcIndexPort &= ~(UINT16)(BIT0); + RWIO(dwEcIndexPort, AccWidthUint8, 0x00, 0x5A); +} + +void +ExitEcConfig() +{ + UINT16 dwEcIndexPort; + + ReadPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4, AccWidthUint16 | S3_SAVE, &dwEcIndexPort); + dwEcIndexPort &= ~(UINT16)(BIT0); + RWIO(dwEcIndexPort, AccWidthUint8, 0x00, 0xA5); +} + + +void +ReadEC8 ( +UINT8 Address, +UINT8* Value +) +{ + UINT16 dwEcIndexPort; + + ReadPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4, AccWidthUint16 | S3_SAVE, &dwEcIndexPort); + dwEcIndexPort &= ~(UINT16)(BIT0); + WriteIO(dwEcIndexPort, AccWidthUint8, &Address); // SB_IOMAP_REGCD6 + ReadIO(dwEcIndexPort+1, AccWidthUint8, Value); // SB_IOMAP_REGCD7 +} + + +void +WriteEC8 ( +UINT8 Address, +UINT8* Value +) +{ + UINT16 dwEcIndexPort; + + ReadPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4, AccWidthUint16 | S3_SAVE, &dwEcIndexPort); + dwEcIndexPort &= ~(UINT16)(BIT0); + WriteIO(dwEcIndexPort, AccWidthUint8, &Address); // SB_IOMAP_REGCD6 + WriteIO(dwEcIndexPort+1, AccWidthUint8, Value); // SB_IOMAP_REGCD7 +} + + +void +RWEC8 ( +UINT8 Address, +UINT8 AndMask, +UINT8 OrMask +) +{ + UINT8 Result; + ReadEC8(Address,&Result); + Result = (Result & AndMask)| OrMask; + WriteEC8(Address, &Result); +} + + +void +programPciByteTable ( +REG8MASK* pPciByteTable, +UINT16 dwTableSize +) +{ + UINT8 i, dbBusNo, dbDevFnNo; + UINT32 ddBDFR; + + dbBusNo = pPciByteTable->bRegIndex; + dbDevFnNo = pPciByteTable->bANDMask; + pPciByteTable++; + for (i = 1; i < dwTableSize; i++){ + if ( (pPciByteTable->bRegIndex==0xFF) && (pPciByteTable->bANDMask==0xFF) && (pPciByteTable->bORMask==0xFF) ){ + pPciByteTable++; + dbBusNo = pPciByteTable->bRegIndex; + dbDevFnNo = pPciByteTable->bANDMask; + } + else{ + ddBDFR = (dbBusNo << 24) + (dbDevFnNo << 16) + (pPciByteTable->bRegIndex) ; + TRACE((DMSG_SB_TRACE, "PFA=%X AND=%X, OR=%X\n", ddBDFR, pPciByteTable->bANDMask, pPciByteTable->bORMask)); + RWPCI(ddBDFR, AccWidthUint8 | S3_SAVE, pPciByteTable->bANDMask, pPciByteTable->bORMask); + pPciByteTable++; + } + } +} + + +void +programPmioByteTable ( +REG8MASK* pPmioByteTable, +UINT16 dwTableSize +) +{ + UINT8 i; + for (i = 0; i < dwTableSize; i++){ + TRACE((DMSG_SB_TRACE, "PMIO Reg = %X AndMask = %X OrMask = %X\n",pPmioByteTable->bRegIndex,pPmioByteTable->bANDMask, pPmioByteTable->bORMask)); + RWPMIO(pPmioByteTable->bRegIndex, AccWidthUint8 , pPmioByteTable->bANDMask, pPmioByteTable->bORMask); + pPmioByteTable++; + } +} + + +UINT8 +getClockMode ( +void +) +{ + UINT8 dbTemp=0; + + RWPMIO(SB_PMIO_REGB2, AccWidthUint8, 0xFF, BIT7); + ReadPMIO(SB_PMIO_REGB0, AccWidthUint8, &dbTemp); + return(dbTemp&BIT4); +} + + +UINT16 +readStrapStatus ( +void +) +{ + UINT16 dwTemp=0; + + RWPMIO(SB_PMIO_REGB2, AccWidthUint8, 0xFF, BIT7); + ReadPMIO(SB_PMIO_REGB0, AccWidthUint16, &dwTemp); + return(dwTemp); +} diff --git a/src/vendorcode/amd/cimx/sb700/AZALIA.c b/src/vendorcode/amd/cimx/sb700/AZALIA.c new file mode 100644 index 0000000..cc72858 --- /dev/null +++ b/src/vendorcode/amd/cimx/sb700/AZALIA.c @@ -0,0 +1,304 @@ +/***************************************************************************** + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + ***************************************************************************/ + + + +#include "Platform.h" + +void configureAzaliaPinCmd (AMDSBCFG* pConfig, UINT32 ddBAR0, UINT8 dbChannelNum); +void configureAzaliaSetConfigD4Dword(CODECENTRY* tempAzaliaCodecEntryPtr, UINT32 ddChannelNum, UINT32 ddBAR0); + +//Pin Config for ALC880, ALC882 and ALC883: +CODECENTRY AzaliaCodecAlc882Table[] = { + {0x14, 0x01014010}, + {0x15, 0x01011012}, + {0x16, 0x01016011}, + {0x17, 0x01012014}, + {0x18, 0x01A19030}, + {0x19, 0x411111F0}, + {0x1a, 0x01813080}, + {0x1b, 0x411111F0}, + {0x1C, 0x411111F0}, + {0x1d, 0x411111F0}, + {0x1e, 0x01441150}, + {0x1f, 0x01C46160}, + {0xff, 0xffffffff} +}; + + +//Pin Config for ALC262 +CODECENTRY AzaliaCodecAlc262Table[] = { + {0x14, 0x01014010}, + {0x15, 0x411111F0}, + {0x16, 0x411111F0}, +// {0x17, 0x01012014}, + {0x18, 0x01A19830}, + {0x19, 0x02A19C40}, + {0x1a, 0x01813031}, + {0x1b, 0x02014C20}, + {0x1c, 0x411111F0}, + {0x1d, 0x411111F0}, + {0x1e, 0x0144111E}, + {0x1f, 0x01C46150}, + {0xff, 0xffffffff} +}; + +//Pin Config for ALC0861: +CODECENTRY AzaliaCodecAlc861Table[] = { + {0x01, 0x8086C601}, + {0x0B, 0x01014110}, + {0x0C, 0x01813140}, + {0x0D, 0x01A19941}, + {0x0E, 0x411111F0}, + {0x0F, 0x02214420}, + {0x10, 0x02A1994E}, + {0x11, 0x99330142}, + {0x12, 0x01451130}, + {0x1F, 0x411111F0}, + {0x20, 0x411111F0}, + {0x23, 0x411111F0}, + {0xff, 0xffffffff} +}; + +//Pin Config for ADI1984: +CODECENTRY AzaliaCodecAd1984Table[] = { + {0x11, 0x0221401F}, + {0x12, 0x90170110}, + {0x13, 0x511301F0}, + {0x14, 0x02A15020}, + {0x15, 0x50A301F0}, + {0x16, 0x593301F0}, + {0x17, 0x55A601F0}, + {0x18, 0x55A601F0}, + {0x1A, 0x91F311F0}, + {0x1B, 0x014511A0}, + {0x1C, 0x599301F0}, + {0xff, 0xffffffff} +}; + + +CODECENTRY FrontPanelAzaliaCodecTableList[] = { + {0x19, 0x02A19040}, + {0x1b, 0x02214020}, + {0xff, 0xffffffff} +}; + + +CODECTBLLIST azaliaCodecTableList[] = { + {0x010ec0880, &AzaliaCodecAlc882Table[0]}, + {0x010ec0882, &AzaliaCodecAlc882Table[0]}, + {0x010ec0883, &AzaliaCodecAlc882Table[0]}, + {0x010ec0885, &AzaliaCodecAlc882Table[0]}, + {0x010ec0262, &AzaliaCodecAlc262Table[0]}, + {0x010ec0861, &AzaliaCodecAlc861Table[0]}, + {0x011d41984, &AzaliaCodecAd1984Table[0]}, + {(UINT32)0x0FFFFFFFF, (CODECENTRY*)0xFFFFFFFF} +}; + + +/*------------------------------------------------------------------------------- +; Procedure: azaliaInitAfterPciEnum +; +; Description: This routine detects Azalia and, if present, initializes Azalia +; This routine is called from atiSbAfterPciInit +; +; +; Exit: None +; +; Modified: None +; +;----------------------------------------------------------------------------- +*/ +void azaliaInitAfterPciEnum (AMDSBCFG* pConfig){ + UINT8 i, dbEnableAzalia=0, dbPinRouting, dbChannelNum=0, dbTempVariable = 0; + UINT16 dwTempVariable = 0; + UINT32 ddBAR0, ddTempVariable = 0; + + if (pConfig->AzaliaController == 1) return; + + if (pConfig->AzaliaController != 1){ + RWPCI((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG04, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT1, BIT1); + ReadPCI((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG10, AccWidthUint32, &ddBAR0); + + if (ddBAR0 != 0){ //Keep the flag as disabled if BAR is 0 or all "F"s. + if (ddBAR0 != 0xFFFFFFFF){ + ddBAR0 &= ~(0x03FFF); + dbEnableAzalia = 1; + TRACE((DMSG_SB_TRACE, "CIMxSB - Enabling Azalia controller (BAR setup is ok) \n")); + } + } + } + + if (dbEnableAzalia){ //if Azalia is enabled + //Get SDIN Configuration + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGF8, AccWidthUint32 | S3_SAVE, 0, ddTempVariable); + ddTempVariable |= (pConfig->AzaliaSdin3 << 6); + ddTempVariable |= (pConfig->AzaliaSdin2 << 4); + ddTempVariable |= (pConfig->AzaliaSdin1 << 2); + ddTempVariable |= pConfig->AzaliaSdin0; + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGFC, AccWidthUint8 | S3_SAVE, 0, (ddTempVariable & 0xFF)); + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG60+3, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT2+BIT1+BIT0), 0); + + i=11; + do{ + ReadMEM( ddBAR0+SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable); + dbTempVariable |= BIT0; + WriteMEM(ddBAR0+SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable); + Stall(1000); + ReadMEM(ddBAR0+SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable); + i--; + } while ( (!(dbTempVariable & BIT0)) && (i > 0) ); + + if (i==0){ + TRACE((DMSG_SB_TRACE, "CIMxSB - Problem in resetting Azalia controller\n")); + return; + } + + Stall(1000); + ReadMEM( ddBAR0+SB_AZ_BAR_REG0E, AccWidthUint16, &dwTempVariable); + if (dwTempVariable & 0x0F){ + TRACE((DMSG_SB_TRACE, "CIMxSB - Atleast One Azalia CODEC found \n")); + //atleast one azalia codec found + ReadPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGFC, AccWidthUint8, &dbPinRouting); + do{ + if ( ( !(dbPinRouting & BIT0) ) && (dbPinRouting & BIT1) ) + configureAzaliaPinCmd(pConfig, ddBAR0, dbChannelNum); + dbPinRouting >>= 2; + dbChannelNum++; + } while (dbChannelNum != 4); + } + else{ + TRACE((DMSG_SB_TRACE, "CIMxSB - Azalia CODEC NOT found \n")); + //No Azalia codec found + if (pConfig->AzaliaController != 2) + dbEnableAzalia = 0; //set flag to disable Azalia + } + } + + if (dbEnableAzalia){ + //redo clear reset + do{ + dwTempVariable = 0; + WriteMEM( ddBAR0+SB_AZ_BAR_REG0C, AccWidthUint16 | S3_SAVE, &dwTempVariable); + ReadMEM(ddBAR0+SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable); + dbTempVariable &= ~(UINT8)(BIT0); + WriteMEM(ddBAR0+SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable); + ReadMEM(ddBAR0+SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable); + } while (dbTempVariable & BIT0); + + if (pConfig->AzaliaSnoop == 1) + RWPCI((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG42, AccWidthUint8 | S3_SAVE, 0xFF, BIT1+BIT0); + } + else{ + //disable Azalia controller + RWPCI((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG04, AccWidthUint16 | S3_SAVE, 0, 0); + RWPMIO(SB_PMIO_REG59, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT3, 0); + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGFC, AccWidthUint8 | S3_SAVE, 0, 0x55); + } +} + + +void configureAzaliaPinCmd (AMDSBCFG* pConfig, UINT32 ddBAR0, UINT8 dbChannelNum){ + UINT32 ddTempVariable, ddChannelNum; + CODECTBLLIST* ptempAzaliaOemCodecTablePtr; + CODECENTRY* tempAzaliaCodecEntryPtr; + + if ((pConfig->AzaliaPinCfg) != 1) + return; + + ddChannelNum = dbChannelNum << 28; + ddTempVariable = 0xF0000; + ddTempVariable |= ddChannelNum; + WriteMEM(ddBAR0 + SB_AZ_BAR_REG60, AccWidthUint32 | S3_SAVE, &ddTempVariable); + Stall(60); + ReadMEM(ddBAR0 + SB_AZ_BAR_REG64, AccWidthUint32 | S3_SAVE, &ddTempVariable); + + if ( ((pConfig->pAzaliaOemCodecTablePtr) == NULL) || ((pConfig->pAzaliaOemCodecTablePtr) == ((CODECTBLLIST*) 0xFFFFFFFF)) ) + ptempAzaliaOemCodecTablePtr = (CODECTBLLIST*) FIXUP_PTR(&azaliaCodecTableList[0]); + else + ptempAzaliaOemCodecTablePtr = (CODECTBLLIST*) pConfig->pAzaliaOemCodecTablePtr; + + TRACE((DMSG_SB_TRACE, "CIMxSB - Azalia CODEC table pointer is %x \n", (UINT32)ptempAzaliaOemCodecTablePtr)); + + while ( ptempAzaliaOemCodecTablePtr->CodecID != 0xFFFFFFFF){ + if ( ptempAzaliaOemCodecTablePtr->CodecID == ddTempVariable) + break; + else + ++ptempAzaliaOemCodecTablePtr; + } + + if ( ptempAzaliaOemCodecTablePtr->CodecID != 0xFFFFFFFF){ + TRACE((DMSG_SB_TRACE, "CIMxSB - Matching CODEC ID found \n")); + tempAzaliaCodecEntryPtr = (CODECENTRY*) ptempAzaliaOemCodecTablePtr->CodecTablePtr; + TRACE((DMSG_SB_TRACE, "CIMxSB - Matching Azalia CODEC table pointer is %x \n", (UINT32)tempAzaliaCodecEntryPtr)); + + if ( ((pConfig->pAzaliaOemCodecTablePtr) == NULL) || ((pConfig->pAzaliaOemCodecTablePtr) == ((CODECTBLLIST*) 0xFFFFFFFF)) ) + tempAzaliaCodecEntryPtr = (CODECENTRY*) FIXUP_PTR(tempAzaliaCodecEntryPtr); + + configureAzaliaSetConfigD4Dword(tempAzaliaCodecEntryPtr, ddChannelNum, ddBAR0); + if (pConfig->AzaliaFrontPanel != 1){ + if ( (pConfig->AzaliaFrontPanel == 2) || (pConfig->FrontPanelDetected == 1) ){ + if ( ((pConfig->pAzaliaOemFpCodecTableptr) == NULL) || ((pConfig->pAzaliaOemFpCodecTableptr) == 0xFFFFFFFF)) + tempAzaliaCodecEntryPtr = (CODECENTRY*) FIXUP_PTR(&FrontPanelAzaliaCodecTableList[0]); + else + tempAzaliaCodecEntryPtr = (CODECENTRY*) pConfig->pAzaliaOemFpCodecTableptr; + configureAzaliaSetConfigD4Dword(tempAzaliaCodecEntryPtr, ddChannelNum, ddBAR0); + } + } + } +} + + +void configureAzaliaSetConfigD4Dword(CODECENTRY* tempAzaliaCodecEntryPtr, UINT32 ddChannelNum, UINT32 ddBAR0){ + UINT8 dbtemp1,dbtemp2, i; + UINT32 ddtemp=0,ddtemp2=0; + + while ((tempAzaliaCodecEntryPtr->Nid) != 0xFF){ + dbtemp1=0x20; + if ((tempAzaliaCodecEntryPtr->Nid) == 0x1) + dbtemp1=0x24; + ddtemp = tempAzaliaCodecEntryPtr->Nid; + ddtemp &= 0xff; + ddtemp <<= 20; + ddtemp |= ddChannelNum; + ddtemp |= (0x700 << 8); + for(i=4; i>0; i--){ + do{ + ReadMEM(ddBAR0 + SB_AZ_BAR_REG68, AccWidthUint32, &ddtemp2); + } while (ddtemp2 & BIT0); + dbtemp2 = ( (tempAzaliaCodecEntryPtr->Byte40) >> ((4-i) * 8 ) ) & 0xff; + ddtemp = (ddtemp & 0xFFFF0000)+ ((dbtemp1 - i) << 8) + dbtemp2; + WriteMEM(ddBAR0 + SB_AZ_BAR_REG60, AccWidthUint32 | S3_SAVE, &ddtemp); + Stall(60); + } + ++tempAzaliaCodecEntryPtr; + } +} + diff --git a/src/vendorcode/amd/cimx/sb700/DEBUG.c b/src/vendorcode/amd/cimx/sb700/DEBUG.c new file mode 100644 index 0000000..f40682e --- /dev/null +++ b/src/vendorcode/amd/cimx/sb700/DEBUG.c @@ -0,0 +1,169 @@ +/***************************************************************************** + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + ***************************************************************************/ + + +#include "Platform.h" + +#define COM_BASE_ADDRESS 0x3f8 +#define DIVISOR 115200 +#define LF 0x0a +#define CR 0x0d + + +#ifdef CIM_DEBUG + #ifndef CIM_DEBUG_LEVEL + #define CIM_DEBUG_LEVEL 0xf +#endif + +void +TraceCode( UINT32 Level, UINT32 Code){ + + if (!(Level & CIM_DEBUG_LEVEL)){ + return; + } +#if CIM_DEBUG & 1 + if (Code != 0xFF){ + WriteIO(0x80,AccWidthUint8,&Code); + } +#endif + +} + + +void +TraceDebug( UINT32 Level, CHAR8 *Format, ...){ + CHAR8 temp[16]; + va_list ArgList; + + if (!(Level & CIM_DEBUG_LEVEL)){ + return; + } + +#if CIM_DEBUG & 2 + ArgList = va_start(ArgList,Format); + Format= (CHAR8*) FIXUP_PTR(Format); + while (1){ + if (*Format == 0) break; + if (*Format == '%'){ + int Radix = 0; + if(*(Format+1)=='s'||*(Format+1)=='S'){ + SendStringPort((CHAR8*) FIXUP_PTR(va_arg(ArgList,CHAR8*))); + Format+=2; + continue; + } + + if(*(Format+1)=='d'||*(Format+1)=='D'){ + Radix = 10; + } + if(*(Format+1)=='x'||*(Format+1)=='X'){ + Radix = 16; + } + if (Radix){ + ItoA(va_arg(ArgList,int),Radix,temp); + SendStringPort(temp); + Format+=2; + continue; + } + } + SendBytePort(*Format); + if(*(Format)==0x0a) SendBytePort(0x0d); + Format++; + } + va_end(ArgList); +#endif +} + + +void +ItoA( UINT32 Value, int Radix, char* pstr) +{ + char* tsptr = pstr; + char* rsptr = pstr; + char ch1,ch2; + unsigned int Reminder; +//Create String + do{ + Reminder = Value%Radix; + Value = Value/Radix; + if (Reminder<0xa) *tsptr=Reminder+'0'; + else *tsptr=Reminder-0xa+'a'; + tsptr++; + } while(Value); +//Reverse String + *tsptr = 0; + tsptr--; + while(tsptr>rsptr){ + ch1 = *tsptr; + ch2 = *rsptr; + *rsptr = ch1; + *tsptr = ch2; + tsptr--; + rsptr++; + } +} + +void +InitSerialOut(){ + UINT8 Data; + UINT16 Divisor; + Data = 0x87; + WriteIO(COM_BASE_ADDRESS + 0x3,AccWidthUint8, &Data); + Divisor = 115200 / DIVISOR; + Data = Divisor & 0xFF; + WriteIO(COM_BASE_ADDRESS + 0x00,AccWidthUint8, &Data); + Data = Divisor >> 8; + WriteIO(COM_BASE_ADDRESS + 0x01,AccWidthUint8, &Data); + Data = 0x07; + WriteIO(COM_BASE_ADDRESS + 0x3,AccWidthUint8, &Data); +} + + +void +SendStringPort(char* pstr){ + + while (*pstr!=0){ + SendBytePort(*pstr); + pstr++; + } +} + +void +SendBytePort(UINT8 Data) +{ + int Count = 80; + UINT8 Status; + do { + ReadIO((COM_BASE_ADDRESS + 0x05),AccWidthUint8, &Status); + if(Status == 0xff) break; + // Loop port is ready + } while ( (Status & 0x20) == 0 && (--Count) != 0); + WriteIO(COM_BASE_ADDRESS + 0x00,AccWidthUint8, &Data); +} +#endif diff --git a/src/vendorcode/amd/cimx/sb700/DISPATCHER.c b/src/vendorcode/amd/cimx/sb700/DISPATCHER.c new file mode 100644 index 0000000..ae5f9b8 --- /dev/null +++ b/src/vendorcode/amd/cimx/sb700/DISPATCHER.c @@ -0,0 +1,208 @@ +/***************************************************************************** + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + ***************************************************************************/ + + +#include "Platform.h" + +void DispatcherEntry(void *pConfig){ + +#ifdef B1_IMAGE + void *pB2ImagePtr = NULL; + CIM_IMAGE_ENTRY pB2ImageEntry; +#endif + +//#if CIM_DEBUG +// InitSerialOut(); +//#endif + + TRACE((DMSG_SB_TRACE, "CIM - SB700 Entry\n")); + +#ifdef B1_IMAGE + if ((UINT32)(((STDCFG*)pConfig)->pB2ImageBase) != 0xffffffff){ + if (((STDCFG*)pConfig)->pB2ImageBase) + pB2ImagePtr = CheckImage('007S',(void*)((STDCFG*)pConfig)->pB2ImageBase); + if (pB2ImagePtr == NULL) + pB2ImagePtr = LocateImage('007S'); + if (pB2ImagePtr!=NULL){ + TRACE((DMSG_SB_TRACE, "CIM - SB700 Redirect to B2 Image\n")); + ((STDCFG*)pConfig)->pImageBase = (UINT32)pB2ImagePtr; + pB2ImageEntry = (CIM_IMAGE_ENTRY)(*((UINT32*)pB2ImagePtr+1) + (UINT32)pB2ImagePtr); + (*pB2ImageEntry)(pConfig); + return; + } + } +#endif + saveConfigPointer(pConfig); + + if (((STDCFG*)pConfig)->Func == SB_POWERON_INIT) + sbPowerOnInit((AMDSBCFG*)pConfig); + +#ifndef B1_IMAGE + if (((STDCFG*)pConfig)->Func == SB_BEFORE_PCI_INIT) + sbBeforePciInit((AMDSBCFG*)pConfig); + if (((STDCFG*)pConfig)->Func == SB_AFTER_PCI_INIT) + sbAfterPciInit((AMDSBCFG*)pConfig); + if (((STDCFG*)pConfig)->Func == SB_LATE_POST_INIT) + sbLatePost((AMDSBCFG*)pConfig); + if (((STDCFG*)pConfig)->Func == SB_BEFORE_PCI_RESTORE_INIT) + sbBeforePciRestoreInit((AMDSBCFG*)pConfig); + if (((STDCFG*)pConfig)->Func == SB_AFTER_PCI_RESTORE_INIT) + sbAfterPciRestoreInit((AMDSBCFG*)pConfig); + if (((STDCFG*)pConfig)->Func == SB_SMM_SERVICE) + { + // sbSmmService((AMDSBCFG*)pConfig); + } + if (((STDCFG*)pConfig)->Func == SB_SMM_ACPION) + sbSmmAcpiOn((AMDSBCFG*)pConfig); +#endif + TRACE((DMSG_SB_TRACE, "CIMx - SB Exit\n")); +} + + +void* LocateImage(UINT32 Signature){ + void *Result; + UINT8 *ImagePtr = (UINT8*)(0xffffffff - (IMAGE_ALIGN-1)); + while ((UINT32)ImagePtr>=(0xfffffff - (NUM_IMAGE_LOCATION*IMAGE_ALIGN -1))){ + Result = CheckImage(Signature,(void*)ImagePtr); + if (Result != NULL) + return Result; + ImagePtr -= IMAGE_ALIGN; + } + return NULL; +} + + +void* CheckImage(UINT32 Signature, void* ImagePtr){ + UINT8 *TempImagePtr; + UINT8 Sum = 0; + UINT32 i; +// if ((*((UINT32*)ImagePtr) == 'ITA$' && ((CIMFILEHEADER*)ImagePtr)->ModuleLogo == Signature)){ + if ((*((UINT32*)ImagePtr) == Int32FromChar ('$', 'A', 'T', 'I')) && (((CIMFILEHEADER*)ImagePtr)->ModuleLogo == Signature)){ + //GetImage Image size + TempImagePtr = (UINT8*)ImagePtr; + for (i=0;i<(((CIMFILEHEADER*)ImagePtr)->ImageSize);i++){ + Sum += *TempImagePtr; + TempImagePtr++; + } + if (Sum == 0) + return ImagePtr; + } + return NULL; +} + + +UINT32 GetPciebase(){ + AMDSBCFG* Result; + Result = getConfigPointer(); + return Result->StdHeader.pPcieBase; +} + + +void saveConfigPointer(AMDSBCFG* pConfig){ + UINT8 dbReg, i; + UINT32 ddValue; + + ddValue = ((UINT32) pConfig); + dbReg = SB_ECMOS_REG08; + + for (i=0; i<=3; i++){ + WriteIO(SB_IOMAP_REG72, AccWidthUint8, &dbReg); + WriteIO(SB_IOMAP_REG73, AccWidthUint8, (UINT8 *)&ddValue); + ddValue >>= 8; + dbReg++; + } +} + + +AMDSBCFG* getConfigPointer(){ + UINT8 dbReg, dbValue, i; + UINT32 ddValue=0; + + dbReg = SB_ECMOS_REG08; + for (i=0; i<=3; i++){ + WriteIO(SB_IOMAP_REG72, AccWidthUint8, &dbReg); + ReadIO(SB_IOMAP_REG73, AccWidthUint8, &dbValue); + ddValue |= (dbValue<<(i*8)); + dbReg++; + } + return( (AMDSBCFG*) ddValue); +} + +/** + * AmdSbDispatcher - Dispatch Southbridge function + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +AGESA_STATUS +AmdSbDispatcher ( + IN VOID *pConfig + ) +{ + AGESA_STATUS Status = AGESA_SUCCESS; + + saveConfigPointer (pConfig); + + if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_POWERON_INIT ) { + sbPowerOnInit ((AMDSBCFG*) pConfig); + } + + if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_BEFORE_PCI_INIT ) { + sbBeforePciInit ((AMDSBCFG*)pConfig); + } + + if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_AFTER_PCI_INIT ) { + sbAfterPciInit ((AMDSBCFG*)pConfig); + } + + if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_LATE_POST_INIT ) { + sbLatePost ((AMDSBCFG*)pConfig); + } + + if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_BEFORE_PCI_RESTORE_INIT ) { + sbBeforePciRestoreInit ((AMDSBCFG*)pConfig); + } + + if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_AFTER_PCI_RESTORE_INIT ) { + sbAfterPciRestoreInit ((AMDSBCFG*)pConfig); + } + + if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_SMM_SERVICE ) { + sbSmmService ((AMDSBCFG*)pConfig); + } + + if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_SMM_ACPION ) { + sbSmmAcpiOn ((AMDSBCFG*)pConfig); + } + + return Status; +} diff --git a/src/vendorcode/amd/cimx/sb700/EC.c b/src/vendorcode/amd/cimx/sb700/EC.c new file mode 100644 index 0000000..3ad15e1 --- /dev/null +++ b/src/vendorcode/amd/cimx/sb700/EC.c @@ -0,0 +1,132 @@ +/***************************************************************************** + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + ***************************************************************************/ + + +#include "Platform.h" + +#ifndef NO_EC_SUPPORT + +REG8MASK sb710PorInitPciTable[] = { + // SMBUS Device(Bus 0, Dev 20, Func 0) + {0x00, SMBUS_BUS_DEV_FUN, 0}, + {SB_SMBUS_REG43, ~(UINT8)BIT3, 0x00}, //Make some hidden registers of smbus visible. + {SB_SMBUS_REG38, (UINT8)~(BIT7+BIT5+BIT4+BIT3+BIT2+BIT1), 0x0D}, + {SB_SMBUS_REG38+1, ~(UINT8)(BIT2+BIT1), BIT3 }, + {SB_SMBUS_REGE1, 0xFF, BIT1}, + {SB_SMBUS_REG43, 0xFF, BIT3}, //Make some hidden registers of smbus invisible. + {0xFF, 0xFF, 0xFF}, + + // LPC Device(Bus 0, Dev 20, Func 3) + {0x00, LPC_BUS_DEV_FUN, 0}, + {SB_LPC_REGB8+3, ~(UINT8)(BIT1), BIT7+BIT2}, + {0xFF, 0xFF, 0xFF}, +}; + +REG8MASK sb710PorPmioInitTbl[]={ + // index andmask ormask + {SB_PMIO_REGD7, 0xFF, BIT5}, + {SB_PMIO_REGBB, 0xFF, BIT5}, +}; + + +void ecPowerOnInit(BUILDPARAM *pBuildOptPtr, AMDSBCFG* pConfig){ + UINT8 dbVar0, i=0; + + if (!(isEcPresent())) + return; //return if EC is not enabled + + for(i=0;i<0xFF;i++){ + ReadPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG40, AccWidthUint8 | S3_SAVE, &dbVar0); + if ( dbVar0 & BIT7 ) break; //break if EC is ready + Stall(500); //wait for EC to become ready + } + + if (getRevisionID() >= SB700_A14){ + programPciByteTable( (REG8MASK*)FIXUP_PTR(&sb710PorInitPciTable[0]), sizeof(sb710PorInitPciTable)/sizeof(REG8MASK) ); + programPmioByteTable( (REG8MASK *)FIXUP_PTR(&sb710PorPmioInitTbl[0]), (sizeof(sb710PorPmioInitTbl)/sizeof(REG8MASK)) ); + } + + RWPCI(((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGBA), AccWidthUint8 | S3_SAVE, 0xFF, BIT2); //Enable SPI Prefetch in EC + + //Enable config mode + EnterEcConfig(); + + //Do settings for mailbox - logical device 0x09 + RWEC8(0x07, 0x00, 0x09); //switch to device 9 (Mailbox) + RWEC8(0x60, 0x00, (pBuildOptPtr->EcLdn9MailBoxAddr >> 8)); //set MSB of Mailbox port + RWEC8(0x61, 0x00, (pBuildOptPtr->EcLdn9MailBoxAddr & 0xFF)); //set LSB of Mailbox port + RWEC8(0x30, 0x00, 0x01); //;Enable Mailbox Registers Interface, bit0=1 + + if (pBuildOptPtr->EcKbd == CIMX_OPTION_ENABLED){ + RWPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG60+3), AccWidthUint8 | S3_SAVE, 0xFF, BIT7+BIT3); + //Enable KBRST#, IRQ1 & IRQ12, GateA20 Function signal from IMC + RWPMIO(SB_PMIO_REGBB, AccWidthUint8, 0xFF, BIT3+BIT2+BIT1+BIT0); + //Disable LPC Decoding of port 60/64 + RWPCI(((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG47), AccWidthUint8 | S3_SAVE, ~(UINT32)BIT5, 0); + //Enable logical device 0x07 (Keyboard controller) + RWEC8(0x07, 0x00, 0x07); + RWEC8(0x30, 0x00, 0x01); + } + + if (pBuildOptPtr->EcChannel0 == CIMX_OPTION_ENABLED){ + //Logical device 0x08 + RWEC8(0x07, 0x00, 0x08); + RWEC8(0x60, 0x00, 0x00); + RWEC8(0x61, 0x00, 0x62); + RWEC8(0x30, 0x00, 0x01); //;Enable Device 8 + } + //Logical device 0x05 + RWEC8(0x07, 0x00, 0x05); //Select logical device 05, IR controller + RWEC8(0x60, 0x00, pBuildOptPtr->EcLdn5MailBoxAddr >> 8); + RWEC8(0x61, 0x00, (pBuildOptPtr->EcLdn5MailBoxAddr & 0xFF)); + RWEC8(0x70, 0xF0, (pBuildOptPtr->EcLdn5Irq)); //Set IRQ to 05h + RWEC8(0x30, 0x00, 0x01); //Enable logical device 5, IR controller + + RWPMIO(SB_PMIO_REGBB, AccWidthUint8, 0xFF, BIT4); //Enable EC(IMC) to generate SMI to BIOS + ExitEcConfig(); +} + + +void ecInitBeforePciEnum(AMDSBCFG* pConfig){ + if (!(isEcPresent())) + return; //return if EC is not enabled +} + + +void ecInitLatePost(AMDSBCFG* pConfig){ + if (!(isEcPresent()) ) + return; //return if EC is not enabled + //Enable config mode + EnterEcConfig(); //Enable config mode + //for future use + ExitEcConfig(); +} + +#endif diff --git a/src/vendorcode/amd/cimx/sb700/FLASH.c b/src/vendorcode/amd/cimx/sb700/FLASH.c new file mode 100644 index 0000000..0d84245 --- /dev/null +++ b/src/vendorcode/amd/cimx/sb700/FLASH.c @@ -0,0 +1,58 @@ +/***************************************************************************** + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + ***************************************************************************/ + + +#include "Platform.h" + +void fcInitBeforePciEnum(AMDSBCFG* pConfig){ + + TRACE((DMSG_SB_TRACE, "Entering PreInit Flash \n")); + RWPMIO(SB_PMIO_REGB2, AccWidthUint8, ~(UINT32)BIT1, 00); + + //Enable IDE and disable flash + //Enable IDE and disable flash + RWPMIO(SB_PMIO_REG59, AccWidthUint8, ~(UINT32)(BIT1+BIT0), 0); + RWPMIO(SB_PMIO_REGB2, AccWidthUint8, ~(UINT32)(BIT3), BIT0); //Configure GPIO3 as IDE_RST# and release RST + if (pConfig->IdeController){ + //Disabling IDE controller + RWPCI((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG04, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT2+BIT1+BIT0), 0); + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGAE, AccWidthUint8 | S3_SAVE, 0xFF, BIT3); + } + else{ + //Enable IDE controller + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGAE, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT3), 0); + } + + //RPR 8.2 Enable IDE Data bus DD7 Pull down Resistor if IDE is enabled and FC is disabled + RWPMIO2(SB_PMIO2_REGE5, AccWidthUint8, 0xFF, BIT2); + //Slowdown the clock to FC if FC is not enabled, this is a power savings feature + RWPMIO(SB_PMIO_REGB2, AccWidthUint8, ~(UINT32)(BIT4), BIT4); + RWPMIO(SB_PMIO_REGBC, AccWidthUint8, 0xC0, 0); +} diff --git a/src/vendorcode/amd/cimx/sb700/LEGACY.c b/src/vendorcode/amd/cimx/sb700/LEGACY.c new file mode 100644 index 0000000..c904d59 --- /dev/null +++ b/src/vendorcode/amd/cimx/sb700/LEGACY.c @@ -0,0 +1,38 @@ +/***************************************************************************** + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + ***************************************************************************/ + + +#include "Platform.h" + +UINT32 GetFixUp(){ + STDCFG* Result; + Result = (STDCFG*) getConfigPointer(); + return Result->pImageBase; +} diff --git a/src/vendorcode/amd/cimx/sb700/Makefile.inc b/src/vendorcode/amd/cimx/sb700/Makefile.inc new file mode 100644 index 0000000..8954133 --- /dev/null +++ b/src/vendorcode/amd/cimx/sb700/Makefile.inc @@ -0,0 +1,77 @@ +#***************************************************************************** +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# * Neither the name of Advanced Micro Devices, Inc. nor the names of +# its contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +#***************************************************************************** + +# CIMX Root directory +CIMX_ROOT = $(src)/vendorcode/amd/cimx + +SB_CIMX_INC = -I$(src)/mainboard/$(MAINBOARDDIR) +SB_CIMX_INC += -I$(src)/southbridge/amd/cimx/sb700 +SB_CIMX_INC += -I$(CIMX_ROOT)/sb700 + +romstage-y += ACPILIB.c +romstage-y += AMDLIB.c +romstage-y += AMDSBLIB.c +romstage-y += AZALIA.c +romstage-y += DEBUG.c +romstage-y += DISPATCHER.c +romstage-y += EC.c +romstage-y += FLASH.c +romstage-y += SATA.c +romstage-y += SBCMN.c +romstage-y += SBCMNLIB.c +romstage-y += SBMAIN.c +romstage-y += SBPOR.c +romstage-y += SMM.c +romstage-y += USB.c + +ramstage-y += ACPILIB.c +ramstage-y += AMDLIB.c +ramstage-y += AMDSBLIB.c +ramstage-y += AZALIA.c +ramstage-y += DEBUG.c +ramstage-y += DISPATCHER.c +ramstage-y += EC.c +ramstage-y += FLASH.c +ramstage-y += SATA.c +ramstage-y += SBCMN.c +ramstage-y += SBCMNLIB.c +ramstage-y += SBMAIN.c +ramstage-y += SBPOR.c +ramstage-y += SMM.c +ramstage-y += USB.c +ramstage-y += LEGACY.c + +SB_CIMX_CFLAGS = +export CIMX_ROOT +export SB_CIMX_INC +export SB_CIMX_CFLAGS +CC := $(CC) $(SB_CIMX_CFLAGS) $(SB_CIMX_INC) + +####################################################################### + diff --git a/src/vendorcode/amd/cimx/sb700/OEM.h b/src/vendorcode/amd/cimx/sb700/OEM.h new file mode 100644 index 0000000..74604c0 --- /dev/null +++ b/src/vendorcode/amd/cimx/sb700/OEM.h @@ -0,0 +1,87 @@ +/*;******************************************************************************** +; +; Copyright (C) 2012 Advanced Micro Devices, Inc. +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; * Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; * Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution. +; * Neither the name of Advanced Micro Devices, Inc. nor the names of +; its contributors may be used to endorse or promote products derived +; from this software without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;*********************************************************************************/ +#ifndef _AMD_SB_CIMx_OEM_H_ +#define _AMD_SB_CIMx_OEM_H_ + +#define BIOS_SIZE 0x04 //04 - 1MB +#define LEGACY_FREE 0x00 + +/** + * PCIEX_BASE_ADDRESS - Define PCIE base address + * + * @param[Option] MOVE_PCIEBAR_TO_F0000000 Set PCIe base address to 0xF7000000 + */ +#ifdef MOVE_PCIEBAR_TO_F0000000 + #define PCIEX_BASE_ADDRESS 0xF7000000 +#else + #define PCIEX_BASE_ADDRESS 0xE0000000 +#endif + + +#define SMBUS0_BASE_ADDRESS 0xB00 +#define SMBUS1_BASE_ADDRESS 0xB20 +#define SIO_PME_BASE_ADDRESS 0xE00 +#define SPI_BASE_ADDRESS 0xFEC10000 + +#define WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0 // Watchdog Timer Base Address +#define HPET_BASE_ADDRESS 0xFED00000 // HPET Base address + +#define PM1_EVT_BLK_ADDRESS 0x800 // AcpiPm1EvtBlkAddr; +#define PM1_CNT_BLK_ADDRESS 0x804 // AcpiPm1CntBlkAddr; +#define PM1_TMR_BLK_ADDRESS 0x808 // AcpiPmTmrBlkAddr; +#define CPU_CNT_BLK_ADDRESS 0x810 // CpuControlBlkAddr; +#define GPE0_BLK_ADDRESS 0x820 // AcpiGpe0BlkAddr; +#define SMI_CMD_PORT 0xB0 // SmiCmdPortAddr; +#define ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 // AcpiPmaCntBlkAddr; + +#define EC_LDN5_MAILBOX_ADDRESS 0x550 +#define EC_LDN5_IRQ 0x05 +#define EC_LDN9_MAILBOX_ADDRESS 0x3E + +#define SATA_IDE_MODE_SSID 0x43901002 +#define SATA_RAID_MODE_SSID 0x43921002 +#define SATA_RAID5_MODE_SSID 0x43931002 +#define SATA_AHCI_SSID 0x43911002 +#define OHCI0_SSID 0x43971002 +#define OHCI1_SSID 0x43981002 +#define EHCI0_SSID 0x43961002 +#define OHCI2_SSID 0x43971002 +#define OHCI3_SSID 0x43981002 +#define EHCI1_SSID 0x43961002 +#define OHCI4_SSID 0x43991002 + +#define SMBUS_SSID 0x43851002 +#define IDE_SSID 0x439C1002 +#define AZALIA_SSID 0x43831002 +#define LPC_SSID 0x439D1002 +#define P2P_SSID 0x43841002 + +#define RESERVED_VALUE 0x00 + +#endif //ifndef _AMD_SB_CIMx_OEM_H_ diff --git a/src/vendorcode/amd/cimx/sb700/SATA.c b/src/vendorcode/amd/cimx/sb700/SATA.c new file mode 100644 index 0000000..09d4923 --- /dev/null +++ b/src/vendorcode/amd/cimx/sb700/SATA.c @@ -0,0 +1,453 @@ +/***************************************************************************** + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + ***************************************************************************/ + + +#include "Platform.h" + +//Table for class code of SATA Controller in different modes +UINT32 sataIfCodeTable[] = { + 0x01018f00, //sata class ID of IDE + 0x01040000, //sata class ID of RAID + 0x01060100, //sata class ID of AHCI + 0x01018a00, //sata class ID of Legacy IDE + 0x01018f00, //sata class ID of IDE to AHCI mode + 0x01060100, //sata class ID of AMD-AHCI mode + 0x01018f00 //sata class ID of IDE to AMD-AHCI mode +}; + +//Table for device id of SATA Controller in different modes +UINT16 sataDeviceIDTable[] = { + 0x4390, //sata device ID of IDE + 0x4392, //sata device ID of RAID + 0x4391, //sata class ID of AHCI + 0x4390, //sata device ID of Legacy IDE + 0x4390, //sata device ID of IDE->AHCI mode + 0x4394, //sata device ID for AMD-AHCI mode + 0x4390 //sata device ID of IDE->AMDAHCI mode +}; + + +void sataInitBeforePciEnum(AMDSBCFG* pConfig){ + UINT32 ddValue, *tempptr; + UINT16 *pDeviceIdptr, dwDeviceId; + UINT8 dbValue, dbOrMask, dbAndMask; + + + dbAndMask=0; + dbOrMask=0; + // Enable/Disable Combined mode & do primary/secondary selections, enable/disable + if (pConfig->SataIdeCombinedMode == CIMX_OPTION_DISABLED) dbAndMask= BIT3; //Clear BIT3 + if (pConfig->SataIdeCombMdPriSecOpt == 1) dbOrMask = BIT4; //Set BIT4 + if (pConfig->SataSmbus == 0) dbOrMask = BIT1; + + RWPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGAD), AccWidthUint8 | S3_SAVE, ~(dbAndMask), dbOrMask); + + if (pConfig->SataController == 0){ + // SATA Controller Disabled & set Power Saving mode to disabled + RWPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGAD), AccWidthUint8 | S3_SAVE, ~(UINT32)BIT0, BIT1); + return; + } + + restrictSataCapabilities(pConfig); + + // Get the appropriate class code from the table and write it to PCI register 08h-0Bh + // Set the appropriate SATA class based on the input parameters + dbValue=pConfig->SataClass; + tempptr= (UINT32 *) FIXUP_PTR (&sataIfCodeTable[0]); + ddValue=tempptr[dbValue]; + + // BIT0: Enable write access to PCI header (reg 08h-0Bh) by setting SATA PCI register 40h, bit 0 + // BIT4:disable fast boot + RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, 0xff, BIT4+BIT0); + + // Write the class code to SATA PCI register 08h-0Bh + RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG08), AccWidthUint32 | S3_SAVE, 0, ddValue); + + if (pConfig->SataClass == LEGACY_IDE_MODE) //SATA = Legacy IDE + //Set PATA controller to native mode + RWPCI(((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG09), AccWidthUint8 | S3_SAVE, 0x00, 0x08F); + + //Change the appropriate device id + if (pConfig->SataClass == AMD_AHCI_MODE) { + RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 3), AccWidthUint8 | S3_SAVE, 0xff, BIT0); + } + pDeviceIdptr= (UINT16 *) FIXUP_PTR (&sataDeviceIDTable[0]); + + ReadPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG02), AccWidthUint16 | S3_SAVE, &dwDeviceId); + if ( !((dwDeviceId==SB750_SATA_DEFAULT_DEVICE_ID) && (pConfig->SataClass == RAID_MODE)) ){ + //if not (SB750 & RAID mode), then program the device id + dwDeviceId=pDeviceIdptr[dbValue]; + RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG02), AccWidthUint16 | S3_SAVE, 0, dwDeviceId); + } + + if (pConfig->AcpiS1Supported) + RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG34), AccWidthUint8 | S3_SAVE, 00, 0x70);//Disable SATA PM & MSI capability + else + RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG60+1), AccWidthUint8 | S3_SAVE, 00, 0x70);//Disable SATA MSI capability + + if (getRevisionID() >= SB700_A13){ + //Enable test/enhancement mode for A13 + RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40+3), AccWidthUint8 | S3_SAVE, ~(UINT32)BIT5, 00); + RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG48), AccWidthUint32 | S3_SAVE, ~(UINT32)(BIT24+BIT21), 0xBF80); + } + + if (getRevisionID() >= SB700_A14){ + //Fix for TT SB01352 - LED Stays On When ODD Attached To Slave Port In IDE Mode + RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG48), AccWidthUint8 | S3_SAVE, 0xFF, BIT6); + } + + // Disable write access to PCI header + RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, ~(UINT32)BIT0, 0); + + // RPR 6.5 SATA PHY Programming Sequence + RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG86, AccWidthUint16 | S3_SAVE, 0x00, 0x2C00); + RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG88, AccWidthUint32 | S3_SAVE, 0x00, 0x01B48016); + RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG8C, AccWidthUint32 | S3_SAVE, 0x00, 0x01B48016); + RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG90, AccWidthUint32 | S3_SAVE, 0x00, 0x01B48016); + RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG94, AccWidthUint32 | S3_SAVE, 0x00, 0x01B48016); + RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG98, AccWidthUint32 | S3_SAVE, 0x00, 0x01B48016); + RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG9C, AccWidthUint32 | S3_SAVE, 0x00, 0x01B48016); + RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REGA0, AccWidthUint32 | S3_SAVE, 0x00, 0xA07AA07A); + RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REGA4, AccWidthUint32 | S3_SAVE, 0x00, 0xA07AA07A); + RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REGA8, AccWidthUint32 | S3_SAVE, 0x00, 0xA07AA07A); + + CallBackToOEM(SATA_PHY_PROGRAMMING, NULL, pConfig); +} + +void sataInitAfterPciEnum(AMDSBCFG* pConfig){ + UINT32 ddAndMask=0, ddOrMask=0, ddBar5=0; + UINT8 dbVar, dbPortNum; + + if (pConfig->SataController == 0) return; //return if SATA controller is disabled. + + //Enable write access to pci header, pm capabilities + RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, 0xFF, BIT0); + + //Disable AHCI enhancement function (RPR 7.2) + RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 2), AccWidthUint8 | S3_SAVE, 0xFF, BIT7); + + restrictSataCapabilities(pConfig); + + ReadPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG24), AccWidthUint32, &ddBar5); + + if ( (ddBar5 == 0) || (ddBar5 == -1) ) { + //assign temporary BAR5 + if ( (pConfig->TempMMIO == 0) || (pConfig->TempMMIO == -1)) + ddBar5 = 0xFEC01000; + else + ddBar5=pConfig->TempMMIO; + + WritePCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG24), AccWidthUint32, &ddBar5); + } + + ReadPCI( ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, &dbVar); + RWPCI( ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8,0xFF, 0x03); //memory and io access enable + + ddBar5 &= 0xFFFFFC00; //Clear Bits 9:0 + if (!pConfig->SataPortMultCap) + ddAndMask |= BIT12; + if (!pConfig->SataAggrLinkPmCap) + ddAndMask |= BIT11; + if (pConfig->SataSscPscCap) + ddOrMask |= BIT1; + + RWMEM((ddBar5 + SB_SATA_BAR5_REGFC),AccWidthUint32 | S3_SAVE, ~ddAndMask, ddOrMask); + + + //Clear HPCP and ESP by default + RWMEM((ddBar5 + SB_SATA_BAR5_REGF8),AccWidthUint32 | S3_SAVE, 0xFFFC0FC0, 0); + + if (pConfig->SataHpcpButNonESP !=0) { + RWMEM((ddBar5 + SB_SATA_BAR5_REGF8),AccWidthUint32 | S3_SAVE, 0xFFFFFFC0, pConfig->SataHpcpButNonESP); + } + + // SATA ESP port setting + // These config bits are set for SATA driver to identify which ports are external SATA ports and need to + // support hotplug. If a port is set as an external SATA port and need to support hotplug, then driver will + // not enable power management(HIPM & DIPM) for these ports. + if (pConfig->SataEspPort !=0) { + RWMEM((ddBar5 + SB_SATA_BAR5_REGFC),AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, BIT20); + RWMEM((ddBar5 + SB_SATA_BAR5_REGF8),AccWidthUint32 | S3_SAVE, ~(pConfig->SataEspPort), 0); + RWMEM((ddBar5 + SB_SATA_BAR5_REGF8),AccWidthUint32 | S3_SAVE, ~(UINT32)(BIT17+BIT16+BIT15+BIT14+BIT13+BIT12),(pConfig->SataEspPort << 12)); + } + + if ( ((pConfig->SataClass) != NATIVE_IDE_MODE) && ((pConfig->SataClass) != LEGACY_IDE_MODE) ) + RWPCI( ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG50+2), AccWidthUint8, ~(UINT32)(BIT3+BIT2+BIT1), BIT2+BIT1); //set MSI to 8 messages + + if ( ((pConfig->SataClass) != NATIVE_IDE_MODE) && ((pConfig->SataClass) != LEGACY_IDE_MODE) && ((pConfig->SataIdeCombinedMode) == CIMX_OPTION_DISABLED) ){ + RWMEM((ddBar5 + SB_SATA_BAR5_REG00),AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT2+BIT1+BIT0), BIT2+BIT0); + RWMEM((ddBar5 + SB_SATA_BAR5_REG0C),AccWidthUint8 | S3_SAVE, 0xC0, 0x3F); + } + + for (dbPortNum=0;dbPortNum<=5;dbPortNum++){ + if (pConfig->SataPortMode & (1 << dbPortNum)){ + //downgrade to GEN1 + RWMEM(ddBar5+ SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0x0F, 0x10); + RWMEM(ddBar5+ SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0xFF, 0x01); + Stall(1000); + RWMEM(ddBar5+ SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0xFE, 0x00); + } + } + + //If this is not S3 resume and also if SATA set to one of IDE mode, then implement drive detection workaround. + if ( !(pConfig->S3Resume) && ( ((pConfig->SataClass) != AHCI_MODE) && ((pConfig->SataClass) != RAID_MODE) && ((pConfig->SataClass) != AMD_AHCI_MODE) ) ) + sataDriveDetection(pConfig, ddBar5); + + if ( (pConfig->SataPhyWorkaround==1) || ( (pConfig->SataPhyWorkaround==0) && (getRevisionID() < SB700_A13)) ) + sataPhyWorkaround(pConfig, ddBar5); + + // Set the handshake bit for IDE driver to detect the disabled IDE channel correctly. + // Set IDE PCI Config 0x63 [3] if primary channel disabled, [4] if secondary channel disabled. + if (pConfig->SataIdeCombinedMode == CIMX_OPTION_DISABLED) + RWPCI( ((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG63), AccWidthUint8 , 0xF9, (0x02 << (pConfig->SataIdeCombMdPriSecOpt)) ); + + WritePCI( ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, &dbVar); + + //Disable write access to pci header, pm capabilities + RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, ~(UINT32)BIT0, 0); +} + + +void sataDriveDetection(AMDSBCFG* pConfig, UINT32 ddBar5){ + UINT32 ddVar0; + UINT8 dbPortNum, dbVar0; + UINT16 dwIoBase, dwVar0; + + TRACE((DMSG_SB_TRACE, "CIMx - Entering sata drive detection procedure\n\n")); + TRACE((DMSG_SB_TRACE, "SATA BAR5 is %X \n", ddBar5)); + + if ( (pConfig->SataClass == NATIVE_IDE_MODE) || (pConfig->SataClass == LEGACY_IDE_MODE) || (pConfig->SataClass == IDE_TO_AHCI_MODE) || (pConfig->SataClass == IDE_TO_AMD_AHCI_MODE) ){ + for (dbPortNum=0;dbPortNum<4;dbPortNum++){ + ReadMEM(ddBar5+ SB_SATA_BAR5_REG128 + dbPortNum * 0x80, AccWidthUint32, &ddVar0); + if ( ( ddVar0 & 0x0F ) == 0x03){ + if ( dbPortNum & BIT0) + //this port belongs to secondary channel + ReadPCI( ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG18), AccWidthUint16, &dwIoBase); + else + //this port belongs to primary channel + ReadPCI( ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG10), AccWidthUint16, &dwIoBase); + + //if legacy ide mode, then the bar registers don't contain the correct values. So we need to hardcode them + if (pConfig->SataClass == LEGACY_IDE_MODE) + dwIoBase = ( (0x170) | ( (~((dbPortNum & BIT0) << 7)) & 0x80 ) ); + + if ( dbPortNum & BIT1) + //this port is slave + dbVar0=0xB0; + else + //this port is master + dbVar0=0xA0; + dwIoBase &= 0xFFF8; + WriteIO(dwIoBase+6, AccWidthUint8, &dbVar0); + + //Wait in loop for 30s for the drive to become ready + for (dwVar0=0;dwVar0<3000;dwVar0++){ + ReadIO(dwIoBase+7, AccWidthUint8, &dbVar0); + if ( (dbVar0 & 0x88) == 0) + break; + Stall(10000); + } + } //end of if ( ( ddVar0 & 0x0F ) == 0x03) + } //for (dbPortNum=0;dbPortNum<4;dbPortNum++) + } //if ( (pConfig->SataClass == NATIVE_IDE_MODE) || (pConfig->SataClass == LEGACY_IDE_MODE) || (pConfig->SataClass == IDE_TO_AHCI_MODE) || (pConfig->SataClass == IDE_TO_AMD_AHCI_MODE) ) +} + + +//This patch is to workaround the SATA PHY logic hardware issue in the SB700. +//Internally this workaround is called as 7NewA +void sataPhyWorkaround(AMDSBCFG* pConfig, UINT32 ddBar5){ + + UINT8 dbPortNum, dbVar0; + + if (pConfig->Gen1DeviceShutdownDuringPhyWrknd == 0x01){ + for (dbPortNum=0;dbPortNum<=5;dbPortNum++){ + ReadMEM(ddBar5+ SB_SATA_BAR5_REG128 + dbPortNum * 0x80, AccWidthUint8, &dbVar0); + if ( (dbVar0 & 0xF0) == 0x10){ + RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40+2, AccWidthUint8 | S3_SAVE, 0xFF, (01 << dbPortNum)); + } + + } + } + + RWPMIO(SB_PMIO_REGD0, AccWidthUint8, ~(UINT32)(BIT4+BIT3), BIT4+BIT3);//set PMIO_D0[4:3] = 11b // this is to tell SATA PHY to use the internal 100MHz clock + RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG86, AccWidthUint8 | S3_SAVE, 0x00, 0x40);// set SATA PCI_CFG 0x86[7:0] = 0x40 //after the reset is done, perform this to turn on the diff clock path into SATA PHY + Stall(2000);// Wait for 2ms + RWPMIO(SB_PMIO_REGD0, AccWidthUint8, ~(UINT32)(BIT4+BIT3), 00);//13. set PMIO_D0[4:3] = 00b + Stall(20000);// Wait 20ms + forceOOB(ddBar5);// Force OOB + + RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40+2, AccWidthUint8 | S3_SAVE, ~(0x03F), 00); +} + + +void forceOOB(UINT32 ddBar5){ + UINT8 dbPortNum; + for (dbPortNum=0;dbPortNum<=5;dbPortNum++) + RWMEM(ddBar5+ SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0xFF, 0x01); + Stall(2000); + for (dbPortNum=0;dbPortNum<=5;dbPortNum++) + RWMEM(ddBar5+ SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0xFE, 0x00); + Stall(2000);// Wait for 2ms +} + +/*++ + +Routine Description: + + SATA Late Configuration + + if the mode is selected as IDE->AHCI + { 1. Set class ID to AHCI + 2. Enable AHCI interrupt + } + +Arguments: + + pConfig - SBconfiguration + +Returns: + + void + +--*/ +void sataInitLatePost(AMDSBCFG* pConfig){ + UINT32 ddBar5; + UINT8 dbVar; + + //Return immediately is sata controller is not enabled + if (pConfig->SataController == 0) return; + + restrictSataCapabilities(pConfig); + + //Get BAR5 value + ReadPCI( ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG24), AccWidthUint32, &ddBar5); + + //Assign temporary BAR if is not already assigned + if ( (ddBar5 == 0) || (ddBar5 == -1) ){ + //assign temporary BAR5 + if ( (pConfig->TempMMIO == 0) || (pConfig->TempMMIO == -1)) + ddBar5 = 0xFEC01000; + else + ddBar5=pConfig->TempMMIO; + WritePCI( ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG24), AccWidthUint32, &ddBar5); + } + + ReadPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, &dbVar); + //Enable memory and io access + RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, 0xFF, 0x03); + //Enable write access to pci header, pm capabilities + RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, 0xff, BIT0); + + shutdownUnconnectedSataPortClock(pConfig, ddBar5); + + if ( (pConfig->SataClass == IDE_TO_AHCI_MODE) || (pConfig->SataClass == IDE_TO_AMD_AHCI_MODE)){ + //program the AHCI class code + RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG08), AccWidthUint32 | S3_SAVE, 0, 0x01060100); + //Set interrupt enable bit + RWMEM((ddBar5 + 0x04),AccWidthUint8,~(UINT32)0,BIT1); + //program the correct device id for AHCI mode + RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG02), AccWidthUint16 | S3_SAVE, 0, 0x4391); + + if (pConfig->SataClass == IDE_TO_AMD_AHCI_MODE) + //program the correct device id for AMD-AHCI mode + RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 3), AccWidthUint8 | S3_SAVE, 0xFF, BIT0); + } + + //Disable write access to pci header and pm capabilities + RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, ~(UINT32)BIT0, 0); + //Clear error status + RWMEM((ddBar5 + SB_SATA_BAR5_REG130),AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF); + RWMEM((ddBar5 + SB_SATA_BAR5_REG1B0),AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF); + RWMEM((ddBar5 + SB_SATA_BAR5_REG230),AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF); + RWMEM((ddBar5 + SB_SATA_BAR5_REG2B0),AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF); + //Restore memory and io access bits + WritePCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, &dbVar ); +} + + +void shutdownUnconnectedSataPortClock(AMDSBCFG* pConfig, UINT32 ddBar5){ + UINT8 dbPortNum, dbPortSataStatus, NumOfPorts=0; + UINT8 UnusedPortBitMap; + UINT8 SataType; + UINT8 ClockOffEnabled ; + + UnusedPortBitMap = 0; + + // First scan for all unused SATA ports + for (dbPortNum = 5; dbPortNum <= 5; dbPortNum--) { + ReadMEM (ddBar5 + SB_SATA_BAR5_REG128 + (dbPortNum * 0x80), AccWidthUint8, &dbPortSataStatus); + if ((!(dbPortSataStatus & 0x01)) && (!((pConfig->SataEspPort) & (1 << dbPortNum)))) { + UnusedPortBitMap |= (1 << dbPortNum); + } + } + + // Decide if we need to shutdown the clock for all unused ports + SataType = pConfig->SataClass; + ClockOffEnabled = (pConfig->SataClkAutoOff && ((SataType == NATIVE_IDE_MODE) || (SataType == LEGACY_IDE_MODE) || \ + (SataType == IDE_TO_AHCI_MODE) || (SataType == IDE_TO_AMD_AHCI_MODE))) || \ + (pConfig->SataClkAutoOffAhciMode && ((SataType == AHCI_MODE) || (SataType == AMD_AHCI_MODE))); + + if (ClockOffEnabled) { + //Shutdown the clock for the port and do the necessary port reporting changes. + TRACE((DMSG_SB_TRACE, "Shutting down clock for SATA ports %X \n", UnusedPortBitMap)); + RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 2), AccWidthUint8, 0xFF, UnusedPortBitMap); + RWMEM(ddBar5 + SB_SATA_BAR5_REG0C, AccWidthUint8, ~UnusedPortBitMap, 00); + } + + // If all ports are in disabled state, report at least one + ReadMEM (ddBar5 + SB_SATA_BAR5_REG0C, AccWidthUint8, &dbPortSataStatus); + if ( (dbPortSataStatus & 0x3F) == 0) { + dbPortSataStatus = 1; + RWMEM (ddBar5 + SB_SATA_BAR5_REG0C, AccWidthUint8, ~(0x3F), dbPortSataStatus); + } + + // Decide if we need to hide unused ports from being seen by OS (this saves OS startup time) + if (pConfig->SataHideUnusedPort && ClockOffEnabled) { + dbPortSataStatus &= ~UnusedPortBitMap; // Mask off unused ports + for (dbPortNum = 0; dbPortNum <= 6; dbPortNum++) { + if (dbPortSataStatus & (1 << dbPortNum)) + NumOfPorts++; + } + if (NumOfPorts == 0 ) { + NumOfPorts = 0x01; + } + RWMEM (ddBar5 + SB_SATA_BAR5_REG00, AccWidthUint8, 0xE0, NumOfPorts - 1); + } +} + + +void restrictSataCapabilities(AMDSBCFG* pConfig){ + //Restrict capabilities + if ( ((getSbCapability(Sb_Raid0_1_Capability)== 0x02) && (pConfig->SataClass == RAID_MODE)) || \ + ((getSbCapability(Sb_Raid5_Capability)== 0x02) && (pConfig->SataClass == RAID_MODE)) || \ + ((getSbCapability(Sb_Ahci_Capability)== 0x02) && ((pConfig->SataClass == AHCI_MODE) || (pConfig->SataClass == IDE_TO_AHCI_MODE)))){ + pConfig->SataClass = NATIVE_IDE_MODE; + } +} diff --git a/src/vendorcode/amd/cimx/sb700/SB700.h b/src/vendorcode/amd/cimx/sb700/SB700.h new file mode 100644 index 0000000..f9e71e8 --- /dev/null +++ b/src/vendorcode/amd/cimx/sb700/SB700.h @@ -0,0 +1,1028 @@ +/*;******************************************************************************** +; +; Copyright (C) 2012 Advanced Micro Devices, Inc. +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; * Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; * Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution. +; * Neither the name of Advanced Micro Devices, Inc. nor the names of +; its contributors may be used to endorse or promote products derived +; from this software without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;*********************************************************************************/ + +#ifndef _AMD_SB700_H_ +#define _AMD_SB700_H_ + +#pragma pack(push,1) + +#define CIMx_Version 0x0660 +#define RC_Information 0x00 +#define Additional_Changes_Indicator 0x00 + +#define SB_POWERON_INIT 0x001 +#define OUTDEBUG_PORT 0x002 +#define SB_BEFORE_PCI_INIT 0x010 +#define SB_AFTER_PCI_INIT 0x020 +#define SB_LATE_POST_INIT 0x030 +#define SB_BEFORE_PCI_RESTORE_INIT 0x040 +#define SB_AFTER_PCI_RESTORE_INIT 0x050 +#define SB_SMM_SERVICE 0x060 +#define SB_SMM_ACPION 0x061 + +#ifndef OEM_CALLBACK_BASE + #define OEM_CALLBACK_BASE 0x100 +#endif + +//0x00 - 0x0F callback functions are reserved for bootblock +#define SATA_PHY_PROGRAMMING OEM_CALLBACK_BASE + 0x10 +#define PULL_UP_PULL_DOWN_SETTINGS OEM_CALLBACK_BASE + 0x20 + +#define CFG_ADDR_PORT 0xCF8 +#define CFG_DATA_PORT 0xCFC +#define ATI_AZALIA_ExtBlk_Addr 0x0F8 +#define ATI_AZALIA_ExtBlk_DATA 0x0FC + +#define ALINK_ACCESS_INDEX 0x0CD8 +#define ALINK_ACCESS_DATA ALINK_ACCESS_INDEX + 4 + +/*------------------------------------------------------------------ +; I/O Base Address - Should be set by host BIOS +;------------------------------------------------------------------ */ +#define DELAY_PORT 0x0E0 + +/*------------------------------------------------------------------ +; DEBUG_PORT = 8-bit I/O Port Address for POST Code Display +;------------------------------------------------------------------ */ +#define SB7XX_DEVICE_ID 0x4385 + +#define SB700_A11 0x39 +#define SB700_A12 0x3A +#define SB700_A13 0x3B +#define SB700_A14 0x3C +#define SB700_A15 0x3D + +#define SATA_BUS_DEV_FUN ((0x11 << 3) + 0) +#define FC_BUS_DEV_FUN ((0x11 << 3) + 1) +#define USB1_OHCI0_BUS_DEV_FUN ((0x12 << 3) + 0) +#define USB1_OHCI1_BUS_DEV_FUN ((0x12 << 3) + 1) +#define USB2_OHCI0_BUS_DEV_FUN ((0x13 << 3) + 0) +#define USB2_OHCI1_BUS_DEV_FUN ((0x13 << 3) + 1) +#define USB3_OHCI_BUS_DEV_FUN ((0x14 << 3) + 5) +#define USB1_EHCI_BUS_DEV_FUN ((0x12 << 3) + 2) +#define USB2_EHCI_BUS_DEV_FUN ((0x13 << 3) + 2) + +#define SMBUS_BUS_DEV_FUN ((0x14 << 3) + 0) +#define IDE_BUS_DEV_FUN ((0x14 << 3) + 1) +#define AZALIA_BUS_DEV_FUN ((0x14 << 3) + 2) +#define LPC_BUS_DEV_FUN ((0x14 << 3) + 3) +#define SBP2P_BUS_DEV_FUN ((0x14 << 3) + 4) +#define NB_BDF ((0 << 3) + 0) +#define HT_LINK_BUS_DEV_FUN ((0x18 << 3) + 0) +#define DCT1_BUS_DEV_FUN ((0x18 << 3) + 2) +#define DCT2_BUS_DEV_FUN ((0x19 << 3) + 2) +#define DCT3_BUS_DEV_FUN ((0x1A << 3) + 2) +#define DCT4_BUS_DEV_FUN ((0x1B << 3) + 2) + + +//Sata Controller Mode +#define NATIVE_IDE_MODE 0 +#define RAID_MODE 1 +#define AHCI_MODE 2 +#define LEGACY_IDE_MODE 3 +#define IDE_TO_AHCI_MODE 4 +#define AMD_AHCI_MODE 5 +#define IDE_TO_AMD_AHCI_MODE 6 + +//Sata Port Configuration +#define SIX_PORTS 0 +#define FOUR_PORTS 1 + +#define SB750_SATA_DEFAULT_DEVICE_ID 0x4393 + +#define SB_AX_INDXC_REG30 0x30 +#define SB_AX_DATAC_REG34 0x34 +#define SB_AX_INDXP_REG38 0x38 +#define SB_AX_DATAP_REG3C 0x3C + +#define AX_INDXC 0 +#define AX_INDXP 1 +#define AXCFG 2 +#define ABCFG 3 + +#define SB_AB_REG02 0x02 +#define SB_AB_REG04 0x04 +#define SB_AB_REG40 0x40 // +#define SB_AB_REG54 0x54 //;miscCtr54 +#define SB_AB_REG58 0x58 //;RAB Control - RW - 32 bits - [RegAddr:58] +#define SB_AB_REG60 0x60 //;DMA Prefetch Enable Port 0 - RW - 32 bits - [RegAddr:60] +#define SB_AB_REG64 0x64 //;DMA Prefetch Flush Port 0 - RW - 32 bits - [RegAddr:64] +#define SB_AB_REG6C 0x6C //;DMA Prefetch Flush Port 0 - RW - 32 bits - [RegAddr:6C] +#define SB_AB_REG80 0x80 //;DMA Prefetch Control Port 1 - RW - 32 bits - [RegAddr:80] +#define SB_AB_REG88 0x88 //;DMA Prefetch Control Port 2 - RW - 32 bits - [RegAddr:88] +#define SB_AB_REG8C 0x8C //;AB Enhancement - RW - 16 bits - [RegAddr:88] +#define SB_AB_REG90 0x90 //;BIF Control - RW - 32 bits - [RegAddr:90] +#define SB_AB_REG94 0x94 //;MSI Control - RW - 32 bits +#define SB_AB_REG98 0x98 //;BIF Control 1 - RW - 32 bits +#define SB_AB_REG9C 0x9C //; +#define SB_AB_REG10050 BIT16+0x50 +#define SB_AB_REG10054 BIT16+0x54 //;AL_Arb_Ctl, AL_Clk_Ctl +#define SB_AB_REG10060 BIT16+0x60 //;DMA Prefetch Enable Port 0 - RW - 32 bits - [RegAddr:10060] +#define SB_AB_REG10064 BIT16+0x64 //;DMA Prefetch Flush Port 0 - RW - 32 bits - [RegAddr:64] +#define SB_AB_REG10090 BIT16+0x90 //; +#define SB_AB_REG1009C BIT16+0x9C //; + + +#define SB_PMIO_REG00 0x000 // MiscControl +#define SB_PMIO_REG01 0x001 // MiscStatus +#define SB_PMIO_REG02 0x002 // SmiWakeUpEventEnable1 +#define SB_PMIO_REG03 0x003 // SmiWakeUpEventEnable2 +#define SB_PMIO_REG04 0x004 // SmiWakeUpEventEnable3 +#define SB_PMIO_REG05 0x005 // SmiWakeUpEventStatus1 +#define SB_PMIO_REG06 0x006 // SmiWakeUpEventStatus2 +#define SB_PMIO_REG07 0x007 // SmiWakeUpEventStatus3 +#define SB_PMIO_REG08 0x008 // InactiveTmrEventEnable1 +#define SB_PMIO_REG09 0x009 // InactiveTmrEventEnable2 +#define SB_PMIO_REG0A 0x00A // InactiveTmrEventEnable3 +#define SB_PMIO_REG0B 0x00B // PmTmr1InitValue +#define SB_PMIO_REG0C 0x00C // PmTmr1CurValue +#define SB_PMIO_REG0D 0x00D // PwrLedExtEvent +#define SB_PMIO_REG0E 0x00E // AcpiControl +#define SB_PMIO_REG0F 0x00F // AcpiStatus +#define SB_PMIO_REG10 0x010 // AcpiEn +#define SB_PMIO_REG11 0x011 // S1AgpStpEn +#define SB_PMIO_REG12 0x012 // PmTmr2InitValue +#define SB_PMIO_REG13 0x013 // PmTmr2CurValue +#define SB_PMIO_REG14 0x014 // Programlo0RangeLo +#define SB_PMIO_REG15 0x015 // ProgramIo0Rangei +#define SB_PMIO_REG16 0x016 // ProgramIo1RangeLo +#define SB_PMIO_REG17 0x017 // ProgramIo1Rangei +#define SB_PMIO_REG18 0x018 // ProgramIo2RangeLo +#define SB_PMIO_REG19 0x019 // ProgramIo2Rangei +#define SB_PMIO_REG1A 0x01A // ProgramIo3RangeLo +#define SB_PMIO_REG1B 0x01B // ProgramIo3Rangei +#define SB_PMIO_REG1C 0x01C // ProgramIoEnable +#define SB_PMIO_REG1D 0x01D // IOMonitorStatus +#define SB_PMIO_REG1E 0x01E // InactiveTmrEventEnable4 +#define SB_PMIO_REG20 0x020 // AcpiPm1EvtBlkLo +#define SB_PMIO_REG21 0x021 // AcpiPm1EvtBlki +#define SB_PMIO_REG22 0x022 // AcpiPm1CntBlkLo +#define SB_PMIO_REG23 0x023 // AcpiPm1CntBlki +#define SB_PMIO_REG24 0x024 // AcpiPmTmrBlkLo +#define SB_PMIO_REG25 0x025 // AcpiPmTmrBlki +#define SB_PMIO_REG26 0x026 // CpuControlLo +#define SB_PMIO_REG27 0x027 // CpuControli +#define SB_PMIO_REG28 0x028 // AcpiGpe0BlkLo +#define SB_PMIO_REG29 0x029 // AcpiGpe0Blki +#define SB_PMIO_REG2A 0x02A // AcpiSmiCmdLo +#define SB_PMIO_REG2B 0x02B // AcpiSmiCmdi +#define SB_PMIO_REG2C 0x02C // AcpiPmaCntBlkLo +#define SB_PMIO_REG2D 0x02D // AcpiPmaCntBlki +#define SB_PMIO_REG2E 0x02E // AcpiSsCntBlkLo +#define SB_PMIO_REG2F 0x02F // AcpiSsCntBlki +#define SB_PMIO_REG30 0x030 // GEvtConfig0 +#define SB_PMIO_REG31 0x031 // GEvtConfig1 +#define SB_PMIO_REG32 0x032 // GPMConfig0 +#define SB_PMIO_REG33 0x033 // GPMConfig1 +#define SB_PMIO_REG34 0x034 // GPMConfig2 +#define SB_PMIO_REG35 0x035 // GPMConfig3 +#define SB_PMIO_REG36 0x036 // GEvtLevelConfig +#define SB_PMIO_REG37 0x037 // GPMLevelConfig0 +#define SB_PMIO_REG38 0x038 // GPMLevelConfig1 +#define SB_PMIO_REG39 0x039 // GEvtStatus +#define SB_PMIO_REG3A 0x03A // PMEStatus0 +#define SB_PMIO_REG3B 0x03B // PMEStatus1 +#define SB_PMIO_REG3C 0x03C // OtersConfig +#define SB_PMIO_REG3E 0x03E // VRT_T1 +#define SB_PMIO_REG3F 0x03F // VRT_T2 +#define SB_PMIO_REG40 0x040 // Fan0DutyCycle +#define SB_PMIO_REG41 0x041 // Fan0Control +#define SB_PMIO_REG42 0x042 // Fan1DutyCycle +#define SB_PMIO_REG43 0x043 // Reserved for internal use +#define SB_PMIO_REG50 0x050 // PM_Enable +#define SB_PMIO_REG51 0x051 // TPRESET1 +#define SB_PMIO_REG52 0x052 // TPRESET2 +#define SB_PMIO_REG53 0x053 // TESTENABLE +#define SB_PMIO_REG54 0x054 // PWRBTTN_CLR +#define SB_PMIO_REG55 0x055 // SoftPciRst +#define SB_PMIO_REG56 0x056 // Reserved +#define SB_PMIO_REG59 0x059 // Ac97Mask +#define SB_PMIO_REG60 0x060 // Options_0 +#define SB_PMIO_REG61 0x061 // Options_1 +#define SB_PMIO_REG62 0x062 // Sadow_SCI +#define SB_PMIO_REG63 0x063 // SwitcVoltageTime +#define SB_PMIO_REG64 0x064 // SwitchGI_Time +#define SB_PMIO_REG65 0x065 // UsbPMControl +#define SB_PMIO_REG66 0x066 // MiscEnable66 +#define SB_PMIO_REG67 0x067 // MiscEnable67 +#define SB_PMIO_REG68 0x068 // MiscEnable68 +#define SB_PMIO_REG69 0x069 // WatcDogTimerControl +#define SB_PMIO_REG6C 0x06C // WatcDogTimerBase0 +#define SB_PMIO_REG6D 0x06D // WatcDogTimerBase1 +#define SB_PMIO_REG6E 0x06E // WatcDogTimerBase2 +#define SB_PMIO_REG6F 0x06F // WatcDogTimerBase3 +#define SB_PMIO_REG70 0x070 // S_LdtStartTime +#define SB_PMIO_REG71 0x071 // FidVidOption +#define SB_PMIO_REG72 0x072 // Spare4 +#define SB_PMIO_REG73 0x073 // Spare5 +#define SB_PMIO_REG74 0x074 // PwrFailSadow +#define SB_PMIO_REG75 0x075 // Tpreset1b +#define SB_PMIO_REG76 0x076 // S0S3ToS5Enable0 +#define SB_PMIO_REG77 0x077 // S0S3ToS5Enable1 +#define SB_PMIO_REG78 0x078 // S0S3ToS5Enable2 +#define SB_PMIO_REG79 0x079 // S0S3ToS5Enable3 +#define SB_PMIO_REG7A 0x07A // NoStatusControl0 +#define SB_PMIO_REG7B 0x07B // NoStatusControl1 +#define SB_PMIO_REG7C 0x07C // MiscEnable7C +#define SB_PMIO_REG80 0x080 // SMAF0 +#define SB_PMIO_REG81 0x081 // SMAF1 +#define SB_PMIO_REG82 0x082 // SMAF2 +#define SB_PMIO_REG83 0x083 // SMAF3 +#define SB_PMIO_REG84 0x084 // WakePinCntl +#define SB_PMIO_REG85 0x085 // CF9Rst +#define SB_PMIO_REG86 0x086 // ThermTrotCntl +#define SB_PMIO_REG87 0x087 // LdtStpCmd +#define SB_PMIO_REG88 0x088 // LdtStartTime +#define SB_PMIO_REG89 0x089 // AgpStartTime +#define SB_PMIO_REG8A 0x08A // LdtAgpTimeCntl +#define SB_PMIO_REG8B 0x08B // StutterTime +#define SB_PMIO_REG8C 0x08C // StpClkDlyTime +#define SB_PMIO_REG8D 0x08D // AbPmeCntl +#define SB_PMIO_REG8E 0x08E // FakeAsr +#define SB_PMIO_REG8F 0x08F // FakeAsrEn +#define SB_PMIO_REG90 0x090 // GEVENTOUT +#define SB_PMIO_REG91 0x091 // GEVENTEnable +#define SB_PMIO_REG92 0x092 // GEVENTIN +#define SB_PMIO_REG95 0x095 // GPM98EN +#define SB_PMIO_REG9A 0x09A // EnanceControl +#define SB_PMIO_REG9E 0x09E // EnanceControl +#define SB_PMIO_REG9F 0x09F // EnanceControl +#define SB_PMIO_REGA0 0x0A0 // Programlo4RangeLo +#define SB_PMIO_REGA1 0x0A1 // ProgramIo4Rangei +#define SB_PMIO_REGA2 0x0A2 // Programlo5RangeLo +#define SB_PMIO_REGA3 0x0A3 // ProgramIo5Rangei +#define SB_PMIO_REGA4 0x0A4 // Programlo6RangeLo +#define SB_PMIO_REGA5 0x0A5 // ProgramIo6Rangei +#define SB_PMIO_REGA6 0x0A6 // Programlo7RangeLo +#define SB_PMIO_REGA7 0x0A7 // ProgramIo7Rangei +#define SB_PMIO_REGA8 0x0A8 // PIO7654Enable +#define SB_PMIO_REGA9 0x0A9 // PIO7654Status +#define SB_PMIO_REGB0 0x0B0 +#define SB_PMIO_REGB1 0x0B1 +#define SB_PMIO_REGB2 0x0B2 // MiscControl3 +#define SB_PMIO_REGB4 0x0B4 // HPET BAR +#define SB_PMIO_REGB6 0x0B6 +#define SB_PMIO_REGB7 0x0B7 +#define SB_PMIO_REGBB 0x0BB // IMC_ACPI_Enable +#define SB_PMIO_REGBC 0x0BC // +#define SB_PMIO_REGBD 0x0BD // +#define SB_PMIO_REGC9 0x0C9 // MultiK8Control +#define SB_PMIO_REGCA 0x0CA // +#define SB_PMIO_REGCB 0x0CB // +#define SB_PMIO_REGCC 0x0CC // +#define SB_PMIO_REGCD 0x0CD // +#define SB_PMIO_REGD0 0x0D0 // +#define SB_PMIO_REGD2 0x0D2 // +#define SB_PMIO_REGD4 0x0D4 // +#define SB_PMIO_REGD7 0x0D7 // + + +#define SB_RTC_REG00 0x00 // Seconds - RW +#define SB_RTC_REG01 0x01 // Seconds Alarm - RW +#define SB_RTC_REG02 0x02 // Minutes - RW +#define SB_RTC_REG03 0x03 // Minutes Alarm - RW +#define SB_RTC_REG04 0x04 // ours - RW +#define SB_RTC_REG05 0x05 // ours Alarm- RW +#define SB_RTC_REG06 0x06 // Day of Week - RW +#define SB_RTC_REG07 0x07 // Date of Mont - RW +#define SB_RTC_REG08 0x08 // Mont - RW +#define SB_RTC_REG09 0x09 // Year - RW +#define SB_RTC_REG0A 0x0A // Register A - RW +#define SB_RTC_REG0B 0x0B // Register B - RW +#define SB_RTC_REG0C 0x0C // Register C - R +#define SB_RTC_REG0D 0x0D // DateAlarm - RW +#define SB_RTC_REG32 0x32 // AltCentury - RW +#define SB_RTC_REG48 0x48 // Century - RW +#define SB_RTC_REG50 0x50 // Extended RAM Address Port - RW +#define SB_RTC_REG53 0x53 // Extended RAM Data Port - RW +#define SB_RTC_REG7E 0x7E // RTC Time Clear - RW +#define SB_RTC_REG7F 0x7F // RTC RAM Enable - RW + +#define B_ECMOS_REG00 0x00 // scratc-reg + //;BIT0=0 AsicDebug is enabled + //;BIT1=0 SLT S3 runs +#define SB_ECMOS_REG01 0x01 +#define SB_ECMOS_REG02 0x02 +#define SB_ECMOS_REG03 0x03 +#define SB_ECMOS_REG04 0x04 +#define SB_ECMOS_REG05 0x05 +#define SB_ECMOS_REG06 0x06 +#define SB_ECMOS_REG07 0x07 +#define SB_ECMOS_REG08 0x08 // save 32BIT Pysical address of Config structure +#define SB_ECMOS_REG09 0x09 +#define SB_ECMOS_REG0A 0x0A +#define SB_ECMOS_REG0B 0x0B + +#define SB_ECMOS_REG0C 0x0C //;save MODULE_ID +#define SB_ECMOS_REG0D 0x0D //;Reserve for NB + +#define SB_IOMAP_REG00 0x000 // Dma_C 0 +#define SB_IOMAP_REG02 0x002 // Dma_C 1 +#define SB_IOMAP_REG04 0x004 // Dma_C 2 +#define SB_IOMAP_REG06 0x006 // Dma_C 3 +#define SB_IOMAP_REG08 0x008 // Dma_Status +#define SB_IOMAP_REG09 0x009 // Dma_WriteRest +#define SB_IOMAP_REG0A 0x00A // Dma_WriteMask +#define SB_IOMAP_REG0B 0x00B // Dma_WriteMode +#define SB_IOMAP_REG0C 0x00C // Dma_Clear +#define SB_IOMAP_REG0D 0x00D // Dma_MasterClr +#define SB_IOMAP_REG0E 0x00E // Dma_ClrMask +#define SB_IOMAP_REG0F 0x00F // Dma_AllMask +#define SB_IOMAP_REG20 0x020 // IntrCntrlReg1 +#define SB_IOMAP_REG21 0x021 // IntrCntrlReg2 +#define SB_IOMAP_REG40 0x040 // TimerC0 +#define SB_IOMAP_REG41 0x041 // TimerC1 +#define SB_IOMAP_REG42 0x042 // TimerC2 +#define SB_IOMAP_REG43 0x043 // Tmr1CntrlWord +#define SB_IOMAP_REG61 0x061 // Nmi_Status +#define SB_IOMAP_REG70 0x070 // Nmi_Enable +#define SB_IOMAP_REG71 0x071 // RtcDataPort +#define SB_IOMAP_REG72 0x072 // AlternatRtcAddrPort +#define SB_IOMAP_REG73 0x073 // AlternatRtcDataPort +#define SB_IOMAP_REG80 0x080 // Dma_Page_Reserved0 +#define SB_IOMAP_REG81 0x081 // Dma_PageC2 +#define SB_IOMAP_REG82 0x082 // Dma_PageC3 +#define SB_IOMAP_REG83 0x083 // Dma_PageC1 +#define SB_IOMAP_REG84 0x084 // Dma_Page_Reserved1 +#define SB_IOMAP_REG85 0x085 // Dma_Page_Reserved2 +#define SB_IOMAP_REG86 0x086 // Dma_Page_Reserved3 +#define SB_IOMAP_REG87 0x087 // Dma_PageC0 +#define SB_IOMAP_REG88 0x088 // Dma_Page_Reserved4 +#define SB_IOMAP_REG89 0x089 // Dma_PageC6 +#define SB_IOMAP_REG8A 0x08A // Dma_PageC7 +#define SB_IOMAP_REG8B 0x08B // Dma_PageC5 +#define SB_IOMAP_REG8C 0x08C // Dma_Page_Reserved5 +#define SB_IOMAP_REG8D 0x08D // Dma_Page_Reserved6 +#define SB_IOMAP_REG8E 0x08E // Dma_Page_Reserved7 +#define SB_IOMAP_REG8F 0x08F // Dma_Refres +#define SB_IOMAP_REG92 0x092 // FastInit +#define SB_IOMAP_REGA0 0x0A0 // IntrCntrl2Reg1 +#define SB_IOMAP_REGA1 0x0A1 // IntrCntrl2Reg2 +#define SB_IOMAP_REGC0 0x0C0 // Dma2_C4Addr +#define SB_IOMAP_REGC2 0x0C2 // Dma2_C4Cnt +#define SB_IOMAP_REGC4 0x0C4 // Dma2_C5Addr +#define SB_IOMAP_REGC6 0x0C6 // Dma2_C5Cnt +#define SB_IOMAP_REGC8 0x0C8 // Dma2_C6Addr +#define SB_IOMAP_REGCA 0x0CA // Dma2_C6Cnt +#define SB_IOMAP_REGCC 0x0CC // Dma2_C7Addr +#define SB_IOMAP_REGCE 0x0CE // Dma2_C7Cnt +#define SB_IOMAP_REGD0 0x0D0 // Dma_Status +#define SB_IOMAP_REGD2 0x0D2 // Dma_WriteRest +#define SB_IOMAP_REGD4 0x0D4 // Dma_WriteMask +#define SB_IOMAP_REGD6 0x0D6 // Dma_WriteMode +#define SB_IOMAP_REGD8 0x0D8 // Dma_Clear +#define SB_IOMAP_REGDA 0x0DA // Dma_Clear +#define SB_IOMAP_REGDC 0x0DC // Dma_ClrMask +#define SB_IOMAP_REGDE 0x0DE // Dma_ClrMask +#define SB_IOMAP_REGF0 0x0F0 // NCP_Error +#define SB_IOMAP_REG40B 0x040B // DMA1_Extend +#define SB_IOMAP_REG4D0 0x04D0 // IntrEdgeControl +#define SB_IOMAP_REG4D6 0x04D6 // DMA2_Extend +#define SB_IOMAP_REGC00 0x0C00 // Pci_Intr_Index +#define SB_IOMAP_REGC01 0x0C01 // Pci_Intr_Data +#define SB_IOMAP_REGC14 0x0C14 // Pci_Error +#define SB_IOMAP_REGC50 0x0C50 // CMIndex +#define SB_IOMAP_REGC51 0x0C51 // CMData +#define SB_IOMAP_REGC52 0x0C52 // GpmPort +#define SB_IOMAP_REGC6F 0x0C6F // Isa_Misc +#define SB_IOMAP_REGCD0 0x0CD0 // PMio2_Index +#define SB_IOMAP_REGCD1 0x0CD1 // PMio2_Data +#define SB_IOMAP_REGCD4 0x0CD4 // BIOSRAM_Index +#define SB_IOMAP_REGCD5 0x0CD5 // BIOSRAM_Data +#define SB_IOMAP_REGCD6 0x0CD6 // PM_Index +#define SB_IOMAP_REGCD7 0x0CD7 // PM_Data +#define SB_IOMAP_REGCF9 0x0CF9 // CF9Rst reg + + +#define SB_CM_REG02 0x002 // TempStatus (via SB_IOMAP_REGC50) +#define SB_CM_REG03 0x003 // TempInterrupt (via SB_IOMAP_REGC50) + +#define SB_SATA_REG00 0x000 // Vendor ID - R- 16 bits +#define SB_SATA_REG02 0x002 // Device ID - RW -16 bits +#define SB_SATA_REG04 0x004 // PCI Command - RW - 16 bits +#define SB_SATA_REG06 0x006 // PCI Status - RW - 16 bits +#define SB_SATA_REG08 0x008 // Revision ID/PCI Class Code - R - 32 bits - Offset: 08 +#define SB_SATA_REG0C 0x00C // Cace Line Size - R/W - 8bits +#define SB_SATA_REG0D 0x00D // Latency Timer - RW - 8 bits +#define SB_SATA_REG0E 0x00E // eader Type - R - 8 bits +#define SB_SATA_REG0F 0x00F // BIST - R - 8 bits +#define SB_SATA_REG10 0x010 // Base Address Register 0 - RW - 32 bits +#define SB_SATA_REG14 0x014 // Base Address Register 1 - RW- 32 bits +#define SB_SATA_REG18 0x018 // Base Address Register 2 - RW - 32 bits +#define SB_SATA_REG1C 0x01C // Base Address Register 3 - RW - 32 bits +#define SB_SATA_REG20 0x020 // Base Address Register 4 - RW - 32 bits +#define SB_SATA_REG24 0x024 // Base Address Register 5 - RW - 32 bits +#define SB_SATA_REG2C 0x02C // Subsystem Vendor ID - R - 16 bits +#define SB_SATA_REG2D 0x02D // Subsystem ID - R - 16 bits +#define SB_SATA_REG30 0x030 // Expansion ROM Base Address - 32 bits +#define SB_SATA_REG34 0x034 // Capabilities Pointer - R - 32 bits +#define SB_SATA_REG3C 0x03C // Interrupt Line - RW - 8 bits +#define SB_SATA_REG3D 0x03D // Interrupt Pin - R - 8 bits +#define SB_SATA_REG3E 0x03E // Min Grant - R - 8 bits +#define SB_SATA_REG3F 0x03F // Max Latency - R - 8 bits +#define SB_SATA_REG40 0x040 // Configuration - RW - 32 bits +#define SB_SATA_REG44 0x044 // Software Data Register - RW - 32 bits +#define SB_SATA_REG48 0x048 +#define SB_SATA_REG50 0x050 // Message Capability - R - 16 bits +#define SB_SATA_REG52 0x052 // Message Control - R/W - 16 bits +#define SB_SATA_REG54 0x054 // Message Address - R/W - 32 bits +#define SB_SATA_REG58 0x058 // Message Data - R/W - 16 bits +#define SB_SATA_REG5C 0x05C // RAMBIST Control Register - R/W - 8 bits +#define SB_SATA_REG5D 0x05D // RAMBIST Status0 Register - R - 8 bits +#define SB_SATA_REG5E 0x05E // RAMBIST Status1 Register - R - 8 bits +#define SB_SATA_REG60 0x060 // Power Management Capabilities - R - 32 bits +#define SB_SATA_REG64 0x064 // Power Management Control + Status - RW - 32 bits +#define SB_SATA_REG68 0x068 // MSI Program Weigt - R/W - 8 bits +#define SB_SATA_REG69 0x069 // PCI Burst Timer - R/W - 8 bits +#define SB_SATA_REG70 0x070 // PCI Bus Master - IDE0 - RW - 32 bits +#define SB_SATA_REG74 0x074 // PRD Table Address - IDE0 - RW - 32 bits +#define SB_SATA_REG78 0x078 // PCI Bus Master - IDE1 - RW - 32 bits +#define SB_SATA_REG7C 0x07C // PRD Table Address - IDE1 - RW - 32 bits +#define SB_SATA_REG80 0x080 // Data Transfer Mode - IDE0 - RW - 32 bits +#define SB_SATA_REG84 0x084 // Data Transfer Mode - IDE1 - RW - 32 bits +#define SB_SATA_REG86 0x086 // PY Global Control +#define SB_SATA_REG87 0x087 +#define SB_SATA_REG88 0x088 // PHY Port0 Control - Port0 PY fine tune(0:23) +#define SB_SATA_REG8A 0x08A +#define SB_SATA_REG8C 0x08C // PHY Port1 Control - Port0 PY fine tune(0:23) +#define SB_SATA_REG8E 0x08E +#define SB_SATA_REG90 0x090 // PHY Port2 Control - Port0 PY fine tune(0:23) +#define SB_SATA_REG92 0x092 +#define SB_SATA_REG94 0x094 // PHY Port3 Control - Port0 PY fine tune(0:23) +#define SB_SATA_REG96 0x096 +#define SB_SATA_REG98 0x098 // EEPROM Memory Address - Command + Status - RW - 32 bits +#define SB_SATA_REG9C 0x09C // EEPROM Memory Data - RW - 32 bits +#define SB_SATA_REGA0 0x0A0 // +#define SB_SATA_REGA4 0x0A4 // +#define SB_SATA_REGA5 0x0A5 //; +#define SB_SATA_REGA8 0x0A8 // +#define SB_SATA_REGAD 0x0AD //; +#define SB_SATA_REGB0 0x0B0 // IDE1 Task File Configuration + Status - RW - 32 bits +#define SB_SATA_REGB5 0x0B5 //; +#define SB_SATA_REGBD 0x0BD //; +#define SB_SATA_REGC0 0x0C0 // BA5 Indirect Address - RW - 32 bits +#define SB_SATA_REGC4 0x0C4 // BA5 Indirect Access - RW - 32 bits + +#define SB_SATA_BAR5_REG00 0x000 // PCI Bus Master - IDE0 - RW - 32 bits +#define SB_SATA_BAR5_REG04 0x004 // PRD Table Address - IDE0 - RW - 32 bits +#define SB_SATA_BAR5_REG08 0x008 // PCI Bus Master - IDE1 - RW - 32 bits +#define SB_SATA_BAR5_REG0C 0x00C // PRD Table Address - IDE1 - RW - 32 bits +#define SB_SATA_BAR5_REG10 0x010 // PCI Bus Master2 - IDE0 - RW - 32 bits +#define SB_SATA_BAR5_REG18 0x018 // PCI Bus Master2 - IDE1 - RW - 32 bits +#define SB_SATA_BAR5_REG20 0x020 // PRD Address - IDE0 - RW - 32 bits +#define SB_SATA_BAR5_REG24 0x024 // PCI Bus Master Byte Count - IDE0- RW - 32 bits +#define SB_SATA_BAR5_REG28 0x028 // PRD Address - IDE1 - RW - 32 bits +#define SB_SATA_BAR5_REG2C 0x02C // PCI Bus Master Byte Count - IDE1 - RW - 32 bits +#define SB_SATA_BAR5_REG40 0x040 // FIFO Valid Byte Count and Control - IDE0 - RW - 32 bits +#define SB_SATA_BAR5_REG44 0x044 // FIFO Valid Byte Count and Control - IDE1 - RW - 32 bits +#define SB_SATA_BAR5_REG48 0x048 // System Configuration Status - Command - RW - 32 bits +#define SB_SATA_BAR5_REG4C 0x04C // System Software Data Register - RW - 32 bits +#define SB_SATA_BAR5_REG50 0x050 // FLAS Memory Address - Command + Status - RW - 32 bits +#define SB_SATA_BAR5_REG54 0x054 // FLAS Memory Data - RW - 32 bits +#define SB_SATA_BAR5_REG58 0x058 // EEPROM Memory Address - Command + Status - RW - 32 bits +#define SB_SATA_BAR5_REG5C 0x05C // EEPROM Memory Data - RW - 32 bits +#define SB_SATA_BAR5_REG60 0x060 // FIFO Port - IDE0 - RW - 32 bits +#define SB_SATA_BAR5_REG68 0x068 // FIFO Pointers1- IDE0 - RW - 32 bits +#define SB_SATA_BAR5_REG6C 0x06C // FIFO Pointers2- IDE0 - RW - 32 bits +#define SB_SATA_BAR5_REG70 0x070 // FIFO Port - IDE1- RW - 32 bits +#define SB_SATA_BAR5_REG78 0x078 // FIFO Pointers1- IDE1- RW - 32 bits +#define SB_SATA_BAR5_REG7C 0x07C // FIFO Pointers2- IDE1- RW - 32 bits +#define SB_SATA_BAR5_REG80 0x080 // IDE0 Task File Register 0- RW - 32 bits +#define SB_SATA_BAR5_REG84 0x084 // IDE0 Task File Register 1- RW - 32 bits +#define SB_SATA_BAR5_REG88 0x088 // IDE0 Task File Register 2- RW - 32 bits +#define SB_SATA_BAR5_REG8C 0x08C // IDE0 Read Aead Data - RW - 32 bits +#define SB_SATA_BAR5_REG90 0x090 // IDE0 Task File Register 0 - Command Buffering - RW - 32 bits +#define SB_SATA_BAR5_REG94 0x094 // IDE0 Task File Register 1 - Command Buffering - RW - 32 bits +#define SB_SATA_BAR5_REG9C 0x09C // IDE0 Virtual DMA/PIO Read Aead Byte Count - RW - 32 bits +#define SB_SATA_BAR5_REGA0 0x0A0 // IDE0 Task File Configuration + Status - RW - 32 bits +#define SB_SATA_BAR5_REGB4 0x0B4 // Data Transfer Mode -IDE0 - RW - 32 bits +#define SB_SATA_BAR5_REGC0 0x0C0 // IDE1 Task File Register 0 - RW - 32 bits +#define SB_SATA_BAR5_REGC4 0x0C4 // IDE1 Task File Register 1 - RW - 32 bits +#define SB_SATA_BAR5_REGC8 0x0C8 // IDE1 Task File Register 2 - RW - 32 bits +#define SB_SATA_BAR5_REGCC 0x0CC // Read/Write Aead Data - RW - 32 bits +#define SB_SATA_BAR5_REGD0 0x0D0 // IDE1 Task File Register 0 - Command Buffering - RW - 32 bits +#define SB_SATA_BAR5_REGD4 0x0D4 // IDE1 Task File Register 1 - Command Buffering - RW - 32 bits +#define SB_SATA_BAR5_REGDC 0x0DC // IDE1 Virtual DMA/PIO Read Aead Byte Count - RW - 32 bits +#define SB_SATA_BAR5_REGE0 0x0E0 // IDE1 Task File Configuration + Status - RW - 32 bits +#define SB_SATA_BAR5_REGF4 0x0F4 // Data Transfer Mode - IDE1 - RW - 32 bits +#define SB_SATA_BAR5_REGF8 0x0F8 // PORT Configuration +#define SB_SATA_BAR5_REGFC 0x0FC + +#define SB_SATA_BAR5_REG100 0x0100 //;Serial ATA SControl - RW - 32 bits - [Offset: 100h (channel 1) / 180 +#define SB_SATA_BAR5_REG104 0x0104 //;Serial ATA Sstatus - RW - 32 bits - [Offset: 104h (channel 1) / 184h (cannel +#define SB_SATA_BAR5_REG108 0x0108 //;Serial ATA Serror - RW - 32 bits - [Offset: 108h (channel 1) / 188h (cannel +#define SB_SATA_BAR5_REG10C 0x010C //;Serial ATA Sdevice - RW - 32 bits - [Offset: 10Ch (channel 1) / 18Ch (cannel +#define SB_SATA_BAR5_REG110 0x0110 // Port-N Interrupt Status +#define SB_SATA_BAR5_REG144 0x0144 //;Serial ATA PY Configuration - RW - 32 bits +#define SB_SATA_BAR5_REG148 0x0148 //;SIEN - RW - 32 bits - [Offset: 148 (channel 1) / 1C8 (cannel 2)] +#define SB_SATA_BAR5_REG14C 0x014C //;SFISCfg - RW - 32 bits - [Offset: 14C (channel 1) / 1CC (cannel 2)] +#define SB_SATA_BAR5_REG120 0x0120 // Port Task Fike Data +#define SB_SATA_BAR5_REG128 0x0128 // Port Serial ATA Status +#define SB_SATA_BAR5_REG12C 0x012C // Port Serial ATA Control + +#define SB_SATA_BAR5_REG130 0x0130 +#define SB_SATA_BAR5_REG1B0 0x01B0 +#define SB_SATA_BAR5_REG230 0x0230 +#define SB_SATA_BAR5_REG2B0 0x02B0 + +#define SB_FC_REG00 0x00 // Device/Vendor ID - R +#define SB_FC_REG04 0x04 // Command - RW +#define SB_FC_REG10 0x10 // BAR + +#define SB_FC_MMIO_REG70 0x070 +#define SB_FC_MMIO_REG200 0x200 + +#define SB_OHCI_REG00 0x00 // Device/Vendor ID - R +#define SB_OHCI_REG04 0x04 // Command - RW +#define SB_OHCI_REG06 0x06 // Status - R +#define SB_OHCI_REG08 0x08 // Revision ID/Class Code - R +#define SB_OHCI_REG0C 0x0C // Miscellaneous - RW +#define SB_OHCI_REG10 0x10 // Bar_OCI - RW +#define SB_OHCI_REG2C 0x2C // Subsystem Vendor ID/ Subsystem ID - RW +#define SB_OHCI_REG34 0x34 // Capability Pointer - R +#define SB_OHCI_REG3C 0x3C // Interrupt Line - RW +#define SB_OHCI_REG3D 0x3D // Interrupt Line - RW + +#define SB_OHCI_REG40 0x40 // Config Timers - RW +#define SB_OHCI_REG4C 0x4C // MSI Weigt - RW +#define SB_OHCI_REG50 0x50 // ATI Misc Control - RW +#define SB_OHCI_REG51 0x51 +#define SB_OHCI_REG58 0x58 // Over Current Control - RW +#define SB_OHCI_REG5C 0x5C // Over Current Control - RW +#define SB_OHCI_REG60 0x60 // Serial Bus Release Number - R +#define SB_OHCI_REG68 0x68 // Over Current Enable - RW +#define SB_OHCI_REGD0 0x0D0 // MSI Control - RW +#define SB_OHCI_REGD4 0x0D4 // MSI Address - RW +#define SB_OHCI_REGD8 0x0D8 // MSI Data - RW +#define SB_OHCI_BAR_REG00 0x00 // cRevision - R +#define SB_OHCI_BAR_REG04 0x04 // cControl +#define SB_OHCI_BAR_REG08 0x08 // cCommandStatus +#define SB_OHCI_BAR_REG0C 0x0C // cInterruptStatus RW +#define SB_OHCI_BAR_REG10 0x10 // cInterruptEnable +#define SB_OHCI_BAR_REG14 0x14 // cInterruptDisable +#define SB_OHCI_BAR_REG18 0x18 // HcCCA +#define SB_OHCI_BAR_REG1C 0x1C // cPeriodCurrentED +#define SB_OHCI_BAR_REG20 0x20 // HcControleadED +#define SB_OHCI_BAR_REG24 0x24 // cControlCurrentED RW +#define SB_OHCI_BAR_REG28 0x28 // HcBulkeadED +#define SB_OHCI_BAR_REG2C 0x2C // cBulkCurrentED- RW +#define SB_OHCI_BAR_REG30 0x30 // HcDoneead +#define SB_OHCI_BAR_REG34 0x34 // cFmInterval +#define SB_OHCI_BAR_REG38 0x38 // cFmRemaining +#define SB_OHCI_BAR_REG3C 0x3C // cFmNumber +#define SB_OHCI_BAR_REG40 0x40 // cPeriodicStart +#define SB_OHCI_BAR_REG44 0x44 // HcLSThresold +#define SB_OHCI_BAR_REG48 0x48 // HcRDescriptorA +#define SB_OHCI_BAR_REG4C 0x4C // HcRDescriptorB +#define SB_OHCI_BAR_REG50 0x50 // HcRStatus +#define SB_OHCI_BAR_REG160 0x160 + +#define SB_EHCI_REG00 0x00 // DEVICE/VENDOR ID - R +#define SB_EHCI_REG04 0x04 // Command - RW +#define SB_EHCI_REG06 0x06 // Status - R +#define SB_EHCI_REG08 0x08 // Revision ID/Class Code - R +#define SB_EHCI_REG0C 0x0C // Miscellaneous - RW +#define SB_EHCI_REG10 0x10 // BAR - RW +#define SB_EHCI_REG2C 0x2C // Subsystem ID/Subsystem Vendor ID - RW +#define SB_EHCI_REG34 0x34 // Capability Pointer - R +#define SB_EHCI_REG3C 0x3C // Interrupt Line - RW +#define SB_EHCI_REG3D 0x3D // Interrupt Line - RW +#define SB_EHCI_REG40 0x40 // Config Timers - RW +#define SB_EHCI_REG4C 0x4C // MSI Weigt - RW +#define SB_EHCI_REG50 0x50 // ATI Misc Control - RW +#define SB_EHCI_REG54 0x54 // ATI Misc Control - RW +#define SB_EHCI_REG58 0x58 // Over Current Control - R +#define SB_EHCI_REG60 0x60 // SBRN - R +#define SB_EHCI_REG61 0x61 // FLADJ - RW +#define SB_EHCI_REG62 0x62 // PORTWAKECAP - RW +#define SB_EHCI_REGD0 0x0D0 // MSI Control - RW +#define SB_EHCI_REGD4 0x0D4 // MSI Address - RW +#define SB_EHCI_REGD8 0x0D8 // MSI Data - RW +#define SB_EHCI_REGDC 0x0DC // PME Control - RW +#define SB_EHCI_REGE0 0x0E0 // PME Data / Status - RW +#define SB_EHCI_BAR_REG00 0x00 // CAPLENGT - R +#define SB_EHCI_BAR_REG02 0x002 // CIVERSION- R +#define SB_EHCI_BAR_REG04 0x004 // CSPARAMS - R +#define SB_EHCI_BAR_REG08 0x008 // CCPARAMS - R +#define SB_EHCI_BAR_REG0C 0x00C // CSP-PORTROUTE - R +#define SB_EHCI_BAR_REG20 0x020 // USBCMD - RW - 32 bits +#define SB_EHCI_BAR_REG24 0x024 // USBSTS - RW - 32 bits +#define SB_EHCI_BAR_REG28 0x028 // USBINTR -RW - 32 bits +#define SB_EHCI_BAR_REG2C 0x02C // FRINDEX -RW - 32 bits +#define SB_EHCI_BAR_REG30 0x030 // CTRLDSSEGMENT -RW - 32 bits +#define SB_EHCI_BAR_REG34 0x034 // PERIODICLISTBASE -RW - 32 bits +#define SB_EHCI_BAR_REG38 0x038 // ASYNCLISTADDR -RW - 32 bits +#define SB_EHCI_BAR_REG60 0x060 // CONFIGFLAG -RW - 32 bits +#define SB_EHCI_BAR_REG64 0x064 // PORTSC(1-N_PORTS) -RW - 32 bits +#define SB_EHCI_BAR_REG84 0x084 // Packet Buffer Thresold Values - RW - 32 bits +#define SB_EHCI_BAR_REG88 0x088 // Packet Buffer Dept Value - RW - 32 bits +#define SB_EHCI_BAR_REG94 0x094 // UTMI Control and Status - RW - 32 bits +#define SB_EHCI_BAR_REG98 0x098 // Bist Control - RW - 32 bits +#define SB_EHCI_BAR_REG9C 0x09C // ATI EOR Control - RW - 32 bits +#define SB_EHCI_BAR_REGA4 0x0A4 // USB IN/OUT FIFO Thresold Setting +#define SB_EHCI_BAR_REGBC 0x0BC // ECI misc Setting +#define SB_EHCI_BAR_REGC0 0x0C0 // USB PHY Auto Calibration Setting + +#define SB_SMBUS_REG00 0x000 //;VendorID - R +#define SB_SMBUS_REG02 0x002 //;DeviceID - R +#define SB_SMBUS_REG04 0x004 // Command- RW +#define SB_SMBUS_REG05 0x005 // Command- RW +#define SB_SMBUS_REG06 0x006 // STATUS- RW +#define SB_SMBUS_REG08 0x008 // Revision ID/Class Code- R +#define SB_SMBUS_REG0A 0x00A //; +#define SB_SMBUS_REG0B 0x00B //; +#define SB_SMBUS_REG0C 0x00C // Cace Line Size- R +#define SB_SMBUS_REG0D 0x00D // Latency Timer- R +#define SB_SMBUS_REG0E 0x00E // eader Type- R +#define SB_SMBUS_REG0F 0x00F // BIST- R +#define SB_SMBUS_REG10 0x010 // Base Address 0- R +#define SB_SMBUS_REG11 0x011 //; +#define SB_SMBUS_REG12 0x012 //; +#define SB_SMBUS_REG13 0x013 //; +#define SB_SMBUS_REG14 0x014 // Base Address 1- R +#define SB_SMBUS_REG18 0x018 // Base Address 2- R +#define SB_SMBUS_REG1C 0x01C // Base Address 3- R +#define SB_SMBUS_REG20 0x020 // Base Address 4- R +#define SB_SMBUS_REG24 0x024 // Base Address 5- R +#define SB_SMBUS_REG28 0x028 // Cardbus CIS Pointer- R +#define SB_SMBUS_REG2C 0x02C // Subsystem Vendor ID- W +#define SB_SMBUS_REG2E 0x02E // Subsystem ID- W +#define SB_SMBUS_REG30 0x030 // Expansion ROM Base Address - R +#define SB_SMBUS_REG34 0x034 // Capability Pointer - R +#define SB_SMBUS_REG38 0x038 +#define SB_SMBUS_REG3C 0x03C // Interrupt Line - R +#define SB_SMBUS_REG3D 0x03D // Interrupt Pin - R +#define SB_SMBUS_REG3E 0x03E // Min_Gnt - R +#define SB_SMBUS_REG3F 0x03F // Max_Lat - R +#define SB_SMBUS_REG40 0x040 // PCI Control- RW +#define SB_SMBUS_REG41 0x041 // MiscFunction- RW +#define SB_SMBUS_REG42 0x042 // DmaLimit- RW +#define SB_SMBUS_REG43 0x043 // DmaEnanceEnable RW +#define SB_SMBUS_REG48 0x048 // ISA Address Decode Control Register #1- RW +#define SB_SMBUS_REG49 0x049 // ISA Address Decode Control Register #2- RW +#define SB_SMBUS_REG4A 0x04A // Scratc Pad- RW +#define SB_SMBUS_REG50 0x050 // PciGpioOutControl- RW +#define SB_SMBUS_REG54 0x054 // PciGpioConfig- RW +#define SB_SMBUS_REG58 0x058 // ASFSMBusIoBase +#define SB_SMBUS_REG59 0x059 //; +#define SB_SMBUS_REG5C 0x05C // Smart Power Control1 +#define SB_SMBUS_REG60 0x060 // MiscEnable- RW +#define SB_SMBUS_REG64 0x064 // Features Enable- RW +#define SB_SMBUS_REG68 0x068 // UsbEnable - RW +#define SB_SMBUS_REG6C 0x06C // TestMode- RW +#define SB_SMBUS_REG70 0x070 // RunTimeTest- R +#define SB_SMBUS_REG74 0x074 // IoApic_Conf- RW +#define SB_SMBUS_REG78 0x078 // IoAddrEnable - R/W +#define SB_SMBUS_REG79 0x079 //; +#define SB_SMBUS_REG7C 0x07C // RTC Control ;VSJ-2005-06-16 +#define SB_SMBUS_REG80 0x080 // GPIO_Out_Cntrl - RW +#define SB_SMBUS_REG81 0x081 // GPIO_Status - R +#define SB_SMBUS_REG90 0x090 // Smbus Base Address - R +#define SB_SMBUS_REG94 0x094 // Reserved - R +#define SB_SMBUS_REG98 0x098 // +#define SB_SMBUS_REGA0 0x0A0 // MoreGPIOIn +C R +#define SB_SMBUS_REGA4 0x0A4 // MoreGPIOIn +C R +#define SB_SMBUS_REGA8 0x0A8 // GPIOControl +C RW +#define SB_SMBUS_REGAC 0x0AC // MiscUsbEt - RW +#define SB_SMBUS_REGAD 0x0AD // MiscSata +#define SB_SMBUS_REGAE 0x0AE +#define SB_SMBUS_REGAF 0x0AF // SataIntMap - RW +#define SB_SMBUS_REGB0 0x0B0 // MSI Mapping Capability - R +#define SB_SMBUS_REGB4 0x0B4 //HPET BASE Address +#define SB_SMBUS_REGBC 0x0BC // PciIntGpio - RW +#define SB_SMBUS_REGBE 0x0BE // UsbIntMap - RW +#define SB_SMBUS_REGC0 0x0C0 // IokHiDrvSt - RW +#define SB_SMBUS_REGD0 0x0D0 // +#define SB_SMBUS_REGD2 0x0D2 // I2CbusConfig - RW +#define SB_SMBUS_REGD3 0x0D3 // I2CCommand - RW +#define SB_SMBUS_REGD4 0x0D4 // I2CSadow1- RW +#define SB_SMBUS_REGD5 0x0D5 // I2Csadow2- RW +#define SB_SMBUS_REGD6 0x0D6 // I2CBusRevision - RW +#define SB_SMBUS_REGE0 0x0E0 // MSI_Weigt +#define SB_SMBUS_REGE1 0x0E1 // MSI_Weigt +#define SB_SMBUS_REGF0 0x0F0 // AB_REG_BAR - RW +#define SB_SMBUS_REGF1 0x0F1 +#define SB_SMBUS_REGF4 0x0F4 // WakeIoAddr- RW +#define SB_SMBUS_REGF8 0x0F8 // ExtendedAddrPort- RW +#define SB_SMBUS_REGFC 0x0FC // ExtendedDataPort- RW + + +#define SB_IDE_REG00 0x00 // Vendor ID +#define SB_IDE_REG02 0x02 // Device ID +#define SB_IDE_REG04 0x04 // Command +#define SB_IDE_REG06 0x06 // Status +#define SB_IDE_REG08 0x08 // Revision ID/Class Code +#define SB_IDE_REG09 0x09 // Class Code +#define SB_IDE_REG0A 0x0A +#define SB_IDE_REG0C 0x0C // Cace Link Size +#define SB_IDE_REG0D 0x0D // Master Latency Timer +#define SB_IDE_REG0E 0x0E // eader Type +#define SB_IDE_REG0F 0x0F // BIST Mode Type +#define SB_IDE_REG10 0x10 // Base Address 0 +#define SB_IDE_REG14 0x14 // Base Address 1 +#define SB_IDE_REG18 0x18 // Base Address 2 +#define SB_IDE_REG1C 0x1C // Base Address 3 +#define SB_IDE_REG20 0x20 // Bus Master Interface Base Address +#define SB_IDE_REG2C 0x2C // Subsystem ID and Subsystem Vendor ID +#define SB_IDE_REG34 0x34 // MSI Capabilities Pointer +#define SB_IDE_REG3C 0x3C // Interrupt Line +#define SB_IDE_REG3D 0x3D // Interrupt Pin +#define SB_IDE_REG3E 0x3E // Min_gnt +#define SB_IDE_REG3F 0x3F // Max_latency +#define SB_IDE_REG40 0x40 // IDE PIO Timing +#define SB_IDE_REG44 0x44 // IDE Legacy DMA (Multi-words DMA) Timing Modes +#define SB_IDE_REG48 0x48 // IDE PIO Control +#define SB_IDE_REG4A 0x4A // IDE PIO Mode +#define SB_IDE_REG4C 0x4C // IDE Status +#define SB_IDE_REG54 0x54 // IDE Ultra DMAControl +#define SB_IDE_REG55 0x55 // IDE Ultra DMA Status +#define SB_IDE_REG56 0x56 // IDE Ultra DMA Mode +#define SB_IDE_REG60 0x60 // IDE PCI Retry Timing Counter +#define SB_IDE_REG61 0x61 // PCI Error Control +#define SB_IDE_REG62 0x62 // IDE Internal Control +#define SB_IDE_REG63 0x63 // IDE Internal Control +#define SB_IDE_REG64 0x64 // IDE PLL Control +#define SB_IDE_REG68 0x68 // IDE MSI Programmable Weigt +#define SB_IDE_REG6C 0x6C // IDE Dynamic Clocking +#define SB_IDE_REG70 0x70 // IDE MSI Control +#define SB_IDE_REG74 0x74 // IDE MSI Address Register +#define SB_IDE_REG78 0x78 // IDE MSI Data Register + + +#define SB_AZ_REG00 0x00 // Vendor ID - R +#define SB_AZ_REG02 0x02 // Device ID - R/W +#define SB_AZ_REG04 0x04 // PCI Command +#define SB_AZ_REG06 0x06 // PCI Status - R/W +#define SB_AZ_REG08 0x08 // Revision ID +#define SB_AZ_REG09 0x09 // Programming Interface +#define SB_AZ_REG0A 0x0A // Sub Class Code +#define SB_AZ_REG0B 0x0B // Base Class Code +#define SB_AZ_REG0C 0x0C // Cace Line Size - R/W +#define SB_AZ_REG0D 0x0D // Latency Timer +#define SB_AZ_REG0E 0x0E // eader Type +#define SB_AZ_REG0F 0x0F // BIST +#define SB_AZ_REG10 0x10 // Lower Base Address Register +#define SB_AZ_REG14 0x14 // Upper Base Address Register +#define SB_AZ_REG2C 0x2C // Subsystem Vendor ID +#define SB_AZ_REG2D 0x2D // Subsystem ID +#define SB_AZ_REG34 0x34 // Capabilities Pointer +#define SB_AZ_REG3C 0x3C // Interrupt Line +#define SB_AZ_REG3D 0x3D // Interrupt Pin +#define SB_AZ_REG3E 0x3E // Minimum Grant +#define SB_AZ_REG3F 0x3F // Maximum Latency +#define SB_AZ_REG40 0x40 // Misc Control 1 +#define SB_AZ_REG42 0x42 // Misc Control 2 Register +#define SB_AZ_REG43 0x43 // Misc Control 3 Register +#define SB_AZ_REG44 0x44 // Interrupt Pin Control Register +#define SB_AZ_REG46 0x46 // Debug Control Register +#define SB_AZ_REG4C 0x4C +#define SB_AZ_REG50 0x50 // Power Management Capability ID +#define SB_AZ_REG52 0x52 // Power Management Capabilities +#define SB_AZ_REG54 0x54 // Power Management Control/Status +#define SB_AZ_REG60 0x60 // MSI Capability ID +#define SB_AZ_REG62 0x62 // MSI Message Control +#define SB_AZ_REG64 0x64 // MSI Message Lower Address +#define SB_AZ_REG68 0x68 // MSI Message Upper Address +#define SB_AZ_REG6C 0x6C // MSI Message Data + +#define SB_AZ_BAR_REG00 0x00 // Global Capabilities - R +#define SB_AZ_BAR_REG02 0x02 // Minor Version - R +#define SB_AZ_BAR_REG03 0x03 // Major Version - R +#define SB_AZ_BAR_REG04 0x04 // Output Payload Capability - R +#define SB_AZ_BAR_REG06 0x06 // Input Payload Capability - R +#define SB_AZ_BAR_REG08 0x08 // Global Control - R/W +#define SB_AZ_BAR_REG0C 0x0C // Wake Enable - R/W +#define SB_AZ_BAR_REG0E 0x0E // State Cange Status - R/W +#define SB_AZ_BAR_REG10 0x10 // Global Status - R/W +#define SB_AZ_BAR_REG18 0x18 // Output Stream Payload Capability - R +#define SB_AZ_BAR_REG1A 0x1A // Input Stream Payload Capability - R +#define SB_AZ_BAR_REG20 0x20 // Interrupt Control - R/W +#define SB_AZ_BAR_REG24 0x24 // Interrupt Status - R/W +#define SB_AZ_BAR_REG30 0x30 // Wall Clock Counter - R +#define SB_AZ_BAR_REG38 0x38 // Stream Syncronization - R/W +#define SB_AZ_BAR_REG40 0x40 // CORB Lower Base Address - R/W +#define SB_AZ_BAR_REG44 0x44 // CORB Upper Base Address - RW +#define SB_AZ_BAR_REG48 0x48 // CORB Write Pointer - R/W +#define SB_AZ_BAR_REG4A 0x4A // CORB Read Pointer - R/W +#define SB_AZ_BAR_REG4C 0x4C // CORB Control - R/W +#define SB_AZ_BAR_REG4D 0x4D // CORB Status - R/W +#define SB_AZ_BAR_REG4E 0x4E // CORB Size - R/W +#define SB_AZ_BAR_REG50 0x50 // RIRB Lower Base Address - RW +#define SB_AZ_BAR_REG54 0x54 // RIRB Upper Address - RW +#define SB_AZ_BAR_REG58 0x58 // RIRB Write Pointer - RW +#define SB_AZ_BAR_REG5A 0x5A // RIRB Response Interrupt Count - R/W +#define SB_AZ_BAR_REG5C 0x5C // RIRB Control - R/W +#define SB_AZ_BAR_REG5D 0x5D // RIRB Status - R/W +#define SB_AZ_BAR_REG5E 0x5E // RIRB Size - R/W +#define SB_AZ_BAR_REG60 0x60 // Immediate Command Output Interface - R/W +#define SB_AZ_BAR_REG64 0x64 // Immediate Command Input Interface - R/W +#define SB_AZ_BAR_REG68 0x68 // Immediate Command Input Interface - R/W +#define SB_AZ_BAR_REG70 0x70 // DMA Position Lower Base Address - R/W +#define SB_AZ_BAR_REG74 0x74 // DMA Position Upper Base Address - R/W +#define SB_AZ_BAR_REG2030 0x2030 // Wall Clock Counter Alias - R + + +#define SB_LPC_REG00 0x00 // VID- R +#define SB_LPC_REG02 0x02 // DID- R +#define SB_LPC_REG04 0x04 // CMD- RW +#define SB_LPC_REG06 0x06 // STATUS- RW +#define SB_LPC_REG08 0x08 // Revision ID/Class Code - R +#define SB_LPC_REG0C 0x0C // Cace Line Size - R +#define SB_LPC_REG0D 0x0D // Latency Timer - R +#define SB_LPC_REG0E 0x0E // eader Type - R +#define SB_LPC_REG0F 0x0F // BIST- R +#define SB_LPC_REG10 0x10 // Base Address Reg 0- RW* +#define SB_LPC_REG2C 0x2C // Subsystem ID & Subsystem Vendor ID - Wo/Ro +#define SB_LPC_REG34 0x34 // Capabilities Pointer - Ro +#define SB_LPC_REG40 0x40 // PCI Control - RW +#define SB_LPC_REG44 0x44 // IO Port Decode Enable Register 1- RW +#define SB_LPC_REG45 0x45 // IO Port Decode Enable Register 2- RW +#define SB_LPC_REG46 0x46 // IO Port Decode Enable Register 3- RW +#define SB_LPC_REG47 0x47 // IO Port Decode Enable Register 4- RW +#define SB_LPC_REG48 0x48 // IO/Mem Port Decode Enable Register 5- RW +#define SB_LPC_REG49 0x49 // LPC Sync Timeout Count - RW +#define SB_LPC_REG4A 0x4A // IO/Mem Port Decode Enable Register 6- RW +#define SB_LPC_REG4C 0x4C // Memory Range Register - RW +#define SB_LPC_REG50 0x50 // Rom Protect 0 - RW +#define SB_LPC_REG54 0x54 // Rom Protect 1 - RW +#define SB_LPC_REG58 0x58 // Rom Protect 2 - RW +#define SB_LPC_REG5C 0x5C // Rom Protect 3 - RW +#define SB_LPC_REG60 0x60 // PCI Memory Start Address of LPC Target Cycles - +#define SB_LPC_REG62 0x62 // PCI Memory End Address of LPC Target Cycles - +#define SB_LPC_REG64 0x64 // PCI IO base Address of Wide Generic Port - RW +#define SB_LPC_REG65 0x65 +#define SB_LPC_REG66 0x66 +#define SB_LPC_REG67 0x67 +#define SB_LPC_REG68 0x68 // LPC ROM Address Range 1 (Start Address) - RW +#define SB_LPC_REG69 0x69 +#define SB_LPC_REG6A 0x6A // LPC ROM Address Range 1 (End Address) - RW +#define SB_LPC_REG6B 0x6B +#define SB_LPC_REG6C 0x6C // LPC ROM Address Range 2 (Start Address)- RW +#define SB_LPC_REG6D 0x6D +#define SB_LPC_REG6E 0x6E // LPC ROM Address Range 2 (End Address) - RW +#define SB_LPC_REG6F 0x6F +#define SB_LPC_REG70 0x70 // Firmware ub Select - RW* +#define SB_LPC_REG71 0x71 +#define SB_LPC_REG72 0x72 +#define SB_LPC_REG73 0x73 +#define SB_LPC_REG74 0x74 // Alternative Wide IO Range Enable- W/R +#define SB_LPC_REG78 0x78 // Miscellaneous Control Bits- W/R +#define SB_LPC_REG7C 0x7C // TPM (trusted plant form module) reg- W/R +#define SB_LPC_REG9C 0x9C +#define SB_LPC_REG80 0x80 // MSI Capability Register- R +#define SB_LPC_REG8C 0x8C +#define SB_LPC_REGA0 0x0A0 // SPI base address +#define SB_LPC_REGA1 0x0A1 // SPI base address +#define SB_LPC_REGA2 0x0A2 // SPI base address +#define SB_LPC_REGA3 0x0A3 // SPI base address +#define SB_LPC_REGA4 0x0A4 +#define SB_LPC_REGB8 0x0B8 +#define SB_LPC_REGBA 0x0BA // EcControl +#define SB_LPC_REGBB 0x0BB // HostControl + + +#define SB_P2P_REG00 0x00 // VID - R +#define SB_P2P_REG02 0x02 // DID - R +#define SB_P2P_REG04 0x04 // CMD- RW +#define SB_P2P_REG06 0x06 // STATUS- RW +#define SB_P2P_REG08 0x08 // Revision ID/Class Code- R +#define SB_P2P_REG0C 0x0C // CSIZE- RW +#define SB_P2P_REG0D 0x0D // LTIMER- RW +#define SB_P2P_REG0E 0x0E // TYPE- R +#define SB_P2P_REG18 0x18 // PBN- RW +#define SB_P2P_REG19 0x19 // SBN- RW +#define SB_P2P_REG1A 0x1A // SUBBN- RW +#define SB_P2P_REG1B 0x1B // SLTIMER- RW +#define SB_P2P_REG1C 0x1C // IOBASE- RW +#define SB_P2P_REG1D 0x1D // IOLMT- RW +#define SB_P2P_REG1E 0x1E // SSTATUS- RW +#define SB_P2P_REG20 0x20 // MBASE- RW +#define SB_P2P_REG21 0x21 +#define SB_P2P_REG22 0x22 // MLMT- RW +#define SB_P2P_REG23 0x23 +#define SB_P2P_REG24 0x24 // PMBASE- RW +#define SB_P2P_REG25 0x25 +#define SB_P2P_REG26 0x26 // PMLMT- RW +#define SB_P2P_REG27 0x27 +#define SB_P2P_REG30 0x30 // IOBU16- RW +#define SB_P2P_REG32 0x32 // IOLU16- RW +#define SB_P2P_REG34 0x34 // ECP_PTR- R +#define SB_P2P_REG3C 0x3C // INTLN- RW +#define SB_P2P_REG3D 0x3D // INTPN- R +#define SB_P2P_REG3E 0x3E // BCTRL- RW +#define SB_P2P_REG40 0x40 // CPCTRL- R/W +#define SB_P2P_REG41 0x41 // DCTRL- RW +#define SB_P2P_REG42 0x42 // CLKCTRL- R/W +#define SB_P2P_REG43 0x43 // ARCTRL- RW +#define SB_P2P_REG44 0x44 // SMLT_PERF- RW +#define SB_P2P_REG46 0x46 // PMLT_PERF- RW +#define SB_P2P_REG48 0x48 // PCDMA- RW +#define SB_P2P_REG49 0x49 // Additional Priority- Bits RW +#define SB_P2P_REG4A 0x4A // PCICLK Enable- Bits RW +#define SB_P2P_REG4B 0x4B // Misc Control RW +#define SB_P2P_REG4C 0x4C // AutoClockRun control RW +#define SB_P2P_REG50 0x50 // Dual Address Cycle Enable and PCIB_CLK_Stop +#define SB_P2P_REG54 0x54 // MSI Mapping Capability +#define SB_P2P_REG58 0x58 // Signature Register of Microsoft Rework +#define SB_P2P_REG64 0x64 // Misc Control Register +#define SB_P2P_REG65 0x65 // Misc Control Register + +#define SB_PMIO2_REG00 0x00 +#define SB_PMIO2_REG01 0x01 +#define SB_PMIO2_REG31 0x31 +#define SB_PMIO2_REG32 0x32 +#define SB_PMIO2_REG33 0x33 +#define SB_PMIO2_REG34 0x34 +#define SB_PMIO2_REG35 0x35 +#define SB_PMIO2_REG36 0x36 +#define SB_PMIO2_REG37 0x37 +#define SB_PMIO2_REG38 0x38 +#define SB_PMIO2_REG39 0x39 +#define SB_PMIO2_REG3A 0x3A +#define SB_PMIO2_REG3B 0x3B +#define SB_PMIO2_REG3C 0x3C +#define SB_PMIO2_REG3D 0x3D +#define SB_PMIO2_REG3E 0x3E +#define SB_PMIO2_REG3F 0x3F +#define SB_PMIO2_REG40 0x40 +#define SB_PMIO2_REG41 0x41 +#define SB_PMIO2_REG42 0x42 +#define SB_PMIO2_REG43 0x43 +#define SB_PMIO2_REG44 0x44 +#define SB_PMIO2_REG45 0x45 +#define SB_PMIO2_REG46 0x46 +#define SB_PMIO2_REG47 0x47 +#define SB_PMIO2_REG48 0x48 +#define SB_PMIO2_REG49 0x49 +#define SB_PMIO2_REG54 0x54 +#define SB_PMIO2_REG58 0x58 +#define SB_PMIO2_REG59 0x59 +#define SB_PMIO2_REG5A 0x5A +#define SB_PMIO2_REG5B 0x5B +#define SB_PMIO2_REG5C 0x5C +#define SB_PMIO2_REG70 0x70 +#define SB_PMIO2_REGE5 0xE5 + +#define SB_SPI_MMIO_REG0C 0x0C //SPI_Cntrl1 Register + + +//Bus 0 Device 0x18 Function 0 HyperTransfer +//Link Frequency/Revision Register 0x88/0xA8/0xC8/0xE8 - 32 bits. +#define HT_LINK_REG89 0x89 +#define HT_LINK_REGA9 0xA9 +#define HT_LINK_REGC9 0xC9 +#define HT_LINK_REGE9 0xE9 + +//Link Type Register 0x98/0xB8/0xD8/0xF8 - 32 bits. +#define HT_LINK_REG98 0x98 +#define HT_LINK_REGB8 0xB8 +#define HT_LINK_REGD8 0xD8 +#define HT_LINK_REGF8 0xF8 + +//Link Frequency Extension Register 0x9C/0xBC/0xDC/0xFC - 32 bits. +#define HT_LINK_REG9C 0x9C +#define HT_LINK_REGBC 0xBC +#define HT_LINK_REGDC 0xDC +#define HT_LINK_REGFC 0xFC + +//DRAM CS Base Address Register D18F2x40/x48/x50/x58 +#define DCT_REG40 0x40 +#define DCT_REG48 0x48 +#define DCT_REG50 0x50 +#define DCT_REG58 0x58 + +//DRAM Configuration Low Register D18F2x90/x91/x92/x93 +#define DCT_REG90 0x90 +#define DCT_REG91 0x91 +#define DCT_REG92 0x92 +#define DCT_REG93 0x93 + +#pragma pack(pop) + +#endif //#ifndef _AMD_SB700_H_ diff --git a/src/vendorcode/amd/cimx/sb700/SBCMN.c b/src/vendorcode/amd/cimx/sb700/SBCMN.c new file mode 100644 index 0000000..7d5b4f4 --- /dev/null +++ b/src/vendorcode/amd/cimx/sb700/SBCMN.c @@ -0,0 +1,572 @@ +/***************************************************************************** + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + ***************************************************************************/ + + +#include "Platform.h" + + +REG8MASK sbEarlyPostByteInitTable[]={ + // SMBUS Device(Bus 0, Dev 20, Func 0) + {0x00, SMBUS_BUS_DEV_FUN, 0}, + {SB_SMBUS_REG43, ~(UINT8)BIT3, 0x00}, //Make BAR registers of smbus visible. + {SB_SMBUS_REG24, 0X00, (CIMx_Version & 0xFF)}, //Program the version information + {SB_SMBUS_REG24+1, 0x00, (CIMx_Version >> 8)}, + {SB_SMBUS_REG24+2, 0x00, RC_Information}, + {SB_SMBUS_REG24+3, 0x00, Additional_Changes_Indicator}, + {SB_SMBUS_REG43, ~(UINT8)BIT3, BIT3}, //Make BAR registers of smbus invisible. + {SB_SMBUS_REGAE, ~(UINT8)(BIT6 + BIT5), BIT6 + BIT5}, //Disable Timer IRQ enhancement for proper operation of the 8254 timer. + // [6] - IoApicPicArbEn, set 1 to enable arbiter between APIC and PIC interrupts + {SB_SMBUS_REGAD, ~(UINT8)(BIT0+BIT1+BIT2+BIT4), BIT0+BIT3}, // Initialize SATA to default values, SATA Enabled, + // Combined mode enabled, SATA as primary, power saving enable + {SB_SMBUS_REGAF, 0xE3, 6 << 2}, // Set SATA Interrupt to INTG# + {SB_SMBUS_REG68, BIT3, 0 }, // First disable all usb controllers and then enable then according to setup selection + {0xFF, 0xFF, 0xFF}, + + // IDE Device(Bus 0, Dev 20, Func 1) + {0x00, IDE_BUS_DEV_FUN, 0}, + {SB_IDE_REG62+1, ~(UINT8)BIT0, BIT5}, // Enabling IDE Explicit Pre-Fetch IDE PCI Config 0x62[8]=0 + // Allow MSI capability of IDE controller to be visible. IDE PCI Config 0x62[13]=1 + {0xFF, 0xFF, 0xFF}, + + // Azalia Device(Bus 0, Dev 20, Func 2) + {0x00, AZALIA_BUS_DEV_FUN, 0}, + {SB_AZ_REG4C, ~(UINT8)BIT0, BIT0}, + {0xFF, 0xFF, 0xFF}, + + // LPC Device(Bus 0, Dev 20, Func 3) + {0x00, LPC_BUS_DEV_FUN, 0}, + + {SB_LPC_REG40, ~(UINT8)BIT2, BIT2}, // Enabling LPC DMA Function 0x40[2] + {SB_LPC_REG78, ~(UINT8)BIT1, 00}, // Disables MSI capability + {0xFF, 0xFF, 0xFF}, + + // P2P Bridge(Bus 0, Dev 20, Func 4) + {0x00, SBP2P_BUS_DEV_FUN, 0}, + + {SB_P2P_REG64+1, 0xFF, BIT7+BIT6}, //Adjusting CLKRUN#, PCIB_PCI_Config 0x64[15]=01 + //Enabling arbiter fix, PCIB_PCI_Config 0x64[14]=01 + {SB_P2P_REG64+2, 0xFF, BIT4}, //Enabling One-Prefetch-Channel Mode, PCIB_PCI_config 0x64 [20] + + {SB_P2P_REG0D, 0x00, 0x40}, //Setting Latency Timers to 0x40, Enables the PCIB to retain ownership + {SB_P2P_REG1B, 0x00, 0x40}, // of the bus on the Primary side and on the Secondary side when GNT# is deasserted. + + {0xFF, 0xFF, 0xFF}, + + // SATA Device(Bus 0, Dev 17, Func 0) + {0x00, SATA_BUS_DEV_FUN, 0}, + {SB_SATA_REG44, 0xff, BIT0}, // Enables the SATA watchdog timer register prior to the SATA BIOS post + {SB_SATA_REG40+3, 0xff, BIT5}, // RPR setting: Disable the testing/enhancement mode SATA_PCI_config 0x40 [29] = 1 + {SB_SATA_REG48+2, 0xff, BIT5}, // RPR setting: Disable the testing/enhancement mode SATA_PCI_config 0x48 [24] = 1, [21] = 1 + {SB_SATA_REG48+3, 0xff, BIT0}, + {SB_SATA_REG44 + 2, 0, 0x10}, // Program watchdog timer with 16 retries before timer time-out. + {0xFF, 0xFF, 0xFF}, +}; + + +REG8MASK sbEarlyPostPmioInitTbl[]={ + // index andmask ormask + {SB_PMIO_REG55, ~(UINT8)(BIT3+BIT4+BIT5), BIT5+BIT3}, //BIT3(PcieNative)=1b, BIT4(Pcie_Wak_Mask)=0b, BIT5(Pcie_WAK_Sci)=1b + {SB_PMIO_REG01, 0xff, BIT1}, + {SB_PMIO_REG0E, 0xff, BIT2 + BIT3}, + {SB_PMIO_REG10, 0x3E, (BIT6+BIT5+BIT3+BIT1)}, // RTC_En_En + TMR_En_En + GLB_EN_EN and clear EOS_EN + PciExpWakeDisEn + {SB_PMIO_REG61, 0xFF, 0x40}, // USB Device Support to Wakeup System from S3/S4 state, USB PME & PCI Act from NB + {SB_PMIO_REG59, 0xFC, 0x00 }, // Clear the flash controller bits BIT1:0 + {SB_PMIO_REG01, 0xFF, 0x97 }, // Clear all the status + {SB_PMIO_REG05, 0xFF, 0xFF }, + {SB_PMIO_REG06, 0xFF, 0xFF }, + {SB_PMIO_REG07, 0xFF, 0xFF }, + {SB_PMIO_REG0F, 0xFF, 0x1F }, + {SB_PMIO_REG1D, 0xFF, 0xFF }, + {SB_PMIO_REG39, 0xFF, 0xFF }, + {SB_PMIO_REG7C, ~(UINT8)(BIT5+BIT3+BIT2), BIT3+BIT2}, //Turn on BLink LED + {SB_PMIO_REG67, 0xFF, 0x06}, // C State enable, must be set in order to exercise C state + {SB_PMIO_REG68, 0x38, 0x84}, + {SB_PMIO_REG8D, 0xFF, 0x01}, // Set PM_Reg_0x8D[0] to enable PmeTurnOff/PmeMsgAck handshake to fix PCIE LAN S3/S4 wake failure + {SB_PMIO_REG84, 0xFD, BIT3+BIT0}, + {SB_PMIO_REG53, 0xFF, BIT7+BIT6}, //ACPI System Clock setting, PMIO Reg 0x53[6]=1. Our reference clock + //is either 25 or 100Mhz and so the default acpi clock is actually + //running at 12.5Mhz and so the system time will run slow. We have + //generated another internal clock which runs at 14.318Mhz which is the + //correct frequency. We should set this bit to turn on this feature PMIO_REG53[6]=1 + //PCI Clock Period, PM_IO 0x53 [7] = 1. By setting this, PCI clock period + //increase to 30.8 ns. + {SB_PMIO_REG95, ~(UINT8)(BIT2+BIT1+BIT0), BIT2+BIT1}, //USB Advanced Sleep Control, Enables USB EHCI controller + //to sleep for 6 uframes in stead of the standard 10us to + //improve power saving. + {SB_PMIO_REGD7, 0xFF, BIT6+BIT1}, + +}; + + +// commonInitEarlyBoot - set /SMBUS/ACPI/IDE/LPC/PCIB. This settings should be done during S3 resume also +void commonInitEarlyBoot(AMDSBCFG* pConfig) { + UINT16 dwTempVar; + CPUID_DATA CpuId; + CPUID_DATA CpuId_Brand; + UINT8 dbValue; + UINT32 ddValue; + UINT8 Family, Model, Stepping; + + TRACE((DMSG_SB_TRACE, "CIMx - Entering commonInitEarlyBoot \n")); + CpuidRead (0x01, &CpuId); + CpuidRead (0x80000001, &CpuId_Brand); //BrandID + + //Early post initialization of pci config space + programPciByteTable( (REG8MASK*)FIXUP_PTR(&sbEarlyPostByteInitTable[0]), sizeof(sbEarlyPostByteInitTable)/sizeof(REG8MASK) ); + + // RPR 5.5 Clear PM_IO 0x65[4] UsbResetByPciRstEnable, Set this bit so that usb gets reset whenever there is PCIRST. + RWPMIO(SB_PMIO_REG65, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT4, BIT4); + + + #if 0 //KZ [083011]-It's used wrong BIOS SIZE for Coreboot. + //For being compatible with earlier revision, check whether ROM decoding is changed already outside CIMx before + //changing it. + ReadPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG68, AccWidthUint16 | S3_SAVE, &dwTempVar); + if ( (dwTempVar == 0x08) || (dwTempVar == 0x00)) + RWPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG68, AccWidthUint8 | S3_SAVE, 0, 0x0E);// Change the 1Mb below ROM decoding range to 0xE0000 to 0xFFFFF + #endif + + if (pConfig->AzaliaController == 1) + RWPMIO(SB_PMIO_REG59, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT3, 0); + else + RWPMIO(SB_PMIO_REG59, AccWidthUint8 | S3_SAVE, 0xFF, BIT3); + + //Disable or Enable PCI Clks based on input + RWPCI((SBP2P_BUS_DEV_FUN << 16) + SB_P2P_REG42, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT5+BIT4+BIT3+BIT2), ((pConfig->PciClks) & 0x0F) << 2 ); + RWPCI((SBP2P_BUS_DEV_FUN << 16) + SB_P2P_REG4A, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT1+BIT0), ((pConfig->PciClks) >> 4) | ((pConfig->PciClk5) << 1) ); + ReadPMIO(SB_PMIO_REG2C, AccWidthUint16, &dwTempVar); // Read Arbiter address, Arbiter address is in PMIO 2Ch + RWIO(dwTempVar, AccWidthUint8, 0, 0); // Write 0 to enable the arbiter + + abLinkInitBeforePciEnum(pConfig); // Set ABCFG registers + // Set LDTSTP# duration to 10us for HydraD CPU model 8, 9 or A; or when HT link is 200MHz; or Family15 Orochi CPU C32/G34 package + ddValue = CpuId.REG_EAX & 0x00FF00F0; + dbValue = 1; + + if((CpuId.REG_EAX & 0x00F00F00) == 0x00600F00) { + if(((CpuId_Brand.REG_EBX & 0xF0000000) == 0x30000000) || ((CpuId_Brand.REG_EBX & 0xF0000000) == 0x50000000)) { + //Orochi processor G34/C32, set to 10us + dbValue = 10; + } + else { + // Orochi processor AM3, set to 5us + dbValue = 5; + } + } + + if ((pConfig->AnyHT200MhzLink) || (ddValue == 0x100080) || (ddValue == 0x100090) || (ddValue == 0x1000A0)) { + //any kind of CPU run HT at 200Mhz , or HydraD CPU model 8, 9 or A, set to 10us + dbValue = 10; + } + + + RWPMIO(SB_PMIO_REG8B, AccWidthUint8 | S3_SAVE, 0x00, dbValue); + + // Enable/Disable watchdog timer + RWPMIO(SB_PMIO_REG69, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT0, (UINT8)(!pConfig->WatchDogTimerEnable)); + + // Per SB700/SP5100 RPR 2.5 + // + // Enable C1e stutter timer for any system with chip revision >= A14 + // Set SMBUS:0x5c[22:16] = 16 -- Set amount of idle time to 16ms + // + + if (getRevisionID() >= SB700_A14) { + dwTempVar = 0x0010; + + // Set PMIO:0xcb[5] = 1 -- AutoStutterTimerEn, set 1 to enable + // Set PMIO:0xcb[6] = 1 -- AutoStutterTimeSel, 1=1ms timer tick increment; 0=2us increment + RWPMIO(SB_PMIO_REGCB, AccWidthUint8 | S3_SAVE, 0xff, BIT6 + BIT5); + + Family = (UINT8)((CpuId.REG_EAX & 0x00ff0000)>> 16); + Model = (UINT8)((CpuId.REG_EAX & 0x000000f0)>> 4); + Stepping = (UINT8) (CpuId.REG_EAX & 0x0000000f); + + // For Server system (SP5100) with CPU type = Family 10h with LS2 mode enabled: + // Model=6 && Stepping=2 || Model=(4I5|6) && Stepping >=3 || Model=(8|9) && Stepping >= 1 || Model Ah + // Set SMBUS:0x5c[22:16] = 20 -- Set amount of idle time to 20ms + if (IsLs2Mode() && (Family == 0x10)) { + switch( Model ){ + case 0x4: + case 0x5: + if( Stepping >= 3 ) dwTempVar = 0x14; + break; + case 0x6: + if( Stepping >= 2 ) dwTempVar = 0x14; + break; + case 0x8: + if( Stepping >= 1 ) dwTempVar = 0x14; + break; + case 0x9: + if( Stepping >= 1 ) dwTempVar = 0x14; + break; + case 0xA: + dwTempVar = 0x14; + break; + } + } + // Set SMBUS:0x5c[7] = 1 -- CheckC3, set 1 to check for C3 state + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG5C, AccWidthUint32 | S3_SAVE, ~(0x7F << 16), (dwTempVar << 16) + BIT7); + } + + //Message-Triggered C1E is not supported in Family 10h G34r1 HY-D0 (0x00100F90) and Family 10h C32 HY-D0 (0x00100F80) processor. + ddValue = CpuId.REG_EAX; + if ((getRevisionID() == SB700_A15) && (pConfig->MTC1e == CIMX_OPTION_ENABLED) && (ddValue != 0x00100F90) && (ddValue != 0x00100F80)) { + // + // MTC1e: For A15 (server only) - The settings here borrow the existing legacy ACPI BM_STS and BM_RLD bits as a + // mechanism to break out from C1e under a non-OS controlled C3 state. Under this scheme, the logic will automatically + // clear the BM_STS bit whenever it enters C1e state. Whenever BM_REQ#/IDLE_EXIT# is detected, it will cause the + // BM_STS bit to be set and therefore causing the C state logic to exit. + // + // Set BMReqEnable (SMBUS:0x64[5]=1) to enable the pin as BM_REQ#/IDLE_EXIT# to the C state logic + // Set CheckOwnReq (SMBUS:0x64[4]=0) to force IDLE_EXIT# to set BM_STS and wake from C3 + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG64, AccWidthUint8 | S3_SAVE, 0xEF, BIT5); + + // Set PCI_Active_enable (PMIO:0x61[2]=1), the secondary enable bit for SB to monitor BM_REQ#/IDLE_EXIT# + RWPMIO(SB_PMIO_REG61, AccWidthUint8 | S3_SAVE, 0xff, BIT2); + + // Set auto_bm_rld (PMIO:0x9a[4]=1) so that assertion on BM_REQ#/IDLE_EXIT# pin will cause C state logic to break out from C1e + // Set auto_clr_bm_sts (PMIO:0x9a[5]=1) will cause the C state logic to automatically clear the BM_STS bit whenever it sees a C1e entry + RWPMIO(SB_PMIO_REG9A, AccWidthUint8 | S3_SAVE, 0xff, BIT5 + BIT4); + + + // MTC1e: The logic basically counts the number of HALT_ENTER messages. When it has received the number of HALT_ENTER + // messages equal to NumOfCpu (PMIO:0xc9[3:0]), it will generate an internal C1e command to the C state logic. + // The count increments when it sees HALT_ENTER message after it has generated the C1e command, and it treats the + // HALT_EXIT message as a break event. + // + // Set ServerCEn + RWPMIO(SB_PMIO_REGBB, AccWidthUint8 | S3_SAVE, 0xFF, BIT7); + + // Enable counting HALT + // PMIO:0xc9[4] = CountHaltMsgEn + // PMIO:0xc9[3:0] = NumOfCpu, set to 1 since CPU logic will coordinate among cores and only generate one HALT message + RWPMIO(SB_PMIO_REGC9, AccWidthUint8 | S3_SAVE, 0xE0, BIT4 + 1); + } + + c3PopupSetting(pConfig); + + TRACE((DMSG_SB_TRACE, "CIMx - Exiting commonInitEarlyBoot \n")); +} + + +void commonInitEarlyPost(AMDSBCFG* pConfig){ + //early post initialization of pmio space + programPmioByteTable( (REG8MASK *)FIXUP_PTR(&sbEarlyPostPmioInitTbl[0]), (sizeof(sbEarlyPostPmioInitTbl)/sizeof(REG8MASK)) ); + CallBackToOEM(PULL_UP_PULL_DOWN_SETTINGS, NULL, pConfig); +} + + +// AB-Link Configuration Table +ABTBLENTRY abTblEntry600[]={ + // Enabling Downstream Posted Transactions to Pass Non-Posted Transactions for the K8 Platform ABCFG 0x10090[8] = 1 + // ABCFG 0x10090 [16] = 1, ensures the SMI# message to be sent before the IO command is completed. The ordering of + // SMI# and IO is important for the IO trap to work properly. + {ABCFG,SB_AB_REG10090 ,BIT16+BIT8 ,BIT16+BIT8 }, + // Enabling UpStream DMA Access AXCFG: 0x04[2]=1 + {AXCFG,SB_AB_REG04 ,BIT2 ,BIT2 }, + // Setting B-Link Prefetch Mode ABCFG 0x80 [17] = 1 ABCFG 0x80 [18] = 1 + {ABCFG,SB_AB_REG80 ,BIT17+BIT18 ,BIT17+BIT18 }, + // Disable B-Link client's credit variable in downstream arbitration equation (for All Revisions) + // ABCFG 0x9C[0] = 1 Disable credit variable in downstream arbitration equation + // Enabling Additional Address Bits Checking in Downstream Register Programming + // ABCFG 0x9C[1] = 1 + {ABCFG,SB_AB_REG9C ,BIT8+BIT1+BIT0 ,BIT8+BIT1+BIT0 }, + // Enabling IDE/PCIB Prefetch for Performance Enhancement + // IDE prefetch ABCFG 0x10060 [17] = 1 ABCFG 0x10064 [17] = 1 + // PCIB prefetch ABCFG 0x10060 [20] = 1 ABCFG 0x10064 [20] = 1 + {ABCFG,SB_AB_REG10060 ,BIT17+BIT20 ,BIT17+BIT20 }, // IDE+PCIB prefetch enable + {ABCFG,SB_AB_REG10064 ,BIT17+BIT20 ,BIT17+BIT20 }, // IDE+PCIB prefetch enable + // Enabling Detection of Upstream Interrupts ABCFG 0x94 [20] = 1 + // ABCFG 0x94 [19:0] = cpu interrupt delivery address [39:20] + {ABCFG,SB_AB_REG94 ,BIT20 ,BIT20+0x00FEE }, + // Programming cycle delay for AB and BIF clock gating + // Enabling AB and BIF Clock Gating + // Enabling AB Int_Arbiter Enhancement + // Enabling Requester ID + {ABCFG,SB_AB_REG10054, 0x00FFFFFF , 0x010407FF }, + {ABCFG,SB_AB_REG98 , 0xFFFF00FF , 0x00014700 }, // Enable the requestor ID for upstream traffic ABCFG 0x98[16]=1 +// {ABCFG,SB_AB_REG54 , 0x00FF0000 , 0x01040000 }, + {ABCFG,SB_AB_REG54 , 0x00FF0000 , 0x00040000 }, + + {ABCFG,0,0,-1}, // This dummy entry is to clear ab index + {-1, -1, -1, -1 }, +}; + + +// AB-Link Configuration Table +ABTBLENTRY abTblForA15[]={ + + //SMI Reordering fix + {ABCFG, SB_AB_REG90 ,BIT21 , BIT21 }, + {ABCFG, SB_AB_REG9C ,BIT15+BIT9+BIT5 ,BIT15+BIT9+BIT5}, + + //Posted pass NP Downstream feature + {AX_INDXC, SB_AB_REG02, BIT9 ,BIT9 }, + {ABCFG, SB_AB_REG9C, BIT14+BIT13+BIT12+BIT11+BIT10+BIT7+BIT6 , BIT14+BIT13+BIT12+BIT11+BIT10+BIT7+BIT6}, + {ABCFG, SB_AB_REG1009C, BIT5+BIT4 , BIT5+BIT4}, + + //Posted pass NP upstream feature + {ABCFG, SB_AB_REG58, BIT15+BIT14+BIT13+BIT12+BIT11, BIT15+BIT14+BIT13+BIT11}, + + //64 bit Non-posted memory write support + {AX_INDXC, SB_AB_REG02, BIT10 ,BIT10 }, + + {ABCFG, SB_AB_REG10090, BIT12+BIT11+BIT10+BIT9 , BIT12+BIT11+BIT10+BIT9}, + + {ABCFG,0,0,-1}, // This dummy entry is to clear ab index + {-1, -1, -1, -1 }, +}; + + +// abLinkInitBeforePciEnum - Set ABCFG registers +void abLinkInitBeforePciEnum(AMDSBCFG* pConfig){ + ABTBLENTRY *pAbTblPtr; + + // disable PMIO decoding when AB is set + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG64, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT2, 0); + + pAbTblPtr = (ABTBLENTRY *)FIXUP_PTR(&abTblEntry600[0]); + abcfgTbl(pAbTblPtr); + + if (getRevisionID() > SB700_A11){ + //Enable OHCI Prefetch + writeAlink( (SB_AB_REG80 | (ABCFG << 30)), (readAlink((SB_AB_REG80 | (ABCFG << 30)))) | BIT0); + //Register bit to maintain correct ordering of SMI and IO write completion + writeAlink( (SB_AB_REG8C | (ABCFG << 30)), (readAlink((SB_AB_REG8C | (ABCFG << 30)))) | BIT8); + } + + if (getRevisionID() >= SB700_A14){ + //Enable fix for TT SB01345 + writeAlink( (SB_AB_REG90 | (ABCFG << 30)), (readAlink((SB_AB_REG90 | (ABCFG << 30)))) | BIT17); + //Disable IO Write and SMI ordering enhancement + writeAlink( (SB_AB_REG9C | (ABCFG << 30)), (readAlink((SB_AB_REG9C | (ABCFG << 30)))) & (0xFFFFFEFF)); + } + + if (getRevisionID() >= SB700_A15) { + pAbTblPtr = (ABTBLENTRY *)FIXUP_PTR(&abTblForA15[0]); + abcfgTbl(pAbTblPtr); + } + + + // enable pmio decoding after ab is configured + // or BYTE PTR es:[ebp+SMBUS_BUS_DEV_FUN shl 12 + SB_SMBUS_REG64], BIT2 + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG64, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT2, BIT2); +} + + +void abcfgTbl(ABTBLENTRY* pABTbl){ + UINT32 ddValue; + + while ((pABTbl->regType) != 0xFF){ + TRACE((DMSG_SB_TRACE, "RegType: %X, RegNumber:%X, AndMask=%X, OrMask=%X \n",pABTbl->regType , pABTbl->regIndex, pABTbl->regMask, pABTbl->regData)); + if (pABTbl->regType > AX_INDXP){ + ddValue = pABTbl->regIndex | (pABTbl->regType << 30); + writeAlink(ddValue, ((readAlink(ddValue)) & (0xFFFFFFFF^(pABTbl->regMask)))|pABTbl->regData); + } + else{ + ddValue = 0x30 | (pABTbl->regType << 30); + writeAlink(ddValue, pABTbl->regIndex); + ddValue = 0x34 | (pABTbl->regType << 30); + writeAlink(ddValue, ((readAlink(ddValue)) & (0xFFFFFFFF^(pABTbl->regMask)))|pABTbl->regData); + } + ++pABTbl; + } + + //Clear ALink Access Index + ddValue = 0; + WriteIO(ALINK_ACCESS_INDEX, AccWidthUint32 | S3_SAVE, &ddValue); + TRACE((DMSG_SB_TRACE, "Exiting abcfgTbl\n")); +} + + +// programSubSystemIDs - Config Subsystem ID for all SB devices. +void programSubSystemIDs(AMDSBCFG* pConfig, BUILDPARAM *pStaticOptions){ + UINT32 ddTempVar; + UINT16 dwDeviceId; + + RWPCI((USB1_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->Ohci0Ssid); + RWPCI((USB1_OHCI1_BUS_DEV_FUN << 16) + SB_OHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->Ohci1Ssid); + RWPCI((USB2_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->Ohci2Ssid); + RWPCI((USB2_OHCI1_BUS_DEV_FUN << 16) + SB_OHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->Ohci3Ssid); + RWPCI((USB3_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->Ohci4Ssid); + + RWPCI((USB1_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->Ehci0Ssid); + RWPCI((USB2_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->Ehci1Ssid); + + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->SmbusSsid); + RWPCI((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->IdeSsid); + RWPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->LpcSsid); + RWPCI((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->AzaliaSsid); + + ddTempVar = pStaticOptions->SataIDESsid; + if ( ((pConfig->SataClass) == AHCI_MODE) || ((pConfig->SataClass)== IDE_TO_AHCI_MODE) ) + ddTempVar = pStaticOptions->SataAHCISsid; + + ReadPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG02), AccWidthUint16 | S3_SAVE, &dwDeviceId); + if ((pConfig->SataClass) == RAID_MODE){ + ddTempVar = pStaticOptions->SataRAIDSsid; + if (dwDeviceId==SB750_SATA_DEFAULT_DEVICE_ID) + ddTempVar = pStaticOptions->SataRAID5Ssid; + } + + if ( ((pConfig->SataClass) == AMD_AHCI_MODE) || ((pConfig->SataClass) == IDE_TO_AMD_AHCI_MODE) ) { + ddTempVar = pStaticOptions->SataAHCISsid; + } + RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG2C, AccWidthUint32 | S3_SAVE, 0x00, ddTempVar); +} + +void commonInitLateBoot(AMDSBCFG* pConfig){ + UINT8 dbValue; + UINT32 ddVar; + + // We need to do the following setting in late post also because some bios core pci enumeration changes these values + // programmed during early post. + // RPR 4.5 Master Latency Timer + // Master Latency Timer PCIB_PCI_config 0x0D/0x1B = 0x40 + // Enables the PCIB to retain ownership of the bus on the + // Primary side and on the Secondary side when GNT# is deasserted. + //mov BYTE PTR es:[ebp+SBP2P_BUS_DEV_FUN shl 12 + SB_P2P_REG0D], 40h + //mov BYTE PTR es:[ebp+SBP2P_BUS_DEV_FUN shl 12 + SB_P2P_REG1B], 40h + dbValue = 0x40; + WritePCI((SBP2P_BUS_DEV_FUN << 16) + SB_P2P_REG0D, AccWidthUint8, &dbValue); + WritePCI((SBP2P_BUS_DEV_FUN << 16) + SB_P2P_REG1B, AccWidthUint8, &dbValue); + + //SB P2P AutoClock control settings. + ddVar = (pConfig->PcibAutoClkCtrlLow) | (pConfig->PcibAutoClkCtrlLow); + WritePCI((SBP2P_BUS_DEV_FUN << 16) + SB_P2P_REG4C, AccWidthUint32, &ddVar); + ddVar = (pConfig->PcibClkStopOverride); + RWPCI((SBP2P_BUS_DEV_FUN << 16) + SB_P2P_REG50, AccWidthUint16, 0x3F, (UINT16) (ddVar << 6)); + + if (pConfig->MobilePowerSavings){ + //If RTC clock is not driven to any chip, it should be shut-off. If system uses external RTC, then SB needs to + //drive out RTC clk to external RTC chip. If system uses internal RTC, then this clk can be shut off. + RWPMIO(SB_PMIO_REG68, AccWidthUint8, ~(UINT32)BIT4, (pConfig->ExternalRTCClock)<<4); + if (!getClockMode()){ + if (!(pConfig->UsbIntClock) ){ + //If the external clock is used, the second PLL should be shut down + RWPMIO(SB_PMIO_REGD0, AccWidthUint8, 0xFF, BIT0); + // If external clock mode is used, the 25Mhz oscillator buffer can be turned-off by setting PMIO 0xD4[7]=1 + RWPMIO(SB_PMIO_REGD4, AccWidthUint8, 0xFF, BIT7); + //Disable unused clocks + RWPMIO(SB_PMIO_REGCA, AccWidthUint8, 0xFF, 0x7E); + } + } + writeAlink(0x30, SB_AB_REG40); + writeAlink(0x34, ((readAlink(0x34)) & 0xFFFF0000) | 0x008A); + + } + else{ + //Don't shutoff RTC clock + RWPMIO(SB_PMIO_REG68, AccWidthUint8, ~(UINT32)BIT4, 0); + //Dont disable second PLL + RWPMIO(SB_PMIO_REGD0, AccWidthUint8, ~(UINT32)BIT0, 0); + //Enable the 25Mhz oscillator + RWPMIO(SB_PMIO_REGD4, AccWidthUint8, ~(UINT32)BIT7, 0); + RWPMIO(SB_PMIO_REGCA, AccWidthUint8, 0xFF, 0x00); + } +} + + +void +hpetInit (AMDSBCFG* pConfig, BUILDPARAM *pStaticOptions) +{ + DESCRIPTION_HEADER* pHpetTable; + + if (pConfig->HpetTimer == 1) { + UINT8 dbTemp; + + RWPMIO(SB_PMIO_REG9A, AccWidthUint8, 0xFF, BIT7); + // Program the HPET BAR address + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGB4, AccWidthUint32 | S3_SAVE, 0, pStaticOptions->HpetBase); + + // Enable HPET MMIO decoding: SMBUS:0x43[4] = 1 + // Enable HPET MSI support only when HpetMsiDis == 0 + dbTemp = (pConfig->HpetMsiDis)? BIT4 : BIT7 + BIT6 + BIT5 + BIT4; + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG43, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT3, dbTemp); + // Program HPET default clock period + if (getRevisionID() >= SB700_A13) { + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG34, AccWidthUint32 | S3_SAVE, 0x00, 0x429B17E); + } + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG43, AccWidthUint8 | S3_SAVE, 0xFF, BIT3); + // Enable High Precision Event Timer (also called Multimedia Timer) interrupt + RWPCI((SMBUS_BUS_DEV_FUN << 16) + (SB_SMBUS_REG64+1), AccWidthUint8 | S3_SAVE, ~(UINT32)BIT2, BIT2); + } + else { + if (!(pConfig->S3Resume)) { +// pHpetTable = (DESCRIPTION_HEADER*)ACPI_LocateTable('TEPH'); + pHpetTable = (DESCRIPTION_HEADER*)ACPI_LocateTable(Int32FromChar ('T', 'E', 'P', 'H')); + if (pHpetTable != NULL) { +// pHpetTable->Signature = 'HPET'; + pHpetTable->Signature = Int32FromChar ('T', 'E', 'P', 'H'); + } + } + } +} + + +void c3PopupSetting(AMDSBCFG* pConfig){ + UINT8 dbTemp; + CPUID_DATA CpuId; + + CpuidRead (0x01, &CpuId); + //RPR 2.3 C-State and VID/FID Change + dbTemp = GetNumberOfCpuCores(); + if (dbTemp > 1){ + //PM_IO 0x9A[5]=1, For system with dual core CPU, set this bit to 1 to automatically clear BM_STS when the C3 state is being initiated. + //PM_IO 0x9A[4]=1, For system with dual core CPU, set this bit to 1 and BM_STS will cause C3 to wakeup regardless of BM_RLD + //PM_IO 0x9A[2]=1, Enable pop-up for C3. For internal bus mastering or BmReq# from the NB, the SB will de-assert + //LDTSTP# (pop-up) to allow DMA traffic, then assert LDTSTP# again after some idle time. + RWPMIO(SB_PMIO_REG9A, AccWidthUint8, 0xFF, BIT5+BIT4+BIT2); + } + + //SB700 needs to changed for RD790 support + //PM_IO 0x8F [4] = 0 for system with RS690 + //Note: RS690 north bridge has AllowLdtStop built for both display and PCIE traffic to wake up the HT link. + //BmReq# needs to be ignored otherwise may cause LDTSTP# not to toggle. + //PM_IO 0x8F[5]=1, Ignore BM_STS_SET message from NB + RWPMIO(SB_PMIO_REG8F, AccWidthUint8, ~(UINT32)(BIT5+BIT4), BIT5); + + //LdtStartTime = 10h for minimum LDTSTP# de-assertion duration of 16us in StutterMode. This is to guarantee that + //the HT link has been safely reconnected before it can be disconnected again. If C3 pop-up is enabled, the 16us also + //serves as the minimum idle time before LDTSTP# can be asserted again. This allows DMA to finish before the HT + //link is disconnected. + //Increase LDTSTOP Deassertion time for SP5100 to 20us, SB700 remains the same + dbTemp = (IsServer())? 0x14 : 0x10; + RWPMIO(SB_PMIO_REG88, AccWidthUint8, 0x00, dbTemp); + + //This setting provides 16us delay before the assertion of LDTSTOP# when C3 is entered. The + //delay will allow USB DMA to go on in a continous manner + RWPMIO(SB_PMIO_REG89, AccWidthUint8, 0x00, 0x10); + + //Set this bit to allow pop-up request being latched during the minimum LDTSTP# assertion time + RWPMIO(SB_PMIO_REG52, AccWidthUint8, 0xFF, BIT7); + +} + diff --git a/src/vendorcode/amd/cimx/sb700/SBCMNLIB.c b/src/vendorcode/amd/cimx/sb700/SBCMNLIB.c new file mode 100644 index 0000000..130dbc4 --- /dev/null +++ b/src/vendorcode/amd/cimx/sb700/SBCMNLIB.c @@ -0,0 +1,108 @@ +/***************************************************************************** + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + ***************************************************************************/ + + +#include "Platform.h" + +UINT8 isEcPresent(){ + UINT8 dbFlag; + UINT16 dwVar0; + + //Read the EC configuration register base address from LPCCfg_A4[15:1] + //Write 0x5A to the EC config index register to unlock the access + //Write 0x20 to the EC config index register to select the device ID register + //Read the value of device ID register from the EC config data register + //If the value read is 0xB7, then EC is enabled. + //Write 0xA5 to re-lock the EC config index register if EC is enabled. + + ReadPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4, AccWidthUint16 | S3_SAVE, &dwVar0); + dwVar0 &= 0xFFFE; + RWIO(dwVar0, AccWidthUint8, 0, 0x5A); + RWIO(dwVar0, AccWidthUint8, 0, 0x20); + ReadIO(dwVar0+1, AccWidthUint8, &dbFlag); + RWIO(dwVar0, AccWidthUint8, 0, 0xA5); + + return ( dbFlag == 0xB7); +} + +void +getSbInformation ( +SB_INFORMATION *sbInfo){ + UINT16 dwDevId; + UINT8 dbRev; + + ReadPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG02, AccWidthUint16 | S3_SAVE, &dwDevId); + ReadPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG08, AccWidthUint8 | S3_SAVE, &dbRev); + sbInfo->sbModelMask = SB_MODEL_UNKNOWN; + if ( (dwDevId == SB7XX_DEVICE_ID) && (dbRev <= SB_Rev_Sb7xx_A14) ){ + sbInfo->sbModelMask |= SB_MODEL_SB700; + sbInfo->sbModelMask |= SB_MODEL_SR5690; + sbInfo->sbRev = dbRev; + ReadPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG9C, AccWidthUint8 | S3_SAVE, &dbRev); + if (dbRev & 01) + sbInfo->sbModelMask |= SB_MODEL_SB750; + if (isEcPresent()) + sbInfo->sbModelMask |= SB_MODEL_SB710; + return; + } +} + + +SB_CAPABILITY_SETTING +getSbCapability ( +SB_CAPABILITY_ITEM sbCapabilityItem +) +{ + SB_CAPABILITY_SETTING sbCapSetting=SB_UNKNOWN; + UINT32 ddTemp0; + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG43, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT3, 00); + ReadPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG10, AccWidthUint32, &ddTemp0); + + if (sbCapabilityItem < Sb_Unknown_Capability) + sbCapSetting = ((ddTemp0 >> (sbCapabilityItem << 1) ) & 0x03); + + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG43, AccWidthUint8 | S3_SAVE, 0xFF, BIT3); + return sbCapSetting; +} + + +void +setSbCapability ( +SB_CAPABILITY_ITEM sbCapabilityItem, SB_CAPABILITY_SETTING sbCapSetting +) +{ + UINT32 ddTemp0; + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG43, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT3, 00); + ReadPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG10, AccWidthUint32, &ddTemp0); + if ( (sbCapabilityItem < Sb_Unknown_Capability) & (sbCapSetting < Sb_Cap_Setting_Unknown) ) + ddTemp0 = (ddTemp0 & ~(0x03 << (sbCapabilityItem << 1))) | ( (sbCapSetting & 0x03) << (sbCapabilityItem << 1)); + WritePCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG10, AccWidthUint32, &ddTemp0); + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG43, AccWidthUint8 | S3_SAVE, 0xFF, BIT3); +} diff --git a/src/vendorcode/amd/cimx/sb700/SBCMNLIB.h b/src/vendorcode/amd/cimx/sb700/SBCMNLIB.h new file mode 100644 index 0000000..e737bc9 --- /dev/null +++ b/src/vendorcode/amd/cimx/sb700/SBCMNLIB.h @@ -0,0 +1,89 @@ +/*;******************************************************************************** +; +; Copyright (C) 2012 Advanced Micro Devices, Inc. +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; * Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; * Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution. +; * Neither the name of Advanced Micro Devices, Inc. nor the names of +; its contributors may be used to endorse or promote products derived +; from this software without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;*********************************************************************************/ + +#ifndef _AMD_SBLIB_H_ +#define _AMD_SBLIB_H_ + +//SB7xx Family +#define SB7xx_DEVICE_ID 0x4385 +#define SB700 0x00 +#define SB750 0x01 +#define SB710 0x02 + +//SB800 Family +#define SB800 0x10 + +#define SB_UNKNOWN 0xFF + +//SB700 Revision IDs +#define SB700_A11 0x39 +#define SB700_A12 0x3A +#define SB700_A13 0x3B +#define SB700_A14 0x3C + +#define SB_Rev_Sb7xx_A11 0x39 +#define SB_Rev_Sb7xx_A12 0x3A +#define SB_Rev_Sb7xx_A13 0x3B +#define SB_Rev_Sb7xx_A14 0x3C + + +typedef enum { + Sb_Raid0_1_Capability, /// + Sb_Raid5_Capability, /// + Sb_Ahci_Capability, /// + Sb_Unknown_Capability +} SB_CAPABILITY_ITEM; + + +typedef enum { + Sb_Cap_Setting_Auto, + Sb_Cap_Setting_Enabled, + Sb_Cap_Setting_Disabled, + Sb_Cap_Setting_Unknown +} SB_CAPABILITY_SETTING; + + +#define SB_MODEL_SB700 BIT0 +#define SB_MODEL_SB750 BIT1 +#define SB_MODEL_SB710 BIT2 +#define SB_MODEL_SR5690 BIT3 +#define SB_MODEL_UNKNOWN BIT31 + +typedef struct +{ + UINT32 sbModelMask; + UINT8 sbRev; +}SB_INFORMATION; + + +void getSbInformation (SB_INFORMATION *sbInfo); +SB_CAPABILITY_SETTING getSbCapability (SB_CAPABILITY_ITEM sbCapabilityItem); +void setSbCapability (SB_CAPABILITY_ITEM sbCapabilityItem, SB_CAPABILITY_SETTING sbCapSetting); + +#endif //#ifndef _AMD_SBLIB_H_ diff --git a/src/vendorcode/amd/cimx/sb700/SBDEF.h b/src/vendorcode/amd/cimx/sb700/SBDEF.h new file mode 100644 index 0000000..01fc1b5 --- /dev/null +++ b/src/vendorcode/amd/cimx/sb700/SBDEF.h @@ -0,0 +1,166 @@ +/*;******************************************************************************** +; +; Copyright (C) 2012 Advanced Micro Devices, Inc. +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; * Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; * Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution. +; * Neither the name of Advanced Micro Devices, Inc. nor the names of +; its contributors may be used to endorse or promote products derived +; from this software without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;*********************************************************************************/ + +#ifndef _AMD_SBDEF_H_ +#define _AMD_SBDEF_H_ + +//AMD Library Routines + +UINT64 +MsrRead ( + IN UINT32 MsrAddress + ); + +VOID +MsrWrite ( + IN UINT32 MsrAddress, + IN UINT64 Value + ); + +void ReadIO(UINT16 Address, UINT8 OpFlag, void *Value); +void WriteIO(UINT16 Address, UINT8 OpFlag, void *Value); +void ReadPCI(UINT32 Address, UINT8 OpFlag, void *Value); +void WritePCI(UINT32 Address,UINT8 OpFlag, void *Value); +void RWPCI(UINT32 Address,UINT8 OpFlag,UINT32 Mask,UINT32 Data); +void ReadIndexPCI32(UINT32 PciAddress,UINT32 IndexAddress,void* Value); +void WriteIndexPCI32(UINT32 PciAddress,UINT32 IndexAddress,UINT8 OpFlag,void* Value); +void RWIndexPCI32(UINT32 PciAddress,UINT32 IndexAddress,UINT8 OpFlag,UINT32 Mask,UINT32 Data); +void RWIO (UINT16 Address, UINT8 OpFlag, UINT32 Mask, UINT32 Data); +void ReadMEM(UINT32 Address,UINT8 OpFlag, void* Value); +void WriteMEM(UINT32 Address,UINT8 OpFlag, void* Value); +void RWMEM(UINT32 Address,UINT8 OpFlag,UINT32 Mask,UINT32 Data); +UINT32 IsFamily10(void); +UINT64 ReadMSR(UINT32 Address); +void WriteMSR(UINT32 Address,UINT64 Value); +void RWMSR(UINT32 Address, UINT64 Mask, UINT64 Value); +void* LocateImage(UINT32 Signature); +void* CheckImage( UINT32 Signature, void* ImagePtr); +void Stall(UINT32 uSec); +void Reset(void); +CIM_STATUS RWSMBUSBlock(UINT8 Controller, UINT8 Address, UINT8 Offset, UINT8 BufferSize, UINT8* BufferPrt); +void InitSerialOut(void); +void ReadPMIO(UINT8 Address, UINT8 OpFlag, void* Value); +void WritePMIO(UINT8 Address, UINT8 OpFlag, void* Value); +void RWPMIO(UINT8 Address, UINT8 OpFlag, UINT32 AndMask, UINT32 OrMask); +void ReadPMIO2(UINT8 Address, UINT8 OpFlag, void* Value); +void WritePMIO2(UINT8 Address, UINT8 OpFlag, void* Value); +void RWPMIO2(UINT8 Address, UINT8 OpFlag, UINT32 AndMask, UINT32 OrMask); +void outPort80(UINT32 pcode); +UINT8 GetNumberOfCpuCores(void); +UINT8 ReadNumberOfCpuCores(void); +UINT8 GetByteSum(void* pData, UINT32 Length); +UINT32 readAlink(UINT32 Index); +void writeAlink(UINT32 Index,UINT32 Data); + +//---------------------------------------------------------------------------------------------- +//---------------------------------------------------------------------------------------------- +void azaliaInitAfterPciEnum (AMDSBCFG* pConfig); + +void SendBytePort(UINT8 Data); +void SendStringPort(char* pstr); +void ItoA(UINT32 Value,int Radix,char* pstr); +AMDSBCFG* getConfigPointer(void); +void saveConfigPointer(AMDSBCFG* pConfig); + + +UINT32 GetFixUp(void); + +void sataInitAfterPciEnum(AMDSBCFG* pConfig); +void sataInitBeforePciEnum(AMDSBCFG* pConfig); +void sataInitLatePost(AMDSBCFG* pConfig); +void sataDriveDetection(AMDSBCFG* pConfig, UINT32 ddBar5); +void sataPhyWorkaround(AMDSBCFG* pConfig, UINT32 ddBar5); +void forceOOB(UINT32 ddBar5); +void shutdownUnconnectedSataPortClock(AMDSBCFG* pConfig, UINT32 ddBar5); +void restrictSataCapabilities(AMDSBCFG* pConfig); + + +void commonInitEarlyBoot(AMDSBCFG* pConfig); +void commonInitEarlyPost(AMDSBCFG* pConfig); +void setRevisionID(void); +UINT8 getRevisionID(void); +UINT8 IsServer (void); +UINT8 IsLs2Mode (void); +void abLinkInitBeforePciEnum(AMDSBCFG* pConfig); +void abcfgTbl(ABTBLENTRY* pABTbl); +void programSubSystemIDs(AMDSBCFG* pConfig, BUILDPARAM *pStaticOptions); +void commonInitLateBoot(AMDSBCFG* pConfig); +void hpetInit(AMDSBCFG* pConfig, BUILDPARAM *pStaticOptions); +void c3PopupSetting(AMDSBCFG* pConfig); + +void sbBeforePciInit (AMDSBCFG* pConfig); +void sbAfterPciInit(AMDSBCFG* pConfig); +void sbLatePost(AMDSBCFG* pConfig); +void sbBeforePciRestoreInit(AMDSBCFG* pConfig); +void sbAfterPciRestoreInit(AMDSBCFG* pConfig); +void sbSmmAcpiOn(AMDSBCFG* pConfig); +UINT32 GetPciebase(void); +UINT32 CallBackToOEM(UINT32 Func, UINTN Data,AMDSBCFG* pConfig); +void sbSmmService(AMDSBCFG* pConfig); +void softwareSMIservice(void); + +void sbPowerOnInit (AMDSBCFG *pConfig); +void programPciByteTable(REG8MASK* pPciByteTable, UINT16 dwTableSize); +void programPmioByteTable(REG8MASK* pPmioByteTable, UINT16 dwTableSize); +UINT8 getClockMode(void); +UINT16 readStrapStatus (void); + +void usbInitBeforePciEnum(AMDSBCFG* pConfig); +void usbInitAfterPciInit(AMDSBCFG* pConfig); +void usbInitMidPost(AMDSBCFG* pConfig); +void programOhciMmioForEmulation(void); + +void fcInitBeforePciEnum(AMDSBCFG* pConfig); + +unsigned char ReadIo8 (IN unsigned short Address); +unsigned short ReadIo16 (IN unsigned short Address); +unsigned int ReadIo32 (IN unsigned short Address); +void WriteIo8 (IN unsigned short Address, IN unsigned char Data); +void WriteIo16 (IN unsigned short Address, IN unsigned short Data); +void WriteIo32 (IN unsigned short Address, IN unsigned int Data); +unsigned long long ReadTSC (void); +void CpuidRead (IN unsigned int Func, IN OUT CPUID_DATA* Data); + +#ifndef NO_EC_SUPPORT +void EnterEcConfig(void); +void ExitEcConfig(void); +void ReadEC8(UINT8 Address, UINT8* Value); +void WriteEC8(UINT8 Address, UINT8* Value); +void RWEC8(UINT8 Address, UINT8 AndMask, UINT8 OrMask); +void ecPowerOnInit(BUILDPARAM *pBuildOptPtr, AMDSBCFG *pConfig); +void ecInitBeforePciEnum(AMDSBCFG* pConfig); +void ecInitLatePost(AMDSBCFG* pConfig); +#endif +UINT8 isEcPresent(void); + +void DispatcherEntry(void *pConfig); +AGESA_STATUS AmdSbDispatcher(void *pConfig); +void AMDFamily15CpuLdtStopReq(void); + +#endif //#ifndef _AMD_SBDEF_H_ diff --git a/src/vendorcode/amd/cimx/sb700/SBMAIN.c b/src/vendorcode/amd/cimx/sb700/SBMAIN.c new file mode 100644 index 0000000..7468eb2 --- /dev/null +++ b/src/vendorcode/amd/cimx/sb700/SBMAIN.c @@ -0,0 +1,289 @@ +/***************************************************************************** + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + ***************************************************************************/ + + +#include "Platform.h" + +#ifndef B1_IMAGE + +BUILDPARAM DfltStaticOptions={ + BIOS_SIZE, // BIOS Size + LEGACY_FREE, // Legacy Free Option + 0x00, // Dummy space holder + + 0x00, // ECKbd disable/enable + 0x00, // EcChannel0 disable/enable + 0x00, // Dummy space holder1 + + SMBUS0_BASE_ADDRESS, // Smbus Base Address; + SMBUS1_BASE_ADDRESS, // Smbus Base Address; + SIO_PME_BASE_ADDRESS, // SIO PME Base Address + WATCHDOG_TIMER_BASE_ADDRESS, // Watchdog Timer Base Address + SPI_BASE_ADDRESS, + + PM1_EVT_BLK_ADDRESS, // AcpiPm1EvtBlkAddr; + PM1_CNT_BLK_ADDRESS, // AcpiPm1CntBlkAddr; + PM1_TMR_BLK_ADDRESS, // AcpiPmTmrBlkAddr; + CPU_CNT_BLK_ADDRESS, // CpuControlBlkAddr; + GPE0_BLK_ADDRESS, // AcpiGpe0BlkAddr; + SMI_CMD_PORT, // SmiCmdPortAddr; + ACPI_PMA_CNT_BLK_ADDRESS, // AcpiPmaCntBlkAddr; + + EC_LDN5_MAILBOX_ADDRESS, + EC_LDN5_IRQ, + EC_LDN9_MAILBOX_ADDRESS, // EC LDN9 Mailbox address + RESERVED_VALUE, + RESERVED_VALUE, + RESERVED_VALUE, + RESERVED_VALUE, + + HPET_BASE_ADDRESS, // HPET Base address + + SATA_IDE_MODE_SSID, + SATA_RAID_MODE_SSID, + SATA_RAID5_MODE_SSID, + SATA_AHCI_SSID, + + OHCI0_SSID, + OHCI1_SSID, + EHCI0_SSID, + OHCI2_SSID, + OHCI3_SSID, + EHCI1_SSID, + OHCI4_SSID, + SMBUS_SSID, + IDE_SSID, + AZALIA_SSID, + LPC_SSID, + P2P_SSID, +}; + + +/********************************************************************************* +* +* Routine Description: Config SB Before PCI INIT +* +* Arguments: +* +* pConfig - SBconfiguration +* +* Returns: +* +* void +* +**********************************************************************************/ +void sbBeforePciInit (AMDSBCFG* pConfig){ + BUILDPARAM *pStaticOptions; + + pStaticOptions = &pConfig->BuildParameters; + TRACE((DMSG_SB_TRACE, "CIMx - Entering sbBeforePciInit \n")); + commonInitEarlyBoot(pConfig); + commonInitEarlyPost(pConfig); +#ifndef NO_EC_SUPPORT + ecInitBeforePciEnum(pConfig); +#endif + usbInitBeforePciEnum(pConfig); // USB POST TIME Only + fcInitBeforePciEnum(pConfig); // Preinit flash controller + sataInitBeforePciEnum(pConfig); // Init SATA class code and PHY + programSubSystemIDs(pConfig, pStaticOptions); // Set subsystem/vendor ID + + TRACE((DMSG_SB_TRACE, "CIMx - Exiting sbBeforePciInit \n")); +} + + +/********************************************************************************* +* +* Routine Description: Config SB After PCI INIT +* +* Arguments: +* +* pConfig - SBconfiguration +* +* Returns: void +* +* Reference: atiSbAfterPciInit +* +**********************************************************************************/ +void sbAfterPciInit(AMDSBCFG* pConfig){ + BUILDPARAM *pStaticOptions; + + TRACE((DMSG_SB_TRACE, "CIMx - Entering sbAfterPciInit \n")); + + pStaticOptions = &pConfig->BuildParameters; + usbInitMidPost(pConfig); //usb initialization which is required only during post + usbInitAfterPciInit(pConfig); // Init USB MMIO + sataInitAfterPciEnum(pConfig); // SATA port enumeration + azaliaInitAfterPciEnum(pConfig); // Detect and configure High Definition Audio + + TRACE((DMSG_SB_TRACE, "CIMx - Exiting sbAfterPciInit \n")); +} + + +/********************************************************************************* +* +* Routine Description: Config SB during late POST +* +* Arguments: +* +* pConfig - SBconfiguration +* +* Returns: void +* +* Reference: atiSbLatePost +* +**********************************************************************************/ +void sbLatePost(AMDSBCFG* pConfig){ + UINT16 dwVar; + BUILDPARAM *pStaticOptions; + pStaticOptions = &pConfig->BuildParameters; + TRACE((DMSG_SB_TRACE, "CIMx - Entering sbLatePost \n")); + ReadPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG02, AccWidthUint16, &dwVar); + if (dwVar != SB7XX_DEVICE_ID){ + // Display message that the SB is wrong and stop the system + TRACE((DMSG_SB_TRACE, "Current system does not have SB700 chipset. Stopping\n")); + for(;;); + } + commonInitLateBoot(pConfig); + sataInitLatePost(pConfig); + hpetInit(pConfig, pStaticOptions); // SB Configure HPET base and enable bit +#ifndef NO_EC_SUPPORT + ecInitLatePost(pConfig); +#endif +} + +/********************************************************************************* +* +* Routine Description: Config SB before ACPI S3 resume PCI config device restore +* +* Arguments: +* +* pConfig - SBconfiguration +* +* Returns: void +* +* Reference: AtiSbBfPciRestore +* +**********************************************************************************/ +void sbBeforePciRestoreInit(AMDSBCFG* pConfig){ + BUILDPARAM *pStaticOptions; + + TRACE((DMSG_SB_TRACE, "CIMx - Entering sbBeforePciRestoreInit \n")); + + pConfig->S3Resume = 1; + + pStaticOptions = &pConfig->BuildParameters; + commonInitEarlyBoot(pConfig); // set /SMBUS/ACPI/IDE/LPC/PCIB + abLinkInitBeforePciEnum(pConfig); // Set ABCFG registers + usbInitBeforePciEnum(pConfig); // USB POST TIME Only + fcInitBeforePciEnum(pConfig); // Preinit flash controller + sataInitBeforePciEnum(pConfig); + programSubSystemIDs(pConfig, pStaticOptions); // Set subsystem/vendor ID +} + + +/********************************************************************************* +* +* Routine Description: Config SB after ACPI S3 resume PCI config device restore +* +* Arguments: +* +* pConfig - SBconfiguration +* +* Returns: void +* +* Reference: AtiSbAfPciRestore +* +**********************************************************************************/ +void sbAfterPciRestoreInit(AMDSBCFG* pConfig){ + BUILDPARAM *pStaticOptions; + + pConfig->S3Resume = 1; + + pStaticOptions = &pConfig->BuildParameters; + TRACE((DMSG_SB_TRACE, "CIMx - Entering sbAfterPciRestoreInit \n")); + + commonInitLateBoot(pConfig); + sataInitAfterPciEnum(pConfig); + azaliaInitAfterPciEnum(pConfig); // Detect and configure High Definition Audio + hpetInit(pConfig, pStaticOptions); // SB Configure HPET base and enable bit + sataInitLatePost(pConfig); + sbSmmAcpiOn(pConfig); +} + + +/*++ + +Routine Description: + + SB config hook during ACPI_ON + +Arguments: + + pConfig - SBconfiguration + +Returns: + + void + +--*/ + +void sbSmmAcpiOn(AMDSBCFG* pConfig){ + UINT32 ddBar5; + UINT8 dbPort; + + //RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG60+2, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT1+BIT0), 0); + if (getRevisionID() >= SB700_A13) + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG43, AccWidthUint8 | S3_SAVE, 0xFF, BIT0); //Enable Legacy DMA prefetch enhancement + + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG60+2, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT1+BIT0), 0); + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG64+3, AccWidthUint8| S3_SAVE, ~(UINT32)BIT7, 0); + programOhciMmioForEmulation(); + + // For IDE_TO_AHCI_MODE and IDE_TO_AMD_AHCI_MODE, clear Interrupt Status register for all ports + ReadPCI( ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG24), AccWidthUint32, &ddBar5); + if ((pConfig->SataClass == IDE_TO_AHCI_MODE) || (pConfig->SataClass == IDE_TO_AMD_AHCI_MODE)){ + for (dbPort = 0; dbPort <= 5; dbPort++) { + RWMEM(ddBar5 + SB_SATA_BAR5_REG110 + dbPort * 0x80, AccWidthUint32, 0x00, 0xFFFFFFFF); + } + } +} + + +UINT32 CallBackToOEM(UINT32 Func, UINTN Data,AMDSBCFG* pConfig){ + UINT32 Result=0; + TRACE((DMSG_SB_TRACE,"OEM Call Back Func [%x] Data [%x]\n",Func,Data)); + if (pConfig->StdHeader.pCallBack==NULL) + return Result; + Result = (*(pConfig->StdHeader.pCallBack))(Func,Data,pConfig); + TRACE((DMSG_SB_TRACE,"SB Hook Status [%x]\n",Result)); + return Result; +} + +#endif diff --git a/src/vendorcode/amd/cimx/sb700/SBPOR.c b/src/vendorcode/amd/cimx/sb700/SBPOR.c new file mode 100644 index 0000000..6c5740b --- /dev/null +++ b/src/vendorcode/amd/cimx/sb700/SBPOR.c @@ -0,0 +1,441 @@ +/***************************************************************************** + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + ***************************************************************************/ + + +#include "Platform.h" + +REG8MASK sbPorInitPciTable[] = { + // SMBUS Device(Bus 0, Dev 20, Func 0) + {0x00, SMBUS_BUS_DEV_FUN, 0}, + {SB_SMBUS_REGD0+2, 0x00, 0x01}, + {SB_SMBUS_REG40, 0x00, 0x44}, + {SB_SMBUS_REG40+1, 0xFF, 0xE9}, //Set smbus pci config 0x40[14]=1, This bit is used for internal bus flow control. + {SB_SMBUS_REG64, 0x00, 0xBF}, //SB_SMBUS_REG64[13]=1, delays back to back interrupts to the CPU + {SB_SMBUS_REG64+1, 0x00, 0x78}, + {SB_SMBUS_REG64+2, ~(UINT8)BIT6, 0x9E}, + {SB_SMBUS_REG64+3, 0x0F, 0x02}, + {SB_SMBUS_REG68+1, 0x00, 0x90}, + {SB_SMBUS_REG6C, 0x00, 0x20}, + {SB_SMBUS_REG78, 0x00, 0xFF}, + {SB_SMBUS_REG04, 0x00, 0x07}, + {SB_SMBUS_REG04+1, 0x00, 0x04}, + {SB_SMBUS_REGE1, 0x00, 0x99}, //RPR recommended setting, Sections "SMBUS Pci Config" & "IMC Access Control" + {SB_SMBUS_REGAC, ~(UINT8)BIT4, BIT1}, + {SB_SMBUS_REG60+2, ~(UINT8)(BIT1+BIT0) , 0x24}, // Disabling Legacy USB Fast SMI# Smbus_PCI_config 0x62 [5] = 1. Legacy USB + // can request SMI# to be sent out early before IO completion. + // Some applications may have problems with this feature. The BIOS should set this bit + // to 1 to disable the feature. Enabling Legacy Interrupt Smbus_PCI_Config 0x62[2]=1. + {0xFF, 0xFF, 0xFF}, + + // LPC Device(Bus 0, Dev 20, Func 3) + {0x00, LPC_BUS_DEV_FUN, 0}, + {SB_LPC_REG40, 0x00, 0x04}, + {SB_LPC_REG48, 0x00, 0x07}, + {SB_LPC_REG4A, 0x00, 0x20}, // Port Enable for IO Port 80h. + {SB_LPC_REG78, ~(UINT8)BIT0, 0x00}, + {SB_LPC_REG7C, 0x00, 0x05}, + {SB_LPC_REGB8+3, ~(UINT8)BIT0, BIT7+BIT6+BIT5+BIT3+BIT0}, //RPR recommended setting,Section "IO / Mem Decoding" & "SPI bus" + {0xFF, 0xFF, 0xFF}, + + // P2P Bridge(Bus 0, Dev 20, Func 4) + {0x00, SBP2P_BUS_DEV_FUN, 0}, + {SB_P2P_REG40, 0x00, 0x26}, // Enabling PCI-bridge subtractive decoding & PCI Bus 64-byte DMA Read Access + {SB_P2P_REG4B, 0xFF, BIT6+BIT7+BIT4}, + {SB_P2P_REG1C, 0x00, 0x11}, + {SB_P2P_REG1D, 0x00, 0x11}, + {SB_P2P_REG04, 0x00, 0x21}, + {SB_P2P_REG50, 0x02, 0x01}, // PCI Bridge upstream dual address window + {0xFF, 0xFF, 0xFF}, +}; + + +REG8MASK sbA13PorInitPciTable[] = { + // SMBUS Device(Bus 0, Dev 20, Func 0) + {0x00, SMBUS_BUS_DEV_FUN, 0}, + {SB_SMBUS_REG43, ~(UINT8)BIT3, 0x00}, //Make some hidden registers of smbus visible. + {SB_SMBUS_REG38, (UINT8)~BIT7, 00}, + {SB_SMBUS_REGAC+1, ~(UINT8)BIT5, 0}, //Enable SATA test/enhancement mode + {SB_SMBUS_REG43, 0xFF, BIT3}, //Make some hidden registers of smbus invisible. + {0xFF, 0xFF, 0xFF}, +}; + + +REG8MASK sbA14PorInitPciTable[] = { + // LPC Device(Bus 0, Dev 20, Func 3) + {0x00, LPC_BUS_DEV_FUN, 0}, + {SB_LPC_REG8C+2, ~(UINT8)BIT1, 00}, + {0xFF, 0xFF, 0xFF}, +}; + +REG8MASK sbPorPmioInitTbl[] = { + // index andmask ormask + {SB_PMIO_REG67, 0xFF, 0x02}, + {SB_PMIO_REG37, 0xFF, 0x04}, // Configure pciepme as rising edge + {SB_PMIO_REG50, 0x00, 0xE0}, // Enable CPU_STP (except S5) & PCI_STP + {SB_PMIO_REG60, 0xFF, 0x20}, // Enable Speaker + {SB_PMIO_REG65, (UINT8)~(BIT4+BIT7), 0x00},// Clear PM_IO 0x65[4] UsbResetByPciRstEnable to avoid S3 reset to reset USB + {SB_PMIO_REG55, ~(UINT8)BIT6, 0x07}, // Select CIR wake event to ACPI.GEVENT[23] & Clear BIT6 SoftPciRst for safety + {SB_PMIO_REG66, 0xFF, BIT5}, // Configure keyboard reset to generate pci reset + {SB_PMIO_REGB2, 0xFF, BIT7}, + {SB_PMIO_REG0E, 0xFF, BIT3}, // Enable ACPI IO decoding + {SB_PMIO_REGD7, 0xF6, 0x80}, + {SB_PMIO_REG7C, 0xFF, BIT4}, // enable RTC AltCentury register + + {SB_PMIO_REG75, 0xC0, 0x05}, // PME_TURN_OFF_MSG during ASF shutdown + {SB_PMIO_REG52, 0xC0, 0x08}, + + {SB_PMIO_REG8B, 0x00, 0x10}, + {SB_PMIO_REG69, 0xF9, 0x01 << 1}, // [Updated RPR] Set default WDT resolution to 10ms +}; + +REG8MASK sbA13PorPmioInitTbl[]={ + // index andmask ormask + {SB_PMIO_REGD7, 0xFF, BIT5+BIT0}, //Fixes for TT SB00068 & SB01054 (BIT5 & BIT0 correspondingly) + {SB_PMIO_REGBB, (UINT8)~BIT7, BIT6+BIT5}, //Fixes for TT SB00866 & SB00696 (BIT6 & BIT5 correspondingly) + // Always clear [7] to begin with SP5100 C1e disabled + +// {SB_PMIO_REG65, 0xFF, BIT7}, +// {SB_PMIO_REG75, 0xC0, 0x01}, // PME_TURN_OFF_MSG during ASF shutdown +// {SB_PMIO_REG52, 0xC0, 0x02}, + +}; + + +void sbPowerOnInit (AMDSBCFG *pConfig){ + UINT8 dbVar0, dbVar1, dbValue; + UINT16 dwTempVar; + BUILDPARAM *pBuildOptPtr; + + TRACE((DMSG_SB_TRACE, "CIMx - Entering sbPowerOnInit \n")); + + setRevisionID(); + ReadPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG02), AccWidthUint16 | S3_SAVE, &dwTempVar); + if (dwTempVar == SB750_SATA_DEFAULT_DEVICE_ID) + RWPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG9C, AccWidthUint8 | S3_SAVE, 0xFF, 0x01); + + // Set A-Link bridge access address. This address is set at device 14h, function 0, + // register 0f0h. This is an I/O address. The I/O address must be on 16-byte boundry. + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGF0, AccWidthUint32, 00, ALINK_ACCESS_INDEX); + + writeAlink(0x80000004, 0x04); // RPR 3.3 Enabling upstream DMA Access + writeAlink(0x30, 0x10); //AXINDC 0x10[9]=1, Enabling Non-Posted memory write for K8 platform. + writeAlink(0x34, readAlink(0x34) | BIT9); + + if (!(pConfig->ResetCpuOnSyncFlood)){ + //Enable reset on sync flood + writeAlink( (UINT32)( ((UINT32)SB_AB_REG10050) | ((UINT32)ABCFG << 30)), + (UINT32)( readAlink((((UINT32)SB_AB_REG10050) | ((UINT32)ABCFG << 30))) | ((UINT32)BIT2) )); + } + + pBuildOptPtr = &(pConfig->BuildParameters); + + WritePCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG90, AccWidthUint32 | S3_SAVE, &(pBuildOptPtr->Smbus0BaseAddress) ); + + dwTempVar = pBuildOptPtr->Smbus1BaseAddress & (UINT16)~BIT0; + if( dwTempVar != 0 ){ + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG58, AccWidthUint16 | S3_SAVE, 00, (dwTempVar|BIT0)); + // Disable ASF Slave controller on SB700 rev A15. + if (getRevisionID() == SB700_A15) { + RWIO((dwTempVar+0x0D), AccWidthUint8, (UINT8)~BIT6, BIT6); + } + } + + WritePCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG64, AccWidthUint16 | S3_SAVE, &(pBuildOptPtr->SioPmeBaseAddress)); + RWPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA0, AccWidthUint32 | S3_SAVE, 0x001F,(pBuildOptPtr->SpiRomBaseAddress)); + + WritePMIO(SB_PMIO_REG20, AccWidthUint16, &(pBuildOptPtr->AcpiPm1EvtBlkAddr)); + WritePMIO(SB_PMIO_REG22, AccWidthUint16, &(pBuildOptPtr->AcpiPm1CntBlkAddr)); + WritePMIO(SB_PMIO_REG24, AccWidthUint16, &(pBuildOptPtr->AcpiPmTmrBlkAddr)); + WritePMIO(SB_PMIO_REG26, AccWidthUint16, &(pBuildOptPtr->CpuControlBlkAddr)); + WritePMIO(SB_PMIO_REG28, AccWidthUint16, &(pBuildOptPtr->AcpiGpe0BlkAddr)); + WritePMIO(SB_PMIO_REG2A, AccWidthUint16, &(pBuildOptPtr->SmiCmdPortAddr)); + WritePMIO(SB_PMIO_REG2C, AccWidthUint16, &(pBuildOptPtr->AcpiPmaCntBlkAddr)); + RWPMIO(SB_PMIO_REG2E, AccWidthUint16, 0x00,(pBuildOptPtr->SmiCmdPortAddr)+8); + WritePMIO(SB_PMIO_REG6C, AccWidthUint32, &(pBuildOptPtr->WatchDogTimerBase)); + + //Program power on pci init table + programPciByteTable( (REG8MASK*)FIXUP_PTR(&sbPorInitPciTable[0]), sizeof(sbPorInitPciTable)/sizeof(REG8MASK) ); + //Program power on pmio init table + programPmioByteTable( (REG8MASK *)FIXUP_PTR(&sbPorPmioInitTbl[0]), (sizeof(sbPorPmioInitTbl)/sizeof(REG8MASK)) ); + + dbValue = 0x00; + ReadIO (SB_IOMAP_REGC14, AccWidthUint8, &dbValue); + dbValue &= 0xF3; + WriteIO (SB_IOMAP_REGC14, AccWidthUint8, &dbValue); + + dbValue = 0x0A; + WriteIO (SB_IOMAP_REG70, AccWidthUint8, &dbValue); + ReadIO (SB_IOMAP_REG71, AccWidthUint8, &dbValue); + dbValue &= 0xEF; + WriteIO (SB_IOMAP_REG71, AccWidthUint8, &dbValue); + + + if (getRevisionID() >= SB700_A13){ + programPciByteTable( (REG8MASK*)FIXUP_PTR(&sbA13PorInitPciTable[0]), sizeof(sbA13PorInitPciTable)/sizeof(REG8MASK) ); + programPmioByteTable( (REG8MASK *)FIXUP_PTR(&sbA13PorPmioInitTbl[0]), (sizeof(sbA13PorPmioInitTbl)/sizeof(REG8MASK)) ); + } + + if ((getRevisionID() >= SB700_A14) ) + programPciByteTable( (REG8MASK*)FIXUP_PTR(&sbA14PorInitPciTable[0]), sizeof(sbA14PorInitPciTable)/sizeof(REG8MASK) ); + + if ( (getRevisionID() >= SB700_A14) && ( (pConfig->TimerClockSource == 1) || (pConfig->TimerClockSource == 2) )){ + ReadPMIO(SB_PMIO_REGD4, AccWidthUint8, &dbVar1); + if (!(dbVar1 & BIT6)){ + RWPMIO(SB_PMIO_REGD4, AccWidthUint8, 0xFF, BIT6); + pConfig->RebootRequired=1; + } + } + + if (getRevisionID() > SB700_A11) { + if (pConfig->PciClk5 == 1) + RWPMIO(SB_PMIO_REG41, AccWidthUint8, ~(UINT32)BIT1, BIT1); // Enabled PCICLK5 for A12 + } + + dbVar0 = (pBuildOptPtr->BiosSize + 1) & 7; + if (dbVar0 > 4) { + dbVar0 = 0; + } + //KZ [061811]-It's used wrong BIOS SIZE for Coreboot. RWPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG6C, AccWidthUint8 | S3_SAVE, 0x00, 0xF8 << dbVar0); + + if (pConfig->Spi33Mhz) + //spi reg0c[13:12] to 01h to run spi 33Mhz in system bios + RWMEM((pBuildOptPtr->SpiRomBaseAddress)+SB_SPI_MMIO_REG0C,AccWidthUint16 | S3_SAVE, ~(UINT32)(BIT13+BIT12), BIT12); + + //SB internal spread spectrum settings. A reboot is required if the spread spectrum settings have to be changed + //from the existing value. + ReadPMIO(SB_PMIO_REG42, AccWidthUint8, &dbVar0); + if (pConfig->SpreadSpectrum != (dbVar0 >> 7) ) + pConfig->RebootRequired = 1; + if (pConfig->SpreadSpectrum) + RWPMIO(SB_PMIO_REG42, AccWidthUint8, ~(UINT32)BIT7, BIT7); + else + RWPMIO(SB_PMIO_REG42, AccWidthUint8, ~(UINT32)BIT7, 0); + + if ( !(pConfig->S3Resume) ){ + //To detect whether internal clock chip is used, do the following procedure + //set PMIO_B2[7]=1, then read PMIO_B0[4]; if it is 1, we are strapped to CLKGEN mode. + //if it is 0, we are using clock chip on board. + RWPMIO(SB_PMIO_REGB2, AccWidthUint8, 0xFF, BIT7); + + //Do the following programming only for SB700-A11. + //1. Set PMIO_B2 [7]=1 and read B0 and B1 and save those values. + //2. Set PMIO_B2 [7]=0 + //3. Write the saved values from step 1, back to B0 and B1. + //4. Set PMIO_B2 [6]=1. + ReadPMIO(SB_PMIO_REGB0, AccWidthUint16, &dwTempVar); + if (getRevisionID() == SB700_A11){ + RWPMIO(SB_PMIO_REGB2, AccWidthUint8, ~(UINT32)BIT7, 00); + WritePMIO(SB_PMIO_REGB0, AccWidthUint16, &dwTempVar); + RWPMIO(SB_PMIO_REGB2, AccWidthUint8, 0xFF, BIT6); + } + + if (!(dwTempVar & BIT4)){ + RWPMIO(SB_PMIO_REGD0, AccWidthUint8, ~(UINT32)BIT0, 0); //Enable PLL2 + + //we are in external clock chip on the board + if (pConfig->UsbIntClock == CIMX_OPTION_ENABLED){ + //Configure usb clock to come from internal PLL + RWPMIO(SB_PMIO_REGD2, AccWidthUint8, 0xFF, BIT3); //Enable 48Mhz clock from PLL2 + RWPMIO(SB_PMIO_REGBD, AccWidthUint8, ~(UINT32)BIT4, BIT4); //Tell USB PHY to use internal 48Mhz clock from PLL2 + } + else{ + //Configure usb clock to come from external clock + RWPMIO(SB_PMIO_REGBD, AccWidthUint8, ~(UINT32)BIT4, 0); //Tell USB PHY to use external 48Mhz clock from PLL2 + RWPMIO(SB_PMIO_REGD2, AccWidthUint8, ~(UINT32)BIT3, 00); //Disable 48Mhz clock from PLL2 + } + } + else{ + //we are using internal clock chip on this board + if (pConfig->UsbIntClock == CIMX_OPTION_ENABLED){ + //Configure usb clock to come from internal PLL + RWPMIO(SB_PMIO_REGD2, AccWidthUint8, ~(UINT32)BIT3, 0); //Enable 48Mhz clock from PLL2 + RWPMIO(SB_PMIO_REGBD, AccWidthUint8, ~(UINT32)BIT4, BIT4); //Tell USB PHY to use internal 48Mhz clock from PLL2 + } + else{ + //Configure usb clock to come from external clock + RWPMIO(SB_PMIO_REGBD, AccWidthUint8, ~(UINT32)BIT4, 0); //Tell USB PHY to use external 48Mhz clock from PLL2 + RWPMIO(SB_PMIO_REGD2, AccWidthUint8, ~(UINT32)BIT3, BIT3); //Disable 48Mhz clock from PLL2 + } + } + + ReadPMIO(SB_PMIO_REG43, AccWidthUint8, &dbVar0); + RWPMIO(SB_PMIO_REG43, AccWidthUint8, ~(UINT32)(BIT6+BIT5+BIT0), (pConfig->UsbIntClock << 5)); + //Check whether our usb clock settings changed compared to previous boot, if yes then we need to reboot. + if ( (dbVar0 & BIT0) || ( (pConfig->UsbIntClock) != ((dbVar0 & (BIT6+BIT5)) >> 5)) ) pConfig->RebootRequired = 1; + } + + if (pBuildOptPtr->LegacyFree) //if LEGACY FREE system + RWPCI(((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG44), AccWidthUint32 | S3_SAVE, 00, 0x0003C000); + else + RWPCI(((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG44), AccWidthUint32 | S3_SAVE, 00, 0xFF03FFD5); + + if ( (getRevisionID() == SB700_A14) || (getRevisionID() == SB700_A13)){ + RWPMIO(SB_PMIO_REG65, AccWidthUint8, 0xFF, BIT7); + RWPMIO(SB_PMIO_REG75, AccWidthUint8, 0xC0, BIT0); + RWPMIO(SB_PMIO_REG52, AccWidthUint8, 0xC0, BIT1); + } + + if (getRevisionID() >= SB700_A15) { + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG40+3, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT3), 0); + //Enable unconditional shutdown fix in A15 + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG38+1, AccWidthUint8 | S3_SAVE, 0xFF, BIT4); + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG40+3, AccWidthUint8 | S3_SAVE, 0xFF, BIT3); + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG06+1, AccWidthUint8 | S3_SAVE, 0xFF, 0xD0); + } + + // [Updated RPR] Set ImcHostSmArbEn(SMBUS:0xE1[5]) only when IMC is enabled + if (isEcPresent()) { + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGE1, AccWidthUint8 | S3_SAVE, 0xFF, BIT5); + } + + //According to AMD Family 15h Models 00h-0fh processor BKDG section 2.12.8 LDTSTOP requirement + // to program VID/FID LDTSTP# duration selection register + AMDFamily15CpuLdtStopReq(); + +#ifndef NO_EC_SUPPORT + ecPowerOnInit(pBuildOptPtr, pConfig); +#endif +} + + +void setRevisionID(void){ + UINT8 dbVar0, dbVar1; + + ReadPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG08), AccWidthUint8, &dbVar0); + ReadPMIO(SB_PMIO_REG53, AccWidthUint8, &dbVar1); + if ( (dbVar0 == 0x39) && (dbVar1 & BIT6) && !(dbVar1 & BIT7)){ + RWPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG40), AccWidthUint8, ~(UINT32)BIT0, BIT0); + RWPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG08), AccWidthUint8, 00, SB700_A12); + RWPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG40), AccWidthUint8, ~(UINT32)BIT0, 00); + } + ReadPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG08), AccWidthUint8, &dbVar0); +} + + +UINT8 getRevisionID(void){ + UINT8 dbVar0; + + ReadPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG08), AccWidthUint8, &dbVar0); + return dbVar0; +} + + +void AMDFamily15CpuLdtStopReq(void) { + CPUID_DATA CpuId; + CPUID_DATA CpuId_Brand; + UINT8 dbVar0, dbVar1, dbVar2; + + //According to AMD Family 15h Models 00h-0fh processor BKDG section 2.12.8 LDTSTOP requirement + //to program VID/FID LDTSTP# duration selection register + //If any of the following system configuration properties are true LDTSTP# assertion time required by the processor is 10us: + // 1. Any link in the system operating at a Gen 1 Frequency. + // 2. Also for server platform (G34/C32) set PM_REG8A[6:4]=100b (16us) + + CpuidRead (0x01, &CpuId); + CpuidRead (0x80000001, &CpuId_Brand); //BrandID, to read socket type + if ((CpuId.REG_EAX & 0xFFFFFF00) == 0x00600F00) { + + //Program to Gen 3 default value - 001b + RWPMIO(SB_PMIO_REG8A, AccWidthUint8, 0x8F, 0x10); //set [6:4]=001b + + //Any link in the system operating at a Gen 1 Frequency. + //Check Link 0 - Link connected regsister + ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REG98), AccWidthUint8, &dbVar2); + dbVar2 = dbVar2 & 0x01; + + if(dbVar2 == 0x01) { + //Check Link 0 - Link Frequency Freq[4:0] + ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REG89), AccWidthUint8, &dbVar0); + ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REG9C), AccWidthUint8, &dbVar1); + dbVar0 = dbVar0 & 0x0F; //Freq[3:0] + dbVar1 = dbVar1 & 0x01; //Freq[4] + dbVar0 = (dbVar1 << 4) | dbVar0; //Freq[4:0] + //Value 6 or less indicate Gen1 + if(dbVar0 <= 0x6) { + RWPMIO(SB_PMIO_REG8A, AccWidthUint8, 0x8F, 0x40); //set [6:4]=100b + } + } + + //Check Link 1 - Link connected regsister + ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGB8), AccWidthUint8, &dbVar2); + dbVar2 = dbVar2 & 0x01; + if(dbVar2 == 0x01) { + //Check Link 1 - Link Frequency Freq[4:0] + ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGA9), AccWidthUint8, &dbVar0); + ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGBC), AccWidthUint8, &dbVar1); + dbVar0 = dbVar0 & 0x0F; //Freq[3:0] + dbVar1 = dbVar1 & 0x01; //Freq[4] + dbVar0 = (dbVar1 << 4) | dbVar0; //Freq[4:0] + //Value 6 or less indicate Gen1 + if(dbVar0 <= 0x6) { + RWPMIO(SB_PMIO_REG8A, AccWidthUint8, 0x8F, 0x40); //set [6:4]=100b + } + } + + //Check Link 2 - Link connected regsister + ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGD8), AccWidthUint8, &dbVar2); + dbVar2 = dbVar2 & 0x01; + if(dbVar2 == 0x01) { + //Check Link 2 - Link Frequency Freq[4:0] + ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGC9), AccWidthUint8, &dbVar0); + ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGDC), AccWidthUint8, &dbVar1); + dbVar0 = dbVar0 & 0x0F; //Freq[3:0] + dbVar1 = dbVar1 & 0x01; //Freq[4] + dbVar0 = (dbVar1 << 4) | dbVar0; //Freq[4:0] + //Value 6 or less indicate Gen1 + if(dbVar0 <= 0x6) { + RWPMIO(SB_PMIO_REG8A, AccWidthUint8, 0x8F, 0x40); //set [6:4]=100b + } + } + + //Check Link 3 - Link connected regsister + ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGF8), AccWidthUint8, &dbVar2); + dbVar2 = dbVar2 & 0x01; + if(dbVar2 == 0x01) { + //Check Link 3 - Link Frequency Freq[4:0] + ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGE9), AccWidthUint8, &dbVar0); + ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGFC), AccWidthUint8, &dbVar1); + dbVar0 = dbVar0 & 0x0F; //Freq[3:0] + dbVar1 = dbVar1 & 0x01; //Freq[4] + dbVar0 = ((dbVar1 << 4) | dbVar0); //Freq[4:0] + //Value 6 or less indicate Gen1 + if(dbVar0 <= 0x6) { + RWPMIO(SB_PMIO_REG8A, AccWidthUint8, 0x8F, 0x40); //set [6:4]=100b + } + } + + // Server platform (G34/C32) set PM_REG8A[6:4]=100b (16us) + if(((CpuId_Brand.REG_EBX & 0xF0000000) == 0x30000000) || ((CpuId_Brand.REG_EBX & 0xF0000000) == 0x50000000)) { + RWPMIO(SB_PMIO_REG8A, AccWidthUint8, 0x8F, 0x40); //set [6:4]=100b + } + } + +} + diff --git a/src/vendorcode/amd/cimx/sb700/SBTYPE.h b/src/vendorcode/amd/cimx/sb700/SBTYPE.h new file mode 100644 index 0000000..faeae5d --- /dev/null +++ b/src/vendorcode/amd/cimx/sb700/SBTYPE.h @@ -0,0 +1,249 @@ +/*;******************************************************************************** +; +; Copyright (C) 2012 Advanced Micro Devices, Inc. +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; * Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; * Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution. +; * Neither the name of Advanced Micro Devices, Inc. nor the names of +; its contributors may be used to endorse or promote products derived +; from this software without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;*********************************************************************************/ + +#ifndef _AMD_SBTYPE_H_ +#define _AMD_SBTYPE_H_ + +#pragma pack(push,1) + +typedef UINT32 (*CIM_HOOK_ENTRY)(UINT32 Param1, UINTN Param2, void* pConfig); +typedef void (*SMM_SERVICE_ROUTINE) (void); + +typedef struct _STDCFG{ + UINT32 pImageBase; + UINT32 pPcieBase; + UINT8 Func; + CIM_HOOK_ENTRY pCallBack; + UINT32 pB2ImageBase; +}STDCFG; //Size of stdcfg is 17 bytes + +typedef struct _BUILDPARAM +{ + UINT16 BiosSize:3; //0-1MB, 1-2MB, 2-4MB, 3-8MB, 7-512KB, all other values reserved + UINT16 LegacyFree:1; + UINT16 Dummy0:12; + + UINT16 EcKbd:1; + UINT16 EcChannel0:1; + UINT16 Dummy1:14; + + UINT32 Smbus0BaseAddress; + UINT16 Smbus1BaseAddress; + UINT32 SioPmeBaseAddress; + UINT32 WatchDogTimerBase; + UINT32 SpiRomBaseAddress; + + UINT16 AcpiPm1EvtBlkAddr; + UINT16 AcpiPm1CntBlkAddr; + UINT16 AcpiPmTmrBlkAddr; + UINT16 CpuControlBlkAddr; + UINT16 AcpiGpe0BlkAddr; + UINT16 SmiCmdPortAddr; + UINT16 AcpiPmaCntBlkAddr; + + UINT16 EcLdn5MailBoxAddr; + UINT8 EcLdn5Irq; + UINT16 EcLdn9MailBoxAddr; + UINT32 ReservedDword0; + UINT32 ReservedDword1; + UINT32 ReservedDword2; + UINT32 ReservedDword3; + + UINT32 HpetBase; //HPET Base address + + UINT32 SataIDESsid; + UINT32 SataRAIDSsid; + UINT32 SataRAID5Ssid; + UINT32 SataAHCISsid; + + UINT32 Ohci0Ssid; + UINT32 Ohci1Ssid; + UINT32 Ehci0Ssid; + UINT32 Ohci2Ssid; + UINT32 Ohci3Ssid; + UINT32 Ehci1Ssid; + UINT32 Ohci4Ssid; + UINT32 SmbusSsid; + UINT32 IdeSsid; + UINT32 AzaliaSsid; + UINT32 LpcSsid; + UINT32 P2PSsid; +}BUILDPARAM; + +typedef struct _CODECENTRY{ + UINT8 Nid; + UINT32 Byte40; +}CODECENTRY; + +typedef struct _CODECTBLLIST{ + UINT32 CodecID; + CODECENTRY* CodecTablePtr; +}CODECTBLLIST; + +typedef struct _AMDSBCFG +{ + STDCFG StdHeader; //offset 0:16 - 17 bytes + //UINT32 MsgXchgBiosCimx; //offset 17:20 - 4 bytes + UINT32 S3Resume:1; + UINT32 RebootRequired:1; + UINT32 Spi33Mhz:1; + UINT32 SpreadSpectrum:1; + UINT32 UsbIntClock:1; //0:Use external clock, 1:Use internal clock + UINT32 PciClk5:1; //0:disable, 1:enable + UINT32 TimerClockSource:2; //0:100Mhz PCIE Reference clock (same as SB700-A12, + //1: 14Mhz using 25M_48M_66M_OSC pin, 2: Auto (100Mhz for SB700-A12, 14Mhz + //using 25M_48m_66m_0SC pin for SB700-A14, SB710, SP5100 + UINT32 ResetCpuOnSyncFlood:1; //0:Reset CPU on Sync Flood, 1:Do not reset CPU on sync flood + UINT32 MsgXchgBiosCimxDummyBB:23; + + /** BuildParameters - The STATIC platform information for CIMx Module. */ + BUILDPARAM BuildParameters; + + //SATA Configuration + UINT32 SataController :1; //0, 0:disable 1:enable* //offset 25:28 - 4 bytes + UINT32 SataClass :3; //1, 0:IDE* 1:RAID 2:AHCI 3:Legacy IDE 4:IDE->AHCI 5:AMD_AHCI, 6:IDE->AMD_AHCI + UINT32 SataSmbus :1; //4, 0:disable 1:enable* + UINT32 SataAggrLinkPmCap:1; //5, 0:OFF 1:ON + UINT32 SataPortMultCap :1; //6, 0:OFF 1:ON + UINT32 SataReserved :2; //8:7, Reserved + UINT32 SataClkAutoOff :1; //9, AutoClockOff for IDE modes 0:Disabled, 1:Enabled + UINT32 SataIdeCombinedMode :1; //10, SataIDECombinedMode 0:Disabled, 1:Enabled + UINT32 SataIdeCombMdPriSecOpt:1; //11, Combined Mode, SATA as primary or secondary 0:primary 1:secondary + UINT32 SataReserved1 :6; //17:12, Not used currently + UINT32 SataEspPort :6; //23:18 SATA port is external accessiable on a signal only connector (eSATA:) + UINT32 SataClkAutoOffAhciMode:1; //24: Sata Auto clock off for AHCI mode + UINT32 SataHpcpButNonESP:6; //25:30 Hotplug capable but not e-sata port + UINT32 SataHideUnusedPort:1; //31, 0:Disabled 1:Enabled + + //Flash Configuration //offset 29:30 - 2 bytes + UINT16 FlashController :1; //0, 0:disable FC & enable IDE 1:enable FC & disable IDE + UINT16 FlashControllerMode:1; //1, 0:Flash behind SATA 1:Flash as standalone + UINT16 FlashHcCrc:1; //2, + UINT16 FlashErrorMode:1; //3 + UINT16 FlashNumOfBankMode:1; //4 + UINT16 FlashDummy:11; //5:15 + + //USB Configuration //offset 31:32 - 2 bytes + UINT16 Usb1Ohci0 :1; //0, 0:disable 1:enable* Bus 0 Dev 18 Func0 + UINT16 Usb1Ohci1 :1; //1, 0:disable 1:enable* Bus 0 Dev 18 Func1 + UINT16 Usb1Ehci :1; //2, 0:disable 1:enable* Bus 0 Dev 18 Func2 + UINT16 Usb2Ohci0 :1; //3, 0:disable 1:enable* Bus 0 Dev 19 Func0 + UINT16 Usb2Ohci1 :1; //4, 0:disable 1:enable* Bus 0 Dev 19 Func1 + UINT16 Usb2Ehci :1; //5, 0:disable 1:enable* Bus 0 Dev 19 Func2 + UINT16 Usb3Ohci :1; //6, 0:disable 1:enable* Bus 0 Dev 20 Func5 + UINT16 UsbOhciLegacyEmulation:1; //7, 0:Enabled, 1:Disabled + UINT16 UsbDummy :8; //8:15 + + //Azalia Configuration //offset 33:36 - 4 bytes + UINT32 AzaliaController:2; //0, 0:AUTO, 1:disable, 2:enable + UINT32 AzaliaPinCfg :1; //2, 0:disable, 1:enable + UINT32 AzaliaFrontPanel:2; //3, 0:AUTO, 1:disable, 2:enable + UINT32 FrontPanelDetected:1; //5, 0:Not detected, 1:detected + UINT32 AzaliaSdin0 :2; //6 + UINT32 AzaliaSdin1 :2; //8 + UINT32 AzaliaSdin2 :2; //10 + UINT32 AzaliaSdin3 :2; //12 + UINT32 AzaliaDummy :18; //14:31 + + CODECTBLLIST* pAzaliaOemCodecTablePtr; //offset 37:40 - 4 bytes + UINT32 pAzaliaOemFpCodecTableptr; //offset 41:44 - 4 bytes + + //Miscellaneous Configuration //offset 45:48 - 4 bytes + UINT32 MiscReserved0:1; //0 + UINT32 HpetTimer:1; //1, 0:disable 1:enable + UINT32 PciClks:5; //2:6, 0:disable, 1:enable + UINT32 MiscReserved1:3; //9:7, Reserved + UINT32 IdeController:1; //10, 0:Enable, 1:Disabled + UINT32 MobilePowerSavings:1; //11, 0:Disable, 1:Enable Power saving features especially for Mobile platform + UINT32 ExternalRTCClock:1; //12, 0:Don't Shut Off, 1:Shut Off, external RTC clock + UINT32 AcpiS1Supported:1; //13, 0:S1 not supported, 1:S1 supported + UINT32 AnyHT200MhzLink:1; //14, 0:No HT 200Mhz Link in platform, 1; There is 200MHz HT Link in platform + UINT32 WatchDogTimerEnable:1; //15, [0]: WDT disabled; 1: WDT enabled + UINT32 MTC1e:1; //16, Message Triggered C1e - 0:Disabled*, 1:Enabled + UINT32 HpetMsiDis:1; //17, HPET MSI - 0:Enable HPET MSI, 1:Disable + UINT32 EhciDataCacheDis:1; //18, 0:Date Cache Enabled, 1:Date Cache Disabled /** EHCI Async Data Cache Disable */ + UINT32 MiscDummy:13; + + UINT32 AsmAslInfoExchange0; //offset 49:52 - 4 bytes + UINT32 AsmAslInfoExchange1; //offset 53:56 + + //DebugOptions_1 //offset 57:60 + UINT32 FlashPinConfig :1; //0, 0:desktop mode 1:mobile mode + UINT32 UsbPhyPowerDown :1; //1 + UINT32 PcibClkStopOverride :10; //11:2 + UINT32 Debug1Reserved0:4; //15:11 + UINT32 AzaliaSnoop:1; //16 0:Disable, 1:Enable + UINT32 SataSscPscCap:1; //17, 0:Enable SSC/PSC capability, 1:Disable SSC/PSC capability + UINT32 SataPortMode:6; //23:18, 0: AUTO, 1:Force SATA port(6/5/4/3/2/1) to GEN1 + UINT32 SataPhyWorkaround:2; //25:24, 0:AUTO, 1:Enable, 2:Disable + UINT32 Gen1DeviceShutdownDuringPhyWrknd:2; //27:26, 0:AUTO, 1:YES, 2:NO + UINT32 OhciIsoOutPrefetchDis:1; //28, 0:Enable OHCI ISO OUT prefetch, 1:Disable + UINT32 Debug1Dummy:3; // + + //DebugOptions_2 + UINT32 PcibAutoClkCtrlLow:16; + UINT32 PcibAutoClkCtrlHigh:16; + + //TempMMIO + UINT32 TempMMIO:32; + +}AMDSBCFG; + +typedef struct _SMMSERVICESTRUC +{ + UINT8 enableRegNum; + UINT8 enableBit; + UINT8 statusRegNum; + UINT8 statusBit; + CHAR8 *debugMessage; + SMM_SERVICE_ROUTINE serviceRoutine; +}SMMSERVICESTRUC; + +typedef struct _ABTblEntry +{ + UINT8 regType; + UINT32 regIndex; + UINT32 regMask; + UINT32 regData; +}ABTBLENTRY; + +#define PCI_ADDRESS(bus,dev,func,reg) \ +(UINT32) ( (((UINT32)bus) << 24) + (((UINT32)dev) << 19) + (((UINT32)func) << 16) + ((UINT32)reg) ) + +typedef UINT32 CIM_STATUS; +#define CIM_SUCCESS 0x00000000 +#define CIM_ERROR 0x80000000 +#define CIM_UNSUPPORTED 0x80000001 + +#pragma pack(pop) + +#define CIMX_OPTION_DISABLED 0 +#define CIMX_OPTION_ENABLED 1 + +#endif // _AMD_SBTYPE_H_ diff --git a/src/vendorcode/amd/cimx/sb700/SMM.c b/src/vendorcode/amd/cimx/sb700/SMM.c new file mode 100644 index 0000000..0d752fb --- /dev/null +++ b/src/vendorcode/amd/cimx/sb700/SMM.c @@ -0,0 +1,91 @@ +/***************************************************************************** + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + ***************************************************************************/ + + +#include "Platform.h" + +SMMSERVICESTRUC smmItemsTable[]={ + {SB_PMIO_REG0E, BIT2, SB_PMIO_REG0F, BIT2, (CHAR8 *)"Software SMI through SMI CMD port \n ", softwareSMIservice}, + {SB_PMIO_REG00, BIT4, SB_PMIO_REG01, BIT4, (CHAR8 *)"Software initiated SMI \n ", NULL}, + {SB_PMIO_REG02, 0xFF, SB_PMIO_REG05, 0xFF, (CHAR8 *)"SMI on IRQ15-8 \n ", NULL}, + {SB_PMIO_REG03, 0xFF, SB_PMIO_REG06, 0xFF, (CHAR8 *)"SMI on IRQ7-0 \n ", NULL}, + {SB_PMIO_REG04, 0xFF, SB_PMIO_REG07, 0xFF, (CHAR8 *)"SMI on legacy devices activity(Serial, FDD etc) \n ", NULL}, + {SB_PMIO_REG1C, 0xFF, SB_PMIO_REG1D, 0xFF, (CHAR8 *)"SMI on PIO 0123 \n ", NULL}, + {SB_PMIO_REGA8, 0x0F, SB_PMIO_REGA9, 0xFF, (CHAR8 *)"SMI on PIO 4567 \n ", NULL}, +}; + + +/*++ + +Routine Description: + + SB SMI service + +Arguments: + + pConfig - SBconfiguration + +Returns: + + void + +--*/ + +void sbSmmService(AMDSBCFG* pConfig){ + UINT8 i, dbEnableValue, dbStatusValue; + SMMSERVICESTRUC *pSmmItems; + SMM_SERVICE_ROUTINE serviceRoutine; + + pSmmItems = (SMMSERVICESTRUC *)FIXUP_PTR(&smmItemsTable[0]); + TRACE((DMSG_SB_TRACE, "CIMx - Entering SMM services \n")); + for (i = 1; i <= (sizeof(smmItemsTable)/sizeof(SMMSERVICESTRUC)); i++){ + dbEnableValue = pSmmItems->enableRegNum; + ReadPMIO(pSmmItems->enableRegNum, AccWidthUint8, &dbEnableValue); + ReadPMIO(pSmmItems->statusRegNum, AccWidthUint8, &dbStatusValue); + if ( (dbEnableValue & (pSmmItems->enableBit)) && (dbStatusValue & (pSmmItems->statusBit)) ){ + TRACE((DMSG_SB_TRACE, "\n \nSmi source is: %s \n", pSmmItems->debugMessage)); + TRACE((DMSG_SB_TRACE, "Enable Reg:%d Value:%d\n", pSmmItems->enableRegNum, dbEnableValue)); + TRACE((DMSG_SB_TRACE, "Status Reg:%d Value:%d\n\n", pSmmItems->statusRegNum, dbStatusValue)); + if ( (pSmmItems->serviceRoutine)!= NULL){ + serviceRoutine = (void *)FIXUP_PTR(pSmmItems->serviceRoutine); + serviceRoutine(); + } + } + } + TRACE((DMSG_SB_TRACE, "CIMx - Exiting SMM services \n")); +} + + +void softwareSMIservice(void){ + UINT16 dwSmiCmdPort, dwVar; + ReadPMIO(SB_PMIO_REG2A, AccWidthUint16, &dwSmiCmdPort); + ReadIO(dwSmiCmdPort, AccWidthUint16, &dwVar); + TRACE((DMSG_SB_TRACE, "SMI CMD Port Address: %X SMICMD Port value is %X \n", dwSmiCmdPort, dwVar)); +} diff --git a/src/vendorcode/amd/cimx/sb700/USB.c b/src/vendorcode/amd/cimx/sb700/USB.c new file mode 100644 index 0000000..9c5e7b3 --- /dev/null +++ b/src/vendorcode/amd/cimx/sb700/USB.c @@ -0,0 +1,187 @@ +/***************************************************************************** + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + ***************************************************************************/ + + +#include "Platform.h" + + +void usbInitBeforePciEnum(AMDSBCFG* pConfig){ + UINT8 dbVar=0; + + TRACE((DMSG_SB_TRACE, "Entering PreInit Usb \n")); + if (pConfig->Usb1Ohci0){ + dbVar = (pConfig->Usb1Ehci << 2); + dbVar |= ((pConfig->Usb1Ohci0) << 0); + dbVar |= ((pConfig->Usb1Ohci1) << 1); + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG68, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT0+BIT1+BIT2), dbVar ); + } + if (pConfig->Usb2Ohci0){ + dbVar = (pConfig->Usb2Ehci << 6) ; + dbVar |= ((pConfig->Usb2Ohci0) << 4); + dbVar |= ((pConfig->Usb2Ohci1) << 5); + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG68, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT6+BIT4+BIT5), dbVar ); + } + if (pConfig->Usb3Ohci) + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG68, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT7), ((pConfig->Usb3Ohci) << 7) ); + + RWPCI((USB1_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG50+1, AccWidthUint16 | S3_SAVE, ~(UINT32)(BIT4), BIT4); +} + + +void usbInitAfterPciInit(AMDSBCFG* pConfig){ + UINT32 ddBarAddress, ddVar; + + ReadPCI((USB1_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG10, AccWidthUint32, &ddBarAddress);//Get BAR address + if ( (ddBarAddress != -1) && (ddBarAddress != 0) ){ + //Enable Memory access + RWPCI((USB1_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG04, AccWidthUint8, 0, BIT1); + //USB Common PHY CAL & Control Register setting + ddVar = 0x00020F00; + WriteMEM(ddBarAddress+SB_EHCI_BAR_REGC0, AccWidthUint32, &ddVar); + //RPR - IN AND OUT DATA PACKET FIFO THRESHOLD + //EHCI BAR 0xA4 //IN threshold bits[7:0]=0x40 //OUT threshold bits[23:16]=0x40 + RWMEM(ddBarAddress+SB_EHCI_BAR_REGA4, AccWidthUint32, 0xFF00FF00, 0x00400040); + //RPR - EHCI dynamic clock gating feature + //EHCI_BAR 0xBC Bit[12] = 0, For normal operation, the clock gating feature must be disabled. + // Disables HS uFrame babble detection for erratum: EHCI_EOR + 9Ch [11] = 1 + RWMEM(ddBarAddress+SB_EHCI_BAR_REGBC, AccWidthUint16, ~(UINT32)(BIT12+BIT11), BIT11); + } + + ReadPCI((USB2_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG10, AccWidthUint32, &ddBarAddress);//Get BAR address + if ( (ddBarAddress != -1) && (ddBarAddress != 0) ){ + //Enable Memory access + RWPCI((USB2_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG04, AccWidthUint8, 0, BIT1); + //USB Common PHY CAL & Control Register setting + ddVar = 0x00020F00; + WriteMEM(ddBarAddress+SB_EHCI_BAR_REGC0, AccWidthUint32, &ddVar); + //RPR - IN AND OUT DATA PACKET FIFO THRESHOLD + //EHCI BAR 0xA4 //IN threshold bits[7:0]=0x40 //OUT threshold bits[23:16]=0x40 + RWMEM(ddBarAddress+SB_EHCI_BAR_REGA4, AccWidthUint32, 0xFF00FF00, 0x00400040); + //RPR - EHCI dynamic clock gating feature + //EHCI_BAR 0xBC Bit[12] = 0, For normal operation, the clock gating feature must be disabled. + // Disables HS uFrame babble detection for erratum: EHCI_EOR + 9Ch [11] = 1 + RWMEM(ddBarAddress+SB_EHCI_BAR_REGBC, AccWidthUint16, ~(UINT32)(BIT12+BIT11), BIT11); + } + + if (pConfig->UsbPhyPowerDown) + RWPMIO(SB_PMIO_REG65, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT0, BIT0); + else + RWPMIO(SB_PMIO_REG65, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT0, 0); + + // Disable the MSI capability of USB host controllers + RWPCI((USB1_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG40+1, AccWidthUint8 | S3_SAVE, 0xFF, BIT1+BIT0); + RWPCI((USB2_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG40+1, AccWidthUint8 | S3_SAVE, 0xFF, BIT1+BIT0); + RWPCI((USB3_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG40+1, AccWidthUint8 | S3_SAVE, 0xFF, BIT0); + + //RPR recommended setting "EHCI Advance Asynchronous Enhancement DISABLE" + //Set EHCI_pci_configx50[28]='1' to disable the advance async enhancement feature to avoid the bug found in Linux. + //Set EHCI_pci_configx50[6]='1' to disable EHCI MSI support + //RPR recommended setting "EHCI Async Park Mode" + //Set EHCI_pci_configx50[23]='1' to disable "EHCI Async Park Mode support" + // RPR recommended setting "EHCI Advance PHY Power Savings" + // Set EHCI_pci_configx50[31]='1' if SB700 A12 & above + // Fix for EHCI controller driver yellow sign issue under device manager + // when used in conjunction with HSET tool driver. EHCI PCI config 0x50[20]=1 + RWPCI((USB1_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG50, AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, BIT31+BIT28+BIT23+BIT20+BIT6); + RWPCI((USB2_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG50, AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, BIT31+BIT28+BIT23+BIT20+BIT6); + + //RPR recommended setting to, enable fix to cover the corner case S3 wake up issue from some USB 1.1 devices + //OHCI 0_PCI_Config 0x50[16] = 1 + RWPCI((USB1_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG50+2, AccWidthUint8 | S3_SAVE, 0xFF, BIT0); + RWPCI((USB2_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG50+2, AccWidthUint8 | S3_SAVE, 0xFF, BIT0); + RWPCI((USB3_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG50+2, AccWidthUint8 | S3_SAVE, 0xFF, BIT0); + + if (getRevisionID() >= SB700_A14){ + RWPCI((USB1_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG50, AccWidthUint32 | S3_SAVE, ~(UINT32)(BIT28), BIT8+BIT7+BIT4+BIT3); + RWPCI((USB2_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG50, AccWidthUint32 | S3_SAVE, ~(UINT32)(BIT28), BIT8+BIT7+BIT4+BIT3); + + RWPCI((USB1_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, BIT26+BIT25+BIT17); + RWPCI((USB2_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, BIT26+BIT25+BIT17); + RWPCI((USB3_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, BIT26+BIT25); + } + + if (getRevisionID() >= SB700_A15) { + //USB PID Error checking + RWPCI((USB1_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG50+1, AccWidthUint8 | S3_SAVE, 0xFF, BIT1); + RWPCI((USB2_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG50+1, AccWidthUint8 | S3_SAVE, 0xFF, BIT1); + } + + // RPR 6.25 - Optionally disable OHCI isochronous out prefetch + if (pConfig->OhciIsoOutPrefetchDis) { + RWPCI((USB1_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint16 | S3_SAVE, ~(UINT32)(BIT9 + BIT8), 0); + RWPCI((USB2_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint16 | S3_SAVE, ~(UINT32)(BIT9 + BIT8), 0); + RWPCI((USB3_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint16 | S3_SAVE, ~(UINT32)(BIT9 + BIT8), 0); + } + + if ( pConfig->EhciDataCacheDis ) { + // Disable Async Data Cache, EHCI_pci_configx50[26]='1' + RWPCI ((USB1_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG50, AccWidthUint32 | S3_SAVE, ~(UINT32)BIT26, BIT26); + RWPCI ((USB2_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG50, AccWidthUint32 | S3_SAVE, ~(UINT32)BIT26, BIT26); + } +} + + +void usbInitMidPost(AMDSBCFG* pConfig){ + if (pConfig->UsbOhciLegacyEmulation == 0){ + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG60+2, AccWidthUint8 | S3_SAVE, 0xFF, BIT1+BIT0); + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG64+3, AccWidthUint8 | S3_SAVE, 0xFF, BIT7); + } + else{ + programOhciMmioForEmulation(); + } +} + + +void programOhciMmioForEmulation(void){ + UINT32 ddBarAddress; + + ReadPCI((USB1_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG10, AccWidthUint32, &ddBarAddress);//Get BAR address + ddBarAddress &= 0xFFFFF000; + if ( (ddBarAddress != 0xFFFFF000) && (ddBarAddress != 0) ){ + //Enable Memory access + RWPCI((USB1_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG04, AccWidthUint8, 0, BIT1); + RWMEM(ddBarAddress+SB_OHCI_BAR_REG160, AccWidthUint32, 0, 0); + } + + ReadPCI((USB2_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG10, AccWidthUint32, &ddBarAddress);//Get BAR address + ddBarAddress &= 0xFFFFF000; + if ( (ddBarAddress != 0xFFFFF000) && (ddBarAddress != 0) ){ + //Enable Memory access + RWPCI((USB2_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG04, AccWidthUint8, 0, BIT1); + RWMEM(ddBarAddress+SB_OHCI_BAR_REG160, AccWidthUint32, 0, 0); + } + + ReadPCI((USB3_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG10, AccWidthUint32, &ddBarAddress);//Get BAR address + if ( (ddBarAddress != 0xFFFFF000) && (ddBarAddress != 0) ){ + //Enable Memory access + RWPCI((USB3_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG04, AccWidthUint8, 0, BIT1); + RWMEM(ddBarAddress+SB_OHCI_BAR_REG160, AccWidthUint32, 0, 0); + } +} diff --git a/src/vendorcode/amd/cimx/sb700/sbAMDLIB.h b/src/vendorcode/amd/cimx/sb700/sbAMDLIB.h new file mode 100644 index 0000000..e8f6b38 --- /dev/null +++ b/src/vendorcode/amd/cimx/sb700/sbAMDLIB.h @@ -0,0 +1,196 @@ +/*;******************************************************************************** +; +; Copyright (C) 2012 Advanced Micro Devices, Inc. +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; * Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; * Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution. +; * Neither the name of Advanced Micro Devices, Inc. nor the names of +; its contributors may be used to endorse or promote products derived +; from this software without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;*********************************************************************************/ + +#ifndef _AMD_AMDLIB_H_ +#define _AMD_AMDLIB_H_ + +typedef CHAR8 *va_list; +#ifndef _INTSIZEOF + #define _INTSIZEOF(n)( (sizeof(n) + sizeof(UINTN) - 1) & ~(sizeof(UINTN) - 1) ) +#endif + +// Also support coding convention rules for var arg macros +#ifndef va_start +#define va_start(ap,v) ( ap = (va_list)&(v) + _INTSIZEOF(v) ) +#endif +#define va_arg(ap,t) ( *(t *)((ap += _INTSIZEOF(t)) - _INTSIZEOF(t)) ) +#define va_end(ap) ( ap = (va_list)0 ) + +#ifndef CIMx_DEBUG + #define CIMx_DEBUG 0 +#endif + + +#pragma pack(push,1) + +#define IMAGE_ALIGN 32*1024 +#define NUM_IMAGE_LOCATION 32 + +//Entry Point Call +typedef void (*CIM_IMAGE_ENTRY)(void* pConfig); + +//Hook Call + +typedef struct _Reg8Mask +{ + UINT8 bRegIndex; + UINT8 bANDMask; + UINT8 bORMask; +}REG8MASK; + + +typedef struct _CIMFILEHEADER{ + UINT32 AtiLogo; + UINT32 EntryPoint; + UINT32 ModuleLogo; + UINT32 ImageSize; + UINT16 Version; + UINT8 CheckSum; + UINT8 Reserved1; + UINT32 Reserved2; +}CIMFILEHEADER; + +typedef struct _CPUID_DATA{ + UINT32 REG_EAX; + UINT32 REG_EBX; + UINT32 REG_ECX; + UINT32 REG_EDX; +}CPUID_DATA; + +#ifndef BIT0 + #define BIT0 (1 << 0) +#endif +#ifndef BIT1 + #define BIT1 (1 << 1) +#endif +#ifndef BIT2 + #define BIT2 (1 << 2) +#endif +#ifndef BIT3 + #define BIT3 (1 << 3) +#endif +#ifndef BIT4 + #define BIT4 (1 << 4) +#endif +#ifndef BIT5 + #define BIT5 (1 << 5) +#endif +#ifndef BIT6 + #define BIT6 (1 << 6) +#endif +#ifndef BIT7 + #define BIT7 (1 << 7) +#endif +#ifndef BIT8 + #define BIT8 (1 << 8) +#endif +#ifndef BIT9 + #define BIT9 (1 << 9) +#endif +#ifndef BIT10 + #define BIT10 (1 << 10) +#endif +#ifndef BIT11 + #define BIT11 (1 << 11) +#endif +#ifndef BIT12 + #define BIT12 (1 << 12) +#endif +#ifndef BIT13 + #define BIT13 (1 << 13) +#endif +#ifndef BIT14 + #define BIT14 (1 << 14) +#endif +#ifndef BIT15 + #define BIT15 (1 << 15) +#endif +#ifndef BIT16 + #define BIT16 (1 << 16) +#endif +#ifndef BIT17 + #define BIT17 (1 << 17) +#endif +#ifndef BIT18 + #define BIT18 (1 << 18) +#endif +#ifndef BIT19 + #define BIT19 (1 << 19) +#endif +#ifndef BIT20 + #define BIT20 (1 << 20) +#endif +#ifndef BIT21 + #define BIT21 (1 << 21) +#endif +#ifndef BIT22 + #define BIT22 (1 << 22) +#endif +#ifndef BIT23 + #define BIT23 (1 << 23) +#endif +#ifndef BIT24 + #define BIT24 (1 << 24) +#endif +#ifndef BIT25 + #define BIT25 (1 << 25) +#endif +#ifndef BIT26 + #define BIT26 (1 << 26) +#endif +#ifndef BIT27 + #define BIT27 (1 << 27) +#endif +#ifndef BIT28 + #define BIT28 (1 << 28) +#endif +#ifndef BIT29 + #define BIT29 (1 << 29) +#endif +#ifndef BIT30 + #define BIT30 (1 << 30) +#endif +#ifndef BIT31 + #define BIT31 (1 << 31) +#endif + +#define PCI_ADDRESS(bus,dev,func,reg) \ +(UINT32) ( (((UINT32)bus) << 24) + (((UINT32)dev) << 19) + (((UINT32)func) << 16) + ((UINT32)reg) ) + +#pragma pack(pop) + +typedef enum { + AccWidthUint8 = 0, + AccWidthUint16, + AccWidthUint32, +} ACC_WIDTH; + +#define S3_SAVE 0x80 + +#endif //#ifndef _AMD_AMDLIB_H_

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coreboot February 2012