coreboot February 2012

coreboot@coreboot.org

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348 discussions

Patch merged into coreboot/master: f8df726 Inagua: Inagua GNB ddi lanes and pcie lanes config update
by gerrit＠coreboot.org 07 Feb '12

07 Feb '12

the following patch was just integrated into master: commit f8df7260201d3f579e552ba3239a94d70f631d0b Author: Kerry Sheh <shekairui(a)gmail.com> Date: Thu Jan 19 13:18:37 2012 +0800 Inagua: Inagua GNB ddi lanes and pcie lanes config update DDI lanes configuration update to make LVDS works. Pcie lanes configuration update to make MiniPcie slot 1 works. Change-Id: I40aaf28119b946b3a6383ceff7c734c9c3fd313e Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Build-Tested: build bot (Jenkins) at Thu Jan 19 06:02:58 2012, giving +1 Reviewed-By: Marc Jones <marcj303(a)gmail.com> at Tue Feb 7 00:24:24 2012, giving +2 See http://review.coreboot.org/544 for details. -gerrit

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Patch merged into coreboot/master: 18d1ed4 Inagua: devicetree.cb update
by gerrit＠coreboot.org 07 Feb '12

07 Feb '12

the following patch was just integrated into master: commit 18d1ed4c01ca2f9c8286347d9c8987d098072254 Author: Kerry Sheh <shekairui(a)gmail.com> Date: Thu Jan 19 13:18:37 2012 +0800 Inagua: devicetree.cb update Add the slots connection comments to devicetree.cb Change-Id: I3ccb2641c8d04a6a3c66ac11a562ba3b0dc0578a Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Build-Tested: build bot (Jenkins) at Thu Jan 19 06:13:25 2012, giving +1 See http://review.coreboot.org/545 for details. -gerrit

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Patch merged into coreboot/master: 7a36e53 Move SeaBIOS output out of coreboot source tree
by gerrit＠coreboot.org 07 Feb '12

07 Feb '12

the following patch was just integrated into master: commit 7a36e53735757b71befbeba7452666d1754e2463 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Sat Jan 21 10:34:22 2012 -0800 Move SeaBIOS output out of coreboot source tree Make sure SeaBIOS build files live under $(OUT) instead of in the source tree. Change-Id: I7d357773e32bc25ba7e7eae3fb6ddc31feb413ec Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Build-Tested: build bot (Jenkins) at Sat Jan 21 20:00:27 2012, giving +1 Reviewed-By: Marc Jones <marcj303(a)gmail.com> at Tue Feb 7 00:20:33 2012, giving +2 See http://review.coreboot.org/552 for details. -gerrit

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Patch merged into coreboot/master: d9c56fa libpayload: Fix EHCI driver
by gerrit＠coreboot.org 07 Feb '12

07 Feb '12

the following patch was just integrated into master: commit d9c56faebed52ad5c583c6337d5b01d2c09ed9bd Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Tue Jan 31 14:37:59 2012 +0100 libpayload: Fix EHCI driver When converting EHCI to not use bitfields, two offsets were converted incorrectly. Change-Id: I0bb4bad0eee42e54ad4fd53d6c35b107e227c41a Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> Build-Tested: build bot (Jenkins) at Tue Jan 31 16:50:48 2012, giving +1 Reviewed-By: Marc Jones <marcj303(a)gmail.com> at Tue Feb 7 00:16:02 2012, giving +2 See http://review.coreboot.org/593 for details. -gerrit

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Patch merged into coreboot/master: 60668d2 Add OPROM mapping support to coreboot
by gerrit＠coreboot.org 07 Feb '12

07 Feb '12

the following patch was just integrated into master: commit 60668d28abfcf877f1e0592178beb2646efb47ee Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Jan 23 14:17:52 2012 -0800 Add OPROM mapping support to coreboot This allows to add a PCI ID mapping function for option roms so that the same option rom can be used for a series of devices / PCI IDs. Intel and AMD often use the same option rom for a number of PCI devices with differend IDs. A function to implement such a mapping could look like this (or anything else appropriate): /* some vga option roms are used for several chipsets but they only have one * PCI ID in their header. If we encounter such an option rom, we need to do * the mapping ourselfes */ u32 map_oprom_vendev(u32 vendev) { u32 new_vendev=vendev; switch(vendev) { case 0xa0118086: new_vendev=0xa0018086; break; } return new_vendev; } Change-Id: I1be7fe113b895075d43ea48fe706b039cef136d2 Build-Tested: build bot (Jenkins) at Mon Jan 23 23:34:49 2012, giving +1 Reviewed-By: Marc Jones <marcj303(a)gmail.com> at Tue Feb 7 00:09:36 2012, giving +2 See http://review.coreboot.org/573 for details. -gerrit

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Patch merged into coreboot/master: 5254c95 Inagua: Synchronize AMD/inagua mainboard.
by gerrit＠coreboot.org 07 Feb '12

07 Feb '12

the following patch was just integrated into master: commit 5254c959694e2fae803b1d44f49dd277cc74f81f Author: Kerry Sheh <shekairui(a)gmail.com> Date: Thu Jan 19 13:18:36 2012 +0800 Inagua: Synchronize AMD/inagua mainboard. AMD/persimmon mainboard code is derived from AMD/inagua mainbard. Persimmom update a lot in the last few month, sync these modification to inagua. Change-Id: Ia038e5a2b9550fe81bb075f31e30b98354758e9e Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Build-Tested: build bot (Jenkins) at Thu Jan 19 06:32:45 2012, giving +1 Reviewed-By: Marc Jones <marcj303(a)gmail.com> at Tue Feb 7 00:06:07 2012, giving +2 See http://review.coreboot.org/542 for details. -gerrit

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Re: [coreboot] FILO can not be built!!
by Peter Stuge 06 Feb '12

06 Feb '12

ali hagigat wrote: > I received filo by the Coreboot site, and libpayload was made > successfully but making filo stops with the following error: > > /root/bios/coreboot/payloads/filo> make > Found Libpayload > /root/bios/coreboot/payloads/filo/build/libpayload/lib/libpayload.a. > CC build/i386/context.o > CC build/i386/segment.o > CC build/i386/timer.o > CC build/i386/sys_info.o > CC build/i386/linux_load.o > /root/bios/coreboot/payloads/filo/i386/linux_load.c:752:5: error: > expected identifier or '(' before numeric constant > make: *** [/root/bios/coreboot/payloads/filo/build/i386/linux_load.o] Error 1 In open source software, when you encounter an error, you typically get to fix it yourself. At the very least, you should do everyone the courtesy of actually looking at the code and analyzing the problem on your own. //Peter

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FILO can not be built!!
by ali hagigat 06 Feb '12

06 Feb '12

I received filo by the Coreboot site, and libpayload was made successfully but making filo stops with the following error: /root/bios/coreboot/payloads/filo> make Found Libpayload /root/bios/coreboot/payloads/filo/build/libpayload/lib/libpayload.a. CC build/i386/context.o CC build/i386/segment.o CC build/i386/timer.o CC build/i386/sys_info.o CC build/i386/linux_load.o /root/bios/coreboot/payloads/filo/i386/linux_load.c:752:5: error: expected identifier or '(' before numeric constant make: *** [/root/bios/coreboot/payloads/filo/build/i386/linux_load.o] Error 1

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Re: [coreboot] How to port core boot
by Peter Stuge 06 Feb '12

06 Feb '12

ali hagigat wrote: > I can verify that by the assembly code i have. writing to any > memory location and reading that. Also I tested it by ram_check() > in Coreboot. Both are correct. This is not a very good memory test. Try running memtest86. It should be possible as long as you have set up serial correctly. //Peter

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Re: [coreboot] How to port core boot
by Peter Stuge 06 Feb '12

06 Feb '12

ali hagigat wrote: > I have developed the assembly code by myself and I am sure that it is > OK as I have written a simple code in assembly which initializes RAM, > serial port and hard disk. How did you verify that your code works? //Peter

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coreboot February 2012