coreboot February 2012

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Patch set updated for coreboot: 9bf1cc6 AGESA F15: AGESA family15 model 00-0fh northbridge wrapper
by Kerry Sheh 07 Feb '12

07 Feb '12

Kerry Sheh (shekairui(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/556 -gerrit commit 9bf1cc623520b43d95ff7e55770fa30590f3b953 Author: Kerry Sheh <shekairui(a)gmail.com> Date: Tue Feb 7 20:31:40 2012 +0800 AGESA F15: AGESA family15 model 00-0fh northbridge wrapper Change-Id: I87c4d47f19161c604b0285102bb3809c8337375a Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> --- src/northbridge/amd/agesa/Kconfig | 3 +- src/northbridge/amd/agesa/Makefile.inc | 3 +- src/northbridge/amd/agesa/family15/Kconfig | 49 + src/northbridge/amd/agesa/family15/Makefile.inc | 20 + src/northbridge/amd/agesa/family15/bootblock.c | 25 + src/northbridge/amd/agesa/family15/chip.h | 24 + src/northbridge/amd/agesa/family15/northbridge.c | 1168 ++++++++++++++++++++ src/northbridge/amd/agesa/family15/northbridge.h | 26 + .../amd/agesa/family15/root_complex/Kconfig | 2 + .../amd/agesa/family15/root_complex/chip.h | 24 + 10 files changed, 1342 insertions(+), 2 deletions(-) diff --git a/src/northbridge/amd/agesa/Kconfig b/src/northbridge/amd/agesa/Kconfig index 3bcb0bb..2ed9fd5 100644 --- a/src/northbridge/amd/agesa/Kconfig +++ b/src/northbridge/amd/agesa/Kconfig @@ -1,7 +1,7 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. +# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -24,4 +24,5 @@ config CONSOLE_VGA_MULTI source src/northbridge/amd/agesa/family10/Kconfig source src/northbridge/amd/agesa/family12/Kconfig source src/northbridge/amd/agesa/family14/Kconfig +source src/northbridge/amd/agesa/family15/Kconfig diff --git a/src/northbridge/amd/agesa/Makefile.inc b/src/northbridge/amd/agesa/Makefile.inc index 1da8f60..eef1cd3 100644 --- a/src/northbridge/amd/agesa/Makefile.inc +++ b/src/northbridge/amd/agesa/Makefile.inc @@ -1,7 +1,7 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. +# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -19,3 +19,4 @@ subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10) += family10 subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY12) += family12 subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY14) += family14 +subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15) += family15 diff --git a/src/northbridge/amd/agesa/family15/Kconfig b/src/northbridge/amd/agesa/family15/Kconfig new file mode 100644 index 0000000..52f7a1e --- /dev/null +++ b/src/northbridge/amd/agesa/family15/Kconfig @@ -0,0 +1,49 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2009 coresystems GmbH +## Copyright (C) 2012 Advanced Micro Devices, Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## +config NORTHBRIDGE_AMD_AGESA_FAMILY15 + bool + select HAVE_DEBUG_RAM_SETUP + select HAVE_DEBUG_SMBUS + select HYPERTRANSPORT_PLUGIN_SUPPORT + select MMCONF_SUPPORT + select NORTHBRIDGE_AMD_AGESA_FAMILY15_ROOT_COMPLEX + +if NORTHBRIDGE_AMD_AGESA_FAMILY15 +config HT3_SUPPORT + bool + default y +config HW_MEM_HOLE_SIZEK + hex + default 0x100000 +config HW_MEM_HOLE_SIZE_AUTO_INC + bool + default n +config MMCONF_BASE_ADDRESS + hex + default 0xF8000000 +config MMCONF_BUS_NUMBER + int + default 64 +config BOOTBLOCK_NORTHBRIDGE_INIT + string + default "northbridge/amd/agesa/family15/bootblock.c" +endif #NORTHBRIDGE_AMD_AGESA_FAMILY15 + +source "src/northbridge/amd/agesa/family15/root_complex/Kconfig" diff --git a/src/northbridge/amd/agesa/family15/Makefile.inc b/src/northbridge/amd/agesa/family15/Makefile.inc new file mode 100644 index 0000000..255fe10 --- /dev/null +++ b/src/northbridge/amd/agesa/family15/Makefile.inc @@ -0,0 +1,20 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +driver-y += northbridge.c diff --git a/src/northbridge/amd/agesa/family15/bootblock.c b/src/northbridge/amd/agesa/family15/bootblock.c new file mode 100644 index 0000000..fc62c3e --- /dev/null +++ b/src/northbridge/amd/agesa/family15/bootblock.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <device/pci_def.h> + +static void bootblock_northbridge_init(void) { +} diff --git a/src/northbridge/amd/agesa/family15/chip.h b/src/northbridge/amd/agesa/family15/chip.h new file mode 100644 index 0000000..cec1fc4 --- /dev/null +++ b/src/northbridge/amd/agesa/family15/chip.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +struct northbridge_amd_agesa_family15_config +{ +}; + +extern struct chip_operations northbridge_amd_agesa_family15_ops; diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c new file mode 100644 index 0000000..b0fc91d --- /dev/null +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -0,0 +1,1168 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <arch/io.h> +#include <stdint.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/hypertransport.h> +#include <stdlib.h> +#include <string.h> +#include <bitops.h> +#include <cpu/cpu.h> + +#include <cpu/x86/lapic.h> + +#include <Porting.h> +#include <AGESA.h> +#include <Options.h> +#include <Topology.h> +#include <cpu/amd/amdfam15.h> +#include <cpuRegisters.h> +#include "agesawrapper.h" +#include "root_complex/chip.h" +#include "northbridge.h" +#include "chip.h" + +#define MAX_NODE_NUMS (MAX_NODES * MAX_DIES) + +#if (defined CONFIG_EXT_CONF_SUPPORT) && CONFIG_EXT_CONF_SUPPORT == 1 +#error CONFIG_EXT_CONF_SUPPORT == 1 not support anymore! +#endif + +typedef struct dram_base_mask { + u32 base; //[47:27] at [28:8] + u32 mask; //[47:27] at [28:8] and enable at bit 0 +} dram_base_mask_t; + +static unsigned node_nums; +static unsigned sblink; +static device_t __f0_dev[MAX_NODE_NUMS]; +static device_t __f1_dev[MAX_NODE_NUMS]; +static device_t __f2_dev[MAX_NODE_NUMS]; +static device_t __f4_dev[MAX_NODE_NUMS]; +static unsigned fx_devs = 0; + + +static dram_base_mask_t get_dram_base_mask(u32 nodeid) +{ + device_t dev; + dram_base_mask_t d; + dev = __f1_dev[0]; + u32 temp; + temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16] + d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out DramMask [26:24] too + temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] + d.mask |= temp<<21; + temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16] + d.mask |= (temp & 1); // enable bit + d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too + temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] + d.base |= temp<<21; + return d; +} + +static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, + u32 io_min, u32 io_max) +{ + u32 i; + u32 tempreg; + /* io range allocation */ + tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit + for (i=0; i<node_nums; i++) + pci_write_config32(__f1_dev[i], reg+4, tempreg); + tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? +#if 0 + // FIXME: can we use VGA reg instead? + if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { + printk(BIOS_SPEW, "%s, enabling legacy VGA IO forwarding for %s link %s\n", + __func__, dev_path(dev), link); + tempreg |= PCI_IO_BASE_VGA_EN; + } + if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_NO_ISA) { + tempreg |= PCI_IO_BASE_NO_ISA; + } +#endif + for (i=0; i<node_nums; i++) + pci_write_config32(__f1_dev[i], reg, tempreg); +} + +static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmio_min, u32 mmio_max, u32 nodes) +{ + u32 i; + u32 tempreg; + /* io range allocation */ + tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit + for (i=0; i<nodes; i++) + pci_write_config32(__f1_dev[i], reg+4, tempreg); + tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); + for (i=0; i<node_nums; i++) + pci_write_config32(__f1_dev[i], reg, tempreg); +} + +static device_t get_node_pci(u32 nodeid, u32 fn) +{ +#if MAX_NODE_NUMS == 64 + if (nodeid < 32) { + return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn)); + } else { + return dev_find_slot(CONFIG_CBB-1, PCI_DEVFN(CONFIG_CDB + nodeid - 32, fn)); + } +#else + return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn)); +#endif +} + +static void get_fx_devs(void) +{ + int i; + for (i = 0; i < MAX_NODE_NUMS; i++) { + __f0_dev[i] = get_node_pci(i, 0); + __f1_dev[i] = get_node_pci(i, 1); + __f2_dev[i] = get_node_pci(i, 2); + __f4_dev[i] = get_node_pci(i, 4); + if (__f0_dev[i] != NULL && __f1_dev[i] != NULL) + fx_devs = i+1; + } + if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) { + die("Cannot find 0:0x18.[0|1]\n"); + } + printk(BIOS_DEBUG, "fx_devs=0x%x\n", fx_devs); +} + +static u32 f1_read_config32(unsigned reg) +{ + if (fx_devs == 0) + get_fx_devs(); + return pci_read_config32(__f1_dev[0], reg); +} + +static void f1_write_config32(unsigned reg, u32 value) +{ + int i; + if (fx_devs == 0) + get_fx_devs(); + for(i = 0; i < fx_devs; i++) { + device_t dev; + dev = __f1_dev[i]; + if (dev && dev->enabled) { + pci_write_config32(dev, reg, value); + } + } +} + +static u32 amdfam15_nodeid(device_t dev) +{ +#if MAX_NODE_NUMS == 64 + unsigned busn; + busn = dev->bus->secondary; + if (busn != CONFIG_CBB) { + return (dev->path.pci.devfn >> 3) - CONFIG_CDB + 32; + } else { + return (dev->path.pci.devfn >> 3) - CONFIG_CDB; + } + +#else + return (dev->path.pci.devfn >> 3) - CONFIG_CDB; +#endif +} + +static void set_vga_enable_reg(u32 nodeid, u32 linkn) +{ + u32 val; + + val = 1 | (nodeid<<4) | (linkn<<12); + /* it will routing + * (1)mmio 0xa0000:0xbffff + * (2)io 0x3b0:0x3bb, 0x3c0:0x3df + */ + f1_write_config32(0xf4, val); + +} + +/** + * @return + * @retval 2 resoure not exist, usable + * @retval 0 resource exist, not usable + * @retval 1 resource exist, resource has been allocated before + */ +static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, + unsigned goal_link) +{ + struct resource *res; + unsigned nodeid, link = 0; + int result; + res = 0; + for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { + device_t dev; + dev = __f0_dev[nodeid]; + if (!dev) + continue; + for (link = 0; !res && (link < 8); link++) { + res = probe_resource(dev, IOINDEX(0x1000 + reg, link)); + } + } + result = 2; + if (res) { + result = 0; + if ((goal_link == (link - 1)) && + (goal_nodeid == (nodeid - 1)) && + (res->flags <= 1)) { + result = 1; + } + } + return result; +} + +static struct resource *amdfam15_find_iopair(device_t dev, unsigned nodeid, unsigned link) +{ + struct resource *resource; + u32 free_reg, reg; + resource = 0; + free_reg = 0; + for (reg = 0xc0; reg <= 0xd8; reg += 0x8) { + int result; + result = reg_useable(reg, dev, nodeid, link); + if (result == 1) { + /* I have been allocated this one */ + break; + } + else if (result > 1) { + /* I have a free register pair */ + free_reg = reg; + } + } + if (reg > 0xd8) { + reg = free_reg; // if no free, the free_reg still be 0 + } + + resource = new_resource(dev, IOINDEX(0x1000 + reg, link)); + + return resource; +} + +static struct resource *amdfam15_find_mempair(device_t dev, u32 nodeid, u32 link) +{ + struct resource *resource; + u32 free_reg, reg; + resource = 0; + free_reg = 0; + for (reg = 0x80; reg <= 0xb8; reg += 0x8) { + int result; + result = reg_useable(reg, dev, nodeid, link); + if (result == 1) { + /* I have been allocated this one */ + break; + } + else if (result > 1) { + /* I have a free register pair */ + free_reg = reg; + } + } + if (reg > 0xb8) { + reg = free_reg; + } + + resource = new_resource(dev, IOINDEX(0x1000 + reg, link)); + return resource; +} + + +static void amdfam15_link_read_bases(device_t dev, u32 nodeid, u32 link) +{ + struct resource *resource; + + /* Initialize the io space constraints on the current bus */ + resource = amdfam15_find_iopair(dev, nodeid, link); + if (resource) { + u32 align; + align = log2(HT_IO_HOST_ALIGN); + resource->base = 0; + resource->size = 0; + resource->align = align; + resource->gran = align; + resource->limit = 0xffffUL; + resource->flags = IORESOURCE_IO | IORESOURCE_BRIDGE; + } + + /* Initialize the prefetchable memory constraints on the current bus */ + resource = amdfam15_find_mempair(dev, nodeid, link); + if (resource) { + resource->base = 0; + resource->size = 0; + resource->align = log2(HT_MEM_HOST_ALIGN); + resource->gran = log2(HT_MEM_HOST_ALIGN); + resource->limit = 0xffffffffffULL; + resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; + resource->flags |= IORESOURCE_BRIDGE; + } + + + /* Initialize the memory constraints on the current bus */ + resource = amdfam15_find_mempair(dev, nodeid, link); + if (resource) { + resource->base = 0; + resource->size = 0; + resource->align = log2(HT_MEM_HOST_ALIGN); + resource->gran = log2(HT_MEM_HOST_ALIGN); + resource->limit = 0xffffffffffULL; + resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE; + } + +} + + +static void read_resources(device_t dev) +{ + u32 nodeid; + struct bus *link; + + nodeid = amdfam15_nodeid(dev); + for (link = dev->link_list; link; link = link->next) { + if (link->children) { + amdfam15_link_read_bases(dev, nodeid, link->link_num); + } + } +} + + +static void set_resource(device_t dev, struct resource *resource, u32 nodeid) +{ + resource_t rbase, rend; + unsigned reg, link_num; + char buf[50]; + + + /* Make certain the resource has actually been set */ + if (!(resource->flags & IORESOURCE_ASSIGNED)) { + return; + } + + /* If I have already stored this resource don't worry about it */ + if (resource->flags & IORESOURCE_STORED) { + return; + } + + /* Only handle PCI memory and IO resources */ + if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO))) + return; + + /* Ensure I am actually looking at a resource of function 1 */ + if ((resource->index & 0xffff) < 0x1000) { + return; + } + /* Get the base address */ + rbase = resource->base; + + /* Get the limit (rounded up) */ + rend = resource_end(resource); + + /* Get the register and link */ + reg = resource->index & 0xfff; // 4k + link_num = IOINDEX_LINK(resource->index); + + if (resource->flags & IORESOURCE_IO) { + set_io_addr_reg(dev, nodeid, link_num, reg, rbase>>8, rend>>8); + } + else if (resource->flags & IORESOURCE_MEM) { + set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, node_nums) ;// [39:8] + } + resource->flags |= IORESOURCE_STORED; + sprintf(buf, " <node %x link %x>", + nodeid, link_num); + report_resource_stored(dev, resource, buf); +} + +/** + * I tried to reuse the resource allocation code in set_resource() + * but it is too difficult to deal with the resource allocation magic. + */ + +static void create_vga_resource(device_t dev, unsigned nodeid) +{ + struct bus *link; + + + /* find out which link the VGA card is connected, + * we only deal with the 'first' vga card */ + for (link = dev->link_list; link; link = link->next) { + if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { +#if CONFIG_MULTIPLE_VGA_ADAPTERS == 1 + extern device_t vga_pri; // the primary vga device, defined in device.c + printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, + link->secondary,link->subordinate); + /* We need to make sure the vga_pri is under the link */ + if((vga_pri->bus->secondary >= link->secondary ) && + (vga_pri->bus->secondary <= link->subordinate ) + ) +#endif + break; + } + } + + /* no VGA card installed */ + if (link == NULL) + return; + + printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, sblink); + set_vga_enable_reg(nodeid, sblink); +} + + +static void set_resources(device_t dev) +{ + unsigned nodeid; + struct bus *bus; + struct resource *res; + + /* Find the nodeid */ + nodeid = amdfam15_nodeid(dev); + + create_vga_resource(dev, nodeid); //TODO: do we need this? + + /* Set each resource we have found */ + for (res = dev->resource_list; res; res = res->next) { + set_resource(dev, res, nodeid); + } + + for (bus = dev->link_list; bus; bus = bus->next) { + if (bus->children) { + assign_resources(bus); + } + } +} + +static void northbridge_init(struct device *dev) +{ +} + +static unsigned scan_chains(device_t dev, unsigned max) +{ + unsigned nodeid; + struct bus *link; + device_t io_hub = NULL; + u32 next_unitid = 0x18; + nodeid = amdfam15_nodeid(dev); + if (nodeid == 0) { + for (link = dev->link_list; link; link = link->next) { + //if (link->link_num == sblink) { /* devicetree put IO Hub on link_lsit[sblink] */ + if (link->link_num == 0) { /* devicetree put IO Hub on link_lsit[0] */ + io_hub = link->children; + if (!io_hub || !io_hub->enabled) { + die("I can't find the IO Hub, or IO Hub not enabled, please check the device tree.\n"); + } + /* Now that nothing is overlapping it is safe to scan the children. */ + max = pci_scan_bus(link, 0x00, ((next_unitid - 1) << 3) | 7, 0); + } + } + } + return max; +} + +static struct device_operations northbridge_operations = { + .read_resources = read_resources, + .set_resources = set_resources, + .enable_resources = pci_dev_enable_resources, + .init = northbridge_init, + .scan_bus = scan_chains, + .enable = 0, + .ops_pci = 0, +}; + +static const struct pci_driver family15_northbridge __pci_driver = { + .ops = &northbridge_operations, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_AMD_15H_MODEL_000F_NB_HT, +}; + +static const struct pci_driver family10_northbridge __pci_driver = { + .ops = &northbridge_operations, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_AMD_10H_NB_HT, +}; + +struct chip_operations northbridge_amd_agesa_family15_ops = { + CHIP_NAME("AMD FAM15 Northbridge") + .enable_dev = 0, +}; + +static void domain_read_resources(device_t dev) +{ + unsigned reg; + + + /* Find the already assigned resource pairs */ + get_fx_devs(); + for (reg = 0x80; reg <= 0xd8; reg+= 0x08) { + u32 base, limit; + base = f1_read_config32(reg); + limit = f1_read_config32(reg + 0x04); + /* Is this register allocated? */ + if ((base & 3) != 0) { + unsigned nodeid, reg_link; + device_t reg_dev; + if (reg<0xc0) { // mmio + nodeid = (limit & 0xf) + (base&0x30); + } else { // io + nodeid = (limit & 0xf) + ((base>>4)&0x30); + } + reg_link = (limit >> 4) & 7; + reg_dev = __f0_dev[nodeid]; + if (reg_dev) { + /* Reserve the resource */ + struct resource *res; + res = new_resource(reg_dev, IOINDEX(0x1000 + reg, reg_link)); + if (res) { + res->flags = 1; + } + } + } + } + /* FIXME: do we need to check extend conf space? + I don't believe that much preset value */ + +#if CONFIG_PCI_64BIT_PREF_MEM == 0 + pci_domain_read_resources(dev); + + +#else + struct bus *link; + struct resource *resource; + for (link=dev->link_list; link; link = link->next) { + /* Initialize the system wide io space constraints */ + resource = new_resource(dev, 0|(link->link_num<<2)); + resource->base = 0x400; + resource->limit = 0xffffUL; + resource->flags = IORESOURCE_IO; + + /* Initialize the system wide prefetchable memory resources constraints */ + resource = new_resource(dev, 1|(link->link_num<<2)); + resource->limit = 0xfcffffffffULL; + resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; + + /* Initialize the system wide memory resources constraints */ + resource = new_resource(dev, 2|(link->link_num<<2)); + resource->limit = 0xfcffffffffULL; + resource->flags = IORESOURCE_MEM; + } +#endif +} + +static void domain_enable_resources(device_t dev) +{ + u32 val; + /* Must be called after PCI enumeration and resource allocation */ + printk(BIOS_DEBUG, "\nFam15 - domain_enable_resources: AmdInitMid.\n"); + val = agesawrapper_amdinitmid(); + if (val) { + printk(BIOS_DEBUG, "agesawrapper_amdinitmid failed: %x \n", val); + } + printk(BIOS_DEBUG, " ader - leaving domain_enable_resources.\n"); +} + + +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 +struct hw_mem_hole_info { + unsigned hole_startk; + int node_id; +}; +static struct hw_mem_hole_info get_hw_mem_hole_info(void) +{ + struct hw_mem_hole_info mem_hole; + int i; + mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK; + mem_hole.node_id = -1; + for (i = 0; i < node_nums; i++) { + dram_base_mask_t d; + u32 hole; + d = get_dram_base_mask(i); + if (!(d.mask & 1)) continue; // no memory on this node + hole = pci_read_config32(__f1_dev[i], 0xf0); + if (hole & 1) { // we find the hole + mem_hole.hole_startk = (hole & (0xff<<24)) >> 10; + mem_hole.node_id = i; // record the node No with hole + break; // only one hole + } + } + //We need to double check if there is speical set on base reg and limit reg are not continous instead of hole, it will find out it's hole_startk + if (mem_hole.node_id == -1) { + resource_t limitk_pri = 0; + for (i=0; i<node_nums; i++) { + dram_base_mask_t d; + resource_t base_k, limit_k; + d = get_dram_base_mask(i); + if (!(d.base & 1)) continue; + base_k = ((resource_t)(d.base & 0x1fffff00)) <<9; + if (base_k > 4 *1024 * 1024) break; // don't need to go to check + if (limitk_pri != base_k) { // we find the hole + mem_hole.hole_startk = (unsigned)limitk_pri; // must beblow 4G + mem_hole.node_id = i; + break; //only one hole + } + limit_k = ((resource_t)((d.mask + 0x00000100) & 0x1fffff00)) << 9; + limitk_pri = limit_k; + } + } + return mem_hole; +} +#endif +#if CONFIG_WRITE_HIGH_TABLES==1 +#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB +extern uint64_t high_tables_base, high_tables_size; +#endif +#if CONFIG_GFXUMA == 1 +extern uint64_t uma_memory_base, uma_memory_size; +static void add_uma_resource(struct device *dev, int index) +{ + struct resource *resource; + + printk(BIOS_DEBUG, "Adding UMA memory area\n"); + resource = new_resource(dev, index); + resource->base = (resource_t) uma_memory_base; + resource->size = (resource_t) uma_memory_size; + resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | + IORESOURCE_FIXED | IORESOURCE_STORED | + IORESOURCE_ASSIGNED; +} +#endif + +static void domain_set_resources(device_t dev) +{ +#if CONFIG_PCI_64BIT_PREF_MEM == 1 + struct resource *io, *mem1, *mem2; + struct resource *res; +#endif + unsigned long mmio_basek; + u32 pci_tolm; + int i, idx; + struct bus *link; +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 + struct hw_mem_hole_info mem_hole; + u32 reset_memhole = 1; +#endif + +#if CONFIG_PCI_64BIT_PREF_MEM == 1 + + for (link = dev->link_list; link; link = link->next) { + /* Now reallocate the pci resources memory with the + * highest addresses I can manage. + */ + mem1 = find_resource(dev, 1|(link->link_num<<2)); + mem2 = find_resource(dev, 2|(link->link_num<<2)); + + printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", + mem1->base, mem1->limit, mem1->size, mem1->align); + printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", + mem2->base, mem2->limit, mem2->size, mem2->align); + + /* See if both resources have roughly the same limits */ + if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) || + ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff))) + { + /* If so place the one with the most stringent alignment first */ + if (mem2->align > mem1->align) { + struct resource *tmp; + tmp = mem1; + mem1 = mem2; + mem2 = tmp; + } + /* Now place the memory as high up as it will go */ + mem2->base = resource_max(mem2); + mem1->limit = mem2->base - 1; + mem1->base = resource_max(mem1); + } + else { + /* Place the resources as high up as they will go */ + mem2->base = resource_max(mem2); + mem1->base = resource_max(mem1); + } + + printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", + mem1->base, mem1->limit, mem1->size, mem1->align); + printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", + mem2->base, mem2->limit, mem2->size, mem2->align); + } + + for (res = &dev->resource_list; res; res = res->next) + { + res->flags |= IORESOURCE_ASSIGNED; + res->flags |= IORESOURCE_STORED; + report_resource_stored(dev, res, ""); + } +#endif + + pci_tolm = 0xffffffffUL; + for (link = dev->link_list; link; link = link->next) { + pci_tolm = find_pci_tolm(link); + } + + // FIXME handle interleaved nodes. If you fix this here, please fix + // amdk8, too. + mmio_basek = pci_tolm >> 10; + /* Round mmio_basek to something the processor can support */ + mmio_basek &= ~((1 << 6) -1); + + // FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M + // MMIO hole. If you fix this here, please fix amdk8, too. + /* Round the mmio hole to 64M */ + mmio_basek &= ~((64*1024) - 1); + +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 + /* if the hw mem hole is already set in raminit stage, here we will compare + * mmio_basek and hole_basek. if mmio_basek is bigger that hole_basek and will + * use hole_basek as mmio_basek and we don't need to reset hole. + * otherwise We reset the hole to the mmio_basek + */ + + mem_hole = get_hw_mem_hole_info(); + + // Use hole_basek as mmio_basek, and we don't need to reset hole anymore + if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) { + mmio_basek = mem_hole.hole_startk; + reset_memhole = 0; + } +#endif + + idx = 0x10; + for (i = 0; i < node_nums; i++) { + dram_base_mask_t d; + resource_t basek, limitk, sizek; // 4 1T + + d = get_dram_base_mask(i); + + if (!(d.mask & 1)) continue; + basek = ((resource_t)(d.base & 0x1fffff00)) << 9; // could overflow, we may lost 6 bit here + limitk = ((resource_t)((d.mask + 0x00000100) & 0x1fffff00)) << 9 ; + + sizek = limitk - basek; + + + /* see if we need a hole from 0xa0000 to 0xbffff */ + if ((basek < ((8*64)+(8*16))) && (sizek > ((8*64)+(16*16)))) { + ram_resource(dev, (idx | i), basek, ((8*64)+(8*16)) - basek); + idx += 0x10; + basek = (8*64)+(16*16); + sizek = limitk - ((8*64)+(16*16)); + + } + + //printk(BIOS_DEBUG, "node %d : mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); + + /* split the region to accomodate pci memory space */ + if ((basek < 4*1024*1024 ) && (limitk > mmio_basek)) { + if (basek <= mmio_basek) { + unsigned pre_sizek; + pre_sizek = mmio_basek - basek; + if (pre_sizek>0) { + ram_resource(dev, (idx | i), basek, pre_sizek); + idx += 0x10; + sizek -= pre_sizek; +#if CONFIG_WRITE_HIGH_TABLES==1 + if (high_tables_base==0) { + /* Leave some space for ACPI, PIRQ and MP tables */ +#if CONFIG_GFXUMA == 1 + high_tables_base = uma_memory_base - (HIGH_TABLES_SIZE * 1024); +#else + high_tables_base = (mmio_basek - HIGH_TABLES_SIZE) * 1024; +#endif + high_tables_size = HIGH_TABLES_SIZE * 1024; + printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", + HIGH_TABLES_SIZE, high_tables_base); + } +#endif + } + basek = mmio_basek; + } + if ((basek + sizek) <= 4*1024*1024) { + sizek = 0; + } + else { + basek = 4*1024*1024; + sizek -= (4*1024*1024 - mmio_basek); + } + } + +#if CONFIG_GFXUMA == 1 + /* Deduct uma memory before reporting because + * this is what the mtrr code expects */ + sizek -= uma_memory_size / 1024; +#endif + ram_resource(dev, (idx | i), basek, sizek); + idx += 0x10; +#if CONFIG_WRITE_HIGH_TABLES==1 + printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", + i, mmio_basek, basek, limitk); + if (high_tables_base==0) { + /* Leave some space for ACPI, PIRQ and MP tables */ +#if CONFIG_GFXUMA == 1 + high_tables_base = uma_memory_base - (HIGH_TABLES_SIZE * 1024); +#else + high_tables_base = (limitk - HIGH_TABLES_SIZE) * 1024; +#endif + high_tables_size = HIGH_TABLES_SIZE * 1024; + } +#endif + } + +#if CONFIG_GFXUMA == 1 + add_uma_resource(dev, 7); +#endif + + for(link = dev->link_list; link; link = link->next) { + if (link->children) { + assign_resources(link); + } + } +} + + +static struct device_operations pci_domain_ops = { + .read_resources = domain_read_resources, + .set_resources = domain_set_resources, + .enable_resources = domain_enable_resources, + .init = NULL, + .scan_bus = pci_domain_scan_bus, + +#if CONFIG_MMCONF_SUPPORT_DEFAULT + .ops_pci_bus = &pci_ops_mmconf, +#else + .ops_pci_bus = &pci_cf8_conf1, +#endif +}; + + +static void sysconf_init(device_t dev) // first node +{ + sblink = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1 + node_nums = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; //NodeCnt[2:0] +} + +static void add_more_links(device_t dev, unsigned total_links) +{ + struct bus *link, *last = NULL; + int link_num; + + for (link = dev->link_list; link; link = link->next) + last = link; + + if (last) { + int links = total_links - last->link_num; + link_num = last->link_num; + if (links > 0) { + link = malloc(links*sizeof(*link)); + if (!link) + die("Couldn't allocate more links!\n"); + memset(link, 0, links*sizeof(*link)); + last->next = link; + } + } + else { + link_num = -1; + link = malloc(total_links*sizeof(*link)); + memset(link, 0, total_links*sizeof(*link)); + dev->link_list = link; + } + + for (link_num = link_num + 1; link_num < total_links; link_num++) { + link->link_num = link_num; + link->dev = dev; + link->next = link + 1; + last = link; + link = link->next; + } + last->next = NULL; +} + +/* dummy read_resources */ +static void lapic_read_resources(device_t dev) +{ +} + +static struct device_operations lapic_ops = { + .read_resources = lapic_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = 0, + .scan_bus = 0, + .enable = 0, + .ops_pci = 0, +}; + +static u32 cpu_bus_scan(device_t dev, u32 max) +{ + struct bus *cpu_bus; + device_t dev_mc; +#if CONFIG_CBB + device_t pci_domain; +#endif + int i,j; + int coreid_bits; + int core_max = 0; + unsigned ApicIdCoreIdSize; + unsigned core_nums; + int siblings = 0; + unsigned int family; + +#if CONFIG_CBB + dev_mc = dev_find_slot(0, PCI_DEVFN(CONFIG_CDB, 0)); //0x00 + if (dev_mc && dev_mc->bus) { + printk(BIOS_DEBUG, "%s found", dev_path(dev_mc)); + pci_domain = dev_mc->bus->dev; + if (pci_domain && (pci_domain->path.type == DEVICE_PATH_PCI_DOMAIN)) { + printk(BIOS_DEBUG, "\n%s move to ",dev_path(dev_mc)); + dev_mc->bus->secondary = CONFIG_CBB; // move to 0xff + printk(BIOS_DEBUG, "%s",dev_path(dev_mc)); + } else { + printk(BIOS_DEBUG, " but it is not under pci_domain directly "); + } + printk(BIOS_DEBUG, "\n"); + } + dev_mc = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0)); + if (!dev_mc) { + dev_mc = dev_find_slot(0, PCI_DEVFN(0x18, 0)); + if (dev_mc && dev_mc->bus) { + printk(BIOS_DEBUG, "%s found\n", dev_path(dev_mc)); + pci_domain = dev_mc->bus->dev; + if (pci_domain && (pci_domain->path.type == DEVICE_PATH_PCI_DOMAIN)) { + if ((pci_domain->link_list) && (pci_domain->link_list->children == dev_mc)) { + printk(BIOS_DEBUG, "%s move to ",dev_path(dev_mc)); + dev_mc->bus->secondary = CONFIG_CBB; // move to 0xff + printk(BIOS_DEBUG, "%s\n",dev_path(dev_mc)); + while (dev_mc) { + printk(BIOS_DEBUG, "%s move to ",dev_path(dev_mc)); + dev_mc->path.pci.devfn -= PCI_DEVFN(0x18,0); + printk(BIOS_DEBUG, "%s\n",dev_path(dev_mc)); + dev_mc = dev_mc->sibling; + } + } + } + } + } +#endif + dev_mc = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0)); + if (!dev_mc) { + printk(BIOS_ERR, "%02x:%02x.0 not found", CONFIG_CBB, CONFIG_CDB); + die(""); + } + sysconf_init(dev_mc); +#if CONFIG_CBB && (MAX_NODE_NUMS > 32) + if (node_nums>32) { // need to put node 32 to node 63 to bus 0xfe + if (pci_domain->link_list && !pci_domain->link_list->next) { + struct bus *new_link = new_link(pci_domain); + pci_domain->link_list->next = new_link; + new_link->link_num = 1; + new_link->dev = pci_domain; + new_link->children = 0; + printk(BIOS_DEBUG, "%s links now 2\n", dev_path(pci_domain)); + } + pci_domain->link_list->next->secondary = CONFIG_CBB - 1; + } +#endif + + /* Get Max Number of cores(MNC) */ + coreid_bits = (cpuid_ecx(AMD_CPUID_ASIZE_PCCOUNT) & 0x0000F000) >> 12; + core_max = 1 << (coreid_bits & 0x000F); //mnc + + ApicIdCoreIdSize = ((cpuid_ecx(0x80000008)>>12) & 0xF); + if (ApicIdCoreIdSize) { + core_nums = (1 << ApicIdCoreIdSize) - 1; + } else { + core_nums = 3; //quad core + } + + /* Find which cpus are present */ + cpu_bus = dev->link_list; + for (i = 0; i < node_nums; i++) { + device_t cdb_dev, cpu; + struct device_path cpu_path; + unsigned busn, devn; + struct bus *pbus; + + busn = CONFIG_CBB; + devn = CONFIG_CDB + i; + pbus = dev_mc->bus; +#if CONFIG_CBB && (MAX_NODE_NUMS > 32) + if (i >= 32) { + busn--; + devn -= 32; + pbus = pci_domain->link_list->next; + } +#endif + + /* Find the cpu's pci device */ + cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 0)); + if (!cdb_dev) { + /* If I am probing things in a weird order + * ensure all of the cpu's pci devices are found. + */ + int fn; + for(fn = 0; fn <= 5; fn++) { //FBDIMM? + cdb_dev = pci_probe_dev(NULL, pbus, + PCI_DEVFN(devn, fn)); + } + cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 0)); + } else { + /* Ok, We need to set the links for that device. + * otherwise the device under it will not be scanned + */ + int linknum; +#if CONFIG_HT3_SUPPORT==1 + linknum = 8; +#else + linknum = 4; +#endif + add_more_links(cdb_dev, linknum); + } + + family = cpuid_eax(1); + family = (family >> 20) & 0xFF; + if (family == 1) { //f10 + u32 dword; + cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 3)); + dword = pci_read_config32(cdb_dev, 0xe8); + siblings = ((dword & BIT15) >> 13) | ((dword & (BIT13 | BIT12)) >> 12); + } else if (family == 6) {//f15 + cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 5)); + if (cdb_dev && cdb_dev->enabled) { + siblings = pci_read_config32(cdb_dev, 0x84); + siblings &= 0xFF; + } + } else { + siblings = 0; //default one core + } + printk(BIOS_SPEW, "%s family%xh, core_max=0x%x, core_nums=0x%x, siblings=0x%x\n", + dev_path(cdb_dev), 0x0f + family, core_max, core_nums, siblings); + + for (j = 0; j <= siblings; j++ ) { + extern CONST OPTIONS_CONFIG_TOPOLOGY ROMDATA TopologyConfiguration; + u32 modules = TopologyConfiguration.PlatformNumberOfModules; + u32 lapicid_start = 0; + + /* Build the cpu device path */ + cpu_path.type = DEVICE_PATH_APIC; + /* + * APIC ID calucation is tightly coupled with AGESA v5 code. + * This calculation MUST match the assignment calculation done + * in LocalApicInitializationAtEarly() function. + * And reference GetLocalApicIdForCore() + * + * Apply apic enumeration rules + * For systems with >= 16 APICs, put the IO-APICs at 0..n and + * put the local-APICs at m..z + * + * This is needed because many IO-APIC devices only have 4 bits + * for their APIC id and therefore must reside at 0..15 + */ +#ifndef CFG_PLAT_NUM_IO_APICS /* defined in mainboard buildOpts.c */ +#define CFG_PLAT_NUM_IO_APICS 3 +#endif + if ((node_nums * core_max) + CFG_PLAT_NUM_IO_APICS >= 0x10) { + lapicid_start = (CFG_PLAT_NUM_IO_APICS - 1) / core_max; + lapicid_start = (lapicid_start + 1) * core_max; + printk(BIOS_SPEW, "lpaicid_start=0x%x ", lapicid_start); + } + cpu_path.apic.apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (siblings + 1)) : j); + printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n", + i, j, cpu_path.apic.apic_id); + + /* See if I can find the cpu */ + cpu = find_dev_path(cpu_bus, &cpu_path); + /* Enable the cpu if I have the processor */ + if (cdb_dev && cdb_dev->enabled) { + if (!cpu) { + cpu = alloc_dev(cpu_bus, &cpu_path); + } + if (cpu) { + cpu->enabled = 1; + } + } + /* Disable the cpu if I don't have the processor */ + if (cpu && (!cdb_dev || !cdb_dev->enabled)) { + cpu->enabled = 0; + } + /* Report what I have done */ + if (cpu) { + cpu->path.apic.node_id = i; + cpu->path.apic.core_id = j; + if (cpu->path.type == DEVICE_PATH_APIC) { + cpu->ops = &lapic_ops; + } + printk(BIOS_DEBUG, "CPU: %s %s\n", + dev_path(cpu), cpu->enabled?"enabled":"disabled"); + } + } //j + } + return max; +} + +static void cpu_bus_init(device_t dev) +{ + initialize_cpus(dev->link_list); +} + +static void cpu_bus_noop(device_t dev) +{ +} + +static void cpu_bus_read_resources(device_t dev) +{ +#if CONFIG_MMCONF_SUPPORT + struct resource *resource = new_resource(dev, 0xc0010058); + resource->base = CONFIG_MMCONF_BASE_ADDRESS; + resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096*256; + resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; +#endif +} + +static void cpu_bus_set_resources(device_t dev) +{ + struct resource *resource = find_resource(dev, 0xc0010058); + if (resource) { + report_resource_stored(dev, resource, " <mmconfig>"); + } + pci_dev_set_resources(dev); +} + +static struct device_operations cpu_bus_ops = { + .read_resources = cpu_bus_read_resources, + .set_resources = cpu_bus_set_resources, + .enable_resources = cpu_bus_noop, + .init = cpu_bus_init, + .scan_bus = cpu_bus_scan, +}; + + +static void root_complex_enable_dev(struct device *dev) +{ + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) { + dev->ops = &pci_domain_ops; + } else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) { + dev->ops = &cpu_bus_ops; + } +} + + +struct chip_operations northbridge_amd_agesa_family15_root_complex_ops = { + CHIP_NAME("AMD FAM15 Root Complex") + .enable_dev = root_complex_enable_dev, +}; diff --git a/src/northbridge/amd/agesa/family15/northbridge.h b/src/northbridge/amd/agesa/family15/northbridge.h new file mode 100644 index 0000000..7606b32 --- /dev/null +++ b/src/northbridge/amd/agesa/family15/northbridge.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef NORTHBRIDGE_AMD_AGESA_FAM15_H +#define NORTHBRIDGE_AMD_AGESA_FAM15_H + +static struct device_operations pci_domain_ops; +static struct device_operations cpu_bus_ops; + +#endif /* NORTHBRIDGE_AMD_AGESA_FAM15_H */ diff --git a/src/northbridge/amd/agesa/family15/root_complex/Kconfig b/src/northbridge/amd/agesa/family15/root_complex/Kconfig new file mode 100644 index 0000000..032b836 --- /dev/null +++ b/src/northbridge/amd/agesa/family15/root_complex/Kconfig @@ -0,0 +1,2 @@ +config NORTHBRIDGE_AMD_AGESA_FAMILY15_ROOT_COMPLEX + bool diff --git a/src/northbridge/amd/agesa/family15/root_complex/chip.h b/src/northbridge/amd/agesa/family15/root_complex/chip.h new file mode 100644 index 0000000..06b3510 --- /dev/null +++ b/src/northbridge/amd/agesa/family15/root_complex/chip.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +struct northbridge_amd_agesa_family15_root_complex_config +{ +}; + +extern struct chip_operations northbridge_amd_agesa_family15_root_complex_ops;

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Patch set updated for coreboot: d59002f pci_ids: Add AMD F15h model 00-0f and F10h cpu HT device pci ids
by Kerry Sheh 07 Feb '12

07 Feb '12

Kerry Sheh (shekairui(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/609 -gerrit commit d59002f19e9dc56bd94c61f055b26bef62943540 Author: Kerry Sheh <shekairui(a)gmail.com> Date: Tue Feb 7 20:31:40 2012 +0800 pci_ids: Add AMD F15h model 00-0f and F10h cpu HT device pci ids Change-Id: I13905f5730d08510c8f0f6e652f41a679d618d1b Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> --- src/include/device/pci_ids.h | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index fcd31c0..60399ef 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -284,6 +284,9 @@ #define PCI_DEVICE_ID_ATI_RADEON_RC 0x5146 #define PCI_DEVICE_ID_ATI_RADEON_RD 0x5147 +#define PCI_DEVICE_ID_AMD_15H_MODEL_000F_NB_HT 0x1600 +#define PCI_DEVICE_ID_AMD_10H_NB_HT 0x1200 + #define PCI_DEVICE_ID_ATI_SB600_LPC 0x438D #define PCI_DEVICE_ID_ATI_SB600_SATA 0x4380 #define PCI_DEVICE_ID_ATI_SB600_IDE 0x438C

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Patch set updated for coreboot: 3354884 AGESA F15: AGESA family15 model 00-0fh cpu wrapper
by Kerry Sheh 07 Feb '12

07 Feb '12

Kerry Sheh (shekairui(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/555 -gerrit commit 33548842f15fb467b28a0a899b4ff84ceccf5116 Author: Kerry Sheh <shekairui(a)gmail.com> Date: Tue Feb 7 20:31:35 2012 +0800 AGESA F15: AGESA family15 model 00-0fh cpu wrapper Change-Id: I7580bc063c09d99d3fca8b20cd39df2384a6ad44 Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> --- src/cpu/amd/agesa/Kconfig | 22 ++++- src/cpu/amd/agesa/Makefile.inc | 3 +- src/cpu/amd/agesa/family15/Kconfig | 82 +++++++++++++++ src/cpu/amd/agesa/family15/Makefile.inc | 30 ++++++ src/cpu/amd/agesa/family15/chip.h | 23 +++++ src/cpu/amd/agesa/family15/chip_name.c | 25 +++++ src/cpu/amd/agesa/family15/model_15_init.c | 147 ++++++++++++++++++++++++++++ src/include/cpu/amd/amdfam15.h | 41 ++++++++ 8 files changed, 371 insertions(+), 2 deletions(-) diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index 60bb74b..631724b 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -1,7 +1,7 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. +# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -17,6 +17,26 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # +config AMD_AGESA + bool + default n + +config XIP_ROM_BASE + hex + default 0xfff00000 + +config XIP_ROM_SIZE + hex + default 0x100000 + help + Overwride the default write through caching size as 1M Bytes. + On some AMD paltform, one socket support 2 or more kinds of + processor family, compiling several cpu families agesa code + will increase the romstage size. + In order to execute romstage in place on the flash rom, + more space is required to be set as write through caching. + source src/cpu/amd/agesa/family10/Kconfig source src/cpu/amd/agesa/family12/Kconfig source src/cpu/amd/agesa/family14/Kconfig +source src/cpu/amd/agesa/family15/Kconfig diff --git a/src/cpu/amd/agesa/Makefile.inc b/src/cpu/amd/agesa/Makefile.inc index 4331435..fb536dd 100644 --- a/src/cpu/amd/agesa/Makefile.inc +++ b/src/cpu/amd/agesa/Makefile.inc @@ -1,7 +1,7 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. +# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -19,6 +19,7 @@ subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY10) += family10 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY12) += family12 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += family14 +subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15) += family15 ramstage-y += apic_timer.c cpu_incs += $(src)/cpu/amd/agesa/cache_as_ram.inc diff --git a/src/cpu/amd/agesa/family15/Kconfig b/src/cpu/amd/agesa/family15/Kconfig new file mode 100644 index 0000000..0f2f920 --- /dev/null +++ b/src/cpu/amd/agesa/family15/Kconfig @@ -0,0 +1,82 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +config CPU_AMD_AGESA_FAMILY15 + bool + select PCI_IO_CFG_EXT + select AMD_AGESA + +if CPU_AMD_AGESA_FAMILY15 + +config CPU_AMD_SOCKET_G34 + bool + default n + help + AMD G34 Socket + +config CPU_AMD_SOCKET_C32 + bool + default n + help + AMD C32 Socket + +config CPU_AMD_SOCKET_AM3R2 + bool + default n + help + AMD AM3r2 Socket + +config EXT_RT_TBL_SUPPORT + bool + default n + +config EXT_CONF_SUPPORT + bool + default n + +config CBB + hex + default 0x0 + +config CDB + hex + default 0x18 + +config XIP_ROM_BASE + hex + default 0xfff80000 + +config XIP_ROM_SIZE + hex + default 0x80000 + +config HAVE_INIT_TIMER + bool + default y + +config REDIRECT_IDS_HDT_CONSOLE_TO_SERIAL + bool "Redirect AGESA IDS_HDT_CONSOLE to serial console" + default n + depends on CPU_AMD_AGESA_FAMILY15 + help + This Option allows you to redirect the AMD AGESA IDS_HDT_CONSOLE debug information to the serial console. + + Warning: Only enable this option when debuging or tracing AMD AGESA code. + +endif #CPU_AMD_AGESA_FAMILY15 diff --git a/src/cpu/amd/agesa/family15/Makefile.inc b/src/cpu/amd/agesa/family15/Makefile.inc new file mode 100644 index 0000000..936d3c8 --- /dev/null +++ b/src/cpu/amd/agesa/family15/Makefile.inc @@ -0,0 +1,30 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +subdirs-y += ../../mtrr +subdirs-y += ../../../x86/tsc +subdirs-y += ../../../x86/lapic +subdirs-y += ../../../x86/cache +subdirs-y += ../../../x86/mtrr +subdirs-y += ../../../x86/pae +subdirs-y += ../../../x86/smm + +ramstage-y += chip_name.c +driver-y += model_15_init.c + diff --git a/src/cpu/amd/agesa/family15/chip.h b/src/cpu/amd/agesa/family15/chip.h new file mode 100644 index 0000000..0171e7f --- /dev/null +++ b/src/cpu/amd/agesa/family15/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations cpu_amd_agesa_family15_ops; + +struct cpu_amd_agesa_family15_config { +}; diff --git a/src/cpu/amd/agesa/family15/chip_name.c b/src/cpu/amd/agesa/family15/chip_name.c new file mode 100644 index 0000000..963a423 --- /dev/null +++ b/src/cpu/amd/agesa/family15/chip_name.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include "chip.h" + +struct chip_operations cpu_amd_agesa_family15_ops = { + CHIP_NAME("AMD CPU Family 15h") +}; diff --git a/src/cpu/amd/agesa/family15/model_15_init.c b/src/cpu/amd/agesa/family15/model_15_init.c new file mode 100644 index 0000000..d100338 --- /dev/null +++ b/src/cpu/amd/agesa/family15/model_15_init.c @@ -0,0 +1,147 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/mtrr.h> +#include <device/device.h> +#include <device/pci.h> +#include <string.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/pae.h> + +#include <cpu/cpu.h> +#include <cpu/x86/lapic.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/mtrr.h> +#include <cpu/amd/amdfam15.h> + +static msr_t rdmsr_amd(u32 index) +{ + msr_t result; + __asm__ __volatile__( + "rdmsr" + :"=a"(result.lo), "=d"(result.hi) + :"c"(index), "D"(0x9c5a203a) + ); + return result; +} + +static void wrmsr_amd(u32 index, msr_t msr) +{ + __asm__ __volatile__( + "wrmsr" + : /* No outputs */ + :"c"(index), "a"(msr.lo), "d"(msr.hi), "D"(0x9c5a203a) + ); +} + +static void model_15_init(device_t dev) +{ + printk(BIOS_DEBUG, "Model 15 Init.\n"); + + u8 i; + msr_t msr; + int msrno; +#if CONFIG_LOGICAL_CPUS == 1 + u32 siblings; +#endif + + disable_cache (); + /* Enable access to AMD RdDram and WrDram extension bits */ + msr = rdmsr(SYSCFG_MSR); + msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; + wrmsr(SYSCFG_MSR, msr); + + // BSP: make a0000-bffff UC, c0000-fffff WB, same as ApMtrrSettingsList for APs + msr.lo = msr.hi = 0; + wrmsr (0x259, msr); + msr.lo = msr.hi = 0x1e1e1e1e; + for (msrno = 0x268; msrno <= 0x26f; msrno++) + wrmsr (msrno, msr); + + msr.lo = 0x04040404; msr.hi = 0x04040404; + wrmsr(0x259, msr); + + /* disable access to AMD RdDram and WrDram extension bits */ + msr = rdmsr(SYSCFG_MSR); + msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; + wrmsr(SYSCFG_MSR, msr); + enable_cache (); + + /* zero the machine check error status registers */ + msr.lo = 0; + msr.hi = 0; + for (i = 0; i < 6; i++) { + wrmsr(MCI_STATUS + (i * 4), msr); + } + + /* Enable the local cpu apics */ + setup_lapic(); + +#if CONFIG_LOGICAL_CPUS == 1 + siblings = cpuid_ecx(0x80000008) & 0xff; + + if (siblings > 0) { + msr = rdmsr_amd(CPU_ID_FEATURES_MSR); + msr.lo |= 1 << 28; + wrmsr_amd(CPU_ID_FEATURES_MSR, msr); + + msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR); + msr.hi |= 1 << (33 - 32); + wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr); + } + printk(BIOS_DEBUG, "siblings = %02d, ", siblings); +#endif + + /* DisableCf8ExtCfg */ + msr = rdmsr(NB_CFG_MSR); + msr.hi &= ~(1 << (46 - 32)); + wrmsr(NB_CFG_MSR, msr); + + + /* Write protect SMM space with SMMLOCK. */ + msr = rdmsr(HWCR_MSR); + msr.lo |= (1 << 0); + wrmsr(HWCR_MSR, msr); +} + +static struct device_operations cpu_dev_ops = { + .init = model_15_init, +}; + +static struct cpu_device_id cpu_table[] = { + { X86_VENDOR_AMD, 0x100F80}, /* HY-D0 */ + { X86_VENDOR_AMD, 0x100F90}, /* HY-D0 */ + { X86_VENDOR_AMD, 0x100F81}, /* HY-D1 */ + { X86_VENDOR_AMD, 0x100F91}, /* HY-D1 */ + { X86_VENDOR_AMD, 0x600f00 }, /* OR_A0x */ + { X86_VENDOR_AMD, 0x600f01 }, /* OR_A0x */ + { X86_VENDOR_AMD, 0x600f10 }, /* OR_B0x */ + { X86_VENDOR_AMD, 0x600f11 }, /* OR_B1x */ + { X86_VENDOR_AMD, 0x600f12 }, /* OR_B2x */ + { X86_VENDOR_AMD, 0x600f13 }, /* OR_B3x */ + { X86_VENDOR_AMD, 0x600f20 }, /* OR_C0x */ + { 0, 0 }, +}; + +static const struct cpu_driver model_15 __cpu_driver = { + .ops = &cpu_dev_ops, + .id_table = cpu_table, +}; diff --git a/src/include/cpu/amd/amdfam15.h b/src/include/cpu/amd/amdfam15.h new file mode 100644 index 0000000..3d300de --- /dev/null +++ b/src/include/cpu/amd/amdfam15.h @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef CPU_AMD_FAM15_H +#define CPU_AMD_FAM15_H + +#include <cpu/x86/msr.h> + +#define MCI_STATUS 0x00000401 +#define HWCR_MSR 0xC0010015 +#define NB_CFG_MSR 0xC001001f + +#define LS_CFG_MSR 0xC0011020 +#define IC_CFG_MSR 0xC0011021 +#define DC_CFG_MSR 0xC0011022 +#define CU_CFG_MSR 0xC0011023 +#define CU_CFG2_MSR 0xC001102A + +#define CPU_ID_FEATURES_MSR 0xC0011004 +#define CPU_ID_EXT_FEATURES_MSR 0xC0011005 + +static msr_t rdmsr_amd(u32 index); +static void wrmsr_amd(u32 index, msr_t msr); + +#endif /* CPU_AMD_FAM15_H */

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Patch set updated for coreboot: 8789a10 AGESA F15: AGESA family15 model 00-0fh cpu wrapper
by Kerry Sheh 07 Feb '12

07 Feb '12

Kerry Sheh (shekairui(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/555 -gerrit commit 8789a10ea5b3eae29754b0f5182dd876d1a1703b Author: Kerry Sheh <shekairui(a)gmail.com> Date: Tue Feb 7 11:38:46 2012 +0800 AGESA F15: AGESA family15 model 00-0fh cpu wrapper Change-Id: I7580bc063c09d99d3fca8b20cd39df2384a6ad44 Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> --- src/cpu/amd/agesa/Kconfig | 7 +- src/cpu/amd/agesa/Makefile.inc | 3 +- src/cpu/amd/agesa/family15/Kconfig | 82 +++++++++++++++ src/cpu/amd/agesa/family15/Makefile.inc | 30 ++++++ src/cpu/amd/agesa/family15/chip.h | 23 +++++ src/cpu/amd/agesa/family15/chip_name.c | 25 +++++ src/cpu/amd/agesa/family15/model_15_init.c | 147 ++++++++++++++++++++++++++++ src/include/cpu/amd/amdfam15.h | 41 ++++++++ 8 files changed, 356 insertions(+), 2 deletions(-) diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index 60bb74b..8eaa11d 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -1,7 +1,7 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. +# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -17,6 +17,11 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # +config AMD_AGESA + bool + default n + source src/cpu/amd/agesa/family10/Kconfig source src/cpu/amd/agesa/family12/Kconfig source src/cpu/amd/agesa/family14/Kconfig +source src/cpu/amd/agesa/family15/Kconfig diff --git a/src/cpu/amd/agesa/Makefile.inc b/src/cpu/amd/agesa/Makefile.inc index 4331435..fb536dd 100644 --- a/src/cpu/amd/agesa/Makefile.inc +++ b/src/cpu/amd/agesa/Makefile.inc @@ -1,7 +1,7 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. +# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -19,6 +19,7 @@ subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY10) += family10 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY12) += family12 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += family14 +subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15) += family15 ramstage-y += apic_timer.c cpu_incs += $(src)/cpu/amd/agesa/cache_as_ram.inc diff --git a/src/cpu/amd/agesa/family15/Kconfig b/src/cpu/amd/agesa/family15/Kconfig new file mode 100644 index 0000000..0f2f920 --- /dev/null +++ b/src/cpu/amd/agesa/family15/Kconfig @@ -0,0 +1,82 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +config CPU_AMD_AGESA_FAMILY15 + bool + select PCI_IO_CFG_EXT + select AMD_AGESA + +if CPU_AMD_AGESA_FAMILY15 + +config CPU_AMD_SOCKET_G34 + bool + default n + help + AMD G34 Socket + +config CPU_AMD_SOCKET_C32 + bool + default n + help + AMD C32 Socket + +config CPU_AMD_SOCKET_AM3R2 + bool + default n + help + AMD AM3r2 Socket + +config EXT_RT_TBL_SUPPORT + bool + default n + +config EXT_CONF_SUPPORT + bool + default n + +config CBB + hex + default 0x0 + +config CDB + hex + default 0x18 + +config XIP_ROM_BASE + hex + default 0xfff80000 + +config XIP_ROM_SIZE + hex + default 0x80000 + +config HAVE_INIT_TIMER + bool + default y + +config REDIRECT_IDS_HDT_CONSOLE_TO_SERIAL + bool "Redirect AGESA IDS_HDT_CONSOLE to serial console" + default n + depends on CPU_AMD_AGESA_FAMILY15 + help + This Option allows you to redirect the AMD AGESA IDS_HDT_CONSOLE debug information to the serial console. + + Warning: Only enable this option when debuging or tracing AMD AGESA code. + +endif #CPU_AMD_AGESA_FAMILY15 diff --git a/src/cpu/amd/agesa/family15/Makefile.inc b/src/cpu/amd/agesa/family15/Makefile.inc new file mode 100644 index 0000000..936d3c8 --- /dev/null +++ b/src/cpu/amd/agesa/family15/Makefile.inc @@ -0,0 +1,30 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +subdirs-y += ../../mtrr +subdirs-y += ../../../x86/tsc +subdirs-y += ../../../x86/lapic +subdirs-y += ../../../x86/cache +subdirs-y += ../../../x86/mtrr +subdirs-y += ../../../x86/pae +subdirs-y += ../../../x86/smm + +ramstage-y += chip_name.c +driver-y += model_15_init.c + diff --git a/src/cpu/amd/agesa/family15/chip.h b/src/cpu/amd/agesa/family15/chip.h new file mode 100644 index 0000000..0171e7f --- /dev/null +++ b/src/cpu/amd/agesa/family15/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations cpu_amd_agesa_family15_ops; + +struct cpu_amd_agesa_family15_config { +}; diff --git a/src/cpu/amd/agesa/family15/chip_name.c b/src/cpu/amd/agesa/family15/chip_name.c new file mode 100644 index 0000000..963a423 --- /dev/null +++ b/src/cpu/amd/agesa/family15/chip_name.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include "chip.h" + +struct chip_operations cpu_amd_agesa_family15_ops = { + CHIP_NAME("AMD CPU Family 15h") +}; diff --git a/src/cpu/amd/agesa/family15/model_15_init.c b/src/cpu/amd/agesa/family15/model_15_init.c new file mode 100644 index 0000000..d100338 --- /dev/null +++ b/src/cpu/amd/agesa/family15/model_15_init.c @@ -0,0 +1,147 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/mtrr.h> +#include <device/device.h> +#include <device/pci.h> +#include <string.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/pae.h> + +#include <cpu/cpu.h> +#include <cpu/x86/lapic.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/mtrr.h> +#include <cpu/amd/amdfam15.h> + +static msr_t rdmsr_amd(u32 index) +{ + msr_t result; + __asm__ __volatile__( + "rdmsr" + :"=a"(result.lo), "=d"(result.hi) + :"c"(index), "D"(0x9c5a203a) + ); + return result; +} + +static void wrmsr_amd(u32 index, msr_t msr) +{ + __asm__ __volatile__( + "wrmsr" + : /* No outputs */ + :"c"(index), "a"(msr.lo), "d"(msr.hi), "D"(0x9c5a203a) + ); +} + +static void model_15_init(device_t dev) +{ + printk(BIOS_DEBUG, "Model 15 Init.\n"); + + u8 i; + msr_t msr; + int msrno; +#if CONFIG_LOGICAL_CPUS == 1 + u32 siblings; +#endif + + disable_cache (); + /* Enable access to AMD RdDram and WrDram extension bits */ + msr = rdmsr(SYSCFG_MSR); + msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; + wrmsr(SYSCFG_MSR, msr); + + // BSP: make a0000-bffff UC, c0000-fffff WB, same as ApMtrrSettingsList for APs + msr.lo = msr.hi = 0; + wrmsr (0x259, msr); + msr.lo = msr.hi = 0x1e1e1e1e; + for (msrno = 0x268; msrno <= 0x26f; msrno++) + wrmsr (msrno, msr); + + msr.lo = 0x04040404; msr.hi = 0x04040404; + wrmsr(0x259, msr); + + /* disable access to AMD RdDram and WrDram extension bits */ + msr = rdmsr(SYSCFG_MSR); + msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; + wrmsr(SYSCFG_MSR, msr); + enable_cache (); + + /* zero the machine check error status registers */ + msr.lo = 0; + msr.hi = 0; + for (i = 0; i < 6; i++) { + wrmsr(MCI_STATUS + (i * 4), msr); + } + + /* Enable the local cpu apics */ + setup_lapic(); + +#if CONFIG_LOGICAL_CPUS == 1 + siblings = cpuid_ecx(0x80000008) & 0xff; + + if (siblings > 0) { + msr = rdmsr_amd(CPU_ID_FEATURES_MSR); + msr.lo |= 1 << 28; + wrmsr_amd(CPU_ID_FEATURES_MSR, msr); + + msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR); + msr.hi |= 1 << (33 - 32); + wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr); + } + printk(BIOS_DEBUG, "siblings = %02d, ", siblings); +#endif + + /* DisableCf8ExtCfg */ + msr = rdmsr(NB_CFG_MSR); + msr.hi &= ~(1 << (46 - 32)); + wrmsr(NB_CFG_MSR, msr); + + + /* Write protect SMM space with SMMLOCK. */ + msr = rdmsr(HWCR_MSR); + msr.lo |= (1 << 0); + wrmsr(HWCR_MSR, msr); +} + +static struct device_operations cpu_dev_ops = { + .init = model_15_init, +}; + +static struct cpu_device_id cpu_table[] = { + { X86_VENDOR_AMD, 0x100F80}, /* HY-D0 */ + { X86_VENDOR_AMD, 0x100F90}, /* HY-D0 */ + { X86_VENDOR_AMD, 0x100F81}, /* HY-D1 */ + { X86_VENDOR_AMD, 0x100F91}, /* HY-D1 */ + { X86_VENDOR_AMD, 0x600f00 }, /* OR_A0x */ + { X86_VENDOR_AMD, 0x600f01 }, /* OR_A0x */ + { X86_VENDOR_AMD, 0x600f10 }, /* OR_B0x */ + { X86_VENDOR_AMD, 0x600f11 }, /* OR_B1x */ + { X86_VENDOR_AMD, 0x600f12 }, /* OR_B2x */ + { X86_VENDOR_AMD, 0x600f13 }, /* OR_B3x */ + { X86_VENDOR_AMD, 0x600f20 }, /* OR_C0x */ + { 0, 0 }, +}; + +static const struct cpu_driver model_15 __cpu_driver = { + .ops = &cpu_dev_ops, + .id_table = cpu_table, +}; diff --git a/src/include/cpu/amd/amdfam15.h b/src/include/cpu/amd/amdfam15.h new file mode 100644 index 0000000..3d300de --- /dev/null +++ b/src/include/cpu/amd/amdfam15.h @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef CPU_AMD_FAM15_H +#define CPU_AMD_FAM15_H + +#include <cpu/x86/msr.h> + +#define MCI_STATUS 0x00000401 +#define HWCR_MSR 0xC0010015 +#define NB_CFG_MSR 0xC001001f + +#define LS_CFG_MSR 0xC0011020 +#define IC_CFG_MSR 0xC0011021 +#define DC_CFG_MSR 0xC0011022 +#define CU_CFG_MSR 0xC0011023 +#define CU_CFG2_MSR 0xC001102A + +#define CPU_ID_FEATURES_MSR 0xC0011004 +#define CPU_ID_EXT_FEATURES_MSR 0xC0011005 + +static msr_t rdmsr_amd(u32 index); +static void wrmsr_amd(u32 index, msr_t msr); + +#endif /* CPU_AMD_FAM15_H */

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Patch set updated for coreboot: 4a1a46e AGESA F15: AGESA family15 model 00-0fh northbridge wrapper
by Kerry Sheh 07 Feb '12

07 Feb '12

Kerry Sheh (shekairui(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/556 -gerrit commit 4a1a46e82adbc3c2b4104caea492c648cf91e38f Author: Kerry Sheh <shekairui(a)gmail.com> Date: Tue Feb 7 18:46:09 2012 +0800 AGESA F15: AGESA family15 model 00-0fh northbridge wrapper Change-Id: I87c4d47f19161c604b0285102bb3809c8337375a Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> --- src/northbridge/amd/agesa/Kconfig | 3 +- src/northbridge/amd/agesa/Makefile.inc | 3 +- src/northbridge/amd/agesa/family15/Kconfig | 49 + src/northbridge/amd/agesa/family15/Makefile.inc | 20 + src/northbridge/amd/agesa/family15/bootblock.c | 25 + src/northbridge/amd/agesa/family15/chip.h | 24 + src/northbridge/amd/agesa/family15/northbridge.c | 1168 ++++++++++++++++++++ src/northbridge/amd/agesa/family15/northbridge.h | 26 + .../amd/agesa/family15/root_complex/Kconfig | 2 + .../amd/agesa/family15/root_complex/chip.h | 24 + 10 files changed, 1342 insertions(+), 2 deletions(-) diff --git a/src/northbridge/amd/agesa/Kconfig b/src/northbridge/amd/agesa/Kconfig index 3bcb0bb..2ed9fd5 100644 --- a/src/northbridge/amd/agesa/Kconfig +++ b/src/northbridge/amd/agesa/Kconfig @@ -1,7 +1,7 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. +# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -24,4 +24,5 @@ config CONSOLE_VGA_MULTI source src/northbridge/amd/agesa/family10/Kconfig source src/northbridge/amd/agesa/family12/Kconfig source src/northbridge/amd/agesa/family14/Kconfig +source src/northbridge/amd/agesa/family15/Kconfig diff --git a/src/northbridge/amd/agesa/Makefile.inc b/src/northbridge/amd/agesa/Makefile.inc index 1da8f60..eef1cd3 100644 --- a/src/northbridge/amd/agesa/Makefile.inc +++ b/src/northbridge/amd/agesa/Makefile.inc @@ -1,7 +1,7 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. +# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -19,3 +19,4 @@ subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10) += family10 subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY12) += family12 subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY14) += family14 +subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15) += family15 diff --git a/src/northbridge/amd/agesa/family15/Kconfig b/src/northbridge/amd/agesa/family15/Kconfig new file mode 100644 index 0000000..52f7a1e --- /dev/null +++ b/src/northbridge/amd/agesa/family15/Kconfig @@ -0,0 +1,49 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2009 coresystems GmbH +## Copyright (C) 2012 Advanced Micro Devices, Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## +config NORTHBRIDGE_AMD_AGESA_FAMILY15 + bool + select HAVE_DEBUG_RAM_SETUP + select HAVE_DEBUG_SMBUS + select HYPERTRANSPORT_PLUGIN_SUPPORT + select MMCONF_SUPPORT + select NORTHBRIDGE_AMD_AGESA_FAMILY15_ROOT_COMPLEX + +if NORTHBRIDGE_AMD_AGESA_FAMILY15 +config HT3_SUPPORT + bool + default y +config HW_MEM_HOLE_SIZEK + hex + default 0x100000 +config HW_MEM_HOLE_SIZE_AUTO_INC + bool + default n +config MMCONF_BASE_ADDRESS + hex + default 0xF8000000 +config MMCONF_BUS_NUMBER + int + default 64 +config BOOTBLOCK_NORTHBRIDGE_INIT + string + default "northbridge/amd/agesa/family15/bootblock.c" +endif #NORTHBRIDGE_AMD_AGESA_FAMILY15 + +source "src/northbridge/amd/agesa/family15/root_complex/Kconfig" diff --git a/src/northbridge/amd/agesa/family15/Makefile.inc b/src/northbridge/amd/agesa/family15/Makefile.inc new file mode 100644 index 0000000..255fe10 --- /dev/null +++ b/src/northbridge/amd/agesa/family15/Makefile.inc @@ -0,0 +1,20 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +driver-y += northbridge.c diff --git a/src/northbridge/amd/agesa/family15/bootblock.c b/src/northbridge/amd/agesa/family15/bootblock.c new file mode 100644 index 0000000..fc62c3e --- /dev/null +++ b/src/northbridge/amd/agesa/family15/bootblock.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <device/pci_def.h> + +static void bootblock_northbridge_init(void) { +} diff --git a/src/northbridge/amd/agesa/family15/chip.h b/src/northbridge/amd/agesa/family15/chip.h new file mode 100644 index 0000000..cec1fc4 --- /dev/null +++ b/src/northbridge/amd/agesa/family15/chip.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +struct northbridge_amd_agesa_family15_config +{ +}; + +extern struct chip_operations northbridge_amd_agesa_family15_ops; diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c new file mode 100644 index 0000000..b0fc91d --- /dev/null +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -0,0 +1,1168 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <arch/io.h> +#include <stdint.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/hypertransport.h> +#include <stdlib.h> +#include <string.h> +#include <bitops.h> +#include <cpu/cpu.h> + +#include <cpu/x86/lapic.h> + +#include <Porting.h> +#include <AGESA.h> +#include <Options.h> +#include <Topology.h> +#include <cpu/amd/amdfam15.h> +#include <cpuRegisters.h> +#include "agesawrapper.h" +#include "root_complex/chip.h" +#include "northbridge.h" +#include "chip.h" + +#define MAX_NODE_NUMS (MAX_NODES * MAX_DIES) + +#if (defined CONFIG_EXT_CONF_SUPPORT) && CONFIG_EXT_CONF_SUPPORT == 1 +#error CONFIG_EXT_CONF_SUPPORT == 1 not support anymore! +#endif + +typedef struct dram_base_mask { + u32 base; //[47:27] at [28:8] + u32 mask; //[47:27] at [28:8] and enable at bit 0 +} dram_base_mask_t; + +static unsigned node_nums; +static unsigned sblink; +static device_t __f0_dev[MAX_NODE_NUMS]; +static device_t __f1_dev[MAX_NODE_NUMS]; +static device_t __f2_dev[MAX_NODE_NUMS]; +static device_t __f4_dev[MAX_NODE_NUMS]; +static unsigned fx_devs = 0; + + +static dram_base_mask_t get_dram_base_mask(u32 nodeid) +{ + device_t dev; + dram_base_mask_t d; + dev = __f1_dev[0]; + u32 temp; + temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16] + d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out DramMask [26:24] too + temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] + d.mask |= temp<<21; + temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16] + d.mask |= (temp & 1); // enable bit + d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too + temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] + d.base |= temp<<21; + return d; +} + +static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, + u32 io_min, u32 io_max) +{ + u32 i; + u32 tempreg; + /* io range allocation */ + tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit + for (i=0; i<node_nums; i++) + pci_write_config32(__f1_dev[i], reg+4, tempreg); + tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? +#if 0 + // FIXME: can we use VGA reg instead? + if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { + printk(BIOS_SPEW, "%s, enabling legacy VGA IO forwarding for %s link %s\n", + __func__, dev_path(dev), link); + tempreg |= PCI_IO_BASE_VGA_EN; + } + if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_NO_ISA) { + tempreg |= PCI_IO_BASE_NO_ISA; + } +#endif + for (i=0; i<node_nums; i++) + pci_write_config32(__f1_dev[i], reg, tempreg); +} + +static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmio_min, u32 mmio_max, u32 nodes) +{ + u32 i; + u32 tempreg; + /* io range allocation */ + tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit + for (i=0; i<nodes; i++) + pci_write_config32(__f1_dev[i], reg+4, tempreg); + tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); + for (i=0; i<node_nums; i++) + pci_write_config32(__f1_dev[i], reg, tempreg); +} + +static device_t get_node_pci(u32 nodeid, u32 fn) +{ +#if MAX_NODE_NUMS == 64 + if (nodeid < 32) { + return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn)); + } else { + return dev_find_slot(CONFIG_CBB-1, PCI_DEVFN(CONFIG_CDB + nodeid - 32, fn)); + } +#else + return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn)); +#endif +} + +static void get_fx_devs(void) +{ + int i; + for (i = 0; i < MAX_NODE_NUMS; i++) { + __f0_dev[i] = get_node_pci(i, 0); + __f1_dev[i] = get_node_pci(i, 1); + __f2_dev[i] = get_node_pci(i, 2); + __f4_dev[i] = get_node_pci(i, 4); + if (__f0_dev[i] != NULL && __f1_dev[i] != NULL) + fx_devs = i+1; + } + if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) { + die("Cannot find 0:0x18.[0|1]\n"); + } + printk(BIOS_DEBUG, "fx_devs=0x%x\n", fx_devs); +} + +static u32 f1_read_config32(unsigned reg) +{ + if (fx_devs == 0) + get_fx_devs(); + return pci_read_config32(__f1_dev[0], reg); +} + +static void f1_write_config32(unsigned reg, u32 value) +{ + int i; + if (fx_devs == 0) + get_fx_devs(); + for(i = 0; i < fx_devs; i++) { + device_t dev; + dev = __f1_dev[i]; + if (dev && dev->enabled) { + pci_write_config32(dev, reg, value); + } + } +} + +static u32 amdfam15_nodeid(device_t dev) +{ +#if MAX_NODE_NUMS == 64 + unsigned busn; + busn = dev->bus->secondary; + if (busn != CONFIG_CBB) { + return (dev->path.pci.devfn >> 3) - CONFIG_CDB + 32; + } else { + return (dev->path.pci.devfn >> 3) - CONFIG_CDB; + } + +#else + return (dev->path.pci.devfn >> 3) - CONFIG_CDB; +#endif +} + +static void set_vga_enable_reg(u32 nodeid, u32 linkn) +{ + u32 val; + + val = 1 | (nodeid<<4) | (linkn<<12); + /* it will routing + * (1)mmio 0xa0000:0xbffff + * (2)io 0x3b0:0x3bb, 0x3c0:0x3df + */ + f1_write_config32(0xf4, val); + +} + +/** + * @return + * @retval 2 resoure not exist, usable + * @retval 0 resource exist, not usable + * @retval 1 resource exist, resource has been allocated before + */ +static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, + unsigned goal_link) +{ + struct resource *res; + unsigned nodeid, link = 0; + int result; + res = 0; + for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { + device_t dev; + dev = __f0_dev[nodeid]; + if (!dev) + continue; + for (link = 0; !res && (link < 8); link++) { + res = probe_resource(dev, IOINDEX(0x1000 + reg, link)); + } + } + result = 2; + if (res) { + result = 0; + if ((goal_link == (link - 1)) && + (goal_nodeid == (nodeid - 1)) && + (res->flags <= 1)) { + result = 1; + } + } + return result; +} + +static struct resource *amdfam15_find_iopair(device_t dev, unsigned nodeid, unsigned link) +{ + struct resource *resource; + u32 free_reg, reg; + resource = 0; + free_reg = 0; + for (reg = 0xc0; reg <= 0xd8; reg += 0x8) { + int result; + result = reg_useable(reg, dev, nodeid, link); + if (result == 1) { + /* I have been allocated this one */ + break; + } + else if (result > 1) { + /* I have a free register pair */ + free_reg = reg; + } + } + if (reg > 0xd8) { + reg = free_reg; // if no free, the free_reg still be 0 + } + + resource = new_resource(dev, IOINDEX(0x1000 + reg, link)); + + return resource; +} + +static struct resource *amdfam15_find_mempair(device_t dev, u32 nodeid, u32 link) +{ + struct resource *resource; + u32 free_reg, reg; + resource = 0; + free_reg = 0; + for (reg = 0x80; reg <= 0xb8; reg += 0x8) { + int result; + result = reg_useable(reg, dev, nodeid, link); + if (result == 1) { + /* I have been allocated this one */ + break; + } + else if (result > 1) { + /* I have a free register pair */ + free_reg = reg; + } + } + if (reg > 0xb8) { + reg = free_reg; + } + + resource = new_resource(dev, IOINDEX(0x1000 + reg, link)); + return resource; +} + + +static void amdfam15_link_read_bases(device_t dev, u32 nodeid, u32 link) +{ + struct resource *resource; + + /* Initialize the io space constraints on the current bus */ + resource = amdfam15_find_iopair(dev, nodeid, link); + if (resource) { + u32 align; + align = log2(HT_IO_HOST_ALIGN); + resource->base = 0; + resource->size = 0; + resource->align = align; + resource->gran = align; + resource->limit = 0xffffUL; + resource->flags = IORESOURCE_IO | IORESOURCE_BRIDGE; + } + + /* Initialize the prefetchable memory constraints on the current bus */ + resource = amdfam15_find_mempair(dev, nodeid, link); + if (resource) { + resource->base = 0; + resource->size = 0; + resource->align = log2(HT_MEM_HOST_ALIGN); + resource->gran = log2(HT_MEM_HOST_ALIGN); + resource->limit = 0xffffffffffULL; + resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; + resource->flags |= IORESOURCE_BRIDGE; + } + + + /* Initialize the memory constraints on the current bus */ + resource = amdfam15_find_mempair(dev, nodeid, link); + if (resource) { + resource->base = 0; + resource->size = 0; + resource->align = log2(HT_MEM_HOST_ALIGN); + resource->gran = log2(HT_MEM_HOST_ALIGN); + resource->limit = 0xffffffffffULL; + resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE; + } + +} + + +static void read_resources(device_t dev) +{ + u32 nodeid; + struct bus *link; + + nodeid = amdfam15_nodeid(dev); + for (link = dev->link_list; link; link = link->next) { + if (link->children) { + amdfam15_link_read_bases(dev, nodeid, link->link_num); + } + } +} + + +static void set_resource(device_t dev, struct resource *resource, u32 nodeid) +{ + resource_t rbase, rend; + unsigned reg, link_num; + char buf[50]; + + + /* Make certain the resource has actually been set */ + if (!(resource->flags & IORESOURCE_ASSIGNED)) { + return; + } + + /* If I have already stored this resource don't worry about it */ + if (resource->flags & IORESOURCE_STORED) { + return; + } + + /* Only handle PCI memory and IO resources */ + if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO))) + return; + + /* Ensure I am actually looking at a resource of function 1 */ + if ((resource->index & 0xffff) < 0x1000) { + return; + } + /* Get the base address */ + rbase = resource->base; + + /* Get the limit (rounded up) */ + rend = resource_end(resource); + + /* Get the register and link */ + reg = resource->index & 0xfff; // 4k + link_num = IOINDEX_LINK(resource->index); + + if (resource->flags & IORESOURCE_IO) { + set_io_addr_reg(dev, nodeid, link_num, reg, rbase>>8, rend>>8); + } + else if (resource->flags & IORESOURCE_MEM) { + set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, node_nums) ;// [39:8] + } + resource->flags |= IORESOURCE_STORED; + sprintf(buf, " <node %x link %x>", + nodeid, link_num); + report_resource_stored(dev, resource, buf); +} + +/** + * I tried to reuse the resource allocation code in set_resource() + * but it is too difficult to deal with the resource allocation magic. + */ + +static void create_vga_resource(device_t dev, unsigned nodeid) +{ + struct bus *link; + + + /* find out which link the VGA card is connected, + * we only deal with the 'first' vga card */ + for (link = dev->link_list; link; link = link->next) { + if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { +#if CONFIG_MULTIPLE_VGA_ADAPTERS == 1 + extern device_t vga_pri; // the primary vga device, defined in device.c + printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, + link->secondary,link->subordinate); + /* We need to make sure the vga_pri is under the link */ + if((vga_pri->bus->secondary >= link->secondary ) && + (vga_pri->bus->secondary <= link->subordinate ) + ) +#endif + break; + } + } + + /* no VGA card installed */ + if (link == NULL) + return; + + printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, sblink); + set_vga_enable_reg(nodeid, sblink); +} + + +static void set_resources(device_t dev) +{ + unsigned nodeid; + struct bus *bus; + struct resource *res; + + /* Find the nodeid */ + nodeid = amdfam15_nodeid(dev); + + create_vga_resource(dev, nodeid); //TODO: do we need this? + + /* Set each resource we have found */ + for (res = dev->resource_list; res; res = res->next) { + set_resource(dev, res, nodeid); + } + + for (bus = dev->link_list; bus; bus = bus->next) { + if (bus->children) { + assign_resources(bus); + } + } +} + +static void northbridge_init(struct device *dev) +{ +} + +static unsigned scan_chains(device_t dev, unsigned max) +{ + unsigned nodeid; + struct bus *link; + device_t io_hub = NULL; + u32 next_unitid = 0x18; + nodeid = amdfam15_nodeid(dev); + if (nodeid == 0) { + for (link = dev->link_list; link; link = link->next) { + //if (link->link_num == sblink) { /* devicetree put IO Hub on link_lsit[sblink] */ + if (link->link_num == 0) { /* devicetree put IO Hub on link_lsit[0] */ + io_hub = link->children; + if (!io_hub || !io_hub->enabled) { + die("I can't find the IO Hub, or IO Hub not enabled, please check the device tree.\n"); + } + /* Now that nothing is overlapping it is safe to scan the children. */ + max = pci_scan_bus(link, 0x00, ((next_unitid - 1) << 3) | 7, 0); + } + } + } + return max; +} + +static struct device_operations northbridge_operations = { + .read_resources = read_resources, + .set_resources = set_resources, + .enable_resources = pci_dev_enable_resources, + .init = northbridge_init, + .scan_bus = scan_chains, + .enable = 0, + .ops_pci = 0, +}; + +static const struct pci_driver family15_northbridge __pci_driver = { + .ops = &northbridge_operations, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_AMD_15H_MODEL_000F_NB_HT, +}; + +static const struct pci_driver family10_northbridge __pci_driver = { + .ops = &northbridge_operations, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_AMD_10H_NB_HT, +}; + +struct chip_operations northbridge_amd_agesa_family15_ops = { + CHIP_NAME("AMD FAM15 Northbridge") + .enable_dev = 0, +}; + +static void domain_read_resources(device_t dev) +{ + unsigned reg; + + + /* Find the already assigned resource pairs */ + get_fx_devs(); + for (reg = 0x80; reg <= 0xd8; reg+= 0x08) { + u32 base, limit; + base = f1_read_config32(reg); + limit = f1_read_config32(reg + 0x04); + /* Is this register allocated? */ + if ((base & 3) != 0) { + unsigned nodeid, reg_link; + device_t reg_dev; + if (reg<0xc0) { // mmio + nodeid = (limit & 0xf) + (base&0x30); + } else { // io + nodeid = (limit & 0xf) + ((base>>4)&0x30); + } + reg_link = (limit >> 4) & 7; + reg_dev = __f0_dev[nodeid]; + if (reg_dev) { + /* Reserve the resource */ + struct resource *res; + res = new_resource(reg_dev, IOINDEX(0x1000 + reg, reg_link)); + if (res) { + res->flags = 1; + } + } + } + } + /* FIXME: do we need to check extend conf space? + I don't believe that much preset value */ + +#if CONFIG_PCI_64BIT_PREF_MEM == 0 + pci_domain_read_resources(dev); + + +#else + struct bus *link; + struct resource *resource; + for (link=dev->link_list; link; link = link->next) { + /* Initialize the system wide io space constraints */ + resource = new_resource(dev, 0|(link->link_num<<2)); + resource->base = 0x400; + resource->limit = 0xffffUL; + resource->flags = IORESOURCE_IO; + + /* Initialize the system wide prefetchable memory resources constraints */ + resource = new_resource(dev, 1|(link->link_num<<2)); + resource->limit = 0xfcffffffffULL; + resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; + + /* Initialize the system wide memory resources constraints */ + resource = new_resource(dev, 2|(link->link_num<<2)); + resource->limit = 0xfcffffffffULL; + resource->flags = IORESOURCE_MEM; + } +#endif +} + +static void domain_enable_resources(device_t dev) +{ + u32 val; + /* Must be called after PCI enumeration and resource allocation */ + printk(BIOS_DEBUG, "\nFam15 - domain_enable_resources: AmdInitMid.\n"); + val = agesawrapper_amdinitmid(); + if (val) { + printk(BIOS_DEBUG, "agesawrapper_amdinitmid failed: %x \n", val); + } + printk(BIOS_DEBUG, " ader - leaving domain_enable_resources.\n"); +} + + +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 +struct hw_mem_hole_info { + unsigned hole_startk; + int node_id; +}; +static struct hw_mem_hole_info get_hw_mem_hole_info(void) +{ + struct hw_mem_hole_info mem_hole; + int i; + mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK; + mem_hole.node_id = -1; + for (i = 0; i < node_nums; i++) { + dram_base_mask_t d; + u32 hole; + d = get_dram_base_mask(i); + if (!(d.mask & 1)) continue; // no memory on this node + hole = pci_read_config32(__f1_dev[i], 0xf0); + if (hole & 1) { // we find the hole + mem_hole.hole_startk = (hole & (0xff<<24)) >> 10; + mem_hole.node_id = i; // record the node No with hole + break; // only one hole + } + } + //We need to double check if there is speical set on base reg and limit reg are not continous instead of hole, it will find out it's hole_startk + if (mem_hole.node_id == -1) { + resource_t limitk_pri = 0; + for (i=0; i<node_nums; i++) { + dram_base_mask_t d; + resource_t base_k, limit_k; + d = get_dram_base_mask(i); + if (!(d.base & 1)) continue; + base_k = ((resource_t)(d.base & 0x1fffff00)) <<9; + if (base_k > 4 *1024 * 1024) break; // don't need to go to check + if (limitk_pri != base_k) { // we find the hole + mem_hole.hole_startk = (unsigned)limitk_pri; // must beblow 4G + mem_hole.node_id = i; + break; //only one hole + } + limit_k = ((resource_t)((d.mask + 0x00000100) & 0x1fffff00)) << 9; + limitk_pri = limit_k; + } + } + return mem_hole; +} +#endif +#if CONFIG_WRITE_HIGH_TABLES==1 +#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB +extern uint64_t high_tables_base, high_tables_size; +#endif +#if CONFIG_GFXUMA == 1 +extern uint64_t uma_memory_base, uma_memory_size; +static void add_uma_resource(struct device *dev, int index) +{ + struct resource *resource; + + printk(BIOS_DEBUG, "Adding UMA memory area\n"); + resource = new_resource(dev, index); + resource->base = (resource_t) uma_memory_base; + resource->size = (resource_t) uma_memory_size; + resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | + IORESOURCE_FIXED | IORESOURCE_STORED | + IORESOURCE_ASSIGNED; +} +#endif + +static void domain_set_resources(device_t dev) +{ +#if CONFIG_PCI_64BIT_PREF_MEM == 1 + struct resource *io, *mem1, *mem2; + struct resource *res; +#endif + unsigned long mmio_basek; + u32 pci_tolm; + int i, idx; + struct bus *link; +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 + struct hw_mem_hole_info mem_hole; + u32 reset_memhole = 1; +#endif + +#if CONFIG_PCI_64BIT_PREF_MEM == 1 + + for (link = dev->link_list; link; link = link->next) { + /* Now reallocate the pci resources memory with the + * highest addresses I can manage. + */ + mem1 = find_resource(dev, 1|(link->link_num<<2)); + mem2 = find_resource(dev, 2|(link->link_num<<2)); + + printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", + mem1->base, mem1->limit, mem1->size, mem1->align); + printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", + mem2->base, mem2->limit, mem2->size, mem2->align); + + /* See if both resources have roughly the same limits */ + if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) || + ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff))) + { + /* If so place the one with the most stringent alignment first */ + if (mem2->align > mem1->align) { + struct resource *tmp; + tmp = mem1; + mem1 = mem2; + mem2 = tmp; + } + /* Now place the memory as high up as it will go */ + mem2->base = resource_max(mem2); + mem1->limit = mem2->base - 1; + mem1->base = resource_max(mem1); + } + else { + /* Place the resources as high up as they will go */ + mem2->base = resource_max(mem2); + mem1->base = resource_max(mem1); + } + + printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", + mem1->base, mem1->limit, mem1->size, mem1->align); + printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", + mem2->base, mem2->limit, mem2->size, mem2->align); + } + + for (res = &dev->resource_list; res; res = res->next) + { + res->flags |= IORESOURCE_ASSIGNED; + res->flags |= IORESOURCE_STORED; + report_resource_stored(dev, res, ""); + } +#endif + + pci_tolm = 0xffffffffUL; + for (link = dev->link_list; link; link = link->next) { + pci_tolm = find_pci_tolm(link); + } + + // FIXME handle interleaved nodes. If you fix this here, please fix + // amdk8, too. + mmio_basek = pci_tolm >> 10; + /* Round mmio_basek to something the processor can support */ + mmio_basek &= ~((1 << 6) -1); + + // FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M + // MMIO hole. If you fix this here, please fix amdk8, too. + /* Round the mmio hole to 64M */ + mmio_basek &= ~((64*1024) - 1); + +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 + /* if the hw mem hole is already set in raminit stage, here we will compare + * mmio_basek and hole_basek. if mmio_basek is bigger that hole_basek and will + * use hole_basek as mmio_basek and we don't need to reset hole. + * otherwise We reset the hole to the mmio_basek + */ + + mem_hole = get_hw_mem_hole_info(); + + // Use hole_basek as mmio_basek, and we don't need to reset hole anymore + if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) { + mmio_basek = mem_hole.hole_startk; + reset_memhole = 0; + } +#endif + + idx = 0x10; + for (i = 0; i < node_nums; i++) { + dram_base_mask_t d; + resource_t basek, limitk, sizek; // 4 1T + + d = get_dram_base_mask(i); + + if (!(d.mask & 1)) continue; + basek = ((resource_t)(d.base & 0x1fffff00)) << 9; // could overflow, we may lost 6 bit here + limitk = ((resource_t)((d.mask + 0x00000100) & 0x1fffff00)) << 9 ; + + sizek = limitk - basek; + + + /* see if we need a hole from 0xa0000 to 0xbffff */ + if ((basek < ((8*64)+(8*16))) && (sizek > ((8*64)+(16*16)))) { + ram_resource(dev, (idx | i), basek, ((8*64)+(8*16)) - basek); + idx += 0x10; + basek = (8*64)+(16*16); + sizek = limitk - ((8*64)+(16*16)); + + } + + //printk(BIOS_DEBUG, "node %d : mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); + + /* split the region to accomodate pci memory space */ + if ((basek < 4*1024*1024 ) && (limitk > mmio_basek)) { + if (basek <= mmio_basek) { + unsigned pre_sizek; + pre_sizek = mmio_basek - basek; + if (pre_sizek>0) { + ram_resource(dev, (idx | i), basek, pre_sizek); + idx += 0x10; + sizek -= pre_sizek; +#if CONFIG_WRITE_HIGH_TABLES==1 + if (high_tables_base==0) { + /* Leave some space for ACPI, PIRQ and MP tables */ +#if CONFIG_GFXUMA == 1 + high_tables_base = uma_memory_base - (HIGH_TABLES_SIZE * 1024); +#else + high_tables_base = (mmio_basek - HIGH_TABLES_SIZE) * 1024; +#endif + high_tables_size = HIGH_TABLES_SIZE * 1024; + printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", + HIGH_TABLES_SIZE, high_tables_base); + } +#endif + } + basek = mmio_basek; + } + if ((basek + sizek) <= 4*1024*1024) { + sizek = 0; + } + else { + basek = 4*1024*1024; + sizek -= (4*1024*1024 - mmio_basek); + } + } + +#if CONFIG_GFXUMA == 1 + /* Deduct uma memory before reporting because + * this is what the mtrr code expects */ + sizek -= uma_memory_size / 1024; +#endif + ram_resource(dev, (idx | i), basek, sizek); + idx += 0x10; +#if CONFIG_WRITE_HIGH_TABLES==1 + printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", + i, mmio_basek, basek, limitk); + if (high_tables_base==0) { + /* Leave some space for ACPI, PIRQ and MP tables */ +#if CONFIG_GFXUMA == 1 + high_tables_base = uma_memory_base - (HIGH_TABLES_SIZE * 1024); +#else + high_tables_base = (limitk - HIGH_TABLES_SIZE) * 1024; +#endif + high_tables_size = HIGH_TABLES_SIZE * 1024; + } +#endif + } + +#if CONFIG_GFXUMA == 1 + add_uma_resource(dev, 7); +#endif + + for(link = dev->link_list; link; link = link->next) { + if (link->children) { + assign_resources(link); + } + } +} + + +static struct device_operations pci_domain_ops = { + .read_resources = domain_read_resources, + .set_resources = domain_set_resources, + .enable_resources = domain_enable_resources, + .init = NULL, + .scan_bus = pci_domain_scan_bus, + +#if CONFIG_MMCONF_SUPPORT_DEFAULT + .ops_pci_bus = &pci_ops_mmconf, +#else + .ops_pci_bus = &pci_cf8_conf1, +#endif +}; + + +static void sysconf_init(device_t dev) // first node +{ + sblink = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1 + node_nums = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; //NodeCnt[2:0] +} + +static void add_more_links(device_t dev, unsigned total_links) +{ + struct bus *link, *last = NULL; + int link_num; + + for (link = dev->link_list; link; link = link->next) + last = link; + + if (last) { + int links = total_links - last->link_num; + link_num = last->link_num; + if (links > 0) { + link = malloc(links*sizeof(*link)); + if (!link) + die("Couldn't allocate more links!\n"); + memset(link, 0, links*sizeof(*link)); + last->next = link; + } + } + else { + link_num = -1; + link = malloc(total_links*sizeof(*link)); + memset(link, 0, total_links*sizeof(*link)); + dev->link_list = link; + } + + for (link_num = link_num + 1; link_num < total_links; link_num++) { + link->link_num = link_num; + link->dev = dev; + link->next = link + 1; + last = link; + link = link->next; + } + last->next = NULL; +} + +/* dummy read_resources */ +static void lapic_read_resources(device_t dev) +{ +} + +static struct device_operations lapic_ops = { + .read_resources = lapic_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = 0, + .scan_bus = 0, + .enable = 0, + .ops_pci = 0, +}; + +static u32 cpu_bus_scan(device_t dev, u32 max) +{ + struct bus *cpu_bus; + device_t dev_mc; +#if CONFIG_CBB + device_t pci_domain; +#endif + int i,j; + int coreid_bits; + int core_max = 0; + unsigned ApicIdCoreIdSize; + unsigned core_nums; + int siblings = 0; + unsigned int family; + +#if CONFIG_CBB + dev_mc = dev_find_slot(0, PCI_DEVFN(CONFIG_CDB, 0)); //0x00 + if (dev_mc && dev_mc->bus) { + printk(BIOS_DEBUG, "%s found", dev_path(dev_mc)); + pci_domain = dev_mc->bus->dev; + if (pci_domain && (pci_domain->path.type == DEVICE_PATH_PCI_DOMAIN)) { + printk(BIOS_DEBUG, "\n%s move to ",dev_path(dev_mc)); + dev_mc->bus->secondary = CONFIG_CBB; // move to 0xff + printk(BIOS_DEBUG, "%s",dev_path(dev_mc)); + } else { + printk(BIOS_DEBUG, " but it is not under pci_domain directly "); + } + printk(BIOS_DEBUG, "\n"); + } + dev_mc = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0)); + if (!dev_mc) { + dev_mc = dev_find_slot(0, PCI_DEVFN(0x18, 0)); + if (dev_mc && dev_mc->bus) { + printk(BIOS_DEBUG, "%s found\n", dev_path(dev_mc)); + pci_domain = dev_mc->bus->dev; + if (pci_domain && (pci_domain->path.type == DEVICE_PATH_PCI_DOMAIN)) { + if ((pci_domain->link_list) && (pci_domain->link_list->children == dev_mc)) { + printk(BIOS_DEBUG, "%s move to ",dev_path(dev_mc)); + dev_mc->bus->secondary = CONFIG_CBB; // move to 0xff + printk(BIOS_DEBUG, "%s\n",dev_path(dev_mc)); + while (dev_mc) { + printk(BIOS_DEBUG, "%s move to ",dev_path(dev_mc)); + dev_mc->path.pci.devfn -= PCI_DEVFN(0x18,0); + printk(BIOS_DEBUG, "%s\n",dev_path(dev_mc)); + dev_mc = dev_mc->sibling; + } + } + } + } + } +#endif + dev_mc = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0)); + if (!dev_mc) { + printk(BIOS_ERR, "%02x:%02x.0 not found", CONFIG_CBB, CONFIG_CDB); + die(""); + } + sysconf_init(dev_mc); +#if CONFIG_CBB && (MAX_NODE_NUMS > 32) + if (node_nums>32) { // need to put node 32 to node 63 to bus 0xfe + if (pci_domain->link_list && !pci_domain->link_list->next) { + struct bus *new_link = new_link(pci_domain); + pci_domain->link_list->next = new_link; + new_link->link_num = 1; + new_link->dev = pci_domain; + new_link->children = 0; + printk(BIOS_DEBUG, "%s links now 2\n", dev_path(pci_domain)); + } + pci_domain->link_list->next->secondary = CONFIG_CBB - 1; + } +#endif + + /* Get Max Number of cores(MNC) */ + coreid_bits = (cpuid_ecx(AMD_CPUID_ASIZE_PCCOUNT) & 0x0000F000) >> 12; + core_max = 1 << (coreid_bits & 0x000F); //mnc + + ApicIdCoreIdSize = ((cpuid_ecx(0x80000008)>>12) & 0xF); + if (ApicIdCoreIdSize) { + core_nums = (1 << ApicIdCoreIdSize) - 1; + } else { + core_nums = 3; //quad core + } + + /* Find which cpus are present */ + cpu_bus = dev->link_list; + for (i = 0; i < node_nums; i++) { + device_t cdb_dev, cpu; + struct device_path cpu_path; + unsigned busn, devn; + struct bus *pbus; + + busn = CONFIG_CBB; + devn = CONFIG_CDB + i; + pbus = dev_mc->bus; +#if CONFIG_CBB && (MAX_NODE_NUMS > 32) + if (i >= 32) { + busn--; + devn -= 32; + pbus = pci_domain->link_list->next; + } +#endif + + /* Find the cpu's pci device */ + cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 0)); + if (!cdb_dev) { + /* If I am probing things in a weird order + * ensure all of the cpu's pci devices are found. + */ + int fn; + for(fn = 0; fn <= 5; fn++) { //FBDIMM? + cdb_dev = pci_probe_dev(NULL, pbus, + PCI_DEVFN(devn, fn)); + } + cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 0)); + } else { + /* Ok, We need to set the links for that device. + * otherwise the device under it will not be scanned + */ + int linknum; +#if CONFIG_HT3_SUPPORT==1 + linknum = 8; +#else + linknum = 4; +#endif + add_more_links(cdb_dev, linknum); + } + + family = cpuid_eax(1); + family = (family >> 20) & 0xFF; + if (family == 1) { //f10 + u32 dword; + cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 3)); + dword = pci_read_config32(cdb_dev, 0xe8); + siblings = ((dword & BIT15) >> 13) | ((dword & (BIT13 | BIT12)) >> 12); + } else if (family == 6) {//f15 + cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 5)); + if (cdb_dev && cdb_dev->enabled) { + siblings = pci_read_config32(cdb_dev, 0x84); + siblings &= 0xFF; + } + } else { + siblings = 0; //default one core + } + printk(BIOS_SPEW, "%s family%xh, core_max=0x%x, core_nums=0x%x, siblings=0x%x\n", + dev_path(cdb_dev), 0x0f + family, core_max, core_nums, siblings); + + for (j = 0; j <= siblings; j++ ) { + extern CONST OPTIONS_CONFIG_TOPOLOGY ROMDATA TopologyConfiguration; + u32 modules = TopologyConfiguration.PlatformNumberOfModules; + u32 lapicid_start = 0; + + /* Build the cpu device path */ + cpu_path.type = DEVICE_PATH_APIC; + /* + * APIC ID calucation is tightly coupled with AGESA v5 code. + * This calculation MUST match the assignment calculation done + * in LocalApicInitializationAtEarly() function. + * And reference GetLocalApicIdForCore() + * + * Apply apic enumeration rules + * For systems with >= 16 APICs, put the IO-APICs at 0..n and + * put the local-APICs at m..z + * + * This is needed because many IO-APIC devices only have 4 bits + * for their APIC id and therefore must reside at 0..15 + */ +#ifndef CFG_PLAT_NUM_IO_APICS /* defined in mainboard buildOpts.c */ +#define CFG_PLAT_NUM_IO_APICS 3 +#endif + if ((node_nums * core_max) + CFG_PLAT_NUM_IO_APICS >= 0x10) { + lapicid_start = (CFG_PLAT_NUM_IO_APICS - 1) / core_max; + lapicid_start = (lapicid_start + 1) * core_max; + printk(BIOS_SPEW, "lpaicid_start=0x%x ", lapicid_start); + } + cpu_path.apic.apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (siblings + 1)) : j); + printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n", + i, j, cpu_path.apic.apic_id); + + /* See if I can find the cpu */ + cpu = find_dev_path(cpu_bus, &cpu_path); + /* Enable the cpu if I have the processor */ + if (cdb_dev && cdb_dev->enabled) { + if (!cpu) { + cpu = alloc_dev(cpu_bus, &cpu_path); + } + if (cpu) { + cpu->enabled = 1; + } + } + /* Disable the cpu if I don't have the processor */ + if (cpu && (!cdb_dev || !cdb_dev->enabled)) { + cpu->enabled = 0; + } + /* Report what I have done */ + if (cpu) { + cpu->path.apic.node_id = i; + cpu->path.apic.core_id = j; + if (cpu->path.type == DEVICE_PATH_APIC) { + cpu->ops = &lapic_ops; + } + printk(BIOS_DEBUG, "CPU: %s %s\n", + dev_path(cpu), cpu->enabled?"enabled":"disabled"); + } + } //j + } + return max; +} + +static void cpu_bus_init(device_t dev) +{ + initialize_cpus(dev->link_list); +} + +static void cpu_bus_noop(device_t dev) +{ +} + +static void cpu_bus_read_resources(device_t dev) +{ +#if CONFIG_MMCONF_SUPPORT + struct resource *resource = new_resource(dev, 0xc0010058); + resource->base = CONFIG_MMCONF_BASE_ADDRESS; + resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096*256; + resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; +#endif +} + +static void cpu_bus_set_resources(device_t dev) +{ + struct resource *resource = find_resource(dev, 0xc0010058); + if (resource) { + report_resource_stored(dev, resource, " <mmconfig>"); + } + pci_dev_set_resources(dev); +} + +static struct device_operations cpu_bus_ops = { + .read_resources = cpu_bus_read_resources, + .set_resources = cpu_bus_set_resources, + .enable_resources = cpu_bus_noop, + .init = cpu_bus_init, + .scan_bus = cpu_bus_scan, +}; + + +static void root_complex_enable_dev(struct device *dev) +{ + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) { + dev->ops = &pci_domain_ops; + } else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) { + dev->ops = &cpu_bus_ops; + } +} + + +struct chip_operations northbridge_amd_agesa_family15_root_complex_ops = { + CHIP_NAME("AMD FAM15 Root Complex") + .enable_dev = root_complex_enable_dev, +}; diff --git a/src/northbridge/amd/agesa/family15/northbridge.h b/src/northbridge/amd/agesa/family15/northbridge.h new file mode 100644 index 0000000..7606b32 --- /dev/null +++ b/src/northbridge/amd/agesa/family15/northbridge.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef NORTHBRIDGE_AMD_AGESA_FAM15_H +#define NORTHBRIDGE_AMD_AGESA_FAM15_H + +static struct device_operations pci_domain_ops; +static struct device_operations cpu_bus_ops; + +#endif /* NORTHBRIDGE_AMD_AGESA_FAM15_H */ diff --git a/src/northbridge/amd/agesa/family15/root_complex/Kconfig b/src/northbridge/amd/agesa/family15/root_complex/Kconfig new file mode 100644 index 0000000..032b836 --- /dev/null +++ b/src/northbridge/amd/agesa/family15/root_complex/Kconfig @@ -0,0 +1,2 @@ +config NORTHBRIDGE_AMD_AGESA_FAMILY15_ROOT_COMPLEX + bool diff --git a/src/northbridge/amd/agesa/family15/root_complex/chip.h b/src/northbridge/amd/agesa/family15/root_complex/chip.h new file mode 100644 index 0000000..06b3510 --- /dev/null +++ b/src/northbridge/amd/agesa/family15/root_complex/chip.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +struct northbridge_amd_agesa_family15_root_complex_config +{ +}; + +extern struct chip_operations northbridge_amd_agesa_family15_root_complex_ops;

1 0

Patch set updated for coreboot: aaed6c6 RD890: AMD RD890/SR56X0 CIMX wrapper
by Kerry Sheh 07 Feb '12

07 Feb '12

Kerry Sheh (shekairui(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/559 -gerrit commit aaed6c6f999c0002f560fda4402909c393fd406b Author: Kerry Sheh <shekairui(a)gmail.com> Date: Tue Feb 7 18:46:12 2012 +0800 RD890: AMD RD890/SR56X0 CIMX wrapper Support AMD RD890 CIMX support AMD RD890TV, RX780, RD780, SR56x0, RD890 and 990FX chipsets. Change-Id: I39dc5fc316fbb465808bac48a13a49b7d867f04f Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> --- src/northbridge/amd/Kconfig | 1 + src/northbridge/amd/Makefile.inc | 1 + src/northbridge/amd/cimx/Kconfig | 24 ++ src/northbridge/amd/cimx/Makefile.inc | 20 ++ src/northbridge/amd/cimx/rd890/Kconfig | 33 +++ src/northbridge/amd/cimx/rd890/Makefile.inc | 25 ++ src/northbridge/amd/cimx/rd890/NbPlatform.h | 147 ++++++++++ src/northbridge/amd/cimx/rd890/amd.h | 385 +++++++++++++++++++++++++++ src/northbridge/amd/cimx/rd890/cbtypes.h | 71 +++++ src/northbridge/amd/cimx/rd890/chip.h | 38 +++ src/northbridge/amd/cimx/rd890/early.c | 113 ++++++++ src/northbridge/amd/cimx/rd890/late.c | 257 ++++++++++++++++++ src/northbridge/amd/cimx/rd890/nb_cimx.h | 44 +++ 13 files changed, 1159 insertions(+), 0 deletions(-) diff --git a/src/northbridge/amd/Kconfig b/src/northbridge/amd/Kconfig index 4a120ca..33e19c2 100644 --- a/src/northbridge/amd/Kconfig +++ b/src/northbridge/amd/Kconfig @@ -4,6 +4,7 @@ source src/northbridge/amd/gx2/Kconfig source src/northbridge/amd/amdfam10/Kconfig source src/northbridge/amd/lx/Kconfig source src/northbridge/amd/agesa/Kconfig +source src/northbridge/amd/cimx/Kconfig menu "HyperTransport setup" #could be implemented for K8 (NORTHBRIDGE_AMD_AMDK8) depends on (NORTHBRIDGE_AMD_AMDFAM10) && EXPERT diff --git a/src/northbridge/amd/Makefile.inc b/src/northbridge/amd/Makefile.inc index bf96b80..c438473 100644 --- a/src/northbridge/amd/Makefile.inc +++ b/src/northbridge/amd/Makefile.inc @@ -5,3 +5,4 @@ subdirs-$(CONFIG_NORTHBRIDGE_AMD_GX2) += gx2 subdirs-$(CONFIG_NORTHBRIDGE_AMD_LX) += lx subdirs-$(CONFIG_AMD_AGESA) += agesa +subdirs-$(CONFIG_AMD_NB_CIMX) += cimx diff --git a/src/northbridge/amd/cimx/Kconfig b/src/northbridge/amd/cimx/Kconfig new file mode 100644 index 0000000..6751bd4 --- /dev/null +++ b/src/northbridge/amd/cimx/Kconfig @@ -0,0 +1,24 @@ +# +# This file is part of the coreboot project. +# +#Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +config AMD_NB_CIMX + bool + default n + +source src/northbridge/amd/cimx/rd890/Kconfig diff --git a/src/northbridge/amd/cimx/Makefile.inc b/src/northbridge/amd/cimx/Makefile.inc new file mode 100644 index 0000000..80844c8 --- /dev/null +++ b/src/northbridge/amd/cimx/Makefile.inc @@ -0,0 +1,20 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +subdirs-$(CONFIG_NORTHBRIDGE_AMD_CIMX_RD890) += rd890 diff --git a/src/northbridge/amd/cimx/rd890/Kconfig b/src/northbridge/amd/cimx/rd890/Kconfig new file mode 100644 index 0000000..6731b60 --- /dev/null +++ b/src/northbridge/amd/cimx/rd890/Kconfig @@ -0,0 +1,33 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +config NORTHBRIDGE_AMD_CIMX_RD890 + bool + default n + select AMD_NB_CIMX + +config REDIRECT_NBCIMX_TRACE_TO_SERIAL + bool "Redirect AMD Northbridge CIMX Trace to serial console" + default n + depends on NORTHBRIDGE_AMD_CIMX_RD890 + help + This Option allows you to redirect the AMD Northbridge CIMX + Trace debug information to the serial console. + + Warning: Only enable this option when debuging or tracing AMD CIMX code. diff --git a/src/northbridge/amd/cimx/rd890/Makefile.inc b/src/northbridge/amd/cimx/rd890/Makefile.inc new file mode 100644 index 0000000..5eaefd1 --- /dev/null +++ b/src/northbridge/amd/cimx/rd890/Makefile.inc @@ -0,0 +1,25 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + + +# RD890 Platform Files +romstage-y += early.c + +ramstage-y += late.c + diff --git a/src/northbridge/amd/cimx/rd890/NbPlatform.h b/src/northbridge/amd/cimx/rd890/NbPlatform.h new file mode 100644 index 0000000..824057a --- /dev/null +++ b/src/northbridge/amd/cimx/rd890/NbPlatform.h @@ -0,0 +1,147 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _NB_PLATFORM_H_ +#define _NB_PLATFORM_H_ + +#define SERIAL_OUT_SUPPORT //enable serial output +#define CIMX_DEBUG + +#ifdef CIMX_DEBUG +#define CIMX_TRACE_SUPPORT +#define CIMX_ASSERT_SUPPORT +#endif + +#ifdef CIMX_TRACE_SUPPORT + #define CIMX_INIT_TRACE(Arguments) + #if CONFIG_REDIRECT_NBCIMX_TRACE_TO_SERIAL + #define TRACE_DATA(Ptr, Level) BIOS_DEBUG //always enable + #define CIMX_TRACE(Argument) do {do_printk Argument;} while (0) + #else + #define TRACE_DATA(Ptr, Level) + #define CIMX_TRACE(Argument) + #endif +#else + #define CIMX_TRACE(Argument) + #define CIMX_INIT_TRACE(Arguments) +#endif + +#ifdef CIMX_ASSERT_SUPPORT + #ifdef ASSERT + #undef ASSERT + #define ASSERT CIMX_ASSERT + #endif + #ifdef CIMX_TRACE_SUPPORT + #define CIMX_ASSERT(x) if(!(x)) {\ + LibAmdTraceDebug (CIMX_TRACE_ALL, (CHAR8 *)"ASSERT !!! "__FILE__" - line %d\n", __LINE__); \ + /*__asm {jmp $}; */\ + } + //#define IDS_HDT_CONSOLE(s, args...) do_printk(BIOS_DEBUG, s, ##args) + #else + #define CIMX_ASSERT(x) if(!(x)) {\ + /*__asm {jmp $}; */\ + } + #endif +#else + #define CIMX_ASSERT(x) +#endif + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +//#define STALL(Ptr, TimeUs, Flag) LibAmdSbStall(TimeUs) +#define STALL(Ptr, TimeUs, Flag) LibAmdSbStall(TimeUs, Ptr) + +#ifdef B2_IMAGE +#define REPORT_EVENT(Class, Info, Param1, Param2, Param3, Param4, CfgPtr) LibNbEventLog(Class, Info, Param1, Param2, Param3, Param4, CfgPtr) +#else +#define REPORT_EVENT(Class, Info, Param1, Param2, Param3, Param4, CfgPtr) +#endif + + + +// CIMX configuration parameters +//#define CIMX_B2_IMAGE_BASE_ADDRESS 0xFFF40000 +/** + * PCIEX_BASE_ADDRESS - Define PCIE base address + * + * @param[Option] MOVE_PCIEBAR_TO_F0000000 Set PCIe base address to 0xF7000000 + */ +#ifdef MOVE_PCIEBAR_TO_F0000000 +#define PCIEX_BASE_ADDRESS 0xF7000000 +#else +#define PCIEX_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS +#endif + + + +#define CIMX_S3_SAVE 1 +#include "cbtypes.h" +#include <console/console.h> + +#include "amd.h" //cimx typedef +#include <amdlib.h> +#include "amdAcpiLib.h" +#include "amdAcpiMadt.h" +#include "amdAcpiIvrs.h" +#include "amdSbLib.h" +#include "nbPcie.h" + +//must put before the nbType.h +#include "platform_cfg.h" /*platform dependented configuration */ +#include "nbType.h" + +#include "nbLib.h" +#include "nbDef.h" +#include "nbInit.h" +#include "nbHtInit.h" +#include "nbIommu.h" +#include "nbEventLog.h" +#include "nbRegisters.h" +#include "nbPcieAspm.h" +#include "nbPcieLinkWidth.h" +#include "nbPcieHotplug.h" +#include "nbPciePortRemap.h" +#include "nbPcieWorkarounds.h" +#include "nbPcieCplBuffers.h" +#include "nbPciePllControl.h" +#include "nbMiscInit.h" +#include "nbIoApic.h" +#include "nbPcieSb.h" +#include "nbRecovery.h" +#include "nbMaskedMemoryInit.h" + + +#define FIX_PTR_ADDR(x, y) x + +#define TRACE_ALWAYS 0xffffffff + +#define AmdNbDispatcher NULL + +#define CIMX_TRACE_ALL 0xFFFFFFFF +#define CIMX_NBPOR_TRACE 0xFFFFFFFF +#define CIMX_NBHT_TRACE 0xFFFFFFFF +#define CIMX_NBPCIE_TRACE 0xFFFFFFFF +#define CIMX_NB_TRACE 0xFFFFFFFF +#define CIMX_NBPCIE_MISC 0xFFFFFFFF + +#endif + diff --git a/src/northbridge/amd/cimx/rd890/amd.h b/src/northbridge/amd/cimx/rd890/amd.h new file mode 100644 index 0000000..d99f90f --- /dev/null +++ b/src/northbridge/amd/cimx/rd890/amd.h @@ -0,0 +1,385 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _AMD_H_ +#define _AMD_H_ + +#include "cbtypes.h" + + +#define VOLATILE volatile +#define CALLCONV +#define ROMDATA +#define CIMXAPI EFIAPI + +// +// +// AGESA Types and Definitions +// +// +#ifndef NULL + #define NULL 0 +#endif + + +#define LAST_ENTRY 0xFFFFFFFF +#define IOCF8 0xCF8 +#define IOCFC 0xCFC +#define IN +#define OUT +#define IMAGE_SIGNATURE 'DMA$' + +typedef UINTN AGESA_STATUS; + + +#define AGESA_SUCCESS ((AGESA_STATUS) 0x0) +#define AGESA_ALERT ((AGESA_STATUS) 0x40000000) +#define AGESA_WARNING ((AGESA_STATUS) 0x40000001) +#define AGESA_UNSUPPORTED ((AGESA_STATUS) 0x80000003) +#define AGESA_ERROR ((AGESA_STATUS) 0xC0000001) +#define AGESA_CRITICAL ((AGESA_STATUS) 0xC0000002) +#define AGESA_FATAL ((AGESA_STATUS) 0xC0000003) + +typedef AGESA_STATUS (*CALLOUT_ENTRY) (UINT32 Param1, UINTN Param2, VOID* ConfigPtr); +typedef AGESA_STATUS (*IMAGE_ENTRY) (IN OUT VOID* ConfigPtr); +typedef AGESA_STATUS (*MODULE_ENTRY) (IN OUT VOID* ConfigPtr); + +///This allocation type is used by the AmdCreateStruct entry point +typedef enum { + PreMemHeap = 0, ///< Create heap in cache. + PostMemDram, ///< Create heap in memory. + ByHost ///< Create heap by Host. +} ALLOCATION_METHOD; + +/// These width descriptors are used by the library function, and others, to specify the data size +typedef enum ACCESS_WIDTH { + AccessWidth8 = 1, ///< Access width is 8 bits. + AccessWidth16, ///< Access width is 16 bits. + AccessWidth32, ///< Access width is 32 bits. + AccessWidth64, ///< Access width is 64 bits. + + AccessS3SaveWidth8 = 0x81, ///< Save 8 bits data. + AccessS3SaveWidth16, ///< Save 16 bits data. + AccessS3SaveWidth32, ///< Save 32 bits data. + AccessS3SaveWidth64, ///< Save 64 bits data. +} ACCESS_WIDTH; + + +// AGESA Structures +/// The standard header AMD NB UEFI drivers +typedef struct _AMD_CONFIG_PARAMS { + VOID **PeiServices; ///< Pointer to PEI service table + VOID *StallPpi; ///< Pointer to Stall PPI +// UINT32 Func; + VOID *PcieBasePtr; ///< TBD + CALLOUT_ENTRY CalloutPtr; ///<pointer to local driver callback function + CALLOUT_ENTRY InterfaceCalloutPtr; ///<pointer to external interface driver callback function +} AMD_CONFIG_PARAMS; + + +/// AGESA Binary module header structure +typedef struct _AMD_IMAGE_HEADER { + IN UINT32 Signature; ///< Binary Signature + IN CHAR8 CreatorID[8]; ///< 8 characters ID + IN CHAR8 Version[12]; ///< 12 characters version + IN UINT32 ModuleInfoOffset; ///< Offset of module + IN UINT32 EntryPointAddress; ///< Entry address + IN UINT32 ImageBase; ///< Image base + IN UINT32 RelocTableOffset; ///< Relocate Table offset + IN UINT32 ImageSize; ///< Size + IN UINT16 Checksum; ///< Checksum + IN UINT8 ImageType; ///< Type + IN UINT8 V_Reserved; ///< Reserved +} AMD_IMAGE_HEADER; + + +/// AGESA Binary module header structure +typedef struct _AMD_MODULE_HEADER { + IN UINT32 ModuleHeaderSignature; ///< Module signature + IN CHAR8 ModuleIdentifier[8]; ///< 8 characters ID + IN CHAR8 ModuleVersion[12]; ///< 12 characters version + IN MODULE_ENTRY ModuleDispatcherPtr; ///< A pointer point to dispatcher + IN struct _AMD_MODULE_HEADER *NextBlockPtr; ///< Next module header link +} AMD_MODULE_HEADER; + +/// Extended PCI address format +typedef struct { + IN OUT UINT32 Register:12; ///< Register offset + IN OUT UINT32 Function:3; ///< Function number + IN OUT UINT32 Device:5; ///< Device number + IN OUT UINT32 Bus:8; ///< Bus number + IN OUT UINT32 Segment:4; ///< Segment +} EXT_PCI_ADDR; + +/// Union type for PCI address +typedef union _PCI_ADDR { + IN UINT32 AddressValue; ///< Formal address + IN EXT_PCI_ADDR Address; ///< Extended address +} PCI_ADDR; + +#define FUNC_0 0 // bit-placed for PCI address creation +#define FUNC_1 1 +#define FUNC_2 2 +#define FUNC_3 3 +#define FUNC_4 4 +#define FUNC_5 5 +#define FUNC_6 6 +#define FUNC_7 7 + +// SBDFO - Segment Bus Device Function Offset +// 31:28 Segment (4-bits) +// 27:20 Bus (8-bits) +// 19:15 Device (5-bits) +// 14:12 Function(3-bits) +// 11:00 Offset (12-bits) + +#define MAKE_SBDFO(Seg, Bus, Dev, Fun, Off) ((((UINT32) (Seg)) << 28) | (((UINT32) (Bus)) << 20) | \ + (((UINT32)(Dev)) << 15) | (((UINT32)(Fun)) << 12) | ((UINT32)(Off))) +#define ILLEGAL_SBDFO 0xFFFFFFFF + +/// CPUID data received registers format +typedef struct _CPUID_DATA { + IN OUT UINT32 EAX_Reg; ///< CPUID instruction result in EAX + IN OUT UINT32 EBX_Reg; ///< CPUID instruction result in EBX + IN OUT UINT32 ECX_Reg; ///< CPUID instruction result in ECX + IN OUT UINT32 EDX_Reg; ///< CPUID instruction result in EDX +} CPUID_DATA; + +#define WARM_RESET 1 +#define COLD_RESET 2 + +/// HT frequency for external callbacks +typedef enum { + HT_FREQUENCY_200M = 0, ///< HT speed 200 for external callbacks + HT_FREQUENCY_400M = 2, ///< HT speed 400 for external callbacks + HT_FREQUENCY_600M = 4, ///< HT speed 600 for external callbacks + HT_FREQUENCY_800M = 5, ///< HT speed 800 for external callbacks + HT_FREQUENCY_1000M = 6, ///< HT speed 1000 for external callbacks + HT_FREQUENCY_1200M = 7, ///< HT speed 1200 for external callbacks + HT_FREQUENCY_1400M = 8, ///< HT speed 1400 for external callbacks + HT_FREQUENCY_1600M = 9, ///< HT speed 1600 for external callbacks + HT_FREQUENCY_1800M = 10, ///< HT speed 1800 for external callbacks + HT_FREQUENCY_2000M = 11, ///< HT speed 2000 for external callbacks + HT_FREQUENCY_2200M = 12, ///< HT speed 2200 for external callbacks + HT_FREQUENCY_2400M = 13, ///< HT speed 2400 for external callbacks + HT_FREQUENCY_2600M = 14, ///< HT speed 2600 for external callbacks + HT_FREQUENCY_2800M = 17, ///< HT speed 2800 for external callbacks + HT_FREQUENCY_3000M = 18, ///< HT speed 3000 for external callbacks + HT_FREQUENCY_3200M = 19 ///< HT speed 3200 for external callbacks +} HT_FREQUENCIES; + +#ifndef BIT0 + #define BIT0 0x0000000000000001ull +#endif +#ifndef BIT1 + #define BIT1 0x0000000000000002ull +#endif +#ifndef BIT2 + #define BIT2 0x0000000000000004ull +#endif +#ifndef BIT3 + #define BIT3 0x0000000000000008ull +#endif +#ifndef BIT4 + #define BIT4 0x0000000000000010ull +#endif +#ifndef BIT5 + #define BIT5 0x0000000000000020ull +#endif +#ifndef BIT6 + #define BIT6 0x0000000000000040ull +#endif +#ifndef BIT7 + #define BIT7 0x0000000000000080ull +#endif +#ifndef BIT8 + #define BIT8 0x0000000000000100ull +#endif +#ifndef BIT9 + #define BIT9 0x0000000000000200ull +#endif +#ifndef BIT10 + #define BIT10 0x0000000000000400ull +#endif +#ifndef BIT11 + #define BIT11 0x0000000000000800ull +#endif +#ifndef BIT12 + #define BIT12 0x0000000000001000ull +#endif +#ifndef BIT13 + #define BIT13 0x0000000000002000ull +#endif +#ifndef BIT14 + #define BIT14 0x0000000000004000ull +#endif +#ifndef BIT15 + #define BIT15 0x0000000000008000ull +#endif +#ifndef BIT16 + #define BIT16 0x0000000000010000ull +#endif +#ifndef BIT17 + #define BIT17 0x0000000000020000ull +#endif +#ifndef BIT18 + #define BIT18 0x0000000000040000ull +#endif +#ifndef BIT19 + #define BIT19 0x0000000000080000ull +#endif +#ifndef BIT20 + #define BIT20 0x0000000000100000ull +#endif +#ifndef BIT21 + #define BIT21 0x0000000000200000ull +#endif +#ifndef BIT22 + #define BIT22 0x0000000000400000ull +#endif +#ifndef BIT23 + #define BIT23 0x0000000000800000ull +#endif +#ifndef BIT24 + #define BIT24 0x0000000001000000ull +#endif +#ifndef BIT25 + #define BIT25 0x0000000002000000ull +#endif +#ifndef BIT26 + #define BIT26 0x0000000004000000ull +#endif +#ifndef BIT27 + #define BIT27 0x0000000008000000ull +#endif +#ifndef BIT28 + #define BIT28 0x0000000010000000ull +#endif +#ifndef BIT29 + #define BIT29 0x0000000020000000ull +#endif +#ifndef BIT30 + #define BIT30 0x0000000040000000ull +#endif +#ifndef BIT31 + #define BIT31 0x0000000080000000ull +#endif +#ifndef BIT32 + #define BIT32 0x0000000100000000ull +#endif +#ifndef BIT33 + #define BIT33 0x0000000200000000ull +#endif +#ifndef BIT34 + #define BIT34 0x0000000400000000ull +#endif +#ifndef BIT35 + #define BIT35 0x0000000800000000ull +#endif +#ifndef BIT36 + #define BIT36 0x0000001000000000ull +#endif +#ifndef BIT37 + #define BIT37 0x0000002000000000ull +#endif +#ifndef BIT38 + #define BIT38 0x0000004000000000ull +#endif +#ifndef BIT39 + #define BIT39 0x0000008000000000ull +#endif +#ifndef BIT40 + #define BIT40 0x0000010000000000ull +#endif +#ifndef BIT41 + #define BIT41 0x0000020000000000ull +#endif +#ifndef BIT42 + #define BIT42 0x0000040000000000ull +#endif +#ifndef BIT43 + #define BIT43 0x0000080000000000ull +#endif +#ifndef BIT44 + #define BIT44 0x0000100000000000ull +#endif +#ifndef BIT45 + #define BIT45 0x0000200000000000ull +#endif +#ifndef BIT46 + #define BIT46 0x0000400000000000ull +#endif +#ifndef BIT47 + #define BIT47 0x0000800000000000ull +#endif +#ifndef BIT48 + #define BIT48 0x0001000000000000ull +#endif +#ifndef BIT49 + #define BIT49 0x0002000000000000ull +#endif +#ifndef BIT50 + #define BIT50 0x0004000000000000ull +#endif +#ifndef BIT51 + #define BIT51 0x0008000000000000ull +#endif +#ifndef BIT52 + #define BIT52 0x0010000000000000ull +#endif +#ifndef BIT53 + #define BIT53 0x0020000000000000ull +#endif +#ifndef BIT54 + #define BIT54 0x0040000000000000ull +#endif +#ifndef BIT55 + #define BIT55 0x0080000000000000ull +#endif +#ifndef BIT56 + #define BIT56 0x0100000000000000ull +#endif +#ifndef BIT57 + #define BIT57 0x0200000000000000ull +#endif +#ifndef BIT58 + #define BIT58 0x0400000000000000ull +#endif +#ifndef BIT59 + #define BIT59 0x0800000000000000ull +#endif +#ifndef BIT60 + #define BIT60 0x1000000000000000ull +#endif +#ifndef BIT61 + #define BIT61 0x2000000000000000ull +#endif +#ifndef BIT62 + #define BIT62 0x4000000000000000ull +#endif +#ifndef BIT63 + #define BIT63 0x8000000000000000ull +#endif + +#ifdef ASSERT + #undef ASSERT + #define ASSERT(x) +#endif + +#endif diff --git a/src/northbridge/amd/cimx/rd890/cbtypes.h b/src/northbridge/amd/cimx/rd890/cbtypes.h new file mode 100644 index 0000000..ade55d7 --- /dev/null +++ b/src/northbridge/amd/cimx/rd890/cbtypes.h @@ -0,0 +1,71 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 - 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _CBTYPES_H_ +#define _CBTYPES_H_ + +//#include <stdint.h> + +/* +typedef int64_t __int64; +typedef void VOID; +typedef uint32_t UINTN;// +typedef int8_t CHAR8; +typedef uint8_t UINT8; +typedef uint16_t UINT16; +typedef uint32_t UINT32; +typedef uint64_t UINT64; +*/ +typedef signed long long __int64; +typedef void VOID; +typedef unsigned int UINTN;// +typedef signed char CHAR8; +typedef unsigned char UINT8; +typedef unsigned short UINT16; +typedef unsigned int UINT32; +typedef signed int INT32; +typedef unsigned long long UINT64; + +#define TRUE 1 +#define FALSE 0 +typedef unsigned char BOOLEAN; + +#ifndef VOLATILE +#define VOLATILE volatile +#endif + +#ifndef IN +#define IN +#endif +#ifndef OUT +#define OUT +#endif + +//porting.h +#ifndef CONST +#define CONST const +#endif +#ifndef STATIC +#define STATIC static +#endif +#ifndef VOLATILE +#define VOLATILE volatile +#endif + +#endif diff --git a/src/northbridge/amd/cimx/rd890/chip.h b/src/northbridge/amd/cimx/rd890/chip.h new file mode 100644 index 0000000..c2f985b --- /dev/null +++ b/src/northbridge/amd/cimx/rd890/chip.h @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#ifndef _CIMX_RD890_CHIP_H_ +#define _CIMX_RD890_CHIP_H_ + +extern struct chip_operations northbridge_amd_cimx_rd890_ops; + +/** + * RD890 specific device configuration + */ +struct northbridge_amd_cimx_rd890_config +{ + u8 gpp1_configuration; + u8 gpp2_configuration; + u8 gpp3a_configuration; + u16 port_enable; +}; + +#endif /* _CIMX_RD890_CHIP_H_ */ + diff --git a/src/northbridge/amd/cimx/rd890/early.c b/src/northbridge/amd/cimx/rd890/early.c new file mode 100644 index 0000000..8008223 --- /dev/null +++ b/src/northbridge/amd/cimx/rd890/early.c @@ -0,0 +1,113 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include "NbPlatform.h" +#include "rd890_cfg.h" +#include "nb_cimx.h" + + +/** + * @brief disable GPP1 Port0,1, GPP2, GPP3a Port0,1,2,3,4,5, GPP3b + * + * SR5650/5670/5690 RD890 chipset, read pci config space hang at POR, + * Disable all Pcie Bridges to work around It. + */ +void sr56x0_rd890_disable_pcie_bridge(void) +{ + u32 nb_dev; + u32 mask; + u32 val; + AMD_NB_CONFIG_BLOCK cfg_block; + AMD_NB_CONFIG_BLOCK *cfg_ptr = &cfg_block; + AMD_NB_CONFIG *nb_cfg = &(cfg_block.Northbridges[0]); + + nb_cfg->ConfigPtr = &cfg_ptr; + nb_dev = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0); + val = (1 << 2) | (1 << 3); /*GPP1*/ + val |= (1 << 4) | (1 << 5) | (1 << 6) | (1 << 7) | (1 << 16) | (1 << 17); /*GPP3a*/ + val |= (1 << 18) | (1 << 19); /*GPP2*/ + val |= (1 << 20); /*GPP3b*/ + mask = ~val; + LibNbPciIndexRMW(nb_dev | NB_MISC_INDEX, NB_MISC_REG0C, + AccessS3SaveWidth32, + mask, + val, + nb_cfg); +} + + +/** + * @brief South Bridge CIMx romstage entry, + * wrapper of AmdPowerOnResetInit entry point. + */ +void nb_Poweron_Init(void) +{ + NB_CONFIG nb_cfg[MAX_NB_COUNT]; + HT_CONFIG ht_cfg[MAX_NB_COUNT]; + PCIE_CONFIG pcie_cfg[MAX_NB_COUNT]; + AMD_NB_CONFIG_BLOCK gConfig; + AMD_NB_CONFIG_BLOCK *ConfigPtr = &gConfig; + AGESA_STATUS status; + + printk(BIOS_DEBUG, "cimx/rd890 early.c %s() Start\n", __func__); + CIMX_INIT_TRACE(); + CIMX_TRACE((BIOS_DEBUG, "NbPowerOnResetInit entry\n")); + rd890_cimx_config(&gConfig, &nb_cfg[0], &ht_cfg[0], &pcie_cfg[0]); + + if (ConfigPtr->StandardHeader.CalloutPtr != NULL) { + ConfigPtr->StandardHeader.CalloutPtr(CB_AmdSetNbPorConfig, 0, &gConfig); + } + + status = AmdPowerOnResetInit(&gConfig); + printk(BIOS_DEBUG, "cimx/rd890 early.c %s() End. return status=%x\n", __func__, status); +} + +/** + * @brief South Bridge CIMx romstage entry, + * wrapper of AmdHtInit entry point. + */ +void nb_Ht_Init(void) +{ + AGESA_STATUS status; + NB_CONFIG nb_cfg[MAX_NB_COUNT]; + HT_CONFIG ht_cfg[MAX_NB_COUNT]; + PCIE_CONFIG pcie_cfg[MAX_NB_COUNT]; + AMD_NB_CONFIG_BLOCK gConfig; + AMD_NB_CONFIG_BLOCK *ConfigPtr = &gConfig; + u32 i; + + rd890_cimx_config(&gConfig, &nb_cfg[0], &ht_cfg[0], &pcie_cfg[0]); + + //Initialize HT structure + LibSystemApiCall(AmdHtInitializer, &gConfig); + for (i = 0; i < MAX_NB_COUNT; i ++) { + if (ConfigPtr->StandardHeader.CalloutPtr != NULL) { + ConfigPtr->StandardHeader.CalloutPtr(CB_AmdSetHtConfig, 0, (VOID*)&(gConfig.Northbridges[i])); + } + } + + status = LibSystemApiCall(AmdHtInit, &gConfig); + printk(BIOS_DEBUG, "AmdHtInit status: %x\n", status); +} + +void nb_S3_Init(void) +{ + //TODO +} diff --git a/src/northbridge/amd/cimx/rd890/late.c b/src/northbridge/amd/cimx/rd890/late.c new file mode 100644 index 0000000..208e5f1 --- /dev/null +++ b/src/northbridge/amd/cimx/rd890/late.c @@ -0,0 +1,257 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <console/console.h> +#include <device/device.h> +#include <arch/ioapic.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include "NbPlatform.h" +#include "nb_cimx.h" +#include "rd890_cfg.h" + + +/** + * Global RD890 CIMX Configuration structure + */ +static NB_CONFIG nb_cfg[MAX_NB_COUNT]; +static HT_CONFIG ht_cfg[MAX_NB_COUNT]; +static PCIE_CONFIG pcie_cfg[MAX_NB_COUNT]; +static AMD_NB_CONFIG_BLOCK gConfig; + + +/** + * Reset PCIE Cores, Training the Ports selected by port_enable of devicetree + * After this call EP are fully operational on particular NB + */ +void nb_Pcie_Early_Init(void) +{ + LibSystemApiCall(AmdPcieEarlyInit, &gConfig); //AmdPcieEarlyInit(&gConfig); +} + +void nb_Pcie_Late_Init(void) +{ + LibSystemApiCall(AmdPcieLateInit, &gConfig); +} + +void nb_Early_Post_Init(void) +{ + LibSystemApiCall(AmdEarlyPostInit, &gConfig); +} + +void nb_Mid_Post_Init(void) +{ + LibSystemApiCall(AmdMidPostInit, &gConfig); +} + +void nb_Late_Post_Init(void) +{ + LibSystemApiCall(AmdLatePostInit, &gConfig); +} + +static void rd890_enable(device_t dev) +{ + u32 address = 0; + u32 mask; + u32 val; + u32 devfn; + u32 port; + AMD_NB_CONFIG *NbConfigPtr = NULL; + + u8 nb_index = 0; /* The first IO Hub, TODO: other NBs */ + address = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0); + NbConfigPtr = &(gConfig.Northbridges[nb_index]); + + devfn = dev->path.pci.devfn; + port = devfn >> 3; + printk(BIOS_INFO, "rd890_enable "); + printk(BIOS_INFO, "Bus-%x Dev-%X Fun-%X, enable=%x\n", + 0, (devfn >> 3), (devfn & 0x07), dev->enabled); + if (port != 0) { + if (dev->enabled) { + NbConfigPtr->pPcieConfig->PortConfiguration[port].ForcePortDisable = OFF; + } else { + NbConfigPtr->pPcieConfig->PortConfiguration[port].ForcePortDisable = ON; + } + } + + switch (port) { + case 0x0: /* Root Complex, and ClkConfig */ + + if ((devfn & 0x07) == 1) { /* skip dev-0 fun-1 */ + break; + } + + /* CIMX configuration defualt initialize */ + rd890_cimx_config(&gConfig, &nb_cfg[0], &ht_cfg[0], &pcie_cfg[0]); + if (gConfig.StandardHeader.CalloutPtr != NULL) { + /* NOTE: not use LibNbCallBack */ + gConfig.StandardHeader.CalloutPtr(CB_AmdSetPcieEarlyConfig, (u32)dev, (VOID*)NbConfigPtr); + } + /* Reset PCIE Cores, Training the Ports selected by port_enable of devicetree + * After this call EP are fully operational on particular NB + */ + nb_Pcie_Early_Init(); + break; + + case 0x2: /* Gpp1 Port0 */ + case 0x3: /* Gpp1 Port1 */ + mask = ~(1 << port); + val = (dev->enabled ? 0 : 1) << port; + LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr); + break; + + case 0x4: /* Gpp3a Port0 */ + case 0x5: /* Gpp3a Port1 */ + case 0x6: /* Gpp3a Port2 */ + case 0x7: /* Gpp3a Port3 */ + mask = ~(1 << port); + val = (dev->enabled ? 0 : 1) << port; + LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr); + break; + + case 0x8: /* SB ALink */ + mask = ~(1 << 6); + val = (dev->enabled ? 1 : 0) << 6; + LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr); + break; + + case 0x9: /* Gpp3a Port4 */ + case 0xa: /* Gpp3a Port5 */ + mask = ~(1 << (7 + port)); + val = (dev->enabled ? 0 : 1) << (7 + port); + LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr); + break; + + case 0xb: /* Gpp2 Port0 */ + case 0xc: /* Gpp2 Port1 */ + mask = ~(1 << (7 + port)); + val = (dev->enabled ? 0 : 1) << (7 + port); + LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr); + break; + + case 0xd: /* Gpp3b */ + mask = ~(1 << (7 + port)); + val = (dev->enabled ? 0 : 1) << (7 + port); + LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr); + + /* Init NB at Early Post */ + if (gConfig.StandardHeader.CalloutPtr != NULL) { + gConfig.StandardHeader.CalloutPtr(CB_AmdSetEarlyPostConfig, 0, (VOID*)NbConfigPtr); + } + nb_Early_Post_Init();// + if (gConfig.StandardHeader.CalloutPtr != NULL) { + gConfig.StandardHeader.CalloutPtr(CB_AmdSetMidPostConfig, 0, (VOID*)NbConfigPtr); + } + nb_Mid_Post_Init(); + nb_Pcie_Late_Init(); + if (gConfig.StandardHeader.CalloutPtr != NULL) { + gConfig.StandardHeader.CalloutPtr(CB_AmdSetLatePostConfig, 0, (VOID*)NbConfigPtr); + } + nb_Late_Post_Init(); + break; + + default: + printk(BIOS_INFO, "Buggy Device Tree\n"); + break; + } +} + +struct chip_operations northbridge_amd_cimx_rd890_ops = { + CHIP_NAME("ATI rd890") + .enable_dev = rd890_enable, +}; + + +static void ioapic_init(struct device *dev) +{ + u32 ioapic_base; + + pci_write_config32(dev, 0xF8, 0x1); + ioapic_base = pci_read_config32(dev, 0xFC) & 0xfffffff0; + setup_ioapic(ioapic_base, 1); +} + +static void rd890_read_resource(struct device *dev) +{ + pci_dev_read_resources(dev); + + /* rpr6.2.(1). Write the Base Address Register (BAR) */ + pci_write_config32(dev, 0xF8, 0x1); /* set IOAPIC's index as 1 and make sure no one changes it. */ + pci_get_resource(dev, 0xFC); /* APIC located in sr5690 */ + + compact_resources(dev); +} + +/* If IOAPIC's index changes, we should replace the pci_dev_set_resource(). */ +static void rd890_set_resources(struct device *dev) +{ + pci_write_config32(dev, 0xF8, 0x1); /* set IOAPIC's index as 1 and make sure no one changes it. */ + pci_dev_set_resources(dev); +} + +static struct pci_operations lops_pci = { + .set_subsystem = pci_dev_set_subsystem, +}; + +static struct device_operations ht_ops = { + .read_resources = rd890_read_resource, + .set_resources = rd890_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = ioapic_init, + .scan_bus = 0, + .ops_pci = &lops_pci, +}; + +static const struct pci_driver ht_driver_sr5690 __pci_driver = { + .ops = &ht_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_AMD_SR5690_HT, +}; + +static const struct pci_driver ht_driver_sr5670 __pci_driver = { + .ops = &ht_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_AMD_SR5670_HT, +}; + +static const struct pci_driver ht_driver_sr5650 __pci_driver = { + .ops = &ht_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_AMD_SR5650_HT, +}; + +static const struct pci_driver ht_driver_rd890tv __pci_driver = { + .ops = &ht_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_AMD_RD890TV_HT, +}; + +static const struct pci_driver ht_driver_rd890 __pci_driver = { + .ops = &ht_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_AMD_RD890_HT, +}; + +static const struct pci_driver ht_driver_990fx __pci_driver = { + .ops = &ht_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_AMD_990FX_HT, +}; diff --git a/src/northbridge/amd/cimx/rd890/nb_cimx.h b/src/northbridge/amd/cimx/rd890/nb_cimx.h new file mode 100644 index 0000000..a6f77db --- /dev/null +++ b/src/northbridge/amd/cimx/rd890/nb_cimx.h @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _NB_CIMX_H_ +#define _NB_CIMX_H_ + +/** + * @brief disable GPP1 Port0,1, GPP2, GPP3a Port0,1,2,3,4,5, GPP3b + * + * SR5650/5670/5690 RD890 chipset, read pci config space hang at POR, + * Disable all Pcie Bridges to work around It. + */ +void sr56x0_rd890_disable_pcie_bridge(void); + +/** + * Northbridge CIMX entries point + */ +void nb_Poweron_Init(void); +void nb_Ht_Init(void); +void nb_S3_Init(void); +void nb_Early_Post_Init(void); +void nb_Mid_Post_Init(void); +void nb_Late_Post_Init(void); +void nb_Pcie_Early_Init(void); +void nb_Pcie_Late_Init(void); + +#endif//_RD890_EARLY_H_ +

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New patch to review for coreboot: 5364fa9 pci_ids: Add AMD F15h model 00-0f and F10h cpu HT device pci ids
by Kerry Sheh 07 Feb '12

07 Feb '12

Kerry Sheh (shekairui(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/609 -gerrit commit 5364fa99949aae6485bf9a4f123f48a09b348cba Author: Kerry Sheh <shekairui(a)gmail.com> Date: Tue Feb 7 18:45:55 2012 +0800 pci_ids: Add AMD F15h model 00-0f and F10h cpu HT device pci ids Change-Id: I13905f5730d08510c8f0f6e652f41a679d618d1b Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> --- src/include/device/pci_ids.h | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index fcd31c0..60399ef 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -284,6 +284,9 @@ #define PCI_DEVICE_ID_ATI_RADEON_RC 0x5146 #define PCI_DEVICE_ID_ATI_RADEON_RD 0x5147 +#define PCI_DEVICE_ID_AMD_15H_MODEL_000F_NB_HT 0x1600 +#define PCI_DEVICE_ID_AMD_10H_NB_HT 0x1200 + #define PCI_DEVICE_ID_ATI_SB600_LPC 0x438D #define PCI_DEVICE_ID_ATI_SB600_SATA 0x4380 #define PCI_DEVICE_ID_ATI_SB600_IDE 0x438C

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Patch merged into coreboot/master: b7929ad Fix multipleVGA cards resource conflict on Windows
by gerrit＠coreboot.org 06 Feb '12

06 Feb '12

the following patch was just integrated into master: commit b7929add7bf1b40795e0a16ab08fc47858971ccc Author: Kerry Sheh <shekairui(a)gmail.com> Date: Wed Jan 4 20:51:47 2012 +0800 Fix multipleVGA cards resource conflict on Windows If multiple VGA-compatible legacy graphic cards decode the IO range 3B0-3BB, 3C0-3DF and MEM range A00000-BFFFF. Windows 7 complain a resource conflict, so only one VGA card can works at the same time. There is a discussion in coreboot mail list before, please reference thread: "how to prevent legacy resource conflictwith multipleVGA cards" http://www.coreboot.org/pipermail/coreboot/2010-October/061508.html Linux using VGA Arbiter module(vgaarb) to resolve this resource conflict, Please see the following linux dmesg log, more information can be found in Linux source dir Documentation/vgaarbiter.txt. But it seems that windows don't dealwith this conflict. ~# dmesg | grep -i vgaarb [ 0.774076] vgaarb: device added: PCI:0000:00:01.0,decodes=io+mem,owns=io+mem [ 0.776065] vgaarb: device added: PCI:0000:01:00.0,decodes=io+mem,owns=none,l [ 0.780051] vgaarb: loaded [ 0.784049] vgaarb: bridge control possible 0000:01:00.0 [ 0.788050] vgaarb: bridge control possible 0000:00:01.0 For the second legacy graphic device, coreboot already disabled the IO and MEM decode in function set_vga_bridge_bits(). But it will be enabled again in function pci_set_resource(), if the second legacy vga-compatible graphic device take any IO/MEM resources. Following log printed by enable_resources() shows the problem: ...snip... PCI: 00:00.0 cmd <- 06 PCI: 00:01.0 subsystem <- 1022/1410 PCI: 00:01.0 cmd <- 07 <== The first graphic device PCI: 00:01.1 subsystem <- 1022/1410 PCI: 00:01.1 cmd <- 02 PCI: 00:02.0 bridge ctrl <- 0003 PCI: 00:02.0 cmd <- 07 ...snip... PCI: 01:00.0 cmd <- 03 <== The second graphic device PCI: 01:00.1 cmd <- 02 PCI: 02:00.0 cmd <- 02 PCI: 03:00.0 cmd <- 03 done. ...snip... The IO & MEM decoding on the second vga graphic device should be disabled. Please reference PCI spec. section 3.10 in detail. set_vga_bridge_bits() would do this work for us, it did the right thing, but was put to the wrong place, the setting would be overwritten by assign_resources() later. In order to make sure the set_vga_bridge_bits() setting not be overwritten by others, moving the call of set_vga_bridge_bits() to the end of dev_configure(), instead of at the beginning. This patch resolved the dual graphic cards resource conflict in windows7, multiple vga-compatible graphic cards can work together in windows7. Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Change-Id: I0de5e3761b51e2723d9c1dc0c39fff692e3a779d Build-Tested: build bot (Jenkins) at Wed Jan 4 13:17:09 2012, giving +1 Reviewed-By: Marc Jones <marcj303(a)gmail.com> at Tue Feb 7 00:32:50 2012, giving +2 See http://review.coreboot.org/489 for details. -gerrit

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Patch merged into coreboot/master: 9f6afb5 Inagua: Indent and wihtespace cleanup
by gerrit＠coreboot.org 06 Feb '12

06 Feb '12

the following patch was just integrated into master: commit 9f6afb597ae330d2246182bb0878fb76bc1212bd Author: Kerry Sheh <shekairui(a)gmail.com> Date: Thu Jan 19 13:25:55 2012 +0800 Inagua: Indent and wihtespace cleanup Change-Id: Ie574e08f138c88084c8ce06d0d0acc489013e3d7 Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Build-Tested: build bot (Jenkins) at Thu Jan 19 05:51:59 2012, giving +1 See http://review.coreboot.org/547 for details. -gerrit

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Patch merged into coreboot/master: cabbc86 Inagua: mainboard specific GPIO setting
by gerrit＠coreboot.org 06 Feb '12

06 Feb '12

the following patch was just integrated into master: commit cabbc861db8d8551fb7ef725b3ce6cbbbb507996 Author: Kerry Sheh <shekairui(a)gmail.com> Date: Thu Jan 19 13:18:36 2012 +0800 Inagua: mainboard specific GPIO setting Pcie device connected to Hudson/sb800 southbridge GPP training can works, by applying this mainbaind specific GPIO PCIE De-Assert setting. Change-Id: I563b2e6354a958a28f5d0162e7a4d60aa437fb9b Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Build-Tested: build bot (Jenkins) at Thu Jan 19 06:23:12 2012, giving +1 Reviewed-By: Marc Jones <marcj303(a)gmail.com> at Tue Feb 7 00:04:45 2012, giving +2 See http://review.coreboot.org/543 for details. -gerrit

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coreboot February 2012