coreboot January 2012

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Patch merged into coreboot/master: 99b78c2 pcengines: align VENDOR_ and BOARD_ names for PC engines
by gerrit＠coreboot.org 30 Jan '12

30 Jan '12

the following patch was just integrated into master: commit 99b78c2949cb8d61ffb5d2941dcfa7e12405f664 Author: Philip Prindeville <philipp(a)redfish-solutions.com> Date: Wed Jan 18 00:31:50 2012 -0700 pcengines: align VENDOR_ and BOARD_ names for PC engines Coming changes to abuild require that VENDOR_ and BOARD_ names have common suffixes. Change-Id: I44cf759dd3b2d02c525eb325dc9c5c989f172ac5 Signed-off-by: Philip Prindeville <philipp(a)redfish-solutions.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Mon Jan 30 09:59:11 2012, giving +2 See http://review.coreboot.org/548 for details. -gerrit

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Patch set updated for coreboot: 0d44787 libpayload: Refactor highlevel CMOS access
by Patrick Georgi 29 Jan '12

29 Jan '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/583 -gerrit commit 0d4478753226d92213f295b2cc72c2b098a5c279 Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Mon Jan 16 10:14:24 2012 +0100 libpayload: Refactor highlevel CMOS access This will allow using libpayload functions to access CMOS data in template files in RAM or CBFS. Change-Id: I323ed625e657cbdc1fae8c279a82ee578e83ad00 Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> --- payloads/libpayload/drivers/options.c | 68 ++++++++++++++++++++---------- payloads/libpayload/include/libpayload.h | 11 +++++ 2 files changed, 56 insertions(+), 23 deletions(-) diff --git a/payloads/libpayload/drivers/options.c b/payloads/libpayload/drivers/options.c index e3f0847..61e6cc5 100644 --- a/payloads/libpayload/drivers/options.c +++ b/payloads/libpayload/drivers/options.c @@ -30,7 +30,17 @@ #include <libpayload.h> #include <coreboot_tables.h> -static int options_checksum_valid(void) +struct nvram_accessor *use_nvram = &(struct nvram_accessor) { + nvram_read, + nvram_write +}; + +struct cb_cmos_option_table *get_system_option_table(void) +{ + return phys_to_virt(lib_sysinfo.option_table); +} + +static int options_checksum_valid(const struct nvram_accessor *nvram) { int i; int range_start = lib_sysinfo.cmos_range_start / 8; @@ -39,15 +49,15 @@ static int options_checksum_valid(void) u16 checksum = 0, checksum_old; for(i = range_start; i <= range_end; i++) { - checksum += nvram_read(i); + checksum += nvram->read(i); } - checksum_old = ((nvram_read(checksum_location)<<8) | nvram_read(checksum_location+1)); + checksum_old = ((nvram->read(checksum_location)<<8) | nvram->read(checksum_location+1)); return (checksum_old == checksum); } -void fix_options_checksum(void) +void fix_options_checksum_with(const struct nvram_accessor *nvram) { int i; int range_start = lib_sysinfo.cmos_range_start / 8; @@ -56,14 +66,19 @@ void fix_options_checksum(void) u16 checksum = 0; for(i = range_start; i <= range_end; i++) { - checksum += nvram_read(i); + checksum += nvram->read(i); } - nvram_write((checksum >> 8), checksum_location); - nvram_write((checksum & 0xff), checksum_location + 1); + nvram->write((checksum >> 8), checksum_location); + nvram->write((checksum & 0xff), checksum_location + 1); +} + +void fix_options_checksum(void) +{ + fix_options_checksum_with(use_nvram); } -static int get_cmos_value(u32 bitnum, u32 len, void *valptr) +static int get_cmos_value(const struct nvram_accessor *nvram, u32 bitnum, u32 len, void *valptr) { u8 *value = (u8 *)valptr; int offs = 0; @@ -76,7 +91,7 @@ static int get_cmos_value(u32 bitnum, u32 len, void *valptr) /* Handle single byte or less */ if(len <= 8) { - reg8 = nvram_read(addr); + reg8 = nvram->read(addr); reg8 >>= bit; value[0] = reg8 & ((1 << len) -1); return 0; @@ -85,13 +100,13 @@ static int get_cmos_value(u32 bitnum, u32 len, void *valptr) /* When handling more than a byte, copy whole bytes */ while (len > 0) { len -= 8; - value[offs++]=nvram_read(addr++); + value[offs++]=nvram->read(addr++); } return 0; } -static int set_cmos_value(u32 bitnum, u32 len, void *valptr) +static int set_cmos_value(const struct nvram_accessor *nvram, u32 bitnum, u32 len, void *valptr) { u8 *value = (u8 *)valptr; int offs = 0; @@ -104,17 +119,17 @@ static int set_cmos_value(u32 bitnum, u32 len, void *valptr) /* Handle single byte or less */ if (len <= 8) { - reg8 = nvram_read(addr); + reg8 = nvram->read(addr); reg8 &= ~(((1 << len) - 1) << bit); reg8 |= (value[0] & ((1 << len) - 1)) << bit; - nvram_write(reg8, addr); + nvram->write(reg8, addr); return 0; } /* When handling more than a byte, copy whole bytes */ while (len > 0) { len -= 8; - nvram_write(value[offs++], addr++); + nvram->write(value[offs++], addr++); } return 0; @@ -139,14 +154,14 @@ static struct cb_cmos_entries *lookup_cmos_entry(struct cb_cmos_option_table *op return NULL; } -int get_option_from(struct cb_cmos_option_table *option_table, void *dest, char *name) +int get_option_with(const struct nvram_accessor *nvram, struct cb_cmos_option_table *option_table, void *dest, char *name) { struct cb_cmos_entries *cmos_entry = lookup_cmos_entry(option_table, name); if (cmos_entry) { - if(get_cmos_value(cmos_entry->bit, cmos_entry->length, dest)) + if(get_cmos_value(nvram, cmos_entry->bit, cmos_entry->length, dest)) return 1; - if(!options_checksum_valid()) + if(!options_checksum_valid(nvram)) return 1; return 0; @@ -154,21 +169,28 @@ int get_option_from(struct cb_cmos_option_table *option_table, void *dest, char return 1; } +int get_option_from(struct cb_cmos_option_table *option_table, void *dest, char *name) +{ + return get_option_with(use_nvram, option_table, dest, name); +} + int get_option(void *dest, char *name) { - struct cb_cmos_option_table *option_table = phys_to_virt(lib_sysinfo.option_table); - return get_option_from(option_table, dest, name); + return get_option_from(get_system_option_table(), dest, name); } -int set_option(void *value, char *name) +int set_option_with(const struct nvram_accessor *nvram, struct cb_cmos_option_table *option_table, void *value, char *name) { - struct cb_cmos_option_table *option_table = phys_to_virt(lib_sysinfo.option_table); struct cb_cmos_entries *cmos_entry = lookup_cmos_entry(option_table, name); if (cmos_entry) { - set_cmos_value(cmos_entry->bit, cmos_entry->length, value); - fix_options_checksum(); + set_cmos_value(nvram, cmos_entry->bit, cmos_entry->length, value); + fix_options_checksum_with(nvram); return 0; } return 1; } +int set_option(void *value, char *name) +{ + return set_option_with(use_nvram, get_system_option_table(), value, name); +} diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h index d9f7d21..91156e5 100644 --- a/payloads/libpayload/include/libpayload.h +++ b/payloads/libpayload/include/libpayload.h @@ -194,9 +194,20 @@ void video_console_set_cursor(unsigned int cursorx, unsigned int cursory); /** @} */ /* drivers/option.c */ +struct nvram_accessor { + u8 (*read)(u8 reg); + void (*write)(u8 val, u8 reg); +}; + +extern struct nvram_accessor *use_nvram; + +struct cb_cmos_option_table *get_system_option_table(void); +void fix_options_checksum_with(const struct nvram_accessor *nvram); void fix_options_checksum(void); +int get_option_with(const struct nvram_accessor *nvram, struct cb_cmos_option_table *option_table, void *dest, char *name); int get_option_from(struct cb_cmos_option_table *option_table, void *dest, char *name); int get_option(void *dest, char *name); +int set_option_with(const struct nvram_accessor *nvram, struct cb_cmos_option_table *option_table, void *value, char *name); int set_option(void *value, char *name); /**

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Trying to port abit A-S78H
by Prakash Punnoor 29 Jan '12

29 Jan '12

Hi, as a noob I am trying to make a port based on the mahagony fam10, as the abit is also an AMD RS780/SB700 board. I have a Phenom II X4 840 installed, so I guess selecting fam10 is correct? I also adjusted the sources to use the correct superio (Winbond W83627DHG). Unfortunately the motherboard doesn't have serial ports, so I am debugging using a port80 diagnostics card... (Should I actually enable the com ports in devicetree.cb?) So, I cannot make coreboot boot. On cold start it seems to hang in src/southbridge/amd/sb700/reset.c in soft_reset. set_bios_reset seems sucessful, but I get no post code after outb(0x06, 0x0cf9). Any idea, what I can try? If I do a warm start (ie: booting with factory bios, flashing coreboot image and then reset) I get further, but it hangs somewhere in dev_enable. Probably my set_pcie_dereset and/or my devicetree.cb is wrong? How to find out the correct GPIOs for the former? But before attacking these problems, I'd like to solve the early problem on cold start. Any hints? (More infos, which are probably irrelevant at this point: I have seabios as payload, included the vga bios, which I extracted from factory bios and set coreboot rom execution off.) Regards, Prakash

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FOSDEM 2012
by Carl-Daniel Hailfinger 28 Jan '12

28 Jan '12

Hey, it seems we forgot to apply for a devroom (well, at least I didn't see anything on the mailing list). Should we submit talks to the individual devrooms? Should we ask for a coreboot/flashrom booth/table? Regards, Carl-Daniel

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crossgcc build problems on openSUSE 12.1 x86_64
by Carl-Daniel Hailfinger 28 Jan '12

28 Jan '12

Hi, crossgcc won't build on openSUSE 12.1 x86_64 because the gmp libraries end up in xgcc/lib64/ (as designed) but mpfr expects them to be in xgcc/lib/ (why?). Workaround is to add a symlink xgcc/lib -> xgcc/lib64 . autoconf is claimed to be needed to build binutils (at least according to buildgcc), but buildgcc ignores a missing autoconf and proceeds anyway. That's not a problem, binutils builds just fine. I wanted to give other openSUSE 12.1 users a heads-up and make the solution searchable via the mailing list archive. Regards, Carl-Daniel -- http://www.hailfinger.org/

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Patch set updated for coreboot: faa6beb northbridge/intel/i945: CHECK_SLFRCS_ON_RESUME Kconfig option
by Peter Stuge 27 Jan '12

27 Jan '12

Peter Stuge (peter(a)stuge.se) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/590 -gerrit commit faa6bebeaa2dbdacb9333d20e5a2f6f52b21a3f0 Author: Peter Stuge <peter(a)stuge.se> Date: Fri Jan 27 22:17:09 2012 +0100 northbridge/intel/i945: CHECK_SLFRCS_ON_RESUME Kconfig option Originally brought up by Sven Schnelle in March 2011 http://patchwork.coreboot.org/patch/2801/ http://www.coreboot.org/pipermail/coreboot/2011-March/064277.html On some mainboards it may be neccessary to reset early during resume from S3 if the SLFRCS register indicates that a memory channel is not guaranteed to be in self-refresh. On other mainboards, such as Lenovo X60 and T60, the check always creates false positives, effectively making it impossible to resume. The SLFRCS register is documented on page 197 of Mobile Intel® 945 Express Chipset Family Datasheet Document Number: 309219-006 which is publically available, and the register indicates if a memory channel is guaranteed to be in self-refresh mode (if bit = 1), or that a memory channel *may or may not be* in self-refresh mode (if bit = 0). The register can thus only be used to positively learn that memory is in self-refresh. It is not known for sure that memory is *not* in self-refresh. The register is reset by the PWROK signal, which *should* go low during S3, and go high again when resuming, so it is unsurprising that SLFRCS has already been cleared when we read the register. Sven's measurements of the CKE signal on a ThinkPad shows that memory remains in self-refresh indefinitely, until coreboot re-initializes the memory controller, even when SLFRCS bits were = 0. Boards which require a warm reset when SLFRCS bits are cleared must now explicitly enable the check in the mainboard Kconfig file. This commit selects the new option in all existing i945 mainboards. A follow-up commit will remove the option for ThinkPads. Change-Id: I02320675efb8fde05c371ef243ba5093a4da6d11 Signed-off-by: Peter Stuge <peter(a)stuge.se> --- src/mainboard/getac/p470/Kconfig | 1 + src/mainboard/ibase/mb899/Kconfig | 1 + src/mainboard/intel/d945gclf/Kconfig | 1 + src/mainboard/kontron/986lcd-m/Kconfig | 1 + src/mainboard/lenovo/t60/Kconfig | 1 + src/mainboard/lenovo/x60/Kconfig | 1 + src/mainboard/roda/rk886ex/Kconfig | 1 + src/northbridge/intel/i945/Kconfig | 9 +++++++++ src/northbridge/intel/i945/raminit.c | 4 ++-- 9 files changed, 18 insertions(+), 2 deletions(-) diff --git a/src/mainboard/getac/p470/Kconfig b/src/mainboard/getac/p470/Kconfig index ec30859..6ca11e5 100644 --- a/src/mainboard/getac/p470/Kconfig +++ b/src/mainboard/getac/p470/Kconfig @@ -23,6 +23,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ARCH_X86 select CPU_INTEL_SOCKET_MFCPGA478 select NORTHBRIDGE_INTEL_I945GM + select CHECK_SLFRCS_ON_RESUME select SOUTHBRIDGE_INTEL_I82801GX select SOUTHBRIDGE_TI_PCIXX12 select SUPERIO_SMSC_FDC37N972 diff --git a/src/mainboard/ibase/mb899/Kconfig b/src/mainboard/ibase/mb899/Kconfig index 02ccfab..ac87466 100644 --- a/src/mainboard/ibase/mb899/Kconfig +++ b/src/mainboard/ibase/mb899/Kconfig @@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ARCH_X86 select CPU_INTEL_SOCKET_MFCPGA478 select NORTHBRIDGE_INTEL_I945GM + select CHECK_SLFRCS_ON_RESUME select SOUTHBRIDGE_INTEL_I82801GX select SUPERIO_WINBOND_W83627EHG select BOARD_HAS_FADT diff --git a/src/mainboard/intel/d945gclf/Kconfig b/src/mainboard/intel/d945gclf/Kconfig index 2b0161c..efc8025 100644 --- a/src/mainboard/intel/d945gclf/Kconfig +++ b/src/mainboard/intel/d945gclf/Kconfig @@ -23,6 +23,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ARCH_X86 select CPU_INTEL_SOCKET_441 select NORTHBRIDGE_INTEL_I945GC + select CHECK_SLFRCS_ON_RESUME select SOUTHBRIDGE_INTEL_I82801GX select SUPERIO_SMSC_LPC47M15X select BOARD_HAS_FADT diff --git a/src/mainboard/kontron/986lcd-m/Kconfig b/src/mainboard/kontron/986lcd-m/Kconfig index 01e4b2f..ec5c073 100644 --- a/src/mainboard/kontron/986lcd-m/Kconfig +++ b/src/mainboard/kontron/986lcd-m/Kconfig @@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ARCH_X86 select CPU_INTEL_SOCKET_MFCPGA478 select NORTHBRIDGE_INTEL_I945GM + select CHECK_SLFRCS_ON_RESUME select SOUTHBRIDGE_INTEL_I82801GX select SUPERIO_WINBOND_W83627THG select BOARD_HAS_FADT diff --git a/src/mainboard/lenovo/t60/Kconfig b/src/mainboard/lenovo/t60/Kconfig index d1abcf6..1e4afd1 100644 --- a/src/mainboard/lenovo/t60/Kconfig +++ b/src/mainboard/lenovo/t60/Kconfig @@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ARCH_X86 select CPU_INTEL_SOCKET_MFCPGA478 select NORTHBRIDGE_INTEL_I945GM + select CHECK_SLFRCS_ON_RESUME select SOUTHBRIDGE_INTEL_I82801GX select SUPERIO_NSC_PC87382 select SUPERIO_NSC_PC87384 diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig index 69f83a8..64a3761 100644 --- a/src/mainboard/lenovo/x60/Kconfig +++ b/src/mainboard/lenovo/x60/Kconfig @@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ARCH_X86 select CPU_INTEL_SOCKET_MFCPGA478 select NORTHBRIDGE_INTEL_I945GM + select CHECK_SLFRCS_ON_RESUME select SOUTHBRIDGE_INTEL_I82801GX select SOUTHBRIDGE_RICOH_RL5C476 select SUPERIO_NSC_PC87382 diff --git a/src/mainboard/roda/rk886ex/Kconfig b/src/mainboard/roda/rk886ex/Kconfig index 7dfcc7d..d5de7dc 100644 --- a/src/mainboard/roda/rk886ex/Kconfig +++ b/src/mainboard/roda/rk886ex/Kconfig @@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ARCH_X86 select CPU_INTEL_SOCKET_MFCPGA478 select NORTHBRIDGE_INTEL_I945GM + select CHECK_SLFRCS_ON_RESUME select SOUTHBRIDGE_INTEL_I82801GX select SOUTHBRIDGE_TI_PCI7420 select SUPERIO_SMSC_LPC47N227 diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index 9ba47da..42cc7ce 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -53,4 +53,13 @@ config MAXIMUM_SUPPORTED_FREQUENCY the board supports, despite what the chipset should be capable of. +config CHECK_SLFRCS_ON_RESUME + def_bool n + help + On some boards it may be neccessary to hard reset early + during resume from S3 if the SLFRCS register indicates that + a memory channel is not guaranteed to be in self-refresh. + On other boards the check always creates a false positive, + effectively making it impossible to resume. + endif diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index a7fbaa4..d92c006 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -294,8 +294,8 @@ static void sdram_detect_errors(struct sys_info *sysinfo) reg8 |= (1<<7); pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8); - /* clear self refresh if not wake-up from suspend */ - if (sysinfo->boot_path != 2) { + /* clear self refresh status if check is disabled or not a resume */ + if (!CONFIG_CHECK_SLFRCS_ON_RESUME || sysinfo->boot_path != 2) { MCHBAR8(0xf14) |= 3; } else { /* Validate self refresh config */

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New patch to review for coreboot: 9829e42 mainboard/lenovo/t60, x60: Disable CHECK_SLFRCS_ON_RESUME
by Peter Stuge 27 Jan '12

27 Jan '12

Peter Stuge (peter(a)stuge.se) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/591 -gerrit commit 9829e42122d2453ae176254d0b00bcfa0f7020db Author: Peter Stuge <peter(a)stuge.se> Date: Fri Jan 27 22:56:25 2012 +0100 mainboard/lenovo/t60, x60: Disable CHECK_SLFRCS_ON_RESUME This makes resume from S3 work. Change-Id: I472baf2fbde46bfac223ce39fc81b8e09849fb7f Signed-off-by: Peter Stuge <peter(a)stuge.se> --- src/mainboard/lenovo/t60/Kconfig | 1 - src/mainboard/lenovo/x60/Kconfig | 1 - 2 files changed, 0 insertions(+), 2 deletions(-) diff --git a/src/mainboard/lenovo/t60/Kconfig b/src/mainboard/lenovo/t60/Kconfig index 1e4afd1..d1abcf6 100644 --- a/src/mainboard/lenovo/t60/Kconfig +++ b/src/mainboard/lenovo/t60/Kconfig @@ -5,7 +5,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ARCH_X86 select CPU_INTEL_SOCKET_MFCPGA478 select NORTHBRIDGE_INTEL_I945GM - select CHECK_SLFRCS_ON_RESUME select SOUTHBRIDGE_INTEL_I82801GX select SUPERIO_NSC_PC87382 select SUPERIO_NSC_PC87384 diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig index 64a3761..69f83a8 100644 --- a/src/mainboard/lenovo/x60/Kconfig +++ b/src/mainboard/lenovo/x60/Kconfig @@ -5,7 +5,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ARCH_X86 select CPU_INTEL_SOCKET_MFCPGA478 select NORTHBRIDGE_INTEL_I945GM - select CHECK_SLFRCS_ON_RESUME select SOUTHBRIDGE_INTEL_I82801GX select SOUTHBRIDGE_RICOH_RL5C476 select SUPERIO_NSC_PC87382

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Patch set updated for coreboot: 7ccf423 northbridge/intel/i945: CHECK_SLFRCS_ON_RESUME Kconfig option
by Peter Stuge 27 Jan '12

27 Jan '12

Peter Stuge (peter(a)stuge.se) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/590 -gerrit commit 7ccf423e6d30117d507f2c5407c4cb3e27047fa6 Author: Peter Stuge <peter(a)stuge.se> Date: Fri Jan 27 22:17:09 2012 +0100 northbridge/intel/i945: CHECK_SLFRCS_ON_RESUME Kconfig option Originally brought up by Sven Schnelle in March 2011 http://patchwork.coreboot.org/patch/2801/ http://www.coreboot.org/pipermail/coreboot/2011-March/064277.html On some mainboards it may be neccessary to reset early during resume from S3 if the SLFRCS register indicates that a memory channel is not guaranteed to be in self-refresh. On other mainboards, such as Lenovo X60 and T60, the check always creates false positives, effectively making it impossible to resume. The SLFRCS register is documented on page 197 of Mobile Intel® 945 Express Chipset Family Datasheet Document Number: 309219-006 which is publically available, and the register indicates if a memory channel is guaranteed to be in self-refresh mode (if bit = 1), or that a memory channel *may or may not be* in self-refresh mode (if bit = 0). The register can thus only be used to positively learn that memory is in self-refresh. It is not known for sure that memory is *not* in self-refresh. The register is reset by the PWROK signal, which *should* go low during S3, and go high again when resuming, so it is unsurprising that SLFRCS has already been cleared when we read the register. Sven's measurements of the CKE signal on a ThinkPad shows that memory remains in self-refresh indefinitely, until coreboot re-initializes the memory controller, even when SLFRCS bits were = 0. Boards which require a warm reset when SLFRCS bits are cleared must now explicitly enable the check in the mainboard Kconfig file. This commit selects the new option for all existing i945 mainboards except ThinkPads, to ensure that no regressions are created, while solving the very real problem of coreboot being unable to resume on ThinkPads. Change-Id: I02320675efb8fde05c371ef243ba5093a4da6d11 Signed-off-by: Peter Stuge <peter(a)stuge.se> --- src/mainboard/getac/p470/Kconfig | 1 + src/mainboard/ibase/mb899/Kconfig | 1 + src/mainboard/intel/d945gclf/Kconfig | 1 + src/mainboard/kontron/986lcd-m/Kconfig | 1 + src/mainboard/roda/rk886ex/Kconfig | 1 + src/northbridge/intel/i945/Kconfig | 9 +++++++++ src/northbridge/intel/i945/raminit.c | 4 ++-- 7 files changed, 16 insertions(+), 2 deletions(-) diff --git a/src/mainboard/getac/p470/Kconfig b/src/mainboard/getac/p470/Kconfig index ec30859..6ca11e5 100644 --- a/src/mainboard/getac/p470/Kconfig +++ b/src/mainboard/getac/p470/Kconfig @@ -23,6 +23,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ARCH_X86 select CPU_INTEL_SOCKET_MFCPGA478 select NORTHBRIDGE_INTEL_I945GM + select CHECK_SLFRCS_ON_RESUME select SOUTHBRIDGE_INTEL_I82801GX select SOUTHBRIDGE_TI_PCIXX12 select SUPERIO_SMSC_FDC37N972 diff --git a/src/mainboard/ibase/mb899/Kconfig b/src/mainboard/ibase/mb899/Kconfig index 02ccfab..ac87466 100644 --- a/src/mainboard/ibase/mb899/Kconfig +++ b/src/mainboard/ibase/mb899/Kconfig @@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ARCH_X86 select CPU_INTEL_SOCKET_MFCPGA478 select NORTHBRIDGE_INTEL_I945GM + select CHECK_SLFRCS_ON_RESUME select SOUTHBRIDGE_INTEL_I82801GX select SUPERIO_WINBOND_W83627EHG select BOARD_HAS_FADT diff --git a/src/mainboard/intel/d945gclf/Kconfig b/src/mainboard/intel/d945gclf/Kconfig index 2b0161c..efc8025 100644 --- a/src/mainboard/intel/d945gclf/Kconfig +++ b/src/mainboard/intel/d945gclf/Kconfig @@ -23,6 +23,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ARCH_X86 select CPU_INTEL_SOCKET_441 select NORTHBRIDGE_INTEL_I945GC + select CHECK_SLFRCS_ON_RESUME select SOUTHBRIDGE_INTEL_I82801GX select SUPERIO_SMSC_LPC47M15X select BOARD_HAS_FADT diff --git a/src/mainboard/kontron/986lcd-m/Kconfig b/src/mainboard/kontron/986lcd-m/Kconfig index 01e4b2f..ec5c073 100644 --- a/src/mainboard/kontron/986lcd-m/Kconfig +++ b/src/mainboard/kontron/986lcd-m/Kconfig @@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ARCH_X86 select CPU_INTEL_SOCKET_MFCPGA478 select NORTHBRIDGE_INTEL_I945GM + select CHECK_SLFRCS_ON_RESUME select SOUTHBRIDGE_INTEL_I82801GX select SUPERIO_WINBOND_W83627THG select BOARD_HAS_FADT diff --git a/src/mainboard/roda/rk886ex/Kconfig b/src/mainboard/roda/rk886ex/Kconfig index 7dfcc7d..d5de7dc 100644 --- a/src/mainboard/roda/rk886ex/Kconfig +++ b/src/mainboard/roda/rk886ex/Kconfig @@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ARCH_X86 select CPU_INTEL_SOCKET_MFCPGA478 select NORTHBRIDGE_INTEL_I945GM + select CHECK_SLFRCS_ON_RESUME select SOUTHBRIDGE_INTEL_I82801GX select SOUTHBRIDGE_TI_PCI7420 select SUPERIO_SMSC_LPC47N227 diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index 9ba47da..42cc7ce 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -53,4 +53,13 @@ config MAXIMUM_SUPPORTED_FREQUENCY the board supports, despite what the chipset should be capable of. +config CHECK_SLFRCS_ON_RESUME + def_bool n + help + On some boards it may be neccessary to hard reset early + during resume from S3 if the SLFRCS register indicates that + a memory channel is not guaranteed to be in self-refresh. + On other boards the check always creates a false positive, + effectively making it impossible to resume. + endif diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index a7fbaa4..d92c006 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -294,8 +294,8 @@ static void sdram_detect_errors(struct sys_info *sysinfo) reg8 |= (1<<7); pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8); - /* clear self refresh if not wake-up from suspend */ - if (sysinfo->boot_path != 2) { + /* clear self refresh status if check is disabled or not a resume */ + if (!CONFIG_CHECK_SLFRCS_ON_RESUME || sysinfo->boot_path != 2) { MCHBAR8(0xf14) |= 3; } else { /* Validate self refresh config */

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New patch to review for coreboot: a8dd8d5 northbridge/intel/i945: CHECK_SLFRCS_ON_RESUME Kconfig option
by Peter Stuge 27 Jan '12

27 Jan '12

Peter Stuge (peter(a)stuge.se) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/590 -gerrit commit a8dd8d5549e0c97dacc6ccb0c5d99f3eb9b32a42 Author: Peter Stuge <peter(a)stuge.se> Date: Fri Jan 27 22:17:09 2012 +0100 northbridge/intel/i945: CHECK_SLFRCS_ON_RESUME Kconfig option Originally brought up by Sven Schnelle in March 2011 http://patchwork.coreboot.org/patch/2801/ http://www.coreboot.org/pipermail/coreboot/2011-March/064277.html On some mainboards it may be neccessary to reset early during resume from S3 if the SLFRCS register indicates that a memory channel is not guaranteed to be in self-refresh. On other mainboards, such as Lenovo X60 and T60, the check always creates false positives, effectively making it impossible to resume. The SLFRCS register is documented on page 197 of Mobile Intel® 945 Express Chipset Family Datasheet Document Number: 309219-006 which is publically available, and the register indicates if a memory channel is guaranteed to be in self-refresh mode if a bit is set (= 1), or that a memory channel *may or may not be* in self-refresh mode if a bit is clear (= 0). The register can thus only be used to learn that RAM is positively in self-refresh. The register is reset by the PWROK signal, which *should* go low during S3 and go high again when resuming, so it is unsurprising that bits have already been reset by the time coreboot reads them. Sven's measurements of the CKE signal on a ThinkPad shows that memory remains in self-refresh indefinitely, until coreboot re-initializes the memory controller, even when the SLFRCS bits were clear (= 0). Boards which require a warm reset when SLFRCS bits are cleared must now explicitly enable the check in the mainboard Kconfig file. All existing i945 mainboards except ThinkPads select the option, to ensure that this commit creates no regressions while solving the very real problem of ThinkPad mainboards being unable to resume from S3. Change-Id: I02320675efb8fde05c371ef243ba5093a4da6d11 Signed-off-by: Peter Stuge <peter(a)stuge.se> --- src/mainboard/getac/p470/Kconfig | 1 + src/mainboard/ibase/mb899/Kconfig | 1 + src/mainboard/intel/d945gclf/Kconfig | 1 + src/mainboard/kontron/986lcd-m/Kconfig | 1 + src/mainboard/roda/rk886ex/Kconfig | 1 + src/northbridge/intel/i945/Kconfig | 9 +++++++++ src/northbridge/intel/i945/raminit.c | 4 ++-- 7 files changed, 16 insertions(+), 2 deletions(-) diff --git a/src/mainboard/getac/p470/Kconfig b/src/mainboard/getac/p470/Kconfig index ec30859..6ca11e5 100644 --- a/src/mainboard/getac/p470/Kconfig +++ b/src/mainboard/getac/p470/Kconfig @@ -23,6 +23,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ARCH_X86 select CPU_INTEL_SOCKET_MFCPGA478 select NORTHBRIDGE_INTEL_I945GM + select CHECK_SLFRCS_ON_RESUME select SOUTHBRIDGE_INTEL_I82801GX select SOUTHBRIDGE_TI_PCIXX12 select SUPERIO_SMSC_FDC37N972 diff --git a/src/mainboard/ibase/mb899/Kconfig b/src/mainboard/ibase/mb899/Kconfig index 02ccfab..ac87466 100644 --- a/src/mainboard/ibase/mb899/Kconfig +++ b/src/mainboard/ibase/mb899/Kconfig @@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ARCH_X86 select CPU_INTEL_SOCKET_MFCPGA478 select NORTHBRIDGE_INTEL_I945GM + select CHECK_SLFRCS_ON_RESUME select SOUTHBRIDGE_INTEL_I82801GX select SUPERIO_WINBOND_W83627EHG select BOARD_HAS_FADT diff --git a/src/mainboard/intel/d945gclf/Kconfig b/src/mainboard/intel/d945gclf/Kconfig index 2b0161c..efc8025 100644 --- a/src/mainboard/intel/d945gclf/Kconfig +++ b/src/mainboard/intel/d945gclf/Kconfig @@ -23,6 +23,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ARCH_X86 select CPU_INTEL_SOCKET_441 select NORTHBRIDGE_INTEL_I945GC + select CHECK_SLFRCS_ON_RESUME select SOUTHBRIDGE_INTEL_I82801GX select SUPERIO_SMSC_LPC47M15X select BOARD_HAS_FADT diff --git a/src/mainboard/kontron/986lcd-m/Kconfig b/src/mainboard/kontron/986lcd-m/Kconfig index 01e4b2f..ec5c073 100644 --- a/src/mainboard/kontron/986lcd-m/Kconfig +++ b/src/mainboard/kontron/986lcd-m/Kconfig @@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ARCH_X86 select CPU_INTEL_SOCKET_MFCPGA478 select NORTHBRIDGE_INTEL_I945GM + select CHECK_SLFRCS_ON_RESUME select SOUTHBRIDGE_INTEL_I82801GX select SUPERIO_WINBOND_W83627THG select BOARD_HAS_FADT diff --git a/src/mainboard/roda/rk886ex/Kconfig b/src/mainboard/roda/rk886ex/Kconfig index 7dfcc7d..d5de7dc 100644 --- a/src/mainboard/roda/rk886ex/Kconfig +++ b/src/mainboard/roda/rk886ex/Kconfig @@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ARCH_X86 select CPU_INTEL_SOCKET_MFCPGA478 select NORTHBRIDGE_INTEL_I945GM + select CHECK_SLFRCS_ON_RESUME select SOUTHBRIDGE_INTEL_I82801GX select SOUTHBRIDGE_TI_PCI7420 select SUPERIO_SMSC_LPC47N227 diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index 9ba47da..42cc7ce 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -53,4 +53,13 @@ config MAXIMUM_SUPPORTED_FREQUENCY the board supports, despite what the chipset should be capable of. +config CHECK_SLFRCS_ON_RESUME + def_bool n + help + On some boards it may be neccessary to hard reset early + during resume from S3 if the SLFRCS register indicates that + a memory channel is not guaranteed to be in self-refresh. + On other boards the check always creates a false positive, + effectively making it impossible to resume. + endif diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index a7fbaa4..d92c006 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -294,8 +294,8 @@ static void sdram_detect_errors(struct sys_info *sysinfo) reg8 |= (1<<7); pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8); - /* clear self refresh if not wake-up from suspend */ - if (sysinfo->boot_path != 2) { + /* clear self refresh status if check is disabled or not a resume */ + if (!CONFIG_CHECK_SLFRCS_ON_RESUME || sysinfo->boot_path != 2) { MCHBAR8(0xf14) |= 3; } else { /* Validate self refresh config */

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Re: [coreboot] Support for Intel Atom E6xx with EG20 needed
by Stefan Reinauer 27 Jan '12

27 Jan '12

* Software Developer <softwaredeveloper755(a)googlemail.com> [120127 12:41]: > Hi, > we're evaluating some bootloaders that we could use for our Intel E6xx with > EG20 platform (its exactly the Kontron nanoETXexpress-TT). > > See here: http://us.kontron.com/products/computeronmodules/com+express/ > com+express+mini/nanoetxexpresstt.html?searchterm=nanoetxexpress-tt > > Is it possible to use Coreboot on that platform? > How great would be the effort to add such support in coreboot??? A few months of development. Stefan

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coreboot January 2012