coreboot January 2012

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Patch set updated for coreboot: 1734252 dumpmmcr: Fix compilation warnings in printf
by Vikram Narayanan 26 Jan '12

26 Jan '12

Vikram Narayanan (vikram186(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/582 -gerrit commit 1734252df27612b8b5acf4fb28a52e5505e26c9a Author: Vikram Narayanan <vikram186(a)gmail.com> Date: Wed Jan 25 17:44:20 2012 +0530 dumpmmcr: Fix compilation warnings in printf cf., `man 3 printf` Change-Id: Ib78937a3e1c1eecf884bde0860594cbdb574f1fe Signed-off-by: Vikram Narayanan <vikram186(a)gmail.com> --- util/dumpmmcr/dumpmmcr.c | 10 +++++----- 1 files changed, 5 insertions(+), 5 deletions(-) diff --git a/util/dumpmmcr/dumpmmcr.c b/util/dumpmmcr/dumpmmcr.c index 4e1e4e7..a92068a 100644 --- a/util/dumpmmcr/dumpmmcr.c +++ b/util/dumpmmcr/dumpmmcr.c @@ -52,8 +52,8 @@ int print_mmcr(struct mmcr *mmcr) printf("eccsta is 0x%x\n", val(mmcr, memregs.eccsta)); printf("ckbpos is 0x%x\n", val(mmcr, memregs.eccckbpos)); printf("cktest is 0x%x\n", val(mmcr, memregs.ecccktest)); - printf("sbadd is 0x%x\n", val(mmcr, memregs.eccsbadd)); - printf("mbadd is 0x%x\n", val(mmcr, memregs.eccmbadd)); + printf("sbadd is 0x%lx\n", val(mmcr, memregs.eccsbadd)); + printf("mbadd is 0x%lx\n", val(mmcr, memregs.eccmbadd)); printf("\n"); printf("dbctl is 0x%x\n", val(mmcr, dbctl.dbctl)); @@ -69,20 +69,20 @@ int print_mmcr(struct mmcr *mmcr) printf("hbtgtirqsta is 0x%x\n", val(mmcr, hostbridge.tgtirqsta)); printf("hbmstirqctl is 0x%x\n", val(mmcr, hostbridge.mstirqctl)); printf("hbmstirqsta is 0x%x\n", val(mmcr, hostbridge.mstirqsta)); - printf("mstintadd is 0x%x\n", val(mmcr, hostbridge.mstintadd)); + printf("mstintadd is 0x%lx\n", val(mmcr, hostbridge.mstintadd)); printf("\n"); printf("sysarbctl is 0x%x\n", val(mmcr, sysarb.ctl)); printf("pciarbsta is 0x%x\n", val(mmcr, sysarb.sta)); printf("sysarbmenb is 0x%x\n", val(mmcr, sysarb.menb)); - printf("arbprictl is 0x%x\n", val(mmcr, sysarb.prictl)); + printf("arbprictl is 0x%lx\n", val(mmcr, sysarb.prictl)); printf("\n"); printf("adddecctl is 0x%x\n", val(mmcr, sysmap.adddecctl)); printf("wpvsta is 0x%x\n", val(mmcr, sysmap.wpvsta)); for (i=0; i<16; i++) - printf("par %d is 0x%x\n", i, val(mmcr, sysmap.par[i])); + printf("par %d is 0x%lx\n", i, val(mmcr, sysmap.par[i])); printf("\n"); printf("gpecho is 0x%x\n", val(mmcr, gpctl.gpecho));

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New patch to review for coreboot: 30e9fed vga: removed inclusion of .c file
by Vikram Narayanan 25 Jan '12

25 Jan '12

Vikram Narayanan (vikram186(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/581 -gerrit commit 30e9fed46bd5e065c0e82de18eda356fd7440b13 Author: Vikram Narayanan <vikram186(a)gmail.com> Date: Wed Jan 25 20:40:40 2012 +0530 vga: removed inclusion of .c file Renamed vga_palette.c -> vga_palette.h Made appropriate changes in vga.c Change-Id: If3e998e609e0a2fcbfad3df79fbbc755acd996c1 Signed-off-by: Vikram Narayanan <vikram186(a)gmail.com> --- src/pc80/vga/vga.c | 4 +- src/pc80/vga/vga_palette.c | 261 ------------------------------------------- src/pc80/vga/vga_palette.h | 265 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 266 insertions(+), 264 deletions(-) diff --git a/src/pc80/vga/vga.c b/src/pc80/vga/vga.c index f87ba66..307e6d9 100644 --- a/src/pc80/vga/vga.c +++ b/src/pc80/vga/vga.c @@ -20,7 +20,7 @@ #include <pc80/vga_io.h> #include <string.h> - +#include "vga_palette.h" /* * pci io enable should've happened before */ @@ -69,8 +69,6 @@ vga_fb_clear(void) memset((void *)VGA_FB, 0x00, 0x8000); } -#include "vga_palette.c" - /* * */ diff --git a/src/pc80/vga/vga_palette.c b/src/pc80/vga/vga_palette.c deleted file mode 100644 index 01c9030..0000000 --- a/src/pc80/vga/vga_palette.c +++ /dev/null @@ -1,261 +0,0 @@ -/* - * Basic palette. - */ -struct palette { - unsigned char red; - unsigned char green; - unsigned char blue; -}; - -static const struct palette -default_vga_palette[0x100] = { - { 0x00, 0x00, 0x00}, - { 0x00, 0x00, 0x2A}, - { 0x00, 0x2A, 0x00}, - { 0x00, 0x2A, 0x2A}, - { 0x2A, 0x00, 0x00}, - { 0x2A, 0x00, 0x2A}, - { 0x2A, 0x15, 0x00}, - { 0x2A, 0x2A, 0x2A}, - { 0x15, 0x15, 0x15}, - { 0x15, 0x15, 0x3F}, - { 0x15, 0x3F, 0x15}, - { 0x15, 0x3F, 0x3F}, - { 0x3F, 0x15, 0x15}, - { 0x3F, 0x15, 0x3F}, - { 0x3F, 0x3F, 0x15}, - { 0x3F, 0x3F, 0x3F}, - { 0x00, 0x00, 0x00}, - { 0x05, 0x05, 0x05}, - { 0x08, 0x08, 0x08}, - { 0x0B, 0x0B, 0x0B}, - { 0x0E, 0x0E, 0x0E}, - { 0x11, 0x11, 0x11}, - { 0x16, 0x16, 0x16}, - { 0x18, 0x18, 0x18}, - { 0x1C, 0x1C, 0x1C}, - { 0x20, 0x20, 0x20}, - { 0x24, 0x24, 0x24}, - { 0x28, 0x28, 0x28}, - { 0x2D, 0x2D, 0x2D}, - { 0x32, 0x32, 0x32}, - { 0x38, 0x38, 0x38}, - { 0x3F, 0x3F, 0x3F}, - { 0x00, 0x00, 0x3F}, - { 0x20, 0x00, 0x3F}, - { 0x1F, 0x00, 0x3F}, - { 0x2F, 0x00, 0x3F}, - { 0x3F, 0x00, 0x3F}, - { 0x3F, 0x00, 0x2F}, - { 0x3F, 0x00, 0x1F}, - { 0x3F, 0x00, 0x20}, - { 0x3F, 0x00, 0x00}, - { 0x3F, 0x20, 0x00}, - { 0x3F, 0x1F, 0x00}, - { 0x3F, 0x2F, 0x00}, - { 0x3F, 0x3F, 0x00}, - { 0x2F, 0x3F, 0x00}, - { 0x1F, 0x3F, 0x00}, - { 0x20, 0x3F, 0x00}, - { 0x00, 0x3F, 0x00}, - { 0x00, 0x3F, 0x20}, - { 0x00, 0x3F, 0x1F}, - { 0x00, 0x3F, 0x2F}, - { 0x00, 0x3F, 0x3F}, - { 0x00, 0x2F, 0x3F}, - { 0x00, 0x1F, 0x3F}, - { 0x00, 0x20, 0x3F}, - { 0x1F, 0x1F, 0x3F}, - { 0x27, 0x1F, 0x3F}, - { 0x2F, 0x1F, 0x3F}, - { 0x37, 0x1F, 0x3F}, - { 0x3F, 0x1F, 0x3F}, - { 0x3F, 0x1F, 0x37}, - { 0x3F, 0x1F, 0x2F}, - { 0x3F, 0x1F, 0x27}, - { 0x3F, 0x1F, 0x1F}, - { 0x3F, 0x27, 0x1F}, - { 0x3F, 0x2F, 0x1F}, - { 0x3F, 0x37, 0x1F}, - { 0x3F, 0x3F, 0x1F}, - { 0x37, 0x3F, 0x1F}, - { 0x2F, 0x3F, 0x1F}, - { 0x27, 0x3F, 0x1F}, - { 0x1F, 0x3F, 0x1F}, - { 0x1F, 0x3F, 0x27}, - { 0x1F, 0x3F, 0x2F}, - { 0x1F, 0x3F, 0x37}, - { 0x1F, 0x3F, 0x3F}, - { 0x1F, 0x37, 0x3F}, - { 0x1F, 0x2F, 0x3F}, - { 0x1F, 0x27, 0x3F}, - { 0x2D, 0x2D, 0x3F}, - { 0x31, 0x2D, 0x3F}, - { 0x36, 0x2D, 0x3F}, - { 0x3A, 0x2D, 0x3F}, - { 0x3F, 0x2D, 0x3F}, - { 0x3F, 0x2D, 0x3A}, - { 0x3F, 0x2D, 0x36}, - { 0x3F, 0x2D, 0x31}, - { 0x3F, 0x2D, 0x2D}, - { 0x3F, 0x31, 0x2D}, - { 0x3F, 0x36, 0x2D}, - { 0x3F, 0x3A, 0x2D}, - { 0x3F, 0x3F, 0x2D}, - { 0x3A, 0x3F, 0x2D}, - { 0x36, 0x3F, 0x2D}, - { 0x31, 0x3F, 0x2D}, - { 0x2D, 0x3F, 0x2D}, - { 0x2D, 0x3F, 0x31}, - { 0x2D, 0x3F, 0x36}, - { 0x2D, 0x3F, 0x3A}, - { 0x2D, 0x3F, 0x3F}, - { 0x2D, 0x3A, 0x3F}, - { 0x2D, 0x36, 0x3F}, - { 0x2D, 0x31, 0x3F}, - { 0x00, 0x00, 0x1C}, - { 0x07, 0x00, 0x1C}, - { 0x0E, 0x00, 0x1C}, - { 0x15, 0x00, 0x1C}, - { 0x1C, 0x00, 0x1C}, - { 0x1C, 0x00, 0x15}, - { 0x1C, 0x00, 0x0E}, - { 0x1C, 0x00, 0x07}, - { 0x1C, 0x00, 0x00}, - { 0x1C, 0x07, 0x00}, - { 0x1C, 0x0E, 0x00}, - { 0x1C, 0x15, 0x00}, - { 0x1C, 0x1C, 0x00}, - { 0x15, 0x1C, 0x00}, - { 0x0E, 0x1C, 0x00}, - { 0x07, 0x1C, 0x00}, - { 0x00, 0x1C, 0x00}, - { 0x00, 0x1C, 0x07}, - { 0x00, 0x1C, 0x0E}, - { 0x00, 0x1C, 0x15}, - { 0x00, 0x1C, 0x1C}, - { 0x00, 0x15, 0x1C}, - { 0x00, 0x0E, 0x1C}, - { 0x00, 0x07, 0x1C}, - { 0x0E, 0x0E, 0x1C}, - { 0x11, 0x0E, 0x1C}, - { 0x15, 0x0E, 0x1C}, - { 0x18, 0x0E, 0x1C}, - { 0x1C, 0x0E, 0x1C}, - { 0x1C, 0x0E, 0x18}, - { 0x1C, 0x0E, 0x15}, - { 0x1C, 0x0E, 0x11}, - { 0x1C, 0x0E, 0x0E}, - { 0x1C, 0x11, 0x0E}, - { 0x1C, 0x15, 0x0E}, - { 0x1C, 0x18, 0x0E}, - { 0x1C, 0x1C, 0x0E}, - { 0x18, 0x1C, 0x0E}, - { 0x15, 0x1C, 0x0E}, - { 0x11, 0x1C, 0x0E}, - { 0x0E, 0x1C, 0x0E}, - { 0x0E, 0x1C, 0x11}, - { 0x0E, 0x1C, 0x15}, - { 0x0E, 0x1C, 0x18}, - { 0x0E, 0x1C, 0x1C}, - { 0x0E, 0x18, 0x1C}, - { 0x0E, 0x15, 0x1C}, - { 0x0E, 0x11, 0x1C}, - { 0x16, 0x16, 0x1C}, - { 0x16, 0x16, 0x1C}, - { 0x18, 0x16, 0x1C}, - { 0x1A, 0x16, 0x1C}, - { 0x1C, 0x16, 0x1C}, - { 0x1C, 0x16, 0x1A}, - { 0x1C, 0x16, 0x18}, - { 0x1C, 0x16, 0x16}, - { 0x1C, 0x16, 0x16}, - { 0x1C, 0x16, 0x16}, - { 0x1C, 0x18, 0x16}, - { 0x1C, 0x1A, 0x16}, - { 0x1C, 0x1C, 0x16}, - { 0x1A, 0x1C, 0x16}, - { 0x18, 0x1C, 0x16}, - { 0x16, 0x1C, 0x16}, - { 0x16, 0x1C, 0x16}, - { 0x16, 0x1C, 0x16}, - { 0x16, 0x1C, 0x18}, - { 0x16, 0x1C, 0x1A}, - { 0x16, 0x1C, 0x1C}, - { 0x16, 0x1A, 0x1C}, - { 0x16, 0x18, 0x1C}, - { 0x16, 0x16, 0x1C}, - { 0x00, 0x00, 0x20}, - { 0x04, 0x00, 0x20}, - { 0x08, 0x00, 0x20}, - { 0x0C, 0x00, 0x20}, - { 0x20, 0x00, 0x20}, - { 0x20, 0x00, 0x0C}, - { 0x20, 0x00, 0x08}, - { 0x20, 0x00, 0x04}, - { 0x20, 0x00, 0x00}, - { 0x20, 0x04, 0x00}, - { 0x20, 0x08, 0x00}, - { 0x20, 0x0C, 0x00}, - { 0x20, 0x20, 0x00}, - { 0x0C, 0x20, 0x00}, - { 0x08, 0x20, 0x00}, - { 0x04, 0x20, 0x00}, - { 0x00, 0x20, 0x00}, - { 0x00, 0x20, 0x04}, - { 0x00, 0x20, 0x08}, - { 0x00, 0x20, 0x0C}, - { 0x00, 0x20, 0x20}, - { 0x00, 0x0C, 0x20}, - { 0x00, 0x08, 0x20}, - { 0x00, 0x04, 0x20}, - { 0x08, 0x08, 0x20}, - { 0x0A, 0x08, 0x20}, - { 0x0C, 0x08, 0x20}, - { 0x0E, 0x08, 0x20}, - { 0x20, 0x08, 0x20}, - { 0x20, 0x08, 0x0E}, - { 0x20, 0x08, 0x0C}, - { 0x20, 0x08, 0x0A}, - { 0x20, 0x08, 0x08}, - { 0x20, 0x0A, 0x08}, - { 0x20, 0x0C, 0x08}, - { 0x20, 0x0E, 0x08}, - { 0x20, 0x20, 0x08}, - { 0x0E, 0x20, 0x08}, - { 0x0C, 0x20, 0x08}, - { 0x0A, 0x20, 0x08}, - { 0x08, 0x20, 0x08}, - { 0x08, 0x20, 0x0A}, - { 0x08, 0x20, 0x0C}, - { 0x08, 0x20, 0x0E}, - { 0x08, 0x20, 0x20}, - { 0x08, 0x0E, 0x20}, - { 0x08, 0x0C, 0x20}, - { 0x08, 0x0A, 0x20}, - { 0x0B, 0x0B, 0x20}, - { 0x0C, 0x0B, 0x20}, - { 0x0D, 0x0B, 0x20}, - { 0x0F, 0x0B, 0x20}, - { 0x20, 0x0B, 0x20}, - { 0x20, 0x0B, 0x0F}, - { 0x20, 0x0B, 0x0D}, - { 0x20, 0x0B, 0x0C}, - { 0x20, 0x0B, 0x0B}, - { 0x20, 0x0C, 0x0B}, - { 0x20, 0x0D, 0x0B}, - { 0x20, 0x0F, 0x0B}, - { 0x20, 0x20, 0x0B}, - { 0x0F, 0x20, 0x0B}, - { 0x0D, 0x20, 0x0B}, - { 0x0C, 0x20, 0x0B}, - { 0x0B, 0x20, 0x0B}, - { 0x0B, 0x20, 0x0C}, - { 0x0B, 0x20, 0x0D}, - { 0x0B, 0x20, 0x0F}, - { 0x0B, 0x20, 0x20}, - { 0x0B, 0x0F, 0x20}, - { 0x0B, 0x0D, 0x20}, - { 0x0B, 0x0C, 0x20}, - /* Pad with NULL */ -}; diff --git a/src/pc80/vga/vga_palette.h b/src/pc80/vga/vga_palette.h new file mode 100644 index 0000000..2e38da1 --- /dev/null +++ b/src/pc80/vga/vga_palette.h @@ -0,0 +1,265 @@ +#ifndef VGA_PALETTE_H +#define VGA_PALETTE_H + +/* + * Basic palette. + */ +struct palette { + unsigned char red; + unsigned char green; + unsigned char blue; +}; + +static const struct palette +default_vga_palette[0x100] = { + { 0x00, 0x00, 0x00}, + { 0x00, 0x00, 0x2A}, + { 0x00, 0x2A, 0x00}, + { 0x00, 0x2A, 0x2A}, + { 0x2A, 0x00, 0x00}, + { 0x2A, 0x00, 0x2A}, + { 0x2A, 0x15, 0x00}, + { 0x2A, 0x2A, 0x2A}, + { 0x15, 0x15, 0x15}, + { 0x15, 0x15, 0x3F}, + { 0x15, 0x3F, 0x15}, + { 0x15, 0x3F, 0x3F}, + { 0x3F, 0x15, 0x15}, + { 0x3F, 0x15, 0x3F}, + { 0x3F, 0x3F, 0x15}, + { 0x3F, 0x3F, 0x3F}, + { 0x00, 0x00, 0x00}, + { 0x05, 0x05, 0x05}, + { 0x08, 0x08, 0x08}, + { 0x0B, 0x0B, 0x0B}, + { 0x0E, 0x0E, 0x0E}, + { 0x11, 0x11, 0x11}, + { 0x16, 0x16, 0x16}, + { 0x18, 0x18, 0x18}, + { 0x1C, 0x1C, 0x1C}, + { 0x20, 0x20, 0x20}, + { 0x24, 0x24, 0x24}, + { 0x28, 0x28, 0x28}, + { 0x2D, 0x2D, 0x2D}, + { 0x32, 0x32, 0x32}, + { 0x38, 0x38, 0x38}, + { 0x3F, 0x3F, 0x3F}, + { 0x00, 0x00, 0x3F}, + { 0x20, 0x00, 0x3F}, + { 0x1F, 0x00, 0x3F}, + { 0x2F, 0x00, 0x3F}, + { 0x3F, 0x00, 0x3F}, + { 0x3F, 0x00, 0x2F}, + { 0x3F, 0x00, 0x1F}, + { 0x3F, 0x00, 0x20}, + { 0x3F, 0x00, 0x00}, + { 0x3F, 0x20, 0x00}, + { 0x3F, 0x1F, 0x00}, + { 0x3F, 0x2F, 0x00}, + { 0x3F, 0x3F, 0x00}, + { 0x2F, 0x3F, 0x00}, + { 0x1F, 0x3F, 0x00}, + { 0x20, 0x3F, 0x00}, + { 0x00, 0x3F, 0x00}, + { 0x00, 0x3F, 0x20}, + { 0x00, 0x3F, 0x1F}, + { 0x00, 0x3F, 0x2F}, + { 0x00, 0x3F, 0x3F}, + { 0x00, 0x2F, 0x3F}, + { 0x00, 0x1F, 0x3F}, + { 0x00, 0x20, 0x3F}, + { 0x1F, 0x1F, 0x3F}, + { 0x27, 0x1F, 0x3F}, + { 0x2F, 0x1F, 0x3F}, + { 0x37, 0x1F, 0x3F}, + { 0x3F, 0x1F, 0x3F}, + { 0x3F, 0x1F, 0x37}, + { 0x3F, 0x1F, 0x2F}, + { 0x3F, 0x1F, 0x27}, + { 0x3F, 0x1F, 0x1F}, + { 0x3F, 0x27, 0x1F}, + { 0x3F, 0x2F, 0x1F}, + { 0x3F, 0x37, 0x1F}, + { 0x3F, 0x3F, 0x1F}, + { 0x37, 0x3F, 0x1F}, + { 0x2F, 0x3F, 0x1F}, + { 0x27, 0x3F, 0x1F}, + { 0x1F, 0x3F, 0x1F}, + { 0x1F, 0x3F, 0x27}, + { 0x1F, 0x3F, 0x2F}, + { 0x1F, 0x3F, 0x37}, + { 0x1F, 0x3F, 0x3F}, + { 0x1F, 0x37, 0x3F}, + { 0x1F, 0x2F, 0x3F}, + { 0x1F, 0x27, 0x3F}, + { 0x2D, 0x2D, 0x3F}, + { 0x31, 0x2D, 0x3F}, + { 0x36, 0x2D, 0x3F}, + { 0x3A, 0x2D, 0x3F}, + { 0x3F, 0x2D, 0x3F}, + { 0x3F, 0x2D, 0x3A}, + { 0x3F, 0x2D, 0x36}, + { 0x3F, 0x2D, 0x31}, + { 0x3F, 0x2D, 0x2D}, + { 0x3F, 0x31, 0x2D}, + { 0x3F, 0x36, 0x2D}, + { 0x3F, 0x3A, 0x2D}, + { 0x3F, 0x3F, 0x2D}, + { 0x3A, 0x3F, 0x2D}, + { 0x36, 0x3F, 0x2D}, + { 0x31, 0x3F, 0x2D}, + { 0x2D, 0x3F, 0x2D}, + { 0x2D, 0x3F, 0x31}, + { 0x2D, 0x3F, 0x36}, + { 0x2D, 0x3F, 0x3A}, + { 0x2D, 0x3F, 0x3F}, + { 0x2D, 0x3A, 0x3F}, + { 0x2D, 0x36, 0x3F}, + { 0x2D, 0x31, 0x3F}, + { 0x00, 0x00, 0x1C}, + { 0x07, 0x00, 0x1C}, + { 0x0E, 0x00, 0x1C}, + { 0x15, 0x00, 0x1C}, + { 0x1C, 0x00, 0x1C}, + { 0x1C, 0x00, 0x15}, + { 0x1C, 0x00, 0x0E}, + { 0x1C, 0x00, 0x07}, + { 0x1C, 0x00, 0x00}, + { 0x1C, 0x07, 0x00}, + { 0x1C, 0x0E, 0x00}, + { 0x1C, 0x15, 0x00}, + { 0x1C, 0x1C, 0x00}, + { 0x15, 0x1C, 0x00}, + { 0x0E, 0x1C, 0x00}, + { 0x07, 0x1C, 0x00}, + { 0x00, 0x1C, 0x00}, + { 0x00, 0x1C, 0x07}, + { 0x00, 0x1C, 0x0E}, + { 0x00, 0x1C, 0x15}, + { 0x00, 0x1C, 0x1C}, + { 0x00, 0x15, 0x1C}, + { 0x00, 0x0E, 0x1C}, + { 0x00, 0x07, 0x1C}, + { 0x0E, 0x0E, 0x1C}, + { 0x11, 0x0E, 0x1C}, + { 0x15, 0x0E, 0x1C}, + { 0x18, 0x0E, 0x1C}, + { 0x1C, 0x0E, 0x1C}, + { 0x1C, 0x0E, 0x18}, + { 0x1C, 0x0E, 0x15}, + { 0x1C, 0x0E, 0x11}, + { 0x1C, 0x0E, 0x0E}, + { 0x1C, 0x11, 0x0E}, + { 0x1C, 0x15, 0x0E}, + { 0x1C, 0x18, 0x0E}, + { 0x1C, 0x1C, 0x0E}, + { 0x18, 0x1C, 0x0E}, + { 0x15, 0x1C, 0x0E}, + { 0x11, 0x1C, 0x0E}, + { 0x0E, 0x1C, 0x0E}, + { 0x0E, 0x1C, 0x11}, + { 0x0E, 0x1C, 0x15}, + { 0x0E, 0x1C, 0x18}, + { 0x0E, 0x1C, 0x1C}, + { 0x0E, 0x18, 0x1C}, + { 0x0E, 0x15, 0x1C}, + { 0x0E, 0x11, 0x1C}, + { 0x16, 0x16, 0x1C}, + { 0x16, 0x16, 0x1C}, + { 0x18, 0x16, 0x1C}, + { 0x1A, 0x16, 0x1C}, + { 0x1C, 0x16, 0x1C}, + { 0x1C, 0x16, 0x1A}, + { 0x1C, 0x16, 0x18}, + { 0x1C, 0x16, 0x16}, + { 0x1C, 0x16, 0x16}, + { 0x1C, 0x16, 0x16}, + { 0x1C, 0x18, 0x16}, + { 0x1C, 0x1A, 0x16}, + { 0x1C, 0x1C, 0x16}, + { 0x1A, 0x1C, 0x16}, + { 0x18, 0x1C, 0x16}, + { 0x16, 0x1C, 0x16}, + { 0x16, 0x1C, 0x16}, + { 0x16, 0x1C, 0x16}, + { 0x16, 0x1C, 0x18}, + { 0x16, 0x1C, 0x1A}, + { 0x16, 0x1C, 0x1C}, + { 0x16, 0x1A, 0x1C}, + { 0x16, 0x18, 0x1C}, + { 0x16, 0x16, 0x1C}, + { 0x00, 0x00, 0x20}, + { 0x04, 0x00, 0x20}, + { 0x08, 0x00, 0x20}, + { 0x0C, 0x00, 0x20}, + { 0x20, 0x00, 0x20}, + { 0x20, 0x00, 0x0C}, + { 0x20, 0x00, 0x08}, + { 0x20, 0x00, 0x04}, + { 0x20, 0x00, 0x00}, + { 0x20, 0x04, 0x00}, + { 0x20, 0x08, 0x00}, + { 0x20, 0x0C, 0x00}, + { 0x20, 0x20, 0x00}, + { 0x0C, 0x20, 0x00}, + { 0x08, 0x20, 0x00}, + { 0x04, 0x20, 0x00}, + { 0x00, 0x20, 0x00}, + { 0x00, 0x20, 0x04}, + { 0x00, 0x20, 0x08}, + { 0x00, 0x20, 0x0C}, + { 0x00, 0x20, 0x20}, + { 0x00, 0x0C, 0x20}, + { 0x00, 0x08, 0x20}, + { 0x00, 0x04, 0x20}, + { 0x08, 0x08, 0x20}, + { 0x0A, 0x08, 0x20}, + { 0x0C, 0x08, 0x20}, + { 0x0E, 0x08, 0x20}, + { 0x20, 0x08, 0x20}, + { 0x20, 0x08, 0x0E}, + { 0x20, 0x08, 0x0C}, + { 0x20, 0x08, 0x0A}, + { 0x20, 0x08, 0x08}, + { 0x20, 0x0A, 0x08}, + { 0x20, 0x0C, 0x08}, + { 0x20, 0x0E, 0x08}, + { 0x20, 0x20, 0x08}, + { 0x0E, 0x20, 0x08}, + { 0x0C, 0x20, 0x08}, + { 0x0A, 0x20, 0x08}, + { 0x08, 0x20, 0x08}, + { 0x08, 0x20, 0x0A}, + { 0x08, 0x20, 0x0C}, + { 0x08, 0x20, 0x0E}, + { 0x08, 0x20, 0x20}, + { 0x08, 0x0E, 0x20}, + { 0x08, 0x0C, 0x20}, + { 0x08, 0x0A, 0x20}, + { 0x0B, 0x0B, 0x20}, + { 0x0C, 0x0B, 0x20}, + { 0x0D, 0x0B, 0x20}, + { 0x0F, 0x0B, 0x20}, + { 0x20, 0x0B, 0x20}, + { 0x20, 0x0B, 0x0F}, + { 0x20, 0x0B, 0x0D}, + { 0x20, 0x0B, 0x0C}, + { 0x20, 0x0B, 0x0B}, + { 0x20, 0x0C, 0x0B}, + { 0x20, 0x0D, 0x0B}, + { 0x20, 0x0F, 0x0B}, + { 0x20, 0x20, 0x0B}, + { 0x0F, 0x20, 0x0B}, + { 0x0D, 0x20, 0x0B}, + { 0x0C, 0x20, 0x0B}, + { 0x0B, 0x20, 0x0B}, + { 0x0B, 0x20, 0x0C}, + { 0x0B, 0x20, 0x0D}, + { 0x0B, 0x20, 0x0F}, + { 0x0B, 0x20, 0x20}, + { 0x0B, 0x0F, 0x20}, + { 0x0B, 0x0D, 0x20}, + { 0x0B, 0x0C, 0x20}, + /* Pad with NULL */ +}; +#endif /* VGA_PALETTE_H */

1 0

Patch set updated for coreboot: f74ca42 pci_ops_mmconf: Move conditional compilation to Makefile
by Vikram Narayanan 25 Jan '12

25 Jan '12

Vikram Narayanan (vikram186(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/578 -gerrit commit f74ca42fc8462f791fdb2866919625a8f6459e1d Author: Vikram Narayanan <vikram186(a)gmail.com> Date: Tue Jan 24 20:22:20 2012 +0530 pci_ops_mmconf: Move conditional compilation to Makefile Moved the conditional compilation out of the source file Change-Id: Ic4045006f39d70f4a0bc37d1bd5e073ed8477c68 Signed-off-by: Vikram Narayanan <vikram186(a)gmail.com> --- src/arch/x86/lib/Makefile.inc | 4 +++- src/arch/x86/lib/pci_ops_mmconf.c | 4 ---- 2 files changed, 3 insertions(+), 5 deletions(-) diff --git a/src/arch/x86/lib/Makefile.inc b/src/arch/x86/lib/Makefile.inc index 3092388..3388a9d 100644 --- a/src/arch/x86/lib/Makefile.inc +++ b/src/arch/x86/lib/Makefile.inc @@ -2,7 +2,9 @@ ramstage-y += c_start.S ramstage-y += cpu.c ramstage-y += pci_ops_conf1.c ramstage-y += pci_ops_conf2.c -ramstage-y += pci_ops_mmconf.c + +ramstage-$(CONFIG_MMCONF_SUPPORT) += pci_ops_mmconf.c + ramstage-y += pci_ops_auto.c ramstage-y += exception.c ramstage-$(CONFIG_IOAPIC) += ioapic.c diff --git a/src/arch/x86/lib/pci_ops_mmconf.c b/src/arch/x86/lib/pci_ops_mmconf.c index 7fcd88a..4f9d826 100644 --- a/src/arch/x86/lib/pci_ops_mmconf.c +++ b/src/arch/x86/lib/pci_ops_mmconf.c @@ -1,5 +1,3 @@ -#if CONFIG_MMCONF_SUPPORT - #include <console/console.h> #include <arch/io.h> #include <arch/pciconf.h> @@ -63,5 +61,3 @@ const struct pci_bus_operations pci_ops_mmconf = { .write16 = pci_mmconf_write_config16, .write32 = pci_mmconf_write_config32, }; - -#endif

1 0

New patch to review for coreboot: 1b785c7 Make Geode GX2 VGA setup work.
by Nils Jacobs 25 Jan '12

25 Jan '12

Nils Jacobs (njacobs8(a)adsltotaal.nl) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/580 -gerrit commit 1b785c7c7c007fab87e773d5ed7c0992b1caede1 Author: Nils Jacobs <njacobs8(a)adsltotaal.nl> Date: Wed Jan 25 22:26:35 2012 +0100 Make Geode GX2 VGA setup work. Add MSR register write for VGA memory setup Add missing license Add bit explanation Change-Id: I1cb36eeccd84f0056c829f50d9864047654ce906 Signed-off-by: Nils Jacobs <njacobs8(a)adsltotaal.nl> --- src/northbridge/amd/gx2/grphinit.c | 83 +++++++++++++++++++++++++++++++++-- 1 files changed, 78 insertions(+), 5 deletions(-) diff --git a/src/northbridge/amd/gx2/grphinit.c b/src/northbridge/amd/gx2/grphinit.c index fce1190..b333c22 100644 --- a/src/northbridge/amd/gx2/grphinit.c +++ b/src/northbridge/amd/gx2/grphinit.c @@ -1,18 +1,91 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * Copyright (C) 2012 Nils Jacobs + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #include <arch/io.h> #include <stdint.h> #include <cpu/amd/vr.h> -#include <device/device.h> -#include "chip.h" -#include "northbridge.h" +#include <console/console.h> +#include <cpu/amd/gx2def.h> +#include <cpu/x86/msr.h> +#include <stdlib.h> + +void geodegx2_vga_msr_init(void); +void graphics_init(void); + +struct msrinit { + u32 msrnum; + msr_t msr; +}; + +static const struct msrinit geodegx2_vga_msr[] = { + /* Enable the GLIU Memory routing to the memory A0000-BFFFF + * PDID1 : Port 4, GLIU0 + * PBASE : 0x000A0 + * PMASK : 0xFFFE0 + */ + {.msrnum = GLIU0_P2D_BM_4, {.lo = 0x0a0fffe0, .hi = 0x80000000}}, +}; + +void geodegx2_vga_msr_init(void) +{ + int i; + for (i = 0; i < ARRAY_SIZE(geodegx2_vga_msr); i++) + wrmsr(geodegx2_vga_msr[i].msrnum, geodegx2_vga_msr[i].msr); +} + /* This function mirrors the Graphics_Init routine in GeodeROM. */ void graphics_init(void) { + uint16_t wClassIndex, wData, res; + /* SoftVG initialization */ + printk(BIOS_DEBUG, "Graphics init...\n"); + + geodegx2_vga_msr_init(); /* Call SoftVG with the main configuration parameters. */ - /* NOTE: SoftVG expects the memory size to be given in 512 KB pages */ - vrWrite((VRC_VG << 8) + VG_MEM_SIZE, 0x0100 | (CONFIG_VIDEO_MB * 2)); + /* NOTE: SoftVG expects the memory size to be given in 512 KB blocks */ + + wClassIndex = (VRC_VG << 8) + VG_CONFIG; + + /* + * Graphics Driver Enabled (13) 0, NO (lets BIOS controls the GP) + * External Monochrome Card Support(12) 0, NO + * Controller Priority Select(11) 1, Primary + * Display Select(10:8) 0x0, CRT + * Graphics Memory Size(7:1) CONFIG_VIDEO_MB >> 1, + * defined in devicetree.cb + * PLL Reference Clock Bypass(0) 0, Default + */ + + /* Video RAM has to be given in 512KB chunks + * the value is read @ 7:1 (value in 7:0 looks like /2) + * so we can add the real value in megabytes + */ + + wData = VG_CFG_PRIORITY | VG_CFG_DSCRT | ((CONFIG_VIDEO_MB * 2) & VG_MEM_MASK); + vrWrite(wClassIndex, wData); + + res = vrRead(wClassIndex); + printk(BIOS_DEBUG, "VRC_VG value: 0x%04x\n", res); }

1 0

New patch to review for coreboot: 9ad3465 Add MSR register write for VGA memory setupMake Geode GX2 VGA setup work.
by Nils Jacobs 25 Jan '12

25 Jan '12

Nils Jacobs (njacobs8(a)adsltotaal.nl) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/579 -gerrit commit 9ad346543e18fa1bfb560feb9e6a92d795e524c3 Author: Nils Jacobs <njacobs8(a)adsltotaal.nl> Date: Wed Jan 25 22:26:35 2012 +0100 Add MSR register write for VGA memory setupMake Geode GX2 VGA setup work. Add MSR register write for VGA memory setup Add missing license Add bit explanation Change-Id: I54d008842e6664fb3ab55bede19ac266617f01aa Signed-off-by: Nils Jacobs <njacobs8(a)adsltotaal.nl> --- src/northbridge/amd/gx2/grphinit.c | 83 +++++++++++++++++++++++++++++++++-- 1 files changed, 78 insertions(+), 5 deletions(-) diff --git a/src/northbridge/amd/gx2/grphinit.c b/src/northbridge/amd/gx2/grphinit.c index fce1190..b333c22 100644 --- a/src/northbridge/amd/gx2/grphinit.c +++ b/src/northbridge/amd/gx2/grphinit.c @@ -1,18 +1,91 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * Copyright (C) 2012 Nils Jacobs + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #include <arch/io.h> #include <stdint.h> #include <cpu/amd/vr.h> -#include <device/device.h> -#include "chip.h" -#include "northbridge.h" +#include <console/console.h> +#include <cpu/amd/gx2def.h> +#include <cpu/x86/msr.h> +#include <stdlib.h> + +void geodegx2_vga_msr_init(void); +void graphics_init(void); + +struct msrinit { + u32 msrnum; + msr_t msr; +}; + +static const struct msrinit geodegx2_vga_msr[] = { + /* Enable the GLIU Memory routing to the memory A0000-BFFFF + * PDID1 : Port 4, GLIU0 + * PBASE : 0x000A0 + * PMASK : 0xFFFE0 + */ + {.msrnum = GLIU0_P2D_BM_4, {.lo = 0x0a0fffe0, .hi = 0x80000000}}, +}; + +void geodegx2_vga_msr_init(void) +{ + int i; + for (i = 0; i < ARRAY_SIZE(geodegx2_vga_msr); i++) + wrmsr(geodegx2_vga_msr[i].msrnum, geodegx2_vga_msr[i].msr); +} + /* This function mirrors the Graphics_Init routine in GeodeROM. */ void graphics_init(void) { + uint16_t wClassIndex, wData, res; + /* SoftVG initialization */ + printk(BIOS_DEBUG, "Graphics init...\n"); + + geodegx2_vga_msr_init(); /* Call SoftVG with the main configuration parameters. */ - /* NOTE: SoftVG expects the memory size to be given in 512 KB pages */ - vrWrite((VRC_VG << 8) + VG_MEM_SIZE, 0x0100 | (CONFIG_VIDEO_MB * 2)); + /* NOTE: SoftVG expects the memory size to be given in 512 KB blocks */ + + wClassIndex = (VRC_VG << 8) + VG_CONFIG; + + /* + * Graphics Driver Enabled (13) 0, NO (lets BIOS controls the GP) + * External Monochrome Card Support(12) 0, NO + * Controller Priority Select(11) 1, Primary + * Display Select(10:8) 0x0, CRT + * Graphics Memory Size(7:1) CONFIG_VIDEO_MB >> 1, + * defined in devicetree.cb + * PLL Reference Clock Bypass(0) 0, Default + */ + + /* Video RAM has to be given in 512KB chunks + * the value is read @ 7:1 (value in 7:0 looks like /2) + * so we can add the real value in megabytes + */ + + wData = VG_CFG_PRIORITY | VG_CFG_DSCRT | ((CONFIG_VIDEO_MB * 2) & VG_MEM_MASK); + vrWrite(wClassIndex, wData); + + res = vrRead(wClassIndex); + printk(BIOS_DEBUG, "VRC_VG value: 0x%04x\n", res); }

1 0

Patch set updated for coreboot: 1cb60b3 Add MSR register write for VGA memory setup Add missing license Add bit explanation
by Nils Jacobs 25 Jan '12

25 Jan '12

Nils Jacobs (njacobs8(a)adsltotaal.nl) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/526 -gerrit commit 1cb60b38b929947dfe32350fb351567224fada60 Author: Nils Jacobs <njacobs8(a)adsltotaal.nl> Date: Wed Jan 25 22:26:35 2012 +0100 Add MSR register write for VGA memory setup Add missing license Add bit explanation Change-Id: Ibf0ee569b1addcad575f20fcfdd6ffc28322ca12 Signed-off-by: Nils Jacobs <njacobs8(a)adsltotaal.nl> --- src/northbridge/amd/gx2/grphinit.c | 83 +++++++++++++++++++++++++++++++++-- 1 files changed, 78 insertions(+), 5 deletions(-) diff --git a/src/northbridge/amd/gx2/grphinit.c b/src/northbridge/amd/gx2/grphinit.c index fce1190..b333c22 100644 --- a/src/northbridge/amd/gx2/grphinit.c +++ b/src/northbridge/amd/gx2/grphinit.c @@ -1,18 +1,91 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * Copyright (C) 2012 Nils Jacobs + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #include <arch/io.h> #include <stdint.h> #include <cpu/amd/vr.h> -#include <device/device.h> -#include "chip.h" -#include "northbridge.h" +#include <console/console.h> +#include <cpu/amd/gx2def.h> +#include <cpu/x86/msr.h> +#include <stdlib.h> + +void geodegx2_vga_msr_init(void); +void graphics_init(void); + +struct msrinit { + u32 msrnum; + msr_t msr; +}; + +static const struct msrinit geodegx2_vga_msr[] = { + /* Enable the GLIU Memory routing to the memory A0000-BFFFF + * PDID1 : Port 4, GLIU0 + * PBASE : 0x000A0 + * PMASK : 0xFFFE0 + */ + {.msrnum = GLIU0_P2D_BM_4, {.lo = 0x0a0fffe0, .hi = 0x80000000}}, +}; + +void geodegx2_vga_msr_init(void) +{ + int i; + for (i = 0; i < ARRAY_SIZE(geodegx2_vga_msr); i++) + wrmsr(geodegx2_vga_msr[i].msrnum, geodegx2_vga_msr[i].msr); +} + /* This function mirrors the Graphics_Init routine in GeodeROM. */ void graphics_init(void) { + uint16_t wClassIndex, wData, res; + /* SoftVG initialization */ + printk(BIOS_DEBUG, "Graphics init...\n"); + + geodegx2_vga_msr_init(); /* Call SoftVG with the main configuration parameters. */ - /* NOTE: SoftVG expects the memory size to be given in 512 KB pages */ - vrWrite((VRC_VG << 8) + VG_MEM_SIZE, 0x0100 | (CONFIG_VIDEO_MB * 2)); + /* NOTE: SoftVG expects the memory size to be given in 512 KB blocks */ + + wClassIndex = (VRC_VG << 8) + VG_CONFIG; + + /* + * Graphics Driver Enabled (13) 0, NO (lets BIOS controls the GP) + * External Monochrome Card Support(12) 0, NO + * Controller Priority Select(11) 1, Primary + * Display Select(10:8) 0x0, CRT + * Graphics Memory Size(7:1) CONFIG_VIDEO_MB >> 1, + * defined in devicetree.cb + * PLL Reference Clock Bypass(0) 0, Default + */ + + /* Video RAM has to be given in 512KB chunks + * the value is read @ 7:1 (value in 7:0 looks like /2) + * so we can add the real value in megabytes + */ + + wData = VG_CFG_PRIORITY | VG_CFG_DSCRT | ((CONFIG_VIDEO_MB * 2) & VG_MEM_MASK); + vrWrite(wClassIndex, wData); + + res = vrRead(wClassIndex); + printk(BIOS_DEBUG, "VRC_VG value: 0x%04x\n", res); }

1 0

Re: [coreboot] Change in coreboot[master]: Inagua: Synchronize AMD/inagua mainboard.
by Wolfgang Kamp - datakamp 25 Jan '12

25 Jan '12

Hello Marc, my debugging shows that SPD reading is ok after Warmstart. This can not be the problem. The error check reports 7 errors when system hangs. Is there a problem with cache as RAM? Is the buffer of SPD data corrupt? I don't know what code here really does. Have you an idea what I can do next? mmflow.c //---------------------------------------------------------------- // Check for errors and return //---------------------------------------------------------------- AGESA_TESTPOINT (TpProcMemEnd, &MemPtr->StdHeader); for (Die = 0; Die < DieCount; Die++) { if (NBPtr[Die].MCTPtr->ErrCode > Retval) { Retval = NBPtr[Die].MCTPtr->ErrCode; } } printk(BIOS_DEBUG, "TpProcMemEnd Retval = 0x%x \n", Retval); return Retval; } Regards, Wolfgang -----Ursprüngliche Nachricht----- Von: Marc Jones [mailto:marcj303@gmail.com] Gesendet: Dienstag, 24. Januar 2012 19:15 An: Wolfgang Kamp - datakamp Cc: coreboot(a)coreboot.org Betreff: Re: [coreboot] Change in coreboot[master]: Inagua: Synchronize AMD/inagua mainboard. On Tue, Jan 24, 2012 at 5:38 AM, Wolfgang Kamp - datakamp <wmkamp(a)datakamp.de> wrote: > > Hi Marc, > > DIMM address and i2c address are ok. > Please look at the log. I think the SB800 is unaccessable. > > Regards > > Wolfgang > The sb800 is accessible, it is fetching rom and initializing devices that it sees: sb800_enable() PCI: 00:11.0 [1002/4390] enabled sb800_enable() PCI: 00:12.0 [1002/4397] ops PCI: 00:12.0 [1002/4397] enabled sb800_enable() PCI: Static device PCI: 00:12.1 not found, disabling it. sb800_enable() PCI: 00:12.2 [1002/4396] ops PCI: 00:12.2 [1002/4396] enabled sb800_enable() PCI: 00:13.0 [1002/4397] ops PCI: 00:13.0 [1002/4397] enabled sb800_enable() PCI: Static device PCI: 00:13.1 not found, disabling it. sb800_enable() PCI: 00:13.2 [1002/4396] ops PCI: 00:13.2 [1002/4396] enabled sb800_enable() sm_init(). .. PCI: 00:14.0 [1002/4385] enabled sb800_enable() PCI: Static device PCI: 00:14.1 not found, disabling it. sb800_enable() hda enabled PCI: 00:14.2 [1002/4383] ops PCI: 00:14.2 [1002/4383] enabled !4.0 is the smbus device, so that is enabled. I think that you need to see what in the spd read fails. Also, see if you can read it earlier in the init. There could be a different device setting that causes the problem. Check that te SMbus enable is set as expected. Check that the PM registers that set the iobase are accessible. Marc > -----Ursprüngliche Nachricht----- > Von: Marc Jones [mailto:marcj303@gmail.com] > Gesendet: Freitag, 20. Januar 2012 18:46 > An: Wolfgang Kamp - datakamp > Cc: coreboot(a)coreboot.org > Betreff: Re: [coreboot] Change in coreboot[master]: Inagua: Synchronize AMD/inagua mainboard. > > On Fri, Jan 20, 2012 at 9:45 AM, Wolfgang Kamp - datakamp > <wmkamp(a)datakamp.de> wrote: >> Hello Marc, >> >> I reviewed the code and it looks good. >> But real testing shows an issue with soft restart (UBUNTU). >> The southbridge seems to hang. Coreboot stops because it could not read the SPI ROM of DIMM Module. >> Please see logs. >> The cold start log also reports errors but will successful boot Ubuntu. >> >> Regards >> >> Wolfgang >> > > Woflgang, > > The ASSERTs in the passing case are non-critical failures for early > heap use. These are AGESA bugs and have been reported to AMD, but they > are not critical. > > As you said, The bad failure is this one: > > EventLog: EventClass = 7, EventInfo = 4011c00. > Param1 = 0, Param2 = 0. > Param3 = 0, Param4 = 0. > > Which is the SPD problem... > #define MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM 0x04011C00 ///< No DIMMs > have been found > > Can you check what happens in AmdMemoryReadSPD(), in dimmSpd.c? Does > it check the correct dimm address? Is the i2c io address set > correctly? > > Thanks, > Marc > > > > > >> >> >> -----Ursprüngliche Nachricht----- >> Von: gerrit code review [mailto:gerrit@coreboot.org] >> Gesendet: Freitag, 20. Januar 2012 00:52 >> An: Wolfgang Kamp - datakamp >> Cc: Kerry Sheh >> Betreff: Change in coreboot[master]: Inagua: Synchronize AMD/inagua mainboard. >> >> From Marc Jones <marcj303(a)gmail.com>: >> >> Hello Wolfgang Kamp, >> >> I'd like you to do a code review. Please visit >> >> http://review.coreboot.org/542 >> >> to review the following change. >> >> Change subject: Inagua: Synchronize AMD/inagua mainboard. >> ..................................................................... >> >> Inagua: Synchronize AMD/inagua mainboard. >> >> AMD/persimmon mainboard code is derived from AMD/inagua mainbard. >> Persimmom update a lot in the last few month, sync these modification to inagua. >> >> Change-Id: Ia038e5a2b9550fe81bb075f31e30b98354758e9e >> Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> >> Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> >> --- >> M src/mainboard/amd/inagua/BiosCallOuts.c >> M src/mainboard/amd/inagua/BiosCallOuts.h >> M src/mainboard/amd/inagua/Kconfig >> M src/mainboard/amd/inagua/Makefile.inc >> M src/mainboard/amd/inagua/OptionsIds.h >> M src/mainboard/amd/inagua/PlatformGnbPcie.c >> D src/mainboard/amd/inagua/acpi/ssdt2.asl >> D src/mainboard/amd/inagua/acpi/ssdt3.asl >> D src/mainboard/amd/inagua/acpi/ssdt4.asl >> D src/mainboard/amd/inagua/acpi/ssdt5.asl >> M src/mainboard/amd/inagua/acpi_tables.c >> M src/mainboard/amd/inagua/agesawrapper.c >> M src/mainboard/amd/inagua/agesawrapper.h >> M src/mainboard/amd/inagua/buildOpts.c >> M src/mainboard/amd/inagua/devicetree.cb >> M src/mainboard/amd/inagua/dimmSpd.c >> M src/mainboard/amd/inagua/dsdt.asl >> M src/mainboard/amd/inagua/fadt.c >> M src/mainboard/amd/inagua/get_bus_conf.c >> M src/mainboard/amd/inagua/irq_tables.c >> M src/mainboard/amd/inagua/mainboard.c >> M src/mainboard/amd/inagua/mptable.c >> M src/mainboard/amd/inagua/platform_cfg.h >> M src/mainboard/amd/inagua/romstage.c >> 24 files changed, 249 insertions(+), 717 deletions(-) >> >> >> git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/542/2 >> -- >> To view, visit http://review.coreboot.org/542 >> To unsubscribe, visit http://review.coreboot.org/settings >> >> Gerrit-MessageType: newchange >> Gerrit-Change-Id: Ia038e5a2b9550fe81bb075f31e30b98354758e9e >> Gerrit-PatchSet: 2 >> Gerrit-Project: coreboot >> Gerrit-Branch: master >> Gerrit-Owner: Kerry Sheh <shekairui(a)gmail.com> >> Gerrit-Reviewer: Kerry Sheh <shekairui(a)gmail.com> >> Gerrit-Reviewer: Wolfgang Kamp <wmkamp(a)datakamp.de> >> Gerrit-Reviewer: build bot (Jenkins) >> >> >> >> >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> http://www.coreboot.org/mailman/listinfo/coreboot > > > > -- > http://se-eng.com > > > > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot -- http://se-eng.com

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Patch merged into coreboot/master: d9da3f0 Mahogany Fam10 MPtable fix
by gerrit＠coreboot.org 24 Jan '12

24 Jan '12

the following patch was just integrated into master: commit d9da3f007263804da7c941ee5631bffccd7fa76a Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Thu Jan 19 14:28:32 2012 -0700 Mahogany Fam10 MPtable fix Make changes MPtable to match ACPI tables. Change-Id: I387f301370582fcb5e0d348d793333a919d2f373 Signed-off-by: Marc Jones <marcj303(a)gmail.com> Build-Tested: build bot (Jenkins) at Tue Jan 24 06:14:40 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Tue Jan 24 22:54:23 2012, giving +2 See http://review.coreboot.org/575 for details. -gerrit

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Patch merged into coreboot/master: c52e62d RD890: pci_ids update
by gerrit＠coreboot.org 24 Jan '12

24 Jan '12

the following patch was just integrated into master: commit c52e62de11ca8c0bc92677794fbfe2f0fb331ea8 Author: Kerry Sheh <shekairui(a)gmail.com> Date: Fri Jan 20 13:58:53 2012 +0800 RD890: pci_ids update RD890 CIMX support AMD RD890TV, RX780, RD780, SR56x0, RD890 and 990FX chipsets, add their pci device id respectively. Change-Id: I30c62c5802279ff2ee8da1cae41395e6899339bb Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> Build-Tested: build bot (Jenkins) at Fri Jan 20 08:10:55 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Tue Jan 24 22:58:05 2012, giving +2 See http://review.coreboot.org/558 for details. -gerrit

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Patch merged into coreboot/master: f878bc4 AMD Mahogany Fam10 ACPI table fixes.
by gerrit＠coreboot.org 24 Jan '12

24 Jan '12

the following patch was just integrated into master: commit f878bc41e0e6c46eab928c7bcb1330e22a4f5237 Author: Marc Jones <marcj303(a)gmail.com> Date: Fri Jan 13 14:39:48 2012 -0700 AMD Mahogany Fam10 ACPI table fixes. Fix the ACPI IRQ routing. Also. fix the SSDT generations and TOM2 fixup. Change-Id: I03e6de7bb58440058306c9c9888eb2961748c385 Signed-off-by: Marc Jones <marcj303(a)gmail.com> Build-Tested: build bot (Jenkins) at Tue Jan 24 06:03:58 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Tue Jan 24 22:46:05 2012, giving +2 See http://review.coreboot.org/574 for details. -gerrit

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coreboot January 2012