coreboot January 2012

coreboot@coreboot.org

40 participants
302 discussions

Patch merged into coreboot/master: 07a8092 pci_ops_conf: Indentation fixes
by gerrit＠coreboot.org 24 Jan '12

24 Jan '12

the following patch was just integrated into master: commit 07a809248b817de1f1476cf84d4b89f8e98e43eb Author: Vikram Narayanan <vikram186(a)gmail.com> Date: Tue Jan 24 19:17:47 2012 +0530 pci_ops_conf: Indentation fixes Indentation fixes in src/arch/x86/lib/pci_ops_conf{1,2}.c Change-Id: I56e8ff6d2ee3a0b871b40577e10c99dea4b3b1bd Signed-off-by: Vikram Narayanan <vikram186(a)gmail.com> Build-Tested: build bot (Jenkins) at Tue Jan 24 15:01:52 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Tue Jan 24 22:45:31 2012, giving +2 See http://review.coreboot.org/576 for details. -gerrit

1 0

Patch merged into coreboot/master: 4730e47 pci_ops_mmconf: Indentation fixes
by gerrit＠coreboot.org 24 Jan '12

24 Jan '12

the following patch was just integrated into master: commit 4730e47a8b3553bc55b1a9c2b7863e3b6fd9ec31 Author: Vikram Narayanan <vikram186(a)gmail.com> Date: Tue Jan 24 20:18:56 2012 +0530 pci_ops_mmconf: Indentation fixes Indentation fixes in src/arch/x86/lib/pci_ops_mmconf.c Change-Id: If8337bae06295db16ed1c129ab76dea37eb465ae Signed-off-by: Vikram Narayanan <vikram186(a)gmail.com> Build-Tested: build bot (Jenkins) at Tue Jan 24 16:03:28 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Tue Jan 24 22:45:01 2012, giving +2 See http://review.coreboot.org/577 for details. -gerrit

1 0

Re: [coreboot] Change in coreboot[master]: Inagua: Synchronize AMD/inagua mainboard.
by Marc Jones 24 Jan '12

24 Jan '12

On Tue, Jan 24, 2012 at 5:38 AM, Wolfgang Kamp - datakamp <wmkamp(a)datakamp.de> wrote: > > Hi Marc, > > DIMM address and i2c address are ok. > Please look at the log. I think the SB800 is unaccessable. > > Regards > > Wolfgang > The sb800 is accessible, it is fetching rom and initializing devices that it sees: sb800_enable() PCI: 00:11.0 [1002/4390] enabled sb800_enable() PCI: 00:12.0 [1002/4397] ops PCI: 00:12.0 [1002/4397] enabled sb800_enable() PCI: Static device PCI: 00:12.1 not found, disabling it. sb800_enable() PCI: 00:12.2 [1002/4396] ops PCI: 00:12.2 [1002/4396] enabled sb800_enable() PCI: 00:13.0 [1002/4397] ops PCI: 00:13.0 [1002/4397] enabled sb800_enable() PCI: Static device PCI: 00:13.1 not found, disabling it. sb800_enable() PCI: 00:13.2 [1002/4396] ops PCI: 00:13.2 [1002/4396] enabled sb800_enable() sm_init(). ... PCI: 00:14.0 [1002/4385] enabled sb800_enable() PCI: Static device PCI: 00:14.1 not found, disabling it. sb800_enable() hda enabled PCI: 00:14.2 [1002/4383] ops PCI: 00:14.2 [1002/4383] enabled !4.0 is the smbus device, so that is enabled. I think that you need to see what in the spd read fails. Also, see if you can read it earlier in the init. There could be a different device setting that causes the problem. Check that te SMbus enable is set as expected. Check that the PM registers that set the iobase are accessible. Marc > -----Ursprüngliche Nachricht----- > Von: Marc Jones [mailto:marcj303@gmail.com] > Gesendet: Freitag, 20. Januar 2012 18:46 > An: Wolfgang Kamp - datakamp > Cc: coreboot(a)coreboot.org > Betreff: Re: [coreboot] Change in coreboot[master]: Inagua: Synchronize AMD/inagua mainboard. > > On Fri, Jan 20, 2012 at 9:45 AM, Wolfgang Kamp - datakamp > <wmkamp(a)datakamp.de> wrote: >> Hello Marc, >> >> I reviewed the code and it looks good. >> But real testing shows an issue with soft restart (UBUNTU). >> The southbridge seems to hang. Coreboot stops because it could not read the SPI ROM of DIMM Module. >> Please see logs. >> The cold start log also reports errors but will successful boot Ubuntu. >> >> Regards >> >> Wolfgang >> > > Woflgang, > > The ASSERTs in the passing case are non-critical failures for early > heap use. These are AGESA bugs and have been reported to AMD, but they > are not critical. > > As you said, The bad failure is this one: > > EventLog: EventClass = 7, EventInfo = 4011c00. > Param1 = 0, Param2 = 0. > Param3 = 0, Param4 = 0. > > Which is the SPD problem... > #define MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM 0x04011C00 ///< No DIMMs > have been found > > Can you check what happens in AmdMemoryReadSPD(), in dimmSpd.c? Does > it check the correct dimm address? Is the i2c io address set > correctly? > > Thanks, > Marc > > > > > >> >> >> -----Ursprüngliche Nachricht----- >> Von: gerrit code review [mailto:gerrit@coreboot.org] >> Gesendet: Freitag, 20. Januar 2012 00:52 >> An: Wolfgang Kamp - datakamp >> Cc: Kerry Sheh >> Betreff: Change in coreboot[master]: Inagua: Synchronize AMD/inagua mainboard. >> >> From Marc Jones <marcj303(a)gmail.com>: >> >> Hello Wolfgang Kamp, >> >> I'd like you to do a code review. Please visit >> >> http://review.coreboot.org/542 >> >> to review the following change. >> >> Change subject: Inagua: Synchronize AMD/inagua mainboard. >> ..................................................................... >> >> Inagua: Synchronize AMD/inagua mainboard. >> >> AMD/persimmon mainboard code is derived from AMD/inagua mainbard. >> Persimmom update a lot in the last few month, sync these modification to inagua. >> >> Change-Id: Ia038e5a2b9550fe81bb075f31e30b98354758e9e >> Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> >> Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> >> --- >> M src/mainboard/amd/inagua/BiosCallOuts.c >> M src/mainboard/amd/inagua/BiosCallOuts.h >> M src/mainboard/amd/inagua/Kconfig >> M src/mainboard/amd/inagua/Makefile.inc >> M src/mainboard/amd/inagua/OptionsIds.h >> M src/mainboard/amd/inagua/PlatformGnbPcie.c >> D src/mainboard/amd/inagua/acpi/ssdt2.asl >> D src/mainboard/amd/inagua/acpi/ssdt3.asl >> D src/mainboard/amd/inagua/acpi/ssdt4.asl >> D src/mainboard/amd/inagua/acpi/ssdt5.asl >> M src/mainboard/amd/inagua/acpi_tables.c >> M src/mainboard/amd/inagua/agesawrapper.c >> M src/mainboard/amd/inagua/agesawrapper.h >> M src/mainboard/amd/inagua/buildOpts.c >> M src/mainboard/amd/inagua/devicetree.cb >> M src/mainboard/amd/inagua/dimmSpd.c >> M src/mainboard/amd/inagua/dsdt.asl >> M src/mainboard/amd/inagua/fadt.c >> M src/mainboard/amd/inagua/get_bus_conf.c >> M src/mainboard/amd/inagua/irq_tables.c >> M src/mainboard/amd/inagua/mainboard.c >> M src/mainboard/amd/inagua/mptable.c >> M src/mainboard/amd/inagua/platform_cfg.h >> M src/mainboard/amd/inagua/romstage.c >> 24 files changed, 249 insertions(+), 717 deletions(-) >> >> >> git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/542/2 >> -- >> To view, visit http://review.coreboot.org/542 >> To unsubscribe, visit http://review.coreboot.org/settings >> >> Gerrit-MessageType: newchange >> Gerrit-Change-Id: Ia038e5a2b9550fe81bb075f31e30b98354758e9e >> Gerrit-PatchSet: 2 >> Gerrit-Project: coreboot >> Gerrit-Branch: master >> Gerrit-Owner: Kerry Sheh <shekairui(a)gmail.com> >> Gerrit-Reviewer: Kerry Sheh <shekairui(a)gmail.com> >> Gerrit-Reviewer: Wolfgang Kamp <wmkamp(a)datakamp.de> >> Gerrit-Reviewer: build bot (Jenkins) >> >> >> >> >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> http://www.coreboot.org/mailman/listinfo/coreboot > > > > -- > http://se-eng.com > > > > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot -- http://se-eng.com

1 0

Job at Norway
by Adam Sulmicki 24 Jan '12

24 Jan '12

Hello all, Creator of the ADLO fame (http://www.coreboot.org/ADLO) is back from sabbatical and is looking for a job. Preferably something linuxbios^w coreboot related but I am open for other options. Preferred country to live at is Norway. Sincerely, Adam Sulmicki

1 0

New patch to review for coreboot: 4d00fc2 pci_ops_mmconf: Move conditional compilation to Makefile
by Vikram Narayanan 24 Jan '12

24 Jan '12

Vikram Narayanan (vikram186(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/578 -gerrit commit 4d00fc2cc948df00447b1140dbcb8cccaa816cac Author: Vikram Narayanan <vikram186(a)gmail.com> Date: Tue Jan 24 20:22:20 2012 +0530 pci_ops_mmconf: Move conditional compilation to Makefile Moved the conditional compilation out of the source file Change-Id: Ic4045006f39d70f4a0bc37d1bd5e073ed8477c68 Signed-off-by: Vikram Narayanan <vikram186(a)gmail.com> --- src/arch/x86/lib/Makefile.inc | 4 ++++ src/arch/x86/lib/pci_ops_mmconf.c | 4 ---- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/arch/x86/lib/Makefile.inc b/src/arch/x86/lib/Makefile.inc index 3092388..8da4719 100644 --- a/src/arch/x86/lib/Makefile.inc +++ b/src/arch/x86/lib/Makefile.inc @@ -2,7 +2,11 @@ ramstage-y += c_start.S ramstage-y += cpu.c ramstage-y += pci_ops_conf1.c ramstage-y += pci_ops_conf2.c + +ifeq ($(CONFIG_MMCONF_SUPPORT),y) ramstage-y += pci_ops_mmconf.c +endif + ramstage-y += pci_ops_auto.c ramstage-y += exception.c ramstage-$(CONFIG_IOAPIC) += ioapic.c diff --git a/src/arch/x86/lib/pci_ops_mmconf.c b/src/arch/x86/lib/pci_ops_mmconf.c index 7fcd88a..4f9d826 100644 --- a/src/arch/x86/lib/pci_ops_mmconf.c +++ b/src/arch/x86/lib/pci_ops_mmconf.c @@ -1,5 +1,3 @@ -#if CONFIG_MMCONF_SUPPORT - #include <console/console.h> #include <arch/io.h> #include <arch/pciconf.h> @@ -63,5 +61,3 @@ const struct pci_bus_operations pci_ops_mmconf = { .write16 = pci_mmconf_write_config16, .write32 = pci_mmconf_write_config32, }; - -#endif

1 0

New patch to review for coreboot: 4730e47 pci_ops_mmconf: Indentation fixes
by Vikram Narayanan 24 Jan '12

24 Jan '12

Vikram Narayanan (vikram186(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/577 -gerrit commit 4730e47a8b3553bc55b1a9c2b7863e3b6fd9ec31 Author: Vikram Narayanan <vikram186(a)gmail.com> Date: Tue Jan 24 20:18:56 2012 +0530 pci_ops_mmconf: Indentation fixes Indentation fixes in src/arch/x86/lib/pci_ops_mmconf.c Change-Id: If8337bae06295db16ed1c129ab76dea37eb465ae Signed-off-by: Vikram Narayanan <vikram186(a)gmail.com> --- src/arch/x86/lib/pci_ops_mmconf.c | 49 +++++++++++++++++++----------------- 1 files changed, 26 insertions(+), 23 deletions(-) diff --git a/src/arch/x86/lib/pci_ops_mmconf.c b/src/arch/x86/lib/pci_ops_mmconf.c index 7d8fb32..7fcd88a 100644 --- a/src/arch/x86/lib/pci_ops_mmconf.c +++ b/src/arch/x86/lib/pci_ops_mmconf.c @@ -7,56 +7,59 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> - /* * Functions for accessing PCI configuration space with mmconf accesses */ -#define PCI_MMIO_ADDR(SEGBUS, DEVFN, WHERE) ( \ - CONFIG_MMCONF_BASE_ADDRESS | \ - (((SEGBUS) & 0xFFF) << 20) | \ - (((DEVFN) & 0xFF) << 12) | \ - ((WHERE) & 0xFFF)) +#define PCI_MMIO_ADDR(SEGBUS, DEVFN, WHERE) \ + (CONFIG_MMCONF_BASE_ADDRESS |\ + (((SEGBUS) & 0xFFF) << 20) |\ + (((DEVFN) & 0xFF) << 12) |\ + ((WHERE) & 0xFFF)) #include <arch/mmio_conf.h> -static uint8_t pci_mmconf_read_config8(struct bus *pbus, int bus, int devfn, int where) +static uint8_t pci_mmconf_read_config8(struct bus *pbus, int bus, int devfn, + int where) { - return (read8x(PCI_MMIO_ADDR(bus, devfn, where))); + return (read8x(PCI_MMIO_ADDR(bus, devfn, where))); } -static uint16_t pci_mmconf_read_config16(struct bus *pbus, int bus, int devfn, int where) +static uint16_t pci_mmconf_read_config16(struct bus *pbus, int bus, int devfn, + int where) { - return (read16x(PCI_MMIO_ADDR(bus, devfn, where) & ~1)); + return (read16x(PCI_MMIO_ADDR(bus, devfn, where) & ~1)); } -static uint32_t pci_mmconf_read_config32(struct bus *pbus, int bus, int devfn, int where) +static uint32_t pci_mmconf_read_config32(struct bus *pbus, int bus, int devfn, + int where) { - return (read32x(PCI_MMIO_ADDR(bus, devfn, where) & ~3)); + return (read32x(PCI_MMIO_ADDR(bus, devfn, where) & ~3)); } -static void pci_mmconf_write_config8(struct bus *pbus, int bus, int devfn, int where, uint8_t value) +static void pci_mmconf_write_config8(struct bus *pbus, int bus, int devfn, + int where, uint8_t value) { - write8x(PCI_MMIO_ADDR(bus, devfn, where), value); + write8x(PCI_MMIO_ADDR(bus, devfn, where), value); } -static void pci_mmconf_write_config16(struct bus *pbus, int bus, int devfn, int where, uint16_t value) +static void pci_mmconf_write_config16(struct bus *pbus, int bus, int devfn, + int where, uint16_t value) { - write16x(PCI_MMIO_ADDR(bus, devfn, where) & ~1, value); + write16x(PCI_MMIO_ADDR(bus, devfn, where) & ~1, value); } -static void pci_mmconf_write_config32(struct bus *pbus, int bus, int devfn, int where, uint32_t value) +static void pci_mmconf_write_config32(struct bus *pbus, int bus, int devfn, + int where, uint32_t value) { - write32x(PCI_MMIO_ADDR(bus, devfn, where) & ~3, value); + write32x(PCI_MMIO_ADDR(bus, devfn, where) & ~3, value); } - -const struct pci_bus_operations pci_ops_mmconf = -{ - .read8 = pci_mmconf_read_config8, +const struct pci_bus_operations pci_ops_mmconf = { + .read8 = pci_mmconf_read_config8, .read16 = pci_mmconf_read_config16, .read32 = pci_mmconf_read_config32, - .write8 = pci_mmconf_write_config8, + .write8 = pci_mmconf_write_config8, .write16 = pci_mmconf_write_config16, .write32 = pci_mmconf_write_config32, };

1 0

New patch to review for coreboot: 07a8092 pci_ops_conf: Indentation fixes
by Vikram Narayanan 24 Jan '12

24 Jan '12

Vikram Narayanan (vikram186(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/576 -gerrit commit 07a809248b817de1f1476cf84d4b89f8e98e43eb Author: Vikram Narayanan <vikram186(a)gmail.com> Date: Tue Jan 24 19:17:47 2012 +0530 pci_ops_conf: Indentation fixes Indentation fixes in src/arch/x86/lib/pci_ops_conf{1,2}.c Change-Id: I56e8ff6d2ee3a0b871b40577e10c99dea4b3b1bd Signed-off-by: Vikram Narayanan <vikram186(a)gmail.com> --- src/arch/x86/lib/pci_ops_conf1.c | 56 +++++++++++++++++++++---------------- src/arch/x86/lib/pci_ops_conf2.c | 26 ++++++++++------- 2 files changed, 47 insertions(+), 35 deletions(-) diff --git a/src/arch/x86/lib/pci_ops_conf1.c b/src/arch/x86/lib/pci_ops_conf1.c index 36db54c..266a9cc 100644 --- a/src/arch/x86/lib/pci_ops_conf1.c +++ b/src/arch/x86/lib/pci_ops_conf1.c @@ -9,55 +9,63 @@ */ #if CONFIG_PCI_IO_CFG_EXT == 0 -#define CONFIG_CMD(bus,devfn, where) (0x80000000 | (bus << 16) | (devfn << 8) | (where & ~3)) +#define CONFIG_CMD(bus,devfn, where) (0x80000000 | (bus << 16) | \ + (devfn << 8) | (where & ~3)) #else -#define CONFIG_CMD(bus,devfn, where) (0x80000000 | (bus << 16) | (devfn << 8) | ((where & 0xff) & ~3) | ((where & 0xf00)<<16) ) +#define CONFIG_CMD(bus,devfn, where) (0x80000000 | (bus << 16) | \ + (devfn << 8) | ((where & 0xff) & ~3) |\ + ((where & 0xf00)<<16)) #endif -static uint8_t pci_conf1_read_config8(struct bus *pbus, int bus, int devfn, int where) +static uint8_t pci_conf1_read_config8(struct bus *pbus, int bus, int devfn, + int where) { - outl(CONFIG_CMD(bus, devfn, where), 0xCF8); - return inb(0xCFC + (where & 3)); + outl(CONFIG_CMD(bus, devfn, where), 0xCF8); + return inb(0xCFC + (where & 3)); } -static uint16_t pci_conf1_read_config16(struct bus *pbus, int bus, int devfn, int where) +static uint16_t pci_conf1_read_config16(struct bus *pbus, int bus, int devfn, + int where) { - outl(CONFIG_CMD(bus, devfn, where), 0xCF8); - return inw(0xCFC + (where & 2)); + outl(CONFIG_CMD(bus, devfn, where), 0xCF8); + return inw(0xCFC + (where & 2)); } -static uint32_t pci_conf1_read_config32(struct bus *pbus, int bus, int devfn, int where) +static uint32_t pci_conf1_read_config32(struct bus *pbus, int bus, int devfn, + int where) { - outl(CONFIG_CMD(bus, devfn, where), 0xCF8); - return inl(0xCFC); + outl(CONFIG_CMD(bus, devfn, where), 0xCF8); + return inl(0xCFC); } -static void pci_conf1_write_config8(struct bus *pbus, int bus, int devfn, int where, uint8_t value) +static void pci_conf1_write_config8(struct bus *pbus, int bus, int devfn, + int where, uint8_t value) { - outl(CONFIG_CMD(bus, devfn, where), 0xCF8); - outb(value, 0xCFC + (where & 3)); + outl(CONFIG_CMD(bus, devfn, where), 0xCF8); + outb(value, 0xCFC + (where & 3)); } -static void pci_conf1_write_config16(struct bus *pbus, int bus, int devfn, int where, uint16_t value) +static void pci_conf1_write_config16(struct bus *pbus, int bus, int devfn, + int where, uint16_t value) { - outl(CONFIG_CMD(bus, devfn, where), 0xCF8); - outw(value, 0xCFC + (where & 2)); + outl(CONFIG_CMD(bus, devfn, where), 0xCF8); + outw(value, 0xCFC + (where & 2)); } -static void pci_conf1_write_config32(struct bus *pbus, int bus, int devfn, int where, uint32_t value) +static void pci_conf1_write_config32(struct bus *pbus, int bus, int devfn, + int where, uint32_t value) { - outl(CONFIG_CMD(bus, devfn, where), 0xCF8); - outl(value, 0xCFC); + outl(CONFIG_CMD(bus, devfn, where), 0xCF8); + outl(value, 0xCFC); } #undef CONFIG_CMD -const struct pci_bus_operations pci_cf8_conf1 = -{ - .read8 = pci_conf1_read_config8, +const struct pci_bus_operations pci_cf8_conf1 = { + .read8 = pci_conf1_read_config8, .read16 = pci_conf1_read_config16, .read32 = pci_conf1_read_config32, - .write8 = pci_conf1_write_config8, + .write8 = pci_conf1_write_config8, .write16 = pci_conf1_write_config16, .write32 = pci_conf1_write_config32, }; diff --git a/src/arch/x86/lib/pci_ops_conf2.c b/src/arch/x86/lib/pci_ops_conf2.c index 839f5b4..e89c933 100644 --- a/src/arch/x86/lib/pci_ops_conf2.c +++ b/src/arch/x86/lib/pci_ops_conf2.c @@ -12,7 +12,8 @@ #define FUNC(devfn) (((devfn & 7) << 1) | 0xf0) #define SET(bus,devfn) outb(FUNC(devfn), 0xCF8); outb(bus, 0xCFA); -static uint8_t pci_conf2_read_config8(struct bus *pbus, int bus, int devfn, int where) +static uint8_t pci_conf2_read_config8(struct bus *pbus, int bus, int devfn, + int where) { uint8_t value; SET(bus, devfn); @@ -21,7 +22,8 @@ static uint8_t pci_conf2_read_config8(struct bus *pbus, int bus, int devfn, int return value; } -static uint16_t pci_conf2_read_config16(struct bus *pbus, int bus, int devfn, int where) +static uint16_t pci_conf2_read_config16(struct bus *pbus, int bus, int devfn, + int where) { uint16_t value; SET(bus, devfn); @@ -30,7 +32,8 @@ static uint16_t pci_conf2_read_config16(struct bus *pbus, int bus, int devfn, in return value; } -static uint32_t pci_conf2_read_config32(struct bus *pbus, int bus, int devfn, int where) +static uint32_t pci_conf2_read_config32(struct bus *pbus, int bus, int devfn, + int where) { uint32_t value; SET(bus, devfn); @@ -39,21 +42,24 @@ static uint32_t pci_conf2_read_config32(struct bus *pbus, int bus, int devfn, in return value; } -static void pci_conf2_write_config8(struct bus *pbus, int bus, int devfn, int where, uint8_t value) +static void pci_conf2_write_config8(struct bus *pbus, int bus, int devfn, + int where, uint8_t value) { SET(bus, devfn); outb(value, IOADDR(devfn, where)); outb(0, 0xCF8); } -static void pci_conf2_write_config16(struct bus *pbus, int bus, int devfn, int where, uint16_t value) +static void pci_conf2_write_config16(struct bus *pbus, int bus, int devfn, + int where, uint16_t value) { SET(bus, devfn); outw(value, IOADDR(devfn, where)); outb(0, 0xCF8); } -static void pci_conf2_write_config32(struct bus *pbus, int bus, int devfn, int where, uint32_t value) +static void pci_conf2_write_config32(struct bus *pbus, int bus, int devfn, + int where, uint32_t value) { SET(bus, devfn); outl(value, IOADDR(devfn, where)); @@ -64,13 +70,11 @@ static void pci_conf2_write_config32(struct bus *pbus, int bus, int devfn, int w #undef IOADDR #undef FUNC -const struct pci_bus_operations pci_cf8_conf2 = -{ - .read8 = pci_conf2_read_config8, +const struct pci_bus_operations pci_cf8_conf2 = { + .read8 = pci_conf2_read_config8, .read16 = pci_conf2_read_config16, .read32 = pci_conf2_read_config32, - .write8 = pci_conf2_write_config8, + .write8 = pci_conf2_write_config8, .write16 = pci_conf2_write_config16, .write32 = pci_conf2_write_config32, }; -

1 0

Re: [coreboot] Change in coreboot[master]: Inagua: Synchronize AMD/inagua mainboard.
by Wolfgang Kamp - datakamp 24 Jan '12

24 Jan '12

Hi Marc, DIMM address and i2c address are ok. Please look at the log. I think the SB800 is unaccessable. Regards Wolfgang -----Ursprüngliche Nachricht----- Von: Marc Jones [mailto:marcj303@gmail.com] Gesendet: Freitag, 20. Januar 2012 18:46 An: Wolfgang Kamp - datakamp Cc: coreboot(a)coreboot.org Betreff: Re: [coreboot] Change in coreboot[master]: Inagua: Synchronize AMD/inagua mainboard. On Fri, Jan 20, 2012 at 9:45 AM, Wolfgang Kamp - datakamp <wmkamp(a)datakamp.de> wrote: > Hello Marc, > > I reviewed the code and it looks good. > But real testing shows an issue with soft restart (UBUNTU). > The southbridge seems to hang. Coreboot stops because it could not read the SPI ROM of DIMM Module. > Please see logs. > The cold start log also reports errors but will successful boot Ubuntu. > > Regards > > Wolfgang > Woflgang, The ASSERTs in the passing case are non-critical failures for early heap use. These are AGESA bugs and have been reported to AMD, but they are not critical. As you said, The bad failure is this one: EventLog: EventClass = 7, EventInfo = 4011c00. Param1 = 0, Param2 = 0. Param3 = 0, Param4 = 0. Which is the SPD problem... #define MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM 0x04011C00 ///< No DIMMs have been found Can you check what happens in AmdMemoryReadSPD(), in dimmSpd.c? Does it check the correct dimm address? Is the i2c io address set correctly? Thanks, Marc > > > -----Ursprüngliche Nachricht----- > Von: gerrit code review [mailto:gerrit@coreboot.org] > Gesendet: Freitag, 20. Januar 2012 00:52 > An: Wolfgang Kamp - datakamp > Cc: Kerry Sheh > Betreff: Change in coreboot[master]: Inagua: Synchronize AMD/inagua mainboard. > > From Marc Jones <marcj303(a)gmail.com>: > > Hello Wolfgang Kamp, > > I'd like you to do a code review. Please visit > > http://review.coreboot.org/542 > > to review the following change. > > Change subject: Inagua: Synchronize AMD/inagua mainboard. > ..................................................................... > > Inagua: Synchronize AMD/inagua mainboard. > > AMD/persimmon mainboard code is derived from AMD/inagua mainbard. > Persimmom update a lot in the last few month, sync these modification to inagua. > > Change-Id: Ia038e5a2b9550fe81bb075f31e30b98354758e9e > Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> > Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> > --- > M src/mainboard/amd/inagua/BiosCallOuts.c > M src/mainboard/amd/inagua/BiosCallOuts.h > M src/mainboard/amd/inagua/Kconfig > M src/mainboard/amd/inagua/Makefile.inc > M src/mainboard/amd/inagua/OptionsIds.h > M src/mainboard/amd/inagua/PlatformGnbPcie.c > D src/mainboard/amd/inagua/acpi/ssdt2.asl > D src/mainboard/amd/inagua/acpi/ssdt3.asl > D src/mainboard/amd/inagua/acpi/ssdt4.asl > D src/mainboard/amd/inagua/acpi/ssdt5.asl > M src/mainboard/amd/inagua/acpi_tables.c > M src/mainboard/amd/inagua/agesawrapper.c > M src/mainboard/amd/inagua/agesawrapper.h > M src/mainboard/amd/inagua/buildOpts.c > M src/mainboard/amd/inagua/devicetree.cb > M src/mainboard/amd/inagua/dimmSpd.c > M src/mainboard/amd/inagua/dsdt.asl > M src/mainboard/amd/inagua/fadt.c > M src/mainboard/amd/inagua/get_bus_conf.c > M src/mainboard/amd/inagua/irq_tables.c > M src/mainboard/amd/inagua/mainboard.c > M src/mainboard/amd/inagua/mptable.c > M src/mainboard/amd/inagua/platform_cfg.h > M src/mainboard/amd/inagua/romstage.c > 24 files changed, 249 insertions(+), 717 deletions(-) > > > git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/542/2 > -- > To view, visit http://review.coreboot.org/542 > To unsubscribe, visit http://review.coreboot.org/settings > > Gerrit-MessageType: newchange > Gerrit-Change-Id: Ia038e5a2b9550fe81bb075f31e30b98354758e9e > Gerrit-PatchSet: 2 > Gerrit-Project: coreboot > Gerrit-Branch: master > Gerrit-Owner: Kerry Sheh <shekairui(a)gmail.com> > Gerrit-Reviewer: Kerry Sheh <shekairui(a)gmail.com> > Gerrit-Reviewer: Wolfgang Kamp <wmkamp(a)datakamp.de> > Gerrit-Reviewer: build bot (Jenkins) > > > > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot -- http://se-eng.com

1 0

New patch to review for coreboot: d9da3f0 Mahogany Fam10 MPtable fix
by Marc Jones 24 Jan '12

24 Jan '12

Marc Jones (marcj303(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/575 -gerrit commit d9da3f007263804da7c941ee5631bffccd7fa76a Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Thu Jan 19 14:28:32 2012 -0700 Mahogany Fam10 MPtable fix Make changes MPtable to match ACPI tables. Change-Id: I387f301370582fcb5e0d348d793333a919d2f373 Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- src/mainboard/amd/mahogany_fam10/mptable.c | 39 +++++++++++++++++++++++----- 1 files changed, 32 insertions(+), 7 deletions(-) diff --git a/src/mainboard/amd/mahogany_fam10/mptable.c b/src/mainboard/amd/mahogany_fam10/mptable.c index 4bf3480..b1a658b 100644 --- a/src/mainboard/amd/mahogany_fam10/mptable.c +++ b/src/mainboard/amd/mahogany_fam10/mptable.c @@ -107,8 +107,30 @@ static void *smp_write_config_table(void *v) #define PCI_INT(bus, dev, fn, pin) #endif + /* changes added to match acpi tables */ + PCI_INT(0x0, 0x02, 0x0, 0x12); + PCI_INT(0x0, 0x03, 0x0, 0x13); + PCI_INT(0x0, 0x04, 0x0, 0x10); + PCI_INT(0x0, 0x09, 0x0, 0x11); + PCI_INT(0x0, 0x0A, 0x0, 0x12); + PCI_INT(0x0, 0x12, 0x2, 0x12); + PCI_INT(0x0, 0x12, 0x3, 0x13); + PCI_INT(0x0, 0x13, 0x2, 0x10); + PCI_INT(0x0, 0x13, 0x2, 0x11); + PCI_INT(0x0, 0x14, 0x1, 0x11); + PCI_INT(0x0, 0x14, 0x3, 0x13); + PCI_INT(0x1, 0x05, 0x2, 0x10); + PCI_INT(0x1, 0x05, 0x3, 0x11); + PCI_INT(0x2, 0x00, 0x0, 0x12); + PCI_INT(0x2, 0x00, 0x1, 0x13); + PCI_INT(0x2, 0x00, 0x2, 0x10); + PCI_INT(0x2, 0x00, 0x3, 0x11); + + /* RS780 PCI to PCI bridge (PCIE port 4) */ + PCI_INT(0x0, 0x09, 0x0, 0x11); + /* usb */ - PCI_INT(0x0, 0x12, 0x0, 0x10); /* USB */ + PCI_INT(0x0, 0x12, 0x0, 0x10); /* USB */ PCI_INT(0x0, 0x12, 0x1, 0x11); PCI_INT(0x0, 0x13, 0x0, 0x12); PCI_INT(0x0, 0x13, 0x1, 0x13); @@ -118,22 +140,25 @@ static void *smp_write_config_table(void *v) PCI_INT(0x0, 0x11, 0x0, 0x16); /* HD Audio: b0:d20:f1:reg63 should be 0. */ - /* PCI_INT(0x0, 0x14, 0x2, 0x12); */ + PCI_INT(0x0, 0x14, 0x2, 0x12); /* on board NIC & Slot PCIE. */ /* PCI_INT(bus_rs780[0x1], 0x5, 0x0, 0x12); */ -/* PCI_INT(bus_rs780[0x1], 0x5, 0x1, 0x13); */ - PCI_INT(bus_rs780[0x2], 0x0, 0x0, 0x12); /* Dev 2, external GFX */ + /* PCI_INT(bus_rs780[0x1], 0x5, 0x1, 0x13); */ + PCI_INT(0x1, 0x5, 0x0, 0x12); /* VGA */ + PCI_INT(0x1, 0x5, 0x1, 0x13); /* Audio */ + /* PCI_INT(bus_rs780[0x2], 0x0, 0x0, 0x12); *//* Dev 2, external GFX */ /* PCI_INT(bus_rs780[0x3], 0x0, 0x0, 0x13); */ - PCI_INT(bus_rs780[0x4], 0x0, 0x0, 0x10); + /* PCI_INT(bus_rs780[0x4], 0x0, 0x0, 0x10); */ /* configuration B doesnt need dev 5,6,7 */ /* * PCI_INT(bus_rs780[0x5], 0x0, 0x0, 0x11); * PCI_INT(bus_rs780[0x6], 0x0, 0x0, 0x12); * PCI_INT(bus_rs780[0x7], 0x0, 0x0, 0x13); */ - PCI_INT(bus_rs780[0x9], 0x0, 0x0, 0x11); - PCI_INT(bus_rs780[0xA], 0x0, 0x0, 0x12); /* NIC */ + /* PCI_INT(bus_rs780[0x9], 0x0, 0x0, 0x11); */ + PCI_INT(0x3, 0x0, 0x0, 0x11); /* NIC */ + /* PCI_INT(bus_rs780[0xA], 0x0, 0x0, 0x12); NIC */ /* PCI slots */ /* PCI_SLOT 0. */

1 0

New patch to review for coreboot: f878bc4 AMD Mahogany Fam10 ACPI table fixes.
by Marc Jones 24 Jan '12

24 Jan '12

Marc Jones (marcj303(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/574 -gerrit commit f878bc41e0e6c46eab928c7bcb1330e22a4f5237 Author: Marc Jones <marcj303(a)gmail.com> Date: Fri Jan 13 14:39:48 2012 -0700 AMD Mahogany Fam10 ACPI table fixes. Fix the ACPI IRQ routing. Also. fix the SSDT generations and TOM2 fixup. Change-Id: I03e6de7bb58440058306c9c9888eb2961748c385 Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- src/mainboard/amd/mahogany_fam10/acpi/routing.asl | 80 +++++++++++------ src/mainboard/amd/mahogany_fam10/acpi_tables.c | 102 +++++++-------------- src/mainboard/amd/mahogany_fam10/dsdt.asl | 32 +++++-- 3 files changed, 113 insertions(+), 101 deletions(-) diff --git a/src/mainboard/amd/mahogany_fam10/acpi/routing.asl b/src/mainboard/amd/mahogany_fam10/acpi/routing.asl index 7b581b4..76a9bfa 100644 --- a/src/mainboard/amd/mahogany_fam10/acpi/routing.asl +++ b/src/mainboard/amd/mahogany_fam10/acpi/routing.asl @@ -31,6 +31,8 @@ Scope(\_SB) { /* NB devices */ /* Bus 0, Dev 0 - RS780 Host Controller */ /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ + Package(){0x0001FFFF, 0, INTC, 0 }, + Package(){0x0001FFFF, 1, INTD, 0 }, /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ Package(){0x0002FFFF, 0, INTC, 0 }, Package(){0x0002FFFF, 1, INTD, 0 }, @@ -57,22 +59,45 @@ Scope(\_SB) { Package(){0x0007FFFF, 1, INTA, 0 }, Package(){0x0007FFFF, 2, INTB, 0 }, Package(){0x0007FFFF, 3, INTC, 0 }, + + Package(){0x0009FFFF, 0, INTB, 0 }, + Package(){0x0009FFFF, 1, INTC, 0 }, + Package(){0x0009FFFF, 2, INTD, 0 }, + Package(){0x0009FFFF, 3, INTA, 0 }, + + Package(){0x000AFFFF, 0, INTC, 0 }, + Package(){0x000AFFFF, 1, INTD, 0 }, + Package(){0x000AFFFF, 2, INTA, 0 }, + Package(){0x000AFFFF, 3, INTB, 0 }, + + Package(){0x000BFFFF, 0, INTD, 0 }, + Package(){0x000BFFFF, 1, INTA, 0 }, + Package(){0x000BFFFF, 2, INTB, 0 }, + Package(){0x000BFFFF, 3, INTC, 0 }, + + Package(){0x000CFFFF, 0, INTA, 0 }, + Package(){0x000CFFFF, 1, INTB, 0 }, + Package(){0x000CFFFF, 2, INTC, 0 }, + Package(){0x000CFFFF, 3, INTD, 0 }, + /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ /* SB devices */ /* Bus 0, Dev 17 - SATA controller #2 */ /* Bus 0, Dev 18 - SATA controller #1 */ - Package(){0x0011FFFF, 0, INTA, 0 }, + Package(){0x0011FFFF, 0, INTG, 0 }, /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5; * EHCI, dev 18, 19 func 2 */ Package(){0x0012FFFF, 0, INTA, 0 }, Package(){0x0012FFFF, 1, INTB, 0 }, Package(){0x0012FFFF, 2, INTC, 0 }, + Package(){0x0012FFFF, 3, INTD, 0 }, Package(){0x0013FFFF, 0, INTC, 0 }, Package(){0x0013FFFF, 1, INTD, 0 }, Package(){0x0013FFFF, 2, INTA, 0 }, + Package(){0x0013FFFF, 3, INTB, 0 }, /* Package(){0x0014FFFF, 1, INTA, 0 }, */ @@ -81,6 +106,12 @@ Scope(\_SB) { Package(){0x0014FFFF, 1, INTB, 0 }, Package(){0x0014FFFF, 2, INTC, 0 }, Package(){0x0014FFFF, 3, INTD, 0 }, + +/* Package(){0x0015FFFF, 0, INTA, 0 }, + Package(){0x0015FFFF, 1, INTB, 0 }, + Package(){0x0015FFFF, 2, INTC, 0 }, + Package(){0x0015FFFF, 3, INTD, 0 }, +*/ }) Name(APR0, Package(){ @@ -129,11 +160,13 @@ Scope(\_SB) { /* Package(){0x0009FFFF, 1, 0, 16 }, */ /* Package(){0x0009FFFF, 2, 0, 17 }, */ /* Package(){0x0009FFFF, 3, 0, 18 }, */ + /* Bus 0, Dev A - PCIe Bridge for network card */ Package(){0x000AFFFF, 0, 0, 18 }, /* Package(){0x000AFFFF, 1, 0, 16 }, */ /* Package(){0x000AFFFF, 2, 0, 17 }, */ /* Package(){0x000AFFFF, 3, 0, 18 }, */ + /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ /* SB devices in APIC mode */ @@ -146,41 +179,34 @@ Scope(\_SB) { Package(){0x0012FFFF, 0, 0, 16 }, Package(){0x0012FFFF, 1, 0, 17 }, Package(){0x0012FFFF, 2, 0, 18 }, + Package(){0x0012FFFF, 3, 0, 19 }, Package(){0x0013FFFF, 0, 0, 18 }, Package(){0x0013FFFF, 1, 0, 19 }, Package(){0x0013FFFF, 2, 0, 16 }, - - /* Package(){0x00140000, 0, 0, 16 }, */ - - /* Package(){0x00130004, 2, 0, 18 }, */ - /* Package(){0x00130005, 3, 0, 19 }, */ + Package(){0x0013FFFF, 3, 0, 17 }, /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */ Package(){0x0014FFFF, 0, 0, 16 }, Package(){0x0014FFFF, 1, 0, 17 }, Package(){0x0014FFFF, 2, 0, 18 }, Package(){0x0014FFFF, 3, 0, 19 }, - /* Package(){0x00140004, 2, 0, 18 }, */ - /* Package(){0x00140004, 3, 0, 19 }, */ - /* Package(){0x00140005, 1, 0, 17 }, */ - /* Package(){0x00140006, 1, 0, 17 }, */ }) Name(PR1, Package(){ /* Internal graphics - RS780 VGA, Bus1, Dev5 */ - Package(){0x0005FFFF, 0, INTA, 0 }, - Package(){0x0005FFFF, 1, INTB, 0 }, - Package(){0x0005FFFF, 2, INTC, 0 }, - Package(){0x0005FFFF, 3, INTD, 0 }, + Package(){0x0005FFFF, 0, INTC, 0 }, + Package(){0x0005FFFF, 1, INTD, 0 }, + Package(){0x0005FFFF, 2, INTA, 0 }, + Package(){0x0005FFFF, 3, INTB, 0 }, }) Name(APR1, Package(){ /* Internal graphics - RS780 VGA, Bus1, Dev5 */ Package(){0x0005FFFF, 0, 0, 18 }, Package(){0x0005FFFF, 1, 0, 19 }, - /* Package(){0x0005FFFF, 2, 0, 20 }, */ - /* Package(){0x0005FFFF, 3, 0, 17 }, */ + Package(){0x0005FFFF, 2, 0, 16 }, + Package(){0x0005FFFF, 3, 0, 17 }, }) Name(PS2, Package(){ @@ -201,10 +227,10 @@ Scope(\_SB) { Name(PS4, Package(){ /* PCIe slot - Hooked to PCIe slot 4 */ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, }) Name(APS4, Package(){ @@ -272,10 +298,10 @@ Scope(\_SB) { Name(APS9, Package(){ /* PCIe slot - Hooked to PCIe slot 9 */ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, + Package(){0x0000FFFF, 0, 0, 19 }, + Package(){0x0000FFFF, 1, 0, 16 }, + Package(){0x0000FFFF, 2, 0, 17 }, + Package(){0x0000FFFF, 3, 0, 18 }, }) Name(PSa, Package(){ /* PCIe slot - Hooked to PCIe slot 10 */ @@ -288,9 +314,9 @@ Scope(\_SB) { Name(APSa, Package(){ /* PCIe slot - Hooked to PCIe slot 10 */ Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, + Package(){0x0000FFFF, 1, 0, 16 }, + Package(){0x0000FFFF, 2, 0, 17 }, + Package(){0x0000FFFF, 3, 0, 18 }, }) Name(PCIB, Package(){ diff --git a/src/mainboard/amd/mahogany_fam10/acpi_tables.c b/src/mainboard/amd/mahogany_fam10/acpi_tables.c index 74f5612..1f7c2f7 100644 --- a/src/mainboard/amd/mahogany_fam10/acpi_tables.c +++ b/src/mainboard/amd/mahogany_fam10/acpi_tables.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Advanced Micro Devices, Inc. + * Copyright (C) 2010-2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -20,6 +20,7 @@ #include <console/console.h> #include <string.h> #include <arch/acpi.h> +#include <arch/acpigen.h> #include <arch/ioapic.h> #include <device/pci.h> #include <device/pci_ids.h> @@ -49,12 +50,33 @@ static void dump_mem(u32 start, u32 end) extern const unsigned char AmlCode[]; extern const unsigned char AmlCode_ssdt[]; -#if CONFIG_ACPI_SSDTX_NUM >= 1 -extern const unsigned char AmlCode_ssdt2[]; -extern const unsigned char AmlCode_ssdt3[]; -extern const unsigned char AmlCode_ssdt4[]; -extern const unsigned char AmlCode_ssdt5[]; -#endif +unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) +{ + int lens; + msr_t msr; + char pscope[] = "\\_SB.PCI0"; + + lens = acpigen_write_scope(pscope); + msr = rdmsr(TOP_MEM); + lens += acpigen_write_name_dword("TOM1", msr.lo); + msr = rdmsr(TOP_MEM2); + /* + * Since XP only implements parts of ACPI 2.0, we can't use a qword + * here. + * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt + * slide 22ff. + * Shift value right by 20 bit to make it fit into 32bit, + * giving us 1MB granularity and a limit of almost 4Exabyte of memory. + */ + lens += acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20); + acpigen_patch_len(lens - 1); + + /* TODO: More HT and other tables need to go into this table generation. + * This should also be moved out to the silicon level if it can. + */ + + return (unsigned long) (acpigen_get_current()); +} unsigned long acpi_fill_mcfg(unsigned long current) { @@ -68,8 +90,8 @@ unsigned long acpi_fill_madt(unsigned long current) current = acpi_create_madt_lapics(current); /* Write SB700 IOAPIC, only one */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2, - IO_APIC_ADDR, 0); + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + CONFIG_MAX_CPUS, IO_APIC_ADDR, 0); current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, 0); @@ -100,11 +122,6 @@ unsigned long write_acpi_tables(unsigned long start) acpi_facs_t *facs; acpi_header_t *dsdt; acpi_header_t *ssdt; -#if CONFIG_ACPI_SSDTX_NUM >= 1 - acpi_header_t *ssdtx; - void *p; - int i; -#endif get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ @@ -186,62 +203,13 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp, slit); /* SSDT */ - current = ( current + 0x0f) & -0x10; - printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); - ssdt = (acpi_header_t *)current; - memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t)); + current = ( current + 0x0f) & -0x10; + printk(BIOS_DEBUG, "ACPI: * coreboot PSTATE/TOM SSDT at %lx\n", current); + ssdt = (acpi_header_t *) current; + acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); current += ssdt->length; - memcpy(ssdt, &AmlCode_ssdt, ssdt->length); - //Here you need to set value in pci1234, sblk and sbdn in get_bus_conf.c - update_ssdt((void*)ssdt); - /* recalculate checksum */ - ssdt->checksum = 0; - ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length); acpi_add_table(rsdp,ssdt); - printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); - current = acpi_add_ssdt_pstates(rsdp, current); - -#if CONFIG_ACPI_SSDTX_NUM >= 1 - - /* same htio, but different position? We may have to copy, - change HCIN, and recalculate the checknum and add_table */ - - for(i=1;i<sysconf.hc_possible_num;i++) { // 0: is hc sblink - if((sysconf.pci1234[i] & 1) != 1 ) continue; - u8 c; - if (i < 7) { - c = (u8) ('4' + i - 1); - } else { - c = (u8) ('A' + i - 1 - 6); - } - current = ( current + 0x07) & -0x08; - printk(BIOS_DEBUG, "ACPI: * SSDT for PCI%c at %lx\n", c, current); //pci0 and pci1 are in dsdt - ssdtx = (acpi_header_t *)current; - switch (sysconf.hcid[i]) { - case 1: - p = &AmlCode_ssdt2; - break; - case 2: - p = &AmlCode_ssdt3; - break; - case 3: /* 8131 */ - p = &AmlCode_ssdt4; - break; - default: - /* HTX no io apic */ - p = &AmlCode_ssdt5; - break; - } - memcpy(ssdtx, p, sizeof(acpi_header_t)); - current += ssdtx->length; - memcpy(ssdtx, p, ssdtx->length); - update_ssdtx((void *)ssdtx, i); - ssdtx->checksum = 0; - ssdtx->checksum = acpi_checksum((u8 *)ssdtx, ssdtx->length); - acpi_add_table(rsdp, ssdtx); - } -#endif #if DUMP_ACPI_TABLES == 1 printk(BIOS_DEBUG, "rsdp\n"); diff --git a/src/mainboard/amd/mahogany_fam10/dsdt.asl b/src/mainboard/amd/mahogany_fam10/dsdt.asl index 692699d..8bba547 100644 --- a/src/mainboard/amd/mahogany_fam10/dsdt.asl +++ b/src/mainboard/amd/mahogany_fam10/dsdt.asl @@ -36,7 +36,7 @@ DefinitionBlock ( Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ Name(PBLN, 0x0) /* Length of BIOS area */ - Name(PCBA, 0xE0000000) /* Base address of PCIe config space */ + Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ Name(HPBA, 0xFED00000) /* Base address of HPET table */ Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ @@ -1168,7 +1168,7 @@ DefinitionBlock ( /* Note: Only need HID on Primary Bus */ Device(PCI0) { External (TOM1) - External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */ + External (TOM2) Name(_HID, EISAID("PNP0A03")) Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ Method(_BBN, 0) { /* Bus number = 0 */ @@ -1421,7 +1421,7 @@ DefinitionBlock ( IRQNoFlags(){13} }) } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ - +#if 0 /* defined by HPET table? */ Device(HPTM) { Name(_HID,EISAID("PNP0103")) Name(CRS,ResourceTemplate() { @@ -1436,6 +1436,7 @@ DefinitionBlock ( Return(CRS) } } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ +#endif } /* end LIBR */ Device(HPBR) { @@ -1546,6 +1547,7 @@ DefinitionBlock ( Memory32Fixed(READWRITE, 0, 0xA0000, BSMM) Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */ +#if 0 Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */ Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */ @@ -1585,12 +1587,14 @@ DefinitionBlock ( ,, PEBM ) - +#endif + /* memory space for PCI BARs below 4GB */ + Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) }) /* End Name(_SB.PCI0.CRES) */ Method(_CRS, 0) { /* DBGO("\\_SB\\PCI0\\_CRS\n") */ - +#if 0 CreateDWordField(CRES, ^EMM1._BAS, EM1B) CreateDWordField(CRES, ^EMM1._LEN, EM1L) CreateDWordField(CRES, ^DMLO._BAS, DMLB) @@ -1614,8 +1618,7 @@ DefinitionBlock ( /* * If(LNotEqual(TOM2, 0x00000000)){ * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2 - * ShiftLeft(TOM2, 20, Local0) - * Subtract(Local0, 0x100000000, DMHL) + * Subtract(TOM2, 0x100000000, DMHL) * } */ @@ -1628,6 +1631,21 @@ DefinitionBlock ( ShiftLeft(PBAD,16,EBMB) /* Reserve the "BIOS" space */ Store(PBLN,EBML) } +#endif + CreateDWordField(CRES, ^MMIO._BAS, MM1B) + CreateDWordField(CRES, ^MMIO._LEN, MM1L) + /* + * Declare memory between TOM1 and 4GB as available + * for PCI MMIO. + * Use ShiftLeft to avoid 64bit constant (for XP). + * This will work even if the OS does 32bit arithmetic, as + * 32bit (0x00000000 - TOM1) will wrap and give the same + * result as 64bit (0x100000000 - TOM1). + */ + Store(TOM1, MM1B) + ShiftLeft(0x10000000, 4, Local0) + Subtract(Local0, TOM1, Local0) + Store(Local0, MM1L) Return(CRES) /* note to change the Name buffer */ } /* end of Method(_SB.PCI0._CRS) */

1 0

← Newer
1
...
7
8
9
10
11
12
13
...
31
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot January 2012