January 2012 - coreboot - mail.coreboot.org

Patch merged into coreboot/master: 715643f X60/T60: fix default baudrate
by gerrit＠coreboot.org Jan. 31, 2012

Jan. 31, 2012

the following patch was just integrated into master: commit 715643ffb2595fb7efb8f6d59fff2dd9634a9a96 Author: Sven Schnelle <svens(a)stackframe.org> Date: Tue Jan 31 12:33:01 2012 +0100 X60/T60: fix default baudrate Value required to get 115200 is actually 0, not 5. Change-Id: Id1385822bf2213c035c4f378a72168ed6676ad03 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> Build-Tested: build bot (Jenkins) at Tue Jan 31 12:51:49 2012, giving +1 Reviewed-By: Sven Schnelle <svens(a)stackframe.org> at Tue Jan 31 12:52:18 2012, giving +2 See http://review.coreboot.org/592 for details. -gerrit

1 0

Patch set updated for coreboot: b25218e H8QGI: Increase xip size of supermicro/h8qgi from 512K to 1M Bytes.
by Kerry Sheh Jan. 31, 2012

Jan. 31, 2012

Kerry Sheh (shekairui(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/568 -gerrit commit b25218ecfccf73157856861ab0713f7860d5c476 Author: Kerry Sheh <shekairui(a)gmail.com> Date: Tue Jan 31 20:42:35 2012 +0800 H8QGI: Increase xip size of supermicro/h8qgi from 512K to 1M Bytes. For mainboard using AMD AGESA framework, lots of AGESA code will be compiled into romstage, so romstage becomes larger, especially for mainboard support 2 or more processor families. H8QGI support both f10 and f15 CPUs, 512K default xip size is not enough, so increase to 1M Bytes. Change-Id: I1fb1aaad68aed8b41253a02cc0bc151c239b0dbe Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> --- src/mainboard/supermicro/h8qgi/Kconfig | 14 ++++++++++++++ 1 files changed, 14 insertions(+), 0 deletions(-) diff --git a/src/mainboard/supermicro/h8qgi/Kconfig b/src/mainboard/supermicro/h8qgi/Kconfig index e900ea8..201df45 100644 --- a/src/mainboard/supermicro/h8qgi/Kconfig +++ b/src/mainboard/supermicro/h8qgi/Kconfig @@ -123,5 +123,19 @@ config VGA_BIOS_ID depends on VGA_BIOS default "102b,0532" +config XIP_ROM_BASE + hex + default 0xfff00000 + +config XIP_ROM_SIZE + hex + default 0x100000 + help + Overwride the default write through caching size as 1M Bytes. + On some AMD paltform, one socket support 2 kinds of processor family, + Compiling 2 cpu families agesa code will increase the romstage size. + In order to execute romstage in place on the flash rom, + more space is required to be set as write through caching. + endif # BOARD_SUPERMICRO_H8QGI

1 0

Patch set updated for coreboot: 4f1f36c HWM: Nuvoton W83795G/ADG HWM support
by Kerry Sheh Jan. 31, 2012

Jan. 31, 2012

Kerry Sheh (shekairui(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/569 -gerrit commit 4f1f36c488d570171c9bb8299ef8e601c2994bc8 Author: Kerry Sheh <shekairui(a)gmail.com> Date: Tue Jan 31 20:42:37 2012 +0800 HWM: Nuvoton W83795G/ADG HWM support Supermicro H8QGI-F 1 Unit Chassis contain 9 system Fans, they are controled by a separate W83795G Hardware Monitor chip. This patch adds Nuvoton W83795G/ADG HWM support. Change-Id: I8756f5ed02dc2fa0884cde36e51451fd8aacee27 Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> --- src/mainboard/supermicro/h8qgi/Makefile.inc | 1 + src/mainboard/supermicro/h8qgi/romstage.c | 9 + src/mainboard/supermicro/h8qgi/w83795.c | 236 +++++++++++++++++++++++++++ src/mainboard/supermicro/h8qgi/w83795.h | 75 +++++++++ 4 files changed, 321 insertions(+), 0 deletions(-) diff --git a/src/mainboard/supermicro/h8qgi/Makefile.inc b/src/mainboard/supermicro/h8qgi/Makefile.inc index 82264a4..ef81caf 100644 --- a/src/mainboard/supermicro/h8qgi/Makefile.inc +++ b/src/mainboard/supermicro/h8qgi/Makefile.inc @@ -17,6 +17,7 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # +romstage-y += w83795.c romstage-$(CONFIG_NORTHBRIDGE_AMD_CIMX_RD890) += rd890_cfg.c romstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += sb700_cfg.c romstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += reset.c diff --git a/src/mainboard/supermicro/h8qgi/romstage.c b/src/mainboard/supermicro/h8qgi/romstage.c index 119593e..4d48474 100644 --- a/src/mainboard/supermicro/h8qgi/romstage.c +++ b/src/mainboard/supermicro/h8qgi/romstage.c @@ -33,6 +33,7 @@ #include <sb_cimx.h> #include "superio/nuvoton/wpcm450/wpcm450.h" #include "superio/winbond/w83627dhg/w83627dhg.h" +#include "w83795.h" extern void disable_cache_as_ram(void); /* cache_as_ram.inc */ @@ -119,6 +120,14 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } post_code(0x3C); + /* W83627DHG pin89,90 function select is RSTOUT3#, RSTOUT2# by default. + * In order to access W83795G/ADG HWM using I2C protocol, + * we select function to SDA, SCL function (or GP33, GP32 function). + */ + w83627dhg_enable_i2c(PNP_DEV(0x2E, W83627DHG_SPI)); + w83795_init(THERMAL_CRUISE_MODE, DTS_SRC_AMD_SBTSI); + w83627dhg_enable_serial(PNP_DEV(0x2E, W83627DHG_SP1), CONFIG_TTYS0_BASE); + nb_Ht_Init(); post_code(0x3D); /* Reset for HT, FIDVID, PLL and ucode patch(errata) changes to take affect. */ diff --git a/src/mainboard/supermicro/h8qgi/w83795.c b/src/mainboard/supermicro/h8qgi/w83795.c new file mode 100644 index 0000000..22828db --- /dev/null +++ b/src/mainboard/supermicro/h8qgi/w83795.c @@ -0,0 +1,236 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <console/console.h> +#include "southbridge/amd/cimx/sb700/smbus.h" /*SMBUS_IO_BASE*/ +#include "w83795.h" + +static u32 w83795_set_bank(u8 bank) +{ + return do_smbus_write_byte(SMBUS_IO_BASE, W83795_DEV, W83795_REG_BANKSEL, bank); +} + +static u8 w83795_read(u16 reg) +{ + u32 ret; + + ret = w83795_set_bank(reg >> 8); + if (ret < 0) { + printk(BIOS_DEBUG, "read faild to set bank %x\n", reg >> 8); + return -1; + } + + ret = do_smbus_read_byte(SMBUS_IO_BASE, W83795_DEV, reg & 0xff); + return ret; +} + +static u8 w83795_write(u16 reg, u8 value) +{ + u32 err; + + err = w83795_set_bank(reg >> 8); + if (err < 0) { + printk(BIOS_DEBUG, "write faild to set bank %x\n", reg >> 8); + return -1; + } + + err = do_smbus_write_byte(SMBUS_IO_BASE, W83795_DEV, reg & 0xff, value); + return err; +} + +#if 0 +static void w83795_set_speed(void) +{ + +} + +static void w83795_set_ttti(void)//KR it works +{ + u32 i; + for (i = 0; i < 6; i++) { + //w83795_write(W83795_REG_TTTI(i), 0xa);//10 degree, default 40 + //w83795_write(W83795_REG_CTFS(i), 0x20);//32 degree, default 80 + } +} +#endif + +/* + * Enable Digital Temperature Sensor + */ +static void w83795_dts_enable(u8 dts_src) +{ + u8 val; + + /* DIS */ + val = w83795_read(W83795_REG_DTSC); + val |= (dts_src & 0x01); + w83795_write(W83795_REG_DTSC, val); + + /* DTSE */ + val = w83795_read(W83795_REG_DTSE); + val |= 0xFF; + w83795_write(W83795_REG_DTSE, val); + + /* store bank3 regs first before enable DTS */ + + /* + * TD/TR1-4 termal diode by default + * 0x00 Disable + * 0x01 thermistors on motherboard + * 0x10 different mode voltage + * 0x11 CPU internal thermal diode output + * + * TR5-6 thermistors by default TRn + */ + val = 0x55; /* thermal diode */ + w83795_write(W83795_REG_TEMP_CTRL2, val); + + /* Enable Digital Temperature Sensor */ + val = w83795_read(W83795_REG_TEMP_CTRL1); + val |= W83795_REG_TEMP_CTRL1_EN_DTS; /* EN_DTS */ + w83795_write(W83795_REG_TEMP_CTRL1, val); +} + +static void w83795_set_tfmr(w83795_fan_mode_t mode) +{ + u8 val; + u8 i; + + if ((mode == SMART_FAN_MODE) || (mode == THERMAL_CRUISE_MODE)) { + val = 0xFF; + } else { + val = 0x00; + } + + for (i = 0; i < 6; i++) + w83795_write(W83795_REG_TFMR(i), val); +} + +static u32 w83795_set_fan_mode(w83795_fan_mode_t mode) +{ + if (mode == SPEED_CRUISE_MODE) { + w83795_write(W83795_REG_FCMS1, 0xFF); + printk(BIOS_INFO, "W83795G/ADG work in Speed Cruise Mode\n"); + } else { + w83795_write(W83795_REG_FCMS1, 0x00); + if (mode == THERMAL_CRUISE_MODE) { + w83795_write(W83795_REG_FCMS2, 0x00); + printk(BIOS_INFO, "W83795G/ADG work in Thermal Cruise Mode\n"); + } else if (mode == SMART_FAN_MODE) { + w83795_write(W83795_REG_FCMS2, 0x3F); + printk(BIOS_INFO, "W83795G/ADG work in Smart Fan Mode\n"); + } else { + printk(BIOS_INFO, "W83795G/ADG work in Manual Mode\n"); + return -1; + } + } + + return 0; +} + +static void w83795_set_tss(void) +{ + u8 val; + + val = 0x00; + w83795_write(W83795_REG_TSS(0), val); /* Temp1, 2 */ + w83795_write(W83795_REG_TSS(1), val); /* Temp3, 4 */ + w83795_write(W83795_REG_TSS(2), val); /* Temp5, 6 */ +} + +static void w83795_set_fan(w83795_fan_mode_t mode) +{ + u8 i; + + /* select temperature sensor (TSS)*/ + w83795_set_tss(); + + /* select Temperature to Fan mapping Relationships (TFMR)*/ + w83795_set_tfmr(mode); + + /* set fan output controlled mode (FCMS)*/ + w83795_set_fan_mode(mode); + + /* Set Critical Temperature to Full Speed all fan (CTFS) */ + for (i = 0; i < 6; i++) { + w83795_write(W83795_REG_CTFS(i), 0x50); /* default 80 celsius degree */ + } + + if (mode == THERMAL_CRUISE_MODE) { + /* Set Target Temperature of Temperature Inputs (TTTI) */ + for (i = 0; i < 6; i++) { + w83795_write(W83795_REG_TTTI(i), 0x28); /* default 40 celsius degree */ + } + } else if (mode == SMART_FAN_MODE) { + /* Set the Relative Register-at SMART FAN IV Control Mode Table */ + //SFIV TODO + } + + /* Set Hystersis of Temperature (HT) */ +} + +void w83795_init(w83795_fan_mode_t mode, u8 dts_src) +{ + u8 i; + u8 val; + + if (do_smbus_read_byte(SMBUS_IO_BASE, W83795_DEV, 0x00) < 0) { + printk(BIOS_INFO, "W83795G/ADG Nuvoton H/W Monitor not found\n"); + return; + } + val = w83795_read(W83795_REG_CONFIG); + if ((val & W83795_REG_CONFIG_CONFIG48) == 0) + printk(BIOS_INFO, "Found 64 pin W83795G Nuvoton H/W Monitor\n"); + else if ((val & W83795_REG_CONFIG_CONFIG48) == 1) + printk(BIOS_INFO, "Found 48 pin W83795ADG Nuvoton H/W Monitor\n"); + + /* Reset */ + val |= W83795_REG_CONFIG_INIT; + w83795_write(W83795_REG_CONFIG, val); + + /* Fan monitoring setting */ + val = 0xFF; /* FAN1-FAN8 */ + w83795_write(W83795_REG_FANIN_CTRL1, val); + val = 0x3F; /* FAN9-FAN14 */ + w83795_write(W83795_REG_FANIN_CTRL2, val); + + /* enable monitoring operations */ + val = w83795_read(W83795_REG_CONFIG); + val |= W83795_REG_CONFIG_START; + w83795_write(W83795_REG_CONFIG, val); + + w83795_dts_enable(dts_src); + w83795_set_fan(mode); + + printk(BIOS_INFO, "Fan CTFS(celsius) TTTI(celsius)\n"); + for (i = 0; i < 6; i++) { + val = w83795_read(W83795_REG_CTFS(i)); + printk(BIOS_INFO, " %x %d", i, val); + val = w83795_read(W83795_REG_TTTI(i)); + printk(BIOS_INFO, " %d\n", val); + } + + /* Temperature ReadOut */ + for (i = 0; i < 9; i++) { + val = w83795_read(W83795_REG_DTS(i)); + printk(BIOS_DEBUG, "DTS%x ReadOut=%x \n", i, val); + } +} + diff --git a/src/mainboard/supermicro/h8qgi/w83795.h b/src/mainboard/supermicro/h8qgi/w83795.h new file mode 100644 index 0000000..abc4d62 --- /dev/null +++ b/src/mainboard/supermicro/h8qgi/w83795.h @@ -0,0 +1,75 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _W83795_H_ +#define _W83795_H_ + +#define W83795_DEV 0x2F /* Host I2c Addr (strap to addr1 addr0 1 1, 0x5E) */ + +#define W83795_REG_I2C_ADDR 0xFC +#define W83795_REG_BANKSEL 0x00 +#define W83795_REG_CONFIG 0x01 +#define W83795_REG_CONFIG_START 0x01 +#define W83795_REG_CONFIG_CONFIG48 0x04 +#define W83795_REG_CONFIG_INIT 0x80 + +#define W83795_REG_TEMP_CTRL1 0x04 /* Temperature Monitoring Control Register */ +#define W83795_REG_TEMP_CTRL2 0x05 /* Temperature Monitoring Control Register */ +#define W83795_REG_FANIN_CTRL1 0x06 +#define W83795_REG_FANIN_CTRL2 0x07 +#define W83795_REG_TEMP_CTRL1_EN_DTS 0x20 /* Enable DTS (Digital Temperature Sensor) interface from INTEL PECI or AMD SB-TSI. */ +#define DTS_SRC_INTEL_PECI (0 << 0) +#define DTS_SRC_AMD_SBTSI (1 << 0) + +#define W83795_REG_TSS(n) (0x209 + (n)) /* Temperature Source Selection Register */ +#define W83795_REG_TTTI(n) (0x260 + (n)) /* tarrget temperature W83795G/ADG will try to tune the fan output to keep */ +#define W83795_REG_CTFS(n) (0x268 + (n)) /* Critical Temperature to Full Speed all fan */ +#define W83795_REG_HT(n) (0x270 + (n)) /* Hystersis of Temperature */ +#define W83795_REG_DTSC 0x301 /* Digital Temperature Sensor Configuration */ + +#define W83795_REG_DTSE 0x302 /* Digital Temperature Sensor Enable */ +#define W83795_REG_DTS(n) (0x26 + (n)) +#define W83795_REG_VRLSB 0x3C + +#define W83795_TEMP_REG_TR1 0x21 +#define W83795_TEMP_REG_TR2 0x22 +#define W83795_TEMP_REG_TR3 0x23 +#define W83795_TEMP_REG_TR4 0x24 +#define W83795_TEMP_REG_TR5 0x1F +#define W83795_TEMP_REG_TR6 0x20 + +#define W83795_REG_FCMS1 0x201 +#define W83795_REG_FCMS2 0x208 +#define W83795_REG_TFMR(n) (0x202 + (n)) /*temperature to fam mappig*/ +#define W83795_REG_DFSP 0x20C + +#define W83795_REG_FTSH(n) (0x240 + (n) * 2) +#define W83795_REG_FTSL(n) (0x241 + (n) * 2) +#define W83795_REG_TFTS 0x250 + +typedef enum w83795_fan_mode { + SPEED_CRUISE_MODE, ///< Fan Speed Cruise mode keeps the fan speed in a specified range + THERMAL_CRUISE_MODE, ///< Thermal Cruise mode is an algorithm to control the fan speed to keep the temperature source around the TTTI + SMART_FAN_MODE, ///< Smart Fan mode offers 6 slopes to control the fan speed + MANUAL_MODE, ///< control manually +} w83795_fan_mode_t; + +void w83795_init(w83795_fan_mode_t mode, u8 dts_src); + +#endif

1 0

Patch set updated for coreboot: b0e96d6 RD890: AMD RD890/SR56X0 CIMX wrapper
by Kerry Sheh Jan. 31, 2012

Jan. 31, 2012

Kerry Sheh (shekairui(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/559 -gerrit commit b0e96d64eaf3a7efaf11c23b6c915ad3ed118fd8 Author: Kerry Sheh <shekairui(a)gmail.com> Date: Tue Jan 31 20:42:12 2012 +0800 RD890: AMD RD890/SR56X0 CIMX wrapper Support AMD RD890 CIMX support AMD RD890TV, RX780, RD780, SR56x0, RD890 and 990FX chipsets. Change-Id: I39dc5fc316fbb465808bac48a13a49b7d867f04f Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> --- src/northbridge/amd/Kconfig | 1 + src/northbridge/amd/Makefile.inc | 1 + src/northbridge/amd/cimx/Kconfig | 24 ++ src/northbridge/amd/cimx/Makefile.inc | 20 ++ src/northbridge/amd/cimx/rd890/Kconfig | 33 +++ src/northbridge/amd/cimx/rd890/Makefile.inc | 26 ++ src/northbridge/amd/cimx/rd890/NbPlatform.h | 147 ++++++++++ src/northbridge/amd/cimx/rd890/amd.h | 385 +++++++++++++++++++++++++++ src/northbridge/amd/cimx/rd890/cbtypes.h | 71 +++++ src/northbridge/amd/cimx/rd890/chip.h | 38 +++ src/northbridge/amd/cimx/rd890/early.c | 113 ++++++++ src/northbridge/amd/cimx/rd890/late.c | 269 +++++++++++++++++++ src/northbridge/amd/cimx/rd890/nb_cimx.h | 44 +++ 13 files changed, 1172 insertions(+), 0 deletions(-) diff --git a/src/northbridge/amd/Kconfig b/src/northbridge/amd/Kconfig index 4a120ca..33e19c2 100644 --- a/src/northbridge/amd/Kconfig +++ b/src/northbridge/amd/Kconfig @@ -4,6 +4,7 @@ source src/northbridge/amd/gx2/Kconfig source src/northbridge/amd/amdfam10/Kconfig source src/northbridge/amd/lx/Kconfig source src/northbridge/amd/agesa/Kconfig +source src/northbridge/amd/cimx/Kconfig menu "HyperTransport setup" #could be implemented for K8 (NORTHBRIDGE_AMD_AMDK8) depends on (NORTHBRIDGE_AMD_AMDFAM10) && EXPERT diff --git a/src/northbridge/amd/Makefile.inc b/src/northbridge/amd/Makefile.inc index bf96b80..c438473 100644 --- a/src/northbridge/amd/Makefile.inc +++ b/src/northbridge/amd/Makefile.inc @@ -5,3 +5,4 @@ subdirs-$(CONFIG_NORTHBRIDGE_AMD_GX2) += gx2 subdirs-$(CONFIG_NORTHBRIDGE_AMD_LX) += lx subdirs-$(CONFIG_AMD_AGESA) += agesa +subdirs-$(CONFIG_AMD_NB_CIMX) += cimx diff --git a/src/northbridge/amd/cimx/Kconfig b/src/northbridge/amd/cimx/Kconfig new file mode 100644 index 0000000..6751bd4 --- /dev/null +++ b/src/northbridge/amd/cimx/Kconfig @@ -0,0 +1,24 @@ +# +# This file is part of the coreboot project. +# +#Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +config AMD_NB_CIMX + bool + default n + +source src/northbridge/amd/cimx/rd890/Kconfig diff --git a/src/northbridge/amd/cimx/Makefile.inc b/src/northbridge/amd/cimx/Makefile.inc new file mode 100644 index 0000000..80844c8 --- /dev/null +++ b/src/northbridge/amd/cimx/Makefile.inc @@ -0,0 +1,20 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +subdirs-$(CONFIG_NORTHBRIDGE_AMD_CIMX_RD890) += rd890 diff --git a/src/northbridge/amd/cimx/rd890/Kconfig b/src/northbridge/amd/cimx/rd890/Kconfig new file mode 100644 index 0000000..6731b60 --- /dev/null +++ b/src/northbridge/amd/cimx/rd890/Kconfig @@ -0,0 +1,33 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +config NORTHBRIDGE_AMD_CIMX_RD890 + bool + default n + select AMD_NB_CIMX + +config REDIRECT_NBCIMX_TRACE_TO_SERIAL + bool "Redirect AMD Northbridge CIMX Trace to serial console" + default n + depends on NORTHBRIDGE_AMD_CIMX_RD890 + help + This Option allows you to redirect the AMD Northbridge CIMX + Trace debug information to the serial console. + + Warning: Only enable this option when debuging or tracing AMD CIMX code. diff --git a/src/northbridge/amd/cimx/rd890/Makefile.inc b/src/northbridge/amd/cimx/rd890/Makefile.inc new file mode 100644 index 0000000..c3a5084 --- /dev/null +++ b/src/northbridge/amd/cimx/rd890/Makefile.inc @@ -0,0 +1,26 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +subdirs-$(CONFIG_NORTHBRIDGE_AMD_CIMX_RD890) += ../../../../../src/vendorcode/amd/cimx/rd890 + +# RD890 Platform Files +romstage-y += early.c + +ramstage-y += late.c + diff --git a/src/northbridge/amd/cimx/rd890/NbPlatform.h b/src/northbridge/amd/cimx/rd890/NbPlatform.h new file mode 100644 index 0000000..824057a --- /dev/null +++ b/src/northbridge/amd/cimx/rd890/NbPlatform.h @@ -0,0 +1,147 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _NB_PLATFORM_H_ +#define _NB_PLATFORM_H_ + +#define SERIAL_OUT_SUPPORT //enable serial output +#define CIMX_DEBUG + +#ifdef CIMX_DEBUG +#define CIMX_TRACE_SUPPORT +#define CIMX_ASSERT_SUPPORT +#endif + +#ifdef CIMX_TRACE_SUPPORT + #define CIMX_INIT_TRACE(Arguments) + #if CONFIG_REDIRECT_NBCIMX_TRACE_TO_SERIAL + #define TRACE_DATA(Ptr, Level) BIOS_DEBUG //always enable + #define CIMX_TRACE(Argument) do {do_printk Argument;} while (0) + #else + #define TRACE_DATA(Ptr, Level) + #define CIMX_TRACE(Argument) + #endif +#else + #define CIMX_TRACE(Argument) + #define CIMX_INIT_TRACE(Arguments) +#endif + +#ifdef CIMX_ASSERT_SUPPORT + #ifdef ASSERT + #undef ASSERT + #define ASSERT CIMX_ASSERT + #endif + #ifdef CIMX_TRACE_SUPPORT + #define CIMX_ASSERT(x) if(!(x)) {\ + LibAmdTraceDebug (CIMX_TRACE_ALL, (CHAR8 *)"ASSERT !!! "__FILE__" - line %d\n", __LINE__); \ + /*__asm {jmp $}; */\ + } + //#define IDS_HDT_CONSOLE(s, args...) do_printk(BIOS_DEBUG, s, ##args) + #else + #define CIMX_ASSERT(x) if(!(x)) {\ + /*__asm {jmp $}; */\ + } + #endif +#else + #define CIMX_ASSERT(x) +#endif + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +//#define STALL(Ptr, TimeUs, Flag) LibAmdSbStall(TimeUs) +#define STALL(Ptr, TimeUs, Flag) LibAmdSbStall(TimeUs, Ptr) + +#ifdef B2_IMAGE +#define REPORT_EVENT(Class, Info, Param1, Param2, Param3, Param4, CfgPtr) LibNbEventLog(Class, Info, Param1, Param2, Param3, Param4, CfgPtr) +#else +#define REPORT_EVENT(Class, Info, Param1, Param2, Param3, Param4, CfgPtr) +#endif + + + +// CIMX configuration parameters +//#define CIMX_B2_IMAGE_BASE_ADDRESS 0xFFF40000 +/** + * PCIEX_BASE_ADDRESS - Define PCIE base address + * + * @param[Option] MOVE_PCIEBAR_TO_F0000000 Set PCIe base address to 0xF7000000 + */ +#ifdef MOVE_PCIEBAR_TO_F0000000 +#define PCIEX_BASE_ADDRESS 0xF7000000 +#else +#define PCIEX_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS +#endif + + + +#define CIMX_S3_SAVE 1 +#include "cbtypes.h" +#include <console/console.h> + +#include "amd.h" //cimx typedef +#include <amdlib.h> +#include "amdAcpiLib.h" +#include "amdAcpiMadt.h" +#include "amdAcpiIvrs.h" +#include "amdSbLib.h" +#include "nbPcie.h" + +//must put before the nbType.h +#include "platform_cfg.h" /*platform dependented configuration */ +#include "nbType.h" + +#include "nbLib.h" +#include "nbDef.h" +#include "nbInit.h" +#include "nbHtInit.h" +#include "nbIommu.h" +#include "nbEventLog.h" +#include "nbRegisters.h" +#include "nbPcieAspm.h" +#include "nbPcieLinkWidth.h" +#include "nbPcieHotplug.h" +#include "nbPciePortRemap.h" +#include "nbPcieWorkarounds.h" +#include "nbPcieCplBuffers.h" +#include "nbPciePllControl.h" +#include "nbMiscInit.h" +#include "nbIoApic.h" +#include "nbPcieSb.h" +#include "nbRecovery.h" +#include "nbMaskedMemoryInit.h" + + +#define FIX_PTR_ADDR(x, y) x + +#define TRACE_ALWAYS 0xffffffff + +#define AmdNbDispatcher NULL + +#define CIMX_TRACE_ALL 0xFFFFFFFF +#define CIMX_NBPOR_TRACE 0xFFFFFFFF +#define CIMX_NBHT_TRACE 0xFFFFFFFF +#define CIMX_NBPCIE_TRACE 0xFFFFFFFF +#define CIMX_NB_TRACE 0xFFFFFFFF +#define CIMX_NBPCIE_MISC 0xFFFFFFFF + +#endif + diff --git a/src/northbridge/amd/cimx/rd890/amd.h b/src/northbridge/amd/cimx/rd890/amd.h new file mode 100644 index 0000000..d99f90f --- /dev/null +++ b/src/northbridge/amd/cimx/rd890/amd.h @@ -0,0 +1,385 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _AMD_H_ +#define _AMD_H_ + +#include "cbtypes.h" + + +#define VOLATILE volatile +#define CALLCONV +#define ROMDATA +#define CIMXAPI EFIAPI + +// +// +// AGESA Types and Definitions +// +// +#ifndef NULL + #define NULL 0 +#endif + + +#define LAST_ENTRY 0xFFFFFFFF +#define IOCF8 0xCF8 +#define IOCFC 0xCFC +#define IN +#define OUT +#define IMAGE_SIGNATURE 'DMA$' + +typedef UINTN AGESA_STATUS; + + +#define AGESA_SUCCESS ((AGESA_STATUS) 0x0) +#define AGESA_ALERT ((AGESA_STATUS) 0x40000000) +#define AGESA_WARNING ((AGESA_STATUS) 0x40000001) +#define AGESA_UNSUPPORTED ((AGESA_STATUS) 0x80000003) +#define AGESA_ERROR ((AGESA_STATUS) 0xC0000001) +#define AGESA_CRITICAL ((AGESA_STATUS) 0xC0000002) +#define AGESA_FATAL ((AGESA_STATUS) 0xC0000003) + +typedef AGESA_STATUS (*CALLOUT_ENTRY) (UINT32 Param1, UINTN Param2, VOID* ConfigPtr); +typedef AGESA_STATUS (*IMAGE_ENTRY) (IN OUT VOID* ConfigPtr); +typedef AGESA_STATUS (*MODULE_ENTRY) (IN OUT VOID* ConfigPtr); + +///This allocation type is used by the AmdCreateStruct entry point +typedef enum { + PreMemHeap = 0, ///< Create heap in cache. + PostMemDram, ///< Create heap in memory. + ByHost ///< Create heap by Host. +} ALLOCATION_METHOD; + +/// These width descriptors are used by the library function, and others, to specify the data size +typedef enum ACCESS_WIDTH { + AccessWidth8 = 1, ///< Access width is 8 bits. + AccessWidth16, ///< Access width is 16 bits. + AccessWidth32, ///< Access width is 32 bits. + AccessWidth64, ///< Access width is 64 bits. + + AccessS3SaveWidth8 = 0x81, ///< Save 8 bits data. + AccessS3SaveWidth16, ///< Save 16 bits data. + AccessS3SaveWidth32, ///< Save 32 bits data. + AccessS3SaveWidth64, ///< Save 64 bits data. +} ACCESS_WIDTH; + + +// AGESA Structures +/// The standard header AMD NB UEFI drivers +typedef struct _AMD_CONFIG_PARAMS { + VOID **PeiServices; ///< Pointer to PEI service table + VOID *StallPpi; ///< Pointer to Stall PPI +// UINT32 Func; + VOID *PcieBasePtr; ///< TBD + CALLOUT_ENTRY CalloutPtr; ///<pointer to local driver callback function + CALLOUT_ENTRY InterfaceCalloutPtr; ///<pointer to external interface driver callback function +} AMD_CONFIG_PARAMS; + + +/// AGESA Binary module header structure +typedef struct _AMD_IMAGE_HEADER { + IN UINT32 Signature; ///< Binary Signature + IN CHAR8 CreatorID[8]; ///< 8 characters ID + IN CHAR8 Version[12]; ///< 12 characters version + IN UINT32 ModuleInfoOffset; ///< Offset of module + IN UINT32 EntryPointAddress; ///< Entry address + IN UINT32 ImageBase; ///< Image base + IN UINT32 RelocTableOffset; ///< Relocate Table offset + IN UINT32 ImageSize; ///< Size + IN UINT16 Checksum; ///< Checksum + IN UINT8 ImageType; ///< Type + IN UINT8 V_Reserved; ///< Reserved +} AMD_IMAGE_HEADER; + + +/// AGESA Binary module header structure +typedef struct _AMD_MODULE_HEADER { + IN UINT32 ModuleHeaderSignature; ///< Module signature + IN CHAR8 ModuleIdentifier[8]; ///< 8 characters ID + IN CHAR8 ModuleVersion[12]; ///< 12 characters version + IN MODULE_ENTRY ModuleDispatcherPtr; ///< A pointer point to dispatcher + IN struct _AMD_MODULE_HEADER *NextBlockPtr; ///< Next module header link +} AMD_MODULE_HEADER; + +/// Extended PCI address format +typedef struct { + IN OUT UINT32 Register:12; ///< Register offset + IN OUT UINT32 Function:3; ///< Function number + IN OUT UINT32 Device:5; ///< Device number + IN OUT UINT32 Bus:8; ///< Bus number + IN OUT UINT32 Segment:4; ///< Segment +} EXT_PCI_ADDR; + +/// Union type for PCI address +typedef union _PCI_ADDR { + IN UINT32 AddressValue; ///< Formal address + IN EXT_PCI_ADDR Address; ///< Extended address +} PCI_ADDR; + +#define FUNC_0 0 // bit-placed for PCI address creation +#define FUNC_1 1 +#define FUNC_2 2 +#define FUNC_3 3 +#define FUNC_4 4 +#define FUNC_5 5 +#define FUNC_6 6 +#define FUNC_7 7 + +// SBDFO - Segment Bus Device Function Offset +// 31:28 Segment (4-bits) +// 27:20 Bus (8-bits) +// 19:15 Device (5-bits) +// 14:12 Function(3-bits) +// 11:00 Offset (12-bits) + +#define MAKE_SBDFO(Seg, Bus, Dev, Fun, Off) ((((UINT32) (Seg)) << 28) | (((UINT32) (Bus)) << 20) | \ + (((UINT32)(Dev)) << 15) | (((UINT32)(Fun)) << 12) | ((UINT32)(Off))) +#define ILLEGAL_SBDFO 0xFFFFFFFF + +/// CPUID data received registers format +typedef struct _CPUID_DATA { + IN OUT UINT32 EAX_Reg; ///< CPUID instruction result in EAX + IN OUT UINT32 EBX_Reg; ///< CPUID instruction result in EBX + IN OUT UINT32 ECX_Reg; ///< CPUID instruction result in ECX + IN OUT UINT32 EDX_Reg; ///< CPUID instruction result in EDX +} CPUID_DATA; + +#define WARM_RESET 1 +#define COLD_RESET 2 + +/// HT frequency for external callbacks +typedef enum { + HT_FREQUENCY_200M = 0, ///< HT speed 200 for external callbacks + HT_FREQUENCY_400M = 2, ///< HT speed 400 for external callbacks + HT_FREQUENCY_600M = 4, ///< HT speed 600 for external callbacks + HT_FREQUENCY_800M = 5, ///< HT speed 800 for external callbacks + HT_FREQUENCY_1000M = 6, ///< HT speed 1000 for external callbacks + HT_FREQUENCY_1200M = 7, ///< HT speed 1200 for external callbacks + HT_FREQUENCY_1400M = 8, ///< HT speed 1400 for external callbacks + HT_FREQUENCY_1600M = 9, ///< HT speed 1600 for external callbacks + HT_FREQUENCY_1800M = 10, ///< HT speed 1800 for external callbacks + HT_FREQUENCY_2000M = 11, ///< HT speed 2000 for external callbacks + HT_FREQUENCY_2200M = 12, ///< HT speed 2200 for external callbacks + HT_FREQUENCY_2400M = 13, ///< HT speed 2400 for external callbacks + HT_FREQUENCY_2600M = 14, ///< HT speed 2600 for external callbacks + HT_FREQUENCY_2800M = 17, ///< HT speed 2800 for external callbacks + HT_FREQUENCY_3000M = 18, ///< HT speed 3000 for external callbacks + HT_FREQUENCY_3200M = 19 ///< HT speed 3200 for external callbacks +} HT_FREQUENCIES; + +#ifndef BIT0 + #define BIT0 0x0000000000000001ull +#endif +#ifndef BIT1 + #define BIT1 0x0000000000000002ull +#endif +#ifndef BIT2 + #define BIT2 0x0000000000000004ull +#endif +#ifndef BIT3 + #define BIT3 0x0000000000000008ull +#endif +#ifndef BIT4 + #define BIT4 0x0000000000000010ull +#endif +#ifndef BIT5 + #define BIT5 0x0000000000000020ull +#endif +#ifndef BIT6 + #define BIT6 0x0000000000000040ull +#endif +#ifndef BIT7 + #define BIT7 0x0000000000000080ull +#endif +#ifndef BIT8 + #define BIT8 0x0000000000000100ull +#endif +#ifndef BIT9 + #define BIT9 0x0000000000000200ull +#endif +#ifndef BIT10 + #define BIT10 0x0000000000000400ull +#endif +#ifndef BIT11 + #define BIT11 0x0000000000000800ull +#endif +#ifndef BIT12 + #define BIT12 0x0000000000001000ull +#endif +#ifndef BIT13 + #define BIT13 0x0000000000002000ull +#endif +#ifndef BIT14 + #define BIT14 0x0000000000004000ull +#endif +#ifndef BIT15 + #define BIT15 0x0000000000008000ull +#endif +#ifndef BIT16 + #define BIT16 0x0000000000010000ull +#endif +#ifndef BIT17 + #define BIT17 0x0000000000020000ull +#endif +#ifndef BIT18 + #define BIT18 0x0000000000040000ull +#endif +#ifndef BIT19 + #define BIT19 0x0000000000080000ull +#endif +#ifndef BIT20 + #define BIT20 0x0000000000100000ull +#endif +#ifndef BIT21 + #define BIT21 0x0000000000200000ull +#endif +#ifndef BIT22 + #define BIT22 0x0000000000400000ull +#endif +#ifndef BIT23 + #define BIT23 0x0000000000800000ull +#endif +#ifndef BIT24 + #define BIT24 0x0000000001000000ull +#endif +#ifndef BIT25 + #define BIT25 0x0000000002000000ull +#endif +#ifndef BIT26 + #define BIT26 0x0000000004000000ull +#endif +#ifndef BIT27 + #define BIT27 0x0000000008000000ull +#endif +#ifndef BIT28 + #define BIT28 0x0000000010000000ull +#endif +#ifndef BIT29 + #define BIT29 0x0000000020000000ull +#endif +#ifndef BIT30 + #define BIT30 0x0000000040000000ull +#endif +#ifndef BIT31 + #define BIT31 0x0000000080000000ull +#endif +#ifndef BIT32 + #define BIT32 0x0000000100000000ull +#endif +#ifndef BIT33 + #define BIT33 0x0000000200000000ull +#endif +#ifndef BIT34 + #define BIT34 0x0000000400000000ull +#endif +#ifndef BIT35 + #define BIT35 0x0000000800000000ull +#endif +#ifndef BIT36 + #define BIT36 0x0000001000000000ull +#endif +#ifndef BIT37 + #define BIT37 0x0000002000000000ull +#endif +#ifndef BIT38 + #define BIT38 0x0000004000000000ull +#endif +#ifndef BIT39 + #define BIT39 0x0000008000000000ull +#endif +#ifndef BIT40 + #define BIT40 0x0000010000000000ull +#endif +#ifndef BIT41 + #define BIT41 0x0000020000000000ull +#endif +#ifndef BIT42 + #define BIT42 0x0000040000000000ull +#endif +#ifndef BIT43 + #define BIT43 0x0000080000000000ull +#endif +#ifndef BIT44 + #define BIT44 0x0000100000000000ull +#endif +#ifndef BIT45 + #define BIT45 0x0000200000000000ull +#endif +#ifndef BIT46 + #define BIT46 0x0000400000000000ull +#endif +#ifndef BIT47 + #define BIT47 0x0000800000000000ull +#endif +#ifndef BIT48 + #define BIT48 0x0001000000000000ull +#endif +#ifndef BIT49 + #define BIT49 0x0002000000000000ull +#endif +#ifndef BIT50 + #define BIT50 0x0004000000000000ull +#endif +#ifndef BIT51 + #define BIT51 0x0008000000000000ull +#endif +#ifndef BIT52 + #define BIT52 0x0010000000000000ull +#endif +#ifndef BIT53 + #define BIT53 0x0020000000000000ull +#endif +#ifndef BIT54 + #define BIT54 0x0040000000000000ull +#endif +#ifndef BIT55 + #define BIT55 0x0080000000000000ull +#endif +#ifndef BIT56 + #define BIT56 0x0100000000000000ull +#endif +#ifndef BIT57 + #define BIT57 0x0200000000000000ull +#endif +#ifndef BIT58 + #define BIT58 0x0400000000000000ull +#endif +#ifndef BIT59 + #define BIT59 0x0800000000000000ull +#endif +#ifndef BIT60 + #define BIT60 0x1000000000000000ull +#endif +#ifndef BIT61 + #define BIT61 0x2000000000000000ull +#endif +#ifndef BIT62 + #define BIT62 0x4000000000000000ull +#endif +#ifndef BIT63 + #define BIT63 0x8000000000000000ull +#endif + +#ifdef ASSERT + #undef ASSERT + #define ASSERT(x) +#endif + +#endif diff --git a/src/northbridge/amd/cimx/rd890/cbtypes.h b/src/northbridge/amd/cimx/rd890/cbtypes.h new file mode 100644 index 0000000..ade55d7 --- /dev/null +++ b/src/northbridge/amd/cimx/rd890/cbtypes.h @@ -0,0 +1,71 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 - 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _CBTYPES_H_ +#define _CBTYPES_H_ + +//#include <stdint.h> + +/* +typedef int64_t __int64; +typedef void VOID; +typedef uint32_t UINTN;// +typedef int8_t CHAR8; +typedef uint8_t UINT8; +typedef uint16_t UINT16; +typedef uint32_t UINT32; +typedef uint64_t UINT64; +*/ +typedef signed long long __int64; +typedef void VOID; +typedef unsigned int UINTN;// +typedef signed char CHAR8; +typedef unsigned char UINT8; +typedef unsigned short UINT16; +typedef unsigned int UINT32; +typedef signed int INT32; +typedef unsigned long long UINT64; + +#define TRUE 1 +#define FALSE 0 +typedef unsigned char BOOLEAN; + +#ifndef VOLATILE +#define VOLATILE volatile +#endif + +#ifndef IN +#define IN +#endif +#ifndef OUT +#define OUT +#endif + +//porting.h +#ifndef CONST +#define CONST const +#endif +#ifndef STATIC +#define STATIC static +#endif +#ifndef VOLATILE +#define VOLATILE volatile +#endif + +#endif diff --git a/src/northbridge/amd/cimx/rd890/chip.h b/src/northbridge/amd/cimx/rd890/chip.h new file mode 100644 index 0000000..c2f985b --- /dev/null +++ b/src/northbridge/amd/cimx/rd890/chip.h @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#ifndef _CIMX_RD890_CHIP_H_ +#define _CIMX_RD890_CHIP_H_ + +extern struct chip_operations northbridge_amd_cimx_rd890_ops; + +/** + * RD890 specific device configuration + */ +struct northbridge_amd_cimx_rd890_config +{ + u8 gpp1_configuration; + u8 gpp2_configuration; + u8 gpp3a_configuration; + u16 port_enable; +}; + +#endif /* _CIMX_RD890_CHIP_H_ */ + diff --git a/src/northbridge/amd/cimx/rd890/early.c b/src/northbridge/amd/cimx/rd890/early.c new file mode 100644 index 0000000..8008223 --- /dev/null +++ b/src/northbridge/amd/cimx/rd890/early.c @@ -0,0 +1,113 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include "NbPlatform.h" +#include "rd890_cfg.h" +#include "nb_cimx.h" + + +/** + * @brief disable GPP1 Port0,1, GPP2, GPP3a Port0,1,2,3,4,5, GPP3b + * + * SR5650/5670/5690 RD890 chipset, read pci config space hang at POR, + * Disable all Pcie Bridges to work around It. + */ +void sr56x0_rd890_disable_pcie_bridge(void) +{ + u32 nb_dev; + u32 mask; + u32 val; + AMD_NB_CONFIG_BLOCK cfg_block; + AMD_NB_CONFIG_BLOCK *cfg_ptr = &cfg_block; + AMD_NB_CONFIG *nb_cfg = &(cfg_block.Northbridges[0]); + + nb_cfg->ConfigPtr = &cfg_ptr; + nb_dev = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0); + val = (1 << 2) | (1 << 3); /*GPP1*/ + val |= (1 << 4) | (1 << 5) | (1 << 6) | (1 << 7) | (1 << 16) | (1 << 17); /*GPP3a*/ + val |= (1 << 18) | (1 << 19); /*GPP2*/ + val |= (1 << 20); /*GPP3b*/ + mask = ~val; + LibNbPciIndexRMW(nb_dev | NB_MISC_INDEX, NB_MISC_REG0C, + AccessS3SaveWidth32, + mask, + val, + nb_cfg); +} + + +/** + * @brief South Bridge CIMx romstage entry, + * wrapper of AmdPowerOnResetInit entry point. + */ +void nb_Poweron_Init(void) +{ + NB_CONFIG nb_cfg[MAX_NB_COUNT]; + HT_CONFIG ht_cfg[MAX_NB_COUNT]; + PCIE_CONFIG pcie_cfg[MAX_NB_COUNT]; + AMD_NB_CONFIG_BLOCK gConfig; + AMD_NB_CONFIG_BLOCK *ConfigPtr = &gConfig; + AGESA_STATUS status; + + printk(BIOS_DEBUG, "cimx/rd890 early.c %s() Start\n", __func__); + CIMX_INIT_TRACE(); + CIMX_TRACE((BIOS_DEBUG, "NbPowerOnResetInit entry\n")); + rd890_cimx_config(&gConfig, &nb_cfg[0], &ht_cfg[0], &pcie_cfg[0]); + + if (ConfigPtr->StandardHeader.CalloutPtr != NULL) { + ConfigPtr->StandardHeader.CalloutPtr(CB_AmdSetNbPorConfig, 0, &gConfig); + } + + status = AmdPowerOnResetInit(&gConfig); + printk(BIOS_DEBUG, "cimx/rd890 early.c %s() End. return status=%x\n", __func__, status); +} + +/** + * @brief South Bridge CIMx romstage entry, + * wrapper of AmdHtInit entry point. + */ +void nb_Ht_Init(void) +{ + AGESA_STATUS status; + NB_CONFIG nb_cfg[MAX_NB_COUNT]; + HT_CONFIG ht_cfg[MAX_NB_COUNT]; + PCIE_CONFIG pcie_cfg[MAX_NB_COUNT]; + AMD_NB_CONFIG_BLOCK gConfig; + AMD_NB_CONFIG_BLOCK *ConfigPtr = &gConfig; + u32 i; + + rd890_cimx_config(&gConfig, &nb_cfg[0], &ht_cfg[0], &pcie_cfg[0]); + + //Initialize HT structure + LibSystemApiCall(AmdHtInitializer, &gConfig); + for (i = 0; i < MAX_NB_COUNT; i ++) { + if (ConfigPtr->StandardHeader.CalloutPtr != NULL) { + ConfigPtr->StandardHeader.CalloutPtr(CB_AmdSetHtConfig, 0, (VOID*)&(gConfig.Northbridges[i])); + } + } + + status = LibSystemApiCall(AmdHtInit, &gConfig); + printk(BIOS_DEBUG, "AmdHtInit status: %x\n", status); +} + +void nb_S3_Init(void) +{ + //TODO +} diff --git a/src/northbridge/amd/cimx/rd890/late.c b/src/northbridge/amd/cimx/rd890/late.c new file mode 100644 index 0000000..62a842a --- /dev/null +++ b/src/northbridge/amd/cimx/rd890/late.c @@ -0,0 +1,269 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <console/console.h> +#include <device/device.h> +#include <arch/ioapic.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include "NbPlatform.h" +#include "nb_cimx.h" +#include "rd890_cfg.h" + + +/** + * Global RD890 CIMX Configuration structure + */ +static NB_CONFIG nb_cfg[MAX_NB_COUNT]; +static HT_CONFIG ht_cfg[MAX_NB_COUNT]; +static PCIE_CONFIG pcie_cfg[MAX_NB_COUNT]; +static AMD_NB_CONFIG_BLOCK gConfig; + + +/** + * Reset PCIE Cores, Training the Ports selected by port_enable of devicetree + * After this call EP are fully operational on particular NB + */ +void nb_Pcie_Early_Init(void) +{ + LibSystemApiCall(AmdPcieEarlyInit, &gConfig); //AmdPcieEarlyInit(&gConfig); +} + +void nb_Pcie_Late_Init(void) +{ + LibSystemApiCall(AmdPcieLateInit, &gConfig); +} + +void nb_Early_Post_Init(void) +{ + LibSystemApiCall(AmdEarlyPostInit, &gConfig); +} + +void nb_Mid_Post_Init(void) +{ + LibSystemApiCall(AmdMidPostInit, &gConfig); +} + +void nb_Late_Post_Init(void) +{ + LibSystemApiCall(AmdLatePostInit, &gConfig); +} + +static void rd890_enable(device_t dev) +{ + u32 address = 0; + u32 mask; + u32 val; + u32 devfn; + u32 port; + AMD_NB_CONFIG *NbConfigPtr = NULL; + + u8 nb_index = 0; /* The first IO Hub, TODO: other NBs */ + address = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0); + NbConfigPtr = &(gConfig.Northbridges[nb_index]); + + devfn = dev->path.pci.devfn; + port = devfn >> 3; + printk(BIOS_INFO, "rd890_enable "); + printk(BIOS_INFO, "Bus-%x Dev-%X Fun-%X, enable=%x\n", + 0, (devfn >> 3), (devfn & 0x07), dev->enabled); + if (port != 0) { + if (dev->enabled) { + NbConfigPtr->pPcieConfig->PortConfiguration[port].ForcePortDisable = OFF; + } else { + NbConfigPtr->pPcieConfig->PortConfiguration[port].ForcePortDisable = ON; + } + } + + switch (port) { + case 0x0: /* Root Complex, and ClkConfig */ + + if ((devfn & 0x07) == 1) { /* skip dev-0 fun-1 */ + break; + } + + /* CIMX configuration defualt initialize */ + rd890_cimx_config(&gConfig, &nb_cfg[0], &ht_cfg[0], &pcie_cfg[0]); + if (gConfig.StandardHeader.CalloutPtr != NULL) { + /* NOTE: not use LibNbCallBack */ + gConfig.StandardHeader.CalloutPtr(CB_AmdSetPcieEarlyConfig, (u32)dev, (VOID*)NbConfigPtr); + } + /* Reset PCIE Cores, Training the Ports selected by port_enable of devicetree + * After this call EP are fully operational on particular NB + */ + nb_Pcie_Early_Init(); + break; + + case 0x2: /* Gpp1 Port0 */ + case 0x3: /* Gpp1 Port1 */ + mask = ~(1 << port); + val = (dev->enabled ? 0 : 1) << port; + LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr); + break; + + case 0x4: /* Gpp3a Port0 */ + case 0x5: /* Gpp3a Port1 */ + case 0x6: /* Gpp3a Port2 */ + case 0x7: /* Gpp3a Port3 */ + mask = ~(1 << port); + val = (dev->enabled ? 0 : 1) << port; + LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr); + break; + + case 0x8: /* SB ALink */ + mask = ~(1 << 6); + val = (dev->enabled ? 1 : 0) << 6; + LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr); + break; + + case 0x9: /* Gpp3a Port4 */ + case 0xa: /* Gpp3a Port5 */ + mask = ~(1 << (7 + port)); + val = (dev->enabled ? 0 : 1) << (7 + port); + LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr); + break; + + case 0xb: /* Gpp2 Port0 */ + case 0xc: /* Gpp2 Port1 */ + mask = ~(1 << (7 + port)); + val = (dev->enabled ? 0 : 1) << (7 + port); + LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr); + break; + + case 0xd: /* Gpp3b */ + mask = ~(1 << (7 + port)); + val = (dev->enabled ? 0 : 1) << (7 + port); + LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr); + + /* Init NB at Early Post */ + if (gConfig.StandardHeader.CalloutPtr != NULL) { + gConfig.StandardHeader.CalloutPtr(CB_AmdSetEarlyPostConfig, 0, (VOID*)NbConfigPtr); + } + nb_Early_Post_Init();// + if (gConfig.StandardHeader.CalloutPtr != NULL) { + gConfig.StandardHeader.CalloutPtr(CB_AmdSetMidPostConfig, 0, (VOID*)NbConfigPtr); + } + nb_Mid_Post_Init(); + nb_Pcie_Late_Init(); + if (gConfig.StandardHeader.CalloutPtr != NULL) { + gConfig.StandardHeader.CalloutPtr(CB_AmdSetLatePostConfig, 0, (VOID*)NbConfigPtr); + } + nb_Late_Post_Init(); + break; + + default: + printk(BIOS_INFO, "Buggy Device Tree\n"); + break; + } +} + +struct chip_operations northbridge_amd_cimx_rd890_ops = { + CHIP_NAME("ATI rd890") + .enable_dev = rd890_enable, +}; + + +static void ioapic_init(struct device *dev) +{ + u32 ioapic_base; + + pci_write_config32(dev, 0xF8, 0x1); + ioapic_base = pci_read_config32(dev, 0xFC) & 0xfffffff0; + setup_ioapic(ioapic_base, 1); +} + +static void rd890_read_resource(struct device *dev) +{ + pci_dev_read_resources(dev); + + /* rpr6.2.(1). Write the Base Address Register (BAR) */ + pci_write_config32(dev, 0xF8, 0x1); /* set IOAPIC's index as 1 and make sure no one changes it. */ + pci_get_resource(dev, 0xFC); /* APIC located in sr5690 */ + + compact_resources(dev); +} + +/* If IOAPIC's index changes, we should replace the pci_dev_set_resource(). */ +static void rd890_set_resources(struct device *dev) +{ + pci_write_config32(dev, 0xF8, 0x1); /* set IOAPIC's index as 1 and make sure no one changes it. */ + pci_dev_set_resources(dev); +} + +static struct pci_operations lops_pci = { + .set_subsystem = pci_dev_set_subsystem, +}; + +static struct device_operations ht_ops = { + .read_resources = rd890_read_resource, + .set_resources = rd890_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = ioapic_init, + .scan_bus = 0, + .ops_pci = &lops_pci, +}; + +static const struct pci_driver ht_driver_sr5690 __pci_driver = { + .ops = &ht_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_AMD_SR5690_HT, +}; + +static const struct pci_driver ht_driver_sr5670 __pci_driver = { + .ops = &ht_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_AMD_SR5670_HT, +}; + +static const struct pci_driver ht_driver_sr5650 __pci_driver = { + .ops = &ht_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_AMD_SR5650_HT, +}; + +static const struct pci_driver ht_driver_rd890tv __pci_driver = { + .ops = &ht_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_AMD_RD890TV_HT, +}; + +static const struct pci_driver ht_driver_rx780 __pci_driver = { + .ops = &ht_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_AMD_RX780_HT, +}; + +static const struct pci_driver ht_driver_rd780 __pci_driver = { + .ops = &ht_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_AMD_RD780_HT, +}; + +static const struct pci_driver ht_driver_rd890 __pci_driver = { + .ops = &ht_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_AMD_RD890_HT, +}; + +static const struct pci_driver ht_driver_990fx __pci_driver = { + .ops = &ht_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_AMD_990FX_HT, +}; diff --git a/src/northbridge/amd/cimx/rd890/nb_cimx.h b/src/northbridge/amd/cimx/rd890/nb_cimx.h new file mode 100644 index 0000000..a6f77db --- /dev/null +++ b/src/northbridge/amd/cimx/rd890/nb_cimx.h @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _NB_CIMX_H_ +#define _NB_CIMX_H_ + +/** + * @brief disable GPP1 Port0,1, GPP2, GPP3a Port0,1,2,3,4,5, GPP3b + * + * SR5650/5670/5690 RD890 chipset, read pci config space hang at POR, + * Disable all Pcie Bridges to work around It. + */ +void sr56x0_rd890_disable_pcie_bridge(void); + +/** + * Northbridge CIMX entries point + */ +void nb_Poweron_Init(void); +void nb_Ht_Init(void); +void nb_S3_Init(void); +void nb_Early_Post_Init(void); +void nb_Mid_Post_Init(void); +void nb_Late_Post_Init(void); +void nb_Pcie_Early_Init(void); +void nb_Pcie_Late_Init(void); + +#endif//_RD890_EARLY_H_ +

1 0

Patch set updated for coreboot: 65f1fb2 SB700 southbridge: AMD SB700/SP5100 southbridge CIMX code
by Kerry Sheh Jan. 31, 2012

Jan. 31, 2012

Kerry Sheh (shekairui(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/560 -gerrit commit 65f1fb27844791bddcc20799305681ebb0e6cce6 Author: Kerry Sheh <shekairui(a)gmail.com> Date: Tue Jan 31 20:42:14 2012 +0800 SB700 southbridge: AMD SB700/SP5100 southbridge CIMX code Support AMD SB700 and SP5100 chipsets. Change-Id: I0955abf7f48a79483f624b46a61b22711315f888 Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> --- src/vendorcode/amd/cimx/Makefile.inc | 1 + src/vendorcode/amd/cimx/sb700/ACPILIB.c | 120 ++++ src/vendorcode/amd/cimx/sb700/ACPILIB.h | 61 ++ src/vendorcode/amd/cimx/sb700/AMDLIB.c | 434 ++++++++++++ src/vendorcode/amd/cimx/sb700/AMDSBLIB.c | 276 ++++++++ src/vendorcode/amd/cimx/sb700/AZALIA.c | 304 ++++++++ src/vendorcode/amd/cimx/sb700/DEBUG.c | 169 +++++ src/vendorcode/amd/cimx/sb700/DISPATCHER.c | 208 ++++++ src/vendorcode/amd/cimx/sb700/EC.c | 132 ++++ src/vendorcode/amd/cimx/sb700/FLASH.c | 58 ++ src/vendorcode/amd/cimx/sb700/LEGACY.c | 38 + src/vendorcode/amd/cimx/sb700/Makefile.inc | 77 ++ src/vendorcode/amd/cimx/sb700/OEM.h | 87 +++ src/vendorcode/amd/cimx/sb700/SATA.c | 453 ++++++++++++ src/vendorcode/amd/cimx/sb700/SB700.h | 1028 ++++++++++++++++++++++++++++ src/vendorcode/amd/cimx/sb700/SBCMN.c | 572 ++++++++++++++++ src/vendorcode/amd/cimx/sb700/SBCMNLIB.c | 108 +++ src/vendorcode/amd/cimx/sb700/SBCMNLIB.h | 89 +++ src/vendorcode/amd/cimx/sb700/SBDEF.h | 166 +++++ src/vendorcode/amd/cimx/sb700/SBMAIN.c | 289 ++++++++ src/vendorcode/amd/cimx/sb700/SBPOR.c | 441 ++++++++++++ src/vendorcode/amd/cimx/sb700/SBTYPE.h | 249 +++++++ src/vendorcode/amd/cimx/sb700/SMM.c | 91 +++ src/vendorcode/amd/cimx/sb700/USB.c | 187 +++++ src/vendorcode/amd/cimx/sb700/sbAMDLIB.h | 196 ++++++ 25 files changed, 5834 insertions(+), 0 deletions(-) diff --git a/src/vendorcode/amd/cimx/Makefile.inc b/src/vendorcode/amd/cimx/Makefile.inc index 3622312..7051ea2 100644 --- a/src/vendorcode/amd/cimx/Makefile.inc +++ b/src/vendorcode/amd/cimx/Makefile.inc @@ -1,3 +1,4 @@ +subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += sb700 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += sb800 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += sb900 subdirs-$(CONFIG_NORTHBRIDGE_AMD_CIMX_RD890) += rd890 diff --git a/src/vendorcode/amd/cimx/sb700/ACPILIB.c b/src/vendorcode/amd/cimx/sb700/ACPILIB.c new file mode 100644 index 0000000..807b166 --- /dev/null +++ b/src/vendorcode/amd/cimx/sb700/ACPILIB.c @@ -0,0 +1,120 @@ +/***************************************************************************** + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + ***************************************************************************/ + + +#include "Platform.h" + +/*++ + +Routine Description: + + Locate ACPI table + +Arguments: + + Signature - table signature + +Returns: + + pointer to ACPI table + +--*/ +void* ACPI_LocateTable( + UINT32 Signature +) +{ + UINT32 i; + UINT32* RsdPtr = (UINT32*)0xe0000; + UINT32* Rsdt = NULL; + DESCRIPTION_HEADER* CurrentTable; + do{ +// if (*RsdPtr == ' DSR' && *(RsdPtr+1) == ' RTP'){ + if ((*RsdPtr == Int32FromChar ('R', 'S', 'D', ' ')) && (*(RsdPtr+1) == Int32FromChar ('R', 'T', 'P', ' '))){ + Rsdt = (UINT32*)((RSDP*)RsdPtr)->RsdtAddress; + break; + } + RsdPtr+=4; + }while (RsdPtr <= (UINT32*)0xffff0); + if(Rsdt != NULL && ACPI_GetTableChecksum(Rsdt)==0){ + for (i = 0;i < (((DESCRIPTION_HEADER*)Rsdt)->Length - sizeof(DESCRIPTION_HEADER))/4;i++){ + CurrentTable = (DESCRIPTION_HEADER*)*(UINT32*)((UINT8*)Rsdt + sizeof(DESCRIPTION_HEADER) + i*4); + if (CurrentTable->Signature == Signature) return CurrentTable; + } + } + return NULL; +} + +/*++ + +Routine Description: + + Update table checksum + +Arguments: + + TablePtr - table pointer + +Returns: + + none + +--*/ +void ACPI_SetTableChecksum( + void* TablePtr +) +{ + UINT8 Checksum = 0; + ((DESCRIPTION_HEADER*)TablePtr)->Checksum = 0; + Checksum = ACPI_GetTableChecksum(TablePtr); + ((DESCRIPTION_HEADER*)TablePtr)->Checksum = 0x100 - Checksum; +} + +/*++ + +Routine Description: + + Get table checksum + +Arguments: + + TablePtr - table pointer + +Returns: + + none + +--*/ +UINT8 ACPI_GetTableChecksum( + void* TablePtr +) +{ + return GetByteSum(TablePtr,((DESCRIPTION_HEADER*)TablePtr)->Length); +} + diff --git a/src/vendorcode/amd/cimx/sb700/ACPILIB.h b/src/vendorcode/amd/cimx/sb700/ACPILIB.h new file mode 100644 index 0000000..5f2734f --- /dev/null +++ b/src/vendorcode/amd/cimx/sb700/ACPILIB.h @@ -0,0 +1,61 @@ +/*;******************************************************************************** +; +; Copyright (C) 2012 Advanced Micro Devices, Inc. +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; * Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; * Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution. +; * Neither the name of Advanced Micro Devices, Inc. nor the names of +; its contributors may be used to endorse or promote products derived +; from this software without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;*********************************************************************************/ + +#ifndef _AMD_ACPILIB_H_ +#define _AMD_ACPILIB_H_ + +typedef struct _RSDP{ + UINT64 Signature; + UINT8 Checksum; + UINT8 OEMID[6]; + UINT8 Revision; + UINT32 RsdtAddress; + UINT32 Length; + UINT64 XsdtAddress; + UINT8 ExtendedChecksum; + UINT8 Reserved[3]; +}RSDP; + +typedef struct _DESCRIPTION_HEADER{ + UINT32 Signature; + UINT32 Length; + UINT8 Revision; + UINT8 Checksum; + UINT8 OEMID[6]; + UINT8 OEMTableID[8]; + UINT32 OEMRevision; + UINT32 CreatorID; + UINT32 CreatorRevision; +}DESCRIPTION_HEADER; + +void* ACPI_LocateTable(UINT32 Signature); +void ACPI_SetTableChecksum(void* TablePtr); +UINT8 ACPI_GetTableChecksum(void* TablePtr); + +#endif //ifndef _AMD_ACPILIB_H_ diff --git a/src/vendorcode/amd/cimx/sb700/AMDLIB.c b/src/vendorcode/amd/cimx/sb700/AMDLIB.c new file mode 100644 index 0000000..b233259 --- /dev/null +++ b/src/vendorcode/amd/cimx/sb700/AMDLIB.c @@ -0,0 +1,434 @@ +/***************************************************************************** + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + ***************************************************************************/ + + + +#include "Platform.h" + +VOID +ReadIO ( + IN UINT16 Address, + IN UINT8 OpFlag, + IN VOID* Value + ) +{ + OpFlag = OpFlag & 0x7f; + switch ( OpFlag ) { + case AccWidthUint8: + *(UINT8*)Value = ReadIo8 (Address); + break; + case AccWidthUint16: + *(UINT16*)Value = ReadIo16 (Address); + break; + case AccWidthUint32: + *(UINT32*)Value = ReadIo32 (Address); + break; + default: + break; + } +} + +VOID +WriteIO ( + IN UINT16 Address, + IN UINT8 OpFlag, + IN VOID* Value + ) +{ + OpFlag = OpFlag & 0x7f; + switch ( OpFlag ) { + case AccWidthUint8: + WriteIo8 (Address, *(UINT8*)Value); + break; + case AccWidthUint16: + WriteIo16 (Address, *(UINT16*)Value); + break; + case AccWidthUint32: + WriteIo32 (Address, *(UINT32*)Value); + break; + default: + break; + } +} + +VOID +RWIO ( + IN UINT16 Address, + IN UINT8 OpFlag, + IN UINT32 Mask, + IN UINT32 Data + ) +{ + UINT32 Result; + ReadIO (Address, OpFlag, &Result); + Result = (Result & Mask) | Data; + WriteIO (Address, OpFlag, &Result); +} + + +VOID +ReadPCI ( + IN UINT32 Address, + IN UINT8 OpFlag, + IN VOID* Value + ) +{ + OpFlag = OpFlag & 0x7f; + + if ( (UINT16)Address < 0xff ) { + //Normal Config Access + UINT32 AddrCf8; + AddrCf8 = (1 << 31) + ((Address >> 8) & 0x0FFFF00) + (Address & 0xFC); + WriteIO (0xCf8, AccWidthUint32, &AddrCf8); + ReadIO ((UINT16) (0xCfC + (Address & 0x3)), OpFlag, Value); + } +} + +VOID +WritePCI ( + IN UINT32 Address, + IN UINT8 OpFlag, + IN VOID* Value + ) +{ + OpFlag = OpFlag & 0x7f; + if ( (UINT16)Address < 0xff ) { + //Normal Config Access + UINT32 AddrCf8; + AddrCf8 = (1 << 31) + ((Address >> 8)&0x0FFFF00) + (Address & 0xFC); + WriteIO (0xCf8, AccWidthUint32, &AddrCf8); + WriteIO ((UINT16) (0xCfC + (Address & 0x3)), OpFlag, Value); + } +} + +VOID +RWPCI ( + IN UINT32 Address, + IN UINT8 OpFlag, + IN UINT32 Mask, + IN UINT32 Data + ) +{ + UINT32 Result; + Result = 0; + OpFlag = OpFlag & 0x7f; + ReadPCI (Address, OpFlag, &Result); + Result = (Result & Mask) | Data; + WritePCI (Address, OpFlag, &Result); +} + +void +ReadIndexPCI32 ( +UINT32 PciAddress, +UINT32 IndexAddress, +void* Value +) +{ + WritePCI(PciAddress,AccWidthUint32,&IndexAddress); + ReadPCI(PciAddress+4,AccWidthUint32,Value); +} + +void +WriteIndexPCI32 ( +UINT32 PciAddress, +UINT32 IndexAddress, +UINT8 OpFlag, +void* Value +) +{ + + WritePCI(PciAddress,AccWidthUint32 | (OpFlag & 0x80),&IndexAddress); + WritePCI(PciAddress+4,AccWidthUint32 | (OpFlag & 0x80) ,Value); +} + +void +RWIndexPCI32 ( +UINT32 PciAddress, +UINT32 IndexAddress, +UINT8 OpFlag, +UINT32 Mask, +UINT32 Data +) +{ + UINT32 Result; + ReadIndexPCI32(PciAddress,IndexAddress,&Result); + Result = (Result & Mask)| Data; + WriteIndexPCI32(PciAddress,IndexAddress,(OpFlag & 0x80),&Result); + +} + +void +ReadMEM ( +UINT32 Address, +UINT8 OpFlag, +void* Value +) +{ + OpFlag = OpFlag & 0x7f; + switch (OpFlag){ + case AccWidthUint8 : *((UINT8*)Value)=*((UINT8*)Address);break; + case AccWidthUint16: *((UINT16*)Value)=*((UINT16*)Address);break; + case AccWidthUint32: *((UINT32*)Value)=*((UINT32*)Address);break; + } +} + +void +WriteMEM ( +UINT32 Address, +UINT8 OpFlag, +void* Value +) +{ + OpFlag = OpFlag & 0x7f; + switch (OpFlag){ + case AccWidthUint8 : *((UINT8*)Address)=*((UINT8*)Value);break; + case AccWidthUint16: *((UINT16*)Address)=*((UINT16*)Value);break; + case AccWidthUint32: *((UINT32*)Address)=*((UINT32*)Value);break; + } +} + +void +RWMEM ( +UINT32 Address, +UINT8 OpFlag, +UINT32 Mask, +UINT32 Data +) +{ + UINT32 Result; + ReadMEM(Address,OpFlag,&Result); + Result = (Result & Mask)| Data; + WriteMEM(Address,OpFlag,&Result); +} + + +void +RWMSR( +UINT32 Address, +UINT64 Mask, +UINT64 Value +) +{ + MsrWrite(Address,(MsrRead(Address)& Mask)|Value); +} + +UINT32 +IsFamily10() +{ + CPUID_DATA Cpuid; + CpuidRead(0x1,(CPUID_DATA *)&Cpuid); + + return Cpuid.REG_EAX & 0xff00000; +} + + +UINT8 GetNumberOfCpuCores(void) +{ + UINT8 Result=1; + Result=ReadNumberOfCpuCores(); + return Result; +} + + +void +Stall( +UINT32 uSec +) +{ + UINT16 timerAddr; + UINT32 startTime, elapsedTime; + ReadPMIO(SB_PMIO_REG24, AccWidthUint16, &timerAddr); + + if (timerAddr ==0){ + uSec = uSec/2; + while (uSec!=0){ + ReadIO(0x80,AccWidthUint8,(UINT8 *)(&startTime)); + uSec--; + } + } + else{ + ReadIO(timerAddr, AccWidthUint32,&startTime); + while (1){ + ReadIO(timerAddr, AccWidthUint32,&elapsedTime); + if (elapsedTime < startTime) + elapsedTime = elapsedTime+0xFFFFFFFF-startTime; + else + elapsedTime = elapsedTime-startTime; + if ((elapsedTime*28/100)>uSec) + break; + } + } +} + + +void +Reset( +) +{ + RWIO(0xcf9,AccWidthUint8,0x0,0x06); +} + + +CIM_STATUS +RWSMBUSBlock( +UINT8 Controller, +UINT8 Address, +UINT8 Offset, +UINT8 BufferSize, +UINT8* BufferPrt +) +{ + UINT16 SmbusPort; + UINT8 i; + UINT8 Status; + ReadPCI(PCI_ADDRESS(0,0x14,0,Controller?0x58:0x10),AccWidthUint16,&SmbusPort); + SmbusPort &= 0xfffe; + RWIO(SmbusPort + 0,AccWidthUint8,0x0,0xff); + RWIO(SmbusPort + 4,AccWidthUint8,0x0,Address); + RWIO(SmbusPort + 3,AccWidthUint8,0x0,Offset); + RWIO(SmbusPort + 2,AccWidthUint8,0x0,0x14); + RWIO(SmbusPort + 5,AccWidthUint8,0x0,BufferSize); + if(!(Address & 0x1)){ + for (i = 0 ;i < BufferSize;i++){ + WriteIO(SmbusPort + 7,AccWidthUint8,&BufferPrt[i]); + } + } + RWIO(SmbusPort + 2,AccWidthUint8,0x0,0x54); + do{ + ReadIO(SmbusPort + 0,AccWidthUint8,&Status); + if (Status & 0x1C) return CIM_ERROR; + if (Status & 0x02) break; + }while(!(Status & 0x1)); + + do{ + ReadIO(SmbusPort + 0,AccWidthUint8,&Status); + }while(Status & 0x1); + + if(Address & 0x1){ + for (i = 0 ;i < BufferSize;i++){ + ReadIO(SmbusPort + 7,AccWidthUint8,&BufferPrt[i]); + } + } + return CIM_SUCCESS; +} + + + +void outPort80(UINT32 pcode) +{ + WriteIO(0x80, AccWidthUint8, &pcode); + return; +} + + +UINT8 +GetByteSum( + void* pData, + UINT32 Length +) +{ + UINT32 i; + UINT8 Checksum = 0; + for (i = 0;i < Length;i++){ + Checksum += *((UINT8*)pData+i); + } + return Checksum; +} + + +UINT32 +readAlink( + UINT32 Index +){ + UINT32 Data; + WriteIO(ALINK_ACCESS_INDEX, AccWidthUint32, &Index); + ReadIO(ALINK_ACCESS_DATA, AccWidthUint32, &Data); + //Clear Index + Index=0; + WriteIO(ALINK_ACCESS_INDEX, AccWidthUint32, &Index); + return Data; +} + + +void +writeAlink( + UINT32 Index, + UINT32 Data +){ + WriteIO(ALINK_ACCESS_INDEX, AccWidthUint32, &Index); + WriteIO(ALINK_ACCESS_DATA, AccWidthUint32, &Data); + //Clear Index + Index=0; + WriteIO(ALINK_ACCESS_INDEX, AccWidthUint32, &Index); + +} + + +/** + * + * IsServer - Determine if southbridge type is SP5100 (server) or SB7x0 (non-server) + * + * A SP5100 is determined when both following two items are true: + * 1) Revision >= A14; + * 2) A server north bridge chipset is detected; + * + * A list of server north bridge chipset: + * + * Family DeviceID + * ---------------------- + * SR5690 0x5A10 + * SR5670 0x5A12 + * SR5650 0x5A13 + * + */ +UINT8 +IsServer (void){ + UINT16 DevID; + + if (getRevisionID () < SB700_A14) { + return 0; + } + ReadPCI ((NB_BDF << 16) + 2, AccWidthUint16, &DevID); + return ((DevID == 0x5a10) || (DevID == 0x5a12) || (DevID == 0x5a13))? 1: 0; +} + +/** + * + * IsLS2Mode - Determine if LS2 mode is enabled or not in northbridge. + * + */ +UINT8 +IsLs2Mode (void) +{ + UINT32 HT3LinkTraining0; + + ReadPCI ((NB_BDF << 16) + 0xAC, AccWidthUint32, &HT3LinkTraining0); + return ( HT3LinkTraining0 & 0x100 )? 1: 0; +} diff --git a/src/vendorcode/amd/cimx/sb700/AMDSBLIB.c b/src/vendorcode/amd/cimx/sb700/AMDSBLIB.c new file mode 100644 index 0000000..bf4f06a --- /dev/null +++ b/src/vendorcode/amd/cimx/sb700/AMDSBLIB.c @@ -0,0 +1,276 @@ +/***************************************************************************** + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + ***************************************************************************/ + + +#include "Platform.h" + + +void +ReadPMIO ( +UINT8 Address, +UINT8 OpFlag, +void* Value +) +{ + UINT8 i; + + OpFlag = OpFlag & 0x7f; + if (OpFlag == 0x02) OpFlag = 0x03; + for (i=0;i<=OpFlag;i++){ + WriteIO(0xCD6, AccWidthUint8, &Address); // SB_IOMAP_REGCD6 + Address++; + ReadIO(0xCD7, AccWidthUint8, (UINT8 *)Value+i); // SB_IOMAP_REGCD7 + } +} + + +void +WritePMIO ( +UINT8 Address, +UINT8 OpFlag, +void* Value +) +{ + UINT8 i; + + OpFlag = OpFlag & 0x7f; + if (OpFlag == 0x02) OpFlag = 0x03; + for (i=0;i<=OpFlag;i++){ + WriteIO(0xCD6, AccWidthUint8, &Address); // SB_IOMAP_REGCD6 + Address++; + WriteIO(0xCD7, AccWidthUint8, (UINT8 *)Value+i); // SB_IOMAP_REGCD7 + } +} + + +void +RWPMIO ( +UINT8 Address, +UINT8 OpFlag, +UINT32 AndMask, +UINT32 OrMask +) +{ + UINT32 Result; + + OpFlag = OpFlag & 0x7f; + ReadPMIO(Address,OpFlag,&Result); + Result = (Result & AndMask)| OrMask; + WritePMIO(Address,OpFlag,&Result); +} + + +void +ReadPMIO2 ( +UINT8 Address, +UINT8 OpFlag, +void* Value +) +{ + UINT8 i; + + OpFlag = OpFlag & 0x7f; + if (OpFlag == 0x02) OpFlag = 0x03; + for (i=0;i<=OpFlag;i++){ + WriteIO(0xCD0, AccWidthUint8, &Address); // SB_IOMAP_REGCD0 + Address++; + ReadIO(0xCD1, AccWidthUint8, (UINT8 *)Value+i); // SB_IOMAP_REGCD1 + } +} + + +void +WritePMIO2 ( +UINT8 Address, +UINT8 OpFlag, +void* Value +) +{ + UINT8 i; + + OpFlag = OpFlag & 0x7f; + if (OpFlag == 0x02) OpFlag = 0x03; + for (i=0;i<=OpFlag;i++){ + WriteIO(0xCD0, AccWidthUint8, &Address); // SB_IOMAP_REGCD0 + Address++; + WriteIO(0xCD1, AccWidthUint8, (UINT8 *)Value+i); // SB_IOMAP_REGCD1 + } +} + + +void +RWPMIO2 ( +UINT8 Address, +UINT8 OpFlag, +UINT32 AndMask, +UINT32 OrMask +) +{ + UINT32 Result; + + OpFlag = OpFlag & 0x7f; + ReadPMIO2(Address,OpFlag,&Result); + Result = (Result & AndMask)| OrMask; + WritePMIO2(Address,OpFlag,&Result); +} + + +void +EnterEcConfig() +{ + UINT16 dwEcIndexPort; + + ReadPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4, AccWidthUint16 | S3_SAVE, &dwEcIndexPort); + dwEcIndexPort &= ~(UINT16)(BIT0); + RWIO(dwEcIndexPort, AccWidthUint8, 0x00, 0x5A); +} + +void +ExitEcConfig() +{ + UINT16 dwEcIndexPort; + + ReadPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4, AccWidthUint16 | S3_SAVE, &dwEcIndexPort); + dwEcIndexPort &= ~(UINT16)(BIT0); + RWIO(dwEcIndexPort, AccWidthUint8, 0x00, 0xA5); +} + + +void +ReadEC8 ( +UINT8 Address, +UINT8* Value +) +{ + UINT16 dwEcIndexPort; + + ReadPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4, AccWidthUint16 | S3_SAVE, &dwEcIndexPort); + dwEcIndexPort &= ~(UINT16)(BIT0); + WriteIO(dwEcIndexPort, AccWidthUint8, &Address); // SB_IOMAP_REGCD6 + ReadIO(dwEcIndexPort+1, AccWidthUint8, Value); // SB_IOMAP_REGCD7 +} + + +void +WriteEC8 ( +UINT8 Address, +UINT8* Value +) +{ + UINT16 dwEcIndexPort; + + ReadPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4, AccWidthUint16 | S3_SAVE, &dwEcIndexPort); + dwEcIndexPort &= ~(UINT16)(BIT0); + WriteIO(dwEcIndexPort, AccWidthUint8, &Address); // SB_IOMAP_REGCD6 + WriteIO(dwEcIndexPort+1, AccWidthUint8, Value); // SB_IOMAP_REGCD7 +} + + +void +RWEC8 ( +UINT8 Address, +UINT8 AndMask, +UINT8 OrMask +) +{ + UINT8 Result; + ReadEC8(Address,&Result); + Result = (Result & AndMask)| OrMask; + WriteEC8(Address, &Result); +} + + +void +programPciByteTable ( +REG8MASK* pPciByteTable, +UINT16 dwTableSize +) +{ + UINT8 i, dbBusNo, dbDevFnNo; + UINT32 ddBDFR; + + dbBusNo = pPciByteTable->bRegIndex; + dbDevFnNo = pPciByteTable->bANDMask; + pPciByteTable++; + for (i = 1; i < dwTableSize; i++){ + if ( (pPciByteTable->bRegIndex==0xFF) && (pPciByteTable->bANDMask==0xFF) && (pPciByteTable->bORMask==0xFF) ){ + pPciByteTable++; + dbBusNo = pPciByteTable->bRegIndex; + dbDevFnNo = pPciByteTable->bANDMask; + } + else{ + ddBDFR = (dbBusNo << 24) + (dbDevFnNo << 16) + (pPciByteTable->bRegIndex) ; + TRACE((DMSG_SB_TRACE, "PFA=%X AND=%X, OR=%X\n", ddBDFR, pPciByteTable->bANDMask, pPciByteTable->bORMask)); + RWPCI(ddBDFR, AccWidthUint8 | S3_SAVE, pPciByteTable->bANDMask, pPciByteTable->bORMask); + pPciByteTable++; + } + } +} + + +void +programPmioByteTable ( +REG8MASK* pPmioByteTable, +UINT16 dwTableSize +) +{ + UINT8 i; + for (i = 0; i < dwTableSize; i++){ + TRACE((DMSG_SB_TRACE, "PMIO Reg = %X AndMask = %X OrMask = %X\n",pPmioByteTable->bRegIndex,pPmioByteTable->bANDMask, pPmioByteTable->bORMask)); + RWPMIO(pPmioByteTable->bRegIndex, AccWidthUint8 , pPmioByteTable->bANDMask, pPmioByteTable->bORMask); + pPmioByteTable++; + } +} + + +UINT8 +getClockMode ( +void +) +{ + UINT8 dbTemp=0; + + RWPMIO(SB_PMIO_REGB2, AccWidthUint8, 0xFF, BIT7); + ReadPMIO(SB_PMIO_REGB0, AccWidthUint8, &dbTemp); + return(dbTemp&BIT4); +} + + +UINT16 +readStrapStatus ( +void +) +{ + UINT16 dwTemp=0; + + RWPMIO(SB_PMIO_REGB2, AccWidthUint8, 0xFF, BIT7); + ReadPMIO(SB_PMIO_REGB0, AccWidthUint16, &dwTemp); + return(dwTemp); +} diff --git a/src/vendorcode/amd/cimx/sb700/AZALIA.c b/src/vendorcode/amd/cimx/sb700/AZALIA.c new file mode 100644 index 0000000..cc72858 --- /dev/null +++ b/src/vendorcode/amd/cimx/sb700/AZALIA.c @@ -0,0 +1,304 @@ +/***************************************************************************** + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + ***************************************************************************/ + + + +#include "Platform.h" + +void configureAzaliaPinCmd (AMDSBCFG* pConfig, UINT32 ddBAR0, UINT8 dbChannelNum); +void configureAzaliaSetConfigD4Dword(CODECENTRY* tempAzaliaCodecEntryPtr, UINT32 ddChannelNum, UINT32 ddBAR0); + +//Pin Config for ALC880, ALC882 and ALC883: +CODECENTRY AzaliaCodecAlc882Table[] = { + {0x14, 0x01014010}, + {0x15, 0x01011012}, + {0x16, 0x01016011}, + {0x17, 0x01012014}, + {0x18, 0x01A19030}, + {0x19, 0x411111F0}, + {0x1a, 0x01813080}, + {0x1b, 0x411111F0}, + {0x1C, 0x411111F0}, + {0x1d, 0x411111F0}, + {0x1e, 0x01441150}, + {0x1f, 0x01C46160}, + {0xff, 0xffffffff} +}; + + +//Pin Config for ALC262 +CODECENTRY AzaliaCodecAlc262Table[] = { + {0x14, 0x01014010}, + {0x15, 0x411111F0}, + {0x16, 0x411111F0}, +// {0x17, 0x01012014}, + {0x18, 0x01A19830}, + {0x19, 0x02A19C40}, + {0x1a, 0x01813031}, + {0x1b, 0x02014C20}, + {0x1c, 0x411111F0}, + {0x1d, 0x411111F0}, + {0x1e, 0x0144111E}, + {0x1f, 0x01C46150}, + {0xff, 0xffffffff} +}; + +//Pin Config for ALC0861: +CODECENTRY AzaliaCodecAlc861Table[] = { + {0x01, 0x8086C601}, + {0x0B, 0x01014110}, + {0x0C, 0x01813140}, + {0x0D, 0x01A19941}, + {0x0E, 0x411111F0}, + {0x0F, 0x02214420}, + {0x10, 0x02A1994E}, + {0x11, 0x99330142}, + {0x12, 0x01451130}, + {0x1F, 0x411111F0}, + {0x20, 0x411111F0}, + {0x23, 0x411111F0}, + {0xff, 0xffffffff} +}; + +//Pin Config for ADI1984: +CODECENTRY AzaliaCodecAd1984Table[] = { + {0x11, 0x0221401F}, + {0x12, 0x90170110}, + {0x13, 0x511301F0}, + {0x14, 0x02A15020}, + {0x15, 0x50A301F0}, + {0x16, 0x593301F0}, + {0x17, 0x55A601F0}, + {0x18, 0x55A601F0}, + {0x1A, 0x91F311F0}, + {0x1B, 0x014511A0}, + {0x1C, 0x599301F0}, + {0xff, 0xffffffff} +}; + + +CODECENTRY FrontPanelAzaliaCodecTableList[] = { + {0x19, 0x02A19040}, + {0x1b, 0x02214020}, + {0xff, 0xffffffff} +}; + + +CODECTBLLIST azaliaCodecTableList[] = { + {0x010ec0880, &AzaliaCodecAlc882Table[0]}, + {0x010ec0882, &AzaliaCodecAlc882Table[0]}, + {0x010ec0883, &AzaliaCodecAlc882Table[0]}, + {0x010ec0885, &AzaliaCodecAlc882Table[0]}, + {0x010ec0262, &AzaliaCodecAlc262Table[0]}, + {0x010ec0861, &AzaliaCodecAlc861Table[0]}, + {0x011d41984, &AzaliaCodecAd1984Table[0]}, + {(UINT32)0x0FFFFFFFF, (CODECENTRY*)0xFFFFFFFF} +}; + + +/*------------------------------------------------------------------------------- +; Procedure: azaliaInitAfterPciEnum +; +; Description: This routine detects Azalia and, if present, initializes Azalia +; This routine is called from atiSbAfterPciInit +; +; +; Exit: None +; +; Modified: None +; +;----------------------------------------------------------------------------- +*/ +void azaliaInitAfterPciEnum (AMDSBCFG* pConfig){ + UINT8 i, dbEnableAzalia=0, dbPinRouting, dbChannelNum=0, dbTempVariable = 0; + UINT16 dwTempVariable = 0; + UINT32 ddBAR0, ddTempVariable = 0; + + if (pConfig->AzaliaController == 1) return; + + if (pConfig->AzaliaController != 1){ + RWPCI((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG04, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT1, BIT1); + ReadPCI((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG10, AccWidthUint32, &ddBAR0); + + if (ddBAR0 != 0){ //Keep the flag as disabled if BAR is 0 or all "F"s. + if (ddBAR0 != 0xFFFFFFFF){ + ddBAR0 &= ~(0x03FFF); + dbEnableAzalia = 1; + TRACE((DMSG_SB_TRACE, "CIMxSB - Enabling Azalia controller (BAR setup is ok) \n")); + } + } + } + + if (dbEnableAzalia){ //if Azalia is enabled + //Get SDIN Configuration + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGF8, AccWidthUint32 | S3_SAVE, 0, ddTempVariable); + ddTempVariable |= (pConfig->AzaliaSdin3 << 6); + ddTempVariable |= (pConfig->AzaliaSdin2 << 4); + ddTempVariable |= (pConfig->AzaliaSdin1 << 2); + ddTempVariable |= pConfig->AzaliaSdin0; + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGFC, AccWidthUint8 | S3_SAVE, 0, (ddTempVariable & 0xFF)); + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG60+3, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT2+BIT1+BIT0), 0); + + i=11; + do{ + ReadMEM( ddBAR0+SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable); + dbTempVariable |= BIT0; + WriteMEM(ddBAR0+SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable); + Stall(1000); + ReadMEM(ddBAR0+SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable); + i--; + } while ( (!(dbTempVariable & BIT0)) && (i > 0) ); + + if (i==0){ + TRACE((DMSG_SB_TRACE, "CIMxSB - Problem in resetting Azalia controller\n")); + return; + } + + Stall(1000); + ReadMEM( ddBAR0+SB_AZ_BAR_REG0E, AccWidthUint16, &dwTempVariable); + if (dwTempVariable & 0x0F){ + TRACE((DMSG_SB_TRACE, "CIMxSB - Atleast One Azalia CODEC found \n")); + //atleast one azalia codec found + ReadPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGFC, AccWidthUint8, &dbPinRouting); + do{ + if ( ( !(dbPinRouting & BIT0) ) && (dbPinRouting & BIT1) ) + configureAzaliaPinCmd(pConfig, ddBAR0, dbChannelNum); + dbPinRouting >>= 2; + dbChannelNum++; + } while (dbChannelNum != 4); + } + else{ + TRACE((DMSG_SB_TRACE, "CIMxSB - Azalia CODEC NOT found \n")); + //No Azalia codec found + if (pConfig->AzaliaController != 2) + dbEnableAzalia = 0; //set flag to disable Azalia + } + } + + if (dbEnableAzalia){ + //redo clear reset + do{ + dwTempVariable = 0; + WriteMEM( ddBAR0+SB_AZ_BAR_REG0C, AccWidthUint16 | S3_SAVE, &dwTempVariable); + ReadMEM(ddBAR0+SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable); + dbTempVariable &= ~(UINT8)(BIT0); + WriteMEM(ddBAR0+SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable); + ReadMEM(ddBAR0+SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable); + } while (dbTempVariable & BIT0); + + if (pConfig->AzaliaSnoop == 1) + RWPCI((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG42, AccWidthUint8 | S3_SAVE, 0xFF, BIT1+BIT0); + } + else{ + //disable Azalia controller + RWPCI((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG04, AccWidthUint16 | S3_SAVE, 0, 0); + RWPMIO(SB_PMIO_REG59, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT3, 0); + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGFC, AccWidthUint8 | S3_SAVE, 0, 0x55); + } +} + + +void configureAzaliaPinCmd (AMDSBCFG* pConfig, UINT32 ddBAR0, UINT8 dbChannelNum){ + UINT32 ddTempVariable, ddChannelNum; + CODECTBLLIST* ptempAzaliaOemCodecTablePtr; + CODECENTRY* tempAzaliaCodecEntryPtr; + + if ((pConfig->AzaliaPinCfg) != 1) + return; + + ddChannelNum = dbChannelNum << 28; + ddTempVariable = 0xF0000; + ddTempVariable |= ddChannelNum; + WriteMEM(ddBAR0 + SB_AZ_BAR_REG60, AccWidthUint32 | S3_SAVE, &ddTempVariable); + Stall(60); + ReadMEM(ddBAR0 + SB_AZ_BAR_REG64, AccWidthUint32 | S3_SAVE, &ddTempVariable); + + if ( ((pConfig->pAzaliaOemCodecTablePtr) == NULL) || ((pConfig->pAzaliaOemCodecTablePtr) == ((CODECTBLLIST*) 0xFFFFFFFF)) ) + ptempAzaliaOemCodecTablePtr = (CODECTBLLIST*) FIXUP_PTR(&azaliaCodecTableList[0]); + else + ptempAzaliaOemCodecTablePtr = (CODECTBLLIST*) pConfig->pAzaliaOemCodecTablePtr; + + TRACE((DMSG_SB_TRACE, "CIMxSB - Azalia CODEC table pointer is %x \n", (UINT32)ptempAzaliaOemCodecTablePtr)); + + while ( ptempAzaliaOemCodecTablePtr->CodecID != 0xFFFFFFFF){ + if ( ptempAzaliaOemCodecTablePtr->CodecID == ddTempVariable) + break; + else + ++ptempAzaliaOemCodecTablePtr; + } + + if ( ptempAzaliaOemCodecTablePtr->CodecID != 0xFFFFFFFF){ + TRACE((DMSG_SB_TRACE, "CIMxSB - Matching CODEC ID found \n")); + tempAzaliaCodecEntryPtr = (CODECENTRY*) ptempAzaliaOemCodecTablePtr->CodecTablePtr; + TRACE((DMSG_SB_TRACE, "CIMxSB - Matching Azalia CODEC table pointer is %x \n", (UINT32)tempAzaliaCodecEntryPtr)); + + if ( ((pConfig->pAzaliaOemCodecTablePtr) == NULL) || ((pConfig->pAzaliaOemCodecTablePtr) == ((CODECTBLLIST*) 0xFFFFFFFF)) ) + tempAzaliaCodecEntryPtr = (CODECENTRY*) FIXUP_PTR(tempAzaliaCodecEntryPtr); + + configureAzaliaSetConfigD4Dword(tempAzaliaCodecEntryPtr, ddChannelNum, ddBAR0); + if (pConfig->AzaliaFrontPanel != 1){ + if ( (pConfig->AzaliaFrontPanel == 2) || (pConfig->FrontPanelDetected == 1) ){ + if ( ((pConfig->pAzaliaOemFpCodecTableptr) == NULL) || ((pConfig->pAzaliaOemFpCodecTableptr) == 0xFFFFFFFF)) + tempAzaliaCodecEntryPtr = (CODECENTRY*) FIXUP_PTR(&FrontPanelAzaliaCodecTableList[0]); + else + tempAzaliaCodecEntryPtr = (CODECENTRY*) pConfig->pAzaliaOemFpCodecTableptr; + configureAzaliaSetConfigD4Dword(tempAzaliaCodecEntryPtr, ddChannelNum, ddBAR0); + } + } + } +} + + +void configureAzaliaSetConfigD4Dword(CODECENTRY* tempAzaliaCodecEntryPtr, UINT32 ddChannelNum, UINT32 ddBAR0){ + UINT8 dbtemp1,dbtemp2, i; + UINT32 ddtemp=0,ddtemp2=0; + + while ((tempAzaliaCodecEntryPtr->Nid) != 0xFF){ + dbtemp1=0x20; + if ((tempAzaliaCodecEntryPtr->Nid) == 0x1) + dbtemp1=0x24; + ddtemp = tempAzaliaCodecEntryPtr->Nid; + ddtemp &= 0xff; + ddtemp <<= 20; + ddtemp |= ddChannelNum; + ddtemp |= (0x700 << 8); + for(i=4; i>0; i--){ + do{ + ReadMEM(ddBAR0 + SB_AZ_BAR_REG68, AccWidthUint32, &ddtemp2); + } while (ddtemp2 & BIT0); + dbtemp2 = ( (tempAzaliaCodecEntryPtr->Byte40) >> ((4-i) * 8 ) ) & 0xff; + ddtemp = (ddtemp & 0xFFFF0000)+ ((dbtemp1 - i) << 8) + dbtemp2; + WriteMEM(ddBAR0 + SB_AZ_BAR_REG60, AccWidthUint32 | S3_SAVE, &ddtemp); + Stall(60); + } + ++tempAzaliaCodecEntryPtr; + } +} + diff --git a/src/vendorcode/amd/cimx/sb700/DEBUG.c b/src/vendorcode/amd/cimx/sb700/DEBUG.c new file mode 100644 index 0000000..f40682e --- /dev/null +++ b/src/vendorcode/amd/cimx/sb700/DEBUG.c @@ -0,0 +1,169 @@ +/***************************************************************************** + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + ***************************************************************************/ + + +#include "Platform.h" + +#define COM_BASE_ADDRESS 0x3f8 +#define DIVISOR 115200 +#define LF 0x0a +#define CR 0x0d + + +#ifdef CIM_DEBUG + #ifndef CIM_DEBUG_LEVEL + #define CIM_DEBUG_LEVEL 0xf +#endif + +void +TraceCode( UINT32 Level, UINT32 Code){ + + if (!(Level & CIM_DEBUG_LEVEL)){ + return; + } +#if CIM_DEBUG & 1 + if (Code != 0xFF){ + WriteIO(0x80,AccWidthUint8,&Code); + } +#endif + +} + + +void +TraceDebug( UINT32 Level, CHAR8 *Format, ...){ + CHAR8 temp[16]; + va_list ArgList; + + if (!(Level & CIM_DEBUG_LEVEL)){ + return; + } + +#if CIM_DEBUG & 2 + ArgList = va_start(ArgList,Format); + Format= (CHAR8*) FIXUP_PTR(Format); + while (1){ + if (*Format == 0) break; + if (*Format == '%'){ + int Radix = 0; + if(*(Format+1)=='s'||*(Format+1)=='S'){ + SendStringPort((CHAR8*) FIXUP_PTR(va_arg(ArgList,CHAR8*))); + Format+=2; + continue; + } + + if(*(Format+1)=='d'||*(Format+1)=='D'){ + Radix = 10; + } + if(*(Format+1)=='x'||*(Format+1)=='X'){ + Radix = 16; + } + if (Radix){ + ItoA(va_arg(ArgList,int),Radix,temp); + SendStringPort(temp); + Format+=2; + continue; + } + } + SendBytePort(*Format); + if(*(Format)==0x0a) SendBytePort(0x0d); + Format++; + } + va_end(ArgList); +#endif +} + + +void +ItoA( UINT32 Value, int Radix, char* pstr) +{ + char* tsptr = pstr; + char* rsptr = pstr; + char ch1,ch2; + unsigned int Reminder; +//Create String + do{ + Reminder = Value%Radix; + Value = Value/Radix; + if (Reminder<0xa) *tsptr=Reminder+'0'; + else *tsptr=Reminder-0xa+'a'; + tsptr++; + } while(Value); +//Reverse String + *tsptr = 0; + tsptr--; + while(tsptr>rsptr){ + ch1 = *tsptr; + ch2 = *rsptr; + *rsptr = ch1; + *tsptr = ch2; + tsptr--; + rsptr++; + } +} + +void +InitSerialOut(){ + UINT8 Data; + UINT16 Divisor; + Data = 0x87; + WriteIO(COM_BASE_ADDRESS + 0x3,AccWidthUint8, &Data); + Divisor = 115200 / DIVISOR; + Data = Divisor & 0xFF; + WriteIO(COM_BASE_ADDRESS + 0x00,AccWidthUint8, &Data); + Data = Divisor >> 8; + WriteIO(COM_BASE_ADDRESS + 0x01,AccWidthUint8, &Data); + Data = 0x07; + WriteIO(COM_BASE_ADDRESS + 0x3,AccWidthUint8, &Data); +} + + +void +SendStringPort(char* pstr){ + + while (*pstr!=0){ + SendBytePort(*pstr); + pstr++; + } +} + +void +SendBytePort(UINT8 Data) +{ + int Count = 80; + UINT8 Status; + do { + ReadIO((COM_BASE_ADDRESS + 0x05),AccWidthUint8, &Status); + if(Status == 0xff) break; + // Loop port is ready + } while ( (Status & 0x20) == 0 && (--Count) != 0); + WriteIO(COM_BASE_ADDRESS + 0x00,AccWidthUint8, &Data); +} +#endif diff --git a/src/vendorcode/amd/cimx/sb700/DISPATCHER.c b/src/vendorcode/amd/cimx/sb700/DISPATCHER.c new file mode 100644 index 0000000..ae5f9b8 --- /dev/null +++ b/src/vendorcode/amd/cimx/sb700/DISPATCHER.c @@ -0,0 +1,208 @@ +/***************************************************************************** + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + ***************************************************************************/ + + +#include "Platform.h" + +void DispatcherEntry(void *pConfig){ + +#ifdef B1_IMAGE + void *pB2ImagePtr = NULL; + CIM_IMAGE_ENTRY pB2ImageEntry; +#endif + +//#if CIM_DEBUG +// InitSerialOut(); +//#endif + + TRACE((DMSG_SB_TRACE, "CIM - SB700 Entry\n")); + +#ifdef B1_IMAGE + if ((UINT32)(((STDCFG*)pConfig)->pB2ImageBase) != 0xffffffff){ + if (((STDCFG*)pConfig)->pB2ImageBase) + pB2ImagePtr = CheckImage('007S',(void*)((STDCFG*)pConfig)->pB2ImageBase); + if (pB2ImagePtr == NULL) + pB2ImagePtr = LocateImage('007S'); + if (pB2ImagePtr!=NULL){ + TRACE((DMSG_SB_TRACE, "CIM - SB700 Redirect to B2 Image\n")); + ((STDCFG*)pConfig)->pImageBase = (UINT32)pB2ImagePtr; + pB2ImageEntry = (CIM_IMAGE_ENTRY)(*((UINT32*)pB2ImagePtr+1) + (UINT32)pB2ImagePtr); + (*pB2ImageEntry)(pConfig); + return; + } + } +#endif + saveConfigPointer(pConfig); + + if (((STDCFG*)pConfig)->Func == SB_POWERON_INIT) + sbPowerOnInit((AMDSBCFG*)pConfig); + +#ifndef B1_IMAGE + if (((STDCFG*)pConfig)->Func == SB_BEFORE_PCI_INIT) + sbBeforePciInit((AMDSBCFG*)pConfig); + if (((STDCFG*)pConfig)->Func == SB_AFTER_PCI_INIT) + sbAfterPciInit((AMDSBCFG*)pConfig); + if (((STDCFG*)pConfig)->Func == SB_LATE_POST_INIT) + sbLatePost((AMDSBCFG*)pConfig); + if (((STDCFG*)pConfig)->Func == SB_BEFORE_PCI_RESTORE_INIT) + sbBeforePciRestoreInit((AMDSBCFG*)pConfig); + if (((STDCFG*)pConfig)->Func == SB_AFTER_PCI_RESTORE_INIT) + sbAfterPciRestoreInit((AMDSBCFG*)pConfig); + if (((STDCFG*)pConfig)->Func == SB_SMM_SERVICE) + { + // sbSmmService((AMDSBCFG*)pConfig); + } + if (((STDCFG*)pConfig)->Func == SB_SMM_ACPION) + sbSmmAcpiOn((AMDSBCFG*)pConfig); +#endif + TRACE((DMSG_SB_TRACE, "CIMx - SB Exit\n")); +} + + +void* LocateImage(UINT32 Signature){ + void *Result; + UINT8 *ImagePtr = (UINT8*)(0xffffffff - (IMAGE_ALIGN-1)); + while ((UINT32)ImagePtr>=(0xfffffff - (NUM_IMAGE_LOCATION*IMAGE_ALIGN -1))){ + Result = CheckImage(Signature,(void*)ImagePtr); + if (Result != NULL) + return Result; + ImagePtr -= IMAGE_ALIGN; + } + return NULL; +} + + +void* CheckImage(UINT32 Signature, void* ImagePtr){ + UINT8 *TempImagePtr; + UINT8 Sum = 0; + UINT32 i; +// if ((*((UINT32*)ImagePtr) == 'ITA$' && ((CIMFILEHEADER*)ImagePtr)->ModuleLogo == Signature)){ + if ((*((UINT32*)ImagePtr) == Int32FromChar ('$', 'A', 'T', 'I')) && (((CIMFILEHEADER*)ImagePtr)->ModuleLogo == Signature)){ + //GetImage Image size + TempImagePtr = (UINT8*)ImagePtr; + for (i=0;i<(((CIMFILEHEADER*)ImagePtr)->ImageSize);i++){ + Sum += *TempImagePtr; + TempImagePtr++; + } + if (Sum == 0) + return ImagePtr; + } + return NULL; +} + + +UINT32 GetPciebase(){ + AMDSBCFG* Result; + Result = getConfigPointer(); + return Result->StdHeader.pPcieBase; +} + + +void saveConfigPointer(AMDSBCFG* pConfig){ + UINT8 dbReg, i; + UINT32 ddValue; + + ddValue = ((UINT32) pConfig); + dbReg = SB_ECMOS_REG08; + + for (i=0; i<=3; i++){ + WriteIO(SB_IOMAP_REG72, AccWidthUint8, &dbReg); + WriteIO(SB_IOMAP_REG73, AccWidthUint8, (UINT8 *)&ddValue); + ddValue >>= 8; + dbReg++; + } +} + + +AMDSBCFG* getConfigPointer(){ + UINT8 dbReg, dbValue, i; + UINT32 ddValue=0; + + dbReg = SB_ECMOS_REG08; + for (i=0; i<=3; i++){ + WriteIO(SB_IOMAP_REG72, AccWidthUint8, &dbReg); + ReadIO(SB_IOMAP_REG73, AccWidthUint8, &dbValue); + ddValue |= (dbValue<<(i*8)); + dbReg++; + } + return( (AMDSBCFG*) ddValue); +} + +/** + * AmdSbDispatcher - Dispatch Southbridge function + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +AGESA_STATUS +AmdSbDispatcher ( + IN VOID *pConfig + ) +{ + AGESA_STATUS Status = AGESA_SUCCESS; + + saveConfigPointer (pConfig); + + if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_POWERON_INIT ) { + sbPowerOnInit ((AMDSBCFG*) pConfig); + } + + if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_BEFORE_PCI_INIT ) { + sbBeforePciInit ((AMDSBCFG*)pConfig); + } + + if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_AFTER_PCI_INIT ) { + sbAfterPciInit ((AMDSBCFG*)pConfig); + } + + if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_LATE_POST_INIT ) { + sbLatePost ((AMDSBCFG*)pConfig); + } + + if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_BEFORE_PCI_RESTORE_INIT ) { + sbBeforePciRestoreInit ((AMDSBCFG*)pConfig); + } + + if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_AFTER_PCI_RESTORE_INIT ) { + sbAfterPciRestoreInit ((AMDSBCFG*)pConfig); + } + + if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_SMM_SERVICE ) { + sbSmmService ((AMDSBCFG*)pConfig); + } + + if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_SMM_ACPION ) { + sbSmmAcpiOn ((AMDSBCFG*)pConfig); + } + + return Status; +} diff --git a/src/vendorcode/amd/cimx/sb700/EC.c b/src/vendorcode/amd/cimx/sb700/EC.c new file mode 100644 index 0000000..3ad15e1 --- /dev/null +++ b/src/vendorcode/amd/cimx/sb700/EC.c @@ -0,0 +1,132 @@ +/***************************************************************************** + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + ***************************************************************************/ + + +#include "Platform.h" + +#ifndef NO_EC_SUPPORT + +REG8MASK sb710PorInitPciTable[] = { + // SMBUS Device(Bus 0, Dev 20, Func 0) + {0x00, SMBUS_BUS_DEV_FUN, 0}, + {SB_SMBUS_REG43, ~(UINT8)BIT3, 0x00}, //Make some hidden registers of smbus visible. + {SB_SMBUS_REG38, (UINT8)~(BIT7+BIT5+BIT4+BIT3+BIT2+BIT1), 0x0D}, + {SB_SMBUS_REG38+1, ~(UINT8)(BIT2+BIT1), BIT3 }, + {SB_SMBUS_REGE1, 0xFF, BIT1}, + {SB_SMBUS_REG43, 0xFF, BIT3}, //Make some hidden registers of smbus invisible. + {0xFF, 0xFF, 0xFF}, + + // LPC Device(Bus 0, Dev 20, Func 3) + {0x00, LPC_BUS_DEV_FUN, 0}, + {SB_LPC_REGB8+3, ~(UINT8)(BIT1), BIT7+BIT2}, + {0xFF, 0xFF, 0xFF}, +}; + +REG8MASK sb710PorPmioInitTbl[]={ + // index andmask ormask + {SB_PMIO_REGD7, 0xFF, BIT5}, + {SB_PMIO_REGBB, 0xFF, BIT5}, +}; + + +void ecPowerOnInit(BUILDPARAM *pBuildOptPtr, AMDSBCFG* pConfig){ + UINT8 dbVar0, i=0; + + if (!(isEcPresent())) + return; //return if EC is not enabled + + for(i=0;i<0xFF;i++){ + ReadPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG40, AccWidthUint8 | S3_SAVE, &dbVar0); + if ( dbVar0 & BIT7 ) break; //break if EC is ready + Stall(500); //wait for EC to become ready + } + + if (getRevisionID() >= SB700_A14){ + programPciByteTable( (REG8MASK*)FIXUP_PTR(&sb710PorInitPciTable[0]), sizeof(sb710PorInitPciTable)/sizeof(REG8MASK) ); + programPmioByteTable( (REG8MASK *)FIXUP_PTR(&sb710PorPmioInitTbl[0]), (sizeof(sb710PorPmioInitTbl)/sizeof(REG8MASK)) ); + } + + RWPCI(((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGBA), AccWidthUint8 | S3_SAVE, 0xFF, BIT2); //Enable SPI Prefetch in EC + + //Enable config mode + EnterEcConfig(); + + //Do settings for mailbox - logical device 0x09 + RWEC8(0x07, 0x00, 0x09); //switch to device 9 (Mailbox) + RWEC8(0x60, 0x00, (pBuildOptPtr->EcLdn9MailBoxAddr >> 8)); //set MSB of Mailbox port + RWEC8(0x61, 0x00, (pBuildOptPtr->EcLdn9MailBoxAddr & 0xFF)); //set LSB of Mailbox port + RWEC8(0x30, 0x00, 0x01); //;Enable Mailbox Registers Interface, bit0=1 + + if (pBuildOptPtr->EcKbd == CIMX_OPTION_ENABLED){ + RWPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG60+3), AccWidthUint8 | S3_SAVE, 0xFF, BIT7+BIT3); + //Enable KBRST#, IRQ1 & IRQ12, GateA20 Function signal from IMC + RWPMIO(SB_PMIO_REGBB, AccWidthUint8, 0xFF, BIT3+BIT2+BIT1+BIT0); + //Disable LPC Decoding of port 60/64 + RWPCI(((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG47), AccWidthUint8 | S3_SAVE, ~(UINT32)BIT5, 0); + //Enable logical device 0x07 (Keyboard controller) + RWEC8(0x07, 0x00, 0x07); + RWEC8(0x30, 0x00, 0x01); + } + + if (pBuildOptPtr->EcChannel0 == CIMX_OPTION_ENABLED){ + //Logical device 0x08 + RWEC8(0x07, 0x00, 0x08); + RWEC8(0x60, 0x00, 0x00); + RWEC8(0x61, 0x00, 0x62); + RWEC8(0x30, 0x00, 0x01); //;Enable Device 8 + } + //Logical device 0x05 + RWEC8(0x07, 0x00, 0x05); //Select logical device 05, IR controller + RWEC8(0x60, 0x00, pBuildOptPtr->EcLdn5MailBoxAddr >> 8); + RWEC8(0x61, 0x00, (pBuildOptPtr->EcLdn5MailBoxAddr & 0xFF)); + RWEC8(0x70, 0xF0, (pBuildOptPtr->EcLdn5Irq)); //Set IRQ to 05h + RWEC8(0x30, 0x00, 0x01); //Enable logical device 5, IR controller + + RWPMIO(SB_PMIO_REGBB, AccWidthUint8, 0xFF, BIT4); //Enable EC(IMC) to generate SMI to BIOS + ExitEcConfig(); +} + + +void ecInitBeforePciEnum(AMDSBCFG* pConfig){ + if (!(isEcPresent())) + return; //return if EC is not enabled +} + + +void ecInitLatePost(AMDSBCFG* pConfig){ + if (!(isEcPresent()) ) + return; //return if EC is not enabled + //Enable config mode + EnterEcConfig(); //Enable config mode + //for future use + ExitEcConfig(); +} + +#endif diff --git a/src/vendorcode/amd/cimx/sb700/FLASH.c b/src/vendorcode/amd/cimx/sb700/FLASH.c new file mode 100644 index 0000000..0d84245 --- /dev/null +++ b/src/vendorcode/amd/cimx/sb700/FLASH.c @@ -0,0 +1,58 @@ +/***************************************************************************** + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + ***************************************************************************/ + + +#include "Platform.h" + +void fcInitBeforePciEnum(AMDSBCFG* pConfig){ + + TRACE((DMSG_SB_TRACE, "Entering PreInit Flash \n")); + RWPMIO(SB_PMIO_REGB2, AccWidthUint8, ~(UINT32)BIT1, 00); + + //Enable IDE and disable flash + //Enable IDE and disable flash + RWPMIO(SB_PMIO_REG59, AccWidthUint8, ~(UINT32)(BIT1+BIT0), 0); + RWPMIO(SB_PMIO_REGB2, AccWidthUint8, ~(UINT32)(BIT3), BIT0); //Configure GPIO3 as IDE_RST# and release RST + if (pConfig->IdeController){ + //Disabling IDE controller + RWPCI((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG04, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT2+BIT1+BIT0), 0); + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGAE, AccWidthUint8 | S3_SAVE, 0xFF, BIT3); + } + else{ + //Enable IDE controller + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGAE, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT3), 0); + } + + //RPR 8.2 Enable IDE Data bus DD7 Pull down Resistor if IDE is enabled and FC is disabled + RWPMIO2(SB_PMIO2_REGE5, AccWidthUint8, 0xFF, BIT2); + //Slowdown the clock to FC if FC is not enabled, this is a power savings feature + RWPMIO(SB_PMIO_REGB2, AccWidthUint8, ~(UINT32)(BIT4), BIT4); + RWPMIO(SB_PMIO_REGBC, AccWidthUint8, 0xC0, 0); +} diff --git a/src/vendorcode/amd/cimx/sb700/LEGACY.c b/src/vendorcode/amd/cimx/sb700/LEGACY.c new file mode 100644 index 0000000..c904d59 --- /dev/null +++ b/src/vendorcode/amd/cimx/sb700/LEGACY.c @@ -0,0 +1,38 @@ +/***************************************************************************** + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + ***************************************************************************/ + + +#include "Platform.h" + +UINT32 GetFixUp(){ + STDCFG* Result; + Result = (STDCFG*) getConfigPointer(); + return Result->pImageBase; +} diff --git a/src/vendorcode/amd/cimx/sb700/Makefile.inc b/src/vendorcode/amd/cimx/sb700/Makefile.inc new file mode 100644 index 0000000..8954133 --- /dev/null +++ b/src/vendorcode/amd/cimx/sb700/Makefile.inc @@ -0,0 +1,77 @@ +#***************************************************************************** +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# * Neither the name of Advanced Micro Devices, Inc. nor the names of +# its contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +#***************************************************************************** + +# CIMX Root directory +CIMX_ROOT = $(src)/vendorcode/amd/cimx + +SB_CIMX_INC = -I$(src)/mainboard/$(MAINBOARDDIR) +SB_CIMX_INC += -I$(src)/southbridge/amd/cimx/sb700 +SB_CIMX_INC += -I$(CIMX_ROOT)/sb700 + +romstage-y += ACPILIB.c +romstage-y += AMDLIB.c +romstage-y += AMDSBLIB.c +romstage-y += AZALIA.c +romstage-y += DEBUG.c +romstage-y += DISPATCHER.c +romstage-y += EC.c +romstage-y += FLASH.c +romstage-y += SATA.c +romstage-y += SBCMN.c +romstage-y += SBCMNLIB.c +romstage-y += SBMAIN.c +romstage-y += SBPOR.c +romstage-y += SMM.c +romstage-y += USB.c + +ramstage-y += ACPILIB.c +ramstage-y += AMDLIB.c +ramstage-y += AMDSBLIB.c +ramstage-y += AZALIA.c +ramstage-y += DEBUG.c +ramstage-y += DISPATCHER.c +ramstage-y += EC.c +ramstage-y += FLASH.c +ramstage-y += SATA.c +ramstage-y += SBCMN.c +ramstage-y += SBCMNLIB.c +ramstage-y += SBMAIN.c +ramstage-y += SBPOR.c +ramstage-y += SMM.c +ramstage-y += USB.c +ramstage-y += LEGACY.c + +SB_CIMX_CFLAGS = +export CIMX_ROOT +export SB_CIMX_INC +export SB_CIMX_CFLAGS +CC := $(CC) $(SB_CIMX_CFLAGS) $(SB_CIMX_INC) + +####################################################################### + diff --git a/src/vendorcode/amd/cimx/sb700/OEM.h b/src/vendorcode/amd/cimx/sb700/OEM.h new file mode 100644 index 0000000..74604c0 --- /dev/null +++ b/src/vendorcode/amd/cimx/sb700/OEM.h @@ -0,0 +1,87 @@ +/*;******************************************************************************** +; +; Copyright (C) 2012 Advanced Micro Devices, Inc. +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; * Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; * Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution. +; * Neither the name of Advanced Micro Devices, Inc. nor the names of +; its contributors may be used to endorse or promote products derived +; from this software without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;*********************************************************************************/ +#ifndef _AMD_SB_CIMx_OEM_H_ +#define _AMD_SB_CIMx_OEM_H_ + +#define BIOS_SIZE 0x04 //04 - 1MB +#define LEGACY_FREE 0x00 + +/** + * PCIEX_BASE_ADDRESS - Define PCIE base address + * + * @param[Option] MOVE_PCIEBAR_TO_F0000000 Set PCIe base address to 0xF7000000 + */ +#ifdef MOVE_PCIEBAR_TO_F0000000 + #define PCIEX_BASE_ADDRESS 0xF7000000 +#else + #define PCIEX_BASE_ADDRESS 0xE0000000 +#endif + + +#define SMBUS0_BASE_ADDRESS 0xB00 +#define SMBUS1_BASE_ADDRESS 0xB20 +#define SIO_PME_BASE_ADDRESS 0xE00 +#define SPI_BASE_ADDRESS 0xFEC10000 + +#define WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0 // Watchdog Timer Base Address +#define HPET_BASE_ADDRESS 0xFED00000 // HPET Base address + +#define PM1_EVT_BLK_ADDRESS 0x800 // AcpiPm1EvtBlkAddr; +#define PM1_CNT_BLK_ADDRESS 0x804 // AcpiPm1CntBlkAddr; +#define PM1_TMR_BLK_ADDRESS 0x808 // AcpiPmTmrBlkAddr; +#define CPU_CNT_BLK_ADDRESS 0x810 // CpuControlBlkAddr; +#define GPE0_BLK_ADDRESS 0x820 // AcpiGpe0BlkAddr; +#define SMI_CMD_PORT 0xB0 // SmiCmdPortAddr; +#define ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 // AcpiPmaCntBlkAddr; + +#define EC_LDN5_MAILBOX_ADDRESS 0x550 +#define EC_LDN5_IRQ 0x05 +#define EC_LDN9_MAILBOX_ADDRESS 0x3E + +#define SATA_IDE_MODE_SSID 0x43901002 +#define SATA_RAID_MODE_SSID 0x43921002 +#define SATA_RAID5_MODE_SSID 0x43931002 +#define SATA_AHCI_SSID 0x43911002 +#define OHCI0_SSID 0x43971002 +#define OHCI1_SSID 0x43981002 +#define EHCI0_SSID 0x43961002 +#define OHCI2_SSID 0x43971002 +#define OHCI3_SSID 0x43981002 +#define EHCI1_SSID 0x43961002 +#define OHCI4_SSID 0x43991002 + +#define SMBUS_SSID 0x43851002 +#define IDE_SSID 0x439C1002 +#define AZALIA_SSID 0x43831002 +#define LPC_SSID 0x439D1002 +#define P2P_SSID 0x43841002 + +#define RESERVED_VALUE 0x00 + +#endif //ifndef _AMD_SB_CIMx_OEM_H_ diff --git a/src/vendorcode/amd/cimx/sb700/SATA.c b/src/vendorcode/amd/cimx/sb700/SATA.c new file mode 100644 index 0000000..09d4923 --- /dev/null +++ b/src/vendorcode/amd/cimx/sb700/SATA.c @@ -0,0 +1,453 @@ +/***************************************************************************** + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + ***************************************************************************/ + + +#include "Platform.h" + +//Table for class code of SATA Controller in different modes +UINT32 sataIfCodeTable[] = { + 0x01018f00, //sata class ID of IDE + 0x01040000, //sata class ID of RAID + 0x01060100, //sata class ID of AHCI + 0x01018a00, //sata class ID of Legacy IDE + 0x01018f00, //sata class ID of IDE to AHCI mode + 0x01060100, //sata class ID of AMD-AHCI mode + 0x01018f00 //sata class ID of IDE to AMD-AHCI mode +}; + +//Table for device id of SATA Controller in different modes +UINT16 sataDeviceIDTable[] = { + 0x4390, //sata device ID of IDE + 0x4392, //sata device ID of RAID + 0x4391, //sata class ID of AHCI + 0x4390, //sata device ID of Legacy IDE + 0x4390, //sata device ID of IDE->AHCI mode + 0x4394, //sata device ID for AMD-AHCI mode + 0x4390 //sata device ID of IDE->AMDAHCI mode +}; + + +void sataInitBeforePciEnum(AMDSBCFG* pConfig){ + UINT32 ddValue, *tempptr; + UINT16 *pDeviceIdptr, dwDeviceId; + UINT8 dbValue, dbOrMask, dbAndMask; + + + dbAndMask=0; + dbOrMask=0; + // Enable/Disable Combined mode & do primary/secondary selections, enable/disable + if (pConfig->SataIdeCombinedMode == CIMX_OPTION_DISABLED) dbAndMask= BIT3; //Clear BIT3 + if (pConfig->SataIdeCombMdPriSecOpt == 1) dbOrMask = BIT4; //Set BIT4 + if (pConfig->SataSmbus == 0) dbOrMask = BIT1; + + RWPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGAD), AccWidthUint8 | S3_SAVE, ~(dbAndMask), dbOrMask); + + if (pConfig->SataController == 0){ + // SATA Controller Disabled & set Power Saving mode to disabled + RWPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGAD), AccWidthUint8 | S3_SAVE, ~(UINT32)BIT0, BIT1); + return; + } + + restrictSataCapabilities(pConfig); + + // Get the appropriate class code from the table and write it to PCI register 08h-0Bh + // Set the appropriate SATA class based on the input parameters + dbValue=pConfig->SataClass; + tempptr= (UINT32 *) FIXUP_PTR (&sataIfCodeTable[0]); + ddValue=tempptr[dbValue]; + + // BIT0: Enable write access to PCI header (reg 08h-0Bh) by setting SATA PCI register 40h, bit 0 + // BIT4:disable fast boot + RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, 0xff, BIT4+BIT0); + + // Write the class code to SATA PCI register 08h-0Bh + RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG08), AccWidthUint32 | S3_SAVE, 0, ddValue); + + if (pConfig->SataClass == LEGACY_IDE_MODE) //SATA = Legacy IDE + //Set PATA controller to native mode + RWPCI(((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG09), AccWidthUint8 | S3_SAVE, 0x00, 0x08F); + + //Change the appropriate device id + if (pConfig->SataClass == AMD_AHCI_MODE) { + RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 3), AccWidthUint8 | S3_SAVE, 0xff, BIT0); + } + pDeviceIdptr= (UINT16 *) FIXUP_PTR (&sataDeviceIDTable[0]); + + ReadPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG02), AccWidthUint16 | S3_SAVE, &dwDeviceId); + if ( !((dwDeviceId==SB750_SATA_DEFAULT_DEVICE_ID) && (pConfig->SataClass == RAID_MODE)) ){ + //if not (SB750 & RAID mode), then program the device id + dwDeviceId=pDeviceIdptr[dbValue]; + RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG02), AccWidthUint16 | S3_SAVE, 0, dwDeviceId); + } + + if (pConfig->AcpiS1Supported) + RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG34), AccWidthUint8 | S3_SAVE, 00, 0x70);//Disable SATA PM & MSI capability + else + RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG60+1), AccWidthUint8 | S3_SAVE, 00, 0x70);//Disable SATA MSI capability + + if (getRevisionID() >= SB700_A13){ + //Enable test/enhancement mode for A13 + RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40+3), AccWidthUint8 | S3_SAVE, ~(UINT32)BIT5, 00); + RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG48), AccWidthUint32 | S3_SAVE, ~(UINT32)(BIT24+BIT21), 0xBF80); + } + + if (getRevisionID() >= SB700_A14){ + //Fix for TT SB01352 - LED Stays On When ODD Attached To Slave Port In IDE Mode + RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG48), AccWidthUint8 | S3_SAVE, 0xFF, BIT6); + } + + // Disable write access to PCI header + RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, ~(UINT32)BIT0, 0); + + // RPR 6.5 SATA PHY Programming Sequence + RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG86, AccWidthUint16 | S3_SAVE, 0x00, 0x2C00); + RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG88, AccWidthUint32 | S3_SAVE, 0x00, 0x01B48016); + RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG8C, AccWidthUint32 | S3_SAVE, 0x00, 0x01B48016); + RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG90, AccWidthUint32 | S3_SAVE, 0x00, 0x01B48016); + RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG94, AccWidthUint32 | S3_SAVE, 0x00, 0x01B48016); + RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG98, AccWidthUint32 | S3_SAVE, 0x00, 0x01B48016); + RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG9C, AccWidthUint32 | S3_SAVE, 0x00, 0x01B48016); + RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REGA0, AccWidthUint32 | S3_SAVE, 0x00, 0xA07AA07A); + RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REGA4, AccWidthUint32 | S3_SAVE, 0x00, 0xA07AA07A); + RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REGA8, AccWidthUint32 | S3_SAVE, 0x00, 0xA07AA07A); + + CallBackToOEM(SATA_PHY_PROGRAMMING, NULL, pConfig); +} + +void sataInitAfterPciEnum(AMDSBCFG* pConfig){ + UINT32 ddAndMask=0, ddOrMask=0, ddBar5=0; + UINT8 dbVar, dbPortNum; + + if (pConfig->SataController == 0) return; //return if SATA controller is disabled. + + //Enable write access to pci header, pm capabilities + RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, 0xFF, BIT0); + + //Disable AHCI enhancement function (RPR 7.2) + RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 2), AccWidthUint8 | S3_SAVE, 0xFF, BIT7); + + restrictSataCapabilities(pConfig); + + ReadPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG24), AccWidthUint32, &ddBar5); + + if ( (ddBar5 == 0) || (ddBar5 == -1) ) { + //assign temporary BAR5 + if ( (pConfig->TempMMIO == 0) || (pConfig->TempMMIO == -1)) + ddBar5 = 0xFEC01000; + else + ddBar5=pConfig->TempMMIO; + + WritePCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG24), AccWidthUint32, &ddBar5); + } + + ReadPCI( ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, &dbVar); + RWPCI( ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8,0xFF, 0x03); //memory and io access enable + + ddBar5 &= 0xFFFFFC00; //Clear Bits 9:0 + if (!pConfig->SataPortMultCap) + ddAndMask |= BIT12; + if (!pConfig->SataAggrLinkPmCap) + ddAndMask |= BIT11; + if (pConfig->SataSscPscCap) + ddOrMask |= BIT1; + + RWMEM((ddBar5 + SB_SATA_BAR5_REGFC),AccWidthUint32 | S3_SAVE, ~ddAndMask, ddOrMask); + + + //Clear HPCP and ESP by default + RWMEM((ddBar5 + SB_SATA_BAR5_REGF8),AccWidthUint32 | S3_SAVE, 0xFFFC0FC0, 0); + + if (pConfig->SataHpcpButNonESP !=0) { + RWMEM((ddBar5 + SB_SATA_BAR5_REGF8),AccWidthUint32 | S3_SAVE, 0xFFFFFFC0, pConfig->SataHpcpButNonESP); + } + + // SATA ESP port setting + // These config bits are set for SATA driver to identify which ports are external SATA ports and need to + // support hotplug. If a port is set as an external SATA port and need to support hotplug, then driver will + // not enable power management(HIPM & DIPM) for these ports. + if (pConfig->SataEspPort !=0) { + RWMEM((ddBar5 + SB_SATA_BAR5_REGFC),AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, BIT20); + RWMEM((ddBar5 + SB_SATA_BAR5_REGF8),AccWidthUint32 | S3_SAVE, ~(pConfig->SataEspPort), 0); + RWMEM((ddBar5 + SB_SATA_BAR5_REGF8),AccWidthUint32 | S3_SAVE, ~(UINT32)(BIT17+BIT16+BIT15+BIT14+BIT13+BIT12),(pConfig->SataEspPort << 12)); + } + + if ( ((pConfig->SataClass) != NATIVE_IDE_MODE) && ((pConfig->SataClass) != LEGACY_IDE_MODE) ) + RWPCI( ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG50+2), AccWidthUint8, ~(UINT32)(BIT3+BIT2+BIT1), BIT2+BIT1); //set MSI to 8 messages + + if ( ((pConfig->SataClass) != NATIVE_IDE_MODE) && ((pConfig->SataClass) != LEGACY_IDE_MODE) && ((pConfig->SataIdeCombinedMode) == CIMX_OPTION_DISABLED) ){ + RWMEM((ddBar5 + SB_SATA_BAR5_REG00),AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT2+BIT1+BIT0), BIT2+BIT0); + RWMEM((ddBar5 + SB_SATA_BAR5_REG0C),AccWidthUint8 | S3_SAVE, 0xC0, 0x3F); + } + + for (dbPortNum=0;dbPortNum<=5;dbPortNum++){ + if (pConfig->SataPortMode & (1 << dbPortNum)){ + //downgrade to GEN1 + RWMEM(ddBar5+ SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0x0F, 0x10); + RWMEM(ddBar5+ SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0xFF, 0x01); + Stall(1000); + RWMEM(ddBar5+ SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0xFE, 0x00); + } + } + + //If this is not S3 resume and also if SATA set to one of IDE mode, then implement drive detection workaround. + if ( !(pConfig->S3Resume) && ( ((pConfig->SataClass) != AHCI_MODE) && ((pConfig->SataClass) != RAID_MODE) && ((pConfig->SataClass) != AMD_AHCI_MODE) ) ) + sataDriveDetection(pConfig, ddBar5); + + if ( (pConfig->SataPhyWorkaround==1) || ( (pConfig->SataPhyWorkaround==0) && (getRevisionID() < SB700_A13)) ) + sataPhyWorkaround(pConfig, ddBar5); + + // Set the handshake bit for IDE driver to detect the disabled IDE channel correctly. + // Set IDE PCI Config 0x63 [3] if primary channel disabled, [4] if secondary channel disabled. + if (pConfig->SataIdeCombinedMode == CIMX_OPTION_DISABLED) + RWPCI( ((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG63), AccWidthUint8 , 0xF9, (0x02 << (pConfig->SataIdeCombMdPriSecOpt)) ); + + WritePCI( ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, &dbVar); + + //Disable write access to pci header, pm capabilities + RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, ~(UINT32)BIT0, 0); +} + + +void sataDriveDetection(AMDSBCFG* pConfig, UINT32 ddBar5){ + UINT32 ddVar0; + UINT8 dbPortNum, dbVar0; + UINT16 dwIoBase, dwVar0; + + TRACE((DMSG_SB_TRACE, "CIMx - Entering sata drive detection procedure\n\n")); + TRACE((DMSG_SB_TRACE, "SATA BAR5 is %X \n", ddBar5)); + + if ( (pConfig->SataClass == NATIVE_IDE_MODE) || (pConfig->SataClass == LEGACY_IDE_MODE) || (pConfig->SataClass == IDE_TO_AHCI_MODE) || (pConfig->SataClass == IDE_TO_AMD_AHCI_MODE) ){ + for (dbPortNum=0;dbPortNum<4;dbPortNum++){ + ReadMEM(ddBar5+ SB_SATA_BAR5_REG128 + dbPortNum * 0x80, AccWidthUint32, &ddVar0); + if ( ( ddVar0 & 0x0F ) == 0x03){ + if ( dbPortNum & BIT0) + //this port belongs to secondary channel + ReadPCI( ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG18), AccWidthUint16, &dwIoBase); + else + //this port belongs to primary channel + ReadPCI( ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG10), AccWidthUint16, &dwIoBase); + + //if legacy ide mode, then the bar registers don't contain the correct values. So we need to hardcode them + if (pConfig->SataClass == LEGACY_IDE_MODE) + dwIoBase = ( (0x170) | ( (~((dbPortNum & BIT0) << 7)) & 0x80 ) ); + + if ( dbPortNum & BIT1) + //this port is slave + dbVar0=0xB0; + else + //this port is master + dbVar0=0xA0; + dwIoBase &= 0xFFF8; + WriteIO(dwIoBase+6, AccWidthUint8, &dbVar0); + + //Wait in loop for 30s for the drive to become ready + for (dwVar0=0;dwVar0<3000;dwVar0++){ + ReadIO(dwIoBase+7, AccWidthUint8, &dbVar0); + if ( (dbVar0 & 0x88) == 0) + break; + Stall(10000); + } + } //end of if ( ( ddVar0 & 0x0F ) == 0x03) + } //for (dbPortNum=0;dbPortNum<4;dbPortNum++) + } //if ( (pConfig->SataClass == NATIVE_IDE_MODE) || (pConfig->SataClass == LEGACY_IDE_MODE) || (pConfig->SataClass == IDE_TO_AHCI_MODE) || (pConfig->SataClass == IDE_TO_AMD_AHCI_MODE) ) +} + + +//This patch is to workaround the SATA PHY logic hardware issue in the SB700. +//Internally this workaround is called as 7NewA +void sataPhyWorkaround(AMDSBCFG* pConfig, UINT32 ddBar5){ + + UINT8 dbPortNum, dbVar0; + + if (pConfig->Gen1DeviceShutdownDuringPhyWrknd == 0x01){ + for (dbPortNum=0;dbPortNum<=5;dbPortNum++){ + ReadMEM(ddBar5+ SB_SATA_BAR5_REG128 + dbPortNum * 0x80, AccWidthUint8, &dbVar0); + if ( (dbVar0 & 0xF0) == 0x10){ + RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40+2, AccWidthUint8 | S3_SAVE, 0xFF, (01 << dbPortNum)); + } + + } + } + + RWPMIO(SB_PMIO_REGD0, AccWidthUint8, ~(UINT32)(BIT4+BIT3), BIT4+BIT3);//set PMIO_D0[4:3] = 11b // this is to tell SATA PHY to use the internal 100MHz clock + RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG86, AccWidthUint8 | S3_SAVE, 0x00, 0x40);// set SATA PCI_CFG 0x86[7:0] = 0x40 //after the reset is done, perform this to turn on the diff clock path into SATA PHY + Stall(2000);// Wait for 2ms + RWPMIO(SB_PMIO_REGD0, AccWidthUint8, ~(UINT32)(BIT4+BIT3), 00);//13. set PMIO_D0[4:3] = 00b + Stall(20000);// Wait 20ms + forceOOB(ddBar5);// Force OOB + + RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40+2, AccWidthUint8 | S3_SAVE, ~(0x03F), 00); +} + + +void forceOOB(UINT32 ddBar5){ + UINT8 dbPortNum; + for (dbPortNum=0;dbPortNum<=5;dbPortNum++) + RWMEM(ddBar5+ SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0xFF, 0x01); + Stall(2000); + for (dbPortNum=0;dbPortNum<=5;dbPortNum++) + RWMEM(ddBar5+ SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0xFE, 0x00); + Stall(2000);// Wait for 2ms +} + +/*++ + +Routine Description: + + SATA Late Configuration + + if the mode is selected as IDE->AHCI + { 1. Set class ID to AHCI + 2. Enable AHCI interrupt + } + +Arguments: + + pConfig - SBconfiguration + +Returns: + + void + +--*/ +void sataInitLatePost(AMDSBCFG* pConfig){ + UINT32 ddBar5; + UINT8 dbVar; + + //Return immediately is sata controller is not enabled + if (pConfig->SataController == 0) return; + + restrictSataCapabilities(pConfig); + + //Get BAR5 value + ReadPCI( ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG24), AccWidthUint32, &ddBar5); + + //Assign temporary BAR if is not already assigned + if ( (ddBar5 == 0) || (ddBar5 == -1) ){ + //assign temporary BAR5 + if ( (pConfig->TempMMIO == 0) || (pConfig->TempMMIO == -1)) + ddBar5 = 0xFEC01000; + else + ddBar5=pConfig->TempMMIO; + WritePCI( ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG24), AccWidthUint32, &ddBar5); + } + + ReadPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, &dbVar); + //Enable memory and io access + RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, 0xFF, 0x03); + //Enable write access to pci header, pm capabilities + RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, 0xff, BIT0); + + shutdownUnconnectedSataPortClock(pConfig, ddBar5); + + if ( (pConfig->SataClass == IDE_TO_AHCI_MODE) || (pConfig->SataClass == IDE_TO_AMD_AHCI_MODE)){ + //program the AHCI class code + RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG08), AccWidthUint32 | S3_SAVE, 0, 0x01060100); + //Set interrupt enable bit + RWMEM((ddBar5 + 0x04),AccWidthUint8,~(UINT32)0,BIT1); + //program the correct device id for AHCI mode + RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG02), AccWidthUint16 | S3_SAVE, 0, 0x4391); + + if (pConfig->SataClass == IDE_TO_AMD_AHCI_MODE) + //program the correct device id for AMD-AHCI mode + RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 3), AccWidthUint8 | S3_SAVE, 0xFF, BIT0); + } + + //Disable write access to pci header and pm capabilities + RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, ~(UINT32)BIT0, 0); + //Clear error status + RWMEM((ddBar5 + SB_SATA_BAR5_REG130),AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF); + RWMEM((ddBar5 + SB_SATA_BAR5_REG1B0),AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF); + RWMEM((ddBar5 + SB_SATA_BAR5_REG230),AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF); + RWMEM((ddBar5 + SB_SATA_BAR5_REG2B0),AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF); + //Restore memory and io access bits + WritePCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, &dbVar ); +} + + +void shutdownUnconnectedSataPortClock(AMDSBCFG* pConfig, UINT32 ddBar5){ + UINT8 dbPortNum, dbPortSataStatus, NumOfPorts=0; + UINT8 UnusedPortBitMap; + UINT8 SataType; + UINT8 ClockOffEnabled ; + + UnusedPortBitMap = 0; + + // First scan for all unused SATA ports + for (dbPortNum = 5; dbPortNum <= 5; dbPortNum--) { + ReadMEM (ddBar5 + SB_SATA_BAR5_REG128 + (dbPortNum * 0x80), AccWidthUint8, &dbPortSataStatus); + if ((!(dbPortSataStatus & 0x01)) && (!((pConfig->SataEspPort) & (1 << dbPortNum)))) { + UnusedPortBitMap |= (1 << dbPortNum); + } + } + + // Decide if we need to shutdown the clock for all unused ports + SataType = pConfig->SataClass; + ClockOffEnabled = (pConfig->SataClkAutoOff && ((SataType == NATIVE_IDE_MODE) || (SataType == LEGACY_IDE_MODE) || \ + (SataType == IDE_TO_AHCI_MODE) || (SataType == IDE_TO_AMD_AHCI_MODE))) || \ + (pConfig->SataClkAutoOffAhciMode && ((SataType == AHCI_MODE) || (SataType == AMD_AHCI_MODE))); + + if (ClockOffEnabled) { + //Shutdown the clock for the port and do the necessary port reporting changes. + TRACE((DMSG_SB_TRACE, "Shutting down clock for SATA ports %X \n", UnusedPortBitMap)); + RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 2), AccWidthUint8, 0xFF, UnusedPortBitMap); + RWMEM(ddBar5 + SB_SATA_BAR5_REG0C, AccWidthUint8, ~UnusedPortBitMap, 00); + } + + // If all ports are in disabled state, report at least one + ReadMEM (ddBar5 + SB_SATA_BAR5_REG0C, AccWidthUint8, &dbPortSataStatus); + if ( (dbPortSataStatus & 0x3F) == 0) { + dbPortSataStatus = 1; + RWMEM (ddBar5 + SB_SATA_BAR5_REG0C, AccWidthUint8, ~(0x3F), dbPortSataStatus); + } + + // Decide if we need to hide unused ports from being seen by OS (this saves OS startup time) + if (pConfig->SataHideUnusedPort && ClockOffEnabled) { + dbPortSataStatus &= ~UnusedPortBitMap; // Mask off unused ports + for (dbPortNum = 0; dbPortNum <= 6; dbPortNum++) { + if (dbPortSataStatus & (1 << dbPortNum)) + NumOfPorts++; + } + if (NumOfPorts == 0 ) { + NumOfPorts = 0x01; + } + RWMEM (ddBar5 + SB_SATA_BAR5_REG00, AccWidthUint8, 0xE0, NumOfPorts - 1); + } +} + + +void restrictSataCapabilities(AMDSBCFG* pConfig){ + //Restrict capabilities + if ( ((getSbCapability(Sb_Raid0_1_Capability)== 0x02) && (pConfig->SataClass == RAID_MODE)) || \ + ((getSbCapability(Sb_Raid5_Capability)== 0x02) && (pConfig->SataClass == RAID_MODE)) || \ + ((getSbCapability(Sb_Ahci_Capability)== 0x02) && ((pConfig->SataClass == AHCI_MODE) || (pConfig->SataClass == IDE_TO_AHCI_MODE)))){ + pConfig->SataClass = NATIVE_IDE_MODE; + } +} diff --git a/src/vendorcode/amd/cimx/sb700/SB700.h b/src/vendorcode/amd/cimx/sb700/SB700.h new file mode 100644 index 0000000..f9e71e8 --- /dev/null +++ b/src/vendorcode/amd/cimx/sb700/SB700.h @@ -0,0 +1,1028 @@ +/*;******************************************************************************** +; +; Copyright (C) 2012 Advanced Micro Devices, Inc. +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; * Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; * Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution. +; * Neither the name of Advanced Micro Devices, Inc. nor the names of +; its contributors may be used to endorse or promote products derived +; from this software without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;*********************************************************************************/ + +#ifndef _AMD_SB700_H_ +#define _AMD_SB700_H_ + +#pragma pack(push,1) + +#define CIMx_Version 0x0660 +#define RC_Information 0x00 +#define Additional_Changes_Indicator 0x00 + +#define SB_POWERON_INIT 0x001 +#define OUTDEBUG_PORT 0x002 +#define SB_BEFORE_PCI_INIT 0x010 +#define SB_AFTER_PCI_INIT 0x020 +#define SB_LATE_POST_INIT 0x030 +#define SB_BEFORE_PCI_RESTORE_INIT 0x040 +#define SB_AFTER_PCI_RESTORE_INIT 0x050 +#define SB_SMM_SERVICE 0x060 +#define SB_SMM_ACPION 0x061 + +#ifndef OEM_CALLBACK_BASE + #define OEM_CALLBACK_BASE 0x100 +#endif + +//0x00 - 0x0F callback functions are reserved for bootblock +#define SATA_PHY_PROGRAMMING OEM_CALLBACK_BASE + 0x10 +#define PULL_UP_PULL_DOWN_SETTINGS OEM_CALLBACK_BASE + 0x20 + +#define CFG_ADDR_PORT 0xCF8 +#define CFG_DATA_PORT 0xCFC +#define ATI_AZALIA_ExtBlk_Addr 0x0F8 +#define ATI_AZALIA_ExtBlk_DATA 0x0FC + +#define ALINK_ACCESS_INDEX 0x0CD8 +#define ALINK_ACCESS_DATA ALINK_ACCESS_INDEX + 4 + +/*------------------------------------------------------------------ +; I/O Base Address - Should be set by host BIOS +;------------------------------------------------------------------ */ +#define DELAY_PORT 0x0E0 + +/*------------------------------------------------------------------ +; DEBUG_PORT = 8-bit I/O Port Address for POST Code Display +;------------------------------------------------------------------ */ +#define SB7XX_DEVICE_ID 0x4385 + +#define SB700_A11 0x39 +#define SB700_A12 0x3A +#define SB700_A13 0x3B +#define SB700_A14 0x3C +#define SB700_A15 0x3D + +#define SATA_BUS_DEV_FUN ((0x11 << 3) + 0) +#define FC_BUS_DEV_FUN ((0x11 << 3) + 1) +#define USB1_OHCI0_BUS_DEV_FUN ((0x12 << 3) + 0) +#define USB1_OHCI1_BUS_DEV_FUN ((0x12 << 3) + 1) +#define USB2_OHCI0_BUS_DEV_FUN ((0x13 << 3) + 0) +#define USB2_OHCI1_BUS_DEV_FUN ((0x13 << 3) + 1) +#define USB3_OHCI_BUS_DEV_FUN ((0x14 << 3) + 5) +#define USB1_EHCI_BUS_DEV_FUN ((0x12 << 3) + 2) +#define USB2_EHCI_BUS_DEV_FUN ((0x13 << 3) + 2) + +#define SMBUS_BUS_DEV_FUN ((0x14 << 3) + 0) +#define IDE_BUS_DEV_FUN ((0x14 << 3) + 1) +#define AZALIA_BUS_DEV_FUN ((0x14 << 3) + 2) +#define LPC_BUS_DEV_FUN ((0x14 << 3) + 3) +#define SBP2P_BUS_DEV_FUN ((0x14 << 3) + 4) +#define NB_BDF ((0 << 3) + 0) +#define HT_LINK_BUS_DEV_FUN ((0x18 << 3) + 0) +#define DCT1_BUS_DEV_FUN ((0x18 << 3) + 2) +#define DCT2_BUS_DEV_FUN ((0x19 << 3) + 2) +#define DCT3_BUS_DEV_FUN ((0x1A << 3) + 2) +#define DCT4_BUS_DEV_FUN ((0x1B << 3) + 2) + + +//Sata Controller Mode +#define NATIVE_IDE_MODE 0 +#define RAID_MODE 1 +#define AHCI_MODE 2 +#define LEGACY_IDE_MODE 3 +#define IDE_TO_AHCI_MODE 4 +#define AMD_AHCI_MODE 5 +#define IDE_TO_AMD_AHCI_MODE 6 + +//Sata Port Configuration +#define SIX_PORTS 0 +#define FOUR_PORTS 1 + +#define SB750_SATA_DEFAULT_DEVICE_ID 0x4393 + +#define SB_AX_INDXC_REG30 0x30 +#define SB_AX_DATAC_REG34 0x34 +#define SB_AX_INDXP_REG38 0x38 +#define SB_AX_DATAP_REG3C 0x3C + +#define AX_INDXC 0 +#define AX_INDXP 1 +#define AXCFG 2 +#define ABCFG 3 + +#define SB_AB_REG02 0x02 +#define SB_AB_REG04 0x04 +#define SB_AB_REG40 0x40 // +#define SB_AB_REG54 0x54 //;miscCtr54 +#define SB_AB_REG58 0x58 //;RAB Control - RW - 32 bits - [RegAddr:58] +#define SB_AB_REG60 0x60 //;DMA Prefetch Enable Port 0 - RW - 32 bits - [RegAddr:60] +#define SB_AB_REG64 0x64 //;DMA Prefetch Flush Port 0 - RW - 32 bits - [RegAddr:64] +#define SB_AB_REG6C 0x6C //;DMA Prefetch Flush Port 0 - RW - 32 bits - [RegAddr:6C] +#define SB_AB_REG80 0x80 //;DMA Prefetch Control Port 1 - RW - 32 bits - [RegAddr:80] +#define SB_AB_REG88 0x88 //;DMA Prefetch Control Port 2 - RW - 32 bits - [RegAddr:88] +#define SB_AB_REG8C 0x8C //;AB Enhancement - RW - 16 bits - [RegAddr:88] +#define SB_AB_REG90 0x90 //;BIF Control - RW - 32 bits - [RegAddr:90] +#define SB_AB_REG94 0x94 //;MSI Control - RW - 32 bits +#define SB_AB_REG98 0x98 //;BIF Control 1 - RW - 32 bits +#define SB_AB_REG9C 0x9C //; +#define SB_AB_REG10050 BIT16+0x50 +#define SB_AB_REG10054 BIT16+0x54 //;AL_Arb_Ctl, AL_Clk_Ctl +#define SB_AB_REG10060 BIT16+0x60 //;DMA Prefetch Enable Port 0 - RW - 32 bits - [RegAddr:10060] +#define SB_AB_REG10064 BIT16+0x64 //;DMA Prefetch Flush Port 0 - RW - 32 bits - [RegAddr:64] +#define SB_AB_REG10090 BIT16+0x90 //; +#define SB_AB_REG1009C BIT16+0x9C //; + + +#define SB_PMIO_REG00 0x000 // MiscControl +#define SB_PMIO_REG01 0x001 // MiscStatus +#define SB_PMIO_REG02 0x002 // SmiWakeUpEventEnable1 +#define SB_PMIO_REG03 0x003 // SmiWakeUpEventEnable2 +#define SB_PMIO_REG04 0x004 // SmiWakeUpEventEnable3 +#define SB_PMIO_REG05 0x005 // SmiWakeUpEventStatus1 +#define SB_PMIO_REG06 0x006 // SmiWakeUpEventStatus2 +#define SB_PMIO_REG07 0x007 // SmiWakeUpEventStatus3 +#define SB_PMIO_REG08 0x008 // InactiveTmrEventEnable1 +#define SB_PMIO_REG09 0x009 // InactiveTmrEventEnable2 +#define SB_PMIO_REG0A 0x00A // InactiveTmrEventEnable3 +#define SB_PMIO_REG0B 0x00B // PmTmr1InitValue +#define SB_PMIO_REG0C 0x00C // PmTmr1CurValue +#define SB_PMIO_REG0D 0x00D // PwrLedExtEvent +#define SB_PMIO_REG0E 0x00E // AcpiControl +#define SB_PMIO_REG0F 0x00F // AcpiStatus +#define SB_PMIO_REG10 0x010 // AcpiEn +#define SB_PMIO_REG11 0x011 // S1AgpStpEn +#define SB_PMIO_REG12 0x012 // PmTmr2InitValue +#define SB_PMIO_REG13 0x013 // PmTmr2CurValue +#define SB_PMIO_REG14 0x014 // Programlo0RangeLo +#define SB_PMIO_REG15 0x015 // ProgramIo0Rangei +#define SB_PMIO_REG16 0x016 // ProgramIo1RangeLo +#define SB_PMIO_REG17 0x017 // ProgramIo1Rangei +#define SB_PMIO_REG18 0x018 // ProgramIo2RangeLo +#define SB_PMIO_REG19 0x019 // ProgramIo2Rangei +#define SB_PMIO_REG1A 0x01A // ProgramIo3RangeLo +#define SB_PMIO_REG1B 0x01B // ProgramIo3Rangei +#define SB_PMIO_REG1C 0x01C // ProgramIoEnable +#define SB_PMIO_REG1D 0x01D // IOMonitorStatus +#define SB_PMIO_REG1E 0x01E // InactiveTmrEventEnable4 +#define SB_PMIO_REG20 0x020 // AcpiPm1EvtBlkLo +#define SB_PMIO_REG21 0x021 // AcpiPm1EvtBlki +#define SB_PMIO_REG22 0x022 // AcpiPm1CntBlkLo +#define SB_PMIO_REG23 0x023 // AcpiPm1CntBlki +#define SB_PMIO_REG24 0x024 // AcpiPmTmrBlkLo +#define SB_PMIO_REG25 0x025 // AcpiPmTmrBlki +#define SB_PMIO_REG26 0x026 // CpuControlLo +#define SB_PMIO_REG27 0x027 // CpuControli +#define SB_PMIO_REG28 0x028 // AcpiGpe0BlkLo +#define SB_PMIO_REG29 0x029 // AcpiGpe0Blki +#define SB_PMIO_REG2A 0x02A // AcpiSmiCmdLo +#define SB_PMIO_REG2B 0x02B // AcpiSmiCmdi +#define SB_PMIO_REG2C 0x02C // AcpiPmaCntBlkLo +#define SB_PMIO_REG2D 0x02D // AcpiPmaCntBlki +#define SB_PMIO_REG2E 0x02E // AcpiSsCntBlkLo +#define SB_PMIO_REG2F 0x02F // AcpiSsCntBlki +#define SB_PMIO_REG30 0x030 // GEvtConfig0 +#define SB_PMIO_REG31 0x031 // GEvtConfig1 +#define SB_PMIO_REG32 0x032 // GPMConfig0 +#define SB_PMIO_REG33 0x033 // GPMConfig1 +#define SB_PMIO_REG34 0x034 // GPMConfig2 +#define SB_PMIO_REG35 0x035 // GPMConfig3 +#define SB_PMIO_REG36 0x036 // GEvtLevelConfig +#define SB_PMIO_REG37 0x037 // GPMLevelConfig0 +#define SB_PMIO_REG38 0x038 // GPMLevelConfig1 +#define SB_PMIO_REG39 0x039 // GEvtStatus +#define SB_PMIO_REG3A 0x03A // PMEStatus0 +#define SB_PMIO_REG3B 0x03B // PMEStatus1 +#define SB_PMIO_REG3C 0x03C // OtersConfig +#define SB_PMIO_REG3E 0x03E // VRT_T1 +#define SB_PMIO_REG3F 0x03F // VRT_T2 +#define SB_PMIO_REG40 0x040 // Fan0DutyCycle +#define SB_PMIO_REG41 0x041 // Fan0Control +#define SB_PMIO_REG42 0x042 // Fan1DutyCycle +#define SB_PMIO_REG43 0x043 // Reserved for internal use +#define SB_PMIO_REG50 0x050 // PM_Enable +#define SB_PMIO_REG51 0x051 // TPRESET1 +#define SB_PMIO_REG52 0x052 // TPRESET2 +#define SB_PMIO_REG53 0x053 // TESTENABLE +#define SB_PMIO_REG54 0x054 // PWRBTTN_CLR +#define SB_PMIO_REG55 0x055 // SoftPciRst +#define SB_PMIO_REG56 0x056 // Reserved +#define SB_PMIO_REG59 0x059 // Ac97Mask +#define SB_PMIO_REG60 0x060 // Options_0 +#define SB_PMIO_REG61 0x061 // Options_1 +#define SB_PMIO_REG62 0x062 // Sadow_SCI +#define SB_PMIO_REG63 0x063 // SwitcVoltageTime +#define SB_PMIO_REG64 0x064 // SwitchGI_Time +#define SB_PMIO_REG65 0x065 // UsbPMControl +#define SB_PMIO_REG66 0x066 // MiscEnable66 +#define SB_PMIO_REG67 0x067 // MiscEnable67 +#define SB_PMIO_REG68 0x068 // MiscEnable68 +#define SB_PMIO_REG69 0x069 // WatcDogTimerControl +#define SB_PMIO_REG6C 0x06C // WatcDogTimerBase0 +#define SB_PMIO_REG6D 0x06D // WatcDogTimerBase1 +#define SB_PMIO_REG6E 0x06E // WatcDogTimerBase2 +#define SB_PMIO_REG6F 0x06F // WatcDogTimerBase3 +#define SB_PMIO_REG70 0x070 // S_LdtStartTime +#define SB_PMIO_REG71 0x071 // FidVidOption +#define SB_PMIO_REG72 0x072 // Spare4 +#define SB_PMIO_REG73 0x073 // Spare5 +#define SB_PMIO_REG74 0x074 // PwrFailSadow +#define SB_PMIO_REG75 0x075 // Tpreset1b +#define SB_PMIO_REG76 0x076 // S0S3ToS5Enable0 +#define SB_PMIO_REG77 0x077 // S0S3ToS5Enable1 +#define SB_PMIO_REG78 0x078 // S0S3ToS5Enable2 +#define SB_PMIO_REG79 0x079 // S0S3ToS5Enable3 +#define SB_PMIO_REG7A 0x07A // NoStatusControl0 +#define SB_PMIO_REG7B 0x07B // NoStatusControl1 +#define SB_PMIO_REG7C 0x07C // MiscEnable7C +#define SB_PMIO_REG80 0x080 // SMAF0 +#define SB_PMIO_REG81 0x081 // SMAF1 +#define SB_PMIO_REG82 0x082 // SMAF2 +#define SB_PMIO_REG83 0x083 // SMAF3 +#define SB_PMIO_REG84 0x084 // WakePinCntl +#define SB_PMIO_REG85 0x085 // CF9Rst +#define SB_PMIO_REG86 0x086 // ThermTrotCntl +#define SB_PMIO_REG87 0x087 // LdtStpCmd +#define SB_PMIO_REG88 0x088 // LdtStartTime +#define SB_PMIO_REG89 0x089 // AgpStartTime +#define SB_PMIO_REG8A 0x08A // LdtAgpTimeCntl +#define SB_PMIO_REG8B 0x08B // StutterTime +#define SB_PMIO_REG8C 0x08C // StpClkDlyTime +#define SB_PMIO_REG8D 0x08D // AbPmeCntl +#define SB_PMIO_REG8E 0x08E // FakeAsr +#define SB_PMIO_REG8F 0x08F // FakeAsrEn +#define SB_PMIO_REG90 0x090 // GEVENTOUT +#define SB_PMIO_REG91 0x091 // GEVENTEnable +#define SB_PMIO_REG92 0x092 // GEVENTIN +#define SB_PMIO_REG95 0x095 // GPM98EN +#define SB_PMIO_REG9A 0x09A // EnanceControl +#define SB_PMIO_REG9E 0x09E // EnanceControl +#define SB_PMIO_REG9F 0x09F // EnanceControl +#define SB_PMIO_REGA0 0x0A0 // Programlo4RangeLo +#define SB_PMIO_REGA1 0x0A1 // ProgramIo4Rangei +#define SB_PMIO_REGA2 0x0A2 // Programlo5RangeLo +#define SB_PMIO_REGA3 0x0A3 // ProgramIo5Rangei +#define SB_PMIO_REGA4 0x0A4 // Programlo6RangeLo +#define SB_PMIO_REGA5 0x0A5 // ProgramIo6Rangei +#define SB_PMIO_REGA6 0x0A6 // Programlo7RangeLo +#define SB_PMIO_REGA7 0x0A7 // ProgramIo7Rangei +#define SB_PMIO_REGA8 0x0A8 // PIO7654Enable +#define SB_PMIO_REGA9 0x0A9 // PIO7654Status +#define SB_PMIO_REGB0 0x0B0 +#define SB_PMIO_REGB1 0x0B1 +#define SB_PMIO_REGB2 0x0B2 // MiscControl3 +#define SB_PMIO_REGB4 0x0B4 // HPET BAR +#define SB_PMIO_REGB6 0x0B6 +#define SB_PMIO_REGB7 0x0B7 +#define SB_PMIO_REGBB 0x0BB // IMC_ACPI_Enable +#define SB_PMIO_REGBC 0x0BC // +#define SB_PMIO_REGBD 0x0BD // +#define SB_PMIO_REGC9 0x0C9 // MultiK8Control +#define SB_PMIO_REGCA 0x0CA // +#define SB_PMIO_REGCB 0x0CB // +#define SB_PMIO_REGCC 0x0CC // +#define SB_PMIO_REGCD 0x0CD // +#define SB_PMIO_REGD0 0x0D0 // +#define SB_PMIO_REGD2 0x0D2 // +#define SB_PMIO_REGD4 0x0D4 // +#define SB_PMIO_REGD7 0x0D7 // + + +#define SB_RTC_REG00 0x00 // Seconds - RW +#define SB_RTC_REG01 0x01 // Seconds Alarm - RW +#define SB_RTC_REG02 0x02 // Minutes - RW +#define SB_RTC_REG03 0x03 // Minutes Alarm - RW +#define SB_RTC_REG04 0x04 // ours - RW +#define SB_RTC_REG05 0x05 // ours Alarm- RW +#define SB_RTC_REG06 0x06 // Day of Week - RW +#define SB_RTC_REG07 0x07 // Date of Mont - RW +#define SB_RTC_REG08 0x08 // Mont - RW +#define SB_RTC_REG09 0x09 // Year - RW +#define SB_RTC_REG0A 0x0A // Register A - RW +#define SB_RTC_REG0B 0x0B // Register B - RW +#define SB_RTC_REG0C 0x0C // Register C - R +#define SB_RTC_REG0D 0x0D // DateAlarm - RW +#define SB_RTC_REG32 0x32 // AltCentury - RW +#define SB_RTC_REG48 0x48 // Century - RW +#define SB_RTC_REG50 0x50 // Extended RAM Address Port - RW +#define SB_RTC_REG53 0x53 // Extended RAM Data Port - RW +#define SB_RTC_REG7E 0x7E // RTC Time Clear - RW +#define SB_RTC_REG7F 0x7F // RTC RAM Enable - RW + +#define B_ECMOS_REG00 0x00 // scratc-reg + //;BIT0=0 AsicDebug is enabled + //;BIT1=0 SLT S3 runs +#define SB_ECMOS_REG01 0x01 +#define SB_ECMOS_REG02 0x02 +#define SB_ECMOS_REG03 0x03 +#define SB_ECMOS_REG04 0x04 +#define SB_ECMOS_REG05 0x05 +#define SB_ECMOS_REG06 0x06 +#define SB_ECMOS_REG07 0x07 +#define SB_ECMOS_REG08 0x08 // save 32BIT Pysical address of Config structure +#define SB_ECMOS_REG09 0x09 +#define SB_ECMOS_REG0A 0x0A +#define SB_ECMOS_REG0B 0x0B + +#define SB_ECMOS_REG0C 0x0C //;save MODULE_ID +#define SB_ECMOS_REG0D 0x0D //;Reserve for NB + +#define SB_IOMAP_REG00 0x000 // Dma_C 0 +#define SB_IOMAP_REG02 0x002 // Dma_C 1 +#define SB_IOMAP_REG04 0x004 // Dma_C 2 +#define SB_IOMAP_REG06 0x006 // Dma_C 3 +#define SB_IOMAP_REG08 0x008 // Dma_Status +#define SB_IOMAP_REG09 0x009 // Dma_WriteRest +#define SB_IOMAP_REG0A 0x00A // Dma_WriteMask +#define SB_IOMAP_REG0B 0x00B // Dma_WriteMode +#define SB_IOMAP_REG0C 0x00C // Dma_Clear +#define SB_IOMAP_REG0D 0x00D // Dma_MasterClr +#define SB_IOMAP_REG0E 0x00E // Dma_ClrMask +#define SB_IOMAP_REG0F 0x00F // Dma_AllMask +#define SB_IOMAP_REG20 0x020 // IntrCntrlReg1 +#define SB_IOMAP_REG21 0x021 // IntrCntrlReg2 +#define SB_IOMAP_REG40 0x040 // TimerC0 +#define SB_IOMAP_REG41 0x041 // TimerC1 +#define SB_IOMAP_REG42 0x042 // TimerC2 +#define SB_IOMAP_REG43 0x043 // Tmr1CntrlWord +#define SB_IOMAP_REG61 0x061 // Nmi_Status +#define SB_IOMAP_REG70 0x070 // Nmi_Enable +#define SB_IOMAP_REG71 0x071 // RtcDataPort +#define SB_IOMAP_REG72 0x072 // AlternatRtcAddrPort +#define SB_IOMAP_REG73 0x073 // AlternatRtcDataPort +#define SB_IOMAP_REG80 0x080 // Dma_Page_Reserved0 +#define SB_IOMAP_REG81 0x081 // Dma_PageC2 +#define SB_IOMAP_REG82 0x082 // Dma_PageC3 +#define SB_IOMAP_REG83 0x083 // Dma_PageC1 +#define SB_IOMAP_REG84 0x084 // Dma_Page_Reserved1 +#define SB_IOMAP_REG85 0x085 // Dma_Page_Reserved2 +#define SB_IOMAP_REG86 0x086 // Dma_Page_Reserved3 +#define SB_IOMAP_REG87 0x087 // Dma_PageC0 +#define SB_IOMAP_REG88 0x088 // Dma_Page_Reserved4 +#define SB_IOMAP_REG89 0x089 // Dma_PageC6 +#define SB_IOMAP_REG8A 0x08A // Dma_PageC7 +#define SB_IOMAP_REG8B 0x08B // Dma_PageC5 +#define SB_IOMAP_REG8C 0x08C // Dma_Page_Reserved5 +#define SB_IOMAP_REG8D 0x08D // Dma_Page_Reserved6 +#define SB_IOMAP_REG8E 0x08E // Dma_Page_Reserved7 +#define SB_IOMAP_REG8F 0x08F // Dma_Refres +#define SB_IOMAP_REG92 0x092 // FastInit +#define SB_IOMAP_REGA0 0x0A0 // IntrCntrl2Reg1 +#define SB_IOMAP_REGA1 0x0A1 // IntrCntrl2Reg2 +#define SB_IOMAP_REGC0 0x0C0 // Dma2_C4Addr +#define SB_IOMAP_REGC2 0x0C2 // Dma2_C4Cnt +#define SB_IOMAP_REGC4 0x0C4 // Dma2_C5Addr +#define SB_IOMAP_REGC6 0x0C6 // Dma2_C5Cnt +#define SB_IOMAP_REGC8 0x0C8 // Dma2_C6Addr +#define SB_IOMAP_REGCA 0x0CA // Dma2_C6Cnt +#define SB_IOMAP_REGCC 0x0CC // Dma2_C7Addr +#define SB_IOMAP_REGCE 0x0CE // Dma2_C7Cnt +#define SB_IOMAP_REGD0 0x0D0 // Dma_Status +#define SB_IOMAP_REGD2 0x0D2 // Dma_WriteRest +#define SB_IOMAP_REGD4 0x0D4 // Dma_WriteMask +#define SB_IOMAP_REGD6 0x0D6 // Dma_WriteMode +#define SB_IOMAP_REGD8 0x0D8 // Dma_Clear +#define SB_IOMAP_REGDA 0x0DA // Dma_Clear +#define SB_IOMAP_REGDC 0x0DC // Dma_ClrMask +#define SB_IOMAP_REGDE 0x0DE // Dma_ClrMask +#define SB_IOMAP_REGF0 0x0F0 // NCP_Error +#define SB_IOMAP_REG40B 0x040B // DMA1_Extend +#define SB_IOMAP_REG4D0 0x04D0 // IntrEdgeControl +#define SB_IOMAP_REG4D6 0x04D6 // DMA2_Extend +#define SB_IOMAP_REGC00 0x0C00 // Pci_Intr_Index +#define SB_IOMAP_REGC01 0x0C01 // Pci_Intr_Data +#define SB_IOMAP_REGC14 0x0C14 // Pci_Error +#define SB_IOMAP_REGC50 0x0C50 // CMIndex +#define SB_IOMAP_REGC51 0x0C51 // CMData +#define SB_IOMAP_REGC52 0x0C52 // GpmPort +#define SB_IOMAP_REGC6F 0x0C6F // Isa_Misc +#define SB_IOMAP_REGCD0 0x0CD0 // PMio2_Index +#define SB_IOMAP_REGCD1 0x0CD1 // PMio2_Data +#define SB_IOMAP_REGCD4 0x0CD4 // BIOSRAM_Index +#define SB_IOMAP_REGCD5 0x0CD5 // BIOSRAM_Data +#define SB_IOMAP_REGCD6 0x0CD6 // PM_Index +#define SB_IOMAP_REGCD7 0x0CD7 // PM_Data +#define SB_IOMAP_REGCF9 0x0CF9 // CF9Rst reg + + +#define SB_CM_REG02 0x002 // TempStatus (via SB_IOMAP_REGC50) +#define SB_CM_REG03 0x003 // TempInterrupt (via SB_IOMAP_REGC50) + +#define SB_SATA_REG00 0x000 // Vendor ID - R- 16 bits +#define SB_SATA_REG02 0x002 // Device ID - RW -16 bits +#define SB_SATA_REG04 0x004 // PCI Command - RW - 16 bits +#define SB_SATA_REG06 0x006 // PCI Status - RW - 16 bits +#define SB_SATA_REG08 0x008 // Revision ID/PCI Class Code - R - 32 bits - Offset: 08 +#define SB_SATA_REG0C 0x00C // Cace Line Size - R/W - 8bits +#define SB_SATA_REG0D 0x00D // Latency Timer - RW - 8 bits +#define SB_SATA_REG0E 0x00E // eader Type - R - 8 bits +#define SB_SATA_REG0F 0x00F // BIST - R - 8 bits +#define SB_SATA_REG10 0x010 // Base Address Register 0 - RW - 32 bits +#define SB_SATA_REG14 0x014 // Base Address Register 1 - RW- 32 bits +#define SB_SATA_REG18 0x018 // Base Address Register 2 - RW - 32 bits +#define SB_SATA_REG1C 0x01C // Base Address Register 3 - RW - 32 bits +#define SB_SATA_REG20 0x020 // Base Address Register 4 - RW - 32 bits +#define SB_SATA_REG24 0x024 // Base Address Register 5 - RW - 32 bits +#define SB_SATA_REG2C 0x02C // Subsystem Vendor ID - R - 16 bits +#define SB_SATA_REG2D 0x02D // Subsystem ID - R - 16 bits +#define SB_SATA_REG30 0x030 // Expansion ROM Base Address - 32 bits +#define SB_SATA_REG34 0x034 // Capabilities Pointer - R - 32 bits +#define SB_SATA_REG3C 0x03C // Interrupt Line - RW - 8 bits +#define SB_SATA_REG3D 0x03D // Interrupt Pin - R - 8 bits +#define SB_SATA_REG3E 0x03E // Min Grant - R - 8 bits +#define SB_SATA_REG3F 0x03F // Max Latency - R - 8 bits +#define SB_SATA_REG40 0x040 // Configuration - RW - 32 bits +#define SB_SATA_REG44 0x044 // Software Data Register - RW - 32 bits +#define SB_SATA_REG48 0x048 +#define SB_SATA_REG50 0x050 // Message Capability - R - 16 bits +#define SB_SATA_REG52 0x052 // Message Control - R/W - 16 bits +#define SB_SATA_REG54 0x054 // Message Address - R/W - 32 bits +#define SB_SATA_REG58 0x058 // Message Data - R/W - 16 bits +#define SB_SATA_REG5C 0x05C // RAMBIST Control Register - R/W - 8 bits +#define SB_SATA_REG5D 0x05D // RAMBIST Status0 Register - R - 8 bits +#define SB_SATA_REG5E 0x05E // RAMBIST Status1 Register - R - 8 bits +#define SB_SATA_REG60 0x060 // Power Management Capabilities - R - 32 bits +#define SB_SATA_REG64 0x064 // Power Management Control + Status - RW - 32 bits +#define SB_SATA_REG68 0x068 // MSI Program Weigt - R/W - 8 bits +#define SB_SATA_REG69 0x069 // PCI Burst Timer - R/W - 8 bits +#define SB_SATA_REG70 0x070 // PCI Bus Master - IDE0 - RW - 32 bits +#define SB_SATA_REG74 0x074 // PRD Table Address - IDE0 - RW - 32 bits +#define SB_SATA_REG78 0x078 // PCI Bus Master - IDE1 - RW - 32 bits +#define SB_SATA_REG7C 0x07C // PRD Table Address - IDE1 - RW - 32 bits +#define SB_SATA_REG80 0x080 // Data Transfer Mode - IDE0 - RW - 32 bits +#define SB_SATA_REG84 0x084 // Data Transfer Mode - IDE1 - RW - 32 bits +#define SB_SATA_REG86 0x086 // PY Global Control +#define SB_SATA_REG87 0x087 +#define SB_SATA_REG88 0x088 // PHY Port0 Control - Port0 PY fine tune(0:23) +#define SB_SATA_REG8A 0x08A +#define SB_SATA_REG8C 0x08C // PHY Port1 Control - Port0 PY fine tune(0:23) +#define SB_SATA_REG8E 0x08E +#define SB_SATA_REG90 0x090 // PHY Port2 Control - Port0 PY fine tune(0:23) +#define SB_SATA_REG92 0x092 +#define SB_SATA_REG94 0x094 // PHY Port3 Control - Port0 PY fine tune(0:23) +#define SB_SATA_REG96 0x096 +#define SB_SATA_REG98 0x098 // EEPROM Memory Address - Command + Status - RW - 32 bits +#define SB_SATA_REG9C 0x09C // EEPROM Memory Data - RW - 32 bits +#define SB_SATA_REGA0 0x0A0 // +#define SB_SATA_REGA4 0x0A4 // +#define SB_SATA_REGA5 0x0A5 //; +#define SB_SATA_REGA8 0x0A8 // +#define SB_SATA_REGAD 0x0AD //; +#define SB_SATA_REGB0 0x0B0 // IDE1 Task File Configuration + Status - RW - 32 bits +#define SB_SATA_REGB5 0x0B5 //; +#define SB_SATA_REGBD 0x0BD //; +#define SB_SATA_REGC0 0x0C0 // BA5 Indirect Address - RW - 32 bits +#define SB_SATA_REGC4 0x0C4 // BA5 Indirect Access - RW - 32 bits + +#define SB_SATA_BAR5_REG00 0x000 // PCI Bus Master - IDE0 - RW - 32 bits +#define SB_SATA_BAR5_REG04 0x004 // PRD Table Address - IDE0 - RW - 32 bits +#define SB_SATA_BAR5_REG08 0x008 // PCI Bus Master - IDE1 - RW - 32 bits +#define SB_SATA_BAR5_REG0C 0x00C // PRD Table Address - IDE1 - RW - 32 bits +#define SB_SATA_BAR5_REG10 0x010 // PCI Bus Master2 - IDE0 - RW - 32 bits +#define SB_SATA_BAR5_REG18 0x018 // PCI Bus Master2 - IDE1 - RW - 32 bits +#define SB_SATA_BAR5_REG20 0x020 // PRD Address - IDE0 - RW - 32 bits +#define SB_SATA_BAR5_REG24 0x024 // PCI Bus Master Byte Count - IDE0- RW - 32 bits +#define SB_SATA_BAR5_REG28 0x028 // PRD Address - IDE1 - RW - 32 bits +#define SB_SATA_BAR5_REG2C 0x02C // PCI Bus Master Byte Count - IDE1 - RW - 32 bits +#define SB_SATA_BAR5_REG40 0x040 // FIFO Valid Byte Count and Control - IDE0 - RW - 32 bits +#define SB_SATA_BAR5_REG44 0x044 // FIFO Valid Byte Count and Control - IDE1 - RW - 32 bits +#define SB_SATA_BAR5_REG48 0x048 // System Configuration Status - Command - RW - 32 bits +#define SB_SATA_BAR5_REG4C 0x04C // System Software Data Register - RW - 32 bits +#define SB_SATA_BAR5_REG50 0x050 // FLAS Memory Address - Command + Status - RW - 32 bits +#define SB_SATA_BAR5_REG54 0x054 // FLAS Memory Data - RW - 32 bits +#define SB_SATA_BAR5_REG58 0x058 // EEPROM Memory Address - Command + Status - RW - 32 bits +#define SB_SATA_BAR5_REG5C 0x05C // EEPROM Memory Data - RW - 32 bits +#define SB_SATA_BAR5_REG60 0x060 // FIFO Port - IDE0 - RW - 32 bits +#define SB_SATA_BAR5_REG68 0x068 // FIFO Pointers1- IDE0 - RW - 32 bits +#define SB_SATA_BAR5_REG6C 0x06C // FIFO Pointers2- IDE0 - RW - 32 bits +#define SB_SATA_BAR5_REG70 0x070 // FIFO Port - IDE1- RW - 32 bits +#define SB_SATA_BAR5_REG78 0x078 // FIFO Pointers1- IDE1- RW - 32 bits +#define SB_SATA_BAR5_REG7C 0x07C // FIFO Pointers2- IDE1- RW - 32 bits +#define SB_SATA_BAR5_REG80 0x080 // IDE0 Task File Register 0- RW - 32 bits +#define SB_SATA_BAR5_REG84 0x084 // IDE0 Task File Register 1- RW - 32 bits +#define SB_SATA_BAR5_REG88 0x088 // IDE0 Task File Register 2- RW - 32 bits +#define SB_SATA_BAR5_REG8C 0x08C // IDE0 Read Aead Data - RW - 32 bits +#define SB_SATA_BAR5_REG90 0x090 // IDE0 Task File Register 0 - Command Buffering - RW - 32 bits +#define SB_SATA_BAR5_REG94 0x094 // IDE0 Task File Register 1 - Command Buffering - RW - 32 bits +#define SB_SATA_BAR5_REG9C 0x09C // IDE0 Virtual DMA/PIO Read Aead Byte Count - RW - 32 bits +#define SB_SATA_BAR5_REGA0 0x0A0 // IDE0 Task File Configuration + Status - RW - 32 bits +#define SB_SATA_BAR5_REGB4 0x0B4 // Data Transfer Mode -IDE0 - RW - 32 bits +#define SB_SATA_BAR5_REGC0 0x0C0 // IDE1 Task File Register 0 - RW - 32 bits +#define SB_SATA_BAR5_REGC4 0x0C4 // IDE1 Task File Register 1 - RW - 32 bits +#define SB_SATA_BAR5_REGC8 0x0C8 // IDE1 Task File Register 2 - RW - 32 bits +#define SB_SATA_BAR5_REGCC 0x0CC // Read/Write Aead Data - RW - 32 bits +#define SB_SATA_BAR5_REGD0 0x0D0 // IDE1 Task File Register 0 - Command Buffering - RW - 32 bits +#define SB_SATA_BAR5_REGD4 0x0D4 // IDE1 Task File Register 1 - Command Buffering - RW - 32 bits +#define SB_SATA_BAR5_REGDC 0x0DC // IDE1 Virtual DMA/PIO Read Aead Byte Count - RW - 32 bits +#define SB_SATA_BAR5_REGE0 0x0E0 // IDE1 Task File Configuration + Status - RW - 32 bits +#define SB_SATA_BAR5_REGF4 0x0F4 // Data Transfer Mode - IDE1 - RW - 32 bits +#define SB_SATA_BAR5_REGF8 0x0F8 // PORT Configuration +#define SB_SATA_BAR5_REGFC 0x0FC + +#define SB_SATA_BAR5_REG100 0x0100 //;Serial ATA SControl - RW - 32 bits - [Offset: 100h (channel 1) / 180 +#define SB_SATA_BAR5_REG104 0x0104 //;Serial ATA Sstatus - RW - 32 bits - [Offset: 104h (channel 1) / 184h (cannel +#define SB_SATA_BAR5_REG108 0x0108 //;Serial ATA Serror - RW - 32 bits - [Offset: 108h (channel 1) / 188h (cannel +#define SB_SATA_BAR5_REG10C 0x010C //;Serial ATA Sdevice - RW - 32 bits - [Offset: 10Ch (channel 1) / 18Ch (cannel +#define SB_SATA_BAR5_REG110 0x0110 // Port-N Interrupt Status +#define SB_SATA_BAR5_REG144 0x0144 //;Serial ATA PY Configuration - RW - 32 bits +#define SB_SATA_BAR5_REG148 0x0148 //;SIEN - RW - 32 bits - [Offset: 148 (channel 1) / 1C8 (cannel 2)] +#define SB_SATA_BAR5_REG14C 0x014C //;SFISCfg - RW - 32 bits - [Offset: 14C (channel 1) / 1CC (cannel 2)] +#define SB_SATA_BAR5_REG120 0x0120 // Port Task Fike Data +#define SB_SATA_BAR5_REG128 0x0128 // Port Serial ATA Status +#define SB_SATA_BAR5_REG12C 0x012C // Port Serial ATA Control + +#define SB_SATA_BAR5_REG130 0x0130 +#define SB_SATA_BAR5_REG1B0 0x01B0 +#define SB_SATA_BAR5_REG230 0x0230 +#define SB_SATA_BAR5_REG2B0 0x02B0 + +#define SB_FC_REG00 0x00 // Device/Vendor ID - R +#define SB_FC_REG04 0x04 // Command - RW +#define SB_FC_REG10 0x10 // BAR + +#define SB_FC_MMIO_REG70 0x070 +#define SB_FC_MMIO_REG200 0x200 + +#define SB_OHCI_REG00 0x00 // Device/Vendor ID - R +#define SB_OHCI_REG04 0x04 // Command - RW +#define SB_OHCI_REG06 0x06 // Status - R +#define SB_OHCI_REG08 0x08 // Revision ID/Class Code - R +#define SB_OHCI_REG0C 0x0C // Miscellaneous - RW +#define SB_OHCI_REG10 0x10 // Bar_OCI - RW +#define SB_OHCI_REG2C 0x2C // Subsystem Vendor ID/ Subsystem ID - RW +#define SB_OHCI_REG34 0x34 // Capability Pointer - R +#define SB_OHCI_REG3C 0x3C // Interrupt Line - RW +#define SB_OHCI_REG3D 0x3D // Interrupt Line - RW + +#define SB_OHCI_REG40 0x40 // Config Timers - RW +#define SB_OHCI_REG4C 0x4C // MSI Weigt - RW +#define SB_OHCI_REG50 0x50 // ATI Misc Control - RW +#define SB_OHCI_REG51 0x51 +#define SB_OHCI_REG58 0x58 // Over Current Control - RW +#define SB_OHCI_REG5C 0x5C // Over Current Control - RW +#define SB_OHCI_REG60 0x60 // Serial Bus Release Number - R +#define SB_OHCI_REG68 0x68 // Over Current Enable - RW +#define SB_OHCI_REGD0 0x0D0 // MSI Control - RW +#define SB_OHCI_REGD4 0x0D4 // MSI Address - RW +#define SB_OHCI_REGD8 0x0D8 // MSI Data - RW +#define SB_OHCI_BAR_REG00 0x00 // cRevision - R +#define SB_OHCI_BAR_REG04 0x04 // cControl +#define SB_OHCI_BAR_REG08 0x08 // cCommandStatus +#define SB_OHCI_BAR_REG0C 0x0C // cInterruptStatus RW +#define SB_OHCI_BAR_REG10 0x10 // cInterruptEnable +#define SB_OHCI_BAR_REG14 0x14 // cInterruptDisable +#define SB_OHCI_BAR_REG18 0x18 // HcCCA +#define SB_OHCI_BAR_REG1C 0x1C // cPeriodCurrentED +#define SB_OHCI_BAR_REG20 0x20 // HcControleadED +#define SB_OHCI_BAR_REG24 0x24 // cControlCurrentED RW +#define SB_OHCI_BAR_REG28 0x28 // HcBulkeadED +#define SB_OHCI_BAR_REG2C 0x2C // cBulkCurrentED- RW +#define SB_OHCI_BAR_REG30 0x30 // HcDoneead +#define SB_OHCI_BAR_REG34 0x34 // cFmInterval +#define SB_OHCI_BAR_REG38 0x38 // cFmRemaining +#define SB_OHCI_BAR_REG3C 0x3C // cFmNumber +#define SB_OHCI_BAR_REG40 0x40 // cPeriodicStart +#define SB_OHCI_BAR_REG44 0x44 // HcLSThresold +#define SB_OHCI_BAR_REG48 0x48 // HcRDescriptorA +#define SB_OHCI_BAR_REG4C 0x4C // HcRDescriptorB +#define SB_OHCI_BAR_REG50 0x50 // HcRStatus +#define SB_OHCI_BAR_REG160 0x160 + +#define SB_EHCI_REG00 0x00 // DEVICE/VENDOR ID - R +#define SB_EHCI_REG04 0x04 // Command - RW +#define SB_EHCI_REG06 0x06 // Status - R +#define SB_EHCI_REG08 0x08 // Revision ID/Class Code - R +#define SB_EHCI_REG0C 0x0C // Miscellaneous - RW +#define SB_EHCI_REG10 0x10 // BAR - RW +#define SB_EHCI_REG2C 0x2C // Subsystem ID/Subsystem Vendor ID - RW +#define SB_EHCI_REG34 0x34 // Capability Pointer - R +#define SB_EHCI_REG3C 0x3C // Interrupt Line - RW +#define SB_EHCI_REG3D 0x3D // Interrupt Line - RW +#define SB_EHCI_REG40 0x40 // Config Timers - RW +#define SB_EHCI_REG4C 0x4C // MSI Weigt - RW +#define SB_EHCI_REG50 0x50 // ATI Misc Control - RW +#define SB_EHCI_REG54 0x54 // ATI Misc Control - RW +#define SB_EHCI_REG58 0x58 // Over Current Control - R +#define SB_EHCI_REG60 0x60 // SBRN - R +#define SB_EHCI_REG61 0x61 // FLADJ - RW +#define SB_EHCI_REG62 0x62 // PORTWAKECAP - RW +#define SB_EHCI_REGD0 0x0D0 // MSI Control - RW +#define SB_EHCI_REGD4 0x0D4 // MSI Address - RW +#define SB_EHCI_REGD8 0x0D8 // MSI Data - RW +#define SB_EHCI_REGDC 0x0DC // PME Control - RW +#define SB_EHCI_REGE0 0x0E0 // PME Data / Status - RW +#define SB_EHCI_BAR_REG00 0x00 // CAPLENGT - R +#define SB_EHCI_BAR_REG02 0x002 // CIVERSION- R +#define SB_EHCI_BAR_REG04 0x004 // CSPARAMS - R +#define SB_EHCI_BAR_REG08 0x008 // CCPARAMS - R +#define SB_EHCI_BAR_REG0C 0x00C // CSP-PORTROUTE - R +#define SB_EHCI_BAR_REG20 0x020 // USBCMD - RW - 32 bits +#define SB_EHCI_BAR_REG24 0x024 // USBSTS - RW - 32 bits +#define SB_EHCI_BAR_REG28 0x028 // USBINTR -RW - 32 bits +#define SB_EHCI_BAR_REG2C 0x02C // FRINDEX -RW - 32 bits +#define SB_EHCI_BAR_REG30 0x030 // CTRLDSSEGMENT -RW - 32 bits +#define SB_EHCI_BAR_REG34 0x034 // PERIODICLISTBASE -RW - 32 bits +#define SB_EHCI_BAR_REG38 0x038 // ASYNCLISTADDR -RW - 32 bits +#define SB_EHCI_BAR_REG60 0x060 // CONFIGFLAG -RW - 32 bits +#define SB_EHCI_BAR_REG64 0x064 // PORTSC(1-N_PORTS) -RW - 32 bits +#define SB_EHCI_BAR_REG84 0x084 // Packet Buffer Thresold Values - RW - 32 bits +#define SB_EHCI_BAR_REG88 0x088 // Packet Buffer Dept Value - RW - 32 bits +#define SB_EHCI_BAR_REG94 0x094 // UTMI Control and Status - RW - 32 bits +#define SB_EHCI_BAR_REG98 0x098 // Bist Control - RW - 32 bits +#define SB_EHCI_BAR_REG9C 0x09C // ATI EOR Control - RW - 32 bits +#define SB_EHCI_BAR_REGA4 0x0A4 // USB IN/OUT FIFO Thresold Setting +#define SB_EHCI_BAR_REGBC 0x0BC // ECI misc Setting +#define SB_EHCI_BAR_REGC0 0x0C0 // USB PHY Auto Calibration Setting + +#define SB_SMBUS_REG00 0x000 //;VendorID - R +#define SB_SMBUS_REG02 0x002 //;DeviceID - R +#define SB_SMBUS_REG04 0x004 // Command- RW +#define SB_SMBUS_REG05 0x005 // Command- RW +#define SB_SMBUS_REG06 0x006 // STATUS- RW +#define SB_SMBUS_REG08 0x008 // Revision ID/Class Code- R +#define SB_SMBUS_REG0A 0x00A //; +#define SB_SMBUS_REG0B 0x00B //; +#define SB_SMBUS_REG0C 0x00C // Cace Line Size- R +#define SB_SMBUS_REG0D 0x00D // Latency Timer- R +#define SB_SMBUS_REG0E 0x00E // eader Type- R +#define SB_SMBUS_REG0F 0x00F // BIST- R +#define SB_SMBUS_REG10 0x010 // Base Address 0- R +#define SB_SMBUS_REG11 0x011 //; +#define SB_SMBUS_REG12 0x012 //; +#define SB_SMBUS_REG13 0x013 //; +#define SB_SMBUS_REG14 0x014 // Base Address 1- R +#define SB_SMBUS_REG18 0x018 // Base Address 2- R +#define SB_SMBUS_REG1C 0x01C // Base Address 3- R +#define SB_SMBUS_REG20 0x020 // Base Address 4- R +#define SB_SMBUS_REG24 0x024 // Base Address 5- R +#define SB_SMBUS_REG28 0x028 // Cardbus CIS Pointer- R +#define SB_SMBUS_REG2C 0x02C // Subsystem Vendor ID- W +#define SB_SMBUS_REG2E 0x02E // Subsystem ID- W +#define SB_SMBUS_REG30 0x030 // Expansion ROM Base Address - R +#define SB_SMBUS_REG34 0x034 // Capability Pointer - R +#define SB_SMBUS_REG38 0x038 +#define SB_SMBUS_REG3C 0x03C // Interrupt Line - R +#define SB_SMBUS_REG3D 0x03D // Interrupt Pin - R +#define SB_SMBUS_REG3E 0x03E // Min_Gnt - R +#define SB_SMBUS_REG3F 0x03F // Max_Lat - R +#define SB_SMBUS_REG40 0x040 // PCI Control- RW +#define SB_SMBUS_REG41 0x041 // MiscFunction- RW +#define SB_SMBUS_REG42 0x042 // DmaLimit- RW +#define SB_SMBUS_REG43 0x043 // DmaEnanceEnable RW +#define SB_SMBUS_REG48 0x048 // ISA Address Decode Control Register #1- RW +#define SB_SMBUS_REG49 0x049 // ISA Address Decode Control Register #2- RW +#define SB_SMBUS_REG4A 0x04A // Scratc Pad- RW +#define SB_SMBUS_REG50 0x050 // PciGpioOutControl- RW +#define SB_SMBUS_REG54 0x054 // PciGpioConfig- RW +#define SB_SMBUS_REG58 0x058 // ASFSMBusIoBase +#define SB_SMBUS_REG59 0x059 //; +#define SB_SMBUS_REG5C 0x05C // Smart Power Control1 +#define SB_SMBUS_REG60 0x060 // MiscEnable- RW +#define SB_SMBUS_REG64 0x064 // Features Enable- RW +#define SB_SMBUS_REG68 0x068 // UsbEnable - RW +#define SB_SMBUS_REG6C 0x06C // TestMode- RW +#define SB_SMBUS_REG70 0x070 // RunTimeTest- R +#define SB_SMBUS_REG74 0x074 // IoApic_Conf- RW +#define SB_SMBUS_REG78 0x078 // IoAddrEnable - R/W +#define SB_SMBUS_REG79 0x079 //; +#define SB_SMBUS_REG7C 0x07C // RTC Control ;VSJ-2005-06-16 +#define SB_SMBUS_REG80 0x080 // GPIO_Out_Cntrl - RW +#define SB_SMBUS_REG81 0x081 // GPIO_Status - R +#define SB_SMBUS_REG90 0x090 // Smbus Base Address - R +#define SB_SMBUS_REG94 0x094 // Reserved - R +#define SB_SMBUS_REG98 0x098 // +#define SB_SMBUS_REGA0 0x0A0 // MoreGPIOIn +C R +#define SB_SMBUS_REGA4 0x0A4 // MoreGPIOIn +C R +#define SB_SMBUS_REGA8 0x0A8 // GPIOControl +C RW +#define SB_SMBUS_REGAC 0x0AC // MiscUsbEt - RW +#define SB_SMBUS_REGAD 0x0AD // MiscSata +#define SB_SMBUS_REGAE 0x0AE +#define SB_SMBUS_REGAF 0x0AF // SataIntMap - RW +#define SB_SMBUS_REGB0 0x0B0 // MSI Mapping Capability - R +#define SB_SMBUS_REGB4 0x0B4 //HPET BASE Address +#define SB_SMBUS_REGBC 0x0BC // PciIntGpio - RW +#define SB_SMBUS_REGBE 0x0BE // UsbIntMap - RW +#define SB_SMBUS_REGC0 0x0C0 // IokHiDrvSt - RW +#define SB_SMBUS_REGD0 0x0D0 // +#define SB_SMBUS_REGD2 0x0D2 // I2CbusConfig - RW +#define SB_SMBUS_REGD3 0x0D3 // I2CCommand - RW +#define SB_SMBUS_REGD4 0x0D4 // I2CSadow1- RW +#define SB_SMBUS_REGD5 0x0D5 // I2Csadow2- RW +#define SB_SMBUS_REGD6 0x0D6 // I2CBusRevision - RW +#define SB_SMBUS_REGE0 0x0E0 // MSI_Weigt +#define SB_SMBUS_REGE1 0x0E1 // MSI_Weigt +#define SB_SMBUS_REGF0 0x0F0 // AB_REG_BAR - RW +#define SB_SMBUS_REGF1 0x0F1 +#define SB_SMBUS_REGF4 0x0F4 // WakeIoAddr- RW +#define SB_SMBUS_REGF8 0x0F8 // ExtendedAddrPort- RW +#define SB_SMBUS_REGFC 0x0FC // ExtendedDataPort- RW + + +#define SB_IDE_REG00 0x00 // Vendor ID +#define SB_IDE_REG02 0x02 // Device ID +#define SB_IDE_REG04 0x04 // Command +#define SB_IDE_REG06 0x06 // Status +#define SB_IDE_REG08 0x08 // Revision ID/Class Code +#define SB_IDE_REG09 0x09 // Class Code +#define SB_IDE_REG0A 0x0A +#define SB_IDE_REG0C 0x0C // Cace Link Size +#define SB_IDE_REG0D 0x0D // Master Latency Timer +#define SB_IDE_REG0E 0x0E // eader Type +#define SB_IDE_REG0F 0x0F // BIST Mode Type +#define SB_IDE_REG10 0x10 // Base Address 0 +#define SB_IDE_REG14 0x14 // Base Address 1 +#define SB_IDE_REG18 0x18 // Base Address 2 +#define SB_IDE_REG1C 0x1C // Base Address 3 +#define SB_IDE_REG20 0x20 // Bus Master Interface Base Address +#define SB_IDE_REG2C 0x2C // Subsystem ID and Subsystem Vendor ID +#define SB_IDE_REG34 0x34 // MSI Capabilities Pointer +#define SB_IDE_REG3C 0x3C // Interrupt Line +#define SB_IDE_REG3D 0x3D // Interrupt Pin +#define SB_IDE_REG3E 0x3E // Min_gnt +#define SB_IDE_REG3F 0x3F // Max_latency +#define SB_IDE_REG40 0x40 // IDE PIO Timing +#define SB_IDE_REG44 0x44 // IDE Legacy DMA (Multi-words DMA) Timing Modes +#define SB_IDE_REG48 0x48 // IDE PIO Control +#define SB_IDE_REG4A 0x4A // IDE PIO Mode +#define SB_IDE_REG4C 0x4C // IDE Status +#define SB_IDE_REG54 0x54 // IDE Ultra DMAControl +#define SB_IDE_REG55 0x55 // IDE Ultra DMA Status +#define SB_IDE_REG56 0x56 // IDE Ultra DMA Mode +#define SB_IDE_REG60 0x60 // IDE PCI Retry Timing Counter +#define SB_IDE_REG61 0x61 // PCI Error Control +#define SB_IDE_REG62 0x62 // IDE Internal Control +#define SB_IDE_REG63 0x63 // IDE Internal Control +#define SB_IDE_REG64 0x64 // IDE PLL Control +#define SB_IDE_REG68 0x68 // IDE MSI Programmable Weigt +#define SB_IDE_REG6C 0x6C // IDE Dynamic Clocking +#define SB_IDE_REG70 0x70 // IDE MSI Control +#define SB_IDE_REG74 0x74 // IDE MSI Address Register +#define SB_IDE_REG78 0x78 // IDE MSI Data Register + + +#define SB_AZ_REG00 0x00 // Vendor ID - R +#define SB_AZ_REG02 0x02 // Device ID - R/W +#define SB_AZ_REG04 0x04 // PCI Command +#define SB_AZ_REG06 0x06 // PCI Status - R/W +#define SB_AZ_REG08 0x08 // Revision ID +#define SB_AZ_REG09 0x09 // Programming Interface +#define SB_AZ_REG0A 0x0A // Sub Class Code +#define SB_AZ_REG0B 0x0B // Base Class Code +#define SB_AZ_REG0C 0x0C // Cace Line Size - R/W +#define SB_AZ_REG0D 0x0D // Latency Timer +#define SB_AZ_REG0E 0x0E // eader Type +#define SB_AZ_REG0F 0x0F // BIST +#define SB_AZ_REG10 0x10 // Lower Base Address Register +#define SB_AZ_REG14 0x14 // Upper Base Address Register +#define SB_AZ_REG2C 0x2C // Subsystem Vendor ID +#define SB_AZ_REG2D 0x2D // Subsystem ID +#define SB_AZ_REG34 0x34 // Capabilities Pointer +#define SB_AZ_REG3C 0x3C // Interrupt Line +#define SB_AZ_REG3D 0x3D // Interrupt Pin +#define SB_AZ_REG3E 0x3E // Minimum Grant +#define SB_AZ_REG3F 0x3F // Maximum Latency +#define SB_AZ_REG40 0x40 // Misc Control 1 +#define SB_AZ_REG42 0x42 // Misc Control 2 Register +#define SB_AZ_REG43 0x43 // Misc Control 3 Register +#define SB_AZ_REG44 0x44 // Interrupt Pin Control Register +#define SB_AZ_REG46 0x46 // Debug Control Register +#define SB_AZ_REG4C 0x4C +#define SB_AZ_REG50 0x50 // Power Management Capability ID +#define SB_AZ_REG52 0x52 // Power Management Capabilities +#define SB_AZ_REG54 0x54 // Power Management Control/Status +#define SB_AZ_REG60 0x60 // MSI Capability ID +#define SB_AZ_REG62 0x62 // MSI Message Control +#define SB_AZ_REG64 0x64 // MSI Message Lower Address +#define SB_AZ_REG68 0x68 // MSI Message Upper Address +#define SB_AZ_REG6C 0x6C // MSI Message Data + +#define SB_AZ_BAR_REG00 0x00 // Global Capabilities - R +#define SB_AZ_BAR_REG02 0x02 // Minor Version - R +#define SB_AZ_BAR_REG03 0x03 // Major Version - R +#define SB_AZ_BAR_REG04 0x04 // Output Payload Capability - R +#define SB_AZ_BAR_REG06 0x06 // Input Payload Capability - R +#define SB_AZ_BAR_REG08 0x08 // Global Control - R/W +#define SB_AZ_BAR_REG0C 0x0C // Wake Enable - R/W +#define SB_AZ_BAR_REG0E 0x0E // State Cange Status - R/W +#define SB_AZ_BAR_REG10 0x10 // Global Status - R/W +#define SB_AZ_BAR_REG18 0x18 // Output Stream Payload Capability - R +#define SB_AZ_BAR_REG1A 0x1A // Input Stream Payload Capability - R +#define SB_AZ_BAR_REG20 0x20 // Interrupt Control - R/W +#define SB_AZ_BAR_REG24 0x24 // Interrupt Status - R/W +#define SB_AZ_BAR_REG30 0x30 // Wall Clock Counter - R +#define SB_AZ_BAR_REG38 0x38 // Stream Syncronization - R/W +#define SB_AZ_BAR_REG40 0x40 // CORB Lower Base Address - R/W +#define SB_AZ_BAR_REG44 0x44 // CORB Upper Base Address - RW +#define SB_AZ_BAR_REG48 0x48 // CORB Write Pointer - R/W +#define SB_AZ_BAR_REG4A 0x4A // CORB Read Pointer - R/W +#define SB_AZ_BAR_REG4C 0x4C // CORB Control - R/W +#define SB_AZ_BAR_REG4D 0x4D // CORB Status - R/W +#define SB_AZ_BAR_REG4E 0x4E // CORB Size - R/W +#define SB_AZ_BAR_REG50 0x50 // RIRB Lower Base Address - RW +#define SB_AZ_BAR_REG54 0x54 // RIRB Upper Address - RW +#define SB_AZ_BAR_REG58 0x58 // RIRB Write Pointer - RW +#define SB_AZ_BAR_REG5A 0x5A // RIRB Response Interrupt Count - R/W +#define SB_AZ_BAR_REG5C 0x5C // RIRB Control - R/W +#define SB_AZ_BAR_REG5D 0x5D // RIRB Status - R/W +#define SB_AZ_BAR_REG5E 0x5E // RIRB Size - R/W +#define SB_AZ_BAR_REG60 0x60 // Immediate Command Output Interface - R/W +#define SB_AZ_BAR_REG64 0x64 // Immediate Command Input Interface - R/W +#define SB_AZ_BAR_REG68 0x68 // Immediate Command Input Interface - R/W +#define SB_AZ_BAR_REG70 0x70 // DMA Position Lower Base Address - R/W +#define SB_AZ_BAR_REG74 0x74 // DMA Position Upper Base Address - R/W +#define SB_AZ_BAR_REG2030 0x2030 // Wall Clock Counter Alias - R + + +#define SB_LPC_REG00 0x00 // VID- R +#define SB_LPC_REG02 0x02 // DID- R +#define SB_LPC_REG04 0x04 // CMD- RW +#define SB_LPC_REG06 0x06 // STATUS- RW +#define SB_LPC_REG08 0x08 // Revision ID/Class Code - R +#define SB_LPC_REG0C 0x0C // Cace Line Size - R +#define SB_LPC_REG0D 0x0D // Latency Timer - R +#define SB_LPC_REG0E 0x0E // eader Type - R +#define SB_LPC_REG0F 0x0F // BIST- R +#define SB_LPC_REG10 0x10 // Base Address Reg 0- RW* +#define SB_LPC_REG2C 0x2C // Subsystem ID & Subsystem Vendor ID - Wo/Ro +#define SB_LPC_REG34 0x34 // Capabilities Pointer - Ro +#define SB_LPC_REG40 0x40 // PCI Control - RW +#define SB_LPC_REG44 0x44 // IO Port Decode Enable Register 1- RW +#define SB_LPC_REG45 0x45 // IO Port Decode Enable Register 2- RW +#define SB_LPC_REG46 0x46 // IO Port Decode Enable Register 3- RW +#define SB_LPC_REG47 0x47 // IO Port Decode Enable Register 4- RW +#define SB_LPC_REG48 0x48 // IO/Mem Port Decode Enable Register 5- RW +#define SB_LPC_REG49 0x49 // LPC Sync Timeout Count - RW +#define SB_LPC_REG4A 0x4A // IO/Mem Port Decode Enable Register 6- RW +#define SB_LPC_REG4C 0x4C // Memory Range Register - RW +#define SB_LPC_REG50 0x50 // Rom Protect 0 - RW +#define SB_LPC_REG54 0x54 // Rom Protect 1 - RW +#define SB_LPC_REG58 0x58 // Rom Protect 2 - RW +#define SB_LPC_REG5C 0x5C // Rom Protect 3 - RW +#define SB_LPC_REG60 0x60 // PCI Memory Start Address of LPC Target Cycles - +#define SB_LPC_REG62 0x62 // PCI Memory End Address of LPC Target Cycles - +#define SB_LPC_REG64 0x64 // PCI IO base Address of Wide Generic Port - RW +#define SB_LPC_REG65 0x65 +#define SB_LPC_REG66 0x66 +#define SB_LPC_REG67 0x67 +#define SB_LPC_REG68 0x68 // LPC ROM Address Range 1 (Start Address) - RW +#define SB_LPC_REG69 0x69 +#define SB_LPC_REG6A 0x6A // LPC ROM Address Range 1 (End Address) - RW +#define SB_LPC_REG6B 0x6B +#define SB_LPC_REG6C 0x6C // LPC ROM Address Range 2 (Start Address)- RW +#define SB_LPC_REG6D 0x6D +#define SB_LPC_REG6E 0x6E // LPC ROM Address Range 2 (End Address) - RW +#define SB_LPC_REG6F 0x6F +#define SB_LPC_REG70 0x70 // Firmware ub Select - RW* +#define SB_LPC_REG71 0x71 +#define SB_LPC_REG72 0x72 +#define SB_LPC_REG73 0x73 +#define SB_LPC_REG74 0x74 // Alternative Wide IO Range Enable- W/R +#define SB_LPC_REG78 0x78 // Miscellaneous Control Bits- W/R +#define SB_LPC_REG7C 0x7C // TPM (trusted plant form module) reg- W/R +#define SB_LPC_REG9C 0x9C +#define SB_LPC_REG80 0x80 // MSI Capability Register- R +#define SB_LPC_REG8C 0x8C +#define SB_LPC_REGA0 0x0A0 // SPI base address +#define SB_LPC_REGA1 0x0A1 // SPI base address +#define SB_LPC_REGA2 0x0A2 // SPI base address +#define SB_LPC_REGA3 0x0A3 // SPI base address +#define SB_LPC_REGA4 0x0A4 +#define SB_LPC_REGB8 0x0B8 +#define SB_LPC_REGBA 0x0BA // EcControl +#define SB_LPC_REGBB 0x0BB // HostControl + + +#define SB_P2P_REG00 0x00 // VID - R +#define SB_P2P_REG02 0x02 // DID - R +#define SB_P2P_REG04 0x04 // CMD- RW +#define SB_P2P_REG06 0x06 // STATUS- RW +#define SB_P2P_REG08 0x08 // Revision ID/Class Code- R +#define SB_P2P_REG0C 0x0C // CSIZE- RW +#define SB_P2P_REG0D 0x0D // LTIMER- RW +#define SB_P2P_REG0E 0x0E // TYPE- R +#define SB_P2P_REG18 0x18 // PBN- RW +#define SB_P2P_REG19 0x19 // SBN- RW +#define SB_P2P_REG1A 0x1A // SUBBN- RW +#define SB_P2P_REG1B 0x1B // SLTIMER- RW +#define SB_P2P_REG1C 0x1C // IOBASE- RW +#define SB_P2P_REG1D 0x1D // IOLMT- RW +#define SB_P2P_REG1E 0x1E // SSTATUS- RW +#define SB_P2P_REG20 0x20 // MBASE- RW +#define SB_P2P_REG21 0x21 +#define SB_P2P_REG22 0x22 // MLMT- RW +#define SB_P2P_REG23 0x23 +#define SB_P2P_REG24 0x24 // PMBASE- RW +#define SB_P2P_REG25 0x25 +#define SB_P2P_REG26 0x26 // PMLMT- RW +#define SB_P2P_REG27 0x27 +#define SB_P2P_REG30 0x30 // IOBU16- RW +#define SB_P2P_REG32 0x32 // IOLU16- RW +#define SB_P2P_REG34 0x34 // ECP_PTR- R +#define SB_P2P_REG3C 0x3C // INTLN- RW +#define SB_P2P_REG3D 0x3D // INTPN- R +#define SB_P2P_REG3E 0x3E // BCTRL- RW +#define SB_P2P_REG40 0x40 // CPCTRL- R/W +#define SB_P2P_REG41 0x41 // DCTRL- RW +#define SB_P2P_REG42 0x42 // CLKCTRL- R/W +#define SB_P2P_REG43 0x43 // ARCTRL- RW +#define SB_P2P_REG44 0x44 // SMLT_PERF- RW +#define SB_P2P_REG46 0x46 // PMLT_PERF- RW +#define SB_P2P_REG48 0x48 // PCDMA- RW +#define SB_P2P_REG49 0x49 // Additional Priority- Bits RW +#define SB_P2P_REG4A 0x4A // PCICLK Enable- Bits RW +#define SB_P2P_REG4B 0x4B // Misc Control RW +#define SB_P2P_REG4C 0x4C // AutoClockRun control RW +#define SB_P2P_REG50 0x50 // Dual Address Cycle Enable and PCIB_CLK_Stop +#define SB_P2P_REG54 0x54 // MSI Mapping Capability +#define SB_P2P_REG58 0x58 // Signature Register of Microsoft Rework +#define SB_P2P_REG64 0x64 // Misc Control Register +#define SB_P2P_REG65 0x65 // Misc Control Register + +#define SB_PMIO2_REG00 0x00 +#define SB_PMIO2_REG01 0x01 +#define SB_PMIO2_REG31 0x31 +#define SB_PMIO2_REG32 0x32 +#define SB_PMIO2_REG33 0x33 +#define SB_PMIO2_REG34 0x34 +#define SB_PMIO2_REG35 0x35 +#define SB_PMIO2_REG36 0x36 +#define SB_PMIO2_REG37 0x37 +#define SB_PMIO2_REG38 0x38 +#define SB_PMIO2_REG39 0x39 +#define SB_PMIO2_REG3A 0x3A +#define SB_PMIO2_REG3B 0x3B +#define SB_PMIO2_REG3C 0x3C +#define SB_PMIO2_REG3D 0x3D +#define SB_PMIO2_REG3E 0x3E +#define SB_PMIO2_REG3F 0x3F +#define SB_PMIO2_REG40 0x40 +#define SB_PMIO2_REG41 0x41 +#define SB_PMIO2_REG42 0x42 +#define SB_PMIO2_REG43 0x43 +#define SB_PMIO2_REG44 0x44 +#define SB_PMIO2_REG45 0x45 +#define SB_PMIO2_REG46 0x46 +#define SB_PMIO2_REG47 0x47 +#define SB_PMIO2_REG48 0x48 +#define SB_PMIO2_REG49 0x49 +#define SB_PMIO2_REG54 0x54 +#define SB_PMIO2_REG58 0x58 +#define SB_PMIO2_REG59 0x59 +#define SB_PMIO2_REG5A 0x5A +#define SB_PMIO2_REG5B 0x5B +#define SB_PMIO2_REG5C 0x5C +#define SB_PMIO2_REG70 0x70 +#define SB_PMIO2_REGE5 0xE5 + +#define SB_SPI_MMIO_REG0C 0x0C //SPI_Cntrl1 Register + + +//Bus 0 Device 0x18 Function 0 HyperTransfer +//Link Frequency/Revision Register 0x88/0xA8/0xC8/0xE8 - 32 bits. +#define HT_LINK_REG89 0x89 +#define HT_LINK_REGA9 0xA9 +#define HT_LINK_REGC9 0xC9 +#define HT_LINK_REGE9 0xE9 + +//Link Type Register 0x98/0xB8/0xD8/0xF8 - 32 bits. +#define HT_LINK_REG98 0x98 +#define HT_LINK_REGB8 0xB8 +#define HT_LINK_REGD8 0xD8 +#define HT_LINK_REGF8 0xF8 + +//Link Frequency Extension Register 0x9C/0xBC/0xDC/0xFC - 32 bits. +#define HT_LINK_REG9C 0x9C +#define HT_LINK_REGBC 0xBC +#define HT_LINK_REGDC 0xDC +#define HT_LINK_REGFC 0xFC + +//DRAM CS Base Address Register D18F2x40/x48/x50/x58 +#define DCT_REG40 0x40 +#define DCT_REG48 0x48 +#define DCT_REG50 0x50 +#define DCT_REG58 0x58 + +//DRAM Configuration Low Register D18F2x90/x91/x92/x93 +#define DCT_REG90 0x90 +#define DCT_REG91 0x91 +#define DCT_REG92 0x92 +#define DCT_REG93 0x93 + +#pragma pack(pop) + +#endif //#ifndef _AMD_SB700_H_ diff --git a/src/vendorcode/amd/cimx/sb700/SBCMN.c b/src/vendorcode/amd/cimx/sb700/SBCMN.c new file mode 100644 index 0000000..7d5b4f4 --- /dev/null +++ b/src/vendorcode/amd/cimx/sb700/SBCMN.c @@ -0,0 +1,572 @@ +/***************************************************************************** + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + ***************************************************************************/ + + +#include "Platform.h" + + +REG8MASK sbEarlyPostByteInitTable[]={ + // SMBUS Device(Bus 0, Dev 20, Func 0) + {0x00, SMBUS_BUS_DEV_FUN, 0}, + {SB_SMBUS_REG43, ~(UINT8)BIT3, 0x00}, //Make BAR registers of smbus visible. + {SB_SMBUS_REG24, 0X00, (CIMx_Version & 0xFF)}, //Program the version information + {SB_SMBUS_REG24+1, 0x00, (CIMx_Version >> 8)}, + {SB_SMBUS_REG24+2, 0x00, RC_Information}, + {SB_SMBUS_REG24+3, 0x00, Additional_Changes_Indicator}, + {SB_SMBUS_REG43, ~(UINT8)BIT3, BIT3}, //Make BAR registers of smbus invisible. + {SB_SMBUS_REGAE, ~(UINT8)(BIT6 + BIT5), BIT6 + BIT5}, //Disable Timer IRQ enhancement for proper operation of the 8254 timer. + // [6] - IoApicPicArbEn, set 1 to enable arbiter between APIC and PIC interrupts + {SB_SMBUS_REGAD, ~(UINT8)(BIT0+BIT1+BIT2+BIT4), BIT0+BIT3}, // Initialize SATA to default values, SATA Enabled, + // Combined mode enabled, SATA as primary, power saving enable + {SB_SMBUS_REGAF, 0xE3, 6 << 2}, // Set SATA Interrupt to INTG# + {SB_SMBUS_REG68, BIT3, 0 }, // First disable all usb controllers and then enable then according to setup selection + {0xFF, 0xFF, 0xFF}, + + // IDE Device(Bus 0, Dev 20, Func 1) + {0x00, IDE_BUS_DEV_FUN, 0}, + {SB_IDE_REG62+1, ~(UINT8)BIT0, BIT5}, // Enabling IDE Explicit Pre-Fetch IDE PCI Config 0x62[8]=0 + // Allow MSI capability of IDE controller to be visible. IDE PCI Config 0x62[13]=1 + {0xFF, 0xFF, 0xFF}, + + // Azalia Device(Bus 0, Dev 20, Func 2) + {0x00, AZALIA_BUS_DEV_FUN, 0}, + {SB_AZ_REG4C, ~(UINT8)BIT0, BIT0}, + {0xFF, 0xFF, 0xFF}, + + // LPC Device(Bus 0, Dev 20, Func 3) + {0x00, LPC_BUS_DEV_FUN, 0}, + + {SB_LPC_REG40, ~(UINT8)BIT2, BIT2}, // Enabling LPC DMA Function 0x40[2] + {SB_LPC_REG78, ~(UINT8)BIT1, 00}, // Disables MSI capability + {0xFF, 0xFF, 0xFF}, + + // P2P Bridge(Bus 0, Dev 20, Func 4) + {0x00, SBP2P_BUS_DEV_FUN, 0}, + + {SB_P2P_REG64+1, 0xFF, BIT7+BIT6}, //Adjusting CLKRUN#, PCIB_PCI_Config 0x64[15]=01 + //Enabling arbiter fix, PCIB_PCI_Config 0x64[14]=01 + {SB_P2P_REG64+2, 0xFF, BIT4}, //Enabling One-Prefetch-Channel Mode, PCIB_PCI_config 0x64 [20] + + {SB_P2P_REG0D, 0x00, 0x40}, //Setting Latency Timers to 0x40, Enables the PCIB to retain ownership + {SB_P2P_REG1B, 0x00, 0x40}, // of the bus on the Primary side and on the Secondary side when GNT# is deasserted. + + {0xFF, 0xFF, 0xFF}, + + // SATA Device(Bus 0, Dev 17, Func 0) + {0x00, SATA_BUS_DEV_FUN, 0}, + {SB_SATA_REG44, 0xff, BIT0}, // Enables the SATA watchdog timer register prior to the SATA BIOS post + {SB_SATA_REG40+3, 0xff, BIT5}, // RPR setting: Disable the testing/enhancement mode SATA_PCI_config 0x40 [29] = 1 + {SB_SATA_REG48+2, 0xff, BIT5}, // RPR setting: Disable the testing/enhancement mode SATA_PCI_config 0x48 [24] = 1, [21] = 1 + {SB_SATA_REG48+3, 0xff, BIT0}, + {SB_SATA_REG44 + 2, 0, 0x10}, // Program watchdog timer with 16 retries before timer time-out. + {0xFF, 0xFF, 0xFF}, +}; + + +REG8MASK sbEarlyPostPmioInitTbl[]={ + // index andmask ormask + {SB_PMIO_REG55, ~(UINT8)(BIT3+BIT4+BIT5), BIT5+BIT3}, //BIT3(PcieNative)=1b, BIT4(Pcie_Wak_Mask)=0b, BIT5(Pcie_WAK_Sci)=1b + {SB_PMIO_REG01, 0xff, BIT1}, + {SB_PMIO_REG0E, 0xff, BIT2 + BIT3}, + {SB_PMIO_REG10, 0x3E, (BIT6+BIT5+BIT3+BIT1)}, // RTC_En_En + TMR_En_En + GLB_EN_EN and clear EOS_EN + PciExpWakeDisEn + {SB_PMIO_REG61, 0xFF, 0x40}, // USB Device Support to Wakeup System from S3/S4 state, USB PME & PCI Act from NB + {SB_PMIO_REG59, 0xFC, 0x00 }, // Clear the flash controller bits BIT1:0 + {SB_PMIO_REG01, 0xFF, 0x97 }, // Clear all the status + {SB_PMIO_REG05, 0xFF, 0xFF }, + {SB_PMIO_REG06, 0xFF, 0xFF }, + {SB_PMIO_REG07, 0xFF, 0xFF }, + {SB_PMIO_REG0F, 0xFF, 0x1F }, + {SB_PMIO_REG1D, 0xFF, 0xFF }, + {SB_PMIO_REG39, 0xFF, 0xFF }, + {SB_PMIO_REG7C, ~(UINT8)(BIT5+BIT3+BIT2), BIT3+BIT2}, //Turn on BLink LED + {SB_PMIO_REG67, 0xFF, 0x06}, // C State enable, must be set in order to exercise C state + {SB_PMIO_REG68, 0x38, 0x84}, + {SB_PMIO_REG8D, 0xFF, 0x01}, // Set PM_Reg_0x8D[0] to enable PmeTurnOff/PmeMsgAck handshake to fix PCIE LAN S3/S4 wake failure + {SB_PMIO_REG84, 0xFD, BIT3+BIT0}, + {SB_PMIO_REG53, 0xFF, BIT7+BIT6}, //ACPI System Clock setting, PMIO Reg 0x53[6]=1. Our reference clock + //is either 25 or 100Mhz and so the default acpi clock is actually + //running at 12.5Mhz and so the system time will run slow. We have + //generated another internal clock which runs at 14.318Mhz which is the + //correct frequency. We should set this bit to turn on this feature PMIO_REG53[6]=1 + //PCI Clock Period, PM_IO 0x53 [7] = 1. By setting this, PCI clock period + //increase to 30.8 ns. + {SB_PMIO_REG95, ~(UINT8)(BIT2+BIT1+BIT0), BIT2+BIT1}, //USB Advanced Sleep Control, Enables USB EHCI controller + //to sleep for 6 uframes in stead of the standard 10us to + //improve power saving. + {SB_PMIO_REGD7, 0xFF, BIT6+BIT1}, + +}; + + +// commonInitEarlyBoot - set /SMBUS/ACPI/IDE/LPC/PCIB. This settings should be done during S3 resume also +void commonInitEarlyBoot(AMDSBCFG* pConfig) { + UINT16 dwTempVar; + CPUID_DATA CpuId; + CPUID_DATA CpuId_Brand; + UINT8 dbValue; + UINT32 ddValue; + UINT8 Family, Model, Stepping; + + TRACE((DMSG_SB_TRACE, "CIMx - Entering commonInitEarlyBoot \n")); + CpuidRead (0x01, &CpuId); + CpuidRead (0x80000001, &CpuId_Brand); //BrandID + + //Early post initialization of pci config space + programPciByteTable( (REG8MASK*)FIXUP_PTR(&sbEarlyPostByteInitTable[0]), sizeof(sbEarlyPostByteInitTable)/sizeof(REG8MASK) ); + + // RPR 5.5 Clear PM_IO 0x65[4] UsbResetByPciRstEnable, Set this bit so that usb gets reset whenever there is PCIRST. + RWPMIO(SB_PMIO_REG65, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT4, BIT4); + + + #if 0 //KZ [083011]-It's used wrong BIOS SIZE for Coreboot. + //For being compatible with earlier revision, check whether ROM decoding is changed already outside CIMx before + //changing it. + ReadPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG68, AccWidthUint16 | S3_SAVE, &dwTempVar); + if ( (dwTempVar == 0x08) || (dwTempVar == 0x00)) + RWPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG68, AccWidthUint8 | S3_SAVE, 0, 0x0E);// Change the 1Mb below ROM decoding range to 0xE0000 to 0xFFFFF + #endif + + if (pConfig->AzaliaController == 1) + RWPMIO(SB_PMIO_REG59, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT3, 0); + else + RWPMIO(SB_PMIO_REG59, AccWidthUint8 | S3_SAVE, 0xFF, BIT3); + + //Disable or Enable PCI Clks based on input + RWPCI((SBP2P_BUS_DEV_FUN << 16) + SB_P2P_REG42, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT5+BIT4+BIT3+BIT2), ((pConfig->PciClks) & 0x0F) << 2 ); + RWPCI((SBP2P_BUS_DEV_FUN << 16) + SB_P2P_REG4A, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT1+BIT0), ((pConfig->PciClks) >> 4) | ((pConfig->PciClk5) << 1) ); + ReadPMIO(SB_PMIO_REG2C, AccWidthUint16, &dwTempVar); // Read Arbiter address, Arbiter address is in PMIO 2Ch + RWIO(dwTempVar, AccWidthUint8, 0, 0); // Write 0 to enable the arbiter + + abLinkInitBeforePciEnum(pConfig); // Set ABCFG registers + // Set LDTSTP# duration to 10us for HydraD CPU model 8, 9 or A; or when HT link is 200MHz; or Family15 Orochi CPU C32/G34 package + ddValue = CpuId.REG_EAX & 0x00FF00F0; + dbValue = 1; + + if((CpuId.REG_EAX & 0x00F00F00) == 0x00600F00) { + if(((CpuId_Brand.REG_EBX & 0xF0000000) == 0x30000000) || ((CpuId_Brand.REG_EBX & 0xF0000000) == 0x50000000)) { + //Orochi processor G34/C32, set to 10us + dbValue = 10; + } + else { + // Orochi processor AM3, set to 5us + dbValue = 5; + } + } + + if ((pConfig->AnyHT200MhzLink) || (ddValue == 0x100080) || (ddValue == 0x100090) || (ddValue == 0x1000A0)) { + //any kind of CPU run HT at 200Mhz , or HydraD CPU model 8, 9 or A, set to 10us + dbValue = 10; + } + + + RWPMIO(SB_PMIO_REG8B, AccWidthUint8 | S3_SAVE, 0x00, dbValue); + + // Enable/Disable watchdog timer + RWPMIO(SB_PMIO_REG69, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT0, (UINT8)(!pConfig->WatchDogTimerEnable)); + + // Per SB700/SP5100 RPR 2.5 + // + // Enable C1e stutter timer for any system with chip revision >= A14 + // Set SMBUS:0x5c[22:16] = 16 -- Set amount of idle time to 16ms + // + + if (getRevisionID() >= SB700_A14) { + dwTempVar = 0x0010; + + // Set PMIO:0xcb[5] = 1 -- AutoStutterTimerEn, set 1 to enable + // Set PMIO:0xcb[6] = 1 -- AutoStutterTimeSel, 1=1ms timer tick increment; 0=2us increment + RWPMIO(SB_PMIO_REGCB, AccWidthUint8 | S3_SAVE, 0xff, BIT6 + BIT5); + + Family = (UINT8)((CpuId.REG_EAX & 0x00ff0000)>> 16); + Model = (UINT8)((CpuId.REG_EAX & 0x000000f0)>> 4); + Stepping = (UINT8) (CpuId.REG_EAX & 0x0000000f); + + // For Server system (SP5100) with CPU type = Family 10h with LS2 mode enabled: + // Model=6 && Stepping=2 || Model=(4I5|6) && Stepping >=3 || Model=(8|9) && Stepping >= 1 || Model Ah + // Set SMBUS:0x5c[22:16] = 20 -- Set amount of idle time to 20ms + if (IsLs2Mode() && (Family == 0x10)) { + switch( Model ){ + case 0x4: + case 0x5: + if( Stepping >= 3 ) dwTempVar = 0x14; + break; + case 0x6: + if( Stepping >= 2 ) dwTempVar = 0x14; + break; + case 0x8: + if( Stepping >= 1 ) dwTempVar = 0x14; + break; + case 0x9: + if( Stepping >= 1 ) dwTempVar = 0x14; + break; + case 0xA: + dwTempVar = 0x14; + break; + } + } + // Set SMBUS:0x5c[7] = 1 -- CheckC3, set 1 to check for C3 state + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG5C, AccWidthUint32 | S3_SAVE, ~(0x7F << 16), (dwTempVar << 16) + BIT7); + } + + //Message-Triggered C1E is not supported in Family 10h G34r1 HY-D0 (0x00100F90) and Family 10h C32 HY-D0 (0x00100F80) processor. + ddValue = CpuId.REG_EAX; + if ((getRevisionID() == SB700_A15) && (pConfig->MTC1e == CIMX_OPTION_ENABLED) && (ddValue != 0x00100F90) && (ddValue != 0x00100F80)) { + // + // MTC1e: For A15 (server only) - The settings here borrow the existing legacy ACPI BM_STS and BM_RLD bits as a + // mechanism to break out from C1e under a non-OS controlled C3 state. Under this scheme, the logic will automatically + // clear the BM_STS bit whenever it enters C1e state. Whenever BM_REQ#/IDLE_EXIT# is detected, it will cause the + // BM_STS bit to be set and therefore causing the C state logic to exit. + // + // Set BMReqEnable (SMBUS:0x64[5]=1) to enable the pin as BM_REQ#/IDLE_EXIT# to the C state logic + // Set CheckOwnReq (SMBUS:0x64[4]=0) to force IDLE_EXIT# to set BM_STS and wake from C3 + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG64, AccWidthUint8 | S3_SAVE, 0xEF, BIT5); + + // Set PCI_Active_enable (PMIO:0x61[2]=1), the secondary enable bit for SB to monitor BM_REQ#/IDLE_EXIT# + RWPMIO(SB_PMIO_REG61, AccWidthUint8 | S3_SAVE, 0xff, BIT2); + + // Set auto_bm_rld (PMIO:0x9a[4]=1) so that assertion on BM_REQ#/IDLE_EXIT# pin will cause C state logic to break out from C1e + // Set auto_clr_bm_sts (PMIO:0x9a[5]=1) will cause the C state logic to automatically clear the BM_STS bit whenever it sees a C1e entry + RWPMIO(SB_PMIO_REG9A, AccWidthUint8 | S3_SAVE, 0xff, BIT5 + BIT4); + + + // MTC1e: The logic basically counts the number of HALT_ENTER messages. When it has received the number of HALT_ENTER + // messages equal to NumOfCpu (PMIO:0xc9[3:0]), it will generate an internal C1e command to the C state logic. + // The count increments when it sees HALT_ENTER message after it has generated the C1e command, and it treats the + // HALT_EXIT message as a break event. + // + // Set ServerCEn + RWPMIO(SB_PMIO_REGBB, AccWidthUint8 | S3_SAVE, 0xFF, BIT7); + + // Enable counting HALT + // PMIO:0xc9[4] = CountHaltMsgEn + // PMIO:0xc9[3:0] = NumOfCpu, set to 1 since CPU logic will coordinate among cores and only generate one HALT message + RWPMIO(SB_PMIO_REGC9, AccWidthUint8 | S3_SAVE, 0xE0, BIT4 + 1); + } + + c3PopupSetting(pConfig); + + TRACE((DMSG_SB_TRACE, "CIMx - Exiting commonInitEarlyBoot \n")); +} + + +void commonInitEarlyPost(AMDSBCFG* pConfig){ + //early post initialization of pmio space + programPmioByteTable( (REG8MASK *)FIXUP_PTR(&sbEarlyPostPmioInitTbl[0]), (sizeof(sbEarlyPostPmioInitTbl)/sizeof(REG8MASK)) ); + CallBackToOEM(PULL_UP_PULL_DOWN_SETTINGS, NULL, pConfig); +} + + +// AB-Link Configuration Table +ABTBLENTRY abTblEntry600[]={ + // Enabling Downstream Posted Transactions to Pass Non-Posted Transactions for the K8 Platform ABCFG 0x10090[8] = 1 + // ABCFG 0x10090 [16] = 1, ensures the SMI# message to be sent before the IO command is completed. The ordering of + // SMI# and IO is important for the IO trap to work properly. + {ABCFG,SB_AB_REG10090 ,BIT16+BIT8 ,BIT16+BIT8 }, + // Enabling UpStream DMA Access AXCFG: 0x04[2]=1 + {AXCFG,SB_AB_REG04 ,BIT2 ,BIT2 }, + // Setting B-Link Prefetch Mode ABCFG 0x80 [17] = 1 ABCFG 0x80 [18] = 1 + {ABCFG,SB_AB_REG80 ,BIT17+BIT18 ,BIT17+BIT18 }, + // Disable B-Link client's credit variable in downstream arbitration equation (for All Revisions) + // ABCFG 0x9C[0] = 1 Disable credit variable in downstream arbitration equation + // Enabling Additional Address Bits Checking in Downstream Register Programming + // ABCFG 0x9C[1] = 1 + {ABCFG,SB_AB_REG9C ,BIT8+BIT1+BIT0 ,BIT8+BIT1+BIT0 }, + // Enabling IDE/PCIB Prefetch for Performance Enhancement + // IDE prefetch ABCFG 0x10060 [17] = 1 ABCFG 0x10064 [17] = 1 + // PCIB prefetch ABCFG 0x10060 [20] = 1 ABCFG 0x10064 [20] = 1 + {ABCFG,SB_AB_REG10060 ,BIT17+BIT20 ,BIT17+BIT20 }, // IDE+PCIB prefetch enable + {ABCFG,SB_AB_REG10064 ,BIT17+BIT20 ,BIT17+BIT20 }, // IDE+PCIB prefetch enable + // Enabling Detection of Upstream Interrupts ABCFG 0x94 [20] = 1 + // ABCFG 0x94 [19:0] = cpu interrupt delivery address [39:20] + {ABCFG,SB_AB_REG94 ,BIT20 ,BIT20+0x00FEE }, + // Programming cycle delay for AB and BIF clock gating + // Enabling AB and BIF Clock Gating + // Enabling AB Int_Arbiter Enhancement + // Enabling Requester ID + {ABCFG,SB_AB_REG10054, 0x00FFFFFF , 0x010407FF }, + {ABCFG,SB_AB_REG98 , 0xFFFF00FF , 0x00014700 }, // Enable the requestor ID for upstream traffic ABCFG 0x98[16]=1 +// {ABCFG,SB_AB_REG54 , 0x00FF0000 , 0x01040000 }, + {ABCFG,SB_AB_REG54 , 0x00FF0000 , 0x00040000 }, + + {ABCFG,0,0,-1}, // This dummy entry is to clear ab index + {-1, -1, -1, -1 }, +}; + + +// AB-Link Configuration Table +ABTBLENTRY abTblForA15[]={ + + //SMI Reordering fix + {ABCFG, SB_AB_REG90 ,BIT21 , BIT21 }, + {ABCFG, SB_AB_REG9C ,BIT15+BIT9+BIT5 ,BIT15+BIT9+BIT5}, + + //Posted pass NP Downstream feature + {AX_INDXC, SB_AB_REG02, BIT9 ,BIT9 }, + {ABCFG, SB_AB_REG9C, BIT14+BIT13+BIT12+BIT11+BIT10+BIT7+BIT6 , BIT14+BIT13+BIT12+BIT11+BIT10+BIT7+BIT6}, + {ABCFG, SB_AB_REG1009C, BIT5+BIT4 , BIT5+BIT4}, + + //Posted pass NP upstream feature + {ABCFG, SB_AB_REG58, BIT15+BIT14+BIT13+BIT12+BIT11, BIT15+BIT14+BIT13+BIT11}, + + //64 bit Non-posted memory write support + {AX_INDXC, SB_AB_REG02, BIT10 ,BIT10 }, + + {ABCFG, SB_AB_REG10090, BIT12+BIT11+BIT10+BIT9 , BIT12+BIT11+BIT10+BIT9}, + + {ABCFG,0,0,-1}, // This dummy entry is to clear ab index + {-1, -1, -1, -1 }, +}; + + +// abLinkInitBeforePciEnum - Set ABCFG registers +void abLinkInitBeforePciEnum(AMDSBCFG* pConfig){ + ABTBLENTRY *pAbTblPtr; + + // disable PMIO decoding when AB is set + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG64, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT2, 0); + + pAbTblPtr = (ABTBLENTRY *)FIXUP_PTR(&abTblEntry600[0]); + abcfgTbl(pAbTblPtr); + + if (getRevisionID() > SB700_A11){ + //Enable OHCI Prefetch + writeAlink( (SB_AB_REG80 | (ABCFG << 30)), (readAlink((SB_AB_REG80 | (ABCFG << 30)))) | BIT0); + //Register bit to maintain correct ordering of SMI and IO write completion + writeAlink( (SB_AB_REG8C | (ABCFG << 30)), (readAlink((SB_AB_REG8C | (ABCFG << 30)))) | BIT8); + } + + if (getRevisionID() >= SB700_A14){ + //Enable fix for TT SB01345 + writeAlink( (SB_AB_REG90 | (ABCFG << 30)), (readAlink((SB_AB_REG90 | (ABCFG << 30)))) | BIT17); + //Disable IO Write and SMI ordering enhancement + writeAlink( (SB_AB_REG9C | (ABCFG << 30)), (readAlink((SB_AB_REG9C | (ABCFG << 30)))) & (0xFFFFFEFF)); + } + + if (getRevisionID() >= SB700_A15) { + pAbTblPtr = (ABTBLENTRY *)FIXUP_PTR(&abTblForA15[0]); + abcfgTbl(pAbTblPtr); + } + + + // enable pmio decoding after ab is configured + // or BYTE PTR es:[ebp+SMBUS_BUS_DEV_FUN shl 12 + SB_SMBUS_REG64], BIT2 + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG64, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT2, BIT2); +} + + +void abcfgTbl(ABTBLENTRY* pABTbl){ + UINT32 ddValue; + + while ((pABTbl->regType) != 0xFF){ + TRACE((DMSG_SB_TRACE, "RegType: %X, RegNumber:%X, AndMask=%X, OrMask=%X \n",pABTbl->regType , pABTbl->regIndex, pABTbl->regMask, pABTbl->regData)); + if (pABTbl->regType > AX_INDXP){ + ddValue = pABTbl->regIndex | (pABTbl->regType << 30); + writeAlink(ddValue, ((readAlink(ddValue)) & (0xFFFFFFFF^(pABTbl->regMask)))|pABTbl->regData); + } + else{ + ddValue = 0x30 | (pABTbl->regType << 30); + writeAlink(ddValue, pABTbl->regIndex); + ddValue = 0x34 | (pABTbl->regType << 30); + writeAlink(ddValue, ((readAlink(ddValue)) & (0xFFFFFFFF^(pABTbl->regMask)))|pABTbl->regData); + } + ++pABTbl; + } + + //Clear ALink Access Index + ddValue = 0; + WriteIO(ALINK_ACCESS_INDEX, AccWidthUint32 | S3_SAVE, &ddValue); + TRACE((DMSG_SB_TRACE, "Exiting abcfgTbl\n")); +} + + +// programSubSystemIDs - Config Subsystem ID for all SB devices. +void programSubSystemIDs(AMDSBCFG* pConfig, BUILDPARAM *pStaticOptions){ + UINT32 ddTempVar; + UINT16 dwDeviceId; + + RWPCI((USB1_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->Ohci0Ssid); + RWPCI((USB1_OHCI1_BUS_DEV_FUN << 16) + SB_OHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->Ohci1Ssid); + RWPCI((USB2_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->Ohci2Ssid); + RWPCI((USB2_OHCI1_BUS_DEV_FUN << 16) + SB_OHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->Ohci3Ssid); + RWPCI((USB3_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->Ohci4Ssid); + + RWPCI((USB1_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->Ehci0Ssid); + RWPCI((USB2_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->Ehci1Ssid); + + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->SmbusSsid); + RWPCI((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->IdeSsid); + RWPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->LpcSsid); + RWPCI((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->AzaliaSsid); + + ddTempVar = pStaticOptions->SataIDESsid; + if ( ((pConfig->SataClass) == AHCI_MODE) || ((pConfig->SataClass)== IDE_TO_AHCI_MODE) ) + ddTempVar = pStaticOptions->SataAHCISsid; + + ReadPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG02), AccWidthUint16 | S3_SAVE, &dwDeviceId); + if ((pConfig->SataClass) == RAID_MODE){ + ddTempVar = pStaticOptions->SataRAIDSsid; + if (dwDeviceId==SB750_SATA_DEFAULT_DEVICE_ID) + ddTempVar = pStaticOptions->SataRAID5Ssid; + } + + if ( ((pConfig->SataClass) == AMD_AHCI_MODE) || ((pConfig->SataClass) == IDE_TO_AMD_AHCI_MODE) ) { + ddTempVar = pStaticOptions->SataAHCISsid; + } + RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG2C, AccWidthUint32 | S3_SAVE, 0x00, ddTempVar); +} + +void commonInitLateBoot(AMDSBCFG* pConfig){ + UINT8 dbValue; + UINT32 ddVar; + + // We need to do the following setting in late post also because some bios core pci enumeration changes these values + // programmed during early post. + // RPR 4.5 Master Latency Timer + // Master Latency Timer PCIB_PCI_config 0x0D/0x1B = 0x40 + // Enables the PCIB to retain ownership of the bus on the + // Primary side and on the Secondary side when GNT# is deasserted. + //mov BYTE PTR es:[ebp+SBP2P_BUS_DEV_FUN shl 12 + SB_P2P_REG0D], 40h + //mov BYTE PTR es:[ebp+SBP2P_BUS_DEV_FUN shl 12 + SB_P2P_REG1B], 40h + dbValue = 0x40; + WritePCI((SBP2P_BUS_DEV_FUN << 16) + SB_P2P_REG0D, AccWidthUint8, &dbValue); + WritePCI((SBP2P_BUS_DEV_FUN << 16) + SB_P2P_REG1B, AccWidthUint8, &dbValue); + + //SB P2P AutoClock control settings. + ddVar = (pConfig->PcibAutoClkCtrlLow) | (pConfig->PcibAutoClkCtrlLow); + WritePCI((SBP2P_BUS_DEV_FUN << 16) + SB_P2P_REG4C, AccWidthUint32, &ddVar); + ddVar = (pConfig->PcibClkStopOverride); + RWPCI((SBP2P_BUS_DEV_FUN << 16) + SB_P2P_REG50, AccWidthUint16, 0x3F, (UINT16) (ddVar << 6)); + + if (pConfig->MobilePowerSavings){ + //If RTC clock is not driven to any chip, it should be shut-off. If system uses external RTC, then SB needs to + //drive out RTC clk to external RTC chip. If system uses internal RTC, then this clk can be shut off. + RWPMIO(SB_PMIO_REG68, AccWidthUint8, ~(UINT32)BIT4, (pConfig->ExternalRTCClock)<<4); + if (!getClockMode()){ + if (!(pConfig->UsbIntClock) ){ + //If the external clock is used, the second PLL should be shut down + RWPMIO(SB_PMIO_REGD0, AccWidthUint8, 0xFF, BIT0); + // If external clock mode is used, the 25Mhz oscillator buffer can be turned-off by setting PMIO 0xD4[7]=1 + RWPMIO(SB_PMIO_REGD4, AccWidthUint8, 0xFF, BIT7); + //Disable unused clocks + RWPMIO(SB_PMIO_REGCA, AccWidthUint8, 0xFF, 0x7E); + } + } + writeAlink(0x30, SB_AB_REG40); + writeAlink(0x34, ((readAlink(0x34)) & 0xFFFF0000) | 0x008A); + + } + else{ + //Don't shutoff RTC clock + RWPMIO(SB_PMIO_REG68, AccWidthUint8, ~(UINT32)BIT4, 0); + //Dont disable second PLL + RWPMIO(SB_PMIO_REGD0, AccWidthUint8, ~(UINT32)BIT0, 0); + //Enable the 25Mhz oscillator + RWPMIO(SB_PMIO_REGD4, AccWidthUint8, ~(UINT32)BIT7, 0); + RWPMIO(SB_PMIO_REGCA, AccWidthUint8, 0xFF, 0x00); + } +} + + +void +hpetInit (AMDSBCFG* pConfig, BUILDPARAM *pStaticOptions) +{ + DESCRIPTION_HEADER* pHpetTable; + + if (pConfig->HpetTimer == 1) { + UINT8 dbTemp; + + RWPMIO(SB_PMIO_REG9A, AccWidthUint8, 0xFF, BIT7); + // Program the HPET BAR address + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGB4, AccWidthUint32 | S3_SAVE, 0, pStaticOptions->HpetBase); + + // Enable HPET MMIO decoding: SMBUS:0x43[4] = 1 + // Enable HPET MSI support only when HpetMsiDis == 0 + dbTemp = (pConfig->HpetMsiDis)? BIT4 : BIT7 + BIT6 + BIT5 + BIT4; + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG43, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT3, dbTemp); + // Program HPET default clock period + if (getRevisionID() >= SB700_A13) { + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG34, AccWidthUint32 | S3_SAVE, 0x00, 0x429B17E); + } + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG43, AccWidthUint8 | S3_SAVE, 0xFF, BIT3); + // Enable High Precision Event Timer (also called Multimedia Timer) interrupt + RWPCI((SMBUS_BUS_DEV_FUN << 16) + (SB_SMBUS_REG64+1), AccWidthUint8 | S3_SAVE, ~(UINT32)BIT2, BIT2); + } + else { + if (!(pConfig->S3Resume)) { +// pHpetTable = (DESCRIPTION_HEADER*)ACPI_LocateTable('TEPH'); + pHpetTable = (DESCRIPTION_HEADER*)ACPI_LocateTable(Int32FromChar ('T', 'E', 'P', 'H')); + if (pHpetTable != NULL) { +// pHpetTable->Signature = 'HPET'; + pHpetTable->Signature = Int32FromChar ('T', 'E', 'P', 'H'); + } + } + } +} + + +void c3PopupSetting(AMDSBCFG* pConfig){ + UINT8 dbTemp; + CPUID_DATA CpuId; + + CpuidRead (0x01, &CpuId); + //RPR 2.3 C-State and VID/FID Change + dbTemp = GetNumberOfCpuCores(); + if (dbTemp > 1){ + //PM_IO 0x9A[5]=1, For system with dual core CPU, set this bit to 1 to automatically clear BM_STS when the C3 state is being initiated. + //PM_IO 0x9A[4]=1, For system with dual core CPU, set this bit to 1 and BM_STS will cause C3 to wakeup regardless of BM_RLD + //PM_IO 0x9A[2]=1, Enable pop-up for C3. For internal bus mastering or BmReq# from the NB, the SB will de-assert + //LDTSTP# (pop-up) to allow DMA traffic, then assert LDTSTP# again after some idle time. + RWPMIO(SB_PMIO_REG9A, AccWidthUint8, 0xFF, BIT5+BIT4+BIT2); + } + + //SB700 needs to changed for RD790 support + //PM_IO 0x8F [4] = 0 for system with RS690 + //Note: RS690 north bridge has AllowLdtStop built for both display and PCIE traffic to wake up the HT link. + //BmReq# needs to be ignored otherwise may cause LDTSTP# not to toggle. + //PM_IO 0x8F[5]=1, Ignore BM_STS_SET message from NB + RWPMIO(SB_PMIO_REG8F, AccWidthUint8, ~(UINT32)(BIT5+BIT4), BIT5); + + //LdtStartTime = 10h for minimum LDTSTP# de-assertion duration of 16us in StutterMode. This is to guarantee that + //the HT link has been safely reconnected before it can be disconnected again. If C3 pop-up is enabled, the 16us also + //serves as the minimum idle time before LDTSTP# can be asserted again. This allows DMA to finish before the HT + //link is disconnected. + //Increase LDTSTOP Deassertion time for SP5100 to 20us, SB700 remains the same + dbTemp = (IsServer())? 0x14 : 0x10; + RWPMIO(SB_PMIO_REG88, AccWidthUint8, 0x00, dbTemp); + + //This setting provides 16us delay before the assertion of LDTSTOP# when C3 is entered. The + //delay will allow USB DMA to go on in a continous manner + RWPMIO(SB_PMIO_REG89, AccWidthUint8, 0x00, 0x10); + + //Set this bit to allow pop-up request being latched during the minimum LDTSTP# assertion time + RWPMIO(SB_PMIO_REG52, AccWidthUint8, 0xFF, BIT7); + +} + diff --git a/src/vendorcode/amd/cimx/sb700/SBCMNLIB.c b/src/vendorcode/amd/cimx/sb700/SBCMNLIB.c new file mode 100644 index 0000000..130dbc4 --- /dev/null +++ b/src/vendorcode/amd/cimx/sb700/SBCMNLIB.c @@ -0,0 +1,108 @@ +/***************************************************************************** + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + ***************************************************************************/ + + +#include "Platform.h" + +UINT8 isEcPresent(){ + UINT8 dbFlag; + UINT16 dwVar0; + + //Read the EC configuration register base address from LPCCfg_A4[15:1] + //Write 0x5A to the EC config index register to unlock the access + //Write 0x20 to the EC config index register to select the device ID register + //Read the value of device ID register from the EC config data register + //If the value read is 0xB7, then EC is enabled. + //Write 0xA5 to re-lock the EC config index register if EC is enabled. + + ReadPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4, AccWidthUint16 | S3_SAVE, &dwVar0); + dwVar0 &= 0xFFFE; + RWIO(dwVar0, AccWidthUint8, 0, 0x5A); + RWIO(dwVar0, AccWidthUint8, 0, 0x20); + ReadIO(dwVar0+1, AccWidthUint8, &dbFlag); + RWIO(dwVar0, AccWidthUint8, 0, 0xA5); + + return ( dbFlag == 0xB7); +} + +void +getSbInformation ( +SB_INFORMATION *sbInfo){ + UINT16 dwDevId; + UINT8 dbRev; + + ReadPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG02, AccWidthUint16 | S3_SAVE, &dwDevId); + ReadPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG08, AccWidthUint8 | S3_SAVE, &dbRev); + sbInfo->sbModelMask = SB_MODEL_UNKNOWN; + if ( (dwDevId == SB7XX_DEVICE_ID) && (dbRev <= SB_Rev_Sb7xx_A14) ){ + sbInfo->sbModelMask |= SB_MODEL_SB700; + sbInfo->sbModelMask |= SB_MODEL_SR5690; + sbInfo->sbRev = dbRev; + ReadPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG9C, AccWidthUint8 | S3_SAVE, &dbRev); + if (dbRev & 01) + sbInfo->sbModelMask |= SB_MODEL_SB750; + if (isEcPresent()) + sbInfo->sbModelMask |= SB_MODEL_SB710; + return; + } +} + + +SB_CAPABILITY_SETTING +getSbCapability ( +SB_CAPABILITY_ITEM sbCapabilityItem +) +{ + SB_CAPABILITY_SETTING sbCapSetting=SB_UNKNOWN; + UINT32 ddTemp0; + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG43, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT3, 00); + ReadPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG10, AccWidthUint32, &ddTemp0); + + if (sbCapabilityItem < Sb_Unknown_Capability) + sbCapSetting = ((ddTemp0 >> (sbCapabilityItem << 1) ) & 0x03); + + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG43, AccWidthUint8 | S3_SAVE, 0xFF, BIT3); + return sbCapSetting; +} + + +void +setSbCapability ( +SB_CAPABILITY_ITEM sbCapabilityItem, SB_CAPABILITY_SETTING sbCapSetting +) +{ + UINT32 ddTemp0; + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG43, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT3, 00); + ReadPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG10, AccWidthUint32, &ddTemp0); + if ( (sbCapabilityItem < Sb_Unknown_Capability) & (sbCapSetting < Sb_Cap_Setting_Unknown) ) + ddTemp0 = (ddTemp0 & ~(0x03 << (sbCapabilityItem << 1))) | ( (sbCapSetting & 0x03) << (sbCapabilityItem << 1)); + WritePCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG10, AccWidthUint32, &ddTemp0); + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG43, AccWidthUint8 | S3_SAVE, 0xFF, BIT3); +} diff --git a/src/vendorcode/amd/cimx/sb700/SBCMNLIB.h b/src/vendorcode/amd/cimx/sb700/SBCMNLIB.h new file mode 100644 index 0000000..e737bc9 --- /dev/null +++ b/src/vendorcode/amd/cimx/sb700/SBCMNLIB.h @@ -0,0 +1,89 @@ +/*;******************************************************************************** +; +; Copyright (C) 2012 Advanced Micro Devices, Inc. +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; * Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; * Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution. +; * Neither the name of Advanced Micro Devices, Inc. nor the names of +; its contributors may be used to endorse or promote products derived +; from this software without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;*********************************************************************************/ + +#ifndef _AMD_SBLIB_H_ +#define _AMD_SBLIB_H_ + +//SB7xx Family +#define SB7xx_DEVICE_ID 0x4385 +#define SB700 0x00 +#define SB750 0x01 +#define SB710 0x02 + +//SB800 Family +#define SB800 0x10 + +#define SB_UNKNOWN 0xFF + +//SB700 Revision IDs +#define SB700_A11 0x39 +#define SB700_A12 0x3A +#define SB700_A13 0x3B +#define SB700_A14 0x3C + +#define SB_Rev_Sb7xx_A11 0x39 +#define SB_Rev_Sb7xx_A12 0x3A +#define SB_Rev_Sb7xx_A13 0x3B +#define SB_Rev_Sb7xx_A14 0x3C + + +typedef enum { + Sb_Raid0_1_Capability, /// + Sb_Raid5_Capability, /// + Sb_Ahci_Capability, /// + Sb_Unknown_Capability +} SB_CAPABILITY_ITEM; + + +typedef enum { + Sb_Cap_Setting_Auto, + Sb_Cap_Setting_Enabled, + Sb_Cap_Setting_Disabled, + Sb_Cap_Setting_Unknown +} SB_CAPABILITY_SETTING; + + +#define SB_MODEL_SB700 BIT0 +#define SB_MODEL_SB750 BIT1 +#define SB_MODEL_SB710 BIT2 +#define SB_MODEL_SR5690 BIT3 +#define SB_MODEL_UNKNOWN BIT31 + +typedef struct +{ + UINT32 sbModelMask; + UINT8 sbRev; +}SB_INFORMATION; + + +void getSbInformation (SB_INFORMATION *sbInfo); +SB_CAPABILITY_SETTING getSbCapability (SB_CAPABILITY_ITEM sbCapabilityItem); +void setSbCapability (SB_CAPABILITY_ITEM sbCapabilityItem, SB_CAPABILITY_SETTING sbCapSetting); + +#endif //#ifndef _AMD_SBLIB_H_ diff --git a/src/vendorcode/amd/cimx/sb700/SBDEF.h b/src/vendorcode/amd/cimx/sb700/SBDEF.h new file mode 100644 index 0000000..01fc1b5 --- /dev/null +++ b/src/vendorcode/amd/cimx/sb700/SBDEF.h @@ -0,0 +1,166 @@ +/*;******************************************************************************** +; +; Copyright (C) 2012 Advanced Micro Devices, Inc. +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; * Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; * Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution. +; * Neither the name of Advanced Micro Devices, Inc. nor the names of +; its contributors may be used to endorse or promote products derived +; from this software without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;*********************************************************************************/ + +#ifndef _AMD_SBDEF_H_ +#define _AMD_SBDEF_H_ + +//AMD Library Routines + +UINT64 +MsrRead ( + IN UINT32 MsrAddress + ); + +VOID +MsrWrite ( + IN UINT32 MsrAddress, + IN UINT64 Value + ); + +void ReadIO(UINT16 Address, UINT8 OpFlag, void *Value); +void WriteIO(UINT16 Address, UINT8 OpFlag, void *Value); +void ReadPCI(UINT32 Address, UINT8 OpFlag, void *Value); +void WritePCI(UINT32 Address,UINT8 OpFlag, void *Value); +void RWPCI(UINT32 Address,UINT8 OpFlag,UINT32 Mask,UINT32 Data); +void ReadIndexPCI32(UINT32 PciAddress,UINT32 IndexAddress,void* Value); +void WriteIndexPCI32(UINT32 PciAddress,UINT32 IndexAddress,UINT8 OpFlag,void* Value); +void RWIndexPCI32(UINT32 PciAddress,UINT32 IndexAddress,UINT8 OpFlag,UINT32 Mask,UINT32 Data); +void RWIO (UINT16 Address, UINT8 OpFlag, UINT32 Mask, UINT32 Data); +void ReadMEM(UINT32 Address,UINT8 OpFlag, void* Value); +void WriteMEM(UINT32 Address,UINT8 OpFlag, void* Value); +void RWMEM(UINT32 Address,UINT8 OpFlag,UINT32 Mask,UINT32 Data); +UINT32 IsFamily10(void); +UINT64 ReadMSR(UINT32 Address); +void WriteMSR(UINT32 Address,UINT64 Value); +void RWMSR(UINT32 Address, UINT64 Mask, UINT64 Value); +void* LocateImage(UINT32 Signature); +void* CheckImage( UINT32 Signature, void* ImagePtr); +void Stall(UINT32 uSec); +void Reset(void); +CIM_STATUS RWSMBUSBlock(UINT8 Controller, UINT8 Address, UINT8 Offset, UINT8 BufferSize, UINT8* BufferPrt); +void InitSerialOut(void); +void ReadPMIO(UINT8 Address, UINT8 OpFlag, void* Value); +void WritePMIO(UINT8 Address, UINT8 OpFlag, void* Value); +void RWPMIO(UINT8 Address, UINT8 OpFlag, UINT32 AndMask, UINT32 OrMask); +void ReadPMIO2(UINT8 Address, UINT8 OpFlag, void* Value); +void WritePMIO2(UINT8 Address, UINT8 OpFlag, void* Value); +void RWPMIO2(UINT8 Address, UINT8 OpFlag, UINT32 AndMask, UINT32 OrMask); +void outPort80(UINT32 pcode); +UINT8 GetNumberOfCpuCores(void); +UINT8 ReadNumberOfCpuCores(void); +UINT8 GetByteSum(void* pData, UINT32 Length); +UINT32 readAlink(UINT32 Index); +void writeAlink(UINT32 Index,UINT32 Data); + +//---------------------------------------------------------------------------------------------- +//---------------------------------------------------------------------------------------------- +void azaliaInitAfterPciEnum (AMDSBCFG* pConfig); + +void SendBytePort(UINT8 Data); +void SendStringPort(char* pstr); +void ItoA(UINT32 Value,int Radix,char* pstr); +AMDSBCFG* getConfigPointer(void); +void saveConfigPointer(AMDSBCFG* pConfig); + + +UINT32 GetFixUp(void); + +void sataInitAfterPciEnum(AMDSBCFG* pConfig); +void sataInitBeforePciEnum(AMDSBCFG* pConfig); +void sataInitLatePost(AMDSBCFG* pConfig); +void sataDriveDetection(AMDSBCFG* pConfig, UINT32 ddBar5); +void sataPhyWorkaround(AMDSBCFG* pConfig, UINT32 ddBar5); +void forceOOB(UINT32 ddBar5); +void shutdownUnconnectedSataPortClock(AMDSBCFG* pConfig, UINT32 ddBar5); +void restrictSataCapabilities(AMDSBCFG* pConfig); + + +void commonInitEarlyBoot(AMDSBCFG* pConfig); +void commonInitEarlyPost(AMDSBCFG* pConfig); +void setRevisionID(void); +UINT8 getRevisionID(void); +UINT8 IsServer (void); +UINT8 IsLs2Mode (void); +void abLinkInitBeforePciEnum(AMDSBCFG* pConfig); +void abcfgTbl(ABTBLENTRY* pABTbl); +void programSubSystemIDs(AMDSBCFG* pConfig, BUILDPARAM *pStaticOptions); +void commonInitLateBoot(AMDSBCFG* pConfig); +void hpetInit(AMDSBCFG* pConfig, BUILDPARAM *pStaticOptions); +void c3PopupSetting(AMDSBCFG* pConfig); + +void sbBeforePciInit (AMDSBCFG* pConfig); +void sbAfterPciInit(AMDSBCFG* pConfig); +void sbLatePost(AMDSBCFG* pConfig); +void sbBeforePciRestoreInit(AMDSBCFG* pConfig); +void sbAfterPciRestoreInit(AMDSBCFG* pConfig); +void sbSmmAcpiOn(AMDSBCFG* pConfig); +UINT32 GetPciebase(void); +UINT32 CallBackToOEM(UINT32 Func, UINTN Data,AMDSBCFG* pConfig); +void sbSmmService(AMDSBCFG* pConfig); +void softwareSMIservice(void); + +void sbPowerOnInit (AMDSBCFG *pConfig); +void programPciByteTable(REG8MASK* pPciByteTable, UINT16 dwTableSize); +void programPmioByteTable(REG8MASK* pPmioByteTable, UINT16 dwTableSize); +UINT8 getClockMode(void); +UINT16 readStrapStatus (void); + +void usbInitBeforePciEnum(AMDSBCFG* pConfig); +void usbInitAfterPciInit(AMDSBCFG* pConfig); +void usbInitMidPost(AMDSBCFG* pConfig); +void programOhciMmioForEmulation(void); + +void fcInitBeforePciEnum(AMDSBCFG* pConfig); + +unsigned char ReadIo8 (IN unsigned short Address); +unsigned short ReadIo16 (IN unsigned short Address); +unsigned int ReadIo32 (IN unsigned short Address); +void WriteIo8 (IN unsigned short Address, IN unsigned char Data); +void WriteIo16 (IN unsigned short Address, IN unsigned short Data); +void WriteIo32 (IN unsigned short Address, IN unsigned int Data); +unsigned long long ReadTSC (void); +void CpuidRead (IN unsigned int Func, IN OUT CPUID_DATA* Data); + +#ifndef NO_EC_SUPPORT +void EnterEcConfig(void); +void ExitEcConfig(void); +void ReadEC8(UINT8 Address, UINT8* Value); +void WriteEC8(UINT8 Address, UINT8* Value); +void RWEC8(UINT8 Address, UINT8 AndMask, UINT8 OrMask); +void ecPowerOnInit(BUILDPARAM *pBuildOptPtr, AMDSBCFG *pConfig); +void ecInitBeforePciEnum(AMDSBCFG* pConfig); +void ecInitLatePost(AMDSBCFG* pConfig); +#endif +UINT8 isEcPresent(void); + +void DispatcherEntry(void *pConfig); +AGESA_STATUS AmdSbDispatcher(void *pConfig); +void AMDFamily15CpuLdtStopReq(void); + +#endif //#ifndef _AMD_SBDEF_H_ diff --git a/src/vendorcode/amd/cimx/sb700/SBMAIN.c b/src/vendorcode/amd/cimx/sb700/SBMAIN.c new file mode 100644 index 0000000..7468eb2 --- /dev/null +++ b/src/vendorcode/amd/cimx/sb700/SBMAIN.c @@ -0,0 +1,289 @@ +/***************************************************************************** + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + ***************************************************************************/ + + +#include "Platform.h" + +#ifndef B1_IMAGE + +BUILDPARAM DfltStaticOptions={ + BIOS_SIZE, // BIOS Size + LEGACY_FREE, // Legacy Free Option + 0x00, // Dummy space holder + + 0x00, // ECKbd disable/enable + 0x00, // EcChannel0 disable/enable + 0x00, // Dummy space holder1 + + SMBUS0_BASE_ADDRESS, // Smbus Base Address; + SMBUS1_BASE_ADDRESS, // Smbus Base Address; + SIO_PME_BASE_ADDRESS, // SIO PME Base Address + WATCHDOG_TIMER_BASE_ADDRESS, // Watchdog Timer Base Address + SPI_BASE_ADDRESS, + + PM1_EVT_BLK_ADDRESS, // AcpiPm1EvtBlkAddr; + PM1_CNT_BLK_ADDRESS, // AcpiPm1CntBlkAddr; + PM1_TMR_BLK_ADDRESS, // AcpiPmTmrBlkAddr; + CPU_CNT_BLK_ADDRESS, // CpuControlBlkAddr; + GPE0_BLK_ADDRESS, // AcpiGpe0BlkAddr; + SMI_CMD_PORT, // SmiCmdPortAddr; + ACPI_PMA_CNT_BLK_ADDRESS, // AcpiPmaCntBlkAddr; + + EC_LDN5_MAILBOX_ADDRESS, + EC_LDN5_IRQ, + EC_LDN9_MAILBOX_ADDRESS, // EC LDN9 Mailbox address + RESERVED_VALUE, + RESERVED_VALUE, + RESERVED_VALUE, + RESERVED_VALUE, + + HPET_BASE_ADDRESS, // HPET Base address + + SATA_IDE_MODE_SSID, + SATA_RAID_MODE_SSID, + SATA_RAID5_MODE_SSID, + SATA_AHCI_SSID, + + OHCI0_SSID, + OHCI1_SSID, + EHCI0_SSID, + OHCI2_SSID, + OHCI3_SSID, + EHCI1_SSID, + OHCI4_SSID, + SMBUS_SSID, + IDE_SSID, + AZALIA_SSID, + LPC_SSID, + P2P_SSID, +}; + + +/********************************************************************************* +* +* Routine Description: Config SB Before PCI INIT +* +* Arguments: +* +* pConfig - SBconfiguration +* +* Returns: +* +* void +* +**********************************************************************************/ +void sbBeforePciInit (AMDSBCFG* pConfig){ + BUILDPARAM *pStaticOptions; + + pStaticOptions = &pConfig->BuildParameters; + TRACE((DMSG_SB_TRACE, "CIMx - Entering sbBeforePciInit \n")); + commonInitEarlyBoot(pConfig); + commonInitEarlyPost(pConfig); +#ifndef NO_EC_SUPPORT + ecInitBeforePciEnum(pConfig); +#endif + usbInitBeforePciEnum(pConfig); // USB POST TIME Only + fcInitBeforePciEnum(pConfig); // Preinit flash controller + sataInitBeforePciEnum(pConfig); // Init SATA class code and PHY + programSubSystemIDs(pConfig, pStaticOptions); // Set subsystem/vendor ID + + TRACE((DMSG_SB_TRACE, "CIMx - Exiting sbBeforePciInit \n")); +} + + +/********************************************************************************* +* +* Routine Description: Config SB After PCI INIT +* +* Arguments: +* +* pConfig - SBconfiguration +* +* Returns: void +* +* Reference: atiSbAfterPciInit +* +**********************************************************************************/ +void sbAfterPciInit(AMDSBCFG* pConfig){ + BUILDPARAM *pStaticOptions; + + TRACE((DMSG_SB_TRACE, "CIMx - Entering sbAfterPciInit \n")); + + pStaticOptions = &pConfig->BuildParameters; + usbInitMidPost(pConfig); //usb initialization which is required only during post + usbInitAfterPciInit(pConfig); // Init USB MMIO + sataInitAfterPciEnum(pConfig); // SATA port enumeration + azaliaInitAfterPciEnum(pConfig); // Detect and configure High Definition Audio + + TRACE((DMSG_SB_TRACE, "CIMx - Exiting sbAfterPciInit \n")); +} + + +/********************************************************************************* +* +* Routine Description: Config SB during late POST +* +* Arguments: +* +* pConfig - SBconfiguration +* +* Returns: void +* +* Reference: atiSbLatePost +* +**********************************************************************************/ +void sbLatePost(AMDSBCFG* pConfig){ + UINT16 dwVar; + BUILDPARAM *pStaticOptions; + pStaticOptions = &pConfig->BuildParameters; + TRACE((DMSG_SB_TRACE, "CIMx - Entering sbLatePost \n")); + ReadPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG02, AccWidthUint16, &dwVar); + if (dwVar != SB7XX_DEVICE_ID){ + // Display message that the SB is wrong and stop the system + TRACE((DMSG_SB_TRACE, "Current system does not have SB700 chipset. Stopping\n")); + for(;;); + } + commonInitLateBoot(pConfig); + sataInitLatePost(pConfig); + hpetInit(pConfig, pStaticOptions); // SB Configure HPET base and enable bit +#ifndef NO_EC_SUPPORT + ecInitLatePost(pConfig); +#endif +} + +/********************************************************************************* +* +* Routine Description: Config SB before ACPI S3 resume PCI config device restore +* +* Arguments: +* +* pConfig - SBconfiguration +* +* Returns: void +* +* Reference: AtiSbBfPciRestore +* +**********************************************************************************/ +void sbBeforePciRestoreInit(AMDSBCFG* pConfig){ + BUILDPARAM *pStaticOptions; + + TRACE((DMSG_SB_TRACE, "CIMx - Entering sbBeforePciRestoreInit \n")); + + pConfig->S3Resume = 1; + + pStaticOptions = &pConfig->BuildParameters; + commonInitEarlyBoot(pConfig); // set /SMBUS/ACPI/IDE/LPC/PCIB + abLinkInitBeforePciEnum(pConfig); // Set ABCFG registers + usbInitBeforePciEnum(pConfig); // USB POST TIME Only + fcInitBeforePciEnum(pConfig); // Preinit flash controller + sataInitBeforePciEnum(pConfig); + programSubSystemIDs(pConfig, pStaticOptions); // Set subsystem/vendor ID +} + + +/********************************************************************************* +* +* Routine Description: Config SB after ACPI S3 resume PCI config device restore +* +* Arguments: +* +* pConfig - SBconfiguration +* +* Returns: void +* +* Reference: AtiSbAfPciRestore +* +**********************************************************************************/ +void sbAfterPciRestoreInit(AMDSBCFG* pConfig){ + BUILDPARAM *pStaticOptions; + + pConfig->S3Resume = 1; + + pStaticOptions = &pConfig->BuildParameters; + TRACE((DMSG_SB_TRACE, "CIMx - Entering sbAfterPciRestoreInit \n")); + + commonInitLateBoot(pConfig); + sataInitAfterPciEnum(pConfig); + azaliaInitAfterPciEnum(pConfig); // Detect and configure High Definition Audio + hpetInit(pConfig, pStaticOptions); // SB Configure HPET base and enable bit + sataInitLatePost(pConfig); + sbSmmAcpiOn(pConfig); +} + + +/*++ + +Routine Description: + + SB config hook during ACPI_ON + +Arguments: + + pConfig - SBconfiguration + +Returns: + + void + +--*/ + +void sbSmmAcpiOn(AMDSBCFG* pConfig){ + UINT32 ddBar5; + UINT8 dbPort; + + //RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG60+2, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT1+BIT0), 0); + if (getRevisionID() >= SB700_A13) + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG43, AccWidthUint8 | S3_SAVE, 0xFF, BIT0); //Enable Legacy DMA prefetch enhancement + + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG60+2, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT1+BIT0), 0); + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG64+3, AccWidthUint8| S3_SAVE, ~(UINT32)BIT7, 0); + programOhciMmioForEmulation(); + + // For IDE_TO_AHCI_MODE and IDE_TO_AMD_AHCI_MODE, clear Interrupt Status register for all ports + ReadPCI( ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG24), AccWidthUint32, &ddBar5); + if ((pConfig->SataClass == IDE_TO_AHCI_MODE) || (pConfig->SataClass == IDE_TO_AMD_AHCI_MODE)){ + for (dbPort = 0; dbPort <= 5; dbPort++) { + RWMEM(ddBar5 + SB_SATA_BAR5_REG110 + dbPort * 0x80, AccWidthUint32, 0x00, 0xFFFFFFFF); + } + } +} + + +UINT32 CallBackToOEM(UINT32 Func, UINTN Data,AMDSBCFG* pConfig){ + UINT32 Result=0; + TRACE((DMSG_SB_TRACE,"OEM Call Back Func [%x] Data [%x]\n",Func,Data)); + if (pConfig->StdHeader.pCallBack==NULL) + return Result; + Result = (*(pConfig->StdHeader.pCallBack))(Func,Data,pConfig); + TRACE((DMSG_SB_TRACE,"SB Hook Status [%x]\n",Result)); + return Result; +} + +#endif diff --git a/src/vendorcode/amd/cimx/sb700/SBPOR.c b/src/vendorcode/amd/cimx/sb700/SBPOR.c new file mode 100644 index 0000000..6c5740b --- /dev/null +++ b/src/vendorcode/amd/cimx/sb700/SBPOR.c @@ -0,0 +1,441 @@ +/***************************************************************************** + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + ***************************************************************************/ + + +#include "Platform.h" + +REG8MASK sbPorInitPciTable[] = { + // SMBUS Device(Bus 0, Dev 20, Func 0) + {0x00, SMBUS_BUS_DEV_FUN, 0}, + {SB_SMBUS_REGD0+2, 0x00, 0x01}, + {SB_SMBUS_REG40, 0x00, 0x44}, + {SB_SMBUS_REG40+1, 0xFF, 0xE9}, //Set smbus pci config 0x40[14]=1, This bit is used for internal bus flow control. + {SB_SMBUS_REG64, 0x00, 0xBF}, //SB_SMBUS_REG64[13]=1, delays back to back interrupts to the CPU + {SB_SMBUS_REG64+1, 0x00, 0x78}, + {SB_SMBUS_REG64+2, ~(UINT8)BIT6, 0x9E}, + {SB_SMBUS_REG64+3, 0x0F, 0x02}, + {SB_SMBUS_REG68+1, 0x00, 0x90}, + {SB_SMBUS_REG6C, 0x00, 0x20}, + {SB_SMBUS_REG78, 0x00, 0xFF}, + {SB_SMBUS_REG04, 0x00, 0x07}, + {SB_SMBUS_REG04+1, 0x00, 0x04}, + {SB_SMBUS_REGE1, 0x00, 0x99}, //RPR recommended setting, Sections "SMBUS Pci Config" & "IMC Access Control" + {SB_SMBUS_REGAC, ~(UINT8)BIT4, BIT1}, + {SB_SMBUS_REG60+2, ~(UINT8)(BIT1+BIT0) , 0x24}, // Disabling Legacy USB Fast SMI# Smbus_PCI_config 0x62 [5] = 1. Legacy USB + // can request SMI# to be sent out early before IO completion. + // Some applications may have problems with this feature. The BIOS should set this bit + // to 1 to disable the feature. Enabling Legacy Interrupt Smbus_PCI_Config 0x62[2]=1. + {0xFF, 0xFF, 0xFF}, + + // LPC Device(Bus 0, Dev 20, Func 3) + {0x00, LPC_BUS_DEV_FUN, 0}, + {SB_LPC_REG40, 0x00, 0x04}, + {SB_LPC_REG48, 0x00, 0x07}, + {SB_LPC_REG4A, 0x00, 0x20}, // Port Enable for IO Port 80h. + {SB_LPC_REG78, ~(UINT8)BIT0, 0x00}, + {SB_LPC_REG7C, 0x00, 0x05}, + {SB_LPC_REGB8+3, ~(UINT8)BIT0, BIT7+BIT6+BIT5+BIT3+BIT0}, //RPR recommended setting,Section "IO / Mem Decoding" & "SPI bus" + {0xFF, 0xFF, 0xFF}, + + // P2P Bridge(Bus 0, Dev 20, Func 4) + {0x00, SBP2P_BUS_DEV_FUN, 0}, + {SB_P2P_REG40, 0x00, 0x26}, // Enabling PCI-bridge subtractive decoding & PCI Bus 64-byte DMA Read Access + {SB_P2P_REG4B, 0xFF, BIT6+BIT7+BIT4}, + {SB_P2P_REG1C, 0x00, 0x11}, + {SB_P2P_REG1D, 0x00, 0x11}, + {SB_P2P_REG04, 0x00, 0x21}, + {SB_P2P_REG50, 0x02, 0x01}, // PCI Bridge upstream dual address window + {0xFF, 0xFF, 0xFF}, +}; + + +REG8MASK sbA13PorInitPciTable[] = { + // SMBUS Device(Bus 0, Dev 20, Func 0) + {0x00, SMBUS_BUS_DEV_FUN, 0}, + {SB_SMBUS_REG43, ~(UINT8)BIT3, 0x00}, //Make some hidden registers of smbus visible. + {SB_SMBUS_REG38, (UINT8)~BIT7, 00}, + {SB_SMBUS_REGAC+1, ~(UINT8)BIT5, 0}, //Enable SATA test/enhancement mode + {SB_SMBUS_REG43, 0xFF, BIT3}, //Make some hidden registers of smbus invisible. + {0xFF, 0xFF, 0xFF}, +}; + + +REG8MASK sbA14PorInitPciTable[] = { + // LPC Device(Bus 0, Dev 20, Func 3) + {0x00, LPC_BUS_DEV_FUN, 0}, + {SB_LPC_REG8C+2, ~(UINT8)BIT1, 00}, + {0xFF, 0xFF, 0xFF}, +}; + +REG8MASK sbPorPmioInitTbl[] = { + // index andmask ormask + {SB_PMIO_REG67, 0xFF, 0x02}, + {SB_PMIO_REG37, 0xFF, 0x04}, // Configure pciepme as rising edge + {SB_PMIO_REG50, 0x00, 0xE0}, // Enable CPU_STP (except S5) & PCI_STP + {SB_PMIO_REG60, 0xFF, 0x20}, // Enable Speaker + {SB_PMIO_REG65, (UINT8)~(BIT4+BIT7), 0x00},// Clear PM_IO 0x65[4] UsbResetByPciRstEnable to avoid S3 reset to reset USB + {SB_PMIO_REG55, ~(UINT8)BIT6, 0x07}, // Select CIR wake event to ACPI.GEVENT[23] & Clear BIT6 SoftPciRst for safety + {SB_PMIO_REG66, 0xFF, BIT5}, // Configure keyboard reset to generate pci reset + {SB_PMIO_REGB2, 0xFF, BIT7}, + {SB_PMIO_REG0E, 0xFF, BIT3}, // Enable ACPI IO decoding + {SB_PMIO_REGD7, 0xF6, 0x80}, + {SB_PMIO_REG7C, 0xFF, BIT4}, // enable RTC AltCentury register + + {SB_PMIO_REG75, 0xC0, 0x05}, // PME_TURN_OFF_MSG during ASF shutdown + {SB_PMIO_REG52, 0xC0, 0x08}, + + {SB_PMIO_REG8B, 0x00, 0x10}, + {SB_PMIO_REG69, 0xF9, 0x01 << 1}, // [Updated RPR] Set default WDT resolution to 10ms +}; + +REG8MASK sbA13PorPmioInitTbl[]={ + // index andmask ormask + {SB_PMIO_REGD7, 0xFF, BIT5+BIT0}, //Fixes for TT SB00068 & SB01054 (BIT5 & BIT0 correspondingly) + {SB_PMIO_REGBB, (UINT8)~BIT7, BIT6+BIT5}, //Fixes for TT SB00866 & SB00696 (BIT6 & BIT5 correspondingly) + // Always clear [7] to begin with SP5100 C1e disabled + +// {SB_PMIO_REG65, 0xFF, BIT7}, +// {SB_PMIO_REG75, 0xC0, 0x01}, // PME_TURN_OFF_MSG during ASF shutdown +// {SB_PMIO_REG52, 0xC0, 0x02}, + +}; + + +void sbPowerOnInit (AMDSBCFG *pConfig){ + UINT8 dbVar0, dbVar1, dbValue; + UINT16 dwTempVar; + BUILDPARAM *pBuildOptPtr; + + TRACE((DMSG_SB_TRACE, "CIMx - Entering sbPowerOnInit \n")); + + setRevisionID(); + ReadPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG02), AccWidthUint16 | S3_SAVE, &dwTempVar); + if (dwTempVar == SB750_SATA_DEFAULT_DEVICE_ID) + RWPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG9C, AccWidthUint8 | S3_SAVE, 0xFF, 0x01); + + // Set A-Link bridge access address. This address is set at device 14h, function 0, + // register 0f0h. This is an I/O address. The I/O address must be on 16-byte boundry. + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGF0, AccWidthUint32, 00, ALINK_ACCESS_INDEX); + + writeAlink(0x80000004, 0x04); // RPR 3.3 Enabling upstream DMA Access + writeAlink(0x30, 0x10); //AXINDC 0x10[9]=1, Enabling Non-Posted memory write for K8 platform. + writeAlink(0x34, readAlink(0x34) | BIT9); + + if (!(pConfig->ResetCpuOnSyncFlood)){ + //Enable reset on sync flood + writeAlink( (UINT32)( ((UINT32)SB_AB_REG10050) | ((UINT32)ABCFG << 30)), + (UINT32)( readAlink((((UINT32)SB_AB_REG10050) | ((UINT32)ABCFG << 30))) | ((UINT32)BIT2) )); + } + + pBuildOptPtr = &(pConfig->BuildParameters); + + WritePCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG90, AccWidthUint32 | S3_SAVE, &(pBuildOptPtr->Smbus0BaseAddress) ); + + dwTempVar = pBuildOptPtr->Smbus1BaseAddress & (UINT16)~BIT0; + if( dwTempVar != 0 ){ + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG58, AccWidthUint16 | S3_SAVE, 00, (dwTempVar|BIT0)); + // Disable ASF Slave controller on SB700 rev A15. + if (getRevisionID() == SB700_A15) { + RWIO((dwTempVar+0x0D), AccWidthUint8, (UINT8)~BIT6, BIT6); + } + } + + WritePCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG64, AccWidthUint16 | S3_SAVE, &(pBuildOptPtr->SioPmeBaseAddress)); + RWPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA0, AccWidthUint32 | S3_SAVE, 0x001F,(pBuildOptPtr->SpiRomBaseAddress)); + + WritePMIO(SB_PMIO_REG20, AccWidthUint16, &(pBuildOptPtr->AcpiPm1EvtBlkAddr)); + WritePMIO(SB_PMIO_REG22, AccWidthUint16, &(pBuildOptPtr->AcpiPm1CntBlkAddr)); + WritePMIO(SB_PMIO_REG24, AccWidthUint16, &(pBuildOptPtr->AcpiPmTmrBlkAddr)); + WritePMIO(SB_PMIO_REG26, AccWidthUint16, &(pBuildOptPtr->CpuControlBlkAddr)); + WritePMIO(SB_PMIO_REG28, AccWidthUint16, &(pBuildOptPtr->AcpiGpe0BlkAddr)); + WritePMIO(SB_PMIO_REG2A, AccWidthUint16, &(pBuildOptPtr->SmiCmdPortAddr)); + WritePMIO(SB_PMIO_REG2C, AccWidthUint16, &(pBuildOptPtr->AcpiPmaCntBlkAddr)); + RWPMIO(SB_PMIO_REG2E, AccWidthUint16, 0x00,(pBuildOptPtr->SmiCmdPortAddr)+8); + WritePMIO(SB_PMIO_REG6C, AccWidthUint32, &(pBuildOptPtr->WatchDogTimerBase)); + + //Program power on pci init table + programPciByteTable( (REG8MASK*)FIXUP_PTR(&sbPorInitPciTable[0]), sizeof(sbPorInitPciTable)/sizeof(REG8MASK) ); + //Program power on pmio init table + programPmioByteTable( (REG8MASK *)FIXUP_PTR(&sbPorPmioInitTbl[0]), (sizeof(sbPorPmioInitTbl)/sizeof(REG8MASK)) ); + + dbValue = 0x00; + ReadIO (SB_IOMAP_REGC14, AccWidthUint8, &dbValue); + dbValue &= 0xF3; + WriteIO (SB_IOMAP_REGC14, AccWidthUint8, &dbValue); + + dbValue = 0x0A; + WriteIO (SB_IOMAP_REG70, AccWidthUint8, &dbValue); + ReadIO (SB_IOMAP_REG71, AccWidthUint8, &dbValue); + dbValue &= 0xEF; + WriteIO (SB_IOMAP_REG71, AccWidthUint8, &dbValue); + + + if (getRevisionID() >= SB700_A13){ + programPciByteTable( (REG8MASK*)FIXUP_PTR(&sbA13PorInitPciTable[0]), sizeof(sbA13PorInitPciTable)/sizeof(REG8MASK) ); + programPmioByteTable( (REG8MASK *)FIXUP_PTR(&sbA13PorPmioInitTbl[0]), (sizeof(sbA13PorPmioInitTbl)/sizeof(REG8MASK)) ); + } + + if ((getRevisionID() >= SB700_A14) ) + programPciByteTable( (REG8MASK*)FIXUP_PTR(&sbA14PorInitPciTable[0]), sizeof(sbA14PorInitPciTable)/sizeof(REG8MASK) ); + + if ( (getRevisionID() >= SB700_A14) && ( (pConfig->TimerClockSource == 1) || (pConfig->TimerClockSource == 2) )){ + ReadPMIO(SB_PMIO_REGD4, AccWidthUint8, &dbVar1); + if (!(dbVar1 & BIT6)){ + RWPMIO(SB_PMIO_REGD4, AccWidthUint8, 0xFF, BIT6); + pConfig->RebootRequired=1; + } + } + + if (getRevisionID() > SB700_A11) { + if (pConfig->PciClk5 == 1) + RWPMIO(SB_PMIO_REG41, AccWidthUint8, ~(UINT32)BIT1, BIT1); // Enabled PCICLK5 for A12 + } + + dbVar0 = (pBuildOptPtr->BiosSize + 1) & 7; + if (dbVar0 > 4) { + dbVar0 = 0; + } + //KZ [061811]-It's used wrong BIOS SIZE for Coreboot. RWPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG6C, AccWidthUint8 | S3_SAVE, 0x00, 0xF8 << dbVar0); + + if (pConfig->Spi33Mhz) + //spi reg0c[13:12] to 01h to run spi 33Mhz in system bios + RWMEM((pBuildOptPtr->SpiRomBaseAddress)+SB_SPI_MMIO_REG0C,AccWidthUint16 | S3_SAVE, ~(UINT32)(BIT13+BIT12), BIT12); + + //SB internal spread spectrum settings. A reboot is required if the spread spectrum settings have to be changed + //from the existing value. + ReadPMIO(SB_PMIO_REG42, AccWidthUint8, &dbVar0); + if (pConfig->SpreadSpectrum != (dbVar0 >> 7) ) + pConfig->RebootRequired = 1; + if (pConfig->SpreadSpectrum) + RWPMIO(SB_PMIO_REG42, AccWidthUint8, ~(UINT32)BIT7, BIT7); + else + RWPMIO(SB_PMIO_REG42, AccWidthUint8, ~(UINT32)BIT7, 0); + + if ( !(pConfig->S3Resume) ){ + //To detect whether internal clock chip is used, do the following procedure + //set PMIO_B2[7]=1, then read PMIO_B0[4]; if it is 1, we are strapped to CLKGEN mode. + //if it is 0, we are using clock chip on board. + RWPMIO(SB_PMIO_REGB2, AccWidthUint8, 0xFF, BIT7); + + //Do the following programming only for SB700-A11. + //1. Set PMIO_B2 [7]=1 and read B0 and B1 and save those values. + //2. Set PMIO_B2 [7]=0 + //3. Write the saved values from step 1, back to B0 and B1. + //4. Set PMIO_B2 [6]=1. + ReadPMIO(SB_PMIO_REGB0, AccWidthUint16, &dwTempVar); + if (getRevisionID() == SB700_A11){ + RWPMIO(SB_PMIO_REGB2, AccWidthUint8, ~(UINT32)BIT7, 00); + WritePMIO(SB_PMIO_REGB0, AccWidthUint16, &dwTempVar); + RWPMIO(SB_PMIO_REGB2, AccWidthUint8, 0xFF, BIT6); + } + + if (!(dwTempVar & BIT4)){ + RWPMIO(SB_PMIO_REGD0, AccWidthUint8, ~(UINT32)BIT0, 0); //Enable PLL2 + + //we are in external clock chip on the board + if (pConfig->UsbIntClock == CIMX_OPTION_ENABLED){ + //Configure usb clock to come from internal PLL + RWPMIO(SB_PMIO_REGD2, AccWidthUint8, 0xFF, BIT3); //Enable 48Mhz clock from PLL2 + RWPMIO(SB_PMIO_REGBD, AccWidthUint8, ~(UINT32)BIT4, BIT4); //Tell USB PHY to use internal 48Mhz clock from PLL2 + } + else{ + //Configure usb clock to come from external clock + RWPMIO(SB_PMIO_REGBD, AccWidthUint8, ~(UINT32)BIT4, 0); //Tell USB PHY to use external 48Mhz clock from PLL2 + RWPMIO(SB_PMIO_REGD2, AccWidthUint8, ~(UINT32)BIT3, 00); //Disable 48Mhz clock from PLL2 + } + } + else{ + //we are using internal clock chip on this board + if (pConfig->UsbIntClock == CIMX_OPTION_ENABLED){ + //Configure usb clock to come from internal PLL + RWPMIO(SB_PMIO_REGD2, AccWidthUint8, ~(UINT32)BIT3, 0); //Enable 48Mhz clock from PLL2 + RWPMIO(SB_PMIO_REGBD, AccWidthUint8, ~(UINT32)BIT4, BIT4); //Tell USB PHY to use internal 48Mhz clock from PLL2 + } + else{ + //Configure usb clock to come from external clock + RWPMIO(SB_PMIO_REGBD, AccWidthUint8, ~(UINT32)BIT4, 0); //Tell USB PHY to use external 48Mhz clock from PLL2 + RWPMIO(SB_PMIO_REGD2, AccWidthUint8, ~(UINT32)BIT3, BIT3); //Disable 48Mhz clock from PLL2 + } + } + + ReadPMIO(SB_PMIO_REG43, AccWidthUint8, &dbVar0); + RWPMIO(SB_PMIO_REG43, AccWidthUint8, ~(UINT32)(BIT6+BIT5+BIT0), (pConfig->UsbIntClock << 5)); + //Check whether our usb clock settings changed compared to previous boot, if yes then we need to reboot. + if ( (dbVar0 & BIT0) || ( (pConfig->UsbIntClock) != ((dbVar0 & (BIT6+BIT5)) >> 5)) ) pConfig->RebootRequired = 1; + } + + if (pBuildOptPtr->LegacyFree) //if LEGACY FREE system + RWPCI(((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG44), AccWidthUint32 | S3_SAVE, 00, 0x0003C000); + else + RWPCI(((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG44), AccWidthUint32 | S3_SAVE, 00, 0xFF03FFD5); + + if ( (getRevisionID() == SB700_A14) || (getRevisionID() == SB700_A13)){ + RWPMIO(SB_PMIO_REG65, AccWidthUint8, 0xFF, BIT7); + RWPMIO(SB_PMIO_REG75, AccWidthUint8, 0xC0, BIT0); + RWPMIO(SB_PMIO_REG52, AccWidthUint8, 0xC0, BIT1); + } + + if (getRevisionID() >= SB700_A15) { + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG40+3, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT3), 0); + //Enable unconditional shutdown fix in A15 + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG38+1, AccWidthUint8 | S3_SAVE, 0xFF, BIT4); + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG40+3, AccWidthUint8 | S3_SAVE, 0xFF, BIT3); + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG06+1, AccWidthUint8 | S3_SAVE, 0xFF, 0xD0); + } + + // [Updated RPR] Set ImcHostSmArbEn(SMBUS:0xE1[5]) only when IMC is enabled + if (isEcPresent()) { + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGE1, AccWidthUint8 | S3_SAVE, 0xFF, BIT5); + } + + //According to AMD Family 15h Models 00h-0fh processor BKDG section 2.12.8 LDTSTOP requirement + // to program VID/FID LDTSTP# duration selection register + AMDFamily15CpuLdtStopReq(); + +#ifndef NO_EC_SUPPORT + ecPowerOnInit(pBuildOptPtr, pConfig); +#endif +} + + +void setRevisionID(void){ + UINT8 dbVar0, dbVar1; + + ReadPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG08), AccWidthUint8, &dbVar0); + ReadPMIO(SB_PMIO_REG53, AccWidthUint8, &dbVar1); + if ( (dbVar0 == 0x39) && (dbVar1 & BIT6) && !(dbVar1 & BIT7)){ + RWPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG40), AccWidthUint8, ~(UINT32)BIT0, BIT0); + RWPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG08), AccWidthUint8, 00, SB700_A12); + RWPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG40), AccWidthUint8, ~(UINT32)BIT0, 00); + } + ReadPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG08), AccWidthUint8, &dbVar0); +} + + +UINT8 getRevisionID(void){ + UINT8 dbVar0; + + ReadPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG08), AccWidthUint8, &dbVar0); + return dbVar0; +} + + +void AMDFamily15CpuLdtStopReq(void) { + CPUID_DATA CpuId; + CPUID_DATA CpuId_Brand; + UINT8 dbVar0, dbVar1, dbVar2; + + //According to AMD Family 15h Models 00h-0fh processor BKDG section 2.12.8 LDTSTOP requirement + //to program VID/FID LDTSTP# duration selection register + //If any of the following system configuration properties are true LDTSTP# assertion time required by the processor is 10us: + // 1. Any link in the system operating at a Gen 1 Frequency. + // 2. Also for server platform (G34/C32) set PM_REG8A[6:4]=100b (16us) + + CpuidRead (0x01, &CpuId); + CpuidRead (0x80000001, &CpuId_Brand); //BrandID, to read socket type + if ((CpuId.REG_EAX & 0xFFFFFF00) == 0x00600F00) { + + //Program to Gen 3 default value - 001b + RWPMIO(SB_PMIO_REG8A, AccWidthUint8, 0x8F, 0x10); //set [6:4]=001b + + //Any link in the system operating at a Gen 1 Frequency. + //Check Link 0 - Link connected regsister + ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REG98), AccWidthUint8, &dbVar2); + dbVar2 = dbVar2 & 0x01; + + if(dbVar2 == 0x01) { + //Check Link 0 - Link Frequency Freq[4:0] + ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REG89), AccWidthUint8, &dbVar0); + ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REG9C), AccWidthUint8, &dbVar1); + dbVar0 = dbVar0 & 0x0F; //Freq[3:0] + dbVar1 = dbVar1 & 0x01; //Freq[4] + dbVar0 = (dbVar1 << 4) | dbVar0; //Freq[4:0] + //Value 6 or less indicate Gen1 + if(dbVar0 <= 0x6) { + RWPMIO(SB_PMIO_REG8A, AccWidthUint8, 0x8F, 0x40); //set [6:4]=100b + } + } + + //Check Link 1 - Link connected regsister + ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGB8), AccWidthUint8, &dbVar2); + dbVar2 = dbVar2 & 0x01; + if(dbVar2 == 0x01) { + //Check Link 1 - Link Frequency Freq[4:0] + ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGA9), AccWidthUint8, &dbVar0); + ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGBC), AccWidthUint8, &dbVar1); + dbVar0 = dbVar0 & 0x0F; //Freq[3:0] + dbVar1 = dbVar1 & 0x01; //Freq[4] + dbVar0 = (dbVar1 << 4) | dbVar0; //Freq[4:0] + //Value 6 or less indicate Gen1 + if(dbVar0 <= 0x6) { + RWPMIO(SB_PMIO_REG8A, AccWidthUint8, 0x8F, 0x40); //set [6:4]=100b + } + } + + //Check Link 2 - Link connected regsister + ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGD8), AccWidthUint8, &dbVar2); + dbVar2 = dbVar2 & 0x01; + if(dbVar2 == 0x01) { + //Check Link 2 - Link Frequency Freq[4:0] + ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGC9), AccWidthUint8, &dbVar0); + ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGDC), AccWidthUint8, &dbVar1); + dbVar0 = dbVar0 & 0x0F; //Freq[3:0] + dbVar1 = dbVar1 & 0x01; //Freq[4] + dbVar0 = (dbVar1 << 4) | dbVar0; //Freq[4:0] + //Value 6 or less indicate Gen1 + if(dbVar0 <= 0x6) { + RWPMIO(SB_PMIO_REG8A, AccWidthUint8, 0x8F, 0x40); //set [6:4]=100b + } + } + + //Check Link 3 - Link connected regsister + ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGF8), AccWidthUint8, &dbVar2); + dbVar2 = dbVar2 & 0x01; + if(dbVar2 == 0x01) { + //Check Link 3 - Link Frequency Freq[4:0] + ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGE9), AccWidthUint8, &dbVar0); + ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGFC), AccWidthUint8, &dbVar1); + dbVar0 = dbVar0 & 0x0F; //Freq[3:0] + dbVar1 = dbVar1 & 0x01; //Freq[4] + dbVar0 = ((dbVar1 << 4) | dbVar0); //Freq[4:0] + //Value 6 or less indicate Gen1 + if(dbVar0 <= 0x6) { + RWPMIO(SB_PMIO_REG8A, AccWidthUint8, 0x8F, 0x40); //set [6:4]=100b + } + } + + // Server platform (G34/C32) set PM_REG8A[6:4]=100b (16us) + if(((CpuId_Brand.REG_EBX & 0xF0000000) == 0x30000000) || ((CpuId_Brand.REG_EBX & 0xF0000000) == 0x50000000)) { + RWPMIO(SB_PMIO_REG8A, AccWidthUint8, 0x8F, 0x40); //set [6:4]=100b + } + } + +} + diff --git a/src/vendorcode/amd/cimx/sb700/SBTYPE.h b/src/vendorcode/amd/cimx/sb700/SBTYPE.h new file mode 100644 index 0000000..faeae5d --- /dev/null +++ b/src/vendorcode/amd/cimx/sb700/SBTYPE.h @@ -0,0 +1,249 @@ +/*;******************************************************************************** +; +; Copyright (C) 2012 Advanced Micro Devices, Inc. +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; * Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; * Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution. +; * Neither the name of Advanced Micro Devices, Inc. nor the names of +; its contributors may be used to endorse or promote products derived +; from this software without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;*********************************************************************************/ + +#ifndef _AMD_SBTYPE_H_ +#define _AMD_SBTYPE_H_ + +#pragma pack(push,1) + +typedef UINT32 (*CIM_HOOK_ENTRY)(UINT32 Param1, UINTN Param2, void* pConfig); +typedef void (*SMM_SERVICE_ROUTINE) (void); + +typedef struct _STDCFG{ + UINT32 pImageBase; + UINT32 pPcieBase; + UINT8 Func; + CIM_HOOK_ENTRY pCallBack; + UINT32 pB2ImageBase; +}STDCFG; //Size of stdcfg is 17 bytes + +typedef struct _BUILDPARAM +{ + UINT16 BiosSize:3; //0-1MB, 1-2MB, 2-4MB, 3-8MB, 7-512KB, all other values reserved + UINT16 LegacyFree:1; + UINT16 Dummy0:12; + + UINT16 EcKbd:1; + UINT16 EcChannel0:1; + UINT16 Dummy1:14; + + UINT32 Smbus0BaseAddress; + UINT16 Smbus1BaseAddress; + UINT32 SioPmeBaseAddress; + UINT32 WatchDogTimerBase; + UINT32 SpiRomBaseAddress; + + UINT16 AcpiPm1EvtBlkAddr; + UINT16 AcpiPm1CntBlkAddr; + UINT16 AcpiPmTmrBlkAddr; + UINT16 CpuControlBlkAddr; + UINT16 AcpiGpe0BlkAddr; + UINT16 SmiCmdPortAddr; + UINT16 AcpiPmaCntBlkAddr; + + UINT16 EcLdn5MailBoxAddr; + UINT8 EcLdn5Irq; + UINT16 EcLdn9MailBoxAddr; + UINT32 ReservedDword0; + UINT32 ReservedDword1; + UINT32 ReservedDword2; + UINT32 ReservedDword3; + + UINT32 HpetBase; //HPET Base address + + UINT32 SataIDESsid; + UINT32 SataRAIDSsid; + UINT32 SataRAID5Ssid; + UINT32 SataAHCISsid; + + UINT32 Ohci0Ssid; + UINT32 Ohci1Ssid; + UINT32 Ehci0Ssid; + UINT32 Ohci2Ssid; + UINT32 Ohci3Ssid; + UINT32 Ehci1Ssid; + UINT32 Ohci4Ssid; + UINT32 SmbusSsid; + UINT32 IdeSsid; + UINT32 AzaliaSsid; + UINT32 LpcSsid; + UINT32 P2PSsid; +}BUILDPARAM; + +typedef struct _CODECENTRY{ + UINT8 Nid; + UINT32 Byte40; +}CODECENTRY; + +typedef struct _CODECTBLLIST{ + UINT32 CodecID; + CODECENTRY* CodecTablePtr; +}CODECTBLLIST; + +typedef struct _AMDSBCFG +{ + STDCFG StdHeader; //offset 0:16 - 17 bytes + //UINT32 MsgXchgBiosCimx; //offset 17:20 - 4 bytes + UINT32 S3Resume:1; + UINT32 RebootRequired:1; + UINT32 Spi33Mhz:1; + UINT32 SpreadSpectrum:1; + UINT32 UsbIntClock:1; //0:Use external clock, 1:Use internal clock + UINT32 PciClk5:1; //0:disable, 1:enable + UINT32 TimerClockSource:2; //0:100Mhz PCIE Reference clock (same as SB700-A12, + //1: 14Mhz using 25M_48M_66M_OSC pin, 2: Auto (100Mhz for SB700-A12, 14Mhz + //using 25M_48m_66m_0SC pin for SB700-A14, SB710, SP5100 + UINT32 ResetCpuOnSyncFlood:1; //0:Reset CPU on Sync Flood, 1:Do not reset CPU on sync flood + UINT32 MsgXchgBiosCimxDummyBB:23; + + /** BuildParameters - The STATIC platform information for CIMx Module. */ + BUILDPARAM BuildParameters; + + //SATA Configuration + UINT32 SataController :1; //0, 0:disable 1:enable* //offset 25:28 - 4 bytes + UINT32 SataClass :3; //1, 0:IDE* 1:RAID 2:AHCI 3:Legacy IDE 4:IDE->AHCI 5:AMD_AHCI, 6:IDE->AMD_AHCI + UINT32 SataSmbus :1; //4, 0:disable 1:enable* + UINT32 SataAggrLinkPmCap:1; //5, 0:OFF 1:ON + UINT32 SataPortMultCap :1; //6, 0:OFF 1:ON + UINT32 SataReserved :2; //8:7, Reserved + UINT32 SataClkAutoOff :1; //9, AutoClockOff for IDE modes 0:Disabled, 1:Enabled + UINT32 SataIdeCombinedMode :1; //10, SataIDECombinedMode 0:Disabled, 1:Enabled + UINT32 SataIdeCombMdPriSecOpt:1; //11, Combined Mode, SATA as primary or secondary 0:primary 1:secondary + UINT32 SataReserved1 :6; //17:12, Not used currently + UINT32 SataEspPort :6; //23:18 SATA port is external accessiable on a signal only connector (eSATA:) + UINT32 SataClkAutoOffAhciMode:1; //24: Sata Auto clock off for AHCI mode + UINT32 SataHpcpButNonESP:6; //25:30 Hotplug capable but not e-sata port + UINT32 SataHideUnusedPort:1; //31, 0:Disabled 1:Enabled + + //Flash Configuration //offset 29:30 - 2 bytes + UINT16 FlashController :1; //0, 0:disable FC & enable IDE 1:enable FC & disable IDE + UINT16 FlashControllerMode:1; //1, 0:Flash behind SATA 1:Flash as standalone + UINT16 FlashHcCrc:1; //2, + UINT16 FlashErrorMode:1; //3 + UINT16 FlashNumOfBankMode:1; //4 + UINT16 FlashDummy:11; //5:15 + + //USB Configuration //offset 31:32 - 2 bytes + UINT16 Usb1Ohci0 :1; //0, 0:disable 1:enable* Bus 0 Dev 18 Func0 + UINT16 Usb1Ohci1 :1; //1, 0:disable 1:enable* Bus 0 Dev 18 Func1 + UINT16 Usb1Ehci :1; //2, 0:disable 1:enable* Bus 0 Dev 18 Func2 + UINT16 Usb2Ohci0 :1; //3, 0:disable 1:enable* Bus 0 Dev 19 Func0 + UINT16 Usb2Ohci1 :1; //4, 0:disable 1:enable* Bus 0 Dev 19 Func1 + UINT16 Usb2Ehci :1; //5, 0:disable 1:enable* Bus 0 Dev 19 Func2 + UINT16 Usb3Ohci :1; //6, 0:disable 1:enable* Bus 0 Dev 20 Func5 + UINT16 UsbOhciLegacyEmulation:1; //7, 0:Enabled, 1:Disabled + UINT16 UsbDummy :8; //8:15 + + //Azalia Configuration //offset 33:36 - 4 bytes + UINT32 AzaliaController:2; //0, 0:AUTO, 1:disable, 2:enable + UINT32 AzaliaPinCfg :1; //2, 0:disable, 1:enable + UINT32 AzaliaFrontPanel:2; //3, 0:AUTO, 1:disable, 2:enable + UINT32 FrontPanelDetected:1; //5, 0:Not detected, 1:detected + UINT32 AzaliaSdin0 :2; //6 + UINT32 AzaliaSdin1 :2; //8 + UINT32 AzaliaSdin2 :2; //10 + UINT32 AzaliaSdin3 :2; //12 + UINT32 AzaliaDummy :18; //14:31 + + CODECTBLLIST* pAzaliaOemCodecTablePtr; //offset 37:40 - 4 bytes + UINT32 pAzaliaOemFpCodecTableptr; //offset 41:44 - 4 bytes + + //Miscellaneous Configuration //offset 45:48 - 4 bytes + UINT32 MiscReserved0:1; //0 + UINT32 HpetTimer:1; //1, 0:disable 1:enable + UINT32 PciClks:5; //2:6, 0:disable, 1:enable + UINT32 MiscReserved1:3; //9:7, Reserved + UINT32 IdeController:1; //10, 0:Enable, 1:Disabled + UINT32 MobilePowerSavings:1; //11, 0:Disable, 1:Enable Power saving features especially for Mobile platform + UINT32 ExternalRTCClock:1; //12, 0:Don't Shut Off, 1:Shut Off, external RTC clock + UINT32 AcpiS1Supported:1; //13, 0:S1 not supported, 1:S1 supported + UINT32 AnyHT200MhzLink:1; //14, 0:No HT 200Mhz Link in platform, 1; There is 200MHz HT Link in platform + UINT32 WatchDogTimerEnable:1; //15, [0]: WDT disabled; 1: WDT enabled + UINT32 MTC1e:1; //16, Message Triggered C1e - 0:Disabled*, 1:Enabled + UINT32 HpetMsiDis:1; //17, HPET MSI - 0:Enable HPET MSI, 1:Disable + UINT32 EhciDataCacheDis:1; //18, 0:Date Cache Enabled, 1:Date Cache Disabled /** EHCI Async Data Cache Disable */ + UINT32 MiscDummy:13; + + UINT32 AsmAslInfoExchange0; //offset 49:52 - 4 bytes + UINT32 AsmAslInfoExchange1; //offset 53:56 + + //DebugOptions_1 //offset 57:60 + UINT32 FlashPinConfig :1; //0, 0:desktop mode 1:mobile mode + UINT32 UsbPhyPowerDown :1; //1 + UINT32 PcibClkStopOverride :10; //11:2 + UINT32 Debug1Reserved0:4; //15:11 + UINT32 AzaliaSnoop:1; //16 0:Disable, 1:Enable + UINT32 SataSscPscCap:1; //17, 0:Enable SSC/PSC capability, 1:Disable SSC/PSC capability + UINT32 SataPortMode:6; //23:18, 0: AUTO, 1:Force SATA port(6/5/4/3/2/1) to GEN1 + UINT32 SataPhyWorkaround:2; //25:24, 0:AUTO, 1:Enable, 2:Disable + UINT32 Gen1DeviceShutdownDuringPhyWrknd:2; //27:26, 0:AUTO, 1:YES, 2:NO + UINT32 OhciIsoOutPrefetchDis:1; //28, 0:Enable OHCI ISO OUT prefetch, 1:Disable + UINT32 Debug1Dummy:3; // + + //DebugOptions_2 + UINT32 PcibAutoClkCtrlLow:16; + UINT32 PcibAutoClkCtrlHigh:16; + + //TempMMIO + UINT32 TempMMIO:32; + +}AMDSBCFG; + +typedef struct _SMMSERVICESTRUC +{ + UINT8 enableRegNum; + UINT8 enableBit; + UINT8 statusRegNum; + UINT8 statusBit; + CHAR8 *debugMessage; + SMM_SERVICE_ROUTINE serviceRoutine; +}SMMSERVICESTRUC; + +typedef struct _ABTblEntry +{ + UINT8 regType; + UINT32 regIndex; + UINT32 regMask; + UINT32 regData; +}ABTBLENTRY; + +#define PCI_ADDRESS(bus,dev,func,reg) \ +(UINT32) ( (((UINT32)bus) << 24) + (((UINT32)dev) << 19) + (((UINT32)func) << 16) + ((UINT32)reg) ) + +typedef UINT32 CIM_STATUS; +#define CIM_SUCCESS 0x00000000 +#define CIM_ERROR 0x80000000 +#define CIM_UNSUPPORTED 0x80000001 + +#pragma pack(pop) + +#define CIMX_OPTION_DISABLED 0 +#define CIMX_OPTION_ENABLED 1 + +#endif // _AMD_SBTYPE_H_ diff --git a/src/vendorcode/amd/cimx/sb700/SMM.c b/src/vendorcode/amd/cimx/sb700/SMM.c new file mode 100644 index 0000000..0d752fb --- /dev/null +++ b/src/vendorcode/amd/cimx/sb700/SMM.c @@ -0,0 +1,91 @@ +/***************************************************************************** + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + ***************************************************************************/ + + +#include "Platform.h" + +SMMSERVICESTRUC smmItemsTable[]={ + {SB_PMIO_REG0E, BIT2, SB_PMIO_REG0F, BIT2, (CHAR8 *)"Software SMI through SMI CMD port \n ", softwareSMIservice}, + {SB_PMIO_REG00, BIT4, SB_PMIO_REG01, BIT4, (CHAR8 *)"Software initiated SMI \n ", NULL}, + {SB_PMIO_REG02, 0xFF, SB_PMIO_REG05, 0xFF, (CHAR8 *)"SMI on IRQ15-8 \n ", NULL}, + {SB_PMIO_REG03, 0xFF, SB_PMIO_REG06, 0xFF, (CHAR8 *)"SMI on IRQ7-0 \n ", NULL}, + {SB_PMIO_REG04, 0xFF, SB_PMIO_REG07, 0xFF, (CHAR8 *)"SMI on legacy devices activity(Serial, FDD etc) \n ", NULL}, + {SB_PMIO_REG1C, 0xFF, SB_PMIO_REG1D, 0xFF, (CHAR8 *)"SMI on PIO 0123 \n ", NULL}, + {SB_PMIO_REGA8, 0x0F, SB_PMIO_REGA9, 0xFF, (CHAR8 *)"SMI on PIO 4567 \n ", NULL}, +}; + + +/*++ + +Routine Description: + + SB SMI service + +Arguments: + + pConfig - SBconfiguration + +Returns: + + void + +--*/ + +void sbSmmService(AMDSBCFG* pConfig){ + UINT8 i, dbEnableValue, dbStatusValue; + SMMSERVICESTRUC *pSmmItems; + SMM_SERVICE_ROUTINE serviceRoutine; + + pSmmItems = (SMMSERVICESTRUC *)FIXUP_PTR(&smmItemsTable[0]); + TRACE((DMSG_SB_TRACE, "CIMx - Entering SMM services \n")); + for (i = 1; i <= (sizeof(smmItemsTable)/sizeof(SMMSERVICESTRUC)); i++){ + dbEnableValue = pSmmItems->enableRegNum; + ReadPMIO(pSmmItems->enableRegNum, AccWidthUint8, &dbEnableValue); + ReadPMIO(pSmmItems->statusRegNum, AccWidthUint8, &dbStatusValue); + if ( (dbEnableValue & (pSmmItems->enableBit)) && (dbStatusValue & (pSmmItems->statusBit)) ){ + TRACE((DMSG_SB_TRACE, "\n \nSmi source is: %s \n", pSmmItems->debugMessage)); + TRACE((DMSG_SB_TRACE, "Enable Reg:%d Value:%d\n", pSmmItems->enableRegNum, dbEnableValue)); + TRACE((DMSG_SB_TRACE, "Status Reg:%d Value:%d\n\n", pSmmItems->statusRegNum, dbStatusValue)); + if ( (pSmmItems->serviceRoutine)!= NULL){ + serviceRoutine = (void *)FIXUP_PTR(pSmmItems->serviceRoutine); + serviceRoutine(); + } + } + } + TRACE((DMSG_SB_TRACE, "CIMx - Exiting SMM services \n")); +} + + +void softwareSMIservice(void){ + UINT16 dwSmiCmdPort, dwVar; + ReadPMIO(SB_PMIO_REG2A, AccWidthUint16, &dwSmiCmdPort); + ReadIO(dwSmiCmdPort, AccWidthUint16, &dwVar); + TRACE((DMSG_SB_TRACE, "SMI CMD Port Address: %X SMICMD Port value is %X \n", dwSmiCmdPort, dwVar)); +} diff --git a/src/vendorcode/amd/cimx/sb700/USB.c b/src/vendorcode/amd/cimx/sb700/USB.c new file mode 100644 index 0000000..9c5e7b3 --- /dev/null +++ b/src/vendorcode/amd/cimx/sb700/USB.c @@ -0,0 +1,187 @@ +/***************************************************************************** + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + ***************************************************************************/ + + +#include "Platform.h" + + +void usbInitBeforePciEnum(AMDSBCFG* pConfig){ + UINT8 dbVar=0; + + TRACE((DMSG_SB_TRACE, "Entering PreInit Usb \n")); + if (pConfig->Usb1Ohci0){ + dbVar = (pConfig->Usb1Ehci << 2); + dbVar |= ((pConfig->Usb1Ohci0) << 0); + dbVar |= ((pConfig->Usb1Ohci1) << 1); + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG68, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT0+BIT1+BIT2), dbVar ); + } + if (pConfig->Usb2Ohci0){ + dbVar = (pConfig->Usb2Ehci << 6) ; + dbVar |= ((pConfig->Usb2Ohci0) << 4); + dbVar |= ((pConfig->Usb2Ohci1) << 5); + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG68, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT6+BIT4+BIT5), dbVar ); + } + if (pConfig->Usb3Ohci) + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG68, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT7), ((pConfig->Usb3Ohci) << 7) ); + + RWPCI((USB1_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG50+1, AccWidthUint16 | S3_SAVE, ~(UINT32)(BIT4), BIT4); +} + + +void usbInitAfterPciInit(AMDSBCFG* pConfig){ + UINT32 ddBarAddress, ddVar; + + ReadPCI((USB1_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG10, AccWidthUint32, &ddBarAddress);//Get BAR address + if ( (ddBarAddress != -1) && (ddBarAddress != 0) ){ + //Enable Memory access + RWPCI((USB1_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG04, AccWidthUint8, 0, BIT1); + //USB Common PHY CAL & Control Register setting + ddVar = 0x00020F00; + WriteMEM(ddBarAddress+SB_EHCI_BAR_REGC0, AccWidthUint32, &ddVar); + //RPR - IN AND OUT DATA PACKET FIFO THRESHOLD + //EHCI BAR 0xA4 //IN threshold bits[7:0]=0x40 //OUT threshold bits[23:16]=0x40 + RWMEM(ddBarAddress+SB_EHCI_BAR_REGA4, AccWidthUint32, 0xFF00FF00, 0x00400040); + //RPR - EHCI dynamic clock gating feature + //EHCI_BAR 0xBC Bit[12] = 0, For normal operation, the clock gating feature must be disabled. + // Disables HS uFrame babble detection for erratum: EHCI_EOR + 9Ch [11] = 1 + RWMEM(ddBarAddress+SB_EHCI_BAR_REGBC, AccWidthUint16, ~(UINT32)(BIT12+BIT11), BIT11); + } + + ReadPCI((USB2_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG10, AccWidthUint32, &ddBarAddress);//Get BAR address + if ( (ddBarAddress != -1) && (ddBarAddress != 0) ){ + //Enable Memory access + RWPCI((USB2_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG04, AccWidthUint8, 0, BIT1); + //USB Common PHY CAL & Control Register setting + ddVar = 0x00020F00; + WriteMEM(ddBarAddress+SB_EHCI_BAR_REGC0, AccWidthUint32, &ddVar); + //RPR - IN AND OUT DATA PACKET FIFO THRESHOLD + //EHCI BAR 0xA4 //IN threshold bits[7:0]=0x40 //OUT threshold bits[23:16]=0x40 + RWMEM(ddBarAddress+SB_EHCI_BAR_REGA4, AccWidthUint32, 0xFF00FF00, 0x00400040); + //RPR - EHCI dynamic clock gating feature + //EHCI_BAR 0xBC Bit[12] = 0, For normal operation, the clock gating feature must be disabled. + // Disables HS uFrame babble detection for erratum: EHCI_EOR + 9Ch [11] = 1 + RWMEM(ddBarAddress+SB_EHCI_BAR_REGBC, AccWidthUint16, ~(UINT32)(BIT12+BIT11), BIT11); + } + + if (pConfig->UsbPhyPowerDown) + RWPMIO(SB_PMIO_REG65, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT0, BIT0); + else + RWPMIO(SB_PMIO_REG65, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT0, 0); + + // Disable the MSI capability of USB host controllers + RWPCI((USB1_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG40+1, AccWidthUint8 | S3_SAVE, 0xFF, BIT1+BIT0); + RWPCI((USB2_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG40+1, AccWidthUint8 | S3_SAVE, 0xFF, BIT1+BIT0); + RWPCI((USB3_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG40+1, AccWidthUint8 | S3_SAVE, 0xFF, BIT0); + + //RPR recommended setting "EHCI Advance Asynchronous Enhancement DISABLE" + //Set EHCI_pci_configx50[28]='1' to disable the advance async enhancement feature to avoid the bug found in Linux. + //Set EHCI_pci_configx50[6]='1' to disable EHCI MSI support + //RPR recommended setting "EHCI Async Park Mode" + //Set EHCI_pci_configx50[23]='1' to disable "EHCI Async Park Mode support" + // RPR recommended setting "EHCI Advance PHY Power Savings" + // Set EHCI_pci_configx50[31]='1' if SB700 A12 & above + // Fix for EHCI controller driver yellow sign issue under device manager + // when used in conjunction with HSET tool driver. EHCI PCI config 0x50[20]=1 + RWPCI((USB1_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG50, AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, BIT31+BIT28+BIT23+BIT20+BIT6); + RWPCI((USB2_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG50, AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, BIT31+BIT28+BIT23+BIT20+BIT6); + + //RPR recommended setting to, enable fix to cover the corner case S3 wake up issue from some USB 1.1 devices + //OHCI 0_PCI_Config 0x50[16] = 1 + RWPCI((USB1_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG50+2, AccWidthUint8 | S3_SAVE, 0xFF, BIT0); + RWPCI((USB2_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG50+2, AccWidthUint8 | S3_SAVE, 0xFF, BIT0); + RWPCI((USB3_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG50+2, AccWidthUint8 | S3_SAVE, 0xFF, BIT0); + + if (getRevisionID() >= SB700_A14){ + RWPCI((USB1_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG50, AccWidthUint32 | S3_SAVE, ~(UINT32)(BIT28), BIT8+BIT7+BIT4+BIT3); + RWPCI((USB2_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG50, AccWidthUint32 | S3_SAVE, ~(UINT32)(BIT28), BIT8+BIT7+BIT4+BIT3); + + RWPCI((USB1_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, BIT26+BIT25+BIT17); + RWPCI((USB2_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, BIT26+BIT25+BIT17); + RWPCI((USB3_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, BIT26+BIT25); + } + + if (getRevisionID() >= SB700_A15) { + //USB PID Error checking + RWPCI((USB1_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG50+1, AccWidthUint8 | S3_SAVE, 0xFF, BIT1); + RWPCI((USB2_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG50+1, AccWidthUint8 | S3_SAVE, 0xFF, BIT1); + } + + // RPR 6.25 - Optionally disable OHCI isochronous out prefetch + if (pConfig->OhciIsoOutPrefetchDis) { + RWPCI((USB1_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint16 | S3_SAVE, ~(UINT32)(BIT9 + BIT8), 0); + RWPCI((USB2_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint16 | S3_SAVE, ~(UINT32)(BIT9 + BIT8), 0); + RWPCI((USB3_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint16 | S3_SAVE, ~(UINT32)(BIT9 + BIT8), 0); + } + + if ( pConfig->EhciDataCacheDis ) { + // Disable Async Data Cache, EHCI_pci_configx50[26]='1' + RWPCI ((USB1_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG50, AccWidthUint32 | S3_SAVE, ~(UINT32)BIT26, BIT26); + RWPCI ((USB2_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG50, AccWidthUint32 | S3_SAVE, ~(UINT32)BIT26, BIT26); + } +} + + +void usbInitMidPost(AMDSBCFG* pConfig){ + if (pConfig->UsbOhciLegacyEmulation == 0){ + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG60+2, AccWidthUint8 | S3_SAVE, 0xFF, BIT1+BIT0); + RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG64+3, AccWidthUint8 | S3_SAVE, 0xFF, BIT7); + } + else{ + programOhciMmioForEmulation(); + } +} + + +void programOhciMmioForEmulation(void){ + UINT32 ddBarAddress; + + ReadPCI((USB1_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG10, AccWidthUint32, &ddBarAddress);//Get BAR address + ddBarAddress &= 0xFFFFF000; + if ( (ddBarAddress != 0xFFFFF000) && (ddBarAddress != 0) ){ + //Enable Memory access + RWPCI((USB1_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG04, AccWidthUint8, 0, BIT1); + RWMEM(ddBarAddress+SB_OHCI_BAR_REG160, AccWidthUint32, 0, 0); + } + + ReadPCI((USB2_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG10, AccWidthUint32, &ddBarAddress);//Get BAR address + ddBarAddress &= 0xFFFFF000; + if ( (ddBarAddress != 0xFFFFF000) && (ddBarAddress != 0) ){ + //Enable Memory access + RWPCI((USB2_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG04, AccWidthUint8, 0, BIT1); + RWMEM(ddBarAddress+SB_OHCI_BAR_REG160, AccWidthUint32, 0, 0); + } + + ReadPCI((USB3_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG10, AccWidthUint32, &ddBarAddress);//Get BAR address + if ( (ddBarAddress != 0xFFFFF000) && (ddBarAddress != 0) ){ + //Enable Memory access + RWPCI((USB3_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG04, AccWidthUint8, 0, BIT1); + RWMEM(ddBarAddress+SB_OHCI_BAR_REG160, AccWidthUint32, 0, 0); + } +} diff --git a/src/vendorcode/amd/cimx/sb700/sbAMDLIB.h b/src/vendorcode/amd/cimx/sb700/sbAMDLIB.h new file mode 100644 index 0000000..e8f6b38 --- /dev/null +++ b/src/vendorcode/amd/cimx/sb700/sbAMDLIB.h @@ -0,0 +1,196 @@ +/*;******************************************************************************** +; +; Copyright (C) 2012 Advanced Micro Devices, Inc. +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; * Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; * Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution. +; * Neither the name of Advanced Micro Devices, Inc. nor the names of +; its contributors may be used to endorse or promote products derived +; from this software without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;*********************************************************************************/ + +#ifndef _AMD_AMDLIB_H_ +#define _AMD_AMDLIB_H_ + +typedef CHAR8 *va_list; +#ifndef _INTSIZEOF + #define _INTSIZEOF(n)( (sizeof(n) + sizeof(UINTN) - 1) & ~(sizeof(UINTN) - 1) ) +#endif + +// Also support coding convention rules for var arg macros +#ifndef va_start +#define va_start(ap,v) ( ap = (va_list)&(v) + _INTSIZEOF(v) ) +#endif +#define va_arg(ap,t) ( *(t *)((ap += _INTSIZEOF(t)) - _INTSIZEOF(t)) ) +#define va_end(ap) ( ap = (va_list)0 ) + +#ifndef CIMx_DEBUG + #define CIMx_DEBUG 0 +#endif + + +#pragma pack(push,1) + +#define IMAGE_ALIGN 32*1024 +#define NUM_IMAGE_LOCATION 32 + +//Entry Point Call +typedef void (*CIM_IMAGE_ENTRY)(void* pConfig); + +//Hook Call + +typedef struct _Reg8Mask +{ + UINT8 bRegIndex; + UINT8 bANDMask; + UINT8 bORMask; +}REG8MASK; + + +typedef struct _CIMFILEHEADER{ + UINT32 AtiLogo; + UINT32 EntryPoint; + UINT32 ModuleLogo; + UINT32 ImageSize; + UINT16 Version; + UINT8 CheckSum; + UINT8 Reserved1; + UINT32 Reserved2; +}CIMFILEHEADER; + +typedef struct _CPUID_DATA{ + UINT32 REG_EAX; + UINT32 REG_EBX; + UINT32 REG_ECX; + UINT32 REG_EDX; +}CPUID_DATA; + +#ifndef BIT0 + #define BIT0 (1 << 0) +#endif +#ifndef BIT1 + #define BIT1 (1 << 1) +#endif +#ifndef BIT2 + #define BIT2 (1 << 2) +#endif +#ifndef BIT3 + #define BIT3 (1 << 3) +#endif +#ifndef BIT4 + #define BIT4 (1 << 4) +#endif +#ifndef BIT5 + #define BIT5 (1 << 5) +#endif +#ifndef BIT6 + #define BIT6 (1 << 6) +#endif +#ifndef BIT7 + #define BIT7 (1 << 7) +#endif +#ifndef BIT8 + #define BIT8 (1 << 8) +#endif +#ifndef BIT9 + #define BIT9 (1 << 9) +#endif +#ifndef BIT10 + #define BIT10 (1 << 10) +#endif +#ifndef BIT11 + #define BIT11 (1 << 11) +#endif +#ifndef BIT12 + #define BIT12 (1 << 12) +#endif +#ifndef BIT13 + #define BIT13 (1 << 13) +#endif +#ifndef BIT14 + #define BIT14 (1 << 14) +#endif +#ifndef BIT15 + #define BIT15 (1 << 15) +#endif +#ifndef BIT16 + #define BIT16 (1 << 16) +#endif +#ifndef BIT17 + #define BIT17 (1 << 17) +#endif +#ifndef BIT18 + #define BIT18 (1 << 18) +#endif +#ifndef BIT19 + #define BIT19 (1 << 19) +#endif +#ifndef BIT20 + #define BIT20 (1 << 20) +#endif +#ifndef BIT21 + #define BIT21 (1 << 21) +#endif +#ifndef BIT22 + #define BIT22 (1 << 22) +#endif +#ifndef BIT23 + #define BIT23 (1 << 23) +#endif +#ifndef BIT24 + #define BIT24 (1 << 24) +#endif +#ifndef BIT25 + #define BIT25 (1 << 25) +#endif +#ifndef BIT26 + #define BIT26 (1 << 26) +#endif +#ifndef BIT27 + #define BIT27 (1 << 27) +#endif +#ifndef BIT28 + #define BIT28 (1 << 28) +#endif +#ifndef BIT29 + #define BIT29 (1 << 29) +#endif +#ifndef BIT30 + #define BIT30 (1 << 30) +#endif +#ifndef BIT31 + #define BIT31 (1 << 31) +#endif + +#define PCI_ADDRESS(bus,dev,func,reg) \ +(UINT32) ( (((UINT32)bus) << 24) + (((UINT32)dev) << 19) + (((UINT32)func) << 16) + ((UINT32)reg) ) + +#pragma pack(pop) + +typedef enum { + AccWidthUint8 = 0, + AccWidthUint16, + AccWidthUint32, +} ACC_WIDTH; + +#define S3_SAVE 0x80 + +#endif //#ifndef _AMD_AMDLIB_H_

1 0

Patch set updated for coreboot: bd405e4 SB700 southbridge: AMD SB700/SP5100 southbridge CIMX wrapper
by Kerry Sheh Jan. 31, 2012

Jan. 31, 2012

Kerry Sheh (shekairui(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/561 -gerrit commit bd405e477b41082a6d738a3f63ea47a3926469c3 Author: Kerry Sheh <shekairui(a)gmail.com> Date: Tue Jan 31 20:42:18 2012 +0800 SB700 southbridge: AMD SB700/SP5100 southbridge CIMX wrapper Change-Id: If924b7eb176e7d3d82fa394929b653b1ced3a743 Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> --- src/southbridge/amd/Makefile.inc | 1 + src/southbridge/amd/cimx/Kconfig | 3 +- src/southbridge/amd/cimx/Makefile.inc | 3 +- src/southbridge/amd/cimx/sb700/Amd.h | 363 +++++++++++++++++++++++++++ src/southbridge/amd/cimx/sb700/AmdSbLib.h | 181 +++++++++++++ src/southbridge/amd/cimx/sb700/Kconfig | 63 +++++ src/southbridge/amd/cimx/sb700/Makefile.inc | 32 +++ src/southbridge/amd/cimx/sb700/Platform.h | 87 +++++++ src/southbridge/amd/cimx/sb700/bootblock.c | 97 +++++++ src/southbridge/amd/cimx/sb700/cbtypes.h | 53 ++++ src/southbridge/amd/cimx/sb700/chip.h | 42 +++ src/southbridge/amd/cimx/sb700/chip_name.c | 25 ++ src/southbridge/amd/cimx/sb700/early.c | 75 ++++++ src/southbridge/amd/cimx/sb700/late.c | 329 ++++++++++++++++++++++++ src/southbridge/amd/cimx/sb700/lpc.c | 195 ++++++++++++++ src/southbridge/amd/cimx/sb700/lpc.h | 30 +++ src/southbridge/amd/cimx/sb700/sb_cimx.h | 49 ++++ src/southbridge/amd/cimx/sb700/smbus.c | 270 ++++++++++++++++++++ src/southbridge/amd/cimx/sb700/smbus.h | 82 ++++++ 19 files changed, 1978 insertions(+), 2 deletions(-) diff --git a/src/southbridge/amd/Makefile.inc b/src/southbridge/amd/Makefile.inc index 406a0b3..54245f2 100644 --- a/src/southbridge/amd/Makefile.inc +++ b/src/southbridge/amd/Makefile.inc @@ -12,6 +12,7 @@ subdirs-$(CONFIG_SOUTHBRIDGE_AMD_SP5100) += sb700 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CS5530) += cs5530 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CS5535) += cs5535 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CS5536) += cs5536 +subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += cimx subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += cimx subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += cimx diff --git a/src/southbridge/amd/cimx/Kconfig b/src/southbridge/amd/cimx/Kconfig index 8f12b90..f61b75a 100644 --- a/src/southbridge/amd/cimx/Kconfig +++ b/src/southbridge/amd/cimx/Kconfig @@ -1,7 +1,7 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. +# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -21,5 +21,6 @@ config AMD_SB_CIMX bool default n +source src/southbridge/amd/cimx/sb700/Kconfig source src/southbridge/amd/cimx/sb800/Kconfig source src/southbridge/amd/cimx/sb900/Kconfig diff --git a/src/southbridge/amd/cimx/Makefile.inc b/src/southbridge/amd/cimx/Makefile.inc index 421a11c..80c6378 100644 --- a/src/southbridge/amd/cimx/Makefile.inc +++ b/src/southbridge/amd/cimx/Makefile.inc @@ -1,7 +1,7 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 Advanced Micro Devices, Inc. +# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -16,5 +16,6 @@ # along with this program; if not, write to the Free Software # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # +subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += sb700 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += sb800 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += sb900 diff --git a/src/southbridge/amd/cimx/sb700/Amd.h b/src/southbridge/amd/cimx/sb700/Amd.h new file mode 100644 index 0000000..fbd5531 --- /dev/null +++ b/src/southbridge/amd/cimx/sb700/Amd.h @@ -0,0 +1,363 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _AMD_H_ +#define _AMD_H_ + +// AGESA Types and Definitions +#ifndef NULL +#define NULL 0 +#endif + +#define LAST_ENTRY 0xFFFFFFFF +#define IOCF8 0xCF8 +#define IOCFC 0xCFC +#define IN +#define OUT + +#ifndef Int16FromChar +#define Int16FromChar(a,b) ((a) << 0 | (b) << 8) +#endif +#ifndef Int32FromChar +#define Int32FromChar(a,b,c,d) ((a) << 0 | (b) << 8 | (c) << 16 | (d) << 24) +#endif + +#define IMAGE_SIGNATURE Int32FromChar ('$', 'A', 'M', 'D') + +typedef unsigned int AGESA_STATUS; + +#define AGESA_SUCCESS ((AGESA_STATUS) 0x0) +#define AGESA_ALERT ((AGESA_STATUS) 0x40000000) +#define AGESA_WARNING ((AGESA_STATUS) 0x40000001) +#define AGESA_UNSUPPORTED ((AGESA_STATUS) 0x80000003) +#define AGESA_ERROR ((AGESA_STATUS) 0xC0000001) +#define AGESA_CRITICAL ((AGESA_STATUS) 0xC0000002) +#define AGESA_FATAL ((AGESA_STATUS) 0xC0000003) + +typedef AGESA_STATUS (*CALLOUT_ENTRY) (unsigned int Param1, unsigned int Param2, void* ConfigPtr); +typedef AGESA_STATUS (*IMAGE_ENTRY) (IN OUT void* ConfigPtr); +typedef AGESA_STATUS (*MODULE_ENTRY) (IN OUT void* ConfigPtr); + +///This allocation type is used by the AmdCreateStruct entry point +typedef enum { + PreMemHeap = 0, ///< Create heap in cache. + PostMemDram, ///< Create heap in memory. + ByHost ///< Create heap by Host. +} ALLOCATION_METHOD; + +/// These width descriptors are used by the library function, and others, to specify the data size +typedef enum ACCESS_WIDTH { + AccessWidth8 = 1, ///< Access width is 8 bits. + AccessWidth16, ///< Access width is 16 bits. + AccessWidth32, ///< Access width is 32 bits. + AccessWidth64, ///< Access width is 64 bits. + + AccessS3SaveWidth8 = 0x81, ///< Save 8 bits data. + AccessS3SaveWidth16, ///< Save 16 bits data. + AccessS3SaveWidth32, ///< Save 32 bits data. + AccessS3SaveWidth64, ///< Save 64 bits data. +} ACCESS_WIDTH; + +// AGESA Structures + +/// The standard header for all AGESA services. +typedef struct _AMD_CONFIG_PARAMS { + IN unsigned int ImageBasePtr; ///< The AGESA Image base address. + IN unsigned int Func; ///< The service desired, @sa dispatch.h. + IN unsigned int AltImageBasePtr; ///< Alternate Image location + IN unsigned int PcieBasePtr; ///< PCIe MMIO Base address, if configured. + union { ///< Callback pointer + IN unsigned long long PlaceHolder; ///< Place holder + IN CALLOUT_ENTRY CalloutPtr; ///< For Callout from AGESA + } CALLBACK; + IN OUT unsigned int Reserved[2]; ///< This space is reserved for future use. +} AMD_CONFIG_PARAMS; + + +/// AGESA Binary module header structure +typedef struct _AMD_IMAGE_HEADER { + IN unsigned int Signature; ///< Binary Signature + IN signed char CreatorID[8]; ///< 8 characters ID + IN signed char Version[12]; ///< 12 characters version + IN unsigned int ModuleInfoOffset; ///< Offset of module + IN unsigned int EntryPointAddress; ///< Entry address + IN unsigned int ImageBase; ///< Image base + IN unsigned int RelocTableOffset; ///< Relocate Table offset + IN unsigned int ImageSize; ///< Size + IN unsigned short Checksum; ///< Checksum + IN unsigned char ImageType; ///< Type + IN unsigned char V_Reserved; ///< Reserved +} AMD_IMAGE_HEADER; + +/// AGESA Binary module header structure +typedef struct _AMD_MODULE_HEADER { + IN unsigned int ModuleHeaderSignature; ///< Module signature + IN signed char ModuleIdentifier[8]; ///< 8 characters ID + IN signed char ModuleVersion[12]; ///< 12 characters version + IN MODULE_ENTRY ModuleDispatcherPtr; ///< A pointer point to dispatcher + IN struct _AMD_MODULE_HEADER *NextBlockPtr; ///< Next module header link +} AMD_MODULE_HEADER; + +#define FUNC_0 0 // bit-placed for PCI address creation +#define FUNC_1 1 +#define FUNC_2 2 +#define FUNC_3 3 +#define FUNC_4 4 +#define FUNC_5 5 +#define FUNC_6 6 +#define FUNC_7 7 + +// SBDFO - Segment Bus Device Function Offset +// 31:28 Segment (4-bits) +// 27:20 Bus (8-bits) +// 19:15 Device (5-bits) +// 14:12 Function (3-bits) +// 11:00 Offset (12-bits) + +#if 0 +#define MAKE_SBDFO(Seg, Bus, Dev, Fun, Off) ((((unsigned int) (Seg)) << 28) | (((unsigned int) (Bus)) << 20) | \ + (((unsigned int) (Dev)) << 15) | (((unsigned int) (Fun)) << 12) | ((unsigned int) (Off))) +#endif +#define ILLEGAL_SBDFO 0xFFFFFFFF + +/// CPUID data received registers format +typedef struct _SB_CPUID_DATA { + IN OUT unsigned int EAX_Reg; ///< CPUID instruction result in EAX + IN OUT unsigned int EBX_Reg; ///< CPUID instruction result in EBX + IN OUT unsigned int ECX_Reg; ///< CPUID instruction result in ECX + IN OUT unsigned int EDX_Reg; ///< CPUID instruction result in EDX +} SB_CPUID_DATA; + +#define WARM_RESET 1 +#define COLD_RESET 2 // Cold reset +#define RESET_CPU 4 // Triggers a CPU reset + +/// HT frequency for external callbacks +typedef enum { + HT_FREQUENCY_200M = 0, ///< HT speed 200 for external callbacks + HT_FREQUENCY_400M = 2, ///< HT speed 400 for external callbacks + HT_FREQUENCY_600M = 4, ///< HT speed 600 for external callbacks + HT_FREQUENCY_800M = 5, ///< HT speed 800 for external callbacks + HT_FREQUENCY_1000M = 6, ///< HT speed 1000 for external callbacks + HT_FREQUENCY_1200M = 7, ///< HT speed 1200 for external callbacks + HT_FREQUENCY_1400M = 8, ///< HT speed 1400 for external callbacks + HT_FREQUENCY_1600M = 9, ///< HT speed 1600 for external callbacks + HT_FREQUENCY_1800M = 10, ///< HT speed 1800 for external callbacks + HT_FREQUENCY_2000M = 11, ///< HT speed 2000 for external callbacks + HT_FREQUENCY_2200M = 12, ///< HT speed 2200 for external callbacks + HT_FREQUENCY_2400M = 13, ///< HT speed 2400 for external callbacks + HT_FREQUENCY_2600M = 14, ///< HT speed 2600 for external callbacks + HT_FREQUENCY_2800M = 17, ///< HT speed 2800 for external callbacks + HT_FREQUENCY_3000M = 18, ///< HT speed 3000 for external callbacks + HT_FREQUENCY_3200M = 19 ///< HT speed 3200 for external callbacks +} HT_FREQUENCIES; + +#ifndef BIT0 +#define BIT0 0x0000000000000001ull +#endif +#ifndef BIT1 +#define BIT1 0x0000000000000002ull +#endif +#ifndef BIT2 +#define BIT2 0x0000000000000004ull +#endif +#ifndef BIT3 +#define BIT3 0x0000000000000008ull +#endif +#ifndef BIT4 +#define BIT4 0x0000000000000010ull +#endif +#ifndef BIT5 +#define BIT5 0x0000000000000020ull +#endif +#ifndef BIT6 +#define BIT6 0x0000000000000040ull +#endif +#ifndef BIT7 +#define BIT7 0x0000000000000080ull +#endif +#ifndef BIT8 +#define BIT8 0x0000000000000100ull +#endif +#ifndef BIT9 +#define BIT9 0x0000000000000200ull +#endif +#ifndef BIT10 +#define BIT10 0x0000000000000400ull +#endif +#ifndef BIT11 +#define BIT11 0x0000000000000800ull +#endif +#ifndef BIT12 +#define BIT12 0x0000000000001000ull +#endif +#ifndef BIT13 +#define BIT13 0x0000000000002000ull +#endif +#ifndef BIT14 +#define BIT14 0x0000000000004000ull +#endif +#ifndef BIT15 +#define BIT15 0x0000000000008000ull +#endif +#ifndef BIT16 +#define BIT16 0x0000000000010000ull +#endif +#ifndef BIT17 +#define BIT17 0x0000000000020000ull +#endif +#ifndef BIT18 +#define BIT18 0x0000000000040000ull +#endif +#ifndef BIT19 +#define BIT19 0x0000000000080000ull +#endif +#ifndef BIT20 +#define BIT20 0x0000000000100000ull +#endif +#ifndef BIT21 +#define BIT21 0x0000000000200000ull +#endif +#ifndef BIT22 +#define BIT22 0x0000000000400000ull +#endif +#ifndef BIT23 +#define BIT23 0x0000000000800000ull +#endif +#ifndef BIT24 +#define BIT24 0x0000000001000000ull +#endif +#ifndef BIT25 +#define BIT25 0x0000000002000000ull +#endif +#ifndef BIT26 +#define BIT26 0x0000000004000000ull +#endif +#ifndef BIT27 +#define BIT27 0x0000000008000000ull +#endif +#ifndef BIT28 +#define BIT28 0x0000000010000000ull +#endif +#ifndef BIT29 +#define BIT29 0x0000000020000000ull +#endif +#ifndef BIT30 +#define BIT30 0x0000000040000000ull +#endif +#ifndef BIT31 +#define BIT31 0x0000000080000000ull +#endif +#ifndef BIT32 +#define BIT32 0x0000000100000000ull +#endif +#ifndef BIT33 +#define BIT33 0x0000000200000000ull +#endif +#ifndef BIT34 +#define BIT34 0x0000000400000000ull +#endif +#ifndef BIT35 +#define BIT35 0x0000000800000000ull +#endif +#ifndef BIT36 +#define BIT36 0x0000001000000000ull +#endif +#ifndef BIT37 +#define BIT37 0x0000002000000000ull +#endif +#ifndef BIT38 +#define BIT38 0x0000004000000000ull +#endif +#ifndef BIT39 +#define BIT39 0x0000008000000000ull +#endif +#ifndef BIT40 +#define BIT40 0x0000010000000000ull +#endif +#ifndef BIT41 +#define BIT41 0x0000020000000000ull +#endif +#ifndef BIT42 +#define BIT42 0x0000040000000000ull +#endif +#ifndef BIT43 +#define BIT43 0x0000080000000000ull +#endif +#ifndef BIT44 +#define BIT44 0x0000100000000000ull +#endif +#ifndef BIT45 +#define BIT45 0x0000200000000000ull +#endif +#ifndef BIT46 +#define BIT46 0x0000400000000000ull +#endif +#ifndef BIT47 +#define BIT47 0x0000800000000000ull +#endif +#ifndef BIT48 +#define BIT48 0x0001000000000000ull +#endif +#ifndef BIT49 +#define BIT49 0x0002000000000000ull +#endif +#ifndef BIT50 +#define BIT50 0x0004000000000000ull +#endif +#ifndef BIT51 +#define BIT51 0x0008000000000000ull +#endif +#ifndef BIT52 +#define BIT52 0x0010000000000000ull +#endif +#ifndef BIT53 +#define BIT53 0x0020000000000000ull +#endif +#ifndef BIT54 +#define BIT54 0x0040000000000000ull +#endif +#ifndef BIT55 +#define BIT55 0x0080000000000000ull +#endif +#ifndef BIT56 +#define BIT56 0x0100000000000000ull +#endif +#ifndef BIT57 +#define BIT57 0x0200000000000000ull +#endif +#ifndef BIT58 +#define BIT58 0x0400000000000000ull +#endif +#ifndef BIT59 +#define BIT59 0x0800000000000000ull +#endif +#ifndef BIT60 +#define BIT60 0x1000000000000000ull +#endif +#ifndef BIT61 +#define BIT61 0x2000000000000000ull +#endif +#ifndef BIT62 +#define BIT62 0x4000000000000000ull +#endif +#ifndef BIT63 +#define BIT63 0x8000000000000000ull +#endif +#endif diff --git a/src/southbridge/amd/cimx/sb700/AmdSbLib.h b/src/southbridge/amd/cimx/sb700/AmdSbLib.h new file mode 100644 index 0000000..2812605 --- /dev/null +++ b/src/southbridge/amd/cimx/sb700/AmdSbLib.h @@ -0,0 +1,181 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _AMD_SB_LIB_H_ +#define _AMD_SB_LIB_H_ + +typedef signed char *va_list; +#ifndef _INTSIZEOF + #define _INTSIZEOF (n) ( (sizeof (n) + sizeof (UINTN) - 1) & ~(sizeof (UINTN) - 1) ) +#endif + +// Also support coding convention rules for var arg macros +#ifndef va_start + #define va_start(ap, v) ( ap = (va_list)&(v) + _INTSIZEOF (v) ) +#endif +#define va_arg(ap, t) ( *(t *) ((ap += _INTSIZEOF (t)) - _INTSIZEOF (t)) ) +#define va_end(ap) ( ap = (va_list)0 ) + + +#pragma pack (push, 1) + +#define IMAGE_ALIGN 32*1024 +#define NUM_IMAGE_LOCATION 32 + +//Entry Point Call +typedef void (*CIM_IMAGE_ENTRY) (void* pConfig); + +//Hook Call + +typedef struct _CIMFILEHEADER +{ + unsigned int AMDLogo; + unsigned long long CreatorID; + unsigned int Version1; + unsigned int Version2; + unsigned int Version3; + unsigned int ModuleInfoOffset; + unsigned int EntryPoint; + unsigned int ImageBase; + unsigned int RelocTableOffset; + unsigned int ImageSize; + unsigned short CheckSum; + unsigned char ImageType; + unsigned char Reserved2; +} CIMFILEHEADER; + +#ifndef BIT0 + #define BIT0 (1 << 0) +#endif +#ifndef BIT1 + #define BIT1 (1 << 1) +#endif +#ifndef BIT2 + #define BIT2 (1 << 2) +#endif +#ifndef BIT3 + #define BIT3 (1 << 3) +#endif +#ifndef BIT4 + #define BIT4 (1 << 4) +#endif +#ifndef BIT5 + #define BIT5 (1 << 5) +#endif +#ifndef BIT6 + #define BIT6 (1 << 6) +#endif +#ifndef BIT7 + #define BIT7 (1 << 7) +#endif +#ifndef BIT8 + #define BIT8 (1 << 8) +#endif +#ifndef BIT9 + #define BIT9 (1 << 9) +#endif +#ifndef BIT10 + #define BIT10 (1 << 10) +#endif +#ifndef BIT11 + #define BIT11 (1 << 11) +#endif +#ifndef BIT12 + #define BIT12 (1 << 12) +#endif +#ifndef BIT13 + #define BIT13 (1 << 13) +#endif +#ifndef BIT14 + #define BIT14 (1 << 14) +#endif +#ifndef BIT15 + #define BIT15 (1 << 15) +#endif +#ifndef BIT16 + #define BIT16 (1 << 16) +#endif +#ifndef BIT17 + #define BIT17 (1 << 17) +#endif +#ifndef BIT18 + #define BIT18 (1 << 18) +#endif +#ifndef BIT19 + #define BIT19 (1 << 19) +#endif +#ifndef BIT20 + #define BIT20 (1 << 20) +#endif +#ifndef BIT21 + #define BIT21 (1 << 21) +#endif +#ifndef BIT22 + #define BIT22 (1 << 22) +#endif +#ifndef BIT23 + #define BIT23 (1 << 23) +#endif +#ifndef BIT24 + #define BIT24 (1 << 24) +#endif +#ifndef BIT25 + #define BIT25 (1 << 25) +#endif +#ifndef BIT26 + #define BIT26 (1 << 26) +#endif +#ifndef BIT27 + #define BIT27 (1 << 27) +#endif +#ifndef BIT28 + #define BIT28 (1 << 28) +#endif +#ifndef BIT29 + #define BIT29 (1 << 29) +#endif +#ifndef BIT30 + #define BIT30 (1 << 30) +#endif +#ifndef BIT31 + #define BIT31 (1 << 31) +#endif + +#pragma pack (pop) + +typedef enum +{ + AccWidthUint8 = 0, + AccWidthUint16, + AccWidthUint32, +} ACC_WIDTH; + +#define S3_SAVE 0x80 + +/** + * AmdSbDispatcher - Dispatch Southbridge function + * + * + * + * @param[in] pConfig Southbridge configuration structure pointer. + * + */ +AGESA_STATUS AmdSbDispatcher (IN void *pConfig); + +#endif diff --git a/src/southbridge/amd/cimx/sb700/Kconfig b/src/southbridge/amd/cimx/sb700/Kconfig new file mode 100644 index 0000000..27338fc --- /dev/null +++ b/src/southbridge/amd/cimx/sb700/Kconfig @@ -0,0 +1,63 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2012 Advanced Micro Devices, Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config SOUTHBRIDGE_AMD_CIMX_SB700 + bool + select IOAPIC + select AMD_SB_CIMX + +if SOUTHBRIDGE_AMD_CIMX_SB700 +config SATA_CONTROLLER_MODE + hex + default 0x0 + help + 0x0 = Native IDE mode. + 0x1 = RAID mode. + 0x2 = AHCI mode. + 0x3 = Legacy IDE mode. + 0x4 = IDE->AHCI mode. + 0x5 = AHCI mode as 7804 ID (AMD driver). + 0x6 = IDE->AHCI mode as 7804 ID (AMD driver). + +config PCIB_ENABLE + bool + default n + help + n = Disable PCI Bridge Device 14 Function 4. + y = Enable PCI Bridge Device 14 Function 4. + +config ACPI_SCI_IRQ + hex + default 0x9 + help + Set SCI IRQ to 9. +config BOOTBLOCK_SOUTHBRIDGE_INIT + string + default "southbridge/amd/cimx/sb700/bootblock.c" + +config REDIRECT_SBCIMX_TRACE_TO_SERIAL + bool "Redirect AMD Southbridge CIMX Trace to serial console" + default n + help + This Option allows you to redirect the AMD Southbridge CIMX Trace + debug information to the serial console. + + Warning: Only enable this option when debuging or tracing AMD CIMX code. +endif #SOUTHBRIDGE_AMD_CIMX_SB700 + diff --git a/src/southbridge/amd/cimx/sb700/Makefile.inc b/src/southbridge/amd/cimx/sb700/Makefile.inc new file mode 100644 index 0000000..3bb8397 --- /dev/null +++ b/src/southbridge/amd/cimx/sb700/Makefile.inc @@ -0,0 +1,32 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += ../../../../../src/vendorcode/amd/cimx/sb700 + +# SB700 Platform Files + +romstage-y += early.c +romstage-y += smbus.c + +ramstage-y += late.c + +driver-y += smbus.c +driver-y += lpc.c + + diff --git a/src/southbridge/amd/cimx/sb700/Platform.h b/src/southbridge/amd/cimx/sb700/Platform.h new file mode 100644 index 0000000..15e5b07 --- /dev/null +++ b/src/southbridge/amd/cimx/sb700/Platform.h @@ -0,0 +1,87 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _AMD_SB_CIMx_PLATFORM_H_ +#define _AMD_SB_CIMx_PLATFORM_H_ + +#pragma pack(push,1) + +#include "cbtypes.h" +#include <console/console.h> +#include <console/loglevel.h> +#ifdef NULL +#undef NULL +#endif +#define NULL 0 + +typedef struct _EXT_PCI_ADDR{ + UINT32 Reg :16; + UINT32 Func:3; + UINT32 Dev :5; + UINT32 Bus :8; +}EXT_PCI_ADDR; + + +typedef union _PCI_ADDR{ + UINT32 ADDR; + EXT_PCI_ADDR Addr; +}PCI_ADDR; + + +#ifdef CIM_DEBUG + +#if CIM_DEBUG & 2 +void TraceDebug( UINT32 Level, CHAR8 *Format, ...); +#define TRACE(Arguments) TraceDebug Arguments +#else +#define TRACE(Arguments) +#endif + +#if CIM_DEBUG & 1 +void TraceCode ( UINT32 Level, UINT32 Code); +#define TRACECODE(Arguments) TraceCode Arguments +#else +#define TRACECODE(Arguments) +#endif +#else + #if CONFIG_REDIRECT_SBCIMX_TRACE_TO_SERIAL + #define TRACE(Arguments) printk Arguments + #else + #define TRACE(Arguments) do {} while(0) + #endif + #define TRACECODE(Arguments) +#endif + +#define FIXUP_PTR(ptr) ptr + +#pragma pack(pop) + +#include "OEM.h" +#include "Amd.h" +#include "ACPILIB.h" +#include "SBTYPE.h" +#include "sbAMDLIB.h" +#include "SBCMNLIB.h" +#include "SB700.h" +#include "SBDEF.h" + +#define DMSG_SB_TRACE 0x02 + +#endif //#ifndef _AMD_SB_CIMx_PLATFORM_H_ + diff --git a/src/southbridge/amd/cimx/sb700/bootblock.c b/src/southbridge/amd/cimx/sb700/bootblock.c new file mode 100644 index 0000000..401c039 --- /dev/null +++ b/src/southbridge/amd/cimx/sb700/bootblock.c @@ -0,0 +1,97 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include <arch/io.h> +#include <arch/romcc_io.h> + + +#if CONFIG_CONSOLE_POST == 1 + +/* Data */ +#define UART_RBR 0x00 +#define UART_TBR 0x00 + +/* Control */ +#define UART_IER 0x01 +#define UART_IIR 0x02 +#define UART_FCR 0x02 +#define UART_LCR 0x03 +#define UART_MCR 0x04 +#define UART_DLL 0x00 +#define UART_DLM 0x01 + +/* Status */ +#define UART_LSR 0x05 +#define UART_MSR 0x06 +#define UART_SCR 0x07 + +#ifndef CONFIG_TTYS0_DIV +#if ((115200%CONFIG_TTYS0_BAUD) != 0) +#error Bad ttys0 baud rate +#endif +#define CONFIG_TTYS0_DIV (115200/CONFIG_TTYS0_BAUD) +#endif // CONFIG_TTYS0_DIV + +#define UART_LCS CONFIG_TTYS0_LCS + +#endif // CONFIG_CONSOLE_POST == 1 + + +static void sb700_enable_rom(void) +{ + u32 word; + u32 dword; + device_t dev; + + dev = PCI_DEV(0, 0x14, 0x03); + /* SB700 LPC Bridge 0:20:3:44h. + * BIT6: Port Enable for serial port 0x3f8-0x3ff + * BIT29: Port Enable for KBC port 0x60 and 0x64 + * BIT30: Port Enable for ACPI Micro-Controller port 0x66 and 0x62 + */ + dword = pci_io_read_config32(dev, 0x44); + //dword |= (1<<6) | (1<<29) | (1<<30) ; + /*Turn on all of LPC IO Port decode enable */ + dword = 0xffffffff; + pci_io_write_config32(dev, 0x44, dword); + + /* SB700 LPC Bridge 0:20:3:48h. + * BIT0: Port Enable for SuperIO 0x2E-0x2F + * BIT1: Port Enable for SuperIO 0x4E-0x4F + * BIT4: Port Enable for LPC ROM Address Arrage2 (0x68-0x6C) + * BIT6: Port Enable for RTC IO 0x70-0x73 + * BIT21: Port Enable for Port 0x80 + */ + dword = pci_io_read_config32(dev, 0x48); + dword |= (1<<0) | (1<<1) | (1<<4) | (1<<6) | (1<<21) ; + pci_io_write_config32(dev, 0x48, dword); + + /* Enable 4MB rom access at 0xFFE00000 - 0xFFFFFFFF */ + /* Set the 4MB enable bits */ + word = pci_io_read_config16(dev, 0x6c); + word = 0xFFC0; + pci_io_write_config16(dev, 0x6c, word); +} + +static void bootblock_southbridge_init(void) +{ + /* Setup the rom access for 2M */ + sb700_enable_rom(); +} diff --git a/src/southbridge/amd/cimx/sb700/cbtypes.h b/src/southbridge/amd/cimx/sb700/cbtypes.h new file mode 100644 index 0000000..d37e1e3 --- /dev/null +++ b/src/southbridge/amd/cimx/sb700/cbtypes.h @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _CBTYPES_H_ +#define _CBTYPES_H_ + +//#include <stdint.h> + +typedef signed long long __int64; +typedef void VOID; +typedef unsigned int UINTN; +typedef signed char CHAR8; +typedef unsigned char UINT8; +typedef unsigned short UINT16; +typedef unsigned int UINT32; +typedef unsigned long long UINT64; + +#ifndef TRUE +#define TRUE 1 +#endif +#ifndef FALSE +#define FALSE 0 +#endif +typedef unsigned char BOOLEAN; + +#ifndef VOLATILE +#define VOLATILE volatile +#endif + +#ifndef IN +#define IN +#endif +#ifndef OUT +#define OUT +#endif + +#endif diff --git a/src/southbridge/amd/cimx/sb700/chip.h b/src/southbridge/amd/cimx/sb700/chip.h new file mode 100644 index 0000000..ef294f4 --- /dev/null +++ b/src/southbridge/amd/cimx/sb700/chip.h @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _CIMX_SB700_CHIP_H_ +#define _CIMX_SB700_CHIP_H_ + +extern struct chip_operations southbridge_amd_cimx_sb700_ops; + +/* + * configuration set in mainboard/devicetree.cb + * boot_switch_sata_ide: + * 0 -set SATA as primary, PATA(IDE) as secondary. + * 1 -set PATA(IDE) as primary, SATA as secondary. if you want to boot from IDE, + * gpp_configuration - The configuration of General Purpose Port A/B/C/D + * 0(GPP_CFGMODE_X4000) -PortA Lanes[3:0] + * 2(GPP_CFGMODE_X2200) -PortA Lanes[1:0], PortB Lanes[3:2] + * 3(GPP_CFGMODE_X2110) -PortA Lanes[1:0], PortB Lane2, PortC Lane3 + * 4(GPP_CFGMODE_X1111) -PortA Lanes0, PortB Lane1, PortC Lane2, PortD Lane3 + */ +struct southbridge_amd_cimx_sb700_config +{ + u32 boot_switch_sata_ide : 1; + u8 gpp_configuration; +}; + +#endif /* _CIMX_SB700_CHIP_H_ */ diff --git a/src/southbridge/amd/cimx/sb700/chip_name.c b/src/southbridge/amd/cimx/sb700/chip_name.c new file mode 100644 index 0000000..13d2276 --- /dev/null +++ b/src/southbridge/amd/cimx/sb700/chip_name.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include "chip.h" + +struct chip_operations southbridge_amd_cimx_sb700_ops = { + CHIP_NAME("AMD South Bridge SB700") +}; diff --git a/src/southbridge/amd/cimx/sb700/early.c b/src/southbridge/amd/cimx/sb700/early.c new file mode 100644 index 0000000..bc3d944 --- /dev/null +++ b/src/southbridge/amd/cimx/sb700/early.c @@ -0,0 +1,75 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +//#include <config.h> +#include <stdint.h> +#include <device/pci_ids.h> +#include <arch/io.h> /* inl, outl */ +#include <arch/romcc_io.h> /* device_t */ +#include "Platform.h" +#include "sb_cimx.h" +#include "sb700_cfg.h" /*sb700_cimx_config*/ +#include <console/console.h> +#include <console/loglevel.h> +#include "smbus.h" + + +#if CONFIG_RAMINIT_SYSINFO == 1 +/** + * @brief Get SouthBridge device number + * @param[in] bus target bus number + * @return southbridge device number + */ +u32 get_sbdn(u32 bus) +{ + device_t dev; + + printk(BIOS_DEBUG, "SB700 - Early.c - get_sbdn - Start.\n"); + //dev = PCI_DEV(bus, 0x14, 0); + dev = pci_locate_device_on_bus( + PCI_ID(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SB700_SM), + bus); + + printk(BIOS_DEBUG, "SB700 - Early.c - get_sbdn - End.\n"); + return (dev >> 15) & 0x1f; +} +#endif + +/** + * @brief Enable A-Link Express Configuration DMA Access. + */ + +/** + * @brief South Bridge CIMx romstage entry, + * wrapper of sbPowerOnInit entry point. + */ +void sb_Poweron_Init(void) +{ + AMDSBCFG sb_early_cfg; + + printk(BIOS_DEBUG, "cimx/sb700 early.c, %s() Start:\n", __func__); + /* Enable A-Link Base Address */ + //sb_enable_alink (); + + sb700_cimx_config(&sb_early_cfg); + sbPowerOnInit(&sb_early_cfg); + printk(BIOS_DEBUG, "cimx/sb700 early.c, %s() End\n", __func__); +} + diff --git a/src/southbridge/amd/cimx/sb700/late.c b/src/southbridge/amd/cimx/sb700/late.c new file mode 100644 index 0000000..8d13cd8 --- /dev/null +++ b/src/southbridge/amd/cimx/sb700/late.c @@ -0,0 +1,329 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include <device/device.h> /* device_t */ +#include <device/pci.h> /* device_operations */ +#include <device/pci_ids.h> +#include <arch/ioapic.h> +#include <device/smbus.h> /* smbus_bus_operations */ +#include <console/console.h> /* printk */ +#include "lpc.h" /* lpc_read_resources */ +#include "Platform.h" /* Platfrom Specific Definitions */ +#include "sb_cimx.h" +#include "sb700_cfg.h" /* sb700 Cimx configuration */ +#include "chip.h" /* struct southbridge_amd_cimx_sb700_config */ + + +/*implement in mainboard.c*/ +void set_pcie_reset(void); +void set_pcie_dereset(void); + +static AMDSBCFG sb_late_cfg; //global, init in sb700_cimx_config +static AMDSBCFG *sb_config = &sb_late_cfg; + + +/** + * @brief Entry point of Southbridge CIMx callout + * + * prototype UINT32 (*SBCIM_HOOK_ENTRY)(UINT32 Param1, UINT32 Param2, void* pConfig) + * + * @param[in] func Southbridge CIMx Function ID. + * @param[in] data Southbridge Input Data. + * @param[in] sb_config Southbridge configuration structure pointer. + * + */ +u32 sb700_callout_entry(u32 func, u32 data, void* config) +{ + u32 ret = 0; + + printk(BIOS_DEBUG, "SB700 - Late.c - sb700_callout_entry - Start.\n"); + printk(BIOS_DEBUG, "SB700 - Late.c - sb700_callout_entry - End.\n"); + return ret; +} + + +static struct pci_operations lops_pci = { + .set_subsystem = pci_dev_set_subsystem, +}; + +static void lpc_enable_resources(device_t dev) +{ + + printk(BIOS_DEBUG, "SB700 - Late.c - lpc_enable_resources - Start.\n"); + pci_dev_enable_resources(dev); + lpc_enable_childrens_resources(dev); + printk(BIOS_DEBUG, "SB700 - Late.c - lpc_enable_resources - End.\n"); +} + +static struct device_operations lpc_ops = { + .read_resources = lpc_read_resources, + .set_resources = lpc_set_resources, + .enable_resources = lpc_enable_resources, + .init = 0, + .scan_bus = scan_static_bus, + .ops_pci = &lops_pci, +}; + +static const struct pci_driver lpc_driver __pci_driver = { + .ops = &lpc_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_SB700_LPC, +}; + + +static struct device_operations sata_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = 0, + .scan_bus = 0, + .ops_pci = &lops_pci, +}; + +static const struct pci_driver sata_driver __pci_driver = { + .ops = &sata_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_SB700_SATA, //SATA IDE Mode 4390 +}; + +#if CONFIG_USBDEBUG +static void usb_set_resources(struct device *dev) +{ + struct resource *res; + u32 base; + u32 old_debug; + + printk(BIOS_DEBUG, "SB700 - Late.c - usb_set_resources - Start.\n"); + old_debug = get_ehci_debug(); + set_ehci_debug(0); + + pci_dev_set_resources(dev); + + res = find_resource(dev, 0x10); + set_ehci_debug(old_debug); + if (!res) + return; + base = res->base; + set_ehci_base(base); + report_resource_stored(dev, res, ""); + printk(BIOS_DEBUG, "SB700 - Late.c - usb_set_resources - End.\n"); +} +#endif + + +static struct device_operations usb_ops = { + .read_resources = pci_dev_read_resources, +#if CONFIG_USBDEBUG + .set_resources = usb_set_resources, +#else + .set_resources = pci_dev_set_resources, +#endif + .enable_resources = pci_dev_enable_resources, + .init = 0, + .scan_bus = 0, + .ops_pci = &lops_pci, +}; + +/* + * The pci id of usb ctrl 0 and 1 are the same. + */ +static const struct pci_driver usb_ohci123_driver __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_SB700_USB_18_0, /* OHCI-USB1, OHCI-USB2, OHCI-USB3 */ +}; + +static const struct pci_driver usb_ohci3_driver __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_SB700_USB_18_1, +}; + +static const struct pci_driver usb_ehci123_driver __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_SB700_USB_18_2, /* EHCI-USB1, EHCI-USB2, EHCI-USB3 */ +}; + +static const struct pci_driver usb_ohci4_driver __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_SB700_USB_20_5, /* OHCI-USB4 */ +}; + +static struct device_operations azalia_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = 0, + .scan_bus = 0, + .ops_pci = &lops_pci, +}; + +static const struct pci_driver azalia_driver __pci_driver = { + .ops = &azalia_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_SB700_HDA, +}; + +#ifdef UNUSED_CODE +static struct device_operations gec_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = 0, + .scan_bus = 0, + .ops_pci = &lops_pci, +}; +#endif + +static struct device_operations pci_ops = { + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .init = 0, + .scan_bus = pci_scan_bridge, + .reset_bus = pci_bus_reset, + .ops_pci = &lops_pci, +}; + +static const struct pci_driver pci_driver __pci_driver = { + .ops = &pci_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_SB700_PCI, +}; + + +static void sb700_enable(device_t dev) +{ + struct southbridge_amd_cimx_sb700_config *sb_chip = + (struct southbridge_amd_cimx_sb700_config *)(dev->chip_info); + + printk(BIOS_DEBUG, "sb700_enable() "); + switch (dev->path.pci.devfn) { + case (0x11 << 3) | 0: /* 0:11.0 SATA */ + sb700_cimx_config(sb_config); + if (dev->enabled) { + sb_config->SataController = CIMX_OPTION_ENABLED; + if (1 == sb_chip->boot_switch_sata_ide) + sb_config->SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary. + else if (0 == sb_chip->boot_switch_sata_ide) + sb_config->SataIdeCombMdPriSecOpt = 1; //1 -IDE as secondary. + } else { + sb_config->SataController = CIMX_OPTION_DISABLED; + } + break; + + case (0x12 << 3) | 0: /* 0:12:0 OHCI-USB1 */ + case (0x12 << 3) | 2: /* 0:12:2 EHCI-USB1 */ + case (0x13 << 3) | 0: /* 0:13:0 OHCI-USB2 */ + case (0x13 << 3) | 2: /* 0:13:2 EHCI-USB2 */ + break; + + case (0x14 << 3) | 0: /* 0:14:0 SMBUS */ + { +#if 1 + u32 ioapic_base; + printk(BIOS_DEBUG, "sm_init().\n"); + ioapic_base = IO_APIC_ADDR; + clear_ioapic(ioapic_base); + /* I/O APIC IDs are normally limited to 4-bits. Enforce this limit. */ +#if (CONFIG_APIC_ID_OFFSET == 0 && CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS >= 1) + /* Assign the ioapic ID the next available number after the processor core local APIC IDs */ + setup_ioapic(ioapic_base, CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS); +#elif (CONFIG_APIC_ID_OFFSET > 0) + /* Assign the ioapic ID the value 0. Processor APIC IDs follow. */ + setup_ioapic(ioapic_base, 0); +#else +#error "The processor APIC IDs must be lifted to make room for the I/O APIC ID" +#endif +#endif + } + break; + + case (0x14 << 3) | 1: /* 0:14:1 IDE */ + break; + + case (0x14 << 3) | 2: /* 0:14:2 HDA */ + if (dev->enabled) { + if (AZALIA_DISABLE == sb_config->AzaliaController) { + sb_config->AzaliaController = AZALIA_AUTO; + } + printk(BIOS_DEBUG, "hda enabled\n"); + } else { + sb_config->AzaliaController = AZALIA_DISABLE; + printk(BIOS_DEBUG, "hda disabled\n"); + } + break; + + + case (0x14 << 3) | 3: /* 0:14:3 LPC */ + break; + + case (0x14 << 3) | 4: /* 0:14:4 PCI */ + break; + + case (0x14 << 3) | 5: /* 0:14:5 OHCI-USB4 */ + /* call CIMX entry after last device enable */ + sb_Before_Pci_Init(); + break; + + default: + break; + } +} + +struct chip_operations southbridge_amd_cimx_sb700_ops = { + CHIP_NAME("ATI SB700") + .enable_dev = sb700_enable, +}; + +/** + * @brief SB Cimx entry point sbBeforePciInit wrapper + */ +void sb_Before_Pci_Init(void) +{ + printk(BIOS_DEBUG, "sb700 %s Start\n", __func__); + /* TODO: The sb700 cimx dispatcher not work yet, calling cimx API directly */ + //sb_config->StdHeader.Func = SB_BEFORE_PCI_INIT; + //AmdSbDispatcher(sb_config); + sbBeforePciInit(sb_config); + printk(BIOS_DEBUG, "sb700 %s End\n", __func__); +} + +void sb_After_Pci_Init(void) +{ + printk(BIOS_DEBUG, "sb700 %s Start\n", __func__); + /* TODO: The sb700 cimx dispatcher not work yet, calling cimx API directly */ + //sb_config->StdHeader.Func = SB_AFTER_PCI_INIT; + //AmdSbDispatcher(sb_config); + sbAfterPciInit(sb_config); + printk(BIOS_DEBUG, "sb700 %s End\n", __func__); +} + +void sb_Late_Post(void) +{ + printk(BIOS_DEBUG, "sb700 %s Start\n", __func__); + /* TODO: The sb700 cimx dispatcher not work yet, calling cimx API directly */ + //sb_config->StdHeader.Func = SB_LATE_POST_INIT; + //AmdSbDispatcher(sb_config); + sbLatePost(sb_config); + printk(BIOS_DEBUG, "sb700 %s End\n", __func__); +} diff --git a/src/southbridge/amd/cimx/sb700/lpc.c b/src/southbridge/amd/cimx/sb700/lpc.c new file mode 100644 index 0000000..5d551cc --- /dev/null +++ b/src/southbridge/amd/cimx/sb700/lpc.c @@ -0,0 +1,195 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/pci.h> +#include "lpc.h" +#include <bitops.h> +#include <arch/io.h> +#include <console/console.h> /* printk */ +#include <cbmem.h> + +#define BIOSRAM_INDEX 0xcd4 +#define BIOSRAM_DATA 0xcd5 + +void set_cbmem_toc(struct cbmem_entry *toc) +{ + u32 dword = (u32) toc; + int nvram_pos = 0xfc, i; + for (i = 0; i<4; i++) { + outb(nvram_pos, BIOSRAM_INDEX); + outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA); + nvram_pos++; + } +} + +void lpc_read_resources(device_t dev) +{ + struct resource *res; + + printk(BIOS_DEBUG, "SB700 - Lpc.c - lpc_read_resources - Start.\n"); + /* Get the normal pci resources of this device */ + pci_dev_read_resources(dev); /* We got one for APIC, or one more for TRAP */ + + pci_get_resource(dev, SPIROM_BASE_ADDRESS); /* SPI ROM base address */ + + /* Add an extra subtractive resource for both memory and I/O. */ + res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); + res->base = 0; + res->size = 0x1000; + res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); + res->base = 0xff800000; + res->size = 0x00800000; /* 8 MB for flash */ + res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, 3); /* IOAPIC */ + res->base = 0xfec00000; + res->size = 0x00001000; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + compact_resources(dev); + printk(BIOS_DEBUG, "SB700 - Lpc.c - lpc_read_resources - End.\n"); +} + +void lpc_set_resources(struct device *dev) +{ + struct resource *res; + + printk(BIOS_DEBUG, "SB700 - Lpc.c - lpc_set_resources - Start.\n"); + pci_dev_set_resources(dev); + + /* Specical case. SPI Base Address. The SpiRomEnable should be set. */ + res = find_resource(dev, SPIROM_BASE_ADDRESS); + pci_write_config32(dev, SPIROM_BASE_ADDRESS, res->base | 1 << 1); + printk(BIOS_DEBUG, "SB700 - Lpc.c - lpc_set_resources - End.\n"); +} + +/** + * @brief Enable resources for children devices + * + * @param dev the device whos children's resources are to be enabled + * + */ +void lpc_enable_childrens_resources(device_t dev) +{ + struct bus *link; + u32 reg, reg_x; + int var_num = 0; + u16 reg_var[3]; + + printk(BIOS_DEBUG, "SB700 - Lpc.c - lpc_enable_childrens_resources - Start.\n"); + reg = pci_read_config32(dev, 0x44); + reg_x = pci_read_config32(dev, 0x48); + + for (link = dev->link_list; link; link = link->next) { + device_t child; + for (child = link->children; child; + child = child->sibling) { + if (child->enabled + && (child->path.type == DEVICE_PATH_PNP)) { + struct resource *res; + for (res = child->resource_list; res; res = res->next) { + u32 base, end; /* don't need long long */ + if (!(res->flags & IORESOURCE_IO)) + continue; + base = res->base; + end = resource_end(res); +/* + printk(BIOS_DEBUG, "sb700 lpc decode:%s, base=0x%08x, end=0x%08x\n", + dev_path(child), base, end); +*/ + switch (base) { + case 0x60: /* KB */ + case 0x64: /* MS */ + reg |= (1 << 29); + break; + case 0x3f8: /* COM1 */ + reg |= (1 << 6); + break; + case 0x2f8: /* COM2 */ + reg |= (1 << 7); + break; + case 0x378: /* Parallal 1 */ + reg |= (1 << 0); + break; + case 0x3f0: /* FD0 */ + reg |= (1 << 26); + break; + case 0x220: /* Aduio 0 */ + reg |= (1 << 8); + break; + case 0x300: /* Midi 0 */ + reg |= (1 << 18); + break; + case 0x400: + reg_x |= (1 << 16); + break; + case 0x480: + reg_x |= (1 << 17); + break; + case 0x500: + reg_x |= (1 << 18); + break; + case 0x580: + reg_x |= (1 << 19); + break; + case 0x4700: + reg_x |= (1 << 22); + break; + case 0xfd60: + reg_x |= (1 << 23); + break; + default: + if (var_num >= 3) + continue; /* only 3 var ; compact them ? */ + switch (var_num) { + case 0: + reg_x |= (1 << 2); + break; + case 1: + reg_x |= (1 << 24); + break; + case 2: + reg_x |= (1 << 25); + break; + } + reg_var[var_num++] = + base & 0xffff; + } + } + } + } + } + pci_write_config32(dev, 0x44, reg); + pci_write_config32(dev, 0x48, reg_x); + /* Set WideIO for as many IOs found (fall through is on purpose) */ + switch (var_num) { + case 2: + pci_write_config16(dev, 0x90, reg_var[2]); + case 1: + pci_write_config16(dev, 0x66, reg_var[1]); + case 0: + //pci_write_config16(dev, 0x64, reg_var[0]); //cause filo can not find sata + break; + } + printk(BIOS_DEBUG, "SB700 - Lpc.c - lpc_enable_childrens_resources - End.\n"); +} diff --git a/src/southbridge/amd/cimx/sb700/lpc.h b/src/southbridge/amd/cimx/sb700/lpc.h new file mode 100644 index 0000000..edb13f8 --- /dev/null +++ b/src/southbridge/amd/cimx/sb700/lpc.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _SB700_LPC_H_ +#define _SB700_LPC_H_ + + +#define SPIROM_BASE_ADDRESS 0xA0 /* SPI ROM base address */ + +void lpc_read_resources(device_t dev); +void lpc_set_resources(device_t dev); +void lpc_enable_childrens_resources(device_t dev); + +#endif diff --git a/src/southbridge/amd/cimx/sb700/sb_cimx.h b/src/southbridge/amd/cimx/sb700/sb_cimx.h new file mode 100644 index 0000000..84fe4d0 --- /dev/null +++ b/src/southbridge/amd/cimx/sb700/sb_cimx.h @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#ifndef _CIMX_H_ +#define _CIMX_H_ + +#define PM_INDEX 0xcd6 +#define PM_DATA 0xcd7 + +#define REV_SB700_A11 0x11 +#define REV_SB700_A12 0x12 + + +/** + * AMD South Bridge CIMx entry point wrapper + */ +void sb_Poweron_Init(void); +void sb_Before_Pci_Init(void); +void sb_After_Pci_Init(void); +void sb_Mid_Post_Init(void); +void sb_Late_Post(void); + + +#if CONFIG_RAMINIT_SYSINFO == 1 +/** + * @brief Get SouthBridge device number, called by finalize_node_setup() + * @param[in] bus target bus number + * @return southbridge device number + */ +u32 get_sbdn(u32 bus); +#endif +#endif diff --git a/src/southbridge/amd/cimx/sb700/smbus.c b/src/southbridge/amd/cimx/sb700/smbus.c new file mode 100644 index 0000000..58dd012 --- /dev/null +++ b/src/southbridge/amd/cimx/sb700/smbus.c @@ -0,0 +1,270 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include <arch/io.h> +#include "smbus.h" +#include <console/console.h> /* printk */ + +static inline void smbus_delay(void) +{ + outb(inb(0x80), 0x80); +} + +static int smbus_wait_until_ready(u32 smbus_io_base) +{ + u32 loops; + + loops = SMBUS_TIMEOUT; + do { + u8 val; + val = inb(smbus_io_base + SMBHSTSTAT); + val &= 0x1f; + if (val == 0) { /* ready now */ + return 0; + } + outb(val, smbus_io_base + SMBHSTSTAT); + } while (--loops); + + return -2; /* time out */ +} + +static int smbus_wait_until_done(u32 smbus_io_base) +{ + u32 loops; + + loops = SMBUS_TIMEOUT; + do { + u8 val; + + val = inb(smbus_io_base + SMBHSTSTAT); + val &= 0x1f; /* mask off reserved bits */ + if (val & 0x1c) { + return -5; /* error */ + } + if (val == 0x02) { + outb(val, smbus_io_base + SMBHSTSTAT); /* clear status */ + return 0; + } + } while (--loops); + + return -3; /* timeout */ +} + +int do_smbus_recv_byte(u32 smbus_io_base, u32 device) +{ + u8 byte; + + if (smbus_wait_until_ready(smbus_io_base) < 0) { + printk(BIOS_SPEW, "SB700 - Smbus.c - do_smbus_recv_byte - smbus no ready.\n"); + return -2; /* not ready */ + } + + printk(BIOS_SPEW, "SB700 - Smbus.c - do_smbus_recv_byte - Start.\n"); + /* set the device I'm talking too */ + outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR); + + byte = inb(smbus_io_base + SMBHSTCTRL); + byte &= 0xe3; /* Clear [4:2] */ + byte |= (1 << 2) | (1 << 6); /* Byte data read/write command, start the command */ + outb(byte, smbus_io_base + SMBHSTCTRL); + + /* poll for transaction completion */ + if (smbus_wait_until_done(smbus_io_base) < 0) { + return -3; /* timeout or error */ + } + + /* read results of transaction */ + byte = inb(smbus_io_base + SMBHSTCMD); + + printk(BIOS_SPEW, "SB700 - Smbus.c - do_smbus_recv_byte - End.\n"); + return byte; +} + +int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val) +{ + u8 byte; + + if (smbus_wait_until_ready(smbus_io_base) < 0) { + printk(BIOS_SPEW, "SB700 - Smbus.c - do_smbus_send_byte - smbus no ready.\n"); + return -2; /* not ready */ + } + + printk(BIOS_SPEW, "SB700 - Smbus.c - do_smbus_send_byte - Start.\n"); + /* set the command... */ + outb(val, smbus_io_base + SMBHSTCMD); + + /* set the device I'm talking too */ + outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR); + + byte = inb(smbus_io_base + SMBHSTCTRL); + byte &= 0xe3; /* Clear [4:2] */ + byte |= (1 << 2) | (1 << 6); /* Byte data read/write command, start the command */ + outb(byte, smbus_io_base + SMBHSTCTRL); + + /* poll for transaction completion */ + if (smbus_wait_until_done(smbus_io_base) < 0) { + return -3; /* timeout or error */ + } + + printk(BIOS_SPEW, "SB700 - Smbus.c - do_smbus_send_byte - End.\n"); + return 0; +} + +int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address) +{ + u8 byte; + + if (smbus_wait_until_ready(smbus_io_base) < 0) { + printk(BIOS_SPEW, "SB700 - Smbus.c - do_smbus_read_byte - smbus no ready.\n"); + return -2; /* not ready */ + } + + printk(BIOS_SPEW, "SB700 - Smbus.c - do_smbus_read_byte - Start.\n"); + /* set the command/address... */ + outb(address & 0xff, smbus_io_base + SMBHSTCMD); + + /* set the device I'm talking too */ + outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR); + + byte = inb(smbus_io_base + SMBHSTCTRL); + byte &= 0xe3; /* Clear [4:2] */ + byte |= (1 << 3) | (1 << 6); /* Byte data read/write command, start the command */ + outb(byte, smbus_io_base + SMBHSTCTRL); + + /* poll for transaction completion */ + if (smbus_wait_until_done(smbus_io_base) < 0) { + return -3; /* timeout or error */ + } + + /* read results of transaction */ + byte = inb(smbus_io_base + SMBHSTDAT0); + + printk(BIOS_SPEW, "SB700 - Smbus.c - do_smbus_read_byte - End.\n"); + return byte; +} + +int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val) +{ + u8 byte; + + if (smbus_wait_until_ready(smbus_io_base) < 0) { + printk(BIOS_SPEW, "SB700 - Smbus.c - do_smbus_write_byte - smbus no ready.\n"); + return -2; /* not ready */ + } + + printk(BIOS_SPEW, "SB700 - Smbus.c - do_smbus_write_byte - Start.\n"); + /* set the command/address... */ + outb(address & 0xff, smbus_io_base + SMBHSTCMD); + + /* set the device I'm talking too */ + outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR); + + /* output value */ + outb(val, smbus_io_base + SMBHSTDAT0); + + byte = inb(smbus_io_base + SMBHSTCTRL); + byte &= 0xe3; /* Clear [4:2] */ + byte |= (1 << 3) | (1 << 6); /* Byte data read/write command, start the command */ + outb(byte, smbus_io_base + SMBHSTCTRL); + + /* poll for transaction completion */ + if (smbus_wait_until_done(smbus_io_base) < 0) { + return -3; /* timeout or error */ + } + + printk(BIOS_SPEW, "SB700 - Smbus.c - do_smbus_write_byte - End.\n"); + return 0; +} + +void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val) +{ + u32 tmp; + + printk(BIOS_SPEW, "SB700 - Smbus.c - alink_ab_indx - Start.\n"); + outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX); + tmp = inl(AB_DATA); + /* rpr 4.2 + * For certain revisions of the chip, the ABCFG registers, + * with an address of 0x100NN (where 'N' is any hexadecimal + * number), require an extra programming step.*/ + outl(0, AB_INDX); + + tmp &= ~mask; + tmp |= val; + + /* printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<29 | reg_addr); */ + outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX); /* probably we dont have to do it again. */ + outl(tmp, AB_DATA); + outl(0, AB_INDX); + printk(BIOS_SPEW, "SB700 - Smbus.c - alink_ab_indx - End.\n"); +} + +void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val) +{ + u32 tmp; + + printk(BIOS_SPEW, "SB700 - Smbus.c - alink_rc_indx - Start.\n"); + outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX); + tmp = inl(AB_DATA); + /* rpr 4.2 + * For certain revisions of the chip, the ABCFG registers, + * with an address of 0x100NN (where 'N' is any hexadecimal + * number), require an extra programming step.*/ + outl(0, AB_INDX); + + tmp &= ~mask; + tmp |= val; + + //printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<29 | (port&3) << 24 | reg_addr); + outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX); /* probably we dont have to do it again. */ + outl(tmp, AB_DATA); + outl(0, AB_INDX); + printk(BIOS_SPEW, "SB700 - Smbus.c - alink_rc_indx - End.\n"); +} + +/* space = 0: AX_INDXC, AX_DATAC + * space = 1: AX_INDXP, AX_DATAP + */ +void alink_ax_indx(u32 space /*c or p? */ , u32 axindc, u32 mask, u32 val) +{ + u32 tmp; + + printk(BIOS_SPEW, "SB700 - Smbus.c - alink_ax_indx - Start.\n"); + /* read axindc to tmp */ + outl(space << 29 | space << 3 | 0x30, AB_INDX); + outl(axindc, AB_DATA); + outl(0, AB_INDX); + outl(space << 29 | space << 3 | 0x34, AB_INDX); + tmp = inl(AB_DATA); + outl(0, AB_INDX); + + tmp &= ~mask; + tmp |= val; + + /* write tmp */ + outl(space << 29 | space << 3 | 0x30, AB_INDX); + outl(axindc, AB_DATA); + outl(0, AB_INDX); + outl(space << 29 | space << 3 | 0x34, AB_INDX); + outl(tmp, AB_DATA); + outl(0, AB_INDX); + printk(BIOS_SPEW, "SB700 - Smbus.c - alink_ax_indx - End.\n"); +} + diff --git a/src/southbridge/amd/cimx/sb700/smbus.h b/src/southbridge/amd/cimx/sb700/smbus.h new file mode 100644 index 0000000..10e0874 --- /dev/null +++ b/src/southbridge/amd/cimx/sb700/smbus.h @@ -0,0 +1,82 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _SB700_SMBUS_H_ +#define _SB700_SMBUS_H_ + +//#include <stdint.h> +#include <Platform.h> /* SMBUS0_BASE_ADDRESS */ +#ifndef SMBUS0_BASE_ADDRESS +#error SMBUS0_BASE_ADDRESS not define +#endif +#define SMBUS_IO_BASE SMBUS0_BASE_ADDRESS + +#define SMBHSTSTAT 0x0 +#define SMBSLVSTAT 0x1 +#define SMBHSTCTRL 0x2 +#define SMBHSTCMD 0x3 +#define SMBHSTADDR 0x4 +#define SMBHSTDAT0 0x5 +#define SMBHSTDAT1 0x6 +#define SMBHSTBLKDAT 0x7 + +#define SMBSLVCTRL 0x8 +#define SMBSLVCMD_SHADOW 0x9 +#define SMBSLVEVT 0xa +#define SMBSLVDAT 0xc + +/*//SB00.H +#define AX_INDXC 0 +#define AX_INDXP 2 +#define AXCFG 4 +#define ABCFG 6 +#define RC_INDXC 1 +#define RC_INDXP 3 +*/ + +#define AB_INDX 0xCD8 +#define AB_DATA (AB_INDX+4) + +/* Between 1-10 seconds, We should never timeout normally + * Longer than this is just painful when a timeout condition occurs. + */ +#define SMBUS_TIMEOUT (100*1000*10) + +#define abcfg_reg(reg, mask, val) \ + alink_ab_indx((ABCFG), (reg), (mask), (val)) +#define axcfg_reg(reg, mask, val) \ + alink_ab_indx((AXCFG), (reg), (mask), (val)) +#define axindxc_reg(reg, mask, val) \ + alink_ax_indx((AX_INDXC), (reg), (mask), (val)) +#define axindxp_reg(reg, mask, val) \ + alink_ax_indx((AX_INDXP), (reg), (mask), (val)) +#define rcindxc_reg(reg, port, mask, val) \ + alink_rc_indx((RC_INDXC), (reg), (port), (mask), (val)) +#define rcindxp_reg(reg, port, mask, val) \ + alink_rc_indx((RC_INDXP), (reg), (port), (mask), (val)) + +int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address); +int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val); +int do_smbus_recv_byte(u32 smbus_io_base, u32 device); +int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val); +void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val); +void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val); +void alink_ax_indx(u32 space /*c or p? */ , u32 axindc, u32 mask, u32 val); + +#endif //_SB700_SMBUS_H_

1 0

Patch set updated for coreboot: 3203aa0 SIO: Add smsc/sch4037 superio support
by Kerry Sheh Jan. 31, 2012

Jan. 31, 2012

Kerry Sheh (shekairui(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/562 -gerrit commit 3203aa050b753dd1bf931fba462369cada510501 Author: Kerry Sheh <shekairui(a)gmail.com> Date: Tue Jan 31 20:42:20 2012 +0800 SIO: Add smsc/sch4037 superio support Change-Id: I3b113a27541b8efd096f3bd44e6621344ec916a5 Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> --- src/superio/smsc/Kconfig | 3 + src/superio/smsc/Makefile.inc | 2 + src/superio/smsc/sch4037/Makefile.inc | 20 +++ src/superio/smsc/sch4037/chip.h | 34 ++++ src/superio/smsc/sch4037/sch4037.h | 227 +++++++++++++++++++++++++ src/superio/smsc/sch4037/sch4037_early_init.c | 71 ++++++++ src/superio/smsc/sch4037/superio.c | 123 +++++++++++++ 7 files changed, 480 insertions(+), 0 deletions(-) diff --git a/src/superio/smsc/Kconfig b/src/superio/smsc/Kconfig index 7378d18..ddd5b96 100644 --- a/src/superio/smsc/Kconfig +++ b/src/superio/smsc/Kconfig @@ -2,6 +2,7 @@ ## This file is part of the coreboot project. ## ## Copyright (C) 2009 Ronald G. Minnich +## Copyright (C) 2012 Advanced Micro Devices, Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -39,3 +40,5 @@ config SUPERIO_SMSC_KBC1100 bool config SUPERIO_SMSC_SMSCSUPERIO bool +config SUPERIO_SMSC_SCH4037 + bool diff --git a/src/superio/smsc/Makefile.inc b/src/superio/smsc/Makefile.inc index 68d4d56..bfdc68e 100644 --- a/src/superio/smsc/Makefile.inc +++ b/src/superio/smsc/Makefile.inc @@ -2,6 +2,7 @@ ## This file is part of the coreboot project. ## ## Copyright (C) 2009 Ronald G. Minnich +## Copyright (C) 2012 Advanced Micro Devices, Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -28,3 +29,4 @@ subdirs-y += lpc47n227 subdirs-y += sio10n268 subdirs-y += kbc1100 subdirs-y += smscsuperio +subdirs-y += sch4037 diff --git a/src/superio/smsc/sch4037/Makefile.inc b/src/superio/smsc/sch4037/Makefile.inc new file mode 100644 index 0000000..8f36f2a --- /dev/null +++ b/src/superio/smsc/sch4037/Makefile.inc @@ -0,0 +1,20 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +ramstage-$(CONFIG_SUPERIO_SMSC_SCH4037) += superio.c diff --git a/src/superio/smsc/sch4037/chip.h b/src/superio/smsc/sch4037/chip.h new file mode 100644 index 0000000..3223750 --- /dev/null +++ b/src/superio/smsc/sch4037/chip.h @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_SCH_4037_CHIP_H +#define SUPERIO_SCH_4037_CHIP_H + +#include <pc80/keyboard.h> +#include <uart8250.h> + +struct chip_operations; +extern struct chip_operations superio_smsc_sch4037_ops; + +struct superio_smsc_sch4037_config { + + struct pc_keyboard keyboard; +}; + +#endif //SUPERIO_SCH_4037_CHIP_H \ No newline at end of file diff --git a/src/superio/smsc/sch4037/sch4037.h b/src/superio/smsc/sch4037/sch4037.h new file mode 100644 index 0000000..f429723 --- /dev/null +++ b/src/superio/smsc/sch4037/sch4037.h @@ -0,0 +1,227 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_SCH_4037_H +#define SUPERIO_SCH_4037_H + +/* BITS Define */ +#ifndef BIT0 +#define BIT0 0x0000000000000001ull +#endif +#ifndef BIT1 +#define BIT1 0x0000000000000002ull +#endif +#ifndef BIT2 +#define BIT2 0x0000000000000004ull +#endif +#ifndef BIT3 +#define BIT3 0x0000000000000008ull +#endif +#ifndef BIT4 +#define BIT4 0x0000000000000010ull +#endif +#ifndef BIT5 +#define BIT5 0x0000000000000020ull +#endif +#ifndef BIT6 +#define BIT6 0x0000000000000040ull +#endif +#ifndef BIT7 +#define BIT7 0x0000000000000080ull +#endif +#ifndef BIT8 +#define BIT8 0x0000000000000100ull +#endif +#ifndef BIT9 +#define BIT9 0x0000000000000200ull +#endif +#ifndef BIT10 +#define BIT10 0x0000000000000400ull +#endif +#ifndef BIT11 +#define BIT11 0x0000000000000800ull +#endif +#ifndef BIT12 +#define BIT12 0x0000000000001000ull +#endif +#ifndef BIT13 +#define BIT13 0x0000000000002000ull +#endif +#ifndef BIT14 +#define BIT14 0x0000000000004000ull +#endif +#ifndef BIT15 +#define BIT15 0x0000000000008000ull +#endif +#ifndef BIT16 +#define BIT16 0x0000000000010000ull +#endif +#ifndef BIT17 +#define BIT17 0x0000000000020000ull +#endif +#ifndef BIT18 +#define BIT18 0x0000000000040000ull +#endif +#ifndef BIT19 +#define BIT19 0x0000000000080000ull +#endif +#ifndef BIT20 +#define BIT20 0x0000000000100000ull +#endif +#ifndef BIT21 +#define BIT21 0x0000000000200000ull +#endif +#ifndef BIT22 +#define BIT22 0x0000000000400000ull +#endif +#ifndef BIT23 +#define BIT23 0x0000000000800000ull +#endif +#ifndef BIT24 +#define BIT24 0x0000000001000000ull +#endif +#ifndef BIT25 +#define BIT25 0x0000000002000000ull +#endif +#ifndef BIT26 +#define BIT26 0x0000000004000000ull +#endif +#ifndef BIT27 +#define BIT27 0x0000000008000000ull +#endif +#ifndef BIT28 +#define BIT28 0x0000000010000000ull +#endif +#ifndef BIT29 +#define BIT29 0x0000000020000000ull +#endif +#ifndef BIT30 +#define BIT30 0x0000000040000000ull +#endif +#ifndef BIT31 +#define BIT31 0x0000000080000000ull +#endif +#ifndef BIT32 +#define BIT32 0x0000000100000000ull +#endif +#ifndef BIT33 +#define BIT33 0x0000000200000000ull +#endif +#ifndef BIT34 +#define BIT34 0x0000000400000000ull +#endif +#ifndef BIT35 +#define BIT35 0x0000000800000000ull +#endif +#ifndef BIT36 +#define BIT36 0x0000001000000000ull +#endif +#ifndef BIT37 +#define BIT37 0x0000002000000000ull +#endif +#ifndef BIT38 +#define BIT38 0x0000004000000000ull +#endif +#ifndef BIT39 +#define BIT39 0x0000008000000000ull +#endif +#ifndef BIT40 +#define BIT40 0x0000010000000000ull +#endif +#ifndef BIT41 +#define BIT41 0x0000020000000000ull +#endif +#ifndef BIT42 +#define BIT42 0x0000040000000000ull +#endif +#ifndef BIT43 +#define BIT43 0x0000080000000000ull +#endif +#ifndef BIT44 +#define BIT44 0x0000100000000000ull +#endif +#ifndef BIT45 +#define BIT45 0x0000200000000000ull +#endif +#ifndef BIT46 +#define BIT46 0x0000400000000000ull +#endif +#ifndef BIT47 +#define BIT47 0x0000800000000000ull +#endif +#ifndef BIT48 +#define BIT48 0x0001000000000000ull +#endif +#ifndef BIT49 +#define BIT49 0x0002000000000000ull +#endif +#ifndef BIT50 +#define BIT50 0x0004000000000000ull +#endif +#ifndef BIT51 +#define BIT51 0x0008000000000000ull +#endif +#ifndef BIT52 +#define BIT52 0x0010000000000000ull +#endif +#ifndef BIT53 +#define BIT53 0x0020000000000000ull +#endif +#ifndef BIT54 +#define BIT54 0x0040000000000000ull +#endif +#ifndef BIT55 +#define BIT55 0x0080000000000000ull +#endif +#ifndef BIT56 +#define BIT56 0x0100000000000000ull +#endif +#ifndef BIT57 +#define BIT57 0x0200000000000000ull +#endif +#ifndef BIT58 +#define BIT58 0x0400000000000000ull +#endif +#ifndef BIT59 +#define BIT59 0x0800000000000000ull +#endif +#ifndef BIT60 +#define BIT60 0x1000000000000000ull +#endif +#ifndef BIT61 +#define BIT61 0x2000000000000000ull +#endif +#ifndef BIT62 +#define BIT62 0x4000000000000000ull +#endif +#ifndef BIT63 +#define BIT63 0x8000000000000000ull +#endif + +#define SCH4037_FDD 0 /* FDD */ +#define SCH4037_LPT 3 /* LPT */ +#define SMSCSUPERIO_SP1 4 /* Com1 */ +#define SMSCSUPERIO_SP2 5 /* Com2 */ +#define SCH4037_RTC 6 /* RTC */ +#define SCH4037_KBC 7 /* KBC */ +#define SCH4037_HWM 8 /* HWM */ +#define SCH4037_RUNTIME 0x0A /* Runtime */ +#define SCH4037_XBUS 0x0B /* X-BUS */ + +#endif //SUPERIO_SCH_4037_H diff --git a/src/superio/smsc/sch4037/sch4037_early_init.c b/src/superio/smsc/sch4037/sch4037_early_init.c new file mode 100644 index 0000000..1ff7aba --- /dev/null +++ b/src/superio/smsc/sch4037/sch4037_early_init.c @@ -0,0 +1,71 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Pre-RAM driver for the SMSC KBC1100 Super I/O chip */ + +#include <arch/romcc_io.h> +#include "sch4037.h" + +static inline void pnp_enter_conf_state(device_t dev) +{ + unsigned port = dev>>8; + outb(0x55, port); +} + +static void pnp_exit_conf_state(device_t dev) +{ + unsigned port = dev>>8; + outb(0xaa, port); +} + +static inline void sch4037_early_init(unsigned port) +{ + device_t dev; + + dev = PNP_DEV (port, SMSCSUPERIO_SP1); + pnp_enter_conf_state(dev); + + /*Auto power management*/ + pnp_write_config (dev, 0x22, BIT3+BIT4+BIT5 ); + pnp_write_config (dev, 0x23, 0 ); + + /* Enable SMSC UART 0 */ + dev = PNP_DEV (port, SMSCSUPERIO_SP1); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + + pnp_set_iobase(dev, PNP_IDX_IO0, CONFIG_TTYS0_BASE); + pnp_set_irq(dev, PNP_IDX_IRQ0, 0x4); + + /* Enabled High speed, disabled MIDI support. */ + pnp_write_config (dev, 0xF0, 0x02); + pnp_set_enable(dev, 1); + + /* Enable keyboard */ + dev = PNP_DEV (port, SCH4037_KBC); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_irq(dev, 0x70, 1); /* IRQ 1 */ + pnp_set_irq(dev, 0x72, 12); /* IRQ 12 */ + pnp_set_enable(dev, 1); + + pnp_exit_conf_state(dev); + +} + diff --git a/src/superio/smsc/sch4037/superio.c b/src/superio/smsc/sch4037/superio.c new file mode 100644 index 0000000..af4040f --- /dev/null +++ b/src/superio/smsc/sch4037/superio.c @@ -0,0 +1,123 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* RAM driver for the SMSC KBC1100 Super I/O chip */ + +#include <arch/io.h> +#include <device/device.h> +#include <device/pnp.h> +#include <console/console.h> +#include <device/smbus.h> +#include <string.h> +#include <bitops.h> +#include <uart8250.h> +#include <pc80/keyboard.h> +#include <stdlib.h> +#include "chip.h" +#include "sch4037.h" + +/* Forward declarations */ +static void enable_dev(device_t dev); +static void sch4037_pnp_set_resources(device_t dev); +static void sch4037_pnp_enable_resources(device_t dev); +static void sch4037_pnp_enable(device_t dev); +static void sch4037_init(device_t dev); + +static void pnp_enter_conf_state(device_t dev); +static void pnp_exit_conf_state(device_t dev); + +struct chip_operations superio_smsc_sch4037_ops = { + CHIP_NAME("SMSC SCH4037 Super I/O") + .enable_dev = enable_dev, +}; + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = sch4037_pnp_set_resources, + .enable_resources = sch4037_pnp_enable_resources, + .enable = sch4037_pnp_enable, + .init = sch4037_init, +}; + +static struct pnp_info pnp_dev_info[] = { + { &ops, SCH4037_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, }, +}; + +static void enable_dev(device_t dev) +{ + printk(BIOS_EMERG, "file '%s',line %d, %s()\n", __FILE__, __LINE__, __func__); + pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +static void sch4037_pnp_set_resources(device_t dev) +{ + pnp_enter_conf_state(dev); + pnp_set_resources(dev); + pnp_exit_conf_state(dev); +} + +static void sch4037_pnp_enable_resources(device_t dev) +{ + pnp_enter_conf_state(dev); + pnp_enable_resources(dev); + pnp_exit_conf_state(dev); +} + +static void sch4037_pnp_enable(device_t dev) +{ + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + + if(dev->enabled) { + pnp_set_enable(dev, 1); + } + else { + pnp_set_enable(dev, 0); + } + pnp_exit_conf_state(dev); +} + +static void sch4037_init(device_t dev) +{ + struct superio_smsc_sch4037_config *conf = dev->chip_info; + struct resource *res0, *res1; + + if (!dev->enabled) { + return; + } + + switch(dev->path.pnp.device) { + + case SCH4037_KBC: + res0 = find_resource(dev, PNP_IDX_IO0); + res1 = find_resource(dev, PNP_IDX_IO1); + pc_keyboard_init(&conf->keyboard); + break; + } +} + +static void pnp_enter_conf_state(device_t dev) +{ + outb(0x55, dev->path.pnp.port); +} + +static void pnp_exit_conf_state(device_t dev) +{ + outb(0xaa, dev->path.pnp.port); +}

1 0

Patch set updated for coreboot: d8b2a08 SIO: Add smsc sio1036 superio
by Kerry Sheh Jan. 31, 2012

Jan. 31, 2012

Kerry Sheh (shekairui(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/563 -gerrit commit d8b2a084872d25a935c2dd57e9c567a17eda30c2 Author: Kerry Sheh <shekairui(a)gmail.com> Date: Tue Jan 31 20:42:22 2012 +0800 SIO: Add smsc sio1036 superio Change-Id: Iaf5519f304f9f16f7ff6e4b02060bb75a3605ce9 Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> --- src/superio/smsc/Kconfig | 2 + src/superio/smsc/Makefile.inc | 1 + src/superio/smsc/sio1036/Makefile.inc | 21 ++++ src/superio/smsc/sio1036/chip.h | 34 +++++++ src/superio/smsc/sio1036/sio1036.h | 25 +++++ src/superio/smsc/sio1036/sio1036_early_init.c | 101 ++++++++++++++++++++ src/superio/smsc/sio1036/superio.c | 122 +++++++++++++++++++++++++ 7 files changed, 306 insertions(+), 0 deletions(-) diff --git a/src/superio/smsc/Kconfig b/src/superio/smsc/Kconfig index ddd5b96..d4f07ec 100644 --- a/src/superio/smsc/Kconfig +++ b/src/superio/smsc/Kconfig @@ -40,5 +40,7 @@ config SUPERIO_SMSC_KBC1100 bool config SUPERIO_SMSC_SMSCSUPERIO bool +config SUPERIO_SMSC_SIO1036 + bool config SUPERIO_SMSC_SCH4037 bool diff --git a/src/superio/smsc/Makefile.inc b/src/superio/smsc/Makefile.inc index bfdc68e..d07afea 100644 --- a/src/superio/smsc/Makefile.inc +++ b/src/superio/smsc/Makefile.inc @@ -29,4 +29,5 @@ subdirs-y += lpc47n227 subdirs-y += sio10n268 subdirs-y += kbc1100 subdirs-y += smscsuperio +subdirs-y += sio1036 subdirs-y += sch4037 diff --git a/src/superio/smsc/sio1036/Makefile.inc b/src/superio/smsc/sio1036/Makefile.inc new file mode 100644 index 0000000..4e48899 --- /dev/null +++ b/src/superio/smsc/sio1036/Makefile.inc @@ -0,0 +1,21 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +ramstage-$(CONFIG_SUPERIO_SMSC_SIO1036) += superio.c + diff --git a/src/superio/smsc/sio1036/chip.h b/src/superio/smsc/sio1036/chip.h new file mode 100644 index 0000000..abed430 --- /dev/null +++ b/src/superio/smsc/sio1036/chip.h @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_SMSC_SIO1036_CHIP_H +#define SUPERIO_SMSC_SIO1036_CHIP_H + +#include <pc80/keyboard.h> +#include <uart8250.h> + +struct chip_operations; +extern struct chip_operations superio_smsc_kbc1100_ops; + +struct superio_smsc_sio1036_config { + struct uart8250 com1; +}; + +#endif //SUPERIO_SMSC_SIO1036_CHIP_H + diff --git a/src/superio/smsc/sio1036/sio1036.h b/src/superio/smsc/sio1036/sio1036.h new file mode 100644 index 0000000..cdd5a8b --- /dev/null +++ b/src/superio/smsc/sio1036/sio1036.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define SIO1036_SP1 0 /* Com1 */ + +#define UART_POWER_DOWN (1 << 7) +#define LPT_POWER_DOWN (1 << 2) +#define IR_OUPUT_MUX (1 << 6) + diff --git a/src/superio/smsc/sio1036/sio1036_early_init.c b/src/superio/smsc/sio1036/sio1036_early_init.c new file mode 100644 index 0000000..980e8c5 --- /dev/null +++ b/src/superio/smsc/sio1036/sio1036_early_init.c @@ -0,0 +1,101 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Pre-RAM driver for the SMSC KBC1100 Super I/O chip */ + +#include <arch/romcc_io.h> +#include "sio1036.h" + +#ifndef CONFIG_TTYS0_BASE +#define CONFIG_TTYS0_BASE 0x3F8 +#endif +static inline void sio1036_enter_conf_state(device_t dev) +{ + unsigned port = dev>>8; + outb(0x55, port); +} + +static inline void sio1036_exit_conf_state(device_t dev) +{ + unsigned port = dev>>8; + outb(0xaa, port); +} + +static u8 detect_sio1036_chip(unsigned port) +{ + device_t dev; + dev = PNP_DEV (port, SIO1036_SP1); + unsigned data; + sio1036_enter_conf_state (dev); + data = pnp_read_config (dev, 0x0D); + sio1036_exit_conf_state(dev); + /* detect smsc sio1036 chip */ + if (data == 0x82) { + /* Found SMSC SIO1036 chip */ + return 0; + } + else { + return -1; + }; +} + +static inline void sio1036_early_init(unsigned port) +{ + device_t dev; + dev = PNP_DEV (port, SIO1036_SP1); + + if (detect_sio1036_chip(port) != 0) { + /* Not found SMSC SIO1036 */ + return; + } + sio1036_enter_conf_state (dev); + + /* Enable SMSC UART 0 */ + /* Valid configuration cycle */ + pnp_write_config (dev, 0x00, 0x28); + + /* PP power/mode/cr lock */ + pnp_write_config (dev, 0x01, 0x98 | LPT_POWER_DOWN); + pnp_write_config (dev, 0x02, 0x08 | UART_POWER_DOWN); + + /*Auto power management*/ + pnp_write_config (dev, 0x07, 0x00 ); + + /*ECP FIFO threhod */ + pnp_write_config (dev, 0x0A, 0x00 | IR_OUPUT_MUX); + + /*GPIO direction register 2 */ + pnp_write_config (dev, 0x033, 0x00); + + /*UART Mode */ + pnp_write_config (dev, 0x0C, 0x02); + + /* GPIO polarity regisgter 2 */ + pnp_write_config (dev, 0x034, 0x00); + + /* Enable SMSC UART 0 */ + /*Set base io address */ + pnp_write_config (dev, 0x25, (u8)((u16)CONFIG_TTYS0_BASE >> 2)); + + /* Set UART IRQ onto 0x04 */ + pnp_write_config (dev, 0x28, 0x04); + + sio1036_exit_conf_state(dev); +} + diff --git a/src/superio/smsc/sio1036/superio.c b/src/superio/smsc/sio1036/superio.c new file mode 100644 index 0000000..2522d92 --- /dev/null +++ b/src/superio/smsc/sio1036/superio.c @@ -0,0 +1,122 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* RAM driver for the SMSC SIO1036 Super I/O chip */ + +#include <arch/io.h> +#include <device/device.h> +#include <device/pnp.h> +#include <console/console.h> +#include <device/smbus.h> +#include <string.h> +#include <bitops.h> +#include <uart8250.h> +#include <pc80/keyboard.h> +#include <stdlib.h> +#include "chip.h" +#include "sio1036.h" + +/* Forward declarations */ +static void enable_dev(device_t dev); +static void sio1036_pnp_set_resources(device_t dev); +static void sio1036_pnp_enable_resources(device_t dev); +static void sio1036_pnp_enable(device_t dev); +static void sio1036_init(device_t dev); + +static void pnp_enter_conf_state(device_t dev); +static void pnp_exit_conf_state(device_t dev); + +struct chip_operations superio_smsc_sio1036_ops = { + CHIP_NAME("SMSC SIO1036 Super I/O") + .enable_dev = enable_dev +}; + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = sio1036_pnp_set_resources, + .enable_resources = sio1036_pnp_enable_resources, + .enable = sio1036_pnp_enable, + .init = sio1036_init, +}; + +static struct pnp_info pnp_dev_info[] = { + {}, +}; + +static void enable_dev(device_t dev) +{ + pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +static void sio1036_pnp_set_resources(device_t dev) +{ + pnp_enter_conf_state(dev); + pnp_set_resources(dev); + pnp_exit_conf_state(dev); +} + +static void sio1036_pnp_enable_resources(device_t dev) +{ + pnp_enter_conf_state(dev); + pnp_enable_resources(dev); + pnp_exit_conf_state(dev); +} + +static void sio1036_pnp_enable(device_t dev) +{ + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + + if(dev->enabled) { + pnp_set_enable(dev, 1); + } + else { + pnp_set_enable(dev, 0); + } + pnp_exit_conf_state(dev); +} + +static void sio1036_init(device_t dev) +{ + struct superio_smsc_sio1036_config *conf = dev->chip_info; + struct resource *res0, *res1; + + + + if (!dev->enabled) { + return; + } + + switch(dev->path.pnp.device) { + + default: + break; + } +} + +static void pnp_enter_conf_state(device_t dev) +{ + outb(0x55, dev->path.pnp.port); +} + +static void pnp_exit_conf_state(device_t dev) +{ + outb(0xaa, dev->path.pnp.port); +} +

1 0

Patch set updated for coreboot: ad27b63 Mainboard: Add AMD dinar mainboard.
by Kerry Sheh Jan. 31, 2012

Jan. 31, 2012

Kerry Sheh (shekairui(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/564 -gerrit commit ad27b632926332521dfded95086f70bfe52723e4 Author: Kerry Sheh <shekairui(a)gmail.com> Date: Tue Jan 31 20:42:24 2012 +0800 Mainboard: Add AMD dinar mainboard. Dinar mainboard is an AMD evaluation board for Orochi Platform family15 model 00-0f processor. The mainbaord has dual G34 Socket, SR5690/SR5670/SR5650 and SP5100 chipsets. 16 cores InterLagos Opteron processor are supported. Windows 7 are verified on this platform. Change-Id: Id97d35e7bca9f0d422841e23f4b762f1ed101ea0 Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> --- src/mainboard/amd/Kconfig | 3 + src/mainboard/amd/dinar/BiosCallOuts.c | 563 ++++++ src/mainboard/amd/dinar/BiosCallOuts.h | 79 + src/mainboard/amd/dinar/Kconfig | 211 ++ src/mainboard/amd/dinar/Makefile.inc | 40 + src/mainboard/amd/dinar/Oem.h | 79 + src/mainboard/amd/dinar/OptionsIds.h | 64 + src/mainboard/amd/dinar/PlatformGnbPcie.c | 176 ++ src/mainboard/amd/dinar/PlatformGnbPcieComplex.h | 72 + src/mainboard/amd/dinar/acpi/cpstate.asl | 75 + src/mainboard/amd/dinar/acpi/ide.asl | 244 +++ src/mainboard/amd/dinar/acpi/routing.asl | 311 +++ src/mainboard/amd/dinar/acpi/sata.asl | 149 ++ src/mainboard/amd/dinar/acpi/usb.asl | 20 + src/mainboard/amd/dinar/acpi_tables.c | 320 +++ src/mainboard/amd/dinar/agesawrapper.c | 628 ++++++ src/mainboard/amd/dinar/agesawrapper.h | 329 +++ src/mainboard/amd/dinar/buildOpts.c | 483 +++++ src/mainboard/amd/dinar/chip.h | 23 + src/mainboard/amd/dinar/cmos.layout | 118 ++ src/mainboard/amd/dinar/devicetree.cb | 104 + src/mainboard/amd/dinar/dimmSpd.c | 333 +++ src/mainboard/amd/dinar/dsdt.asl | 1157 +++++++++++ src/mainboard/amd/dinar/fadt.c | 173 ++ src/mainboard/amd/dinar/get_bus_conf.c | 156 ++ src/mainboard/amd/dinar/gpio.c | 482 +++++ src/mainboard/amd/dinar/gpio.h | 2329 ++++++++++++++++++++++ src/mainboard/amd/dinar/irq_tables.c | 122 ++ src/mainboard/amd/dinar/mainboard.c | 138 ++ src/mainboard/amd/dinar/mptable.c | 196 ++ src/mainboard/amd/dinar/platform_cfg.h | 54 + src/mainboard/amd/dinar/rd890_cfg.c | 274 +++ src/mainboard/amd/dinar/rd890_cfg.h | 175 ++ src/mainboard/amd/dinar/reset.c | 66 + src/mainboard/amd/dinar/romstage.c | 157 ++ src/mainboard/amd/dinar/sb700_cfg.c | 142 ++ src/mainboard/amd/dinar/sb700_cfg.h | 237 +++ 37 files changed, 10282 insertions(+), 0 deletions(-) diff --git a/src/mainboard/amd/Kconfig b/src/mainboard/amd/Kconfig index 62ae584..c6de048 100644 --- a/src/mainboard/amd/Kconfig +++ b/src/mainboard/amd/Kconfig @@ -7,6 +7,8 @@ config BOARD_AMD_DB800 bool "DB800 (Salsa)" config BOARD_AMD_DBM690T bool "DBM690T (Herring)" +config BOARD_AMD_DINAR + bool "Dinar" config BOARD_AMD_MAHOGANY bool "Mahogany" config BOARD_AMD_MAHOGANY_FAM10 @@ -39,6 +41,7 @@ endchoice source "src/mainboard/amd/db800/Kconfig" source "src/mainboard/amd/dbm690t/Kconfig" +source "src/mainboard/amd/dinar/Kconfig" source "src/mainboard/amd/mahogany/Kconfig" source "src/mainboard/amd/mahogany_fam10/Kconfig" source "src/mainboard/amd/norwich/Kconfig" diff --git a/src/mainboard/amd/dinar/BiosCallOuts.c b/src/mainboard/amd/dinar/BiosCallOuts.c new file mode 100644 index 0000000..39e1d13 --- /dev/null +++ b/src/mainboard/amd/dinar/BiosCallOuts.c @@ -0,0 +1,563 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "agesawrapper.h" +#include "amdlib.h" +#include "BiosCallOuts.h" +#include "Ids.h" +#include "OptionsIds.h" +#include "heapManager.h" +#include "SB700.h" + +#ifndef SB_GPIO_REG01 +#define SB_GPIO_REG01 1 +#endif + +#ifndef SB_GPIO_REG24 +#define SB_GPIO_REG24 24 +#endif + +#ifndef SB_GPIO_REG27 +#define SB_GPIO_REG27 27 +#endif + +STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = +{ + {AGESA_ALLOCATE_BUFFER, + BiosAllocateBuffer + }, + + {AGESA_DEALLOCATE_BUFFER, + BiosDeallocateBuffer + }, + + {AGESA_DO_RESET, + BiosReset + }, + + {AGESA_LOCATE_BUFFER, + BiosLocateBuffer + }, + + {AGESA_READ_SPD, + BiosReadSpd + }, + + {AGESA_READ_SPD_RECOVERY, + BiosDefaultRet + }, + + {AGESA_RUNFUNC_ONAP, + BiosRunFuncOnAp + }, + + {AGESA_GNB_PCIE_SLOT_RESET, + BiosGnbPcieSlotReset + }, + + {AGESA_GET_IDS_INIT_DATA, + BiosGetIdsInitData + }, + + {AGESA_HOOKBEFORE_DRAM_INIT, + BiosHookBeforeDramInit + }, + + {AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, + BiosHookBeforeDramInitRecovery + }, + + {AGESA_HOOKBEFORE_DQS_TRAINING, + BiosHookBeforeDQSTraining + }, + + {AGESA_HOOKBEFORE_EXIT_SELF_REF, + BiosHookBeforeExitSelfRefresh + }, +}; + +AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + UINTN i; + AGESA_STATUS CalloutStatus; + UINTN CallOutCount = sizeof (BiosCallouts) / sizeof (BiosCallouts [0]); + + for (i = 0; i < CallOutCount; i++) + { + if (BiosCallouts[i].CalloutName == Func) + { + break; + } + } + + if(i >= CallOutCount) + { + return AGESA_UNSUPPORTED; + } + + CalloutStatus = BiosCallouts[i].CalloutPtr (Func, Data, ConfigPtr); + + return CalloutStatus; +} + + +CONST IDS_NV_ITEM IdsData[] = +{ + /*{ + AGESA_IDS_NV_MAIN_PLL_CON, + 0x1 + }, + { + AGESA_IDS_NV_MAIN_PLL_FID_EN, + 0x1 + }, + { + AGESA_IDS_NV_MAIN_PLL_FID, + 0x8 + }, + + { + AGESA_IDS_NV_CUSTOM_NB_PSTATE, + }, + { + AGESA_IDS_NV_CUSTOM_NB_P0_DIV_CTRL, + }, + { + AGESA_IDS_NV_CUSTOM_NB_P1_DIV_CTRL, + }, + { + AGESA_IDS_NV_FORCE_NB_PSTATE, + }, + */ + { + 0xFFFF, + 0xFFFF + } +}; + +#define NUM_IDS_ENTRIES (sizeof (IdsData) / sizeof (IDS_NV_ITEM)) + + +AGESA_STATUS BiosGetIdsInitData (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + UINTN i; + IDS_NV_ITEM *IdsPtr; + + IdsPtr = ((IDS_CALLOUT_STRUCT *) ConfigPtr)->IdsNvPtr; + + if (Data == IDS_CALLOUT_INIT) { + for (i = 0; i < NUM_IDS_ENTRIES; i++) { + IdsPtr[i].IdsNvValue = IdsData[i].IdsNvValue; + IdsPtr[i].IdsNvId = IdsData[i].IdsNvId; + } + } + return AGESA_SUCCESS; +} + + +AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + UINT32 AvailableHeapSize; + UINT8 *BiosHeapBaseAddr; + UINT32 CurrNodeOffset; + UINT32 PrevNodeOffset; + UINT32 FreedNodeOffset; + UINT32 BestFitNodeOffset; + UINT32 BestFitPrevNodeOffset; + UINT32 NextFreeOffset; + BIOS_BUFFER_NODE *CurrNodePtr; + BIOS_BUFFER_NODE *FreedNodePtr; + BIOS_BUFFER_NODE *BestFitNodePtr; + BIOS_BUFFER_NODE *BestFitPrevNodePtr; + BIOS_BUFFER_NODE *NextFreePtr; + BIOS_HEAP_MANAGER *BiosHeapBasePtr; + AGESA_BUFFER_PARAMS *AllocParams; + + AllocParams = ((AGESA_BUFFER_PARAMS *) ConfigPtr); + AllocParams->BufferPointer = NULL; + + AvailableHeapSize = BIOS_HEAP_SIZE - sizeof (BIOS_HEAP_MANAGER); + BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS; + BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS; + + if (BiosHeapBasePtr->StartOfAllocatedNodes == 0) { + /* First allocation */ + CurrNodeOffset = sizeof (BIOS_HEAP_MANAGER); + CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset); + CurrNodePtr->BufferHandle = AllocParams->BufferHandle; + CurrNodePtr->BufferSize = AllocParams->BufferLength; + CurrNodePtr->NextNodeOffset = 0; + AllocParams->BufferPointer = (UINT8 *) CurrNodePtr + sizeof (BIOS_BUFFER_NODE); + + /* Update the remaining free space */ + FreedNodeOffset = CurrNodeOffset + CurrNodePtr->BufferSize + sizeof (BIOS_BUFFER_NODE); + FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset); + FreedNodePtr->BufferSize = AvailableHeapSize - sizeof (BIOS_BUFFER_NODE) - CurrNodePtr->BufferSize; + FreedNodePtr->NextNodeOffset = 0; + + /* Update the offsets for Allocated and Freed nodes */ + BiosHeapBasePtr->StartOfAllocatedNodes = CurrNodeOffset; + BiosHeapBasePtr->StartOfFreedNodes = FreedNodeOffset; + } else { + /* Find out whether BufferHandle has been allocated on the heap. */ + /* If it has, return AGESA_BOUNDS_CHK */ + CurrNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; + CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset); + + while (CurrNodeOffset != 0) { + CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset); + if (CurrNodePtr->BufferHandle == AllocParams->BufferHandle) { + return AGESA_BOUNDS_CHK; + } + CurrNodeOffset = CurrNodePtr->NextNodeOffset; + /* If BufferHandle has not been allocated on the heap, CurrNodePtr here points + to the end of the allocated nodes list. + */ + + } + /* Find the node that best fits the requested buffer size */ + FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes; + PrevNodeOffset = FreedNodeOffset; + BestFitNodeOffset = 0; + BestFitPrevNodeOffset = 0; + while (FreedNodeOffset != 0) { + FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset); + if (FreedNodePtr->BufferSize >= (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE))) { + if (BestFitNodeOffset == 0) { + /* First node that fits the requested buffer size */ + BestFitNodeOffset = FreedNodeOffset; + BestFitPrevNodeOffset = PrevNodeOffset; + } else { + /* Find out whether current node is a better fit than the previous nodes */ + BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset); + if (BestFitNodePtr->BufferSize > FreedNodePtr->BufferSize) { + BestFitNodeOffset = FreedNodeOffset; + BestFitPrevNodeOffset = PrevNodeOffset; + } + } + } + PrevNodeOffset = FreedNodeOffset; + FreedNodeOffset = FreedNodePtr->NextNodeOffset; + } /* end of while loop */ + + + if (BestFitNodeOffset == 0) { + /* If we could not find a node that fits the requested buffer */ + /* size, return AGESA_BOUNDS_CHK */ + return AGESA_BOUNDS_CHK; + } else { + BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset); + BestFitPrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitPrevNodeOffset); + + /* If BestFitNode is larger than the requested buffer, fragment the node further */ + if (BestFitNodePtr->BufferSize > (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE))) { + NextFreeOffset = BestFitNodeOffset + AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE); + + NextFreePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextFreeOffset); + NextFreePtr->BufferSize = BestFitNodePtr->BufferSize - (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE)); + NextFreePtr->NextNodeOffset = BestFitNodePtr->NextNodeOffset; + } else { + /* Otherwise, next free node is NextNodeOffset of BestFitNode */ + NextFreeOffset = BestFitNodePtr->NextNodeOffset; + } + + /* If BestFitNode is the first buffer in the list, then update + StartOfFreedNodes to reflect the new free node + */ + if (BestFitNodeOffset == BiosHeapBasePtr->StartOfFreedNodes) { + BiosHeapBasePtr->StartOfFreedNodes = NextFreeOffset; + } else { + BestFitPrevNodePtr->NextNodeOffset = NextFreeOffset; + } + + /* Add BestFitNode to the list of Allocated nodes */ + CurrNodePtr->NextNodeOffset = BestFitNodeOffset; + BestFitNodePtr->BufferSize = AllocParams->BufferLength; + BestFitNodePtr->BufferHandle = AllocParams->BufferHandle; + BestFitNodePtr->NextNodeOffset = 0; + + /* Remove BestFitNode from list of Freed nodes */ + AllocParams->BufferPointer = (UINT8 *) BestFitNodePtr + sizeof (BIOS_BUFFER_NODE); + } + } + + return AGESA_SUCCESS; +} + +AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + + UINT8 *BiosHeapBaseAddr; + UINT32 AllocNodeOffset; + UINT32 PrevNodeOffset; + UINT32 NextNodeOffset; + UINT32 FreedNodeOffset; + UINT32 EndNodeOffset; + BIOS_BUFFER_NODE *AllocNodePtr; + BIOS_BUFFER_NODE *PrevNodePtr; + BIOS_BUFFER_NODE *FreedNodePtr; + BIOS_BUFFER_NODE *NextNodePtr; + BIOS_HEAP_MANAGER *BiosHeapBasePtr; + AGESA_BUFFER_PARAMS *AllocParams; + + BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS; + BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS; + + AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr; + + /* Find target node to deallocate in list of allocated nodes. + Return AGESA_BOUNDS_CHK if the BufferHandle is not found + */ + AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; + AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); + PrevNodeOffset = AllocNodeOffset; + + while (AllocNodePtr->BufferHandle != AllocParams->BufferHandle) { + if (AllocNodePtr->NextNodeOffset == 0) { + return AGESA_BOUNDS_CHK; + } + PrevNodeOffset = AllocNodeOffset; + AllocNodeOffset = AllocNodePtr->NextNodeOffset; + AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); + } + + /* Remove target node from list of allocated nodes */ + PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset); + PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset; + + /* Zero out the buffer, and clear the BufferHandle */ + LibAmdMemFill ((UINT8 *)AllocNodePtr + sizeof (BIOS_BUFFER_NODE), 0, AllocNodePtr->BufferSize, &(AllocParams->StdHeader)); + AllocNodePtr->BufferHandle = 0; + AllocNodePtr->BufferSize += sizeof (BIOS_BUFFER_NODE); + + /* Add deallocated node in order to the list of freed nodes */ + FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes; + FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset); + + EndNodeOffset = AllocNodeOffset + AllocNodePtr->BufferSize; + + if (AllocNodeOffset < FreedNodeOffset) { + /* Add to the start of the freed list */ + if (EndNodeOffset == FreedNodeOffset) { + /* If the freed node is adjacent to the first node in the list, concatenate both nodes */ + AllocNodePtr->BufferSize += FreedNodePtr->BufferSize; + AllocNodePtr->NextNodeOffset = FreedNodePtr->NextNodeOffset; + + /* Clear the BufferSize and NextNodeOffset of the previous first node */ + FreedNodePtr->BufferSize = 0; + FreedNodePtr->NextNodeOffset = 0; + + } else { + /* Otherwise, add freed node to the start of the list + Update NextNodeOffset and BufferSize to include the + size of BIOS_BUFFER_NODE + */ + AllocNodePtr->NextNodeOffset = FreedNodeOffset; + } + /* Update StartOfFreedNodes to the new first node */ + BiosHeapBasePtr->StartOfFreedNodes = AllocNodeOffset; + } else { + /* Traverse list of freed nodes to find where the deallocated node + should be place + */ + NextNodeOffset = FreedNodeOffset; + NextNodePtr = FreedNodePtr; + while (AllocNodeOffset > NextNodeOffset) { + PrevNodeOffset = NextNodeOffset; + if (NextNodePtr->NextNodeOffset == 0) { + break; + } + NextNodeOffset = NextNodePtr->NextNodeOffset; + NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset); + } + + /* If deallocated node is adjacent to the next node, + concatenate both nodes + */ + if (NextNodeOffset == EndNodeOffset) { + NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset); + AllocNodePtr->BufferSize += NextNodePtr->BufferSize; + AllocNodePtr->NextNodeOffset = NextNodePtr->NextNodeOffset; + + NextNodePtr->BufferSize = 0; + NextNodePtr->NextNodeOffset = 0; + } else { + /*AllocNodePtr->NextNodeOffset = FreedNodePtr->NextNodeOffset; */ + AllocNodePtr->NextNodeOffset = NextNodeOffset; + } + /* If deallocated node is adjacent to the previous node, + concatenate both nodes + */ + PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset); + EndNodeOffset = PrevNodeOffset + PrevNodePtr->BufferSize; + if (AllocNodeOffset == EndNodeOffset) { + PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset; + PrevNodePtr->BufferSize += AllocNodePtr->BufferSize; + + AllocNodePtr->BufferSize = 0; + AllocNodePtr->NextNodeOffset = 0; + } else { + PrevNodePtr->NextNodeOffset = AllocNodeOffset; + } + } + return AGESA_SUCCESS; +} + +AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + UINT32 AllocNodeOffset; + UINT8 *BiosHeapBaseAddr; + BIOS_BUFFER_NODE *AllocNodePtr; + BIOS_HEAP_MANAGER *BiosHeapBasePtr; + AGESA_BUFFER_PARAMS *AllocParams; + + AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr; + + BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS; + BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS; + + AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; + AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); + + while (AllocParams->BufferHandle != AllocNodePtr->BufferHandle) { + if (AllocNodePtr->NextNodeOffset == 0) { + AllocParams->BufferPointer = NULL; + AllocParams->BufferLength = 0; + return AGESA_BOUNDS_CHK; + } else { + AllocNodeOffset = AllocNodePtr->NextNodeOffset; + AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); + } + } + + AllocParams->BufferPointer = (UINT8 *) ((UINT8 *) AllocNodePtr + sizeof (BIOS_BUFFER_NODE)); + AllocParams->BufferLength = AllocNodePtr->BufferSize; + + return AGESA_SUCCESS; + +} + +AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + AGESA_STATUS Status; + + Status = agesawrapper_amdlaterunaptask (Data, ConfigPtr); + return Status; +} + +AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + AGESA_STATUS Status; + UINT8 Value; + UINTN ResetType; + AMD_CONFIG_PARAMS *StdHeader; + + ResetType = Data; + StdHeader = ConfigPtr; + + // + // Perform the RESET based upon the ResetType. In case of + // WARM_RESET_WHENVER and COLD_RESET_WHENEVER, the request will go to + // AmdResetManager. During the critical condition, where reset is required + // immediately, the reset will be invoked directly by writing 0x04 to port + // 0xCF9 (Reset Port). + // + switch (ResetType) { + case WARM_RESET_WHENEVER: + case COLD_RESET_WHENEVER: + break; + + case WARM_RESET_IMMEDIATELY: + case COLD_RESET_IMMEDIATELY: + Value = 0x06; + LibAmdIoWrite (AccessWidth8, 0xCf9, &Value, StdHeader); + break; + + default: + break; + } + + Status = 0; + return Status; +} + +AGESA_STATUS BiosReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + AGESA_STATUS Status; + Status = AmdMemoryReadSPD (Func, Data, (AGESA_READ_SPD_PARAMS *)ConfigPtr); + + return Status; +} + +AGESA_STATUS BiosDefaultRet (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + return AGESA_UNSUPPORTED; +} +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeDQSTraining (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + return AGESA_SUCCESS; +} +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + AGESA_STATUS Status; + UINTN FcnData; + MEM_DATA_STRUCT *MemData; + UINT32 AcpiMmioAddr; + UINT32 GpioMmioAddr; + UINT8 Data8; + UINT16 Data16; + UINT8 TempData8; + + FcnData = Data; + MemData = ConfigPtr; + + Status = AGESA_SUCCESS; + /* Get SB MMIO Base (AcpiMmioAddr) */ + WriteIo8 (0xCD6, 0x27); + Data8 = ReadIo8(0xCD7); + Data16 = Data8<<8; + WriteIo8 (0xCD6, 0x26); + Data8 = ReadIo8(0xCD7); + Data16 |= Data8; + AcpiMmioAddr = (UINT32)Data16 << 16; + GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; + Status = AGESA_SUCCESS; + return Status; +} + +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeDramInitRecovery (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + return AGESA_SUCCESS; +} +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + return AGESA_SUCCESS; +} +/* PCIE slot reset control */ +AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + AGESA_STATUS Status; + + Status = AGESA_SUCCESS; + return Status; +} diff --git a/src/mainboard/amd/dinar/BiosCallOuts.h b/src/mainboard/amd/dinar/BiosCallOuts.h new file mode 100644 index 0000000..22451aa --- /dev/null +++ b/src/mainboard/amd/dinar/BiosCallOuts.h @@ -0,0 +1,79 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _BIOS_CALLOUT_H_ +#define _BIOS_CALLOUT_H_ + +#include "Porting.h" +#include "AGESA.h" + +#define BIOS_HEAP_START_ADDRESS 0x00010000 +#define BIOS_HEAP_SIZE 0x20000 /* 64MB */ + +typedef struct _BIOS_HEAP_MANAGER { + //UINT32 AvailableSize; + UINT32 StartOfAllocatedNodes; + UINT32 StartOfFreedNodes; +} BIOS_HEAP_MANAGER; + +typedef struct _BIOS_BUFFER_NODE { + UINT32 BufferHandle; + UINT32 BufferSize; + UINT32 NextNodeOffset; +} BIOS_BUFFER_NODE; +/* + * CALLOUTS + */ +AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr); + +/* REQUIRED CALLOUTS + * AGESA ADVANCED CALLOUTS - CPU + */ +AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS BiosGetIdsInitData (UINT32 Func, UINT32 Data, VOID *ConfigPtr); + +/* AGESA ADVANCED CALLOUTS - MEMORY */ +AGESA_STATUS BiosReadSpd (UINT32 Func,UINT32 Data,VOID *ConfigPtr); + +/* BIOS DEFAULT RET */ +AGESA_STATUS BiosDefaultRet (UINT32 Func, UINT32 Data, VOID *ConfigPtr); + +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeDQSTraining (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeDramInitRecovery (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +/* PCIE slot reset control */ +AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +#define SB_GPIO_REG02 2 +#define SB_GPIO_REG09 9 +#define SB_GPIO_REG10 10 +#define SB_GPIO_REG15 15 +#define SB_GPIO_REG17 17 +#define SB_GPIO_REG21 21 +#define SB_GPIO_REG25 25 +#define SB_GPIO_REG28 28 +#endif //_BIOS_CALLOUT_H_ diff --git a/src/mainboard/amd/dinar/Kconfig b/src/mainboard/amd/dinar/Kconfig new file mode 100644 index 0000000..dcb4c52 --- /dev/null +++ b/src/mainboard/amd/dinar/Kconfig @@ -0,0 +1,211 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +if BOARD_AMD_DINAR + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_AMD_AGESA_FAMILY15 + select CPU_AMD_SOCKET_G34 + select NORTHBRIDGE_AMD_AGESA_FAMILY15_ROOT_COMPLEX + select NORTHBRIDGE_AMD_AGESA_FAMILY15 + select NORTHBRIDGE_AMD_CIMX_RD890 + select SOUTHBRIDGE_AMD_CIMX_SB700 + select SUPERIO_SMSC_SCH4037 + select SB_HT_CHAIN_UNITID_OFFSET_ONLY + select LIFT_BSP_APIC_ID + select SERIAL_CPU_INIT + select BOARD_ROMSIZE_KB_2048 + select BOARD_HAS_FADT + select HAVE_BUS_CONFIG + select HAVE_OPTION_TABLE + select HAVE_PIRQ_TABLE + select HAVE_MP_TABLE + select HAVE_MAINBOARD_RESOURCES + select HAVE_HARD_RESET + select HAVE_ACPI_TABLES + select HAVE_ACPI_RESUME + select ENABLE_APIC_EXT_ID + select TINY_BOOTBLOCK + select GFXUMA + +config MAINBOARD_DIR + string + default amd/dinar + +config APIC_ID_OFFSET + hex + default 0x0 + +config MAINBOARD_PART_NUMBER + string + default "Dinar" + +config HW_MEM_HOLE_SIZEK + hex + default 0x200000 + +config MAX_CPUS + int + default 64 + +config MAX_PHYSICAL_CPUS + int + default 16 + +config HW_MEM_HOLE_SIZE_AUTO_INC + bool + default n + +config IRQ_SLOT_COUNT + int + default 11 + +config RAMTOP + hex + default 0x1000000 + +config HEAP_SIZE + hex + default 0xc0000 + +config STACK_SIZE + hex + default 0x10000 + +config ACPI_SSDTX_NUM + int + default 0 + +config RAMBASE + hex + default 0x200000 + +config XIP_ROM_BASE + hex + default 0xfff00000 + +config XIP_ROM_SIZE + hex + default 0x100000 + +config SIO_PORT + hex + default 0x2e + +config DRIVERS_PS2_KEYBOARD + bool + default y + +config WARNINGS_ARE_ERRORS + bool + default n + +config ONBOARD_VGA_IS_PRIMARY + bool + default y + +config VGA_BIOS + bool + default n + +config VGA_BIOS_ID + depends on VGA_BIOS + default "1002,515e" + +config AHCI_BIOS + bool + default y + +config AHCI_BIOS_FILE + string "AHCI ROM path and filename" + depends on AHCI_BIOS + default "site-local/ahci/sb700.bin" + +config AHCI_BIOS_ID + string "AHCI device PCI IDs" + depends on AHCI_BIOS + default "1002,4391" + +config XHC_BIOS + bool + default n + +config XHC_BIOS_FILE + string "XHC BIOS path and filename" + depends on XHC_BIOS + default "site-local/xhc/Xhc.rom" + +config XHC_BIOS_ID + string "XHC device PCI IDs" + depends on XHC_BIOS + default "1022,7812" + +config CONSOLE_POST + bool + depends on !NO_POST + default n + +config SATA_CONTROLLER_MODE + hex + default 0x0 + depends on SOUTHBRIDGE_AMD_CIMX_SB700 + +config ONBOARD_LAN + bool + default y + +config ONBOARD_1394 + bool + default y + +config ONBOARD_USB30 + bool + default n + +config ONBOARD_BLUETOOTH + bool + default y + +config ONBOARD_WEBCAM + bool + default y + +config ONBOARD_TRAVIS + bool + default y + +config ONBOARD_LIGHTSENSOR + bool + default n + +config PCI_ROM_RUN + bool + default n + +config UDELAY_IO + bool + default n + +config REDIRECT_CIMX_TRACE_TO_SERIAL + bool "Redirect CIMX Trace to serial console" + default y + +endif # BOARD_AMD_DINAR diff --git a/src/mainboard/amd/dinar/Makefile.inc b/src/mainboard/amd/dinar/Makefile.inc new file mode 100644 index 0000000..89e6d42 --- /dev/null +++ b/src/mainboard/amd/dinar/Makefile.inc @@ -0,0 +1,40 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +romstage-y += buildOpts.c +romstage-y += agesawrapper.c +romstage-y += dimmSpd.c +romstage-y += BiosCallOuts.c +romstage-y += sb700_cfg.c +romstage-y += rd890_cfg.c +#romstage-y += PlatformGnbPcie.c + +ramstage-y += buildOpts.c +ramstage-y += agesawrapper.c +ramstage-y += dimmSpd.c +ramstage-y += BiosCallOuts.c +ramstage-y += sb700_cfg.c +ramstage-y += rd890_cfg.c +#ramstage-y += PlatformGnbPcie.c + +ramstage-y += reset.c + +AGESA_PREFIX ?= $(src)/vendorcode/amd/agesa +AGESA_ROOT ?= $(AGESA_PREFIX)/$(if $(CONFIG_CPU_AMD_AGESA_FAMILY15),f15,\ + echo `wrong configuration`) diff --git a/src/mainboard/amd/dinar/Oem.h b/src/mainboard/amd/dinar/Oem.h new file mode 100644 index 0000000..67b1314 --- /dev/null +++ b/src/mainboard/amd/dinar/Oem.h @@ -0,0 +1,79 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _AMD_SB_CIMx_OEM_H_ +#define _AMD_SB_CIMx_OEM_H_ + +#define MOVE_PCIEBAR_TO_F0000000 + +#define LEGACY_FREE 0x00 + +/** + * PCIEX_BASE_ADDRESS - Define PCIE base address + * + * @param[Option] MOVE_PCIEBAR_TO_F0000000 Set PCIe base address to 0xF7000000 + */ +#ifdef MOVE_PCIEBAR_TO_F0000000 +#define PCIEX_BASE_ADDRESS 0xF8000000 +#else +#define PCIEX_BASE_ADDRESS 0xE0000000 +#endif + + +#define SMBUS0_BASE_ADDRESS 0xB00 +#define SMBUS1_BASE_ADDRESS 0xB20 +#define SIO_PME_BASE_ADDRESS 0xE00 +#define SPI_BASE_ADDRESS 0xFEC10000 + +#define WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0 // Watchdog Timer Base Address +#define HPET_BASE_ADDRESS 0xFED00000 // HPET Base address + +#define PM1_EVT_BLK_ADDRESS 0x800 // AcpiPm1EvtBlkAddr; +#define PM1_CNT_BLK_ADDRESS 0x804 // AcpiPm1CntBlkAddr; +#define PM1_TMR_BLK_ADDRESS 0x808 // AcpiPmTmrBlkAddr; +#define CPU_CNT_BLK_ADDRESS 0x810 // CpuControlBlkAddr; +#define GPE0_BLK_ADDRESS 0x820 // AcpiGpe0BlkAddr; +#define SMI_CMD_PORT 0xB0 // SmiCmdPortAddr; +#define ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 // AcpiPmaCntBlkAddr; + +#define EC_LDN5_MAILBOX_ADDRESS 0x550 +#define EC_LDN5_IRQ 0x05 +#define EC_LDN9_MAILBOX_ADDRESS 0x3E + +#define SATA_IDE_MODE_SSID 0x43901002 +#define SATA_RAID_MODE_SSID 0x43921002 +#define SATA_RAID5_MODE_SSID 0x43931002 +#define SATA_AHCI_SSID 0x43911002 +#define OHCI0_SSID 0x43971002 +#define OHCI1_SSID 0x43981002 +#define EHCI0_SSID 0x43961002 +#define OHCI2_SSID 0x43971002 +#define OHCI3_SSID 0x43981002 +#define EHCI1_SSID 0x43961002 +#define OHCI4_SSID 0x43991002 + +#define SMBUS_SSID 0x43851002 +#define IDE_SSID 0x439C1002 +#define AZALIA_SSID 0x43831002 +#define LPC_SSID 0x439D1002 +#define P2P_SSID 0x43841002 + +#define RESERVED_VALUE 0x00 + +#endif //ifndef _AMD_SB_CIMx_OEM_H_ diff --git a/src/mainboard/amd/dinar/OptionsIds.h b/src/mainboard/amd/dinar/OptionsIds.h new file mode 100644 index 0000000..e1d397e --- /dev/null +++ b/src/mainboard/amd/dinar/OptionsIds.h @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/** + * @file + * + * IDS Option File + * + * This file is used to switch on/off IDS features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Core + * @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ + */ +#ifndef _OPTION_IDS_H_ +#define _OPTION_IDS_H_ + +/** + * + * This file generates the defaults tables for the Integrated Debug Support + * Module. The documented build options are imported from a user controlled + * file for processing. The build options for the Integrated Debug Support + * Module are listed below: + * + * IDSOPT_IDS_ENABLED + * IDSOPT_ERROR_TRAP_ENABLED + * IDSOPT_CONTROL_ENABLED + * IDSOPT_TRACING_ENABLED + * IDSOPT_PERF_ANALYSIS + * IDSOPT_ASSERT_ENABLED + * IDS_DEBUG_PORT + * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED + * + **/ + +//#define IDSOPT_IDS_ENABLED TRUE +//#define IDSOPT_TRACING_ENABLED TRUE +#define IDSOPT_ASSERT_ENABLED TRUE + +//#define IDSOPT_DEBUG_ENABLED FALSE +//#undef IDSOPT_HOST_SIMNOW +//#define IDSOPT_HOST_SIMNOW FALSE +//#undef IDSOPT_HOST_HDT +//#define IDSOPT_HOST_HDT FALSE +//#define IDS_DEBUG_PORT 0x80 + +#endif diff --git a/src/mainboard/amd/dinar/PlatformGnbPcie.c b/src/mainboard/amd/dinar/PlatformGnbPcie.c new file mode 100644 index 0000000..277d247 --- /dev/null +++ b/src/mainboard/amd/dinar/PlatformGnbPcie.c @@ -0,0 +1,176 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "heapManager.h" +#include "PlatformGnbPcieComplex.h" +#include "Filecode.h" + +#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE + +PCIe_PORT_DESCRIPTOR PortList [] = { + // Initialize Port descriptor (PCIe port, Lanes 8:15, PCI Device Number 2, ...) + { + 0, //Descriptor flags + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 15), + PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, BIT2) + }, + // Initialize Port descriptor (PCIe port, Lanes 16:19, PCI Device Number 3, ...) + { + 0, //Descriptor flags + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 16, 19), + PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, BIT3) + }, + // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) + { + 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), + PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) + }, + // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) + { + 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), + PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) + }, + // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) + { + 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), + PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) + }, + // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) + { + DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), + PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) + } + // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) + // { + // DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + // PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 8), + // PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) + // } +}; + +PCIe_DDI_DESCRIPTOR DdiList [] = { + // Initialize Ddi descriptor (DDI interface Lanes 24:27, DdA, ...) + { + 0, //Descriptor flags + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27), + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeNutmegDpToVga, Aux2, Hdp2) + }, + // Initialize Ddi descriptor (DDI interface Lanes 28:31, DdB, ...) + { + DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 28, 31), + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeEDP, Aux1, Hdp1) + } +}; + +PCIe_COMPLEX_DESCRIPTOR Llano = { + DESCRIPTOR_TERMINATE_LIST, + 0, + &PortList[0], + &DdiList[0] +}; + +/*---------------------------------------------------------------------------------------*/ +/** + * OemCustomizeInitEarly + * + * Description: + * This is the stub function will call the host environment through the binary block + * interface (call-out port) to provide a user hook opportunity + * + * Parameters: + * @param[in] **PeiServices + * @param[in] *InitEarly + * + * @retval VOID + * + **/ +/*---------------------------------------------------------------------------------------*/ +VOID +OemCustomizeInitEarly ( + IN OUT AMD_EARLY_PARAMS *InitEarly + ) +{ + AGESA_STATUS Status; + VOID *LlanoPcieComplexListPtr; + VOID *LlanoPciePortPtr; + VOID *LlanoPcieDdiPtr; + + ALLOCATE_HEAP_PARAMS AllocHeapParams; + + // GNB PCIe topology Porting + + // + // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR + // + AllocHeapParams.RequestedBufferSize = (sizeof (PCIe_COMPLEX_DESCRIPTOR) + + sizeof (PCIe_PORT_DESCRIPTOR) * 7 + + sizeof (PCIe_DDI_DESCRIPTOR)) * 6; + + AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; + AllocHeapParams.Persist = HEAP_LOCAL_CACHE; + Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader); + if ( Status!= AGESA_SUCCESS) { + // Could not allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR + ASSERT(FALSE); + return Status; + } + + LlanoPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; + + AllocHeapParams.BufferPtr += sizeof (PCIe_COMPLEX_DESCRIPTOR); + LlanoPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr; + + AllocHeapParams.BufferPtr += sizeof (PCIe_PORT_DESCRIPTOR) * 7; + LlanoPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; + + LibAmdMemFill (LlanoPcieComplexListPtr, + 0, + sizeof (PCIe_COMPLEX_DESCRIPTOR), + &InitEarly->StdHeader); + + LibAmdMemFill (LlanoPciePortPtr, + 0, + sizeof (PCIe_PORT_DESCRIPTOR) * 7, + &InitEarly->StdHeader); + + LibAmdMemFill (LlanoPcieDdiPtr, + 0, + sizeof (PCIe_DDI_DESCRIPTOR) * 6, + &InitEarly->StdHeader); + + LibAmdMemCopy (LlanoPcieComplexListPtr, &Llano, sizeof (PCIe_COMPLEX_DESCRIPTOR), &InitEarly->StdHeader); + LibAmdMemCopy (LlanoPciePortPtr, &PortList[0], sizeof (PCIe_PORT_DESCRIPTOR) * 7, &InitEarly->StdHeader); + LibAmdMemCopy (LlanoPcieDdiPtr, &DdiList[0], sizeof (PCIe_DDI_DESCRIPTOR) * 6, &InitEarly->StdHeader); + + + ((PCIe_COMPLEX_DESCRIPTOR*)LlanoPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)LlanoPciePortPtr; + ((PCIe_COMPLEX_DESCRIPTOR*)LlanoPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)LlanoPcieDdiPtr; + + InitEarly->GnbConfig.PcieComplexList = LlanoPcieComplexListPtr; + InitEarly->GnbConfig.PsppPolicy = 0; +} + diff --git a/src/mainboard/amd/dinar/PlatformGnbPcieComplex.h b/src/mainboard/amd/dinar/PlatformGnbPcieComplex.h new file mode 100644 index 0000000..c10d251 --- /dev/null +++ b/src/mainboard/amd/dinar/PlatformGnbPcieComplex.h @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H +#define _PLATFORM_GNB_PCIE_COMPLEX_H + +#include "Porting.h" +#include "AGESA.h" +#include "amdlib.h" + +//GNB GPP Port4 +#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced + +//GNB GPP Port5 +#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced + +//GNB GPP Port6 +#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced + +//GNB GPP Port7 +#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced + +//GNB GPP Port8 +#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 +#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 +#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) +#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced + +VOID +OemCustomizeInitEarly ( + IN OUT AMD_EARLY_PARAMS *InitEarly + ); + +#endif //_PLATFORM_GNB_PCIE_COMPLEX_H diff --git a/src/mainboard/amd/dinar/acpi/cpstate.asl b/src/mainboard/amd/dinar/acpi/cpstate.asl new file mode 100644 index 0000000..ea670a3 --- /dev/null +++ b/src/mainboard/amd/dinar/acpi/cpstate.asl @@ -0,0 +1,75 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This file defines the processor and performance state capability + * for each core in the system. It is included into the DSDT for each + * core. It assumes that each core of the system has the same performance + * characteristics. +*/ +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001) + { + Scope (\_PR) { + Processor(CPU0,0,0x808,0x06) { + #include "cpstate.asl" + } + Processor(CPU1,1,0x0,0x0) { + #include "cpstate.asl" + } + Processor(CPU2,2,0x0,0x0) { + #include "cpstate.asl" + } + Processor(CPU3,3,0x0,0x0) { + #include "cpstate.asl" + } + } +*/ + /* P-state support: The maximum number of P-states supported by the */ + /* CPUs we'll use is 6. */ + /* Get from AMI BIOS. */ + Name(_PSS, Package(){ + Package () + { + 0x00000AF0, + 0x0000BF81, + 0x00000002, + 0x00000002, + 0x00000000, + 0x00000000 + }, + + Package () + { + 0x00000578, + 0x000076F2, + 0x00000002, + 0x00000002, + 0x00000001, + 0x00000001 + } + }) + + Name(_PCT, Package(){ + ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, + ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} + }) + + Method(_PPC, 0){ + Return(0) + } diff --git a/src/mainboard/amd/dinar/acpi/ide.asl b/src/mainboard/amd/dinar/acpi/ide.asl new file mode 100644 index 0000000..765a67e --- /dev/null +++ b/src/mainboard/amd/dinar/acpi/ide.asl @@ -0,0 +1,244 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* +Scope (_SB) { + Device(PCI0) { + Device(IDEC) { + Name(_ADR, 0x00140001) + #include "ide.asl" + } + } +} +*/ + +/* Some timing tables */ +Name(UDTT, Package(){ /* Udma timing table */ + 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */ +}) + +Name(MDTT, Package(){ /* MWDma timing table */ + 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */ +}) + +Name(POTT, Package(){ /* Pio timing table */ + 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */ +}) + +/* Some timing register value tables */ +Name(MDRT, Package(){ /* MWDma timing register table */ + 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */ +}) + +Name(PORT, Package(){ + 0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */ +}) + +OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */ + Field(ICRG, AnyAcc, NoLock, Preserve) +{ + PPTS, 8, /* Primary PIO Slave Timing */ + PPTM, 8, /* Primary PIO Master Timing */ + OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */ + PMTM, 8, /* Primary MWDMA Master Timing */ + OFFSET(0x08), PPCR, 8, /* Primary PIO Control */ + OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */ + PPSM, 4, /* Primary PIO slave Mode */ + OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */ + OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */ + PDSM, 4, /* Primary UltraDMA Mode */ +} + +Method(GTTM, 1) /* get total time*/ +{ + Store(And(Arg0, 0x0F), Local0) /* Recovery Width */ + Increment(Local0) + Store(ShiftRight(Arg0, 4), Local1) /* Command Width */ + Increment(Local1) + Return(Multiply(30, Add(Local0, Local1))) +} + +Device(PRID) +{ + Name (_ADR, Zero) + Method(_GTM, 0) + { + NAME(OTBF, Buffer(20) { /* out buffer */ + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 + }) + + CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */ + CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */ + CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */ + CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */ + CreateDwordField(OTBF, 16, BFFG) /* buffer flags */ + + /* Just return if the channel is disabled */ + If(And(PPCR, 0x01)) { /* primary PIO control */ + Return(OTBF) + } + + /* Always tell them independent timing available and IOChannelReady used on both drives */ + Or(BFFG, 0x1A, BFFG) + + Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */ + Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */ + + If(And(PDCR, 0x01)) { /* It's under UDMA mode */ + Or(BFFG, 0x01, BFFG) + Store(DerefOf(Index(UDTT, PDMM)), DSD0) + } + Else { + Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */ + } + + If(And(PDCR, 0x02)) { /* It's under UDMA mode */ + Or(BFFG, 0x04, BFFG) + Store(DerefOf(Index(UDTT, PDSM)), DSD1) + } + Else { + Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */ + } + + Return(OTBF) /* out buffer */ + } /* End Method(_GTM) */ + + Method(_STM, 3, NotSerialized) + { + NAME(INBF, Buffer(20) { /* in buffer */ + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 + }) + + CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */ + CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */ + CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */ + CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */ + CreateDwordField(INBF, 16, BFFG) /*buffer flag */ + + Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0) + Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */ + Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1) + Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */ + + Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */ + Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */ + + If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */ + Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0) + Divide(Local0, 7, PDMM,) + Or(PDCR, 0x01, PDCR) + } + Else { + If(LNotEqual(DSD0, 0xFFFFFFFF)) { + Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0) + Store(DerefOf(Index(MDRT, Local0)), PMTM) + } + } + + If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */ + Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0) + Divide(Local0, 7, PDSM,) + Or(PDCR, 0x02, PDCR) + } + Else { + If(LNotEqual(DSD1, 0xFFFFFFFF)) { + Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0) + Store(DerefOf(Index(MDRT, Local0)), PMTS) + } + } + /* Return(INBF) */ + } /*End Method(_STM) */ + Device(MST) + { + Name(_ADR, 0) + Method(_GTF) { + Name(CMBF, Buffer(21) { + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 + }) + CreateByteField(CMBF, 1, POMD) + CreateByteField(CMBF, 8, DMMD) + CreateByteField(CMBF, 5, CMDA) + CreateByteField(CMBF, 12, CMDB) + CreateByteField(CMBF, 19, CMDC) + + Store(0xA0, CMDA) + Store(0xA0, CMDB) + Store(0xA0, CMDC) + + Or(PPMM, 0x08, POMD) + + If(And(PDCR, 0x01)) { + Or(PDMM, 0x40, DMMD) + } + Else { + Store(Match + (MDTT, MLE, GTTM(PMTM), + MTR, 0, 0), Local0) + If(LLess(Local0, 3)) { + Or(0x20, Local0, DMMD) + } + } + Return(CMBF) + } + } /* End Device(MST) */ + + Device(SLAV) + { + Name(_ADR, 1) + Method(_GTF) { + Name(CMBF, Buffer(21) { + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 + }) + CreateByteField(CMBF, 1, POMD) + CreateByteField(CMBF, 8, DMMD) + CreateByteField(CMBF, 5, CMDA) + CreateByteField(CMBF, 12, CMDB) + CreateByteField(CMBF, 19, CMDC) + + Store(0xB0, CMDA) + Store(0xB0, CMDB) + Store(0xB0, CMDC) + + Or(PPSM, 0x08, POMD) + + If(And(PDCR, 0x02)) { + Or(PDSM, 0x40, DMMD) + } + Else { + Store(Match + (MDTT, MLE, GTTM(PMTS), + MTR, 0, 0), Local0) + If(LLess(Local0, 3)) { + Or(0x20, Local0, DMMD) + } + } + Return(CMBF) + } + } /* End Device(SLAV) */ +} diff --git a/src/mainboard/amd/dinar/acpi/routing.asl b/src/mainboard/amd/dinar/acpi/routing.asl new file mode 100644 index 0000000..c7a9165 --- /dev/null +++ b/src/mainboard/amd/dinar/acpi/routing.asl @@ -0,0 +1,311 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 + ) + { + #include "routing.asl" + } +*/ + +/* Routing is in System Bus scope */ +Scope(\_SB) { + Name(PR0, Package(){ + /* NB devices */ + /* Bus 0, Dev 0 - RS780 Host Controller */ + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ + Package(){0x0001FFFF, 0, INTC, 0 }, + Package(){0x0001FFFF, 1, INTD, 0 }, + /* Bus 0, Dev 2 - */ + Package(){0x0002FFFF, 0, INTC, 0 }, + Package(){0x0002FFFF, 1, INTD, 0 }, + Package(){0x0002FFFF, 2, INTA, 0 }, + Package(){0x0002FFFF, 3, INTB, 0 }, + /* Bus 0, Dev 3 - */ + Package(){0x0003FFFF, 0, INTD, 0 }, + Package(){0x0003FFFF, 1, INTA, 0 }, + Package(){0x0003FFFF, 2, INTB, 0 }, + Package(){0x0003FFFF, 3, INTC, 0 }, + /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ + Package(){0x0004FFFF, 0, INTA, 0 }, + Package(){0x0004FFFF, 1, INTB, 0 }, + Package(){0x0004FFFF, 2, INTC, 0 }, + Package(){0x0004FFFF, 3, INTD, 0 }, + /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ + Package(){0x0005FFFF, 0, INTB, 0 }, + Package(){0x0005FFFF, 1, INTC, 0 }, + Package(){0x0005FFFF, 2, INTD, 0 }, + Package(){0x0005FFFF, 3, INTA, 0 }, + /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */ + Package(){0x0006FFFF, 0, INTC, 0 }, + Package(){0x0006FFFF, 1, INTD, 0 }, + Package(){0x0006FFFF, 2, INTA, 0 }, + Package(){0x0006FFFF, 3, INTB, 0 }, + /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */ + Package(){0x0007FFFF, 0, INTD, 0 }, + Package(){0x0007FFFF, 1, INTA, 0 }, + Package(){0x0007FFFF, 2, INTB, 0 }, + Package(){0x0007FFFF, 3, INTC, 0 }, + + /* SB devices */ + /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */ + Package(){0x0014FFFF, 0, INTA, 0 }, + Package(){0x0014FFFF, 1, INTB, 0 }, + Package(){0x0014FFFF, 2, INTC, 0 }, + Package(){0x0014FFFF, 3, INTD, 0 }, + /* Bus 0, Dev 18,19,22 - USB: OHCI,EHCI */ + Package(){0x0012FFFF, 0, INTC, 0 }, + Package(){0x0012FFFF, 1, INTB, 0 }, + Package(){0x0013FFFF, 0, INTC, 0 }, + Package(){0x0013FFFF, 1, INTB, 0 }, + Package(){0x0016FFFF, 0, INTC, 0 }, + Package(){0x0016FFFF, 1, INTB, 0 }, + Package(){0x0010FFFF, 0, INTC, 0 }, + Package(){0x0010FFFF, 1, INTB, 0 }, + /* Bus 0, Dev 17 - SATA controller #2 */ + Package(){0x0011FFFF, 0, INTD, 0 }, + /* Bus 0, Dev 21 - PCIe Bridge for x1 PCIe Slot */ + Package(){0x0015FFFF, 0, INTA, 0 }, + Package(){0x0015FFFF, 1, INTB, 0 }, + Package(){0x0015FFFF, 2, INTC, 0 }, + Package(){0x0015FFFF, 3, INTD, 0 }, + }) + + Name(APR0, Package(){ + /* NB devices in APIC mode */ + /* Bus 0, Dev 0 - RS780 Host Controller */ + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ + Package(){0x0001FFFF, 0, 0, 18 }, + Package(){0x0001FFFF, 1, 0, 19 }, + /* Bus 0, Dev 2 */ + Package(){0x0002FFFF, 0, 0, 18 }, + Package(){0x0002FFFF, 1, 0, 19 }, + Package(){0x0002FFFF, 2, 0, 16 }, + Package(){0x0002FFFF, 3, 0, 17 }, + /* Bus 0, Dev 3 */ + Package(){0x0003FFFF, 0, 0, 19 }, + Package(){0x0003FFFF, 1, 0, 16 }, + Package(){0x0003FFFF, 2, 0, 17 }, + Package(){0x0003FFFF, 3, 0, 18 }, + /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ + Package(){0x0004FFFF, 0, 0, 16 }, + Package(){0x0004FFFF, 1, 0, 17 }, + Package(){0x0004FFFF, 2, 0, 18 }, + Package(){0x0004FFFF, 3, 0, 19 }, + /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ + Package(){0x0005FFFF, 0, 0, 17 }, + Package(){0x0005FFFF, 1, 0, 18 }, + Package(){0x0005FFFF, 2, 0, 19 }, + Package(){0x0005FFFF, 3, 0, 16 }, + /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */ + Package(){0x0006FFFF, 0, 0, 18 }, + Package(){0x0006FFFF, 1, 0, 19 }, + Package(){0x0006FFFF, 2, 0, 16 }, + Package(){0x0006FFFF, 3, 0, 17 }, + /* Bus 0, Dev 7 - PCIe Bridge for network card */ + Package(){0x0007FFFF, 0, 0, 19 }, + Package(){0x0007FFFF, 1, 0, 16 }, + Package(){0x0007FFFF, 2, 0, 17 }, + Package(){0x0007FFFF, 3, 0, 18 }, + + /* SB devices in APIC mode */ + /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */ + Package(){0x0014FFFF, 0, 0, 16 }, + Package(){0x0014FFFF, 1, 0, 17 }, + Package(){0x0014FFFF, 2, 0, 18 }, + Package(){0x0014FFFF, 3, 0, 19 }, + /* Bus 0, Dev 18,19,22 - USB: OHCI,EHCI*/ + Package(){0x0012FFFF, 0, 0, 18 }, + Package(){0x0012FFFF, 1, 0, 17 }, + Package(){0x0013FFFF, 0, 0, 18 }, + Package(){0x0013FFFF, 1, 0, 17 }, + Package(){0x0016FFFF, 0, 0, 18 }, + Package(){0x0016FFFF, 1, 0, 17 }, + Package(){0x0010FFFF, 0, 0, 18 }, + Package(){0x0010FFFF, 1, 0, 17 }, + /* Bus 0, Dev 17 - SATA controller #2 */ + Package(){0x0011FFFF, 0, 0, 19 }, + /* Bus 0, Dev 21 - PCIe Bridge for x1 PCIe Slot */ + Package(){0x0015FFFF, 0, 0, 16 }, + Package(){0x0015FFFF, 1, 0, 17 }, + Package(){0x0015FFFF, 2, 0, 18 }, + Package(){0x0015FFFF, 3, 0, 19 }, + }) + + Name(PS2, Package(){ + /* For Device(PBR2) PIC mode*/ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, + }) + + Name(APS2, Package(){ + /* For Device(PBR2) APIC mode*/ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + Name(PS3, Package(){ + /* For Device(PBR3) PIC mode*/ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + + Name(APS3, Package(){ + /* For Device(PBR3) APIC mode*/ + Package(){0x0000FFFF, 0, 0, 19 }, + Package(){0x0000FFFF, 1, 0, 16 }, + Package(){0x0000FFFF, 2, 0, 17 }, + Package(){0x0000FFFF, 3, 0, 18 }, + }) + + Name(PS4, Package(){ + /* For Device(PBR4) PIC mode*/ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, + }) + + Name(APS4, Package(){ + /* For Device(PBR4) APIC mode*/ + Package(){0x0000FFFF, 0, 0, 16 }, + Package(){0x0000FFFF, 1, 0, 17 }, + Package(){0x0000FFFF, 2, 0, 18 }, + Package(){0x0000FFFF, 3, 0, 19 }, + }) + + Name(PS5, Package(){ + /* For Device(PBR5) PIC mode*/ + Package(){0x0000FFFF, 0, INTB, 0 }, + Package(){0x0000FFFF, 1, INTC, 0 }, + Package(){0x0000FFFF, 2, INTD, 0 }, + Package(){0x0000FFFF, 3, INTA, 0 }, + }) + + Name(APS5, Package(){ + /* For Device(PBR5) APIC mode*/ + Package(){0x0000FFFF, 0, 0, 17 }, + Package(){0x0000FFFF, 1, 0, 18 }, + Package(){0x0000FFFF, 2, 0, 19 }, + Package(){0x0000FFFF, 3, 0, 16 }, + }) + + Name(PS6, Package(){ + /* For Device(PBR6) PIC mode*/ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, + }) + + Name(APS6, Package(){ + /* For Device(PBR6) APIC mode*/ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + Name(PS7, Package(){ + /* For Device(PBR7) PIC mode*/ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + + Name(APS7, Package(){ + /* For Device(PBR7) APIC mode*/ + Package(){0x0000FFFF, 0, 0, 19 }, + Package(){0x0000FFFF, 1, 0, 16 }, + Package(){0x0000FFFF, 2, 0, 17 }, + Package(){0x0000FFFF, 3, 0, 18 }, + }) + + Name(PE0, Package(){ + /* For Device(PE20) PIC mode*/ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, + }) + + Name(APE0, Package(){ + /* For Device(PE20) APIC mode*/ + Package(){0x0000FFFF, 0, 0, 16 }, + Package(){0x0000FFFF, 1, 0, 17 }, + Package(){0x0000FFFF, 2, 0, 18 }, + Package(){0x0000FFFF, 3, 0, 19 }, + }) + + Name(PE1, Package(){ + /* For Device(PE21) PIC mode*/ + Package(){0x0000FFFF, 0, INTB, 0 }, + Package(){0x0000FFFF, 1, INTC, 0 }, + Package(){0x0000FFFF, 2, INTD, 0 }, + Package(){0x0000FFFF, 3, INTA, 0 }, + }) + + Name(APE1, Package(){ + /* For Device(PE21) APIC mode*/ + Package(){0x0000FFFF, 0, 0, 17 }, + Package(){0x0000FFFF, 1, 0, 18 }, + Package(){0x0000FFFF, 2, 0, 19 }, + Package(){0x0000FFFF, 3, 0, 16 }, + }) + + Name(PE2, Package(){ + /* For Device(PE22) PIC mode*/ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, + }) + + Name(APE2, Package(){ + /* For Device(PE22) APIC mode*/ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + Name(PE3, Package(){ + /* For Device(PE23) PIC mode*/ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + + Name(APE3, Package(){ + /* For Device(PE23) APIC mode*/ + Package(){0x0000FFFF, 0, 0, 19 }, + Package(){0x0000FFFF, 1, 0, 16 }, + Package(){0x0000FFFF, 2, 0, 17 }, + Package(){0x0000FFFF, 3, 0, 18 }, + }) +} diff --git a/src/mainboard/amd/dinar/acpi/sata.asl b/src/mainboard/amd/dinar/acpi/sata.asl new file mode 100644 index 0000000..32b9cd9 --- /dev/null +++ b/src/mainboard/amd/dinar/acpi/sata.asl @@ -0,0 +1,149 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* simple name description */ + +/* +Scope (_SB) { + Device(PCI0) { + Device(SATA) { + Name(_ADR, 0x00110000) + #include "sata.asl" + } + } +} +*/ + +Name(STTM, Buffer(20) { + 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, + 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, + 0x1f, 0x00, 0x00, 0x00 +}) + +/* Start by clearing the PhyRdyChg bits */ +Method(_INI) { + \_GPE._L1F() +} + +Device(PMRY) +{ + Name(_ADR, 0) + Method(_GTM, 0x0, NotSerialized) { + Return(STTM) + } + Method(_STM, 0x3, NotSerialized) {} + + Device(PMST) { + Name(_ADR, 0) + Method(_STA,0) { + if (LGreater(P0IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + }/* end of PMST */ + + Device(PSLA) + { + Name(_ADR, 1) + Method(_STA,0) { + if (LGreater(P1IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of PSLA */ +} /* end of PMRY */ + + +Device(SEDY) +{ + Name(_ADR, 1) /* IDE Scondary Channel */ + Method(_GTM, 0x0, NotSerialized) { + Return(STTM) + } + Method(_STM, 0x3, NotSerialized) {} + + Device(SMST) + { + Name(_ADR, 0) + Method(_STA,0) { + if (LGreater(P2IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of SMST */ + + Device(SSLA) + { + Name(_ADR, 1) + Method(_STA,0) { + if (LGreater(P3IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of SSLA */ +} /* end of SEDY */ + +/* SATA Hot Plug Support */ +Scope(\_GPE) { + Method(_L1F,0x0,NotSerialized) { + if (\_SB.P0PR) { + if (LGreater(\_SB.P0IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P0PR) + } + + if (\_SB.P1PR) { + if (LGreater(\_SB.P1IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P1PR) + } + + if (\_SB.P2PR) { + if (LGreater(\_SB.P2IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P2PR) + } + + if (\_SB.P3PR) { + if (LGreater(\_SB.P3IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P3PR) + } + } +} diff --git a/src/mainboard/amd/dinar/acpi/usb.asl b/src/mainboard/amd/dinar/acpi/usb.asl new file mode 100644 index 0000000..8a87ace --- /dev/null +++ b/src/mainboard/amd/dinar/acpi/usb.asl @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + diff --git a/src/mainboard/amd/dinar/acpi_tables.c b/src/mainboard/amd/dinar/acpi_tables.c new file mode 100644 index 0000000..ee00e81 --- /dev/null +++ b/src/mainboard/amd/dinar/acpi_tables.c @@ -0,0 +1,320 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <string.h> +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <arch/ioapic.h> +#include <arch/io.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/mtrr.h> + +#include "agesawrapper.h" + +#define DUMP_ACPI_TABLES 0 + +#if DUMP_ACPI_TABLES == 1 +static void dump_mem(u32 start, u32 end) +{ + + u32 i; + print_debug("dump_mem:"); + for (i = start; i < end; i++) { + if ((i & 0xf) == 0) { + printk(BIOS_DEBUG, "\n%08x:", i); + } + printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i)); + } + print_debug("\n"); +} +#endif + +extern const unsigned char AmlCode[]; + + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + /* Just a dummy */ + return current; +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + device_t dev; + u32 dword; + u32 gsi_base = 0; + u32 apicid_sb700; + u32 apicid_rd890; + + /* + * AGESA v5 Apply apic enumeration rules + * For systems with >= 16 APICs, put the IO-APICs at 0..n and + * put the local-APICs at m..z + * For systems with < 16 APICs, put the Local-APICs at 0..n and + * put the IO-APICs at (n + 1)..z + */ +#if CONFIG_MAX_CPUS >= 16 + apicid_sb700 = 0x0; +#else + apicid_sb700 = CONFIG_MAX_CPUS + 1 +#endif + apicid_rd890 = apicid_sb700 + 1; + + /* create all subtables for processors */ + current = acpi_create_madt_lapics(current); + + /* Write sb700 IOAPIC, only one */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + apicid_sb700, + IO_APIC_ADDR, + 0 + ); + + /* IOAPIC on rs5690 */ + gsi_base += IO_APIC_INTERRUPTS; /* sb700 has 24 IOAPIC entries. */ + dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + if (dev) { + pci_write_config32(dev, 0xF8, 0x1); + dword = pci_read_config32(dev, 0xFC) & 0xfffffff0; + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + apicid_rd890, + dword, + gsi_base + ); + } + + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, + 0, //BUS + 0, //SOURCE + 2, //gsirq + 0 //flags + ); + + /* 0: mean bus 0--->ISA */ + /* 0: PIC 0 */ + /* 2: APIC 2 */ + /* 5 mean: 0101 --> Edige-triggered, Active high */ + + /* create all subtables for processors */ + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0, 5, 1); + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 1, 5, 1); + /* 1: LINT1 connect to NMI */ + + return current; +} + +unsigned long acpi_fill_slit(unsigned long current) +{ + // Not implemented + return current; +} + +unsigned long acpi_fill_srat(unsigned long current) +{ + /* No NUMA, no SRAT */ + return current; +} + +unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) +{ + int lens; + msr_t msr; + char pscope[] = "\\_SB.PCI0"; + + lens = acpigen_write_scope(pscope); + msr = rdmsr(TOP_MEM); + lens += acpigen_write_name_dword("TOM1", msr.lo); + msr = rdmsr(TOP_MEM2); + /* + * Since XP only implements parts of ACPI 2.0, we can't use a qword + * here. + * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt + * slide 22ff. + * Shift value right by 20 bit to make it fit into 32bit, + * giving us 1MB granularity and a limit of almost 4Exabyte of memory. + */ + lens += acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20); + acpigen_patch_len(lens - 1); + return (unsigned long) (acpigen_get_current()); +} + +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + acpi_rsdp_t *rsdp; + acpi_rsdt_t *rsdt; + //acpi_hpet_t *hpet; + acpi_madt_t *madt; + acpi_srat_t *srat; + acpi_slit_t *slit; + acpi_fadt_t *fadt; + acpi_facs_t *facs; + acpi_header_t *dsdt; + acpi_header_t *ssdt; + acpi_header_t *ssdt2; + acpi_header_t *alib; + + get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ + + /* Align ACPI tables to 16 bytes */ + start = (start + 0x0f) & -0x10; + current = start; + + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); + + /* We need at least an RSDP and an RSDT Table */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + + /* clear all table memory */ + memset((void *)start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt, NULL); + acpi_write_rsdt(rsdt); + + /* FACS */ + printk(BIOS_DEBUG, "ACPI: * FACS\n"); + facs = (acpi_facs_t *) current; + current += sizeof(acpi_facs_t); + acpi_create_facs(facs); + + /* DSDT */ + printk(BIOS_DEBUG, "ACPI: * DSDT\n"); + dsdt = (acpi_header_t *)current; + memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); + current += dsdt->length; + memcpy(dsdt, &AmlCode, dsdt->length); + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, dsdt->length); + /* FADT */ + printk(BIOS_DEBUG, "ACPI: * FADT\n"); + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdp, fadt); + + /* + * We explicitly add these tables later on: + */ +#ifdef UNUSED_CODE // Don't need HPET table. we have one in dsdt + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current); + hpet = (acpi_hpet_t *) current; + current += sizeof(acpi_hpet_t); + acpi_create_hpet(hpet); + acpi_add_table(rsdp, hpet); +#endif + + /* If we want to use HPET Timers Linux wants an MADT */ + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current); + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current += madt->header.length; + acpi_add_table(rsdp, madt); + + /* SRAT */ + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); + srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT); + if (srat != NULL) { + memcpy((void *)current, srat, srat->header.length); + srat = (acpi_srat_t *) current; + //acpi_create_srat(srat); + current += srat->header.length; + acpi_add_table(rsdp, srat); + } + + /* SLIT */ + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); + slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT); + if (slit != NULL) { + memcpy((void *)current, slit, slit->header.length); + slit = (acpi_slit_t *) current; + //acpi_create_slit(slit); + current += slit->header.length; + acpi_add_table(rsdp, slit); + } + + /* SSDT */ + current = (current + 0x0f) & -0x10; + printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current); + alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); + if (alib != NULL) { + memcpy((void *)current, alib, alib->length); + ssdt = (acpi_header_t *) current; + current += alib->length; + acpi_add_table(rsdp,alib); + } else { + printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); + } + +#if 0 // The DSDT needs additional work for the AGESA SSDT Pstate table + current = ( current + 0x0f) & -0x10; + printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current); + ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); + if (ssdt != NULL) { + memcpy((void *)current, ssdt, ssdt->length); + ssdt = (acpi_header_t *) current; + current += ssdt->length; + } else { + printk(BIOS_DEBUG, " AGESA SSDT table NULL. Skipping.\n"); + } + acpi_add_table(rsdp,ssdt); +#endif + + current = ( current + 0x0f) & -0x10; + printk(BIOS_DEBUG, "ACPI: * coreboot TOM SSDT2 at %lx\n", current); + ssdt2 = (acpi_header_t *) current; + acpi_create_ssdt_generator(ssdt2, ACPI_TABLE_CREATOR); + current += ssdt2->length; + acpi_add_table(rsdp,ssdt2); + +#if DUMP_ACPI_TABLES == 1 + printk(BIOS_DEBUG, "rsdp\n"); + dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t)); + + printk(BIOS_DEBUG, "rsdt\n"); + dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t)); + + printk(BIOS_DEBUG, "madt\n"); + dump_mem(madt, ((void *)madt) + madt->header.length); + + printk(BIOS_DEBUG, "srat\n"); + dump_mem(srat, ((void *)srat) + srat->header.length); + + printk(BIOS_DEBUG, "slit\n"); + dump_mem(slit, ((void *)slit) + slit->header.length); + + printk(BIOS_DEBUG, "ssdt\n"); + dump_mem(ssdt, ((void *)ssdt) + ssdt->length); + + printk(BIOS_DEBUG, "fadt\n"); + dump_mem(fadt, ((void *)fadt) + fadt->header.length); +#endif + + printk(BIOS_INFO, "ACPI: done.\n"); + return current; +} diff --git a/src/mainboard/amd/dinar/agesawrapper.c b/src/mainboard/amd/dinar/agesawrapper.c new file mode 100644 index 0000000..afbf108 --- /dev/null +++ b/src/mainboard/amd/dinar/agesawrapper.c @@ -0,0 +1,628 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#include <stdint.h> +#include <string.h> +#include "agesawrapper.h" +#include "BiosCallOuts.h" +#include "cpuRegisters.h" +#include "cpuCacheInit.h" +#include "cpuApicUtilities.h" +#include "cpuEarlyInit.h" +#include "cpuLateInit.h" +#include "Dispatcher.h" +#include "cpuCacheInit.h" +#include "amdlib.h" +#include "PlatformGnbPcieComplex.h" +#include "heapManager.h" +#include "Filecode.h" +#include <arch/io.h> + +#define FILECODE UNASSIGNED_FILE_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/* ACPI table pointers returned by AmdInitLate */ +VOID *DmiTable = NULL; +VOID *AcpiPstate = NULL; +VOID *AcpiSrat = NULL; +VOID *AcpiSlit = NULL; + +VOID *AcpiWheaMce = NULL; +VOID *AcpiWheaCmc = NULL; +VOID *AcpiAlib = NULL; + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*--------------------------------------------------------------------------------------- + * L O C A L F U N C T I O N S + *--------------------------------------------------------------------------------------- + */ + +/*Get the Bus Number from CONFIG_MMCONF_BUS_NUMBER, Please reference AMD BIOS BKDG docuemt about it*/ +/* +BusRange: bus range identifier. Read-write. Reset: X. This specifies the number of buses in the +MMIO configuration space range. The size of the MMIO configuration space range varies with this +field as follows: the size is 1 Mbyte times the number of buses. This field is encoded as follows: +Bits Buses Bits Buses +0h 1 5h 32 +1h 2 6h 64 +2h 4 7h 128 +3h 8 8h 256 +4h 16 Fh-9h Reserved +*/ +UINT8 +GetEndBusNum ( + VOID + ) +{ + UINT64 BusNum; + UINT8 Index; + for (Index = 1; Index <= 8; Index ++ ) { + BusNum = CONFIG_MMCONF_BUS_NUMBER >> Index; + if (BusNum == 1 ) { + break; + } + } + return Index; +} + +UINT32 +agesawrapper_amdinitcpuio ( + VOID + ) +{ + AGESA_STATUS Status; + UINT64 MsrReg; + UINT32 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader; + UINT32 TopMem; + UINT32 NodeCnt; + UINT32 Node; + UINT32 SbLink; + UINT32 Index; + + /* get the number of coherent nodes in the system */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 0, 0x60); + LibAmdPciRead(AccessWidth32, PciAddress, &PciData, &StdHeader); + NodeCnt = ((PciData >> 4) & 7) + 1; //NodeCnt[6:4] + /* Find out the Link ID of Node0 that connects to the + * Southbridge (system IO hub). e.g. family10 MCM Processor, + * SbLink is Processor0 Link2, internal Node0 Link3 + */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 0, 0x64); + LibAmdPciRead(AccessWidth32, PciAddress, &PciData, &StdHeader); + SbLink = (PciData >> 8) & 3; //assume ganged + /* Enable MMIO on AMD CPU Address Map Controller for all nodes */ + for (Node = 0; Node < NodeCnt; Node ++) { + /* clear all MMIO Mapped Base/Limit Registers */ + for (Index = 0; Index < 8; Index ++) { + PciData = 0x00000000; + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18 + Node, 1, 0x80 + Index * 8); + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18 + Node, 1, 0x84 + Index * 8); + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + } + /* clear all IO Space Base/Limit Registers */ + for (Index = 0; Index < 4; Index ++) { + PciData = 0x00000000; + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18 + Node, 1, 0xC0 + Index * 8); + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18 + Node, 1, 0xC4 + Index * 8); + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + } + + /* Enable MMIO on AMD CPU Address Map Controller */ + + /* Set VGA Ram MMIO 0000A0000-0000BFFFF to Node0 sbLink */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0x80); + PciData = (0xA0000 >> 8) |3; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0x84); + PciData = 0xB0000 >> 8; + PciData &= (~0xFF); + PciData |= SbLink << 4; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Set UMA MMIO. */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0x88); + LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader); + TopMem = (UINT32)MsrReg; + MsrReg = (MsrReg >> 8) | 3; + PciData = (UINT32)MsrReg; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0x8c); + if (TopMem <= CONFIG_MMCONF_BASE_ADDRESS) { + PciData = (CONFIG_MMCONF_BASE_ADDRESS - 1) >> 8; + } + else { + PciData = (0x100000000ull - 1) >> 8; + } + PciData &= (~0xFF); + PciData |= SbLink << 4; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Set PCIE MMIO. */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0x90); + PciData = (CONFIG_MMCONF_BASE_ADDRESS >> 8) |3; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0x94); + PciData = (( CONFIG_MMCONF_BASE_ADDRESS + CONFIG_MMCONF_BUS_NUMBER * 4096 *256 - 1) >> 8) & (~0xFF); + PciData &= (~0xFF); + PciData |= MMIO_NP_BIT; + PciData |= SbLink << 4; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Set XAPIC MMIO. 24K */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0x98); + PciData = (0xFEC00000 >> 8) |3; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0x9c); + PciData = ((0xFEC00000 + 6 * 4096 - 1) >> 8); + PciData &= (~0xFF); + PciData |= MMIO_NP_BIT; + PciData |= SbLink << 4; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Set Local APIC MMIO. 4K*4= 16K, Llano CPU are 4 cores */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0xA0); + PciData = (0xFEE00000 >> 8) |3; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0xA8); + PciData = (0xFEE00000 + 4 * 4096 - 1) >> 8; + PciData &= (~0xFF); + PciData |= MMIO_NP_BIT; + PciData |= SbLink << 4; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Set PCIO: 0x0 - 0xFFF000 and enabled VGA IO*/ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0xC0); + PciData = 0x13; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0xC4); + PciData = 0x00FFF000; + PciData &= (~0x7F); + PciData |= SbLink << 4; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + } + Status = AGESA_SUCCESS; + return (UINT32)Status; +} + +UINT32 +agesawrapper_amdinitmmio ( + VOID + ) +{ + AGESA_STATUS Status; + UINT64 MsrReg; + UINT32 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader; + + /* + Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base + Address MSR register. + */ + MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (GetEndBusNum () << 2) | 1; + LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader); + + /* + Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. + */ + LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader); + MsrReg = MsrReg | BIT46; + LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); + + /* Set PCIE MMIO. */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x90); + + PciData = (CONFIG_MMCONF_BASE_ADDRESS >> 8) |3; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x94); + PciData = (( CONFIG_MMCONF_BASE_ADDRESS + CONFIG_MMCONF_BUS_NUMBER * 4096 *256 - 1) >> 8) | MMIO_NP_BIT; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Enable memory access */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0x04); + LibAmdPciRead(AccessWidth8, PciAddress, &PciData, &StdHeader); + + PciData |= BIT1; + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0x04); + LibAmdPciWrite(AccessWidth8, PciAddress, &PciData, &StdHeader); + + /* Set ROM cache onto WP to decrease post time */ + MsrReg = (0x0100000000 - CONFIG_ROM_SIZE) | 5; + LibAmdMsrWrite (0x20E, &MsrReg, &StdHeader); + MsrReg = (0x1000000000 - CONFIG_ROM_SIZE) | 0x800; + LibAmdMsrWrite (0x20F, &MsrReg, &StdHeader); + + Status = AGESA_SUCCESS; + return (UINT32)Status; +} + +UINT32 +agesawrapper_amdinitreset ( + VOID + ) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_RESET_PARAMS AmdResetParams; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + + LibAmdMemFill (&AmdResetParams, + 0, + sizeof (AMD_RESET_PARAMS), + &(AmdResetParams.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET; + AmdParamStruct.AllocationMethod = ByHost; + AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS); + AmdParamStruct.NewStructPtr = &AmdResetParams; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = NULL; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct (&AmdParamStruct); + AmdResetParams.HtConfig.Depth = 0; +#if (defined AGESA_ENTRY_INIT_RESET) && (AGESA_ENTRY_INIT_RESET == TRUE) + status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); +#endif + + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AmdReleaseStruct (&AmdParamStruct); + return (UINT32)status; +} + +UINT32 +agesawrapper_amdinitearly ( + VOID + ) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_EARLY_PARAMS *AmdEarlyParamsPtr; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; + AmdParamStruct.AllocationMethod = PreMemHeap; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct (&AmdParamStruct); + + AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr; + OemCustomizeInitEarly (AmdEarlyParamsPtr); + + status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AmdReleaseStruct (&AmdParamStruct); + + return (UINT32)status; +} +/*---------------------------------------------------------------------------------------*/ +/** + * OemCustomizeInitEarly + * + * Description: + * This is the stub function will call the host environment through the binary block + * interface (call-out port) to provide a user hook opportunity + * + * Parameters: + * @param[in] **PeiServices + * @param[in] *InitEarly + * + * @retval VOID + * + **/ +/*---------------------------------------------------------------------------------------*/ +VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly) +{ + //InitEarly->PlatformConfig.CoreLevelingMode = CORE_LEVEL_TWO; +} + +VOID +OemCustomizeInitPost ( + IN AMD_POST_PARAMS *InitPost + ) +{ + InitPost->MemConfig.UmaMode = UMA_AUTO; + InitPost->MemConfig.BottomIo = 0xE0; + InitPost->MemConfig.UmaSize = 0xE0-0xC0; +} + +UINT32 +agesawrapper_amdinitpost ( + VOID + ) +{ + AGESA_STATUS status; + UINT16 i; + UINT32 *HeadPtr; + AMD_INTERFACE_PARAMS AmdParamStruct; + BIOS_HEAP_MANAGER *BiosManagerPtr; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; + AmdParamStruct.AllocationMethod = PreMemHeap; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + + AmdCreateStruct (&AmdParamStruct); + + /* OEM Should Customize the defaults through this hook */ + OemCustomizeInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr); + + status = AmdInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AmdReleaseStruct (&AmdParamStruct); + + /* Initialize heap space */ + BiosManagerPtr = (BIOS_HEAP_MANAGER *)BIOS_HEAP_START_ADDRESS; + + HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof (BIOS_HEAP_MANAGER)); + for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++) + { + *HeadPtr = 0x00000000; + HeadPtr++; + } + BiosManagerPtr->StartOfAllocatedNodes = 0; + BiosManagerPtr->StartOfFreedNodes = 0; + + return (UINT32)status; +} + +UINT32 +agesawrapper_amdinitenv ( + VOID + ) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + PCI_ADDR PciAddress; + UINT32 PciValue; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct (&AmdParamStruct); + status = AmdInitEnv ((AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AmdReleaseStruct (&AmdParamStruct); + + return (UINT32)status; +} + +VOID * +agesawrapper_getlateinitptr ( + int pick + ) +{ + switch (pick) { + case PICK_DMI: + return DmiTable; + + case PICK_PSTATE: + return AcpiPstate; + + case PICK_SRAT: + return AcpiSrat; + + case PICK_SLIT: + return AcpiSlit; + case PICK_WHEA_MCE: + return AcpiWheaMce; + case PICK_WHEA_CMC: + return AcpiWheaCmc; + case PICK_ALIB: + return AcpiAlib; + default: + return NULL; + } +} + +UINT32 +agesawrapper_amdinitmid ( + VOID + ) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + + printk(BIOS_EMERG, "file '%s',line %d, %s()\n", __FILE__, __LINE__, __func__); + /* Enable MMIO on AMD CPU Address Map Controller */ + agesawrapper_amdinitcpuio (); + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + + AmdCreateStruct (&AmdParamStruct); + + status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AmdReleaseStruct (&AmdParamStruct); + + return (UINT32)status; +} + +UINT32 +agesawrapper_amdinitlate(VOID) +{ + AGESA_STATUS Status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_LATE_PARAMS *AmdLateParamsPtr; + + LibAmdMemFill(&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdParamStruct.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; + + AmdCreateStruct (&AmdParamStruct); + AmdLateParamsPtr = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr; + + printk(BIOS_DEBUG, "agesawrapper_amdinitlate: AmdLateParamsPtr = %X\n", (u32)AmdLateParamsPtr); + + Status = AmdInitLate(AmdLateParamsPtr); + if (Status != AGESA_SUCCESS) { + //agesawrapper_amdreadeventlog(AmdLateParamsPtr->StdHeader.HeapStatus); + agesawrapper_amdreadeventlog(); + ASSERT(Status == AGESA_SUCCESS); + } + DmiTable = AmdLateParamsPtr->DmiTable; + AcpiPstate = AmdLateParamsPtr->AcpiPState; + AcpiSrat = AmdLateParamsPtr->AcpiSrat; + AcpiSlit = AmdLateParamsPtr->AcpiSlit; + AcpiWheaMce = AmdLateParamsPtr->AcpiWheaMce; + AcpiWheaCmc = AmdLateParamsPtr->AcpiWheaCmc; + AcpiAlib = AmdLateParamsPtr->AcpiAlib; + + printk(BIOS_DEBUG, "In %s, AGESA generated ACPI tables:\n" + " DmiTable:%p\n AcpiPstate: %p\n AcpiSrat:%p\n AcpiSlit:%p\n" + " Mce:%p\n Cmc:%p\n Alib:%p\n", + __func__, DmiTable, AcpiPstate, AcpiSrat, AcpiSlit, + AcpiWheaMce, AcpiWheaCmc, AcpiAlib); + + /* Don't release the structure until coreboot has copied the ACPI tables. + * AmdReleaseStruct (&AmdLateParams); + */ + + return (UINT32)Status; +} + +UINT32 +agesawrapper_amdlaterunaptask ( + UINT32 Data, + VOID *ConfigPtr + ) +{ + AGESA_STATUS Status; + AMD_LATE_PARAMS AmdLateParams; + + LibAmdMemFill (&AmdLateParams, + 0, + sizeof (AMD_LATE_PARAMS), + &(AmdLateParams.StdHeader)); + + AmdLateParams.StdHeader.AltImageBasePtr = 0; + AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdLateParams.StdHeader.Func = 0; + AmdLateParams.StdHeader.ImageBasePtr = 0; + + Status = AmdLateRunApTask (&AmdLateParams); + if (Status != AGESA_SUCCESS) { + agesawrapper_amdreadeventlog(); + ASSERT(Status == AGESA_SUCCESS); + } + + return (UINT32)Status; +} + +UINT32 +agesawrapper_amdreadeventlog ( + VOID + ) +{ + AGESA_STATUS Status; + EVENT_PARAMS AmdEventParams; + + LibAmdMemFill (&AmdEventParams, + 0, + sizeof (EVENT_PARAMS), + &(AmdEventParams.StdHeader)); + + AmdEventParams.StdHeader.AltImageBasePtr = 0; + AmdEventParams.StdHeader.CalloutPtr = NULL; + AmdEventParams.StdHeader.Func = 0; + AmdEventParams.StdHeader.ImageBasePtr = 0; + Status = AmdReadEventLog (&AmdEventParams); + while (AmdEventParams.EventClass != 0) { + printk(BIOS_DEBUG,"\nEventLog: EventClass = %x, EventInfo = %x.\n",AmdEventParams.EventClass,AmdEventParams.EventInfo); + printk(BIOS_DEBUG," Param1 = %x, Param2 = %x.\n",AmdEventParams.DataParam1,AmdEventParams.DataParam2); + printk(BIOS_DEBUG," Param3 = %x, Param4 = %x.\n",AmdEventParams.DataParam3,AmdEventParams.DataParam4); + Status = AmdReadEventLog (&AmdEventParams); + } + + return (UINT32)Status; +} diff --git a/src/mainboard/amd/dinar/agesawrapper.h b/src/mainboard/amd/dinar/agesawrapper.h new file mode 100644 index 0000000..400e0c0 --- /dev/null +++ b/src/mainboard/amd/dinar/agesawrapper.h @@ -0,0 +1,329 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + + +#ifndef _AGESAWRAPPER_H_ +#define _AGESAWRAPPER_H_ + +#include <stdint.h> +#include "Porting.h" +#include "AGESA.h" + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +/* BITS Define */ +#ifndef BIT0 +#define BIT0 0x0000000000000001ull +#endif +#ifndef BIT1 +#define BIT1 0x0000000000000002ull +#endif +#ifndef BIT2 +#define BIT2 0x0000000000000004ull +#endif +#ifndef BIT3 +#define BIT3 0x0000000000000008ull +#endif +#ifndef BIT4 +#define BIT4 0x0000000000000010ull +#endif +#ifndef BIT5 +#define BIT5 0x0000000000000020ull +#endif +#ifndef BIT6 +#define BIT6 0x0000000000000040ull +#endif +#ifndef BIT7 +#define BIT7 0x0000000000000080ull +#endif +#ifndef BIT8 +#define BIT8 0x0000000000000100ull +#endif +#ifndef BIT9 +#define BIT9 0x0000000000000200ull +#endif +#ifndef BIT10 +#define BIT10 0x0000000000000400ull +#endif +#ifndef BIT11 +#define BIT11 0x0000000000000800ull +#endif +#ifndef BIT12 +#define BIT12 0x0000000000001000ull +#endif +#ifndef BIT13 +#define BIT13 0x0000000000002000ull +#endif +#ifndef BIT14 +#define BIT14 0x0000000000004000ull +#endif +#ifndef BIT15 +#define BIT15 0x0000000000008000ull +#endif +#ifndef BIT16 +#define BIT16 0x0000000000010000ull +#endif +#ifndef BIT17 +#define BIT17 0x0000000000020000ull +#endif +#ifndef BIT18 +#define BIT18 0x0000000000040000ull +#endif +#ifndef BIT19 +#define BIT19 0x0000000000080000ull +#endif +#ifndef BIT20 +#define BIT20 0x0000000000100000ull +#endif +#ifndef BIT21 +#define BIT21 0x0000000000200000ull +#endif +#ifndef BIT22 +#define BIT22 0x0000000000400000ull +#endif +#ifndef BIT23 +#define BIT23 0x0000000000800000ull +#endif +#ifndef BIT24 +#define BIT24 0x0000000001000000ull +#endif +#ifndef BIT25 +#define BIT25 0x0000000002000000ull +#endif +#ifndef BIT26 +#define BIT26 0x0000000004000000ull +#endif +#ifndef BIT27 +#define BIT27 0x0000000008000000ull +#endif +#ifndef BIT28 +#define BIT28 0x0000000010000000ull +#endif +#ifndef BIT29 +#define BIT29 0x0000000020000000ull +#endif +#ifndef BIT30 +#define BIT30 0x0000000040000000ull +#endif +#ifndef BIT31 +#define BIT31 0x0000000080000000ull +#endif +#ifndef BIT32 +#define BIT32 0x0000000100000000ull +#endif +#ifndef BIT33 +#define BIT33 0x0000000200000000ull +#endif +#ifndef BIT34 +#define BIT34 0x0000000400000000ull +#endif +#ifndef BIT35 +#define BIT35 0x0000000800000000ull +#endif +#ifndef BIT36 +#define BIT36 0x0000001000000000ull +#endif +#ifndef BIT37 +#define BIT37 0x0000002000000000ull +#endif +#ifndef BIT38 +#define BIT38 0x0000004000000000ull +#endif +#ifndef BIT39 +#define BIT39 0x0000008000000000ull +#endif +#ifndef BIT40 +#define BIT40 0x0000010000000000ull +#endif +#ifndef BIT41 +#define BIT41 0x0000020000000000ull +#endif +#ifndef BIT42 +#define BIT42 0x0000040000000000ull +#endif +#ifndef BIT43 +#define BIT43 0x0000080000000000ull +#endif +#ifndef BIT44 +#define BIT44 0x0000100000000000ull +#endif +#ifndef BIT45 +#define BIT45 0x0000200000000000ull +#endif +#ifndef BIT46 +#define BIT46 0x0000400000000000ull +#endif +#ifndef BIT47 +#define BIT47 0x0000800000000000ull +#endif +#ifndef BIT48 +#define BIT48 0x0001000000000000ull +#endif +#ifndef BIT49 +#define BIT49 0x0002000000000000ull +#endif +#ifndef BIT50 +#define BIT50 0x0004000000000000ull +#endif +#ifndef BIT51 +#define BIT51 0x0008000000000000ull +#endif +#ifndef BIT52 +#define BIT52 0x0010000000000000ull +#endif +#ifndef BIT53 +#define BIT53 0x0020000000000000ull +#endif +#ifndef BIT54 +#define BIT54 0x0040000000000000ull +#endif +#ifndef BIT55 +#define BIT55 0x0080000000000000ull +#endif +#ifndef BIT56 +#define BIT56 0x0100000000000000ull +#endif +#ifndef BIT57 +#define BIT57 0x0200000000000000ull +#endif +#ifndef BIT58 +#define BIT58 0x0400000000000000ull +#endif +#ifndef BIT59 +#define BIT59 0x0800000000000000ull +#endif +#ifndef BIT60 +#define BIT60 0x1000000000000000ull +#endif +#ifndef BIT61 +#define BIT61 0x2000000000000000ull +#endif +#ifndef BIT62 +#define BIT62 0x4000000000000000ull +#endif +#ifndef BIT63 +#define BIT63 0x8000000000000000ull +#endif +/* Define AMD Ontario APPU SSID/SVID */ +#define AMD_APU_SVID 0x1022 +#define AMD_APU_SSID 0x1234 +#define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS +#define MMIO_NP_BIT BIT7 + +/* Hudson-2 ACPI PmIO Space Define */ +#define SB_ACPI_BASE_ADDRESS 0x0400 +#define ACPI_MMIO_BASE 0xFED80000 +#define SB_CFG_BASE 0x000 // DWORD +#define GPIO_BASE 0x100 // BYTE +#define SMI_BASE 0x200 // DWORD +#define PMIO_BASE 0x300 // DWORD +#define PMIO2_BASE 0x400 // BYTE +#define BIOS_RAM_BASE 0x500 // BYTE +#define CMOS_RAM_BASE 0x600 // BYTE +#define CMOS_BASE 0x700 // BYTE +#define ASF_BASE 0x900 // DWORD +#define SMBUS_BASE 0xA00 // DWORD +#define WATCHDOG_BASE 0xB00 // ?? +#define HPET_BASE 0xC00 // DWORD +#define IOMUX_BASE 0xD00 // BYTE +#define MISC_BASE 0xE00 +#define SERIAL_DEBUG_BASE 0x1000 +#define GFX_DAC_BASE 0x1400 +#define CEC_BASE 0x1800 +#define XHCI_BASE 0x1C00 +#define ACPI_SMI_DATA_PORT 0xB1 +#define R_SB_ACPI_PM1_STATUS 0x00 +#define R_SB_ACPI_PM1_ENABLE 0x02 +#define R_SB_ACPI_PM_CONTROL 0x04 +#define R_SB_ACPI_EVENT_STATUS 0x20 +#define R_SB_ACPI_EVENT_ENABLE 0x24 +#define B_PWR_BTN_STATUS BIT8 +#define B_WAKEUP_STATUS BIT15 +#define B_SCI_EN BIT0 +#define SB_PM_INDEX_PORT 0xCD6 +#define SB_PM_DATA_PORT 0xCD7 +#define SB_PMIOA_REG24 0x24 // AcpiMmioEn +#define MmioAddress( BaseAddr, Register ) \ + ( (UINTN)BaseAddr + \ + (UINTN)(Register) \ + ) +#define Mmio32Ptr( BaseAddr, Register ) \ + ( (volatile UINT32 *)MmioAddress( BaseAddr, Register ) ) +#define Mmio32( BaseAddr, Register ) \ + *Mmio32Ptr( BaseAddr, Register ) + +enum { + PICK_DMI, /* DMI Interface */ + PICK_PSTATE, /* Acpi Pstate SSDT Table */ + PICK_SRAT, /* SRAT Table */ + PICK_SLIT, /* SLIT Table */ + PICK_WHEA_MCE, /* WHEA MCE table */ + PICK_WHEA_CMC, /* WHEA CMV table */ + PICK_ALIB, /* SACPI SSDT table with ALIB implementation */ +}; + + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +typedef struct { + UINT32 CalloutName; + AGESA_STATUS (*CalloutPtr) (UINT32 Func, UINT32 Data, VOID* ConfigPtr); +} BIOS_CALLOUT_STRUCT; + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*--------------------------------------------------------------------------------------- + * L O C A L F U N C T I O N S + *--------------------------------------------------------------------------------------- + */ + +//void brazos_platform_stage(void); +UINT32 agesawrapper_amdinitreset (void); +UINT32 agesawrapper_amdinitearly (void); +UINT32 agesawrapper_amdinitenv (void); +UINT32 agesawrapper_amdinitlate (void); +UINT32 agesawrapper_amdinitpost (void); +UINT32 agesawrapper_amdinitmid (void); +void sb_After_Pci_Init (void); +void sb_Mid_Post_Init (void); +void sb_Late_Post (void); +UINT32 agesawrapper_amdreadeventlog (void); +UINT32 agesawrapper_amdinitmmio (void); +void *agesawrapper_getlateinitptr (int pick); + +#endif diff --git a/src/mainboard/amd/dinar/buildOpts.c b/src/mainboard/amd/dinar/buildOpts.c new file mode 100644 index 0000000..fd0464d --- /dev/null +++ b/src/mainboard/amd/dinar/buildOpts.c @@ -0,0 +1,483 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/** + * @file + * + * AMD User options selection for a Sabine/Lynx platform solution system + * + * This file is placed in the user's platform directory and contains the + * build option selections desired for that platform. + * + * For Information about this file, see @ref platforminstall. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Core + * @e \$Revision: 6049 $ @e \$Date: 2008-05-14 01:58:02 -0500 (Wed, 14 May 2008) $ + */ +#include "AGESA.h" +#include "CommonReturns.h" +#include "Filecode.h" +#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE + + +/* Select the cpu family. */ + + +/* Select the cpu socket type. */ +#define INSTALL_G34_SOCKET_SUPPORT TURE +#define INSTALL_C32_SOCKET_SUPPORT FALSE +#define INSTALL_S1G3_SOCKET_SUPPORT FALSE +#define INSTALL_S1G4_SOCKET_SUPPORT FALSE +#define INSTALL_ASB2_SOCKET_SUPPORT FALSE +#define INSTALL_FS1_SOCKET_SUPPORT FALSE +#define INSTALL_FM1_SOCKET_SUPPORT FALSE +#define INSTALL_FP1_SOCKET_SUPPORT FALSE +#define INSTALL_FT1_SOCKET_SUPPORT FALSE +#define INSTALL_AM3_SOCKET_SUPPORT FALSE + +/* + * Agesa optional capabilities selection. + * Uncomment and mark FALSE those features you wish to include in the build. + * Comment out or mark TRUE those features you want to REMOVE from the build. + */ + +/* User makes option selections here + * Comment out the items wanted to be included in the build. + * Uncomment those items you with to REMOVE from the build. + */ +//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE +//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE +//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE +//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE +//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE +//#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE +#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE +//#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE +//#define BLDOPT_REMOVE_DDR3_SUPPORT TRUE +//#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE +//#define BLDOPT_REMOVE_ACPI_PSTATES TRUE +//#define BLDOPT_REMOVE_SRAT TRUE +//#define BLDOPT_REMOVE_SLIT TRUE +#define BLDOPT_REMOVE_WHEA TRUE +//#define BLDOPT_REMOVE_DMI TRUE +#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE +//#define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE +/* Build configuration values here. +*/ +#define BLDCFG_VRM_CURRENT_LIMIT 120000 +#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0 +#define BLDCFG_PLAT_NUM_IO_APICS 2 +#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST +#define BLDCFG_MEM_INIT_PSTATE 0 +#define BLDCFG_AMD_PSTATE_CAP_VALUE 0 + +#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_SERVER + +#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1600_FREQUENCY +#define BLDCFG_MEMORY_MODE_UNGANGED TRUE +#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE +#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED +#define BLDCFG_MEMORY_RDIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_SODIMM_CAPABLE FALSE +#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE +#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING TRUE +#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE +#define BLDCFG_MEMORY_POWER_DOWN TRUE +#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT //FALSE +#define BLDCFG_ONLINE_SPARE TRUE +#define BLDCFG_MEMORY_PARITY_ENABLE TRUE +#define BLDCFG_BANK_SWIZZLE TRUE +#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO +#define BLDCFG_MEMORY_CLOCK_SELECT DDR800_FREQUENCY +#define BLDCFG_DQS_TRAINING_CONTROL TRUE +#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE +#define BLDCFG_USE_BURST_MODE FALSE +#define BLDCFG_MEMORY_ALL_CLOCKS_ON TRUE +#define BLDCFG_ENABLE_ECC_FEATURE TRUE +#define BLDCFG_ECC_REDIRECTION TRUE +#define BLDCFG_SCRUB_IC_RATE 0 +#define BLDCFG_ECC_SYNC_FLOOD TRUE +#define BLDCFG_ECC_SYMBOL_SIZE 0 +#define BLDCFG_1GB_ALIGN FALSE +#define BLDCFG_PLATFORM_C1E_MODE C1eModeMsgBased +#define BLDCFG_PLATFORM_C1E_OPDATA 0x2000 +//#define BLDCFG_USE_ATM_MODE TRUE + +#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 +#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0xCB0 +#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance //BatteryLife +//#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeMsgBasedC1e +//#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x2000 + +//#define IDSOPT_IDS_ENABLED TRUE +#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE +#define BLDOPT_REMOVE_LOW_PWR_PSTATE_FOR_PROCHOT TRUE +#define BLDCFG_PSTATE_HPC_MODE FALSE + +#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST &MaranelloOverrideDevCap +/* + * Agesa entry points used in this implementation. + */ +/* Process the options... + * This file include MUST occur AFTER the user option selection settings + */ +#define AGESA_ENTRY_INIT_RESET TRUE//FALSE +#define AGESA_ENTRY_INIT_RECOVERY FALSE +#define AGESA_ENTRY_INIT_EARLY TRUE +#define AGESA_ENTRY_INIT_POST TRUE +#define AGESA_ENTRY_INIT_ENV TRUE +#define AGESA_ENTRY_INIT_MID TRUE +#define AGESA_ENTRY_INIT_LATE TRUE +#define AGESA_ENTRY_INIT_S3SAVE TRUE +#define AGESA_ENTRY_INIT_RESUME TRUE +#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE +#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE +#define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE + + +/***************************************************************************** + * Define the RELEASE VERSION string + * + * The Release Version string should identify the next planned release. + * When a branch is made in preparation for a release, the release manager + * should change/confirm that the branch version of this file contains the + * string matching the desired version for the release. The trunk version of + * the file should always contain a trailing 'X'. This will make sure that a + * development build from trunk will not be confused for a released version. + * The release manager will need to remove the trailing 'X' and update the + * version string as appropriate for the release. The trunk copy of this file + * should also be updated/incremented for the next expected version, + trailing 'X' + ****************************************************************************/ +// This is the delivery package title, "MarG34PI" +// This string MUST be exactly 8 characters long +#define AGESA_PACKAGE_STRING {'O', 'r', 'o', 'c', 'h', 'i', 'P', 'I'} + +// This is the release version number of the AGESA component +// This string MUST be exactly 12 characters long +#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '9', '.', '0', ' ', ' ', ' ', ' '} + +// The Maranello solution is defined to be families 0x10 and 0x15 models 0x0 - 0xF in the G34 socket. +#define INSTALL_G34_SOCKET_SUPPORT TRUE +#define INSTALL_FAMILY_10_SUPPORT TRUE +#define INSTALL_FAMILY_15_MODEL_0x_SUPPORT TRUE + +#ifdef BLDOPT_REMOVE_FAMILY_10_SUPPORT +#if BLDOPT_REMOVE_FAMILY_10_SUPPORT == TRUE +#undef INSTALL_FAMILY_10_SUPPORT +#define INSTALL_FAMILY_10_SUPPORT FALSE +#endif +#endif + +#ifdef BLDOPT_REMOVE_FAMILY_15_SUPPORT +#if BLDOPT_REMOVE_FAMILY_15_SUPPORT == TRUE +#undef INSTALL_FAMILY_15_MODEL_0x_SUPPORT +#define INSTALL_FAMILY_15_MODEL_0x_SUPPORT FALSE +#endif +#endif + +// The following definitions specify the default values for various parameters in which there are +// no clearly defined defaults to be used in the common file. The values below are based on product +// and BKDG content, please consult the AGESA Memory team for consultation. +#define DFLT_SCRUB_DRAM_RATE (0xFF) +#define DFLT_SCRUB_L2_RATE (0x10) +#define DFLT_SCRUB_L3_RATE (0x10) +#define DFLT_SCRUB_IC_RATE (0) +#define DFLT_SCRUB_DC_RATE (0x12) +#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED +#define DFLT_VRM_SLEW_RATE (2500) + +/* Process the options... + * This file include MUST occur + AFTER the user option selection settings + */ +CONST MANUAL_BUID_SWAP_LIST ROMDATA MaranelloManualBuidSwapList[2] = +{ + HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, + 0, 0, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF +}; + +#define BLDCFG_BUID_SWAP_LIST &MaranelloManualBuidSwapList + +// And another platform specific one ... +//CONST CPU_TO_CPU_PCB_LIMITS ROMDATA MaranelloCpuToCpuLimitList[2] = +//{ +// HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, +// HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_3200M, +// HT_LIST_TERMINAL +//}; + +CONST CPU_TO_CPU_PCB_LIMITS ROMDATA MaranelloCpuToCpuLimitList[] = +{ + HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, + HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_2600M, + HT_LIST_MATCH_ANY, HT_LIST_MATCH_INTERNAL_LINK, HT_LIST_MATCH_ANY, HT_LIST_MATCH_INTERNAL_LINK, + HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_2600M, + HT_LIST_TERMINAL +}; + +#define BLDCFG_HTFABRIC_LIMITS_LIST &MaranelloCpuToCpuLimitList + +// A performance-per-watt optimization. +CONST SKIP_REGANG ROMDATA PerfPerWatt[] = { + HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, POWERED_OFF, + HT_LIST_MATCH_ANY, HT_LIST_MATCH_INTERNAL_LINK, HT_LIST_MATCH_ANY, HT_LIST_MATCH_INTERNAL_LINK, POWERED_OFF, + HT_LIST_TERMINAL, +}; + +// uncomment the line below to make Perf-per-watt enabled by default. +#define BLDCFG_LINK_SKIP_REGANG_LIST &PerfPerWatt + + +CONST IO_PCB_LIMITS ROMDATA MaranelloIoLimitList[2] = +{ + HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_2600M, + HT_LIST_TERMINAL +}; + +#define BLDCFG_HTCHAIN_LIMITS_LIST &MaranelloIoLimitList + +CONST SYSTEM_PHYSICAL_SOCKET_MAP ROMDATA DinarPhysicalSocketMap[] = +{ + // Source Socket, Link (4-7 are sublink 1), Target Socket + {0, 0, 1}, + {0, 1, 1}, + {0, 3, 1}, + {0, 4, 1}, + {0, 5, 1}, + {0, 7, 1}, +}; + +#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP &DinarPhysicalSocketMap + +/* + * PCI Bus numbers for Drachma/Peso board + */ +CONST OVERRIDE_BUS_NUMBERS ROMDATA MaranelloOverrideBusNumbers[5] = +{ + // Socket, Link, SecBus, SubBus + 0, 2, 0x00, 0xBF, // RD890 of Dinar + 1, 0, 0xC0, 0xFF, // HTX + HT_LIST_TERMINAL +}; + +#define BLDCFG_BUS_NUMBERS_LIST &MaranelloOverrideBusNumbers + +CONST CPU_HT_DEEMPHASIS_LEVEL ROMDATA DinarDeemphasisList[] = +{ + { HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_200M, HT_FREQUENCY_1800M, DeemphasisLevelNone, DcvLevelNone}, + { HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_2000M, HT_FREQUENCY_2600M, DeemphasisLevelMinus3, DcvLevelMinus3}, + { HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_2800M, HT_FREQUENCY_MAX, DeemphasisLevelMinus6, DcvLevelMinus6}, + 0xFF +}; + +#define BLDCFG_PLATFORM_DEEMPHASIS_LIST DinarDeemphasisList +/* + CONST SKIP_REGANG ROMDATA DinarSkipRegangMap[] = + { +// {socketA, linkA, socketB, linkB} +{0, 0, 1, 1}, +}; + +#define BLDCFG_LINK_SKIP_REGANG_LIST &DinarSkipRegangMap +*/ + +/* + * Device Capabilities Override for disabling ID Clumping + */ +CONST DEVICE_CAP_OVERRIDE ROMDATA MaranelloOverrideDevCap[2] = +{ + HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, + 0, 0, HT_LIST_MATCH_ANY, {0, 0, 0, 0, 0, 1, 0}, 0, 0, 0, 0, {0}, + HT_LIST_TERMINAL +}; + +#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST &MaranelloOverrideDevCap + + +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "AdvancedApi.h" +#include "heapManager.h" +#include "CreateStruct.h" +#include "cpuFeatures.h" +#include "Table.h" +#include "CommonReturns.h" +#include "cpuEarlyInit.h" +#include "cpuLateInit.h" +#include "GnbInterfaceStub.h" +#include "PlatformInstall.h" + +/*---------------------------------------------------------------------------------------- + * CUSTOMER OVERIDES MEMORY TABLE + *---------------------------------------------------------------------------------------- + */ + +/* + * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA + * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable + * is populated, AGESA will base its settings on the data from the table. Otherwise, it will + * use its default conservative settings. + */ +CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { + // + // The following macros are supported (use comma to separate macros): + // + // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap) + // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap. + // AGESA will base on this value to disable unused MemClk to save power. + // Example: + // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below: + // Bit AM3/S1g3 pin name + // 0 M[B,A]_CLK_H/L[0] + // 1 M[B,A]_CLK_H/L[1] + // 2 M[B,A]_CLK_H/L[2] + // 3 M[B,A]_CLK_H/L[3] + // 4 M[B,A]_CLK_H/L[4] + // 5 M[B,A]_CLK_H/L[5] + // 6 M[B,A]_CLK_H/L[6] + // 7 M[B,A]_CLK_H/L[7] + // And platform has the following routing: + // CS0 M[B,A]_CLK_H/L[4] + // CS1 M[B,A]_CLK_H/L[2] + // CS2 M[B,A]_CLK_H/L[3] + // CS3 M[B,A]_CLK_H/L[5] + // Then platform can specify the following macro: + // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00) + // + // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap) + // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap. + // AGESA will base on this value to tristate unused CKE to save power. + // + // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap) + // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap. + // AGESA will base on this value to tristate unused ODT pins to save power. + // + // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap) + // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap. + // AGESA will base on this value to tristate unused Chip select to save power. + // + // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel) + // Specifies the number of DIMM slots per channel. + // + // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket) + // Specifies the number of channels per socket. + // + + // Dinar has the following routing: + // CS0 M[B,A]_CLK_H/L[0] + // CS1 M[B,A]_CLK_H/L[2] + // CS2 M[B,A]_CLK_H/L[1] + // CS3 M[B,A]_CLK_H/L[3] + MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x01, 0x04, 0x02, 0x08, 0x00, 0x00), + NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), + PSO_END +}; + +/* + * These tables are optional and may be used to adjust memory timing settings + */ +#include "mm.h" +#include "mn.h" + +//HY Customer table +UINT8 AGESA_MEM_TABLE_HY[][sizeof(MEM_TABLE_ALIAS)] = +{ + // Hardcoded Memory Training Values + + // The following macro should be used to override training values for your platform + // + // DQSACCESS(MTAfterDqsRwPosTrn, MTNodes, MTDcts, MTDIMMs, BFRdDqsDly, MTOverride, 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x1c, 0x20), + // + // NOTE: + // The following training hardcode values are example values that were taken from a tilapia motherboard + // with a particular DIMM configuration. To harcode your own values, uncomment the appropriate line in + // the table and replace the byte lane values with your own. + // + // ------------------ BYTE LANES ---------------------- + // BL0 BL1 BL2 BL3 BL4 BL5 BL6 Bl7 ECC + // Write Data Timing + // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM0, BFWrDatDly, MTOverride, 0x1D, 0x20, 0x26, 0x2B, 0x37, 0x3A, 0x3e, 0x3F, 0x30),// DCT0, DIMM0 + // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM1, BFWrDatDly, MTOverride, 0x1D, 0x00, 0x06, 0x0B, 0x17, 0x1A, 0x1E, 0x1F, 0x10),// DCT0, DIMM1 + // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM0, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x27, 0x2B, 0x3B, 0x3B, 0x3E, 0x3E, 0x30),// DCT1, DIMM0 + // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM1, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x1C, 0x0B, 0x17, 0x1A, 0x1D, 0x1C, 0x10),// DCT1, DIMM1 + + // DQS Receiver Enable + // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0 + // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM1, BFRcvEnDly, MTOverride, 0x7C, 0x7D, 0x7E, 0x81, 0x88, 0x8F, 0x96, 0x9F, 0x84),// DCT0, DIMM1 + // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT1, DIMM0 + // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM1, BFRcvEnDly, MTOverride, 0x1C, 0x1D, 0x1E, 0x01, 0x08, 0x0F, 0x16, 0x1F, 0x04),// DCT1, DIMM1 + + // Write DQS Delays + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFWrDqsDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFWrDqsDly, MTOverride, 0x06, 0x0D, 0x12, 0x1A, 0x25, 0x28, 0x2C, 0x2C, 0x44),// DCT0, DIMM1 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFWrDqsDly, MTOverride, 0x07, 0x0E, 0x14, 0x1B, 0x24, 0x29, 0x2B, 0x2C, 0x1F),// DCT1, DIMM0 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFWrDqsDly, MTOverride, 0x07, 0x0C, 0x14, 0x19, 0x25, 0x28, 0x2B, 0x2B, 0x1A),// DCT1, DIMM1 + + // Read DQS Delays + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x0E, 0x10),// DCT0, DIMM0 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT0, DIMM1 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM0 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM1 + //-------------------------------------------------------------------------------------------------------------------------------------------------- + // TABLE END + NBACCESS (MTEnd, 0, 0, 0, 0, 0), // End of Table +}; +UINT8 SizeOfTableHy = sizeof (AGESA_MEM_TABLE_HY) / sizeof (AGESA_MEM_TABLE_HY[0]); +/* *************************************************************************** + * Optional User code to be included into the AGESA build + * These may be 32-bit call-out routines... + */ +//AGESA_STATUS +//AgesaReadSpd ( +// IN UINTN FcnData, +// IN OUT AGESA_READ_SPD_PARAMS *ReadSpd +// ) +//{ +// /* platform code to read an SPD... */ +// return Status; +//} + +/* *************************************************************************** + * Optional User code to be included into the AGESA build + * These may be 32-bit call-out routines... + */ +//AGESA_STATUS +//AgesaReadSpd ( +// IN UINTN FcnData, +// IN OUT AGESA_READ_SPD_PARAMS *ReadSpd +// ) +//{ +// /* platform code to read an SPD... */ +// return Status; +//} + + diff --git a/src/mainboard/amd/dinar/chip.h b/src/mainboard/amd/dinar/chip.h new file mode 100644 index 0000000..42630fa --- /dev/null +++ b/src/mainboard/amd/dinar/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/amd/dinar/cmos.layout b/src/mainboard/amd/dinar/cmos.layout new file mode 100644 index 0000000..5178430 --- /dev/null +++ b/src/mainboard/amd/dinar/cmos.layout @@ -0,0 +1,118 @@ +#***************************************************************************** +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +#***************************************************************************** + +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 amd_reserved + + + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% + +checksums + +checksum 392 983 984 + + diff --git a/src/mainboard/amd/dinar/devicetree.cb b/src/mainboard/amd/dinar/devicetree.cb new file mode 100644 index 0000000..92fe521 --- /dev/null +++ b/src/mainboard/amd/dinar/devicetree.cb @@ -0,0 +1,104 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +chip northbridge/amd/agesa/family15/root_complex + device lapic_cluster 0 on + chip cpu/amd/agesa/family15 + device lapic 0x20 on end + end + end + device pci_domain 0 on + subsystemid 0x1022 0x1705 inherit + chip northbridge/amd/agesa/family15 # CPU side of HT root complex + device pci 18.0 on end # Link 0 + device pci 18.0 on # Link 1, IO-HUB on socket0 link 2(internal Node0 Link 1) + chip northbridge/amd/cimx/rd890 # North Bridge PCI side of HT Root complex + device pci 0.0 on end # HT Root Complex + device pci 0.1 off end # CLKCONFIG + device pci 2.0 on end # GPP1 Port0 + device pci 3.0 off end # GPP1 Port1 + device pci 4.0 off end # GPP3a Port0 + device pci 5.0 off end # GPP3a Port1 + device pci 6.0 off end # GPP3a Port2 + device pci 7.0 off end # GPP3a Port3 + device pci 8.0 off end # NB/SB Link P2P bridge, should be hidden at boot time + device pci 9.0 off end # GPP3a Port4 + device pci a.0 off end # GPP3a Port5 + device pci b.0 off end # GPP2 Port0 (Not for sr5650) + device pci c.0 off end # GPP2 Port1 (Not for sr5650/sr5670) + device pci d.0 on end # GPP3b Port0 (Not for sr5650/sr5670) 0x5A1E, Intel 82576 + register "gpp1_configuration" = "0" # Configuration 16:0 default + register "gpp2_configuration" = "1" # Configuration 8:8 + register "gpp3a_configuration" = "2" # 2 Configuration 4:1:1:0:0:0, 11 Configuration 1:1:1:1:1:1 + register "port_enable" = "0x2104" + end # northbridge/amd/cimx/rd890 + chip southbridge/amd/cimx/sb700 # it is under NB/SB Link, but on the same pri bus + device pci 11.0 on end # SATA + device pci 12.0 on end # USB1 + device pci 12.1 on end # USB1 + device pci 12.2 on end # USB1 + device pci 13.0 on end # USB2 + device pci 13.1 on end # USB2 + device pci 13.2 on end # USB2 + device pci 14.0 on # SM + end # SM + device pci 14.1 off end # IDE 0x439c + device pci 14.2 off end # HDA 0x4383 + device pci 14.3 on # LPC + chip superio/smsc/sch4037 # SIO SMSC SCH4037 + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + irq 0x74 = 2 + end + device pnp 2e.3 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + irq 0x74 = 4 + end + device pnp 2e.4 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.5 on # COM2 / IR + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.7 on # PS/2 keyboard / mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # PS/2 keyboard interrupt + irq 0x72 = 12 # PS/2 mouse interrupt + end + end #SIO SMSC307 + end #LPC + device pci 14.4 on end # PCI bridge, 0x4384 + device pci 14.5 on end # USB 3 + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + end #southbridge/amd/cimx/sb700 + end # device pci 18.0 + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + end #chip northbridge/amd/agesa/family15 # CPU side of HT root complex + end #pci_domain +end #northbridge/amd/agesa/family15/root_complex + diff --git a/src/mainboard/amd/dinar/dimmSpd.c b/src/mainboard/amd/dinar/dimmSpd.c new file mode 100644 index 0000000..f26ec20 --- /dev/null +++ b/src/mainboard/amd/dinar/dimmSpd.c @@ -0,0 +1,333 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#include "Porting.h" +#include "AGESA.h" +#include "amdlib.h" + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +#define SMBUS_BASE_ADDR 0xB00 +#define DIMENSION(array)(sizeof (array)/ sizeof (array [0])) + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ +#define LTC4305_SMBUS_ADDR 0x94 + +typedef struct _DIMM_INFO_SMBUS{ + UINT8 SocketId; + UINT8 MemChannelId; + UINT8 DimmId; + UINT8 SmbusAddress; +} DIMM_INFO_SMBUS; +/* + * SPD address table - porting required + */ +STATIC CONST DIMM_INFO_SMBUS SpdAddrLookup [] = +{ + /* Socket, Channel, Dimm, Smbus */ + {0, 0, 0, 0xAC}, + {0, 0, 1, 0xAE}, + {0, 1, 0, 0xA8}, + {0, 1, 1, 0xAA}, + {0, 2, 0, 0xA4}, + {0, 2, 1, 0xA6}, + {0, 3, 0, 0xA0}, + {0, 3, 1, 0xA2}, + {1, 0, 0, 0xAC}, + {1, 0, 1, 0xAE}, + {1, 1, 0, 0xA8}, + {1, 1, 1, 0xAA}, + {1, 2, 0, 0xA4}, + {1, 2, 1, 0xA6}, + {1, 3, 0, 0xA0}, + {1, 3, 1, 0xA2} +}; + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +AGESA_STATUS +AmdMemoryReadSPD ( + IN UINT32 Func, + IN UINT32 Data, + IN OUT AGESA_READ_SPD_PARAMS *SpdData + ); + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +/*--------------------------------------------------------------------------------------- + * L O C A L F U N C T I O N S + *--------------------------------------------------------------------------------------- + */ + +STATIC +VOID +WritePmReg ( + IN UINT8 Reg, + IN UINT8 Data + ) +{ + __outbyte (0xCD6, Reg); + __outbyte (0xCD7, Data); +} +STATIC +VOID +SetupFch ( + IN UINT16 + IN IoBase + ) +{ + + AMD_CONFIG_PARAMS StdHeader; + UINT32 PciData32; + UINT8 PciData8; + PCI_ADDR PciAddress; + + /* Set SMBUS MMIO. */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 20, 0, 0x90); + PciData32 = (SMBUS_BASE_ADDR & 0xFFFFFFF0) | BIT0; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData32, &StdHeader); + + /* Enable SMBUS MMIO. */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 20, 0, 0xD2); + LibAmdPciRead(AccessWidth8, PciAddress, &PciData8, &StdHeader); ; + PciData8 |= BIT0; + LibAmdPciWrite(AccessWidth8, PciAddress, &PciData8, &StdHeader); + /* set SMBus clock to 400 KHz */ + __outbyte (IoBase + 0x0E, 66000000 / 400000 / 4); +} + +/* + * + * ReadSmbusByteData - read a single SPD byte from any offset + * + */ + +STATIC +AGESA_STATUS +ReadSmbusByteData ( + IN UINT16 Iobase, + IN UINT8 Address, + OUT UINT8 *ByteData, + IN UINTN Offset + ) +{ + UINTN Status; + UINT64 Limit; + + Address |= 1; // set read bit + + __outbyte (Iobase + 0, 0xFF); // clear error status + __outbyte (Iobase + 1, 0x1F); // clear error status + __outbyte (Iobase + 3, Offset); // offset in eeprom + __outbyte (Iobase + 4, Address); // slave address and read bit + __outbyte (Iobase + 2, 0x48); // read byte command + + /* time limit to avoid hanging for unexpected error status (should never happen) */ + Limit = __rdtsc () + 2000000000 / 10; + for (;;) { + Status = __inbyte (Iobase); + if (__rdtsc () > Limit) break; + if ((Status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting + if ((Status & 1) == 1) continue; // HostBusy set, keep waiting + break; + } + + *ByteData = __inbyte (Iobase + 5); + if (Status == 2) Status = 0; // check for done with no errors + return Status; +} +/* + * + * WriteSmbusByteData - Write a single SPD byte onto any offset + * + */ +STATIC +AGESA_STATUS +WriteSmbusByteData ( + IN UINT16 Iobase, + IN UINT8 Address, + IN UINT8 ByteData, + IN UINTN Offset + ) +{ + UINTN Status; + UINT64 Limit; + Address &= 0xFE; // set write bit + + __outbyte (Iobase + 0, 0xFF); // clear error status + __outbyte (Iobase + 1, 0x1F); // clear error status + __outbyte (Iobase + 3, Offset); // offset in eeprom + __outbyte (Iobase + 4, Address); // slave address and write bit + __outbyte (Iobase + 5, ByteData); // offset in byte data // + __outbyte (Iobase + 2, 0x48); // write byte command + /* time limit to avoid hanging for unexpected error status (should never happen) */ + Limit = __rdtsc () + 2000000000 / 10; + for (;;) { + Status = __inbyte (Iobase); + if (__rdtsc () > Limit) break; + if ((Status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting + if ((Status & 1) == 1) continue; // HostBusy set, keep waiting + break; + } + if (Status == 2) Status = 0; // check for done with no errors + return Status; +} + +/* + * + * ReadSmbusByte - read a single SPD byte from the default offset + * this function is faster function readSmbusByteData + * + */ + +STATIC +AGESA_STATUS +ReadSmbusByte ( + IN UINT16 Iobase, + IN UINT8 Address, + OUT UINT8 *Buffer + ) +{ + UINTN Status; + UINT64 Limit; + + __outbyte (Iobase + 0, 0xFF); // clear error status + __outbyte (Iobase + 1, 0x1F); // clear error status + __outbyte (Iobase + 2, 0x44); // read command + + // time limit to avoid hanging for unexpected error status + Limit = __rdtsc () + 2000000000 / 10; + for (;;) { + Status = __inbyte (Iobase); + if (__rdtsc () > Limit) break; + if ((Status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting + if ((Status & 1) == 1) continue; // HostBusy set, keep waiting + break; + } + + Buffer [0] = __inbyte (Iobase + 5); + if (Status == 2) Status = 0; // check for done with no errors + return Status; +} + +/* + * + * ReadSpd - Read one or more SPD bytes from a DIMM. + * Start with offset zero and read sequentially. + * Optimization relies on autoincrement to avoid + * sending offset for every byte. + * Reads 128 bytes in 7-8 ms at 400 KHz. + * + */ + +STATIC +AGESA_STATUS +ReadSpd ( + IN UINT16 IoBase, + IN UINT8 SmbusSlaveAddress, + OUT UINT8 *Buffer, + IN UINTN Count + ) +{ + UINTN Index, Status; + + /* read the first byte using offset zero */ + Status = ReadSmbusByteData (IoBase, SmbusSlaveAddress, Buffer, 0); + if (Status) return Status; + + /* read the remaining bytes using auto-increment for speed */ + for (Index = 1; Index < Count; Index++){ + Status = ReadSmbusByte (IoBase, SmbusSlaveAddress, &Buffer [Index]); + if (Status) return Status; + } + return 0; +} + +AGESA_STATUS +AmdMemoryReadSPD ( + IN UINT32 Func, + IN UINT32 Data, + IN OUT AGESA_READ_SPD_PARAMS *SpdData + ) +{ + AGESA_STATUS Status; + UINT8 SmBusAddress = 0; + UINTN Index; + UINTN MaxSocket = DIMENSION (SpdAddrLookup); + + for (Index = 0; Index < MaxSocket; Index ++){ + if ((SpdData->SocketId == SpdAddrLookup[Index].SocketId) && + (SpdData->MemChannelId == SpdAddrLookup[Index].MemChannelId) && + (SpdData->DimmId == SpdAddrLookup[Index].DimmId)) { + SmBusAddress = SpdAddrLookup[Index].SmbusAddress; + break; + } + } + + + if (SmBusAddress == 0) return AGESA_ERROR; + + SetupFch (SMBUS_BASE_ADDR); + + Status = WriteSmbusByteData (SMBUS_BASE_ADDR, LTC4305_SMBUS_ADDR, 0x80, 0x03); + + switch (SpdData->SocketId) { + case 0: + /* Switch onto the First CPU Socket SMBUS */ + WriteSmbusByteData (SMBUS_BASE_ADDR, LTC4305_SMBUS_ADDR, 0x80, 0x03); + break; + case 1: + /* Switch onto the Second CPU Socket SMBUS */ + WriteSmbusByteData (SMBUS_BASE_ADDR, LTC4305_SMBUS_ADDR, 0x40, 0x03); + break; + default: + /* Switch off two CPU Sockets SMBUS */ + WriteSmbusByteData (SMBUS_BASE_ADDR, LTC4305_SMBUS_ADDR, 0x00, 0x03); + break; + } + Status = ReadSpd (SMBUS_BASE_ADDR, SmBusAddress, SpdData->Buffer, 256); + + /*Output SPD Debug Message*/ + printk(BIOS_EMERG, "file '%s',line %d, %s()\n", __FILE__, __LINE__, __func__); + printk(BIOS_DEBUG, " Status = %d\n",Status); + printk(BIOS_DEBUG, "SocketId MemChannelId SpdData->DimmId SmBusAddress Buffer\n"); + printk(BIOS_DEBUG, "%x, %x, %x, %x, %x\n", SpdData->SocketId, SpdData->MemChannelId, SpdData->DimmId, SmBusAddress, SpdData->Buffer); + + /* Switch off two CPU Sockets SMBUS */ + WriteSmbusByteData (SMBUS_BASE_ADDR, LTC4305_SMBUS_ADDR, 0x00, 0x03); + return Status; +} diff --git a/src/mainboard/amd/dinar/dsdt.asl b/src/mainboard/amd/dinar/dsdt.asl new file mode 100644 index 0000000..0cbffb7 --- /dev/null +++ b/src/mainboard/amd/dinar/dsdt.asl @@ -0,0 +1,1157 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* DefinitionBlock Statement */ +DefinitionBlock ( + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ + 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + "AMD ", /* OEMID */ + "DINAR ", /* TABLE ID */ + 0x00010001 /* OEM Revision */ + ) +{ /* Start of ASL file */ + /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + + /* Data to be patched by the BIOS during POST */ + /* FIXME the patching is not done yet! */ + /* Memory related values */ + Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ + Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ + Name(PBLN, 0x0) /* Length of BIOS area */ + + Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ + Name(HPBA, 0xFED00000) /* Base address of HPET table */ + + Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ + + /* Some global data */ + Name(OSV, Ones) /* Assume nothing */ + Name(GPIC, 0x1) /* Assume PIC */ + + /* + * Processor Object + * + */ + Scope (\_PR) { /* define processor scope */ + Processor( + CPU0, /* name space name */ + 0, /* Unique number for this processor */ + 0x810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + #include "acpi/cpstate.asl" + } + Processor( + CPU1, /* name space name */ + 1, /* Unique number for this processor */ + 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + #include "acpi/cpstate.asl" + } + Processor( + CPU2, /* name space name */ + 2, /* Unique number for this processor */ + 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + #include "acpi/cpstate.asl" + } + Processor( + CPU3, /* name space name */ + 3, /* Unique number for this processor */ + 0x0000, /* PBLK system I/O address !hardcoded! */ + 0x00 /* PBLKLEN for boot processor */ + ) { + #include "acpi/cpstate.asl" + } + } /* End _PR scope */ + + /* PIC IRQ mapping registers, C00h-C01h. */ + OperationRegion(PIRQ, SystemIO, 0x00000C00, 0x00000002) + Field(PIRQ, ByteAcc, NoLock, Preserve) { + PIDX, 0x00000008, + PDAT, 0x00000008, /* Offset: 1h */ + } + IndexField(PIDX, PDAT, ByteAcc, NoLock, Preserve) { + PIRA, 0x00000008, /* Index 0 */ + PIRB, 0x00000008, /* Index 1 */ + PIRC, 0x00000008, /* Index 2 */ + PIRD, 0x00000008, /* Index 3 */ + PIRE, 0x00000008, /* Index 4 */ + PIRF, 0x00000008, /* Index 5 */ + PIRG, 0x00000008, /* Index 6 */ + PIRH, 0x00000008, /* Index 7 */ + Offset(0x10), + PIRS, 0x00000008, + Offset(0x13), + HDAD, 0x00000008, + , 0x00000008, + GEC, 0x00000008, + Offset(0x30), + USB1, 0x00000008, + USB2, 0x00000008, + USB3, 0x00000008, + USB4, 0x00000008, + USB5, 0x00000008, + USB6, 0x00000008, + USB7, 0x00000008, + Offset(0x40), + IDE, 0x00000008, + SATA, 0x00000008, + Offset(0x50), + GPP0, 0x00000008, + GPP1, 0x00000008, + GPP2, 0x00000008, + GPP3, 0x00000008 + } + + /* PCI Error control register */ + OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001) + Field(PERC, ByteAcc, NoLock, Preserve) { + SENS, 0x00000001, + PENS, 0x00000001, + SENE, 0x00000001, + PENE, 0x00000001, + } + + /* Client Management index/data registers */ + OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) + Field(CMT, ByteAcc, NoLock, Preserve) { + CMTI, 8, + /* Client Management Data register */ + G64E, 1, + G64O, 1, + G32O, 2, + , 2, + GPSL, 2, + } + + /* GPM Port register */ + OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001) + Field(GPT, ByteAcc, NoLock, Preserve) { + GPB0,1, + GPB1,1, + GPB2,1, + GPB3,1, + GPB4,1, + GPB5,1, + GPB6,1, + GPB7,1, + } + + /* Flash ROM program enable register */ + OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) + Field(FRE, ByteAcc, NoLock, Preserve) { + , 0x00000006, + FLRE, 0x00000001, + } + + /* PM2 index/data registers */ + OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002) + Field(PM2R, ByteAcc, NoLock, Preserve) { + PM2I, 0x00000008, + PM2D, 0x00000008, + } + + /* Power Management I/O registers, TODO:PMIO is quite different in SB700. */ + OperationRegion(PMRG, SystemIO, 0x00000CD6, 0x00000002) + Field(PMRG, ByteAcc, NoLock, Preserve) { + PMRI, 0x00000008, + PMRD, 0x00000008, + } + IndexField (PMRI, PMRD, ByteAcc, NoLock, Preserve) { + Offset(0x24), + MMSO,32, + Offset(0x37), /* GPMLevelConfig0 */ + , 3, + PLC0, 1, + PLC1, 1, + PLC2, 1, + PLC3, 1, + PLC8, 1, + Offset(0x38), /* GPMLevelConfig1 */ + , 1, + PLC4, 1, + PLC5, 1, + , 1, + PLC6, 1, + PLC7, 1, + Offset(0x50), + HPAD,32, + Offset(0x60), + P1EB,16, + Offset(0x65), /* UsbPMControl */ + , 4, + URRE, 1, + Offset(0x96), /* GPM98IN */ + G8IS, 1, + G9IS, 1, + Offset(0x9A), /* EnhanceControl */ + ,7, + HPDE, 1, + Offset(0xC8), + ,2, + SPRE,1, + TPDE,1, + Offset(0xF0), + ,3, + RSTU,1 + } + + /* PM1 Event Block + * First word is PM1_Status, Second word is PM1_Enable + */ + OperationRegion(P1E0, SystemIO, P1EB, 0x04) + Field(P1E0, ByteAcc, NoLock, Preserve) { + ,14, + PEWS,1, + WSTA,1, + ,14, + PEWD,1 + } + + OperationRegion (GRAM, SystemMemory, 0x0400, 0x0100) + Field (GRAM, ByteAcc, Lock, Preserve) + { + Offset (0x10), + FLG0, 8 + } + + Scope(\_SB) { + /* PCIe Configuration Space for 16 busses */ + OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */ + Field(PCFG, ByteAcc, NoLock, Preserve) { + /* Byte offsets are computed using the following technique: + * ((bus number + 1) * ((device number * 8) * 4096)) + register offset + * The 8 comes from 8 functions per device, and 4096 bytes per function config space + */ + Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */ + STB5, 32, + Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */ + PT0D, 1, + PT1D, 1, + PT2D, 1, + PT3D, 1, + PT4D, 1, + PT5D, 1, + PT6D, 1, + PT7D, 1, + PT8D, 1, + PT9D, 1, + Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */ + SBIE, 1, + SBME, 1, + Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */ + SBRI, 8, + Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */ + SBB1, 32, + Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */ + ,14, + P92E, 1, /* Port92 decode enable */ + } + + OperationRegion(SB5, SystemMemory, STB5, 0x1000) + Field(SB5, AnyAcc, NoLock, Preserve){ + /* Port 0 */ + Offset(0x120), /* Port 0 Task file status */ + P0ER, 1, + , 2, + P0DQ, 1, + , 3, + P0BY, 1, + Offset(0x128), /* Port 0 Serial ATA status */ + P0DD, 4, + , 4, + P0IS, 4, + Offset(0x12C), /* Port 0 Serial ATA control */ + P0DI, 4, + Offset(0x130), /* Port 0 Serial ATA error */ + , 16, + P0PR, 1, + + /* Port 1 */ + offset(0x1A0), /* Port 1 Task file status */ + P1ER, 1, + , 2, + P1DQ, 1, + , 3, + P1BY, 1, + Offset(0x1A8), /* Port 1 Serial ATA status */ + P1DD, 4, + , 4, + P1IS, 4, + Offset(0x1AC), /* Port 1 Serial ATA control */ + P1DI, 4, + Offset(0x1B0), /* Port 1 Serial ATA error */ + , 16, + P1PR, 1, + + /* Port 2 */ + Offset(0x220), /* Port 2 Task file status */ + P2ER, 1, + , 2, + P2DQ, 1, + , 3, + P2BY, 1, + Offset(0x228), /* Port 2 Serial ATA status */ + P2DD, 4, + , 4, + P2IS, 4, + Offset(0x22C), /* Port 2 Serial ATA control */ + P2DI, 4, + Offset(0x230), /* Port 2 Serial ATA error */ + , 16, + P2PR, 1, + + /* Port 3 */ + Offset(0x2A0), /* Port 3 Task file status */ + P3ER, 1, + , 2, + P3DQ, 1, + , 3, + P3BY, 1, + Offset(0x2A8), /* Port 3 Serial ATA status */ + P3DD, 4, + , 4, + P3IS, 4, + Offset(0x2AC), /* Port 3 Serial ATA control */ + P3DI, 4, + Offset(0x2B0), /* Port 3 Serial ATA error */ + , 16, + P3PR, 1, + } + } + + + #include "acpi/routing.asl" + + Scope(\_SB) { + + /* Debug Port registers, 80h. */ + OperationRegion(DBBG, SystemIO, 0x00000080, 0x00000001) + Field(DBBG, ByteAcc, NoLock, Preserve) { + DBG8, 0x00000008, + } + + Method(_PIC, 1) { + Store(Arg0, GPIC) + If (GPIC) { + Store(0xAA, \_SB.DBG8) + \_SB.DSPI() + } else { + Store(0xAC, \_SB.DBG8) + } + } + + Method(DSPI, 0) { + \_SB.GRUA(0x1F) + \_SB.GRUB(0x1F) + \_SB.GRUC(0x1F) + \_SB.GRUD(0x1F) + Store(0x1F, PIRE) + Store(0x1F, PIRF) + Store(0x1F, PIRG) + Store(0x1F, PIRH) + } + + Method(GRUA, 1) { + Store(Arg0, PIRA) + Store(Arg0, HDAD) + Store(Arg0, GEC) + Store(Arg0, GPP0) + Store(Arg0, GPP0) + } + + Method(GRUB, 1) { + Store(Arg0, PIRB) + Store(Arg0, USB2) + Store(Arg0, USB4) + Store(Arg0, USB6) + Store(Arg0, GPP1) + Store(Arg0, IDE) + } + + Method(GRUC, 1) { + Store(Arg0, PIRC) + Store(Arg0, USB1) + Store(Arg0, USB3) + Store(Arg0, USB5) + Store(Arg0, USB7) + Store(Arg0, GPP2) + } + + Method(GRUD, 1) { + Store(Arg0, PIRD) + Store(Arg0, SATA) + Store(Arg0, GPP3) + } + + Name(IRQB, ResourceTemplate() { + IRQ(Level, ActiveLow, Shared) { + 15 + }}) + + Name(IRQP, ResourceTemplate() { + IRQ(Level, ActiveLow, Shared) { + 3, 4, 5, 7, 10, 11, 12, 14, 15 + }}) + + Device(INTA) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 1) + Method(_STA, 0) { + if (PIRA) { + Return(0x0B) + } else { + Return(0x09) + } + } + Method(_DIS ,0) { + \_SB.GRUA(0x1F) + } + Method(_PRS ,0) { + Return(IRQP) + } + Method(_CRS ,0) { + CreateWordField(IRQB, 1, IRQN) + ShiftLeft(1, PIRA, IRQN) + Return(IRQB) + } + Method(_SRS, 1) { + CreateWordField(Arg0, 1, IRQM) + FindSetRightBit(IRQM, Local0) + Decrement(Local0) + \_SB.GRUA(Local0) + } + } + + Device(INTB) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 2) + Method(_STA, 0) { + if (PIRB) { + Return(0x0B) + } else { + Return(0x09) + } + } + Method(_DIS ,0) { + \_SB.GRUB(0x1F) + } + Method(_PRS ,0) { + Return(IRQP) + } + Method(_CRS ,0) { + CreateWordField(IRQB, 1, IRQN) + ShiftLeft(1, PIRB, IRQN) + Return(IRQB) + } + Method(_SRS, 1) { + CreateWordField(Arg0, 1, IRQM) + FindSetRightBit(IRQM, Local0) + Decrement(Local0) + \_SB.GRUB(Local0) + } + } + + Device(INTC) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 3) + Method(_STA, 0) { + if (PIRC) { + Return(0x0B) + } else { + Return(0x09) + } + } + Method(_DIS ,0) { + \_SB.GRUC(0x1F) + } + Method(_PRS ,0) { + Return(IRQP) + } + Method(_CRS ,0) { + CreateWordField(IRQB, 1, IRQN) + ShiftLeft(1, PIRC, IRQN) + Return(IRQB) + } + Method(_SRS, 1) { + CreateWordField(Arg0, 1, IRQM) + FindSetRightBit(IRQM, Local0) + Decrement(Local0) + \_SB.GRUC(Local0) + } + } + + Device(INTD) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 4) + Method(_STA, 0) { + if (PIRD) { + Return(0x0B) + } else { + Return(0x09) + } + } + Method(_DIS ,0) { + \_SB.GRUD(0x1F) + } + Method(_PRS ,0) { + Return(IRQP) + } + Method(_CRS ,0) { + CreateWordField(IRQB, 1, IRQN) + ShiftLeft(1, PIRD, IRQN) + Return(IRQB) + } + Method(_SRS, 1) { + CreateWordField(Arg0, 1, IRQM) + FindSetRightBit(IRQM, Local0) + Decrement(Local0) + \_SB.GRUD(Local0) + } + } + + Device(INTE) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 5) + Method(_STA, 0) { + if (PIRE) { + Return(0x0B) + } else { + Return(0x09) + } + } + Method(_DIS ,0) { + Store(0x1F, PIRE) + } + Method(_PRS ,0) { + Return(IRQP) + } + Method(_CRS ,0) { + CreateWordField(IRQB, 1, IRQN) + ShiftLeft(1, PIRE, IRQN) + Return(IRQB) + } + Method(_SRS, 1) { + CreateWordField(Arg0, 1, IRQM) + FindSetRightBit(IRQM, Local0) + Decrement(Local0) + Store(Local0, PIRE) + } + } + + Device(INTF) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 6) + Method(_STA, 0) { + if (PIRF) { + Return(0x0B) + } else { + Return(0x09) + } + } + Method(_DIS ,0) { + Store(0x1F, PIRF) + } + Method(_PRS ,0) { + Return(IRQP) + } + Method(_CRS ,0) { + CreateWordField(IRQB, 1, IRQN) + ShiftLeft(1, PIRF, IRQN) + Return(IRQB) + } + Method(_SRS, 1) { + CreateWordField(Arg0, 1, IRQM) + FindSetRightBit(IRQM, Local0) + Decrement(Local0) + Store(Local0, PIRF) + } + } + + Device(INTG) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 7) + Method(_STA, 0) { + if (PIRG) { + Return(0x0B) + } else { + Return(0x09) + } + } + Method(_DIS ,0) { + Store(0x1F, PIRG) + } + Method(_PRS ,0) { + Return(IRQP) + } + Method(_CRS ,0) { + CreateWordField(IRQB, 1, IRQN) + ShiftLeft(1, PIRG, IRQN) + Return(IRQB) + } + Method(_SRS, 1) { + CreateWordField(Arg0, 1, IRQM) + FindSetRightBit(IRQM, Local0) + Decrement(Local0) + Store(Local0, PIRG) + } + } + + Device(INTH) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 8) + Method(_STA, 0) { + if (PIRH) { + Return(0x0B) + } else { + Return(0x09) + } + } + Method(_DIS ,0) { + Store(0x1F, PIRH) + } + Method(_PRS ,0) { + Return(IRQP) + } + Method(_CRS ,0) { + CreateWordField(IRQB, 1, IRQN) + ShiftLeft(1, PIRH, IRQN) + Return(IRQB) + } + Method(_SRS, 1) { + CreateWordField(Arg0, 1, IRQM) + FindSetRightBit(IRQM, Local0) + Decrement(Local0) + Store(Local0, PIRH) + } + } + } /* End Scope(_SB) */ + + + /* Supported sleep states: */ + Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */ + + If (LAnd(SSFG, 0x01)) { + Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */ + } + If (LAnd(SSFG, 0x02)) { + Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */ + } + If (LAnd(SSFG, 0x04)) { + Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */ + } + If (LAnd(SSFG, 0x08)) { + Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */ + } + + Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */ + + Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */ + Name(CSMS, 0) /* Current System State */ + + /* Wake status package */ + Name(WKST,Package(){Zero, Zero}) + + /* + * \_PTS - Prepare to Sleep method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2, etc + * + * Exit: + * -none- + * + * The _PTS control method is executed at the beginning of the sleep process + * for S1-S5. The sleeping value is passed to the _PTS control method. This + * control method may be executed a relatively long time before entering the + * sleep state and the OS may abort the operation without notification to + * the ACPI driver. This method cannot modify the configuration or power + * state of any device in the system. + */ + Method(\_PTS, 1) { + /* DBGO("\\_PTS\n") */ + /* DBGO("From S0 to S") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + + /* Don't allow PCIRST# to reset USB */ + if (LEqual(Arg0,3)){ + Store(0,URRE) + } + + /* Clear sleep SMI status flag and enable sleep SMI trap. */ + /*Store(One, CSSM) + Store(One, SSEN)*/ + + /* On older chips, clear PciExpWakeDisEn */ + /*if (LLessEqual(\_SB.SBRI, 0x13)) { + * Store(0,\_SB.PWDE) + *} + */ + + /* Clear wake status structure. */ + Store(0, Index(WKST,0)) + Store(0, Index(WKST,1)) + } /* End Method(\_PTS) */ + + /* + * The following method results in a "not a valid reserved NameSeg" + * warning so I have commented it out for the duration. It isn't + * used, so it could be removed. + * + * + * \_GTS OEM Going To Sleep method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2 + * + * Exit: + * -none- + * + * Method(\_GTS, 1) { + * DBGO("\\_GTS\n") + * DBGO("From S0 to S") + * DBGO(Arg0) + * DBGO("\n") + * } + */ + + /* + * \_BFS OEM Back From Sleep method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2 + * + * Exit: + * -none- + */ + Method(\_BFS, 1) { + /* DBGO("\\_BFS\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ + } + + /* + * \_WAK System Wake method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2 + * + * Exit: + * Return package of 2 DWords + * Dword 1 - Status + * 0x00000000 wake succeeded + * 0x00000001 Wake was signaled but failed due to lack of power + * 0x00000002 Wake was signaled but failed due to thermal condition + * Dword 2 - Power Supply state + * if non-zero the effective S-state the power supply entered + */ + Method(\_WAK, 1) { + /* DBGO("\\_WAK\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ + + /* Re-enable HPET */ + Store(1,HPDE) + + /* Restore PCIRST# so it resets USB */ + if (LEqual(Arg0,3)){ + Store(1,URRE) + } + + /* Arbitrarily clear PciExpWakeStatus */ + Store(PEWS, PEWS) + + /* if(DeRefOf(Index(WKST,0))) { + * Store(0, Index(WKST,1)) + * } else { + * Store(Arg0, Index(WKST,1)) + * } + */ + Return(WKST) + } /* End Method(\_WAK) */ + + Scope(\_GPE) { /* Start Scope GPE */ + } /* End Scope GPE */ + + /* South Bridge */ + Scope(\_SB) { /* Start \_SB scope */ + #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + + /* _SB.PCI0 */ + /* Note: Only need HID on Primary Bus */ + Device(PCI0) { + External (TOM1) + External (TOM2) + External (TOM3) + External (TOM4) + Name(_HID, EISAID("PNP0A03")) + Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ + Method(_BBN, 0) { /* Bus number = 0 */ + Return(0) + } + Method(_STA, 0) { + /* DBGO("\\_SB\\PCI0\\_STA\n") */ + Return(0x0B) /* Status is visible */ + } + Method(_PRT,0) { + If(GPIC){ Return(APR0) } /* APIC mode */ + Return (PR0) /* PIC Mode */ + } /* end _PRT */ + + /* Describe the Northbridge devices */ + Device(AMRT) { + Name(_ADR, 0x00000000) + } /* end AMRT */ + + /* The internal GFX bridge */ + Device(AGPB) { + Name(_ADR, 0x00010000) + Method(_STA,0) { + Return(0x0F) + } + } /* end AGPB */ + + /* The external GFX bridge */ + Device(PBR2) { + Name(_ADR, 0x00020000) + Method(_PRT,0) { + If(GPIC){ Return(APS2) } /* APIC mode */ + Return (PS2) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR2 */ + + /* The external GFX bridge */ + Device(PBR3) { + Name(_ADR, 0x00030000) + Method(_PRT,0) { + If(GPIC){ Return(APS3) } /* APIC mode */ + Return (PS3) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR3 */ + + Device(PBR4) { + Name(_ADR, 0x00040000) + Method(_PRT,0) { + If(GPIC){ Return(APS4) } /* APIC mode */ + Return (PS4) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR4 */ + + Device(PBR5) { + Name(_ADR, 0x00050000) + Method(_PRT,0) { + If(GPIC){ Return(APS5) } /* APIC mode */ + Return (PS5) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR5 */ + + Device(PBR6) { + Name(_ADR, 0x00060000) + Method(_PRT,0) { + If(GPIC){ Return(APS6) } /* APIC mode */ + Return (PS6) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR6 */ + + /* The onboard EtherNet chip */ + Device(PBR7) { + Name(_ADR, 0x00070000) + Method(_PRT,0) { + If(GPIC){ Return(APS7) } /* APIC mode */ + Return (PS7) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR7 */ + + Device(PE20) { + Name(_ADR, 0x00150000) + Method(_PRT,0) { + If(GPIC){ Return(APE0) } /* APIC mode */ + Return (PE0) /* PIC Mode */ + } /* end _PRT */ + } /* end PE20 */ + Device(PE21) { + Name(_ADR, 0x00150001) + Method(_PRT,0) { + If(GPIC){ Return(APE1) } /* APIC mode */ + Return (PE1) /* PIC Mode */ + } /* end _PRT */ + } /* end PE21 */ + Device(PE22) { + Name(_ADR, 0x00150002) + Method(_PRT,0) { + If(GPIC){ Return(APE2) } /* APIC mode */ + Return (APE2) /* PIC Mode */ + } /* end _PRT */ + } /* end PE22 */ + Device(PE23) { + Name(_ADR, 0x00150003) + Method(_PRT,0) { + If(GPIC){ Return(APE3) } /* APIC mode */ + Return (PE3) /* PIC Mode */ + } /* end _PRT */ + } /* end PE23 */ + + /* Describe the Southbridge devices */ + Device(AZHD) { + Name(_ADR, 0x00140002) + OperationRegion(AZPD, PCI_Config, 0x00, 0x100) + Field(AZPD, AnyAcc, NoLock, Preserve) { + offset (0x42), + NSDI, 1, + NSDO, 1, + NSEN, 1, + } + } /* end AZHD */ + + Device(GEC) { + Name(_ADR, 0x00140006) + } /* end GEC */ + + Device(UOH1) { + Name(_ADR, 0x00120000) + #include "acpi/usb.asl" + } /* end UOH1 */ + + Device(UOH3) { + Name(_ADR, 0x00130000) + #include "acpi/usb.asl" + } /* end UOH3 */ + + Device(UOH5) { + Name(_ADR, 0x00160000) + #include "acpi/usb.asl" + } /* end UOH5 */ + + Device(UEH1) { + Name(_ADR, 0x00140005) + #include "acpi/usb.asl" + } /* end UEH1 */ + + Device(UOH2) { + Name(_ADR, 0x00120002) + #include "acpi/usb.asl" + } /* end UOH2 */ + + Device(UOH4) { + Name(_ADR, 0x00130002) + #include "acpi/usb.asl" + } /* end UOH4 */ + + Device(UOH6) { + Name(_ADR, 0x00160002) + #include "acpi/usb.asl" + } /* end UOH5 */ + + Device(XHC0) { + Name(_ADR, 0x00100000) + #include "acpi/usb.asl" + } /* end XHC0 */ + + Device(XHC1) { + Name(_ADR, 0x00100001) + #include "acpi/usb.asl" + } /* end XHC1 */ + + Device(SBUS) { + Name(_ADR, 0x00140000) + } /* end SBUS */ + + Device(LIBR) { + Name(_ADR, 0x00140003) + /* Real Time Clock Device */ + Device(RTC0) { + Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ + Name(BUF0, ResourceTemplate() { + IO(Decode16, 0x0070, 0x0070, 0x01, 0x02) + }) + Name(BUF1, ResourceTemplate() { + IRQNoFlags() {8} + IO(Decode16, 0x0070, 0x0070, 0x01, 0x02) + }) + Method(_CRS, 0) { + If(LAnd(HPAD, 0xFFFFFF00)) { + Return(BUF0) + } + Return(BUF1) + } + } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */ + + Device(TMR) { /* Timer */ + Name(_HID,EISAID("PNP0100")) /* System Timer */ + Name(BUF0, ResourceTemplate() { + IO(Decode16, 0x0040, 0x0040, 0x01, 0x04) + }) + Name(BUF1, ResourceTemplate() { + IRQNoFlags() {0} + IO(Decode16, 0x0040, 0x0040, 0x01, 0x04) + }) + Method(_CRS, 0) { + If(LAnd(HPAD, 0xFFFFFF00)) { + Return(BUF0) + } + Return(BUF1) + } + } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */ + + Device(SPKR) { /* Speaker */ + Name(_HID,EISAID("PNP0800")) /* AT style speaker */ + Name(_CRS, ResourceTemplate() { + IO(Decode16, 0x0061, 0x0061, 0, 1) + }) + } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */ + + Device(PIC) { + Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */ + Name(_CRS, ResourceTemplate() { + IRQNoFlags(){2} + IO(Decode16,0x0020, 0x0020, 0, 2) + IO(Decode16,0x00A0, 0x00A0, 0, 2) + /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */ + /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */ + }) + } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */ + + Device(MAD) { /* 8257 DMA */ + Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */ + Name(_CRS, ResourceTemplate() { + DMA(Compatibility,BusMaster,Transfer8){4} + IO(Decode16, 0x0000, 0x0000, 0x10, 0x10) + IO(Decode16, 0x0081, 0x0081, 0x01, 0x03) + IO(Decode16, 0x0087, 0x0087, 0x01, 0x01) + IO(Decode16, 0x0089, 0x0089, 0x01, 0x03) + IO(Decode16, 0x008F, 0x008F, 0x01, 0x01) + IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20) + }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */ + } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */ + + Device(COPR) { + Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */ + Name(_CRS, ResourceTemplate() { + IO(Decode16, 0x00F0, 0x00F0, 0, 0x10) + IRQNoFlags(){13} + }) + } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ + + Device (PS2M) { + Name (_HID, EisaId ("PNP0F13")) + Name (_CRS, ResourceTemplate () { + IRQNoFlags () {12} + }) + Method (_STA, 0) { + And (FLG0, 0x04, Local0) + If (LEqual (Local0, 0x04)) { + Return (0x0F) + } Else { + Return (0x00) + } + } + } + + Device (PS2K) { + Name (_HID, EisaId ("PNP0303")) + Name (_CRS, ResourceTemplate () { + IO (Decode16, 0x0060, 0x0060, 0x01, 0x01) + IO (Decode16, 0x0064, 0x0064, 0x01, 0x01) + IRQNoFlags () {1} + }) + } + } /* end LIBR */ + + Device(STCR) { + Name(_ADR, 0x00110000) + #include "acpi/sata.asl" + } /* end STCR */ + + /* Primary (and only) IDE channel */ + Device(IDEC) { + Name(_ADR, 0x00140001) + #include "acpi/ide.asl" + } /* end IDEC */ + + Device(HPET) { + Name(_HID,EISAID("PNP0103")) + Name(CRS, ResourceTemplate() { + IRQNoFlags() {0} + IRQNoFlags() {8} + Memory32Fixed(ReadOnly, 0xFED00000, 0x00000400) + }) + Method(_STA, 0) { + If(LAnd(HPAD, 0xFFFFFF00)) { + Return(0x0F) + } + Return(0x0) + } + Method(_CRS, 0) { + CreateDWordField(CRS, 0x0A, HPEB) + Store(HPAD, Local0) + And(Local0, 0xFFFFFFC0, HPEB) + Return(CRS) + } + } /* End Device(_SB.PCI0.HPET) */ + + Name(CRES, ResourceTemplate() { + IO(Decode16, 0x0CF8, 0x0CF8, 1, 8) + + WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, /* address granularity */ + 0x0000, /* range minimum */ + 0x0CF7, /* range maximum */ + 0x0000, /* translation */ + 0x0CF8 /* length */ + ) + + WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, /* address granularity */ + 0x0D00, /* range minimum */ + 0xFFFF, /* range maximum */ + 0x0000, /* translation */ + 0xF300 /* length */ + ) + + /* memory space for PCI BARs below 4GB */ + Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) + }) /* End Name(_SB.PCI0.CRES) */ + + Method(_CRS, 0) { + /* DBGO("\\_SB\\PCI0\\_CRS\n") */ + CreateDWordField(CRES, ^MMIO._BAS, MM1B) + CreateDWordField(CRES, ^MMIO._LEN, MM1L) + + Store(\_SB.PCI0.TOM1, MM1B) + Subtract(PCBA, MM1B, MM1L) + + Return(CRES) /* note to change the Name buffer */ + } /* end of Method(_SB.PCI0._CRS) */ + } /* End Device(PCI0) */ + + Device(PWRB) { /* Start Power button device */ + Name(_HID, EISAID("PNP0C0C")) + Name(_UID, 0xAA) + Name(_STA, 0x0B) /* sata is invisible */ + } + } /* End \_SB scope */ +} +/* End of ASL file */ diff --git a/src/mainboard/amd/dinar/fadt.c b/src/mainboard/amd/dinar/fadt.c new file mode 100644 index 0000000..baf0328 --- /dev/null +++ b/src/mainboard/amd/dinar/fadt.c @@ -0,0 +1,173 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +/* + * ACPI - create the Fixed ACPI Description Tables (FADT) + */ + + +#include <string.h> +#include <console/console.h> +#include <arch/acpi.h> +#include <arch/io.h> +#include <device/device.h> +#include "Platform.h" /*sb700 platform header*/ + +#ifndef ACPI_BLK_BASE +#define ACPI_BLK_BASE PM1_EVT_BLK_ADDRESS +#endif +void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + + printk(BIOS_DEBUG, "ACPI_BLK_BASE: 0x%04x\n", ACPI_BLK_BASE); + /* Prepare the header */ + memset((void *)fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = 244; + header->revision = 1; + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->asl_compiler_revision = 0; + + fadt->firmware_ctrl = (u32) facs; + fadt->dsdt = (u32) dsdt; + /* 3=Workstation,4=Enterprise Server, 7=Performance Server */ + fadt->preferred_pm_profile = 0x03; + fadt->sci_int = 9; + /* disable system management mode by setting to 0: */ + fadt->smi_cmd = 0; + fadt->acpi_enable = 0xf0; + fadt->acpi_disable = 0xf1; + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = 0xe2; + + /* RTC_En_En, TMR_En_En, GBL_EN_EN */ + outl(0x1, PM1_CNT_BLK_ADDRESS); /* set SCI_EN */ + fadt->pm1a_evt_blk = PM1_EVT_BLK_ADDRESS; + fadt->pm1b_evt_blk = 0x0000; + fadt->pm1a_cnt_blk = PM1_CNT_BLK_ADDRESS; + fadt->pm1b_cnt_blk = 0x0000; + fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK_ADDRESS; + fadt->pm_tmr_blk = PM1_TMR_BLK_ADDRESS; + fadt->gpe0_blk = GPE0_BLK_ADDRESS; + fadt->gpe1_blk = 0x0000; /* we dont have gpe1 block, do we? */ + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm2_cnt_len = 1; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 8; + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + + fadt->cst_cnt = 0xe3; + fadt->p_lvl2_lat = 101; + fadt->p_lvl3_lat = 1001; + fadt->flush_size = 0; + fadt->flush_stride = 0; + fadt->duty_offset = 1; + fadt->duty_width = 3; + fadt->day_alrm = 0; /* 0x7d these have to be */ + fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */ + fadt->century = 0; /* 0x7f to make rtc alrm work */ + fadt->iapc_boot_arch = 0x3; /* See table 5-11 */ + fadt->flags = 0x0001c1a5;/* 0x25; */ + + fadt->res2 = 0; + + fadt->reset_reg.space_id = 1; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.resv = 0; + fadt->reset_reg.addrl = 0xcf9; + fadt->reset_reg.addrh = 0x0; + + fadt->reset_value = 6; + fadt->x_firmware_ctl_l = (u32) facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (u32) dsdt; + fadt->x_dsdt_h = 0; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = 32; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.resv = 0; + fadt->x_pm1a_evt_blk.addrl = PM1_EVT_BLK_ADDRESS; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.bit_width = 4; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.resv = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = 16; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.resv = 0; + fadt->x_pm1a_cnt_blk.addrl = PM1_CNT_BLK_ADDRESS; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.bit_width = 2; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.resv = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = 0; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.resv = 0; + fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK_ADDRESS; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.resv = 0; + fadt->x_pm_tmr_blk.addrl = PM1_TMR_BLK_ADDRESS; + fadt->x_pm_tmr_blk.addrh = 0x0; + + + fadt->x_gpe0_blk.space_id = 1; + fadt->x_gpe0_blk.bit_width = 32; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.resv = 0; + fadt->x_gpe0_blk.addrl = GPE0_BLK_ADDRESS; + fadt->x_gpe0_blk.addrh = 0x0; + + + fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.resv = 0; + fadt->x_gpe1_blk.addrl = 0; + fadt->x_gpe1_blk.addrh = 0x0; + + header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t)); + +} diff --git a/src/mainboard/amd/dinar/get_bus_conf.c b/src/mainboard/amd/dinar/get_bus_conf.c new file mode 100644 index 0000000..f66e92c --- /dev/null +++ b/src/mainboard/amd/dinar/get_bus_conf.c @@ -0,0 +1,156 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <string.h> +#include <stdint.h> +#include <stdlib.h> +#include <cpu/amd/amdfam15.h> +#include "agesawrapper.h" +#if CONFIG_AMD_SB_CIMX +#include <sb_cimx.h> +#endif + + +/* Global variables for MB layouts and these will be shared by irqtable mptable + * and acpi_tables busnum is default. + */ +u8 bus_isa; +u8 bus_sb700[2]; +u8 bus_rd890[14]; + +/* + * Here you only need to set value in pci1234 for HT-IO that could be installed or not + * You may need to preset pci1234 for HTIO board, + * please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail + */ +u32 pci1234x[] = { + 0x0000ff0, +}; + +/* + * HT Chain device num, actually it is unit id base of every ht device in chain, + * assume every chain only have 4 ht device at most + */ +u32 hcdnx[] = { + 0x20202020, +}; + +u32 bus_type[256]; + +u32 sbdn_sb700; +u32 sbdn_rd890; + +static u32 get_bus_conf_done = 0; + + + + +void get_bus_conf(void) +{ + u32 status; + + device_t dev; + int i, j; + + if (get_bus_conf_done == 1) + return; /* do it only once */ + + get_bus_conf_done = 1; + + printk(BIOS_DEBUG, "Mainboard - Get_bus_conf.c - get_bus_conf - Start.\n"); + /* + * This is the call to AmdInitLate. It is really in the wrong place, conceptually, + * but functionally within the coreboot model, this is the best place to make the + * call. The logically correct place to call AmdInitLate is after PCI scan is done, + * after the decision about S3 resume is made, and before the system tables are + * written into RAM. The routine that is responsible for writing the tables is + * "write_tables", called near the end of "hardwaremain". There is no platform + * specific entry point between the S3 resume decision point and the call to + * "write_tables", and the next platform specific entry points are the calls to + * the ACPI table write functions. The first of ose would seem to be the right + * place, but other table write functions, e.g. the PIRQ table write function, are + * called before the ACPI tables are written. This routine is called at the beginning + * of each of the write functions called prior to the ACPI write functions, so this + * becomes the best place for this call. + */ + status = agesawrapper_amdinitlate(); + if(status) { + printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); + } + printk(BIOS_DEBUG, "Got past agesawrapper_amdinitlate\n"); + + sbdn_sb700 = 0; + + for (i = 0; i < ARRAY_SIZE(bus_sb700); i++) { + bus_sb700[i] = 0; + } + for (i = 0; i < ARRAY_SIZE(bus_rd890); i++) { + bus_rd890[i] = 0; + } + + for (i = 0; i < 256; i++) { + bus_type[i] = 0; /* default ISA bus. */ + } + + + bus_type[0] = 1; /* pci */ + + bus_rd890[0] = (pci1234x[0] >> 16) & 0xff; + bus_sb700[0] = bus_rd890[0]; + + /* sb700 */ + dev = dev_find_slot(bus_sb700[0], PCI_DEVFN(sbdn_sb700 + 0x14, 4)); + + + + if (dev) { + bus_sb700[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); + + bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_isa++; + for (j = bus_sb700[1]; j < bus_isa; j++) + bus_type[j] = 1; + } + + /* rd890 */ + for (i = 1; i < ARRAY_SIZE(bus_rd890); i++) { + dev = dev_find_slot(bus_rd890[0], PCI_DEVFN(sbdn_rd890 + i, 0)); + if (dev) { + bus_rd890[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); + if(255 != bus_rd890[i]) { + bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_isa++; + bus_type[bus_rd890[i]] = 1; /* PCI bus. */ + } + } + } + + + /* I/O APICs: APIC ID Version State Address */ + bus_isa = 10; + +#if CONFIG_AMD_SB_CIMX +// sb_After_Pci_Init(); +// sb_Late_Post(); +#endif + printk(BIOS_DEBUG, "Mainboard - Get_bus_conf.c - get_bus_conf - End.\n"); +} diff --git a/src/mainboard/amd/dinar/gpio.c b/src/mainboard/amd/dinar/gpio.c new file mode 100644 index 0000000..f18c09d --- /dev/null +++ b/src/mainboard/amd/dinar/gpio.c @@ -0,0 +1,482 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#include "Filecode.h" +#include "Hudson-2.h" +#include "AmdSbLib.h" +#include "gpio.h" + +#define FILECODE UNASSIGNED_FILE_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +#ifndef SB_GPIO_REG01 +#define SB_GPIO_REG01 1 +#endif + +#ifndef SB_GPIO_REG07 +#define SB_GPIO_REG07 7 +#endif + +#ifndef SB_GPIO_REG25 +#define SB_GPIO_REG25 25 +#endif + +#ifndef SB_GPIO_REG26 +#define SB_GPIO_REG26 26 +#endif + +#ifndef SB_GPIO_REG27 +#define SB_GPIO_REG27 27 +#endif + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +void gpioEarlyInit (void); + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*--------------------------------------------------------------------------------------- + * L O C A L F U N C T I O N S + *--------------------------------------------------------------------------------------- + */ +void +gpioEarlyInit( + void + ) +{ + u8 Flags; + u8 Data8 = 0; + u8 StripInfo = 0; + u8 BoardType = 1; + u8 RegIndex8 = 0; + u8 boardRevC = 0x2; + u16 Data16 = 0; + u32 Index = 0; + u32 AcpiMmioAddr = 0; + u32 GpioMmioAddr = 0; + u32 IoMuxMmioAddr = 0; + u32 MiscMmioAddr = 0; + u32 SmiMmioAddr = 0; + u32 andMask32 = 0; + + // Enable HUDSON MMIO Base (AcpiMmioAddr) + ReadPMIO (SB_PMIOA_REG24, AccWidthUint8, &Data8); + Data8 |= BIT0; + WritePMIO (SB_PMIOA_REG24, AccWidthUint8, &Data8); + // Get HUDSON MMIO Base (AcpiMmioAddr) + ReadPMIO (SB_PMIOA_REG24 + 3, AccWidthUint8, &Data8); + Data16 = Data8 << 8; + ReadPMIO (SB_PMIOA_REG24 + 2, AccWidthUint8, &Data8); + Data16 |= Data8; + AcpiMmioAddr = (u32)Data16 << 16; + GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; + IoMuxMmioAddr = AcpiMmioAddr + IOMUX_BASE; + MiscMmioAddr = AcpiMmioAddr + MISC_BASE; + Data8 = Mmio8_G (MiscMmioAddr, SB_MISC_REG80); + if ((Data8 & BIT4) == 0) { + BoardType = 0; // external clock board + } + Data8 = Mmio8_G (GpioMmioAddr, GPIO_30); + StripInfo = (Data8 & BIT7) >> 7; + Data8 = Mmio8_G (GpioMmioAddr, GPIO_31); + StripInfo |= (Data8 & BIT7) >> 6; + if (StripInfo < boardRevC) { // for old board. Rev B + Mmio8_And_Or (IoMuxMmioAddr, GPIO_111, 0x00, 3); // function 3 + Mmio8_And_Or (IoMuxMmioAddr, GPIO_113, 0x00, 0); // function 0 + } + for (Index = 0; Index < MAX_GPIO_NO; Index++) { + if (!(((Index >= GPIO_RSVD_ZONE0_S) && (Index <= GPIO_RSVD_ZONE0_E)) || ((Index >= GPIO_RSVD_ZONE1_S) && (Index <= GPIO_RSVD_ZONE1_E)))) { + if ((StripInfo >= boardRevC) || ((Index != GPIO_111) && (Index != GPIO_113))) { + // Configure multi-funtion + Mmio8_And_Or (IoMuxMmioAddr, Index, 0x00, (gpio_table[Index].select & ~NonGpio)); + } + // Configure GPIO + if(!((gpio_table[Index].NonGpioGevent & NonGpio))) { + Mmio8_And_Or (GpioMmioAddr, Index, 0xDF, gpio_table[Index].type); + Mmio8_And_Or (GpioMmioAddr, Index, 0xA3, gpio_table[Index].value); + } + if (Index == GPIO_65) { + if ( BoardType == 0 ) { + Mmio8_And_Or (IoMuxMmioAddr, GPIO_65, 0x00, 3); // function 3 + } + } + } + // Configure GEVENT + if ((Index >= GEVENT_00) && (Index <= GEVENT_23) && ((gevent_table[Index - GEVENT_00].EventEnable))) { + SmiMmioAddr = AcpiMmioAddr + SMI_BASE; + + andMask32 = ~(1 << (Index - GEVENT_00)); + + //EventEnable: 0-Disable, 1-Enable + Mmio32_And_Or (SmiMmioAddr, SMIREG_EVENT_ENABLE, andMask32, (gevent_table[Index - GEVENT_00].EventEnable << (Index - GEVENT_00))); + + //SciTrig: 0-Falling Edge, 1-Rising Edge + Mmio32_And_Or (SmiMmioAddr, SMIREG_SCITRIG, andMask32, (gevent_table[Index - GEVENT_00].SciTrig << (Index - GEVENT_00))); + + //SciLevl: 0-Edge trigger, 1-Level Trigger + Mmio32_And_Or (SmiMmioAddr, SMIREG_SCILEVEL, andMask32, (gevent_table[Index - GEVENT_00].SciLevl << (Index - GEVENT_00))); + + //SmiSciEn: 0-Not send SMI, 1-Send SMI + Mmio32_And_Or (SmiMmioAddr, SMIREG_SMISCIEN, andMask32, (gevent_table[Index - GEVENT_00].SmiSciEn << (Index - GEVENT_00))); + + //SciS0En: 0-Disable, 1-Enable + Mmio32_And_Or (SmiMmioAddr, SMIREG_SCIS0EN, andMask32, (gevent_table[Index - GEVENT_00].SciS0En << (Index - GEVENT_00))); + + //SciMap: 00000b ~ 11111b + RegIndex8=(u8)((Index - GEVENT_00) >> 2); + Data8=(u8)(((Index - GEVENT_00) & 0x3) * 8); + Mmio32_And_Or (SmiMmioAddr, SMIREG_SCIMAP0+RegIndex8, ~(GEVENT_SCIMASK << Data8), (gevent_table[Index - GEVENT_00].SciMap << Data8)); + + //SmiTrig: 0-Active Low, 1-Active High + Mmio32_And_Or (SmiMmioAddr, SMIREG_SMITRIG, ~(gevent_table[Index - GEVENT_00].SmiTrig << (Index - GEVENT_00)), (gevent_table[Index - GEVENT_00].SmiTrig << (Index - GEVENT_00))); + + //SmiControl: 0-Disable, 1-SMI, 2-NMI, 3-IRQ13 + RegIndex8=(u8)((Index - GEVENT_00) >> 4); + Data8=(u8)(((Index - GEVENT_00) & 0xF) * 2); + Mmio32_And_Or (SmiMmioAddr, SMIREG_SMICONTROL0+RegIndex8, ~(SMICONTROL_MASK << Data8), (gevent_table[Index - GEVENT_00].SmiControl << Data8)); + } + } + + // + // config MXM + // GPIO9: Input for MXM_PRESENT2# + // GPIO10: Input for MXM_PRESENT1# + // GPIO28: Input for MXM_PWRGD + // GPIO35: Output for MXM Reset + // GPIO45: Output for MXM Power Enable, active HIGH + // GPIO55: Output for MXM_PWR_EN, 1 - Enable, 0 - Disable + // GPIO32: Output for PCIE_SW, 1 - MXM, 0 - LASSO + // + // set INTE#/GPIO32 as GPO for PCIE_SW + RWMEM (IoMuxMmioAddr + SB_GPIO_REG32, AccWidthUint8, 00, 0x1); // GPIO + RWMEM (GpioMmioAddr + SB_GPIO_REG32, AccWidthUint8, 0x03, 0); // GPO + RWMEM (GpioMmioAddr + SB_GPIO_REG32, AccWidthUint8, 0x23, BIT3+BIT6); + + // set SATA_IS4#/FANOUT3/GPIO55 as GPO for MXM_PWR_EN + RWMEM (IoMuxMmioAddr + SB_GPIO_REG55, AccWidthUint8, 00, 0x2); // GPIO + RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0x03, 0); // GPO + + // set AD9/GPIO9 as GPI for MXM_PRESENT2# + RWMEM (IoMuxMmioAddr + SB_GPIO_REG09, AccWidthUint8, 00, 0x1); // GPIO + RWMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, 0x03, BIT5); // GPI + + // set AD10/GPIO10 as GPI for MXM_PRESENT1# + RWMEM (IoMuxMmioAddr + SB_GPIO_REG10, AccWidthUint8, 00, 0x1); // GPIO + RWMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, 0x03, BIT5); // GPI + + // set GNT1#/GPIO44 as GPO for MXM Reset + RWMEM (IoMuxMmioAddr + SB_GPIO_REG44, AccWidthUint8, 00, 0x1); // GPIO + RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0x03, 0); // GPO + + // set GNT2#/SD_LED/GPO45 as GPO for MXM Power Enable + RWMEM (IoMuxMmioAddr + SB_GPIO_REG45, AccWidthUint8, 00, 0x2); // GPIO + RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0x03, 0); // GPO + + // set AD28/GPIO28 as GPI for MXM_PWRGD + RWMEM (IoMuxMmioAddr + SB_GPIO_REG28, AccWidthUint8, 00, 0x1); // GPIO + RWMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, 0x03, BIT5); // GPI + + // set BIT3=1 (PULLUP disable), BIT4=0 (PULLDOWN Disable), BIT6=0 (Output LOW) + RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0x23, BIT3); + RWMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, 0x23, BIT3); + RWMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, 0x23, BIT3); + RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0x23, BIT3); + RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0x23, BIT3); + RWMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, 0x23, BIT3); + + // + // [GPIO] STRP_DATA: 1->RS880M VCC_NB 1.0V. 0->RS880M VCC_NB 1.1V (Default). + // + //Fusion_Llano BLWriteNBMISC_Dword (ATI_MISC_REG42, (BLReadNBMISC_Dword (ATI_MISC_REG42) | BIT20)); + //Fusion_Llano BLWriteNBMISC_Dword (ATI_MISC_REG40, (BLReadNBMISC_Dword (ATI_MISC_REG40) & (~BIT20))); + + // check if there any GFX card + Flags = 0; + // Value32 = MmPci32 (0, SB_ISA_BUS, SB_ISA_DEV, SB_ISA_FUNC, R_SB_ISA_GPIO_CONTROL); + // Data8 = Mmio8 (GpioMmioAddr, SB_GPIO_REG09); + ReadMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, &Data8); + if (!(Data8 & BIT7)) + { + //Data8 = Mmio8 (GpioMmioAddr, SB_GPIO_REG10); + ReadMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, &Data8); + if (!(Data8 & BIT7)) + { + Flags = 1; + } + } + if ( Flags ) + { + // [GPIO] GPIO44: PE_GPIO0 MXM Reset set to 0 for reset, ENH164467 + RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0xBF, 0); + + // [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE, SET HIGH + RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0xFF, BIT6); + + //PeiStall (PeiServices, NULL, 100); //delay 100 ms (should be >1ms) + SbStall (10000); + + // Write the GPIO55(MXM_PWR_EN) to enable the integrated power module + RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0xFF, BIT6); + + //PeiStall (PeiServices, NULL, 100); //delay 100 ms (should be >1ms) + // WAIT POWER READY: GPIO28 (MXM_PWRGD) + //while (!(Mmio8 (GpioMmioAddr, SB_GPIO_REG28) && BIT7)){} + ReadMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, &Data8); + while (!(Data8 && BIT7)) + { + ReadMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, &Data8); + } + // [GPIO] GPIO44: PE_GPIO0 MXM Reset set to 1 for reset + // RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0xBF, BIT6); + } + else + { + // Write the GPIO55(MXM_PWR_EN) to disable the integrated power module + RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0xBF, 0); + + //PeiStall (PeiServices, NULL, 100); //delay 100 ms (should be >1ms) + SbStall (10000); + + // [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE down + RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0xBF, 0); + } + + // + // APU GPP0: On board LAN + // GPIO25: PCIE_RST#_LAN, LOW active + // GPIO63: LAN_CLKREQ# + // GPIO197: LOM_POWER, HIGH Active + // Clock: GPP_CLK3 + // + // Set EC_PWM0/EC_TIMER0/GPIO197 as GPO for LOM_POWER + RWMEM (IoMuxMmioAddr + SB_GPIO_REG197, AccWidthUint8, 00, 0x2); // GPIO + // RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x03, 0); // GPO + RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x03, BIT6); // output HIGH + RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x63, BIT3); // pullup DISABLE + + // Setup AD25/GPIO25 as GPO for PCIE_RST#_LAN: + RWMEM (IoMuxMmioAddr + SB_GPIO_REG25, AccWidthUint8, 00, 0x1); // GPIO + // RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x03, 0); // GPO + RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x03, BIT6); // output HIGH + RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x63, BIT3); // pullup DISABLE + + + // set CLK_REQ3#/SATA_IS1#/GPIO63 as CLK_REQ for LAN_CLKREQ# + RWMEM (IoMuxMmioAddr + SB_GPIO_REG63, AccWidthUint8, 00, 0x0); // CLK_REQ3# + RWMEM (MiscMmioAddr + SB_MISC_REG00+1, AccWidthUint8, 0x0F, 0xF0); // Enable GPP_CLK3 + + // + // APU GPP1: WUSB + // GPIO1: MPCIE_RST2#, LOW active + // GPIO13: WU_DISABLE#, LOW active + // GPIO177: MPICE_PD2, 1 - DISABLE, 0 - ENABLE (Default) + // + // Setup VIN2/SATA1_1/GPIO177 as GPO for MPCIE_PD2#: wireless disable + RWMEM (IoMuxMmioAddr + SB_GPIO_REG177, AccWidthUint8, 00, 0x2); // GPIO + // RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x03, 0); // GPO + RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x03, 0); // output LOW + RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x63, BIT3); // pullup DISABLE + + // Setup AD01/GPIO01 as GPO for MPCIE_RST2# + RWMEM (IoMuxMmioAddr + SB_GPIO_REG01, AccWidthUint8, 00, 0x1); // GPIO + // RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x03, 0); // GPO + RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x03, BIT6); // output LOW + RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x63, BIT3); // pullup DISABLE + + // Setup AD13/GPIO13 as GPO for WU_DISABLE#: disable WUSB + // RWMEM (IoMuxMmioAddr + SB_GPIO_REG13, AccWidthUint8, 00, 0x1); // GPIO + // RWMEM (GpioMmioAddr + SB_GPIO_REG13, AccWidthUint8, 0x03, 0); // GPO + // RWMEM (GpioMmioAddr + SB_GPIO_REG13, AccWidthUint8, 0x03, BIT6); // output HIGH + // RWMEM (GpioMmioAddr + SB_GPIO_REG13, AccWidthUint8, 0x63, BIT3); // pullup DISABLE + + // + // APU GPP2: WWAN + // GPIO0: MPCIE_RST1#, LOW active + // GPIO14: WP_DISABLE#, LOW active + // GPIO176: MPICE_PD1, 1 - DISABLE, 0 - ENABLE (Default) + // + // Set VIN1/GPIO176 as GPO for MPCIE_PD1# for wireless disable + RWMEM (IoMuxMmioAddr + SB_GPIO_REG176, AccWidthUint8, 00, 0x1); // GPIO + // RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x03, 0); // GPO + RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x03, 0); // output LOW + RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x63, BIT3); // pullup DISABLE + + // Set AD00/GPIO00 as GPO for MPCIE_RST1# + RWMEM (IoMuxMmioAddr + SB_GPIO_REG00, AccWidthUint8, 00, 0x1); // GPIO + // RWMEM (GpioMmioAddr + SB_GPIO_REG00, AccWidthUint8, 0x03, 0); // GPO + // RWMEM (GpioMmioAddr + SB_GPIO_REG00, AccWidthUint8, 0x03, BIT6); // output LOW + RWMEM (GpioMmioAddr + SB_GPIO_REG00, AccWidthUint8, 0x63, BIT3); // pullup DISABLE + + // Set AD14/GPIO14 as GPO for WP_DISABLE#: disable WWAN + // RWMEM (IoMuxMmioAddr + SB_GPIO_REG14, AccWidthUint8, 00, 0x1); // GPIO + // RWMEM (GpioMmioAddr + SB_GPIO_REG14, AccWidthUint8, 0x03, 0); // GPO + // RWMEM (GpioMmioAddr + SB_GPIO_REG14, AccWidthUint8, 0x03, BIT6); + // RWMEM (GpioMmioAddr + SB_GPIO_REG14, AccWidthUint8, 0x63, BIT3); + + // + // APU GPP3: 1394 + // GPIO59: Power control, HIGH active + // GPIO27: PCIE_RST#_1394, LOW active + // GPIO41: CLKREQ# + // Clock: GPP_CLK8 + // + // Setup SATA_IS5#/FANIN3/GPIO59 as GPO for 1394_ON: + RWMEM (IoMuxMmioAddr + SB_GPIO_REG59, AccWidthUint8, 00, 0x2); // GPIO + // RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, 0); // GPO + RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, BIT6); // output HIGH + RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x63, BIT3); // pullup DISABLE + + // Setup AD27/GPIO27 as GPO for MPCIE_RST#_1394 + RWMEM (IoMuxMmioAddr + SB_GPIO_REG27, AccWidthUint8, 00, 0x1); // GPIO + // RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, 0); // GPO + RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, BIT6); // output HIGH + RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x63, BIT3); // pullup DISABLE + + // set REQ2#/CLK_REQ2#/GPIO41 as CLK_REQ# + RWMEM (IoMuxMmioAddr + SB_GPIO_REG41, AccWidthUint8, 00, 0x1); // CLK_REQ2# + + // set AZ_SDIN3/GPIO170 as GPO for GPIO_GATE_C + RWMEM (IoMuxMmioAddr + SB_GPIO_REG170, AccWidthUint8, 00, 0x1); // GPIO + RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x03, 0); // GPO + RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x03, BIT6); // output HIGH + RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x63, BIT3); // pullup DISABLE + // To fix glitch issue + RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, 0); // set GPIO_GATE_C to LOW + // + // Enable/Disable OnBoard LAN + // + if (!CONFIG_ONBOARD_LAN) + { // 1 - DISABLED + RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0xBF, 0); // LOM_POWER off + RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0xBF, 0); + RWMEM (GpioMmioAddr + SB_GPIO_REG63, AccWidthUint8, 0xFF, BIT3); // PULL UP - DISABLED + RWMEM (MiscMmioAddr + SB_MISC_REG00+1, AccWidthUint8, 0x0F, 0); // Disable GPP_CLK3 + } + // else + // { // 0 - AUTO + // // set BIT3=1 (PULLUP disable), BIT4=0 (PULLDOWN Disable) + // RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x23, BIT3); + // RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x23, BIT3); + // } + + + // + // Enable/Disable 1394 + // + if (!CONFIG_ONBOARD_1394) + { // 1 - DISABLED + // RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, 0); // set GPIO_GATE_C to LOW + RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0xBF, 0); // 1394 power off + RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0xBF, 0); + RWMEM (GpioMmioAddr + SB_GPIO_REG41, AccWidthUint8, 0xFF, BIT3); // pullup DISABLE + RWMEM (MiscMmioAddr + SB_MISC_REG04, AccWidthUint8, 0xF0, 0); // DISABLE GPP_CLK8 + // RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, BIT6); // set GPIO_GATE_C to HIGH + } + // else + // { // 0 - AUTO + // // set BIT3=1 (PULLUP disable), BIT4=0 (PULLDOWN Disable), BIT6=1 (output HIGH) + // RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, BIT6); + // RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x63, BIT3); + // + // RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, BIT6); + // RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x63, BIT3); + // } + + // + // external USB 3.0 control: + // amdExternalUSBController: CMOS, 0 - AUTO, 1 - DISABLE + // GPIO26: PCIE_RST#_USB3.0 + // GPIO46: PCIE_USB30_CLKREQ# + // GPIO200: NEC_USB30_PWR_EN, 0 - OFF, 1 - ON + // Clock: GPP_CLK7 + // GPIO172 used as FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE + // if ((Amd_SystemConfiguration.XhciSwitch == 1) || (SystemConfiguration.amdExternalUSBController == 1)) { + // disable Onboard NEC USB3.0 controller + if (!CONFIG_ONBOARD_USB30) { + RWMEM (GpioMmioAddr + SB_GPIO_REG200, AccWidthUint8, 0xBF, 0); + RWMEM (GpioMmioAddr + SB_GPIO_REG26, AccWidthUint8, 0xBF, 0); + RWMEM (GpioMmioAddr + SB_GPIO_REG46, AccWidthUint8, 0xFF, BIT3); // PULL_UP DISABLE + RWMEM (MiscMmioAddr + SB_MISC_REG00+3, AccWidthUint8, 0x0F, 0); // DISABLE GPP_CLK7 + RWMEM (GpioMmioAddr + SB_GPIO_REG172, AccWidthUint8, 0xBF, 0); // FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE + } + // } + + // + // BlueTooth control: BT_ON + // amdBlueTooth: CMOS, 0 - AUTO, 1 - DISABLE + // GPIO07: BT_ON, 0 - OFF, 1 - ON + // + if (!CONFIG_ONBOARD_BLUETOOTH) { + //- if (SystemConfiguration.amdBlueTooth == 1) { + RWMEM (GpioMmioAddr + SB_GPIO_REG07, AccWidthUint8, 0xBF, 0); + //- } + } + + // + // WebCam control: + // amdWebCam: CMOS, 0 - AUTO, 1 - DISABLE + // GPIO34: WEBCAM_ON#, 0 - ON, 1 - OFF + // + if (!CONFIG_ONBOARD_WEBCAM) { + //- if (SystemConfiguration.amdWebCam == 1) { + RWMEM (GpioMmioAddr + SB_GPIO_REG34, AccWidthUint8, 0xBF, BIT6); + //- } + } + + // + // Travis enable: + // amdTravisCtrl: CMOS, 0 - DISABLE, 1 - ENABLE + // GPIO66: TRAVIS_EN#, 0 - ENABLE, 1 - DISABLE + // + if (!CONFIG_ONBOARD_TRAVIS) { + //- if (SystemConfiguration.amdTravisCtrl == 0) { + RWMEM (GpioMmioAddr + SB_GPIO_REG66, AccWidthUint8, 0xBF, BIT6); + //- } + } + + // + // Disable Light Sensor if needed + // + if (CONFIG_ONBOARD_LIGHTSENSOR) { + //- if (SystemConfiguration.amdLightSensor == 1) { + RWMEM (IoMuxMmioAddr + SB_GEVENT_REG12, AccWidthUint8, 0x00, 0x1); + //- } + } + +} + + diff --git a/src/mainboard/amd/dinar/gpio.h b/src/mainboard/amd/dinar/gpio.h new file mode 100644 index 0000000..c936e50 --- /dev/null +++ b/src/mainboard/amd/dinar/gpio.h @@ -0,0 +1,2329 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + + +#ifndef _GPIO_H_ +#define _GPIO_H_ + +#include <stdint.h> +#include <cbtypes.h> + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +#define Mmio_Address( BaseAddr, Register ) \ + ( (UINTN)BaseAddr + \ + (UINTN)(Register) \ + ) + +#define Mmio32_Ptr( BaseAddr, Register ) \ + ( (volatile u32 *)Mmio_Address( BaseAddr, Register ) ) + +#define Mmio32_G( BaseAddr, Register ) \ + *Mmio32_Ptr( BaseAddr, Register ) + +#define Mmio32_And_Or( BaseAddr, Register, AndData, OrData ) \ + Mmio32_G( BaseAddr, Register ) = \ +(u32) ( \ + ( Mmio32_G( BaseAddr, Register ) & \ + (u32)(AndData) \ + ) | \ + (u32)(OrData) \ + ) + +#define Mmio8_Ptr( BaseAddr, Register ) \ + ( (volatile u8 *)Mmio_Address( BaseAddr, Register ) ) + +#define Mmio8_G( BaseAddr, Register ) \ + *Mmio8_Ptr( BaseAddr, Register ) + +#define Mmio8_And_Or( BaseAddr, Register, AndData, OrData ) \ + Mmio8_G( BaseAddr, Register ) = \ +(u8) ( \ + ( Mmio8_G( BaseAddr, Register ) & \ + (u8)(AndData) \ + ) | \ + (u8)(OrData) \ + ) + +#define SMIREG_EVENT_ENABLE 0x04 +#define SMIREG_SCITRIG 0x08 +#define SMIREG_SCILEVEL 0x0C +#define SMIREG_SMISCIEN 0x14 +#define SMIREG_SCIS0EN 0x20 +#define SMIREG_SCIMAP0 0x40 +#define SMIREG_SCIMAP1 0x44 +#define SMIREG_SCIMAP2 0x48 +#define SMIREG_SCIMAP3 0x4C +#define SMIREG_SCIMAP4 0x50 +#define SMIREG_SCIMAP5 0x54 +#define SMIREG_SCIMAP6 0x58 +#define SMIREG_SCIMAP7 0x5C +#define SMIREG_SCIMAP8 0x60 +#define SMIREG_SCIMAP9 0x64 +#define SMIREG_SCIMAP10 0x68 +#define SMIREG_SCIMAP11 0x6C +#define SMIREG_SCIMAP12 0x70 +#define SMIREG_SCIMAP13 0x74 +#define SMIREG_SCIMAP14 0x78 +#define SMIREG_SCIMAP15 0x7C +#define SMIREG_SMITRIG 0x98 +#define SMIREG_SMICONTROL0 0xA0 +#define SMIREG_SMICONTROL1 0xA4 + +#define FUNCTION0 0 +#define FUNCTION1 1 +#define FUNCTION2 2 +#define FUNCTION3 3 +#define NonGpio 0x80 // BIT7 + +// S0-domain General Purpose I/O: GPIO 00~67 +#define GPIO_00_SELECT FUNCTION1+NonGpio // MPCIE_RST1# for J3703, LOW ACTIVE, HIGH DEFAULT +#define GPIO_01_SELECT FUNCTION1+NonGpio // MPCIE_RST2# for J3711, LOW ACTIVE, HIGH DEFAULT +#define GPIO_02_SELECT FUNCTION1 // MPCIE_RST0# for J3700, LOW ACTIVE, HIGH DEFAULT +#define GPIO_03_SELECT FUNCTION1+NonGpio // NOT USED +#define GPIO_04_SELECT FUNCTION1+NonGpio // x1 gpp reset, for J3701, low active, HIGH DEFAULT +#define GPIO_05_SELECT FUNCTION1+NonGpio // express card reset, for J2500, low active, HIGH DEFAULT +#define GPIO_06_SELECT FUNCTION0+NonGpio //NOT USED +#define GPIO_07_SELECT FUNCTION1 // BT_ON, 1: BT ON(DEFAULT); 0: BT OFF +#define GPIO_08_SELECT FUNCTION1 // PEX_STD_SW#, 1:Low Level Mode(default); 0:Standard(desktop) Swing Level +#define GPIO_09_SELECT FUNCTION1+NonGpio // MXM_PRESENT2#, INPUT, LOW MEANS MXM IS INSTALLED +#define GPIO_10_SELECT FUNCTION1+NonGpio // MXM_PRESENT1#, INPUT, LOW MEANS MXM IS INSTALLED +#define GPIO_11_SELECT FUNCTION0+NonGpio // NOT USED +#define GPIO_12_SELECT FUNCTION1 // WL_DISABLE#, DISABLE THE WALN IN J3702 +#define GPIO_13_SELECT FUNCTION1 // WU_DISABLE#, DISABLE THE WUSB IN J3711 +#define GPIO_14_SELECT FUNCTION1 // WP_DISABLE, DISABLE THE WWAN IN J3703 +#define GPIO_15_SELECT FUNCTION1+NonGpio // NOT USED, //FUNCTION1, Reset_CEC# Low Active, High default +#define GPIO_16_SELECT FUNCTION0+NonGpio // NOT USED +#define GPIO_17_SELECT FUNCTION0+NonGpio // NOT USED +#define GPIO_18_SELECT FUNCTION0+NonGpio // NOT USED +#define GPIO_19_SELECT FUNCTION1 // For LASSO_DET# detection when Gevent14# is asserted. +#define GPIO_20_SELECT FUNCTION1 // PX_MUX for DOCKING card, PX MUX selection in mux mode. dGPU enable with high(option) +#define GPIO_21_SELECT FUNCTION1 // DOCK_MUX for DCKING card, MUX selection output. Docking display enabled when high(option) +#define GPIO_22_SELECT FUNCTION1 // SB_PWR_LV, INDICATE TO THE MXM THE SYSTEM IS IN LOW BATTERY MODE +// 1:BATTERY IS FINE(DEFAULT) +// 0:BATTERY IS LOW +#define GPIO_23_SELECT FUNCTION1 // CODEC_ON.1: CODEC ON (default)0: CODEC OFF +#define GPIO_24_SELECT FUNCTION1 // Travis reset,Low active High default +#define GPIO_25_SELECT FUNCTION1+NonGpio // PCIE_RST# for LAN (AND gate with PCIE_RST#); default high +#define GPIO_26_SELECT FUNCTION1+NonGpio // PCIE_RST# for USB3.0 (AND gate with PCIE_RST#); default high +#define GPIO_27_SELECT FUNCTION1+NonGpio // PCIE_RST# for 1394 (AND gate with PCIE_RST#); default high +#define GPIO_28_SELECT FUNCTION1 // MXM PWRGD INDICATOR, INPUT +#define GPIO_29_SELECT FUNCTION1 // MEM HOT, LOW ACTIVE, OUTPUT +#define GPIO_30_SELECT FUNCTION1 // INPUT, DEFINE THE BOARD REVISION 0 +#define GPIO_31_SELECT FUNCTION1 // INPUT, DEFINE THE BOARD REVISION 1 +// 00 - REVA +// 01 - REVB +// 10 - REVC +// 11 - REVD +#define GPIO_32_SELECT FUNCTION1+NonGpio // PCIE_SW - HIGH:MXM; LOW:LASSO +#define GPIO_33_SELECT FUNCTION1 // USB3.0 DETECT of Express Card:USB3.0_DET#, Low active. +// 0:USB3.0 I/F in Express CARD +// 1:PCIE I/F in Express CARD detection +#define GPIO_34_SELECT FUNCTION1 // WEBCAM_ON#. 0: ON (default) 1: OFF +#define GPIO_35_SELECT FUNCTION1 // ODD_DA_INTH# +#define GPIO_36_SELECT FUNCTION0+NonGpio // PCICLK FOR KBC +#define GPIO_37_SELECT FUNCTION0+NonGpio // NOT USED +#define GPIO_38_SELECT FUNCTION0+NonGpio // NOT USED +#define GPIO_39_SELECT FUNCTION0+NonGpio // NOT USED +#define GPIO_40_SELECT FUNCTION1 // For DOCK# detection when Gevent14# is asserted. +#define GPIO_41_SELECT FUNCTION1+NonGpio // 1394 CLK REQ# +#define GPIO_42_SELECT FUNCTION1+NonGpio // X4 GPP CLK REQ# +#define GPIO_43_SELECT FUNCTION0+NonGpio // SMBUS0, CLOCK +#define GPIO_44_SELECT FUNCTION1+NonGpio // PEGPIO0, RESET THE MXM MODULE +#define GPIO_45_SELECT FUNCTION2+NonGpio // PEGPIO1, 1:MXM IS POWER ON; 0:MXM IS OFF +#define GPIO_46_SELECT FUNCTION1+NonGpio // USB3.0_CLKREQ# +#define GPIO_47_SELECT FUNCTION0+NonGpio // SMBUS0, DATA +#define GPIO_48_SELECT FUNCTION0+NonGpio // SERIRQ +#define GPIO_49_SELECT FUNCTION0+NonGpio // LDRQ#1 +#define GPIO_50_SELECT FUNCTION2 // SMARTVOLTAGE TO CONTROL THE 5V - 1:5V; 0:4.56V +#define GPIO_51_SELECT FUNCTION0+NonGpio // back-up for SMARTVOLTAGE1 +#define GPIO_52_SELECT FUNCTION0+NonGpio // CPU FAN OUT +#define GPIO_53_SELECT FUNCTION1 // ODD POWER ENABLE, HIGH ACTIVE +#define GPIO_54_SELECT FUNCTION0+NonGpio // SB_PROCHOT, OUTPUT, LOW ACTIVE +#define GPIO_55_SELECT FUNCTION2+NonGpio // MXM POWER ENABLE(POWER ON MODULE) +// 1:ENABLE; 0:DISABLE +// DEFAULT VALUE DEPENDS ON GPIO 9 AND 10 +#define GPIO_56_SELECT FUNCTION0+NonGpio //HDD2_POWER/HDD0_POWER/CPU FAN ;CPU FAN +#define GPIO_57_SELECT FUNCTION1 // HDD0_POWER +#define GPIO_58_SELECT FUNCTION1 // HDD2_POWER +#define GPIO_59_SELECT FUNCTION2+NonGpio // 1394 POWER, OUTPUT, HIGH ACTIVE +#define GPIO_60_SELECT FUNCTION0+NonGpio // EXPCARD_CLKREQ# +#define GPIO_61_SELECT FUNCTION0+NonGpio // PE0_CLKREQ#, FROM J3700 +#define GPIO_62_SELECT FUNCTION0+NonGpio // PE2_CLKREQ#, FROM J3711 +#define GPIO_63_SELECT FUNCTION0+NonGpio // LAN_CLKREQ# +#define GPIO_64_SELECT FUNCTION0+NonGpio // PE1_CLKREQ#, FROM J3703 +#define GPIO_65_SELECT FUNCTION0+NonGpio // MXM CLK REQ#, FROM MXM +#define GPIO_66_SELECT FUNCTION1 // USED AS TRAVIS_EN#; 0:ENABLE as default +#define GPIO_67_SELECT FUNCTION0+NonGpio // USED AS SATA_ACT# +#define GPIO_68_SELECT FUNCTION0+NonGpio +#define GPIO_69_SELECT FUNCTION0+NonGpio +#define GPIO_70_SELECT FUNCTION0+NonGpio +#define GPIO_71_SELECT FUNCTION0+NonGpio +#define GPIO_72_SELECT FUNCTION0+NonGpio +#define GPIO_73_SELECT FUNCTION0+NonGpio +#define GPIO_74_SELECT FUNCTION0+NonGpio +#define GPIO_75_SELECT FUNCTION0+NonGpio +#define GPIO_76_SELECT FUNCTION0+NonGpio +#define GPIO_77_SELECT FUNCTION0+NonGpio +#define GPIO_78_SELECT FUNCTION0+NonGpio +#define GPIO_79_SELECT FUNCTION0+NonGpio +#define GPIO_80_SELECT FUNCTION0+NonGpio +#define GPIO_81_SELECT FUNCTION0+NonGpio +#define GPIO_82_SELECT FUNCTION0+NonGpio +#define GPIO_83_SELECT FUNCTION0+NonGpio +#define GPIO_84_SELECT FUNCTION0+NonGpio +#define GPIO_85_SELECT FUNCTION0+NonGpio +#define GPIO_86_SELECT FUNCTION0+NonGpio +#define GPIO_87_SELECT FUNCTION0+NonGpio +#define GPIO_88_SELECT FUNCTION0+NonGpio +#define GPIO_89_SELECT FUNCTION0+NonGpio +#define GPIO_90_SELECT FUNCTION0+NonGpio +#define GPIO_91_SELECT FUNCTION0+NonGpio +#define GPIO_92_SELECT FUNCTION0+NonGpio +#define GPIO_93_SELECT FUNCTION0+NonGpio +#define GPIO_94_SELECT FUNCTION0+NonGpio +#define GPIO_95_SELECT FUNCTION0+NonGpio +// GEVENT 00~23 are mapped to GPIO 96~119 +#define GPIO_96_SELECT FUNCTION0 // GA20IN/GEVENT0# +#define GPIO_97_SELECT FUNCTION0 // KBRST#/GEVENT1# +#define GPIO_98_SELECT FUNCTION0 // THRMTRIP#/SMBALERT#/GEVENT2# -> APU_THERMTRIP +#define GPIO_99_SELECT FUNCTION1 // LPC_PME#/GEVENT3# -> EC_SCI# +#define GPIO_100_SELECT FUNCTION2 // PCIE_RST2#/PCI_PME#/GEVENT4# -> APU_MEMHOT# +#define GPIO_101_SELECT FUNCTION1 // LPC_PD#/GEVENT5# -> hotplug of express card, low active +#define GPIO_102_SELECT FUNCTION0+NonGpio // USB_OC6#/IR_TX1/ GEVENT6# -> NOT USED, +// there is a confliction to IR function when this pin is as a GEVENT. +#define GPIO_103_SELECT FUNCTION0+NonGpio // DDR3_RST#/GEVENT7#/VGA_PD -> VGA_PD, +// special pin difination for SB700 VGA OUTPUT, high active, +// VGA power for Hudson-M2 will be down when it was asserted. +#define GPIO_104_SELECT FUNCTION0 // WAKE#/GEVENT8# -> WAKEUP, low active +#define GPIO_105_SELECT FUNCTION2 // SPI_HOLD/GBE_LED1/GEVENT9# - WF_RADIO (wireless radio) +#define GPIO_106_SELECT FUNCTION0 // GBE_LED2/GEVENT10# -> GBE_LED2 +#define GPIO_107_SELECT FUNCTION0+NonGpio // GBE_STAT0/GEVENT11# -> GBE_STAT0 +#define GPIO_108_SELECT FUNCTION2 // USB_OC0#/TRST#/GEVENT12# -> SMBALERT# (Light Sensor), low active +// [option for SPI_TPM_CS# in Hudson-M2 A12)] +#define GPIO_109_SELECT FUNCTION0 // USB_OC1#/TDI/GEVENT13# - USB OC for 0, 1,2,3 & USB_OC expresscard (usb4) & +// USB3.0 PORT0,1:low active,disable all usb ports and new card power at a same time +#define GPIO_110_SELECT FUNCTION2 // USB_OC2#/TCK/GEVENT14# -> Lasso detect or Dock detect, +// plus judge GPIO40 and GPIO19 level,low is assert. +// LASSO_DET# :0 & GPIO19:0 -----> LASSO is present (default) +// DOCK#:0 & GPIO40:0 -----------> DOCK is present(option) +#define GPIO_111_SELECT FUNCTION1+NonGpio // USB_OC3#/AC_PRES/TDO/GEVENT15# -> AC_PRES, high active +#define GPIO_112_SELECT FUNCTION2 // USB_OC4#/IR_RX0/GEVENT16# -> ODD_DA, ODD device attention, +// low active, when it's low, BIOS will enbale ODD_PWR +#define GPIO_113_SELECT FUNCTION2 // USB_OC5#/IR_TX0/GEVENT17# -> use TWARN mapping to trigger GEVENT17# +#define GPIO_114_SELECT FUNCTION2 // BLINK/USB_OC7#/GEVENT18# -> BLINK +#define GPIO_115_SELECT FUNCTION0 // SYS_RESET#/GEVENT19# -> SYS_RST# +#define GPIO_116_SELECT FUNCTION0 // R_RX1/GEVENT20# -> IR INPUT +#define GPIO_117_SELECT FUNCTION1+NonGpio // SPI_CS3#/GBE_STAT1/GEVENT21# -> GBE_STAT1 +#define GPIO_118_SELECT FUNCTION1 // RI#/GEVENT22# -> LID_CLOSED# +#define GPIO_119_SELECT FUNCTION0 // LPC_SMI#/GEVENT23# -> EC_SMI +#define GPIO_120_SELECT FUNCTION0+NonGpio +#define GPIO_121_SELECT FUNCTION0+NonGpio +#define GPIO_122_SELECT FUNCTION0+NonGpio +#define GPIO_123_SELECT FUNCTION0+NonGpio +#define GPIO_124_SELECT FUNCTION0+NonGpio +#define GPIO_125_SELECT FUNCTION0+NonGpio +#define GPIO_126_SELECT FUNCTION0+NonGpio +#define GPIO_127_SELECT FUNCTION0+NonGpio +#define GPIO_128_SELECT FUNCTION0+NonGpio +#define GPIO_129_SELECT FUNCTION0+NonGpio +#define GPIO_130_SELECT FUNCTION0+NonGpio +#define GPIO_131_SELECT FUNCTION0+NonGpio +#define GPIO_132_SELECT FUNCTION0+NonGpio +#define GPIO_133_SELECT FUNCTION0+NonGpio +#define GPIO_134_SELECT FUNCTION0+NonGpio +#define GPIO_135_SELECT FUNCTION0+NonGpio +#define GPIO_136_SELECT FUNCTION0+NonGpio +#define GPIO_137_SELECT FUNCTION0+NonGpio +#define GPIO_138_SELECT FUNCTION0+NonGpio +#define GPIO_139_SELECT FUNCTION0+NonGpio +#define GPIO_140_SELECT FUNCTION0+NonGpio +#define GPIO_141_SELECT FUNCTION0+NonGpio +#define GPIO_142_SELECT FUNCTION0+NonGpio +#define GPIO_143_SELECT FUNCTION0+NonGpio +#define GPIO_144_SELECT FUNCTION0+NonGpio +#define GPIO_145_SELECT FUNCTION0+NonGpio +#define GPIO_146_SELECT FUNCTION0+NonGpio +#define GPIO_147_SELECT FUNCTION0+NonGpio +#define GPIO_148_SELECT FUNCTION0+NonGpio +#define GPIO_149_SELECT FUNCTION0+NonGpio +#define GPIO_150_SELECT FUNCTION0+NonGpio +#define GPIO_151_SELECT FUNCTION0+NonGpio +#define GPIO_152_SELECT FUNCTION0+NonGpio +#define GPIO_153_SELECT FUNCTION0+NonGpio +#define GPIO_154_SELECT FUNCTION0+NonGpio +#define GPIO_155_SELECT FUNCTION0+NonGpio +#define GPIO_156_SELECT FUNCTION0+NonGpio +#define GPIO_157_SELECT FUNCTION0+NonGpio +#define GPIO_158_SELECT FUNCTION0+NonGpio +#define GPIO_159_SELECT FUNCTION0+NonGpio +#define GPIO_160_SELECT FUNCTION0+NonGpio + +// S5-domain General Purpose I/O +#define GPIO_161_SELECT FUNCTION0+NonGpio // ROM_RST# +#define GPIO_162_SELECT FUNCTION0+NonGpio // SPI ROM +#define GPIO_163_SELECT FUNCTION0+NonGpio // SPI ROM +#define GPIO_164_SELECT FUNCTION0+NonGpio // SPI ROM +#define GPIO_165_SELECT FUNCTION0+NonGpio // SPI ROM +#define GPIO_166_SELECT FUNCTION1+NonGpio // GBE_STAT2 +#define GPIO_167_SELECT FUNCTION0+NonGpio // AZ_SDATA_IN0 +#define GPIO_168_SELECT FUNCTION0+NonGpio // AZ_SDATA_IN1 +#define GPIO_169_SELECT FUNCTION0+NonGpio // AZ_SDATA_IN2 +#define GPIO_170_SELECT FUNCTION1+NonGpio // gating the power control signal for ODD, see BIOS requirements doc for detail. +#define GPIO_171_SELECT FUNCTION0+NonGpio // TEMPIN0, +#define GPIO_172_SELECT FUNCTION1 // used as FCH_USB3.0PORT_EN# - 0:ENABLE; 1:DISABLE +#define GPIO_173_SELECT FUNCTION0+NonGpio // TEMPIN3 +#define GPIO_174_SELECT FUNCTION1+NonGpio // USED AS TALERT# +#define GPIO_175_SELECT FUNCTION1 // WLAN, WIRELESS DISABLE 1:DISABLE; 0:ENABLE +#define GPIO_176_SELECT FUNCTION1+NonGpio // WWAN, WIRELESS DISABLE 1:DISABLE; 0:ENABLE +#define GPIO_177_SELECT FUNCTION2+NonGpio // WUSB, WIRELESS DISABLE 1:DISABLE; 0:ENABLE +#define GPIO_178_SELECT FUNCTION2 // MEM_1V5 +#define GPIO_179_SELECT FUNCTION2 // MEM_1V35 +#define GPIO_180_SELECT FUNCTION0+NonGpio // Use as VIN VDDIO +#define GPIO_181_SELECT FUNCTION0+NonGpio // Use as VIN VDDR +#define GPIO_182_SELECT FUNCTION1+NonGpio // GBE_LED3 +#define GPIO_183_SELECT FUNCTION0+NonGpio // GBE_LED0 +#define GPIO_184_SELECT FUNCTION1+NonGpio // USED AS LLB# +#define GPIO_185_SELECT FUNCTION0+NonGpio // USED AS USB +#define GPIO_186_SELECT FUNCTION0+NonGpio // USED AS USB +#define GPIO_187_SELECT FUNCTION2 // USED AS AC LED INDICATOR, LOW ACTIVE +#define GPIO_188_SELECT FUNCTION2 // default used AS BATT LED INDICATOR, LOW ACTIVE +// option for HDMI CEC signal OW ACTIVE +#define GPIO_189_SELECT FUNCTION1 // USED AS AC_OK RECIEVER, INPUT, low active +#define GPIO_190_SELECT FUNCTION1 // USED TO MONITER INTERUPT FROM BATT CHARGER, INPUT +#define GPIO_191_SELECT FUNCTION0+NonGpio // TOUCH PAD, DATA +#define GPIO_192_SELECT FUNCTION0+NonGpio // TOUCH PAD, CLK +#define GPIO_193_SELECT FUNCTION0+NonGpio // SMBUS CLK, +#define GPIO_194_SELECT FUNCTION0+NonGpio // SMBUS, DATA +#define GPIO_195_SELECT FUNCTION0+NonGpio // SMBUS CLK, +#define GPIO_196_SELECT FUNCTION0+NonGpio // SMBUS, DATA +#define GPIO_197_SELECT FUNCTION2+NonGpio // Default GPIO for LOM_POWER, high active +// RESERVED FOR LCD BACKLIGHT PWM +#define GPIO_198_SELECT FUNCTION0+NonGpio // IMC SCROLL LED CONTROL +#define GPIO_199_SELECT FUNCTION3 // STRAP TO SELECT BOOT ROM - H:LPC ROM L: SPI ROM +#define GPIO_200_SELECT FUNCTION2 // NEC USB3.0 POWER CONTROL 1:ON(DEFAULT); 0:OFF +#define GPIO_201_SELECT FUNCTION0+NonGpio // KSI +#define GPIO_202_SELECT FUNCTION0+NonGpio // KSI +#define GPIO_203_SELECT FUNCTION0+NonGpio // KSI +#define GPIO_204_SELECT FUNCTION0+NonGpio // KSI +#define GPIO_205_SELECT FUNCTION0+NonGpio // KSI +#define GPIO_206_SELECT FUNCTION0+NonGpio // KSI +#define GPIO_207_SELECT FUNCTION0+NonGpio // KSI +#define GPIO_208_SELECT FUNCTION0+NonGpio // KSI +#define GPIO_209_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_210_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_211_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_212_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_213_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_214_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_215_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_216_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_217_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_218_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_219_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_220_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_221_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_222_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_223_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_224_SELECT FUNCTION0+NonGpio // KSO +#define GPIO_225_SELECT FUNCTION2+NonGpio // KSO +#define GPIO_226_SELECT FUNCTION2+NonGpio // KSO +#define GPIO_227_SELECT FUNCTION0+NonGpio // SMBUS CLK, +#define GPIO_228_SELECT FUNCTION0+NonGpio // SMBUS, DATA +#define GPIO_229_SELECT FUNCTION0+NonGpio // DP1_HPD + +#define TYPE_GPI (1<<5) +#define TYPE_GPO (0<<5) + +#define GPIO_00_TYPE TYPE_GPO +#define GPIO_01_TYPE TYPE_GPO +#define GPIO_02_TYPE TYPE_GPO +#define GPIO_03_TYPE TYPE_GPO +#define GPIO_04_TYPE TYPE_GPO +#define GPIO_05_TYPE TYPE_GPO +#define GPIO_06_TYPE TYPE_GPO +#define GPIO_07_TYPE TYPE_GPO +#define GPIO_08_TYPE TYPE_GPO +#define GPIO_09_TYPE TYPE_GPI +#define GPIO_10_TYPE TYPE_GPI +#define GPIO_11_TYPE TYPE_GPO +#define GPIO_12_TYPE TYPE_GPO +#define GPIO_13_TYPE TYPE_GPO +#define GPIO_14_TYPE TYPE_GPO +#define GPIO_15_TYPE TYPE_GPO +#define GPIO_16_TYPE TYPE_GPO +#define GPIO_17_TYPE TYPE_GPO +#define GPIO_18_TYPE TYPE_GPO +#define GPIO_19_TYPE TYPE_GPO +#define GPIO_20_TYPE TYPE_GPO +#define GPIO_21_TYPE TYPE_GPO +#define GPIO_22_TYPE TYPE_GPO +#define GPIO_23_TYPE TYPE_GPO +#define GPIO_24_TYPE TYPE_GPO +#define GPIO_25_TYPE TYPE_GPO +#define GPIO_26_TYPE TYPE_GPO +#define GPIO_27_TYPE TYPE_GPO +#define GPIO_28_TYPE TYPE_GPI +#define GPIO_29_TYPE TYPE_GPO +#define GPIO_30_TYPE TYPE_GPI +#define GPIO_31_TYPE TYPE_GPI +#define GPIO_32_TYPE TYPE_GPO +#define GPIO_33_TYPE TYPE_GPI +#define GPIO_34_TYPE TYPE_GPO +#define GPIO_35_TYPE TYPE_GPO +#define GPIO_36_TYPE TYPE_GPO +#define GPIO_37_TYPE TYPE_GPO +#define GPIO_38_TYPE TYPE_GPO +#define GPIO_39_TYPE TYPE_GPO +#define GPIO_40_TYPE TYPE_GPO +#define GPIO_41_TYPE TYPE_GPI +#define GPIO_42_TYPE TYPE_GPI +#define GPIO_43_TYPE TYPE_GPO +#define GPIO_44_TYPE TYPE_GPO +#define GPIO_45_TYPE TYPE_GPO +#define GPIO_46_TYPE TYPE_GPI +#define GPIO_47_TYPE TYPE_GPO +#define GPIO_48_TYPE TYPE_GPO +#define GPIO_49_TYPE TYPE_GPO +#define GPIO_50_TYPE TYPE_GPO +#define GPIO_51_TYPE TYPE_GPO +#define GPIO_52_TYPE TYPE_GPO +#define GPIO_53_TYPE TYPE_GPO +#define GPIO_54_TYPE TYPE_GPO +#define GPIO_55_TYPE TYPE_GPO +#define GPIO_56_TYPE TYPE_GPI +#define GPIO_57_TYPE TYPE_GPO +#define GPIO_58_TYPE TYPE_GPO +#define GPIO_59_TYPE TYPE_GPO +#define GPIO_60_TYPE TYPE_GPI +#define GPIO_61_TYPE TYPE_GPI +#define GPIO_62_TYPE TYPE_GPI +#define GPIO_63_TYPE TYPE_GPI +#define GPIO_64_TYPE TYPE_GPI +#define GPIO_65_TYPE TYPE_GPI +#define GPIO_66_TYPE TYPE_GPO +#define GPIO_67_TYPE TYPE_GPO +#define GPIO_68_TYPE TYPE_GPO +#define GPIO_69_TYPE TYPE_GPO +#define GPIO_70_TYPE TYPE_GPO +#define GPIO_71_TYPE TYPE_GPO +#define GPIO_72_TYPE TYPE_GPO +#define GPIO_73_TYPE TYPE_GPO +#define GPIO_74_TYPE TYPE_GPO +#define GPIO_75_TYPE TYPE_GPO +#define GPIO_76_TYPE TYPE_GPO +#define GPIO_77_TYPE TYPE_GPO +#define GPIO_78_TYPE TYPE_GPO +#define GPIO_79_TYPE TYPE_GPO +#define GPIO_80_TYPE TYPE_GPO +#define GPIO_81_TYPE TYPE_GPO +#define GPIO_82_TYPE TYPE_GPO +#define GPIO_83_TYPE TYPE_GPO +#define GPIO_84_TYPE TYPE_GPO +#define GPIO_85_TYPE TYPE_GPO +#define GPIO_86_TYPE TYPE_GPO +#define GPIO_87_TYPE TYPE_GPO +#define GPIO_88_TYPE TYPE_GPO +#define GPIO_89_TYPE TYPE_GPO +#define GPIO_90_TYPE TYPE_GPO +#define GPIO_91_TYPE TYPE_GPO +#define GPIO_92_TYPE TYPE_GPO +#define GPIO_93_TYPE TYPE_GPO +#define GPIO_94_TYPE TYPE_GPO +#define GPIO_95_TYPE TYPE_GPO + +// GEVENT 00 ~ 23 are mapped to GPIO 96 ~ 119 +#define GPIO_96_TYPE TYPE_GPI +#define GPIO_97_TYPE TYPE_GPI +#define GPIO_98_TYPE TYPE_GPI +#define GPIO_99_TYPE TYPE_GPI +#define GPIO_100_TYPE TYPE_GPI +#define GPIO_101_TYPE TYPE_GPI +#define GPIO_102_TYPE TYPE_GPO +#define GPIO_103_TYPE TYPE_GPO +#define GPIO_104_TYPE TYPE_GPI +#define GPIO_105_TYPE TYPE_GPI +#define GPIO_106_TYPE TYPE_GPO +#define GPIO_107_TYPE TYPE_GPI +#define GPIO_108_TYPE TYPE_GPI +#define GPIO_109_TYPE TYPE_GPI +#define GPIO_110_TYPE TYPE_GPI +#define GPIO_111_TYPE TYPE_GPI +#define GPIO_112_TYPE TYPE_GPI +#define GPIO_113_TYPE TYPE_GPI +#define GPIO_114_TYPE TYPE_GPO +#define GPIO_115_TYPE TYPE_GPI +#define GPIO_116_TYPE TYPE_GPI +#define GPIO_117_TYPE TYPE_GPI +#define GPIO_118_TYPE TYPE_GPI +#define GPIO_119_TYPE TYPE_GPI + +#define GPIO_120_TYPE TYPE_GPO +#define GPIO_121_TYPE TYPE_GPO +#define GPIO_122_TYPE TYPE_GPO +#define GPIO_123_TYPE TYPE_GPO +#define GPIO_124_TYPE TYPE_GPO +#define GPIO_125_TYPE TYPE_GPO +#define GPIO_126_TYPE TYPE_GPO +#define GPIO_127_TYPE TYPE_GPO +#define GPIO_128_TYPE TYPE_GPO +#define GPIO_129_TYPE TYPE_GPO +#define GPIO_130_TYPE TYPE_GPO +#define GPIO_131_TYPE TYPE_GPO +#define GPIO_132_TYPE TYPE_GPO +#define GPIO_133_TYPE TYPE_GPO +#define GPIO_134_TYPE TYPE_GPO +#define GPIO_135_TYPE TYPE_GPO +#define GPIO_136_TYPE TYPE_GPO +#define GPIO_137_TYPE TYPE_GPO +#define GPIO_138_TYPE TYPE_GPO +#define GPIO_139_TYPE TYPE_GPO +#define GPIO_140_TYPE TYPE_GPO +#define GPIO_141_TYPE TYPE_GPO +#define GPIO_142_TYPE TYPE_GPO +#define GPIO_143_TYPE TYPE_GPO +#define GPIO_144_TYPE TYPE_GPO +#define GPIO_145_TYPE TYPE_GPO +#define GPIO_146_TYPE TYPE_GPO +#define GPIO_147_TYPE TYPE_GPO +#define GPIO_148_TYPE TYPE_GPO +#define GPIO_149_TYPE TYPE_GPO +#define GPIO_150_TYPE TYPE_GPO +#define GPIO_151_TYPE TYPE_GPO +#define GPIO_152_TYPE TYPE_GPO +#define GPIO_153_TYPE TYPE_GPO +#define GPIO_154_TYPE TYPE_GPO +#define GPIO_155_TYPE TYPE_GPO +#define GPIO_156_TYPE TYPE_GPO +#define GPIO_157_TYPE TYPE_GPO +#define GPIO_158_TYPE TYPE_GPO +#define GPIO_159_TYPE TYPE_GPO +#define GPIO_160_TYPE TYPE_GPO +#define GPIO_161_TYPE TYPE_GPO +#define GPIO_162_TYPE TYPE_GPO +#define GPIO_163_TYPE TYPE_GPO +#define GPIO_164_TYPE TYPE_GPI +#define GPIO_165_TYPE TYPE_GPO +#define GPIO_166_TYPE TYPE_GPI +#define GPIO_167_TYPE TYPE_GPI +#define GPIO_168_TYPE TYPE_GPI +#define GPIO_169_TYPE TYPE_GPI +#define GPIO_170_TYPE TYPE_GPO +#define GPIO_171_TYPE TYPE_GPI +#define GPIO_172_TYPE TYPE_GPO +#define GPIO_173_TYPE TYPE_GPI +#define GPIO_174_TYPE TYPE_GPI +#define GPIO_175_TYPE TYPE_GPO +#define GPIO_176_TYPE TYPE_GPO +#define GPIO_177_TYPE TYPE_GPO +#define GPIO_178_TYPE TYPE_GPO +#define GPIO_179_TYPE TYPE_GPO +#define GPIO_180_TYPE TYPE_GPO +#define GPIO_181_TYPE TYPE_GPO +#define GPIO_182_TYPE TYPE_GPO +#define GPIO_183_TYPE TYPE_GPO +#define GPIO_184_TYPE TYPE_GPI +#define GPIO_185_TYPE TYPE_GPO +#define GPIO_186_TYPE TYPE_GPO +#define GPIO_187_TYPE TYPE_GPO +#define GPIO_188_TYPE TYPE_GPO +#define GPIO_189_TYPE TYPE_GPI +#define GPIO_190_TYPE TYPE_GPI +#define GPIO_191_TYPE TYPE_GPO +#define GPIO_192_TYPE TYPE_GPO +#define GPIO_193_TYPE TYPE_GPO +#define GPIO_194_TYPE TYPE_GPO +#define GPIO_195_TYPE TYPE_GPO +#define GPIO_196_TYPE TYPE_GPO +#define GPIO_197_TYPE TYPE_GPO +#define GPIO_198_TYPE TYPE_GPO +#define GPIO_199_TYPE TYPE_GPI +#define GPIO_200_TYPE TYPE_GPO +#define GPIO_201_TYPE TYPE_GPI +#define GPIO_202_TYPE TYPE_GPI +#define GPIO_203_TYPE TYPE_GPI +#define GPIO_204_TYPE TYPE_GPI +#define GPIO_205_TYPE TYPE_GPI +#define GPIO_206_TYPE TYPE_GPI +#define GPIO_207_TYPE TYPE_GPI +#define GPIO_208_TYPE TYPE_GPI +#define GPIO_209_TYPE TYPE_GPO +#define GPIO_210_TYPE TYPE_GPO +#define GPIO_211_TYPE TYPE_GPO +#define GPIO_212_TYPE TYPE_GPO +#define GPIO_213_TYPE TYPE_GPO +#define GPIO_214_TYPE TYPE_GPO +#define GPIO_215_TYPE TYPE_GPO +#define GPIO_216_TYPE TYPE_GPO +#define GPIO_217_TYPE TYPE_GPO +#define GPIO_218_TYPE TYPE_GPO +#define GPIO_219_TYPE TYPE_GPO +#define GPIO_220_TYPE TYPE_GPO +#define GPIO_221_TYPE TYPE_GPO +#define GPIO_222_TYPE TYPE_GPO +#define GPIO_223_TYPE TYPE_GPO +#define GPIO_224_TYPE TYPE_GPO +#define GPIO_225_TYPE TYPE_GPO +#define GPIO_226_TYPE TYPE_GPO +#define GPIO_227_TYPE TYPE_GPO +#define GPIO_228_TYPE TYPE_GPO +#define GPIO_229_TYPE TYPE_GPO + +#define GPO_LOW (0<<6) +#define GPO_HI (1<<6) + +#define GPO_00_LEVEL GPO_HI +#define GPO_01_LEVEL GPO_HI +#define GPO_02_LEVEL GPO_HI +#define GPO_03_LEVEL GPO_HI +#define GPO_04_LEVEL GPO_HI +#define GPO_05_LEVEL GPO_HI +#define GPO_06_LEVEL GPO_HI +#define GPO_07_LEVEL GPO_HI +#define GPO_08_LEVEL GPO_HI +#define GPO_09_LEVEL GPO_LOW +#define GPO_10_LEVEL GPO_LOW +#define GPO_11_LEVEL GPO_HI +#define GPO_12_LEVEL GPO_HI +#define GPO_13_LEVEL GPO_HI +#define GPO_14_LEVEL GPO_HI +#define GPO_15_LEVEL GPO_HI +#define GPO_16_LEVEL GPO_HI +#define GPO_17_LEVEL GPO_HI +#define GPO_18_LEVEL GPO_HI +#define GPO_19_LEVEL GPO_LOW +#define GPO_20_LEVEL GPO_LOW +#define GPO_21_LEVEL GPO_LOW +#define GPO_22_LEVEL GPO_HI +#define GPO_23_LEVEL GPO_HI +#define GPO_24_LEVEL GPO_HI +#define GPO_25_LEVEL GPO_HI +#define GPO_26_LEVEL GPO_HI +#define GPO_27_LEVEL GPO_HI +#define GPO_28_LEVEL GPO_LOW +#define GPO_29_LEVEL GPO_HI +#define GPO_30_LEVEL GPO_LOW +#define GPO_31_LEVEL GPO_LOW +#define GPO_32_LEVEL GPO_HI +#define GPO_33_LEVEL GPO_LOW +#define GPO_34_LEVEL GPO_LOW +#define GPO_35_LEVEL GPO_LOW +#define GPO_36_LEVEL GPO_LOW +#define GPO_37_LEVEL GPO_HI +#define GPO_38_LEVEL GPO_HI +#define GPO_39_LEVEL GPO_HI +#define GPO_40_LEVEL GPO_LOW +#define GPO_41_LEVEL GPO_LOW +#define GPO_42_LEVEL GPO_LOW +#define GPO_43_LEVEL GPO_LOW +#define GPO_44_LEVEL GPO_HI +#define GPO_45_LEVEL GPO_HI +#define GPO_46_LEVEL GPO_LOW +#define GPO_47_LEVEL GPO_LOW +#define GPO_48_LEVEL GPO_LOW +#define GPO_49_LEVEL GPO_HI +#define GPO_50_LEVEL GPO_HI +#define GPO_51_LEVEL GPO_LOW +#define GPO_52_LEVEL GPO_HI +#define GPO_53_LEVEL GPO_HI +#define GPO_54_LEVEL GPO_LOW +#define GPO_55_LEVEL GPO_LOW +#define GPO_56_LEVEL GPO_LOW +#define GPO_57_LEVEL GPO_HI +#define GPO_58_LEVEL GPO_HI +#define GPO_59_LEVEL GPO_HI +#define GPO_60_LEVEL GPO_LOW +#define GPO_61_LEVEL GPO_LOW +#define GPO_62_LEVEL GPO_LOW +#define GPO_63_LEVEL GPO_LOW +#define GPO_64_LEVEL GPO_LOW +#define GPO_65_LEVEL GPO_LOW +#define GPO_66_LEVEL GPO_LOW +#define GPO_67_LEVEL GPO_LOW +#define GPO_68_LEVEL GPO_LOW +#define GPO_69_LEVEL GPO_LOW +#define GPO_70_LEVEL GPO_LOW +#define GPO_71_LEVEL GPO_LOW +#define GPO_72_LEVEL GPO_LOW +#define GPO_73_LEVEL GPO_LOW +#define GPO_74_LEVEL GPO_LOW +#define GPO_75_LEVEL GPO_LOW +#define GPO_76_LEVEL GPO_LOW +#define GPO_77_LEVEL GPO_LOW +#define GPO_78_LEVEL GPO_LOW +#define GPO_79_LEVEL GPO_LOW +#define GPO_80_LEVEL GPO_LOW +#define GPO_81_LEVEL GPO_LOW +#define GPO_82_LEVEL GPO_LOW +#define GPO_83_LEVEL GPO_LOW +#define GPO_84_LEVEL GPO_LOW +#define GPO_85_LEVEL GPO_LOW +#define GPO_86_LEVEL GPO_LOW +#define GPO_87_LEVEL GPO_LOW +#define GPO_88_LEVEL GPO_LOW +#define GPO_89_LEVEL GPO_LOW +#define GPO_90_LEVEL GPO_LOW +#define GPO_91_LEVEL GPO_LOW +#define GPO_92_LEVEL GPO_LOW +#define GPO_93_LEVEL GPO_LOW +#define GPO_94_LEVEL GPO_LOW +#define GPO_95_LEVEL GPO_LOW +#define GPO_96_LEVEL GPO_LOW +#define GPO_97_LEVEL GPO_LOW +#define GPO_98_LEVEL GPO_LOW +#define GPO_99_LEVEL GPO_LOW +#define GPO_100_LEVEL GPO_LOW +#define GPO_101_LEVEL GPO_LOW +#define GPO_102_LEVEL GPO_LOW +#define GPO_103_LEVEL GPO_LOW +#define GPO_104_LEVEL GPO_LOW +#define GPO_105_LEVEL GPO_LOW +#define GPO_106_LEVEL GPO_LOW +#define GPO_107_LEVEL GPO_LOW +#define GPO_108_LEVEL GPO_HI +#define GPO_109_LEVEL GPO_LOW +#define GPO_110_LEVEL GPO_HI +#define GPO_111_LEVEL GPO_HI +#define GPO_112_LEVEL GPO_HI +#define GPO_113_LEVEL GPO_LOW +#define GPO_114_LEVEL GPO_LOW +#define GPO_115_LEVEL GPO_LOW +#define GPO_116_LEVEL GPO_LOW +#define GPO_117_LEVEL GPO_LOW +#define GPO_118_LEVEL GPO_LOW +#define GPO_119_LEVEL GPO_LOW +#define GPO_120_LEVEL GPO_LOW +#define GPO_121_LEVEL GPO_LOW +#define GPO_122_LEVEL GPO_LOW +#define GPO_123_LEVEL GPO_LOW +#define GPO_124_LEVEL GPO_LOW +#define GPO_125_LEVEL GPO_LOW +#define GPO_126_LEVEL GPO_LOW +#define GPO_127_LEVEL GPO_LOW +#define GPO_128_LEVEL GPO_LOW +#define GPO_129_LEVEL GPO_LOW +#define GPO_130_LEVEL GPO_LOW +#define GPO_131_LEVEL GPO_LOW +#define GPO_132_LEVEL GPO_LOW +#define GPO_133_LEVEL GPO_LOW +#define GPO_134_LEVEL GPO_LOW +#define GPO_135_LEVEL GPO_LOW +#define GPO_136_LEVEL GPO_LOW +#define GPO_137_LEVEL GPO_LOW +#define GPO_138_LEVEL GPO_LOW +#define GPO_139_LEVEL GPO_LOW +#define GPO_140_LEVEL GPO_LOW +#define GPO_141_LEVEL GPO_LOW +#define GPO_142_LEVEL GPO_LOW +#define GPO_143_LEVEL GPO_LOW +#define GPO_144_LEVEL GPO_LOW +#define GPO_145_LEVEL GPO_LOW +#define GPO_146_LEVEL GPO_LOW +#define GPO_147_LEVEL GPO_LOW +#define GPO_148_LEVEL GPO_LOW +#define GPO_149_LEVEL GPO_LOW +#define GPO_150_LEVEL GPO_LOW +#define GPO_151_LEVEL GPO_LOW +#define GPO_152_LEVEL GPO_LOW +#define GPO_153_LEVEL GPO_LOW +#define GPO_154_LEVEL GPO_LOW +#define GPO_155_LEVEL GPO_LOW +#define GPO_156_LEVEL GPO_LOW +#define GPO_157_LEVEL GPO_LOW +#define GPO_158_LEVEL GPO_LOW +#define GPO_159_LEVEL GPO_LOW +#define GPO_160_LEVEL GPO_LOW +#define GPO_161_LEVEL GPO_LOW +#define GPO_162_LEVEL GPO_LOW +#define GPO_163_LEVEL GPO_LOW +#define GPO_164_LEVEL GPO_LOW +#define GPO_165_LEVEL GPO_LOW +#define GPO_166_LEVEL GPO_LOW +#define GPO_167_LEVEL GPO_LOW +#define GPO_168_LEVEL GPO_LOW +#define GPO_169_LEVEL GPO_LOW +#define GPO_170_LEVEL GPO_HI +#define GPO_171_LEVEL GPO_LOW +#define GPO_172_LEVEL GPO_HI // FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE +#define GPO_173_LEVEL GPO_LOW +#define GPO_174_LEVEL GPO_LOW +#define GPO_175_LEVEL GPO_LOW +#define GPO_176_LEVEL GPO_LOW +#define GPO_177_LEVEL GPO_LOW +#define GPO_178_LEVEL GPO_HI // AMD.SR BU to set VDDIO level to 1.5V for Barb BU +#define GPO_179_LEVEL GPO_HI +#define GPO_180_LEVEL GPO_HI +#define GPO_181_LEVEL GPO_LOW +#define GPO_182_LEVEL GPO_HI +#define GPO_183_LEVEL GPO_LOW +#define GPO_184_LEVEL GPO_LOW +#define GPO_185_LEVEL GPO_LOW +#define GPO_186_LEVEL GPO_LOW +#define GPO_187_LEVEL GPO_LOW +#define GPO_188_LEVEL GPO_LOW +#define GPO_189_LEVEL GPO_LOW +#define GPO_190_LEVEL GPO_LOW +#define GPO_191_LEVEL GPO_LOW +#define GPO_192_LEVEL GPO_LOW +#define GPO_193_LEVEL GPO_LOW +#define GPO_194_LEVEL GPO_LOW +#define GPO_195_LEVEL GPO_LOW +#define GPO_196_LEVEL GPO_LOW +#define GPO_197_LEVEL GPO_LOW +#define GPO_198_LEVEL GPO_LOW +#define GPO_199_LEVEL GPO_LOW +#define GPO_200_LEVEL GPO_HI +#define GPO_201_LEVEL GPO_LOW +#define GPO_202_LEVEL GPO_LOW +#define GPO_203_LEVEL GPO_LOW +#define GPO_204_LEVEL GPO_LOW +#define GPO_205_LEVEL GPO_LOW +#define GPO_206_LEVEL GPO_LOW +#define GPO_207_LEVEL GPO_LOW +#define GPO_208_LEVEL GPO_LOW +#define GPO_209_LEVEL GPO_LOW +#define GPO_210_LEVEL GPO_LOW +#define GPO_211_LEVEL GPO_LOW +#define GPO_212_LEVEL GPO_LOW +#define GPO_213_LEVEL GPO_LOW +#define GPO_214_LEVEL GPO_LOW +#define GPO_215_LEVEL GPO_LOW +#define GPO_216_LEVEL GPO_LOW +#define GPO_217_LEVEL GPO_LOW +#define GPO_218_LEVEL GPO_LOW +#define GPO_219_LEVEL GPO_LOW +#define GPO_220_LEVEL GPO_LOW +#define GPO_221_LEVEL GPO_LOW +#define GPO_222_LEVEL GPO_LOW +#define GPO_223_LEVEL GPO_LOW +#define GPO_224_LEVEL GPO_LOW +#define GPO_225_LEVEL GPO_LOW +#define GPO_226_LEVEL GPO_LOW +#define GPO_227_LEVEL GPO_LOW +#define GPO_228_LEVEL GPO_LOW +#define GPO_229_LEVEL GPO_LOW + +#define GPIO_NONSTICKY (0<<2) +#define GPIO_STICKY (1<<2) + +#define GPIO_00_STICKY GPIO_NONSTICKY +#define GPIO_01_STICKY GPIO_NONSTICKY +#define GPIO_02_STICKY GPIO_NONSTICKY +#define GPIO_03_STICKY GPIO_NONSTICKY +#define GPIO_04_STICKY GPIO_NONSTICKY +#define GPIO_05_STICKY GPIO_NONSTICKY +#define GPIO_06_STICKY GPIO_NONSTICKY +#define GPIO_07_STICKY GPIO_NONSTICKY +#define GPIO_08_STICKY GPIO_NONSTICKY +#define GPIO_09_STICKY GPIO_NONSTICKY +#define GPIO_10_STICKY GPIO_NONSTICKY +#define GPIO_11_STICKY GPIO_NONSTICKY +#define GPIO_12_STICKY GPIO_NONSTICKY +#define GPIO_13_STICKY GPIO_NONSTICKY +#define GPIO_14_STICKY GPIO_NONSTICKY +#define GPIO_15_STICKY GPIO_NONSTICKY +#define GPIO_16_STICKY GPIO_NONSTICKY +#define GPIO_17_STICKY GPIO_STICKY +#define GPIO_18_STICKY GPIO_NONSTICKY +#define GPIO_19_STICKY GPIO_NONSTICKY +#define GPIO_20_STICKY GPIO_NONSTICKY +#define GPIO_21_STICKY GPIO_NONSTICKY +#define GPIO_22_STICKY GPIO_NONSTICKY +#define GPIO_23_STICKY GPIO_NONSTICKY +#define GPIO_24_STICKY GPIO_NONSTICKY +#define GPIO_25_STICKY GPIO_NONSTICKY +#define GPIO_26_STICKY GPIO_NONSTICKY +#define GPIO_27_STICKY GPIO_NONSTICKY +#define GPIO_28_STICKY GPIO_NONSTICKY +#define GPIO_29_STICKY GPIO_NONSTICKY +#define GPIO_30_STICKY GPIO_NONSTICKY +#define GPIO_31_STICKY GPIO_NONSTICKY +#define GPIO_32_STICKY GPIO_NONSTICKY +#define GPIO_33_STICKY GPIO_NONSTICKY +#define GPIO_34_STICKY GPIO_NONSTICKY +#define GPIO_35_STICKY GPIO_NONSTICKY +#define GPIO_36_STICKY GPIO_NONSTICKY +#define GPIO_37_STICKY GPIO_NONSTICKY +#define GPIO_38_STICKY GPIO_NONSTICKY +#define GPIO_39_STICKY GPIO_NONSTICKY +#define GPIO_40_STICKY GPIO_NONSTICKY +#define GPIO_41_STICKY GPIO_NONSTICKY +#define GPIO_42_STICKY GPIO_NONSTICKY +#define GPIO_43_STICKY GPIO_NONSTICKY +#define GPIO_44_STICKY GPIO_NONSTICKY +#define GPIO_45_STICKY GPIO_NONSTICKY +#define GPIO_46_STICKY GPIO_NONSTICKY +#define GPIO_47_STICKY GPIO_NONSTICKY +#define GPIO_48_STICKY GPIO_NONSTICKY +#define GPIO_49_STICKY GPIO_NONSTICKY +#define GPIO_50_STICKY GPIO_NONSTICKY +#define GPIO_51_STICKY GPIO_NONSTICKY +#define GPIO_52_STICKY GPIO_NONSTICKY +#define GPIO_53_STICKY GPIO_NONSTICKY +#define GPIO_54_STICKY GPIO_NONSTICKY +#define GPIO_55_STICKY GPIO_NONSTICKY +#define GPIO_56_STICKY GPIO_NONSTICKY +#define GPIO_57_STICKY GPIO_NONSTICKY +#define GPIO_58_STICKY GPIO_NONSTICKY +#define GPIO_59_STICKY GPIO_NONSTICKY +#define GPIO_60_STICKY GPIO_NONSTICKY +#define GPIO_61_STICKY GPIO_NONSTICKY +#define GPIO_62_STICKY GPIO_NONSTICKY +#define GPIO_63_STICKY GPIO_NONSTICKY +#define GPIO_64_STICKY GPIO_NONSTICKY +#define GPIO_65_STICKY GPIO_NONSTICKY +#define GPIO_66_STICKY GPIO_NONSTICKY +#define GPIO_67_STICKY GPIO_NONSTICKY +#define GPIO_68_STICKY GPIO_NONSTICKY +#define GPIO_69_STICKY GPIO_NONSTICKY +#define GPIO_70_STICKY GPIO_NONSTICKY +#define GPIO_71_STICKY GPIO_NONSTICKY +#define GPIO_72_STICKY GPIO_NONSTICKY +#define GPIO_73_STICKY GPIO_NONSTICKY +#define GPIO_74_STICKY GPIO_NONSTICKY +#define GPIO_75_STICKY GPIO_NONSTICKY +#define GPIO_76_STICKY GPIO_NONSTICKY +#define GPIO_77_STICKY GPIO_NONSTICKY +#define GPIO_78_STICKY GPIO_NONSTICKY +#define GPIO_79_STICKY GPIO_NONSTICKY +#define GPIO_80_STICKY GPIO_NONSTICKY +#define GPIO_81_STICKY GPIO_NONSTICKY +#define GPIO_82_STICKY GPIO_NONSTICKY +#define GPIO_83_STICKY GPIO_NONSTICKY +#define GPIO_84_STICKY GPIO_NONSTICKY +#define GPIO_85_STICKY GPIO_NONSTICKY +#define GPIO_86_STICKY GPIO_NONSTICKY +#define GPIO_87_STICKY GPIO_NONSTICKY +#define GPIO_88_STICKY GPIO_NONSTICKY +#define GPIO_89_STICKY GPIO_NONSTICKY +#define GPIO_90_STICKY GPIO_NONSTICKY +#define GPIO_91_STICKY GPIO_NONSTICKY +#define GPIO_92_STICKY GPIO_NONSTICKY +#define GPIO_93_STICKY GPIO_NONSTICKY +#define GPIO_94_STICKY GPIO_NONSTICKY +#define GPIO_95_STICKY GPIO_NONSTICKY +#define GPIO_96_STICKY GPIO_NONSTICKY +#define GPIO_97_STICKY GPIO_NONSTICKY +#define GPIO_98_STICKY GPIO_NONSTICKY +#define GPIO_99_STICKY GPIO_NONSTICKY +#define GPIO_100_STICKY GPIO_NONSTICKY +#define GPIO_101_STICKY GPIO_NONSTICKY +#define GPIO_102_STICKY GPIO_STICKY +#define GPIO_103_STICKY GPIO_STICKY +#define GPIO_104_STICKY GPIO_NONSTICKY +#define GPIO_105_STICKY GPIO_NONSTICKY +#define GPIO_106_STICKY GPIO_NONSTICKY +#define GPIO_107_STICKY GPIO_NONSTICKY +#define GPIO_108_STICKY GPIO_STICKY +#define GPIO_109_STICKY GPIO_NONSTICKY +#define GPIO_110_STICKY GPIO_NONSTICKY +#define GPIO_111_STICKY GPIO_NONSTICKY +#define GPIO_112_STICKY GPIO_NONSTICKY +#define GPIO_113_STICKY GPIO_NONSTICKY +#define GPIO_114_STICKY GPIO_NONSTICKY +#define GPIO_115_STICKY GPIO_NONSTICKY +#define GPIO_116_STICKY GPIO_NONSTICKY +#define GPIO_117_STICKY GPIO_NONSTICKY +#define GPIO_118_STICKY GPIO_NONSTICKY +#define GPIO_119_STICKY GPIO_NONSTICKY +#define GPIO_120_STICKY GPIO_NONSTICKY +#define GPIO_121_STICKY GPIO_NONSTICKY +#define GPIO_122_STICKY GPIO_NONSTICKY +#define GPIO_123_STICKY GPIO_NONSTICKY +#define GPIO_124_STICKY GPIO_NONSTICKY +#define GPIO_125_STICKY GPIO_NONSTICKY +#define GPIO_126_STICKY GPIO_NONSTICKY +#define GPIO_127_STICKY GPIO_NONSTICKY +#define GPIO_128_STICKY GPIO_NONSTICKY +#define GPIO_129_STICKY GPIO_NONSTICKY +#define GPIO_130_STICKY GPIO_NONSTICKY +#define GPIO_131_STICKY GPIO_NONSTICKY +#define GPIO_132_STICKY GPIO_NONSTICKY +#define GPIO_133_STICKY GPIO_NONSTICKY +#define GPIO_134_STICKY GPIO_NONSTICKY +#define GPIO_135_STICKY GPIO_NONSTICKY +#define GPIO_136_STICKY GPIO_NONSTICKY +#define GPIO_137_STICKY GPIO_NONSTICKY +#define GPIO_138_STICKY GPIO_NONSTICKY +#define GPIO_139_STICKY GPIO_NONSTICKY +#define GPIO_140_STICKY GPIO_NONSTICKY +#define GPIO_141_STICKY GPIO_NONSTICKY +#define GPIO_142_STICKY GPIO_NONSTICKY +#define GPIO_143_STICKY GPIO_NONSTICKY +#define GPIO_144_STICKY GPIO_NONSTICKY +#define GPIO_145_STICKY GPIO_NONSTICKY +#define GPIO_146_STICKY GPIO_NONSTICKY +#define GPIO_147_STICKY GPIO_NONSTICKY +#define GPIO_148_STICKY GPIO_NONSTICKY +#define GPIO_149_STICKY GPIO_NONSTICKY +#define GPIO_150_STICKY GPIO_NONSTICKY +#define GPIO_151_STICKY GPIO_NONSTICKY +#define GPIO_152_STICKY GPIO_NONSTICKY +#define GPIO_153_STICKY GPIO_NONSTICKY +#define GPIO_154_STICKY GPIO_NONSTICKY +#define GPIO_155_STICKY GPIO_NONSTICKY +#define GPIO_156_STICKY GPIO_NONSTICKY +#define GPIO_157_STICKY GPIO_NONSTICKY +#define GPIO_158_STICKY GPIO_NONSTICKY +#define GPIO_159_STICKY GPIO_NONSTICKY +#define GPIO_160_STICKY GPIO_NONSTICKY +#define GPIO_161_STICKY GPIO_NONSTICKY +#define GPIO_162_STICKY GPIO_NONSTICKY +#define GPIO_163_STICKY GPIO_NONSTICKY +#define GPIO_164_STICKY GPIO_NONSTICKY +#define GPIO_165_STICKY GPIO_NONSTICKY +#define GPIO_166_STICKY GPIO_NONSTICKY +#define GPIO_167_STICKY GPIO_NONSTICKY +#define GPIO_168_STICKY GPIO_NONSTICKY +#define GPIO_169_STICKY GPIO_NONSTICKY +#define GPIO_170_STICKY GPIO_STICKY +#define GPIO_171_STICKY GPIO_NONSTICKY +#define GPIO_172_STICKY GPIO_STICKY +#define GPIO_173_STICKY GPIO_NONSTICKY +#define GPIO_174_STICKY GPIO_NONSTICKY +#define GPIO_175_STICKY GPIO_NONSTICKY +#define GPIO_176_STICKY GPIO_NONSTICKY +#define GPIO_177_STICKY GPIO_NONSTICKY +#define GPIO_178_STICKY GPIO_NONSTICKY +#define GPIO_179_STICKY GPIO_NONSTICKY +#define GPIO_180_STICKY GPIO_NONSTICKY +#define GPIO_181_STICKY GPIO_NONSTICKY +#define GPIO_182_STICKY GPIO_NONSTICKY +#define GPIO_183_STICKY GPIO_NONSTICKY +#define GPIO_184_STICKY GPIO_NONSTICKY +#define GPIO_185_STICKY GPIO_NONSTICKY +#define GPIO_186_STICKY GPIO_NONSTICKY +#define GPIO_187_STICKY GPIO_NONSTICKY +#define GPIO_188_STICKY GPIO_NONSTICKY +#define GPIO_189_STICKY GPIO_NONSTICKY +#define GPIO_190_STICKY GPIO_NONSTICKY +#define GPIO_191_STICKY GPIO_NONSTICKY +#define GPIO_192_STICKY GPIO_NONSTICKY +#define GPIO_193_STICKY GPIO_NONSTICKY +#define GPIO_194_STICKY GPIO_NONSTICKY +#define GPIO_195_STICKY GPIO_NONSTICKY +#define GPIO_196_STICKY GPIO_NONSTICKY +#define GPIO_197_STICKY GPIO_NONSTICKY +#define GPIO_198_STICKY GPIO_NONSTICKY +#define GPIO_199_STICKY GPIO_NONSTICKY +#define GPIO_200_STICKY GPIO_NONSTICKY +#define GPIO_201_STICKY GPIO_NONSTICKY +#define GPIO_202_STICKY GPIO_NONSTICKY +#define GPIO_203_STICKY GPIO_NONSTICKY +#define GPIO_204_STICKY GPIO_NONSTICKY +#define GPIO_205_STICKY GPIO_NONSTICKY +#define GPIO_206_STICKY GPIO_NONSTICKY +#define GPIO_207_STICKY GPIO_NONSTICKY +#define GPIO_208_STICKY GPIO_NONSTICKY +#define GPIO_209_STICKY GPIO_NONSTICKY +#define GPIO_210_STICKY GPIO_NONSTICKY +#define GPIO_211_STICKY GPIO_NONSTICKY +#define GPIO_212_STICKY GPIO_NONSTICKY +#define GPIO_213_STICKY GPIO_NONSTICKY +#define GPIO_214_STICKY GPIO_NONSTICKY +#define GPIO_215_STICKY GPIO_NONSTICKY +#define GPIO_216_STICKY GPIO_NONSTICKY +#define GPIO_217_STICKY GPIO_NONSTICKY +#define GPIO_218_STICKY GPIO_NONSTICKY +#define GPIO_219_STICKY GPIO_NONSTICKY +#define GPIO_220_STICKY GPIO_NONSTICKY +#define GPIO_221_STICKY GPIO_NONSTICKY +#define GPIO_222_STICKY GPIO_NONSTICKY +#define GPIO_223_STICKY GPIO_NONSTICKY +#define GPIO_224_STICKY GPIO_NONSTICKY +#define GPIO_225_STICKY GPIO_NONSTICKY +#define GPIO_226_STICKY GPIO_NONSTICKY +#define GPIO_227_STICKY GPIO_NONSTICKY +#define GPIO_228_STICKY GPIO_NONSTICKY +#define GPIO_229_STICKY GPIO_NONSTICKY + +#define PULLUP_ENABLE (0<<3) +#define PULLUP_DISABLE (1<<3) + +#define GPIO_00_PULLUP PULLUP_DISABLE +#define GPIO_01_PULLUP PULLUP_DISABLE +#define GPIO_02_PULLUP PULLUP_DISABLE +#define GPIO_03_PULLUP PULLUP_DISABLE +#define GPIO_04_PULLUP PULLUP_DISABLE +#define GPIO_05_PULLUP PULLUP_DISABLE +#define GPIO_06_PULLUP PULLUP_DISABLE +#define GPIO_07_PULLUP PULLUP_DISABLE +#define GPIO_08_PULLUP PULLUP_DISABLE +#define GPIO_09_PULLUP PULLUP_DISABLE +#define GPIO_10_PULLUP PULLUP_DISABLE +#define GPIO_11_PULLUP PULLUP_DISABLE +#define GPIO_12_PULLUP PULLUP_DISABLE +#define GPIO_13_PULLUP PULLUP_DISABLE +#define GPIO_14_PULLUP PULLUP_DISABLE +#define GPIO_15_PULLUP PULLUP_DISABLE +#define GPIO_16_PULLUP PULLUP_DISABLE +#define GPIO_17_PULLUP PULLUP_DISABLE +#define GPIO_18_PULLUP PULLUP_DISABLE +#define GPIO_19_PULLUP PULLUP_DISABLE +#define GPIO_20_PULLUP PULLUP_DISABLE +#define GPIO_21_PULLUP PULLUP_DISABLE +#define GPIO_22_PULLUP PULLUP_DISABLE +#define GPIO_23_PULLUP PULLUP_DISABLE +#define GPIO_24_PULLUP PULLUP_DISABLE +#define GPIO_25_PULLUP PULLUP_DISABLE +#define GPIO_26_PULLUP PULLUP_DISABLE +#define GPIO_27_PULLUP PULLUP_DISABLE +#define GPIO_28_PULLUP PULLUP_DISABLE +#define GPIO_29_PULLUP PULLUP_DISABLE +#define GPIO_30_PULLUP PULLUP_DISABLE +#define GPIO_31_PULLUP PULLUP_DISABLE +#define GPIO_32_PULLUP PULLUP_DISABLE +#define GPIO_33_PULLUP PULLUP_DISABLE +#define GPIO_34_PULLUP PULLUP_DISABLE +#define GPIO_35_PULLUP PULLUP_DISABLE +#define GPIO_36_PULLUP PULLUP_DISABLE +#define GPIO_37_PULLUP PULLUP_DISABLE +#define GPIO_38_PULLUP PULLUP_DISABLE +#define GPIO_39_PULLUP PULLUP_DISABLE +#define GPIO_40_PULLUP PULLUP_DISABLE +#define GPIO_41_PULLUP PULLUP_DISABLE +#define GPIO_42_PULLUP PULLUP_DISABLE +#define GPIO_43_PULLUP PULLUP_DISABLE +#define GPIO_44_PULLUP PULLUP_DISABLE +#define GPIO_45_PULLUP PULLUP_DISABLE +#define GPIO_46_PULLUP PULLUP_DISABLE +#define GPIO_47_PULLUP PULLUP_DISABLE +#define GPIO_48_PULLUP PULLUP_DISABLE +#define GPIO_49_PULLUP PULLUP_DISABLE +#define GPIO_50_PULLUP PULLUP_DISABLE +#define GPIO_51_PULLUP PULLUP_DISABLE +#define GPIO_52_PULLUP PULLUP_DISABLE +#define GPIO_53_PULLUP PULLUP_DISABLE +#define GPIO_54_PULLUP PULLUP_DISABLE +#define GPIO_55_PULLUP PULLUP_DISABLE +#define GPIO_56_PULLUP PULLUP_DISABLE +#define GPIO_57_PULLUP PULLUP_DISABLE +#define GPIO_58_PULLUP PULLUP_DISABLE +#define GPIO_59_PULLUP PULLUP_DISABLE +#define GPIO_60_PULLUP PULLUP_DISABLE +#define GPIO_61_PULLUP PULLUP_DISABLE +#define GPIO_62_PULLUP PULLUP_DISABLE +#define GPIO_63_PULLUP PULLUP_DISABLE +#define GPIO_64_PULLUP PULLUP_DISABLE +#define GPIO_65_PULLUP PULLUP_DISABLE +#define GPIO_66_PULLUP PULLUP_DISABLE +#define GPIO_67_PULLUP PULLUP_DISABLE +#define GPIO_68_PULLUP PULLUP_DISABLE +#define GPIO_69_PULLUP PULLUP_DISABLE +#define GPIO_70_PULLUP PULLUP_DISABLE +#define GPIO_71_PULLUP PULLUP_DISABLE +#define GPIO_72_PULLUP PULLUP_DISABLE +#define GPIO_73_PULLUP PULLUP_DISABLE +#define GPIO_74_PULLUP PULLUP_DISABLE +#define GPIO_75_PULLUP PULLUP_DISABLE +#define GPIO_76_PULLUP PULLUP_DISABLE +#define GPIO_77_PULLUP PULLUP_DISABLE +#define GPIO_78_PULLUP PULLUP_DISABLE +#define GPIO_79_PULLUP PULLUP_DISABLE +#define GPIO_80_PULLUP PULLUP_DISABLE +#define GPIO_80_PULLUP PULLUP_DISABLE +#define GPIO_81_PULLUP PULLUP_DISABLE +#define GPIO_82_PULLUP PULLUP_DISABLE +#define GPIO_83_PULLUP PULLUP_DISABLE +#define GPIO_84_PULLUP PULLUP_DISABLE +#define GPIO_85_PULLUP PULLUP_DISABLE +#define GPIO_86_PULLUP PULLUP_DISABLE +#define GPIO_87_PULLUP PULLUP_DISABLE +#define GPIO_88_PULLUP PULLUP_DISABLE +#define GPIO_89_PULLUP PULLUP_DISABLE +#define GPIO_90_PULLUP PULLUP_DISABLE +#define GPIO_91_PULLUP PULLUP_DISABLE +#define GPIO_92_PULLUP PULLUP_DISABLE +#define GPIO_93_PULLUP PULLUP_DISABLE +#define GPIO_94_PULLUP PULLUP_DISABLE +#define GPIO_95_PULLUP PULLUP_DISABLE +#define GPIO_96_PULLUP PULLUP_DISABLE +#define GPIO_97_PULLUP PULLUP_DISABLE +#define GPIO_98_PULLUP PULLUP_DISABLE +#define GPIO_99_PULLUP PULLUP_DISABLE +#define GPIO_100_PULLUP PULLUP_DISABLE +#define GPIO_101_PULLUP PULLUP_DISABLE +#define GPIO_102_PULLUP PULLUP_DISABLE +#define GPIO_103_PULLUP PULLUP_DISABLE +#define GPIO_104_PULLUP PULLUP_DISABLE +#define GPIO_105_PULLUP PULLUP_DISABLE +#define GPIO_106_PULLUP PULLUP_DISABLE +#define GPIO_107_PULLUP PULLUP_DISABLE +#define GPIO_108_PULLUP PULLUP_DISABLE +#define GPIO_109_PULLUP PULLUP_DISABLE +#define GPIO_110_PULLUP PULLUP_DISABLE +#define GPIO_111_PULLUP PULLUP_DISABLE +#define GPIO_112_PULLUP PULLUP_DISABLE +#define GPIO_113_PULLUP PULLUP_DISABLE +#define GPIO_114_PULLUP PULLUP_DISABLE +#define GPIO_115_PULLUP PULLUP_DISABLE +#define GPIO_116_PULLUP PULLUP_DISABLE +#define GPIO_117_PULLUP PULLUP_DISABLE +#define GPIO_118_PULLUP PULLUP_ENABLE +#define GPIO_119_PULLUP PULLUP_DISABLE +#define GPIO_120_PULLUP PULLUP_DISABLE +#define GPIO_121_PULLUP PULLUP_DISABLE +#define GPIO_122_PULLUP PULLUP_DISABLE +#define GPIO_123_PULLUP PULLUP_DISABLE +#define GPIO_124_PULLUP PULLUP_DISABLE +#define GPIO_125_PULLUP PULLUP_DISABLE +#define GPIO_126_PULLUP PULLUP_DISABLE +#define GPIO_127_PULLUP PULLUP_DISABLE +#define GPIO_128_PULLUP PULLUP_DISABLE +#define GPIO_129_PULLUP PULLUP_DISABLE +#define GPIO_130_PULLUP PULLUP_DISABLE +#define GPIO_131_PULLUP PULLUP_DISABLE +#define GPIO_132_PULLUP PULLUP_DISABLE +#define GPIO_133_PULLUP PULLUP_DISABLE +#define GPIO_134_PULLUP PULLUP_DISABLE +#define GPIO_135_PULLUP PULLUP_DISABLE +#define GPIO_136_PULLUP PULLUP_DISABLE +#define GPIO_137_PULLUP PULLUP_DISABLE +#define GPIO_138_PULLUP PULLUP_DISABLE +#define GPIO_139_PULLUP PULLUP_DISABLE +#define GPIO_140_PULLUP PULLUP_DISABLE +#define GPIO_141_PULLUP PULLUP_DISABLE +#define GPIO_142_PULLUP PULLUP_DISABLE +#define GPIO_143_PULLUP PULLUP_DISABLE +#define GPIO_144_PULLUP PULLUP_DISABLE +#define GPIO_145_PULLUP PULLUP_DISABLE +#define GPIO_146_PULLUP PULLUP_DISABLE +#define GPIO_147_PULLUP PULLUP_DISABLE +#define GPIO_148_PULLUP PULLUP_DISABLE +#define GPIO_149_PULLUP PULLUP_DISABLE +#define GPIO_150_PULLUP PULLUP_DISABLE +#define GPIO_151_PULLUP PULLUP_DISABLE +#define GPIO_152_PULLUP PULLUP_DISABLE +#define GPIO_153_PULLUP PULLUP_DISABLE +#define GPIO_154_PULLUP PULLUP_DISABLE +#define GPIO_155_PULLUP PULLUP_DISABLE +#define GPIO_156_PULLUP PULLUP_DISABLE +#define GPIO_157_PULLUP PULLUP_DISABLE +#define GPIO_158_PULLUP PULLUP_DISABLE +#define GPIO_159_PULLUP PULLUP_DISABLE +#define GPIO_160_PULLUP PULLUP_DISABLE +#define GPIO_161_PULLUP PULLUP_DISABLE +#define GPIO_162_PULLUP PULLUP_DISABLE +#define GPIO_163_PULLUP PULLUP_DISABLE +#define GPIO_164_PULLUP PULLUP_DISABLE +#define GPIO_165_PULLUP PULLUP_DISABLE +#define GPIO_166_PULLUP PULLUP_DISABLE +#define GPIO_167_PULLUP PULLUP_DISABLE +#define GPIO_168_PULLUP PULLUP_DISABLE +#define GPIO_169_PULLUP PULLUP_DISABLE +#define GPIO_170_PULLUP PULLUP_DISABLE +#define GPIO_171_PULLUP PULLUP_DISABLE +#define GPIO_172_PULLUP PULLUP_DISABLE +#define GPIO_173_PULLUP PULLUP_DISABLE +#define GPIO_174_PULLUP PULLUP_DISABLE +#define GPIO_175_PULLUP PULLUP_DISABLE +#define GPIO_176_PULLUP PULLUP_DISABLE +#define GPIO_177_PULLUP PULLUP_DISABLE +#define GPIO_178_PULLUP PULLUP_DISABLE +#define GPIO_179_PULLUP PULLUP_DISABLE +#define GPIO_180_PULLUP PULLUP_DISABLE +#define GPIO_180_PULLUP PULLUP_DISABLE +#define GPIO_181_PULLUP PULLUP_DISABLE +#define GPIO_182_PULLUP PULLUP_DISABLE +#define GPIO_183_PULLUP PULLUP_DISABLE +#define GPIO_184_PULLUP PULLUP_DISABLE +#define GPIO_185_PULLUP PULLUP_DISABLE +#define GPIO_186_PULLUP PULLUP_DISABLE +#define GPIO_187_PULLUP PULLUP_DISABLE +#define GPIO_188_PULLUP PULLUP_DISABLE +#define GPIO_189_PULLUP PULLUP_DISABLE +#define GPIO_190_PULLUP PULLUP_DISABLE +#define GPIO_191_PULLUP PULLUP_DISABLE +#define GPIO_192_PULLUP PULLUP_DISABLE +#define GPIO_193_PULLUP PULLUP_DISABLE +#define GPIO_194_PULLUP PULLUP_DISABLE +#define GPIO_195_PULLUP PULLUP_DISABLE +#define GPIO_196_PULLUP PULLUP_DISABLE +#define GPIO_197_PULLUP PULLUP_DISABLE +#define GPIO_198_PULLUP PULLUP_DISABLE +#define GPIO_199_PULLUP PULLUP_DISABLE +#define GPIO_200_PULLUP PULLUP_DISABLE +#define GPIO_201_PULLUP PULLUP_DISABLE +#define GPIO_202_PULLUP PULLUP_DISABLE +#define GPIO_203_PULLUP PULLUP_DISABLE +#define GPIO_204_PULLUP PULLUP_DISABLE +#define GPIO_205_PULLUP PULLUP_DISABLE +#define GPIO_206_PULLUP PULLUP_DISABLE +#define GPIO_207_PULLUP PULLUP_DISABLE +#define GPIO_208_PULLUP PULLUP_DISABLE +#define GPIO_209_PULLUP PULLUP_DISABLE +#define GPIO_210_PULLUP PULLUP_DISABLE +#define GPIO_211_PULLUP PULLUP_DISABLE +#define GPIO_212_PULLUP PULLUP_DISABLE +#define GPIO_213_PULLUP PULLUP_DISABLE +#define GPIO_214_PULLUP PULLUP_DISABLE +#define GPIO_215_PULLUP PULLUP_DISABLE +#define GPIO_216_PULLUP PULLUP_DISABLE +#define GPIO_217_PULLUP PULLUP_DISABLE +#define GPIO_218_PULLUP PULLUP_DISABLE +#define GPIO_219_PULLUP PULLUP_DISABLE +#define GPIO_220_PULLUP PULLUP_DISABLE +#define GPIO_221_PULLUP PULLUP_DISABLE +#define GPIO_222_PULLUP PULLUP_DISABLE +#define GPIO_223_PULLUP PULLUP_DISABLE +#define GPIO_224_PULLUP PULLUP_DISABLE +#define GPIO_225_PULLUP PULLUP_DISABLE +#define GPIO_226_PULLUP PULLUP_DISABLE +#define GPIO_227_PULLUP PULLUP_DISABLE +#define GPIO_228_PULLUP PULLUP_DISABLE +#define GPIO_229_PULLUP PULLUP_DISABLE + +#define PULLDOWN_ENABLE (1<<4) +#define PULLDOWN_DISABLE (0<<4) + +#define GPIO_00_PULLDOWN PULLDOWN_DISABLE +#define GPIO_01_PULLDOWN PULLDOWN_DISABLE +#define GPIO_02_PULLDOWN PULLDOWN_DISABLE +#define GPIO_03_PULLDOWN PULLDOWN_DISABLE +#define GPIO_04_PULLDOWN PULLDOWN_DISABLE +#define GPIO_05_PULLDOWN PULLDOWN_DISABLE +#define GPIO_06_PULLDOWN PULLDOWN_DISABLE +#define GPIO_07_PULLDOWN PULLDOWN_DISABLE +#define GPIO_08_PULLDOWN PULLDOWN_DISABLE +#define GPIO_09_PULLDOWN PULLDOWN_DISABLE +#define GPIO_10_PULLDOWN PULLDOWN_DISABLE +#define GPIO_11_PULLDOWN PULLDOWN_DISABLE +#define GPIO_12_PULLDOWN PULLDOWN_DISABLE +#define GPIO_13_PULLDOWN PULLDOWN_DISABLE +#define GPIO_14_PULLDOWN PULLDOWN_DISABLE +#define GPIO_15_PULLDOWN PULLDOWN_DISABLE +#define GPIO_16_PULLDOWN PULLDOWN_DISABLE +#define GPIO_17_PULLDOWN PULLDOWN_DISABLE +#define GPIO_18_PULLDOWN PULLDOWN_DISABLE +#define GPIO_19_PULLDOWN PULLDOWN_DISABLE +#define GPIO_20_PULLDOWN PULLDOWN_DISABLE +#define GPIO_21_PULLDOWN PULLDOWN_DISABLE +#define GPIO_22_PULLDOWN PULLDOWN_DISABLE +#define GPIO_23_PULLDOWN PULLDOWN_DISABLE +#define GPIO_24_PULLDOWN PULLDOWN_DISABLE +#define GPIO_25_PULLDOWN PULLDOWN_DISABLE +#define GPIO_26_PULLDOWN PULLDOWN_DISABLE +#define GPIO_27_PULLDOWN PULLDOWN_DISABLE +#define GPIO_28_PULLDOWN PULLDOWN_DISABLE +#define GPIO_29_PULLDOWN PULLDOWN_DISABLE +#define GPIO_30_PULLDOWN PULLDOWN_DISABLE +#define GPIO_31_PULLDOWN PULLDOWN_DISABLE +#define GPIO_32_PULLDOWN PULLDOWN_DISABLE +#define GPIO_33_PULLDOWN PULLDOWN_DISABLE +#define GPIO_34_PULLDOWN PULLDOWN_DISABLE +#define GPIO_35_PULLDOWN PULLDOWN_DISABLE +#define GPIO_36_PULLDOWN PULLDOWN_DISABLE +#define GPIO_37_PULLDOWN PULLDOWN_DISABLE +#define GPIO_38_PULLDOWN PULLDOWN_DISABLE +#define GPIO_39_PULLDOWN PULLDOWN_DISABLE +#define GPIO_40_PULLDOWN PULLDOWN_DISABLE +#define GPIO_41_PULLDOWN PULLDOWN_DISABLE +#define GPIO_42_PULLDOWN PULLDOWN_DISABLE +#define GPIO_43_PULLDOWN PULLDOWN_DISABLE +#define GPIO_44_PULLDOWN PULLDOWN_DISABLE +#define GPIO_45_PULLDOWN PULLDOWN_DISABLE +#define GPIO_46_PULLDOWN PULLDOWN_DISABLE +#define GPIO_47_PULLDOWN PULLDOWN_DISABLE +#define GPIO_48_PULLDOWN PULLDOWN_DISABLE +#define GPIO_49_PULLDOWN PULLDOWN_DISABLE +#define GPIO_50_PULLDOWN PULLDOWN_DISABLE +#define GPIO_51_PULLDOWN PULLDOWN_DISABLE +#define GPIO_52_PULLDOWN PULLDOWN_DISABLE +#define GPIO_53_PULLDOWN PULLDOWN_DISABLE +#define GPIO_54_PULLDOWN PULLDOWN_DISABLE +#define GPIO_55_PULLDOWN PULLDOWN_DISABLE +#define GPIO_56_PULLDOWN PULLDOWN_DISABLE +#define GPIO_57_PULLDOWN PULLDOWN_DISABLE +#define GPIO_58_PULLDOWN PULLDOWN_DISABLE +#define GPIO_59_PULLDOWN PULLDOWN_DISABLE +#define GPIO_60_PULLDOWN PULLDOWN_DISABLE +#define GPIO_61_PULLDOWN PULLDOWN_DISABLE +#define GPIO_62_PULLDOWN PULLDOWN_DISABLE +#define GPIO_63_PULLDOWN PULLDOWN_DISABLE +#define GPIO_64_PULLDOWN PULLDOWN_DISABLE +#define GPIO_65_PULLDOWN PULLDOWN_DISABLE +#define GPIO_66_PULLDOWN PULLDOWN_DISABLE +#define GPIO_67_PULLDOWN PULLDOWN_DISABLE +#define GPIO_68_PULLDOWN PULLDOWN_DISABLE +#define GPIO_69_PULLDOWN PULLDOWN_DISABLE +#define GPIO_70_PULLDOWN PULLDOWN_DISABLE +#define GPIO_71_PULLDOWN PULLDOWN_DISABLE +#define GPIO_72_PULLDOWN PULLDOWN_DISABLE +#define GPIO_73_PULLDOWN PULLDOWN_DISABLE +#define GPIO_74_PULLDOWN PULLDOWN_DISABLE +#define GPIO_75_PULLDOWN PULLDOWN_DISABLE +#define GPIO_76_PULLDOWN PULLDOWN_DISABLE +#define GPIO_77_PULLDOWN PULLDOWN_DISABLE +#define GPIO_78_PULLDOWN PULLDOWN_DISABLE +#define GPIO_79_PULLDOWN PULLDOWN_DISABLE +#define GPIO_80_PULLDOWN PULLDOWN_DISABLE +#define GPIO_80_PULLDOWN PULLDOWN_DISABLE +#define GPIO_81_PULLDOWN PULLDOWN_DISABLE +#define GPIO_82_PULLDOWN PULLDOWN_DISABLE +#define GPIO_83_PULLDOWN PULLDOWN_DISABLE +#define GPIO_84_PULLDOWN PULLDOWN_DISABLE +#define GPIO_85_PULLDOWN PULLDOWN_DISABLE +#define GPIO_86_PULLDOWN PULLDOWN_DISABLE +#define GPIO_87_PULLDOWN PULLDOWN_DISABLE +#define GPIO_88_PULLDOWN PULLDOWN_DISABLE +#define GPIO_89_PULLDOWN PULLDOWN_DISABLE +#define GPIO_90_PULLDOWN PULLDOWN_DISABLE +#define GPIO_91_PULLDOWN PULLDOWN_DISABLE +#define GPIO_92_PULLDOWN PULLDOWN_DISABLE +#define GPIO_93_PULLDOWN PULLDOWN_DISABLE +#define GPIO_94_PULLDOWN PULLDOWN_DISABLE +#define GPIO_95_PULLDOWN PULLDOWN_DISABLE +#define GPIO_96_PULLDOWN PULLDOWN_DISABLE +#define GPIO_97_PULLDOWN PULLDOWN_DISABLE +#define GPIO_98_PULLDOWN PULLDOWN_DISABLE +#define GPIO_99_PULLDOWN PULLDOWN_DISABLE +#define GPIO_100_PULLDOWN PULLDOWN_DISABLE +#define GPIO_101_PULLDOWN PULLDOWN_DISABLE +#define GPIO_102_PULLDOWN PULLDOWN_DISABLE +#define GPIO_103_PULLDOWN PULLDOWN_DISABLE +#define GPIO_104_PULLDOWN PULLDOWN_DISABLE +#define GPIO_105_PULLDOWN PULLDOWN_DISABLE +#define GPIO_106_PULLDOWN PULLDOWN_DISABLE +#define GPIO_107_PULLDOWN PULLDOWN_DISABLE +#define GPIO_108_PULLDOWN PULLDOWN_DISABLE +#define GPIO_109_PULLDOWN PULLDOWN_DISABLE +#define GPIO_110_PULLDOWN PULLDOWN_DISABLE +#define GPIO_111_PULLDOWN PULLDOWN_DISABLE +#define GPIO_112_PULLDOWN PULLDOWN_DISABLE +#define GPIO_113_PULLDOWN PULLDOWN_DISABLE +#define GPIO_114_PULLDOWN PULLDOWN_DISABLE +#define GPIO_115_PULLDOWN PULLDOWN_DISABLE +#define GPIO_116_PULLDOWN PULLDOWN_DISABLE +#define GPIO_117_PULLDOWN PULLDOWN_DISABLE +#define GPIO_118_PULLDOWN PULLDOWN_DISABLE +#define GPIO_119_PULLDOWN PULLDOWN_DISABLE +#define GPIO_120_PULLDOWN PULLDOWN_DISABLE +#define GPIO_121_PULLDOWN PULLDOWN_DISABLE +#define GPIO_122_PULLDOWN PULLDOWN_DISABLE +#define GPIO_123_PULLDOWN PULLDOWN_DISABLE +#define GPIO_124_PULLDOWN PULLDOWN_DISABLE +#define GPIO_125_PULLDOWN PULLDOWN_DISABLE +#define GPIO_126_PULLDOWN PULLDOWN_DISABLE +#define GPIO_127_PULLDOWN PULLDOWN_DISABLE +#define GPIO_128_PULLDOWN PULLDOWN_DISABLE +#define GPIO_129_PULLDOWN PULLDOWN_DISABLE +#define GPIO_130_PULLDOWN PULLDOWN_DISABLE +#define GPIO_131_PULLDOWN PULLDOWN_DISABLE +#define GPIO_132_PULLDOWN PULLDOWN_DISABLE +#define GPIO_133_PULLDOWN PULLDOWN_DISABLE +#define GPIO_134_PULLDOWN PULLDOWN_DISABLE +#define GPIO_135_PULLDOWN PULLDOWN_DISABLE +#define GPIO_136_PULLDOWN PULLDOWN_DISABLE +#define GPIO_137_PULLDOWN PULLDOWN_DISABLE +#define GPIO_138_PULLDOWN PULLDOWN_DISABLE +#define GPIO_139_PULLDOWN PULLDOWN_DISABLE +#define GPIO_140_PULLDOWN PULLDOWN_DISABLE +#define GPIO_141_PULLDOWN PULLDOWN_DISABLE +#define GPIO_142_PULLDOWN PULLDOWN_DISABLE +#define GPIO_143_PULLDOWN PULLDOWN_DISABLE +#define GPIO_144_PULLDOWN PULLDOWN_DISABLE +#define GPIO_145_PULLDOWN PULLDOWN_DISABLE +#define GPIO_146_PULLDOWN PULLDOWN_DISABLE +#define GPIO_147_PULLDOWN PULLDOWN_DISABLE +#define GPIO_148_PULLDOWN PULLDOWN_DISABLE +#define GPIO_149_PULLDOWN PULLDOWN_DISABLE +#define GPIO_150_PULLDOWN PULLDOWN_DISABLE +#define GPIO_151_PULLDOWN PULLDOWN_DISABLE +#define GPIO_152_PULLDOWN PULLDOWN_DISABLE +#define GPIO_153_PULLDOWN PULLDOWN_DISABLE +#define GPIO_154_PULLDOWN PULLDOWN_DISABLE +#define GPIO_155_PULLDOWN PULLDOWN_DISABLE +#define GPIO_156_PULLDOWN PULLDOWN_DISABLE +#define GPIO_157_PULLDOWN PULLDOWN_DISABLE +#define GPIO_158_PULLDOWN PULLDOWN_DISABLE +#define GPIO_159_PULLDOWN PULLDOWN_DISABLE +#define GPIO_160_PULLDOWN PULLDOWN_DISABLE +#define GPIO_161_PULLDOWN PULLDOWN_DISABLE +#define GPIO_162_PULLDOWN PULLDOWN_ENABLE +#define GPIO_163_PULLDOWN PULLDOWN_ENABLE +#define GPIO_164_PULLDOWN PULLDOWN_ENABLE +#define GPIO_165_PULLDOWN PULLDOWN_DISABLE +#define GPIO_166_PULLDOWN PULLDOWN_DISABLE +#define GPIO_167_PULLDOWN PULLDOWN_ENABLE +#define GPIO_168_PULLDOWN PULLDOWN_DISABLE +#define GPIO_169_PULLDOWN PULLDOWN_DISABLE +#define GPIO_170_PULLDOWN PULLDOWN_DISABLE +#define GPIO_171_PULLDOWN PULLDOWN_DISABLE +#define GPIO_172_PULLDOWN PULLDOWN_DISABLE +#define GPIO_173_PULLDOWN PULLDOWN_DISABLE +#define GPIO_174_PULLDOWN PULLDOWN_DISABLE +#define GPIO_175_PULLDOWN PULLDOWN_DISABLE +#define GPIO_176_PULLDOWN PULLDOWN_DISABLE +#define GPIO_177_PULLDOWN PULLDOWN_DISABLE +#define GPIO_178_PULLDOWN PULLDOWN_DISABLE +#define GPIO_179_PULLDOWN PULLDOWN_DISABLE +#define GPIO_180_PULLDOWN PULLDOWN_DISABLE +#define GPIO_180_PULLDOWN PULLDOWN_DISABLE +#define GPIO_181_PULLDOWN PULLDOWN_DISABLE +#define GPIO_182_PULLDOWN PULLDOWN_DISABLE +#define GPIO_183_PULLDOWN PULLDOWN_DISABLE +#define GPIO_184_PULLDOWN PULLDOWN_DISABLE +#define GPIO_185_PULLDOWN PULLDOWN_ENABLE +#define GPIO_186_PULLDOWN PULLDOWN_ENABLE +#define GPIO_187_PULLDOWN PULLDOWN_DISABLE +#define GPIO_188_PULLDOWN PULLDOWN_DISABLE +#define GPIO_189_PULLDOWN PULLDOWN_DISABLE +#define GPIO_190_PULLDOWN PULLDOWN_DISABLE +#define GPIO_191_PULLDOWN PULLDOWN_DISABLE +#define GPIO_192_PULLDOWN PULLDOWN_DISABLE +#define GPIO_193_PULLDOWN PULLDOWN_DISABLE +#define GPIO_194_PULLDOWN PULLDOWN_DISABLE +#define GPIO_195_PULLDOWN PULLDOWN_DISABLE +#define GPIO_196_PULLDOWN PULLDOWN_DISABLE +#define GPIO_197_PULLDOWN PULLDOWN_DISABLE +#define GPIO_198_PULLDOWN PULLDOWN_DISABLE +#define GPIO_199_PULLDOWN PULLDOWN_DISABLE +#define GPIO_200_PULLDOWN PULLDOWN_DISABLE +#define GPIO_201_PULLDOWN PULLDOWN_DISABLE +#define GPIO_202_PULLDOWN PULLDOWN_DISABLE +#define GPIO_203_PULLDOWN PULLDOWN_DISABLE +#define GPIO_204_PULLDOWN PULLDOWN_DISABLE +#define GPIO_205_PULLDOWN PULLDOWN_DISABLE +#define GPIO_206_PULLDOWN PULLDOWN_DISABLE +#define GPIO_207_PULLDOWN PULLDOWN_DISABLE +#define GPIO_208_PULLDOWN PULLDOWN_DISABLE +#define GPIO_209_PULLDOWN PULLDOWN_DISABLE +#define GPIO_210_PULLDOWN PULLDOWN_DISABLE +#define GPIO_211_PULLDOWN PULLDOWN_DISABLE +#define GPIO_212_PULLDOWN PULLDOWN_DISABLE +#define GPIO_213_PULLDOWN PULLDOWN_DISABLE +#define GPIO_214_PULLDOWN PULLDOWN_DISABLE +#define GPIO_215_PULLDOWN PULLDOWN_DISABLE +#define GPIO_216_PULLDOWN PULLDOWN_DISABLE +#define GPIO_217_PULLDOWN PULLDOWN_DISABLE +#define GPIO_218_PULLDOWN PULLDOWN_DISABLE +#define GPIO_219_PULLDOWN PULLDOWN_DISABLE +#define GPIO_220_PULLDOWN PULLDOWN_DISABLE +#define GPIO_221_PULLDOWN PULLDOWN_DISABLE +#define GPIO_222_PULLDOWN PULLDOWN_DISABLE +#define GPIO_223_PULLDOWN PULLDOWN_DISABLE +#define GPIO_224_PULLDOWN PULLDOWN_DISABLE +#define GPIO_225_PULLDOWN PULLDOWN_DISABLE +#define GPIO_226_PULLDOWN PULLDOWN_DISABLE +#define GPIO_227_PULLDOWN PULLDOWN_DISABLE +#define GPIO_228_PULLDOWN PULLDOWN_DISABLE +#define GPIO_229_PULLDOWN PULLDOWN_DISABLE + +#define EVENT_DISABLE 0 +#define EVENT_ENABLE 1 + +#define GEVENT_00_EVENTENABLE EVENT_DISABLE +#define GEVENT_01_EVENTENABLE EVENT_DISABLE +#define GEVENT_02_EVENTENABLE EVENT_ENABLE // APU THERMTRIP# +#define GEVENT_03_EVENTENABLE EVENT_ENABLE // EC_SCI# +#define GEVENT_04_EVENTENABLE EVENT_ENABLE // APU_MEMHOT# +#define GEVENT_05_EVENTENABLE EVENT_ENABLE // PCIE_EXPCARD_PWREN# +#define GEVENT_06_EVENTENABLE EVENT_DISABLE +#define GEVENT_07_EVENTENABLE EVENT_DISABLE +#define GEVENT_08_EVENTENABLE EVENT_DISABLE +#define GEVENT_09_EVENTENABLE EVENT_ENABLE // WF_RADIO +#define GEVENT_10_EVENTENABLE EVENT_DISABLE +#define GEVENT_11_EVENTENABLE EVENT_DISABLE +#define GEVENT_12_EVENTENABLE EVENT_ENABLE // SMBALERT# +#define GEVENT_13_EVENTENABLE EVENT_DISABLE +#define GEVENT_14_EVENTENABLE EVENT_ENABLE // LASSO_DET#/DOCK# +#define GEVENT_15_EVENTENABLE EVENT_ENABLE // ODD_PLUGIN# +#define GEVENT_16_EVENTENABLE EVENT_ENABLE // ODD_DA +#define GEVENT_17_EVENTENABLE EVENT_ENABLE // TWARN +#define GEVENT_18_EVENTENABLE EVENT_DISABLE +#define GEVENT_19_EVENTENABLE EVENT_DISABLE +#define GEVENT_20_EVENTENABLE EVENT_DISABLE +#define GEVENT_21_EVENTENABLE EVENT_DISABLE +#define GEVENT_22_EVENTENABLE EVENT_ENABLE // LID_CLOSE# +#define GEVENT_23_EVENTENABLE EVENT_DISABLE // EC_SMI# + +#define SCITRIG_LOW 0 +#define SCITRIG_HI 1 + +#define GEVENT_00_SCITRIG SCITRIG_LOW +#define GEVENT_01_SCITRIG SCITRIG_LOW +#define GEVENT_02_SCITRIG SCITRIG_LOW +#define GEVENT_03_SCITRIG SCITRIG_LOW +#define GEVENT_04_SCITRIG SCITRIG_LOW +#define GEVENT_05_SCITRIG SCITRIG_LOW +#define GEVENT_06_SCITRIG SCITRIG_LOW +#define GEVENT_07_SCITRIG SCITRIG_LOW +#define GEVENT_08_SCITRIG SCITRIG_LOW +#define GEVENT_09_SCITRIG SCITRIG_LOW +#define GEVENT_10_SCITRIG SCITRIG_LOW +#define GEVENT_11_SCITRIG SCITRIG_LOW +#define GEVENT_12_SCITRIG SCITRIG_LOW +#define GEVENT_13_SCITRIG SCITRIG_LOW +#define GEVENT_14_SCITRIG SCITRIG_LOW +#define GEVENT_15_SCITRIG SCITRIG_LOW +#define GEVENT_16_SCITRIG SCITRIG_LOW +#define GEVENT_17_SCITRIG SCITRIG_HI +#define GEVENT_18_SCITRIG SCITRIG_LOW +#define GEVENT_19_SCITRIG SCITRIG_LOW +#define GEVENT_20_SCITRIG SCITRIG_LOW +#define GEVENT_21_SCITRIG SCITRIG_LOW +#define GEVENT_22_SCITRIG SCITRIG_LOW +#define GEVENT_23_SCITRIG SCITRIG_LOW + +#define SCILEVEL_EDGE 0 +#define SCILEVEL_LEVEL 1 + +#define GEVENT_00_SCILEVEL SCILEVEL_EDGE +#define GEVENT_01_SCILEVEL SCILEVEL_EDGE +#define GEVENT_02_SCILEVEL SCILEVEL_EDGE +#define GEVENT_03_SCILEVEL SCILEVEL_EDGE +#define GEVENT_04_SCILEVEL SCILEVEL_EDGE +#define GEVENT_05_SCILEVEL SCILEVEL_EDGE +#define GEVENT_06_SCILEVEL SCILEVEL_EDGE +#define GEVENT_07_SCILEVEL SCILEVEL_EDGE +#define GEVENT_08_SCILEVEL SCILEVEL_EDGE +#define GEVENT_09_SCILEVEL SCILEVEL_EDGE +#define GEVENT_10_SCILEVEL SCILEVEL_EDGE +#define GEVENT_11_SCILEVEL SCILEVEL_EDGE +#define GEVENT_12_SCILEVEL SCILEVEL_EDGE +#define GEVENT_13_SCILEVEL SCILEVEL_EDGE +#define GEVENT_14_SCILEVEL SCILEVEL_EDGE +#define GEVENT_15_SCILEVEL SCILEVEL_EDGE +#define GEVENT_16_SCILEVEL SCILEVEL_EDGE +#define GEVENT_17_SCILEVEL SCILEVEL_EDGE +#define GEVENT_18_SCILEVEL SCILEVEL_EDGE +#define GEVENT_19_SCILEVEL SCILEVEL_EDGE +#define GEVENT_20_SCILEVEL SCILEVEL_EDGE +#define GEVENT_21_SCILEVEL SCILEVEL_EDGE +#define GEVENT_22_SCILEVEL SCILEVEL_EDGE +#define GEVENT_23_SCILEVEL SCILEVEL_EDGE + +#define SMISCI_DISABLE 0 +#define SMISCI_ENABLE 1 + +#define GEVENT_00_SMISCIEN SMISCI_DISABLE +#define GEVENT_01_SMISCIEN SMISCI_DISABLE +#define GEVENT_02_SMISCIEN SMISCI_DISABLE +#define GEVENT_03_SMISCIEN SMISCI_DISABLE +#define GEVENT_04_SMISCIEN SMISCI_DISABLE +#define GEVENT_05_SMISCIEN SMISCI_DISABLE +#define GEVENT_06_SMISCIEN SMISCI_DISABLE +#define GEVENT_07_SMISCIEN SMISCI_DISABLE +#define GEVENT_08_SMISCIEN SMISCI_DISABLE +#define GEVENT_09_SMISCIEN SMISCI_DISABLE +#define GEVENT_10_SMISCIEN SMISCI_DISABLE +#define GEVENT_11_SMISCIEN SMISCI_DISABLE +#define GEVENT_12_SMISCIEN SMISCI_DISABLE +#define GEVENT_13_SMISCIEN SMISCI_DISABLE +#define GEVENT_14_SMISCIEN SMISCI_DISABLE +#define GEVENT_15_SMISCIEN SMISCI_DISABLE +#define GEVENT_16_SMISCIEN SMISCI_DISABLE +#define GEVENT_17_SMISCIEN SMISCI_DISABLE +#define GEVENT_18_SMISCIEN SMISCI_DISABLE +#define GEVENT_19_SMISCIEN SMISCI_DISABLE +#define GEVENT_20_SMISCIEN SMISCI_DISABLE +#define GEVENT_21_SMISCIEN SMISCI_DISABLE +#define GEVENT_22_SMISCIEN SMISCI_DISABLE +#define GEVENT_23_SMISCIEN SMISCI_DISABLE + +#define SCIS0_DISABLE 0 +#define SCIS0_ENABLE 1 + +#define GEVENT_00_SCIS0EN SCIS0_DISABLE +#define GEVENT_01_SCIS0EN SCIS0_DISABLE +#define GEVENT_02_SCIS0EN SCIS0_DISABLE +#define GEVENT_03_SCIS0EN SCIS0_DISABLE +#define GEVENT_04_SCIS0EN SCIS0_DISABLE +#define GEVENT_05_SCIS0EN SCIS0_DISABLE +#define GEVENT_06_SCIS0EN SCIS0_DISABLE +#define GEVENT_07_SCIS0EN SCIS0_DISABLE +#define GEVENT_08_SCIS0EN SCIS0_DISABLE +#define GEVENT_09_SCIS0EN SCIS0_DISABLE +#define GEVENT_10_SCIS0EN SCIS0_DISABLE +#define GEVENT_11_SCIS0EN SCIS0_DISABLE +#define GEVENT_12_SCIS0EN SCIS0_DISABLE +#define GEVENT_13_SCIS0EN SCIS0_DISABLE +#define GEVENT_14_SCIS0EN SCIS0_DISABLE +#define GEVENT_15_SCIS0EN SCIS0_DISABLE +#define GEVENT_16_SCIS0EN SCIS0_DISABLE +#define GEVENT_17_SCIS0EN SCIS0_DISABLE +#define GEVENT_18_SCIS0EN SCIS0_DISABLE +#define GEVENT_19_SCIS0EN SCIS0_DISABLE +#define GEVENT_20_SCIS0EN SCIS0_DISABLE +#define GEVENT_21_SCIS0EN SCIS0_DISABLE +#define GEVENT_22_SCIS0EN SCIS0_DISABLE +#define GEVENT_23_SCIS0EN SCIS0_DISABLE + +#define GEVENT_SCIMASK 0x1F +#define GEVENT_00_SCIMAP 0 +#define GEVENT_01_SCIMAP 1 +#define GEVENT_02_SCIMAP 2 +#define GEVENT_03_SCIMAP 3 +#define GEVENT_04_SCIMAP 4 +#define GEVENT_05_SCIMAP 5 +#define GEVENT_06_SCIMAP 6 +#define GEVENT_07_SCIMAP 7 +#define GEVENT_08_SCIMAP 8 +#define GEVENT_09_SCIMAP 9 +#define GEVENT_10_SCIMAP 10 +#define GEVENT_11_SCIMAP 11 +#define GEVENT_12_SCIMAP 12 +#define GEVENT_13_SCIMAP 13 +#define GEVENT_14_SCIMAP 14 +#define GEVENT_15_SCIMAP 15 +#define GEVENT_16_SCIMAP 16 +#define GEVENT_17_SCIMAP 17 +#define GEVENT_18_SCIMAP 18 +#define GEVENT_19_SCIMAP 19 +#define GEVENT_20_SCIMAP 20 +#define GEVENT_21_SCIMAP 21 +#define GEVENT_22_SCIMAP 22 +#define GEVENT_23_SCIMAP 23 + +#define SMITRIG_LOW 0 +#define SMITRIG_HI 1 + +#define GEVENT_00_SMITRIG SMITRIG_HI +#define GEVENT_01_SMITRIG SMITRIG_HI +#define GEVENT_02_SMITRIG SMITRIG_HI +#define GEVENT_03_SMITRIG SMITRIG_HI +#define GEVENT_04_SMITRIG SMITRIG_HI +#define GEVENT_05_SMITRIG SMITRIG_HI +#define GEVENT_06_SMITRIG SMITRIG_HI +#define GEVENT_07_SMITRIG SMITRIG_HI +#define GEVENT_08_SMITRIG SMITRIG_HI +#define GEVENT_09_SMITRIG SMITRIG_HI +#define GEVENT_10_SMITRIG SMITRIG_HI +#define GEVENT_11_SMITRIG SMITRIG_HI +#define GEVENT_12_SMITRIG SMITRIG_HI +#define GEVENT_13_SMITRIG SMITRIG_HI +#define GEVENT_14_SMITRIG SMITRIG_HI +#define GEVENT_15_SMITRIG SMITRIG_HI +#define GEVENT_16_SMITRIG SMITRIG_HI +#define GEVENT_17_SMITRIG SMITRIG_HI +#define GEVENT_18_SMITRIG SMITRIG_HI +#define GEVENT_19_SMITRIG SMITRIG_HI +#define GEVENT_20_SMITRIG SMITRIG_HI +#define GEVENT_21_SMITRIG SMITRIG_HI +#define GEVENT_22_SMITRIG SMITRIG_HI +#define GEVENT_23_SMITRIG SMITRIG_HI + +#define SMICONTROL_MASK 3 +#define SMICONTROL_DISABLE 0 +#define SMICONTROL_SMI 1 +#define SMICONTROL_NMI 2 +#define SMICONTROL_IRQ13 3 + +#define GEVENT_00_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_01_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_02_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_03_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_04_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_05_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_06_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_07_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_08_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_09_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_10_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_11_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_12_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_13_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_14_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_15_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_16_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_17_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_18_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_19_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_20_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_21_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_22_SMICONTROL SMICONTROL_DISABLE +#define GEVENT_23_SMICONTROL SMICONTROL_DISABLE + +#define GPIO_RSVD_ZONE0_S GPIO_81 +#define GPIO_RSVD_ZONE0_E GPIO_95 +#define GPIO_RSVD_ZONE1_S GPIO_120 +#define GPIO_RSVD_ZONE1_E GPIO_127 + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ +typedef enum _GPIO_COUNT +{ + GPIO_00=0, + GPIO_01, + GPIO_02, + GPIO_03, + GPIO_04, + GPIO_05, + GPIO_06, + GPIO_07, + GPIO_08, + GPIO_09, + GPIO_10, + GPIO_11, + GPIO_12, + GPIO_13, + GPIO_14, + GPIO_15, + GPIO_16, + GPIO_17, + GPIO_18, + GPIO_19, + GPIO_20, + GPIO_21, + GPIO_22, + GPIO_23, + GPIO_24, + GPIO_25, + GPIO_26, + GPIO_27, + GPIO_28, + GPIO_29, + GPIO_30, + GPIO_31, + GPIO_32, + GPIO_33, + GPIO_34, + GPIO_35, + GPIO_36, + GPIO_37, + GPIO_38, + GPIO_39, + GPIO_40, + GPIO_41, + GPIO_42, + GPIO_43, + GPIO_44, + GPIO_45, + GPIO_46, + GPIO_47, + GPIO_48, + GPIO_49, + GPIO_50, + GPIO_51, + GPIO_52, + GPIO_53, + GPIO_54, + GPIO_55, + GPIO_56, + GPIO_57, + GPIO_58, + GPIO_59, + GPIO_60, + GPIO_61, + GPIO_62, + GPIO_63, + GPIO_64, + GPIO_65, + GPIO_66, + GPIO_67, + GPIO_68, + GPIO_69, + GPIO_70, + GPIO_71, + GPIO_72, + GPIO_73, + GPIO_74, + GPIO_75, + GPIO_76, + GPIO_77, + GPIO_78, + GPIO_79, + GPIO_80, + GPIO_81, + GPIO_82, + GPIO_83, + GPIO_84, + GPIO_85, + GPIO_86, + GPIO_87, + GPIO_88, + GPIO_89, + GPIO_90, + GPIO_91, + GPIO_92, + GPIO_93, + GPIO_94, + GPIO_95, + GPIO_96, + GPIO_97, + GPIO_98, + GPIO_99, + GPIO_100, + GPIO_101, + GPIO_102, + GPIO_103, + GPIO_104, + GPIO_105, + GPIO_106, + GPIO_107, + GPIO_108, + GPIO_109, + GPIO_110, + GPIO_111, + GPIO_112, + GPIO_113, + GPIO_114, + GPIO_115, + GPIO_116, + GPIO_117, + GPIO_118, + GPIO_119, + GPIO_120, + GPIO_121, + GPIO_122, + GPIO_123, + GPIO_124, + GPIO_125, + GPIO_126, + GPIO_127, + GPIO_128, + GPIO_129, + GPIO_130, + GPIO_131, + GPIO_132, + GPIO_133, + GPIO_134, + GPIO_135, + GPIO_136, + GPIO_137, + GPIO_138, + GPIO_139, + GPIO_140, + GPIO_141, + GPIO_142, + GPIO_143, + GPIO_144, + GPIO_145, + GPIO_146, + GPIO_147, + GPIO_148, + GPIO_149, + GPIO_150, + GPIO_151, + GPIO_152, + GPIO_153, + GPIO_154, + GPIO_155, + GPIO_156, + GPIO_157, + GPIO_158, + GPIO_159, + GPIO_160, + GPIO_161, + GPIO_162, + GPIO_163, + GPIO_164, + GPIO_165, + GPIO_166, + GPIO_167, + GPIO_168, + GPIO_169, + GPIO_170, + GPIO_171, + GPIO_172, + GPIO_173, + GPIO_174, + GPIO_175, + GPIO_176, + GPIO_177, + GPIO_178, + GPIO_179, + GPIO_180, + GPIO_181, + GPIO_182, + GPIO_183, + GPIO_184, + GPIO_185, + GPIO_186, + GPIO_187, + GPIO_188, + GPIO_189, + GPIO_190, + GPIO_191, + GPIO_192, + GPIO_193, + GPIO_194, + GPIO_195, + GPIO_196, + GPIO_197, + GPIO_198, + GPIO_199, + GPIO_200, + GPIO_201, + GPIO_202, + GPIO_203, + GPIO_204, + GPIO_205, + GPIO_206, + GPIO_207, + GPIO_208, + GPIO_209, + GPIO_210, + GPIO_211, + GPIO_212, + GPIO_213, + GPIO_214, + GPIO_215, + GPIO_216, + GPIO_217, + GPIO_218, + GPIO_219, + GPIO_220, + GPIO_221, + GPIO_222, + GPIO_223, + GPIO_224, + GPIO_225, + GPIO_226, + GPIO_227, + GPIO_228, + GPIO_229, + MAX_GPIO_NO +} GPIO_COUNT; + +typedef struct _GPIO_SETTINGS +{ + u8 select; + u8 type; + u8 value; + u8 NonGpioGevent; +} GPIO_SETTINGS; + +GPIO_SETTINGS gpio_table[]= +{ + {GPIO_00_SELECT, GPIO_00_TYPE, GPO_00_LEVEL+GPIO_00_STICKY+GPIO_00_PULLUP+GPIO_00_PULLDOWN, GPIO_00_SELECT}, + {GPIO_01_SELECT, GPIO_01_TYPE, GPO_01_LEVEL+GPIO_01_STICKY+GPIO_01_PULLUP+GPIO_01_PULLDOWN, GPIO_01_SELECT}, + {GPIO_02_SELECT, GPIO_02_TYPE, GPO_02_LEVEL+GPIO_02_STICKY+GPIO_02_PULLUP+GPIO_02_PULLDOWN, GPIO_02_SELECT}, + {GPIO_03_SELECT, GPIO_03_TYPE, GPO_03_LEVEL+GPIO_03_STICKY+GPIO_03_PULLUP+GPIO_03_PULLDOWN, GPIO_03_SELECT}, + {GPIO_04_SELECT, GPIO_04_TYPE, GPO_04_LEVEL+GPIO_04_STICKY+GPIO_04_PULLUP+GPIO_04_PULLDOWN, GPIO_04_SELECT}, + {GPIO_05_SELECT, GPIO_05_TYPE, GPO_05_LEVEL+GPIO_05_STICKY+GPIO_05_PULLUP+GPIO_05_PULLDOWN, GPIO_05_SELECT}, + {GPIO_06_SELECT, GPIO_06_TYPE, GPO_06_LEVEL+GPIO_06_STICKY+GPIO_06_PULLUP+GPIO_06_PULLDOWN, GPIO_06_SELECT}, + {GPIO_07_SELECT, GPIO_07_TYPE, GPO_07_LEVEL+GPIO_07_STICKY+GPIO_07_PULLUP+GPIO_07_PULLDOWN, GPIO_07_SELECT}, + {GPIO_08_SELECT, GPIO_08_TYPE, GPO_08_LEVEL+GPIO_08_STICKY+GPIO_08_PULLUP+GPIO_08_PULLDOWN, GPIO_08_SELECT}, + {GPIO_09_SELECT, GPIO_09_TYPE, GPO_09_LEVEL+GPIO_09_STICKY+GPIO_09_PULLUP+GPIO_09_PULLDOWN, GPIO_09_SELECT}, + {GPIO_10_SELECT, GPIO_10_TYPE, GPO_10_LEVEL+GPIO_10_STICKY+GPIO_10_PULLUP+GPIO_10_PULLDOWN, GPIO_10_SELECT}, + {GPIO_11_SELECT, GPIO_11_TYPE, GPO_11_LEVEL+GPIO_11_STICKY+GPIO_11_PULLUP+GPIO_11_PULLDOWN, GPIO_11_SELECT}, + {GPIO_12_SELECT, GPIO_12_TYPE, GPO_12_LEVEL+GPIO_12_STICKY+GPIO_12_PULLUP+GPIO_12_PULLDOWN, GPIO_12_SELECT}, + {GPIO_13_SELECT, GPIO_13_TYPE, GPO_13_LEVEL+GPIO_13_STICKY+GPIO_13_PULLUP+GPIO_13_PULLDOWN, GPIO_13_SELECT}, + {GPIO_14_SELECT, GPIO_14_TYPE, GPO_14_LEVEL+GPIO_14_STICKY+GPIO_14_PULLUP+GPIO_14_PULLDOWN, GPIO_14_SELECT}, + {GPIO_15_SELECT, GPIO_15_TYPE, GPO_15_LEVEL+GPIO_15_STICKY+GPIO_15_PULLUP+GPIO_15_PULLDOWN, GPIO_15_SELECT}, + {GPIO_16_SELECT, GPIO_16_TYPE, GPO_16_LEVEL+GPIO_16_STICKY+GPIO_16_PULLUP+GPIO_16_PULLDOWN, GPIO_16_SELECT}, + {GPIO_17_SELECT, GPIO_17_TYPE, GPO_17_LEVEL+GPIO_17_STICKY+GPIO_17_PULLUP+GPIO_17_PULLDOWN, GPIO_17_SELECT}, + {GPIO_18_SELECT, GPIO_18_TYPE, GPO_18_LEVEL+GPIO_18_STICKY+GPIO_18_PULLUP+GPIO_18_PULLDOWN, GPIO_18_SELECT}, + {GPIO_19_SELECT, GPIO_19_TYPE, GPO_19_LEVEL+GPIO_19_STICKY+GPIO_19_PULLUP+GPIO_19_PULLDOWN, GPIO_19_SELECT}, + {GPIO_20_SELECT, GPIO_20_TYPE, GPO_20_LEVEL+GPIO_20_STICKY+GPIO_20_PULLUP+GPIO_20_PULLDOWN, GPIO_20_SELECT}, + {GPIO_21_SELECT, GPIO_21_TYPE, GPO_21_LEVEL+GPIO_21_STICKY+GPIO_21_PULLUP+GPIO_21_PULLDOWN, GPIO_21_SELECT}, + {GPIO_22_SELECT, GPIO_22_TYPE, GPO_22_LEVEL+GPIO_22_STICKY+GPIO_22_PULLUP+GPIO_22_PULLDOWN, GPIO_22_SELECT}, + {GPIO_23_SELECT, GPIO_23_TYPE, GPO_23_LEVEL+GPIO_23_STICKY+GPIO_23_PULLUP+GPIO_23_PULLDOWN, GPIO_23_SELECT}, + {GPIO_24_SELECT, GPIO_24_TYPE, GPO_24_LEVEL+GPIO_24_STICKY+GPIO_24_PULLUP+GPIO_24_PULLDOWN, GPIO_24_SELECT}, + {GPIO_25_SELECT, GPIO_25_TYPE, GPO_25_LEVEL+GPIO_25_STICKY+GPIO_25_PULLUP+GPIO_25_PULLDOWN, GPIO_25_SELECT}, + {GPIO_26_SELECT, GPIO_26_TYPE, GPO_26_LEVEL+GPIO_26_STICKY+GPIO_26_PULLUP+GPIO_26_PULLDOWN, GPIO_26_SELECT}, + {GPIO_27_SELECT, GPIO_27_TYPE, GPO_27_LEVEL+GPIO_27_STICKY+GPIO_27_PULLUP+GPIO_27_PULLDOWN, GPIO_27_SELECT}, + {GPIO_28_SELECT, GPIO_28_TYPE, GPO_28_LEVEL+GPIO_28_STICKY+GPIO_28_PULLUP+GPIO_28_PULLDOWN, GPIO_28_SELECT}, + {GPIO_29_SELECT, GPIO_29_TYPE, GPO_29_LEVEL+GPIO_29_STICKY+GPIO_29_PULLUP+GPIO_29_PULLDOWN, GPIO_29_SELECT}, + {GPIO_30_SELECT, GPIO_30_TYPE, GPO_30_LEVEL+GPIO_30_STICKY+GPIO_30_PULLUP+GPIO_30_PULLDOWN, GPIO_30_SELECT}, + {GPIO_31_SELECT, GPIO_31_TYPE, GPO_31_LEVEL+GPIO_31_STICKY+GPIO_31_PULLUP+GPIO_31_PULLDOWN, GPIO_31_SELECT}, + {GPIO_32_SELECT, GPIO_32_TYPE, GPO_32_LEVEL+GPIO_32_STICKY+GPIO_32_PULLUP+GPIO_32_PULLDOWN, GPIO_32_SELECT}, + {GPIO_33_SELECT, GPIO_33_TYPE, GPO_33_LEVEL+GPIO_33_STICKY+GPIO_33_PULLUP+GPIO_33_PULLDOWN, GPIO_33_SELECT}, + {GPIO_34_SELECT, GPIO_34_TYPE, GPO_34_LEVEL+GPIO_34_STICKY+GPIO_34_PULLUP+GPIO_34_PULLDOWN, GPIO_34_SELECT}, + {GPIO_35_SELECT, GPIO_35_TYPE, GPO_35_LEVEL+GPIO_35_STICKY+GPIO_35_PULLUP+GPIO_35_PULLDOWN, GPIO_35_SELECT}, + {GPIO_36_SELECT, GPIO_36_TYPE, GPO_36_LEVEL+GPIO_36_STICKY+GPIO_36_PULLUP+GPIO_36_PULLDOWN, GPIO_36_SELECT}, + {GPIO_37_SELECT, GPIO_37_TYPE, GPO_37_LEVEL+GPIO_37_STICKY+GPIO_37_PULLUP+GPIO_37_PULLDOWN, GPIO_37_SELECT}, + {GPIO_38_SELECT, GPIO_38_TYPE, GPO_38_LEVEL+GPIO_38_STICKY+GPIO_38_PULLUP+GPIO_38_PULLDOWN, GPIO_38_SELECT}, + {GPIO_39_SELECT, GPIO_39_TYPE, GPO_39_LEVEL+GPIO_39_STICKY+GPIO_39_PULLUP+GPIO_39_PULLDOWN, GPIO_39_SELECT}, + {GPIO_40_SELECT, GPIO_40_TYPE, GPO_40_LEVEL+GPIO_40_STICKY+GPIO_40_PULLUP+GPIO_40_PULLDOWN, GPIO_40_SELECT}, + {GPIO_41_SELECT, GPIO_41_TYPE, GPO_41_LEVEL+GPIO_41_STICKY+GPIO_41_PULLUP+GPIO_41_PULLDOWN, GPIO_41_SELECT}, + {GPIO_42_SELECT, GPIO_42_TYPE, GPO_42_LEVEL+GPIO_42_STICKY+GPIO_42_PULLUP+GPIO_42_PULLDOWN, GPIO_42_SELECT}, + {GPIO_43_SELECT, GPIO_43_TYPE, GPO_43_LEVEL+GPIO_43_STICKY+GPIO_43_PULLUP+GPIO_43_PULLDOWN, GPIO_43_SELECT}, + {GPIO_44_SELECT, GPIO_44_TYPE, GPO_44_LEVEL+GPIO_44_STICKY+GPIO_44_PULLUP+GPIO_44_PULLDOWN, GPIO_44_SELECT}, + {GPIO_45_SELECT, GPIO_45_TYPE, GPO_45_LEVEL+GPIO_45_STICKY+GPIO_45_PULLUP+GPIO_45_PULLDOWN, GPIO_45_SELECT}, + {GPIO_46_SELECT, GPIO_46_TYPE, GPO_46_LEVEL+GPIO_46_STICKY+GPIO_46_PULLUP+GPIO_46_PULLDOWN, GPIO_46_SELECT}, + {GPIO_47_SELECT, GPIO_47_TYPE, GPO_47_LEVEL+GPIO_47_STICKY+GPIO_47_PULLUP+GPIO_47_PULLDOWN, GPIO_47_SELECT}, + {GPIO_48_SELECT, GPIO_48_TYPE, GPO_48_LEVEL+GPIO_48_STICKY+GPIO_48_PULLUP+GPIO_48_PULLDOWN, GPIO_48_SELECT}, + {GPIO_49_SELECT, GPIO_49_TYPE, GPO_49_LEVEL+GPIO_49_STICKY+GPIO_49_PULLUP+GPIO_49_PULLDOWN, GPIO_49_SELECT}, + {GPIO_50_SELECT, GPIO_50_TYPE, GPO_50_LEVEL+GPIO_50_STICKY+GPIO_50_PULLUP+GPIO_50_PULLDOWN, GPIO_50_SELECT}, + {GPIO_51_SELECT, GPIO_51_TYPE, GPO_51_LEVEL+GPIO_51_STICKY+GPIO_51_PULLUP+GPIO_51_PULLDOWN, GPIO_51_SELECT}, + {GPIO_52_SELECT, GPIO_52_TYPE, GPO_52_LEVEL+GPIO_52_STICKY+GPIO_52_PULLUP+GPIO_52_PULLDOWN, GPIO_52_SELECT}, + {GPIO_53_SELECT, GPIO_53_TYPE, GPO_53_LEVEL+GPIO_53_STICKY+GPIO_53_PULLUP+GPIO_53_PULLDOWN, GPIO_53_SELECT}, + {GPIO_54_SELECT, GPIO_54_TYPE, GPO_54_LEVEL+GPIO_54_STICKY+GPIO_54_PULLUP+GPIO_54_PULLDOWN, GPIO_54_SELECT}, + {GPIO_55_SELECT, GPIO_55_TYPE, GPO_55_LEVEL+GPIO_55_STICKY+GPIO_55_PULLUP+GPIO_55_PULLDOWN, GPIO_55_SELECT}, + {GPIO_56_SELECT, GPIO_56_TYPE, GPO_56_LEVEL+GPIO_56_STICKY+GPIO_56_PULLUP+GPIO_56_PULLDOWN, GPIO_56_SELECT}, + {GPIO_57_SELECT, GPIO_57_TYPE, GPO_57_LEVEL+GPIO_57_STICKY+GPIO_57_PULLUP+GPIO_57_PULLDOWN, GPIO_57_SELECT}, + {GPIO_58_SELECT, GPIO_58_TYPE, GPO_58_LEVEL+GPIO_58_STICKY+GPIO_58_PULLUP+GPIO_58_PULLDOWN, GPIO_58_SELECT}, + {GPIO_59_SELECT, GPIO_59_TYPE, GPO_59_LEVEL+GPIO_59_STICKY+GPIO_59_PULLUP+GPIO_59_PULLDOWN, GPIO_59_SELECT}, + {GPIO_60_SELECT, GPIO_60_TYPE, GPO_60_LEVEL+GPIO_60_STICKY+GPIO_60_PULLUP+GPIO_60_PULLDOWN, GPIO_60_SELECT}, + {GPIO_61_SELECT, GPIO_61_TYPE, GPO_61_LEVEL+GPIO_61_STICKY+GPIO_61_PULLUP+GPIO_61_PULLDOWN, GPIO_61_SELECT}, + {GPIO_62_SELECT, GPIO_62_TYPE, GPO_62_LEVEL+GPIO_62_STICKY+GPIO_62_PULLUP+GPIO_62_PULLDOWN, GPIO_62_SELECT}, + {GPIO_63_SELECT, GPIO_63_TYPE, GPO_63_LEVEL+GPIO_63_STICKY+GPIO_63_PULLUP+GPIO_63_PULLDOWN, GPIO_63_SELECT}, + {GPIO_64_SELECT, GPIO_64_TYPE, GPO_64_LEVEL+GPIO_64_STICKY+GPIO_64_PULLUP+GPIO_64_PULLDOWN, GPIO_64_SELECT}, + {GPIO_65_SELECT, GPIO_65_TYPE, GPO_65_LEVEL+GPIO_65_STICKY+GPIO_65_PULLUP+GPIO_65_PULLDOWN, GPIO_65_SELECT}, + {GPIO_66_SELECT, GPIO_66_TYPE, GPO_66_LEVEL+GPIO_66_STICKY+GPIO_66_PULLUP+GPIO_66_PULLDOWN, GPIO_66_SELECT}, + {GPIO_67_SELECT, GPIO_67_TYPE, GPO_67_LEVEL+GPIO_67_STICKY+GPIO_67_PULLUP+GPIO_67_PULLDOWN, GPIO_67_SELECT}, + {GPIO_68_SELECT, GPIO_68_TYPE, GPO_68_LEVEL+GPIO_68_STICKY+GPIO_68_PULLUP+GPIO_68_PULLDOWN, GPIO_68_SELECT}, + {GPIO_69_SELECT, GPIO_69_TYPE, GPO_69_LEVEL+GPIO_69_STICKY+GPIO_69_PULLUP+GPIO_69_PULLDOWN, GPIO_69_SELECT}, + {GPIO_70_SELECT, GPIO_70_TYPE, GPO_70_LEVEL+GPIO_70_STICKY+GPIO_70_PULLUP+GPIO_70_PULLDOWN, GPIO_70_SELECT}, + {GPIO_71_SELECT, GPIO_71_TYPE, GPO_71_LEVEL+GPIO_71_STICKY+GPIO_71_PULLUP+GPIO_71_PULLDOWN, GPIO_71_SELECT}, + {GPIO_72_SELECT, GPIO_72_TYPE, GPO_72_LEVEL+GPIO_72_STICKY+GPIO_72_PULLUP+GPIO_72_PULLDOWN, GPIO_72_SELECT}, + {GPIO_73_SELECT, GPIO_73_TYPE, GPO_73_LEVEL+GPIO_73_STICKY+GPIO_73_PULLUP+GPIO_73_PULLDOWN, GPIO_73_SELECT}, + {GPIO_74_SELECT, GPIO_74_TYPE, GPO_74_LEVEL+GPIO_74_STICKY+GPIO_74_PULLUP+GPIO_74_PULLDOWN, GPIO_74_SELECT}, + {GPIO_75_SELECT, GPIO_75_TYPE, GPO_75_LEVEL+GPIO_75_STICKY+GPIO_75_PULLUP+GPIO_75_PULLDOWN, GPIO_75_SELECT}, + {GPIO_76_SELECT, GPIO_76_TYPE, GPO_76_LEVEL+GPIO_76_STICKY+GPIO_76_PULLUP+GPIO_76_PULLDOWN, GPIO_76_SELECT}, + {GPIO_77_SELECT, GPIO_77_TYPE, GPO_77_LEVEL+GPIO_77_STICKY+GPIO_77_PULLUP+GPIO_77_PULLDOWN, GPIO_77_SELECT}, + {GPIO_78_SELECT, GPIO_78_TYPE, GPO_78_LEVEL+GPIO_78_STICKY+GPIO_78_PULLUP+GPIO_78_PULLDOWN, GPIO_78_SELECT}, + {GPIO_79_SELECT, GPIO_79_TYPE, GPO_79_LEVEL+GPIO_79_STICKY+GPIO_79_PULLUP+GPIO_79_PULLDOWN, GPIO_79_SELECT}, + {GPIO_80_SELECT, GPIO_80_TYPE, GPO_80_LEVEL+GPIO_80_STICKY+GPIO_80_PULLUP+GPIO_80_PULLDOWN, GPIO_80_SELECT}, + {GPIO_81_SELECT, GPIO_81_TYPE, GPO_81_LEVEL+GPIO_81_STICKY+GPIO_81_PULLUP+GPIO_81_PULLDOWN, GPIO_81_SELECT}, + {GPIO_82_SELECT, GPIO_82_TYPE, GPO_82_LEVEL+GPIO_82_STICKY+GPIO_82_PULLUP+GPIO_82_PULLDOWN, GPIO_82_SELECT}, + {GPIO_83_SELECT, GPIO_83_TYPE, GPO_83_LEVEL+GPIO_83_STICKY+GPIO_83_PULLUP+GPIO_83_PULLDOWN, GPIO_83_SELECT}, + {GPIO_84_SELECT, GPIO_84_TYPE, GPO_84_LEVEL+GPIO_84_STICKY+GPIO_84_PULLUP+GPIO_84_PULLDOWN, GPIO_84_SELECT}, + {GPIO_85_SELECT, GPIO_85_TYPE, GPO_85_LEVEL+GPIO_85_STICKY+GPIO_85_PULLUP+GPIO_85_PULLDOWN, GPIO_85_SELECT}, + {GPIO_86_SELECT, GPIO_86_TYPE, GPO_86_LEVEL+GPIO_86_STICKY+GPIO_86_PULLUP+GPIO_86_PULLDOWN, GPIO_86_SELECT}, + {GPIO_87_SELECT, GPIO_87_TYPE, GPO_87_LEVEL+GPIO_87_STICKY+GPIO_87_PULLUP+GPIO_87_PULLDOWN, GPIO_87_SELECT}, + {GPIO_88_SELECT, GPIO_88_TYPE, GPO_88_LEVEL+GPIO_88_STICKY+GPIO_88_PULLUP+GPIO_88_PULLDOWN, GPIO_88_SELECT}, + {GPIO_89_SELECT, GPIO_89_TYPE, GPO_89_LEVEL+GPIO_89_STICKY+GPIO_89_PULLUP+GPIO_89_PULLDOWN, GPIO_89_SELECT}, + {GPIO_90_SELECT, GPIO_90_TYPE, GPO_90_LEVEL+GPIO_90_STICKY+GPIO_90_PULLUP+GPIO_90_PULLDOWN, GPIO_90_SELECT}, + {GPIO_91_SELECT, GPIO_91_TYPE, GPO_91_LEVEL+GPIO_91_STICKY+GPIO_91_PULLUP+GPIO_91_PULLDOWN, GPIO_91_SELECT}, + {GPIO_92_SELECT, GPIO_92_TYPE, GPO_92_LEVEL+GPIO_92_STICKY+GPIO_92_PULLUP+GPIO_92_PULLDOWN, GPIO_92_SELECT}, + {GPIO_93_SELECT, GPIO_93_TYPE, GPO_93_LEVEL+GPIO_93_STICKY+GPIO_93_PULLUP+GPIO_93_PULLDOWN, GPIO_93_SELECT}, + {GPIO_94_SELECT, GPIO_94_TYPE, GPO_94_LEVEL+GPIO_94_STICKY+GPIO_94_PULLUP+GPIO_94_PULLDOWN, GPIO_94_SELECT}, + {GPIO_95_SELECT, GPIO_95_TYPE, GPO_95_LEVEL+GPIO_95_STICKY+GPIO_95_PULLUP+GPIO_95_PULLDOWN, GPIO_95_SELECT}, + {GPIO_96_SELECT, GPIO_96_TYPE, GPO_96_LEVEL+GPIO_96_STICKY+GPIO_96_PULLUP+GPIO_96_PULLDOWN, GPIO_96_SELECT}, + {GPIO_97_SELECT, GPIO_97_TYPE, GPO_97_LEVEL+GPIO_97_STICKY+GPIO_97_PULLUP+GPIO_97_PULLDOWN, GPIO_97_SELECT}, + {GPIO_98_SELECT, GPIO_98_TYPE, GPO_98_LEVEL+GPIO_98_STICKY+GPIO_98_PULLUP+GPIO_98_PULLDOWN, GPIO_98_SELECT}, + {GPIO_99_SELECT, GPIO_99_TYPE, GPO_99_LEVEL+GPIO_99_STICKY+GPIO_99_PULLUP+GPIO_99_PULLDOWN, GPIO_99_SELECT}, + {GPIO_100_SELECT, GPIO_100_TYPE, GPO_100_LEVEL+GPIO_100_STICKY+GPIO_100_PULLUP+GPIO_100_PULLDOWN, GPIO_100_SELECT}, + {GPIO_101_SELECT, GPIO_101_TYPE, GPO_101_LEVEL+GPIO_101_STICKY+GPIO_101_PULLUP+GPIO_101_PULLDOWN, GPIO_101_SELECT}, + {GPIO_102_SELECT, GPIO_102_TYPE, GPO_102_LEVEL+GPIO_102_STICKY+GPIO_102_PULLUP+GPIO_102_PULLDOWN, GPIO_102_SELECT}, + {GPIO_103_SELECT, GPIO_103_TYPE, GPO_103_LEVEL+GPIO_103_STICKY+GPIO_103_PULLUP+GPIO_103_PULLDOWN, GPIO_103_SELECT}, + {GPIO_104_SELECT, GPIO_104_TYPE, GPO_104_LEVEL+GPIO_104_STICKY+GPIO_104_PULLUP+GPIO_104_PULLDOWN, GPIO_104_SELECT}, + {GPIO_105_SELECT, GPIO_105_TYPE, GPO_105_LEVEL+GPIO_105_STICKY+GPIO_105_PULLUP+GPIO_105_PULLDOWN, GPIO_105_SELECT}, + {GPIO_106_SELECT, GPIO_106_TYPE, GPO_106_LEVEL+GPIO_106_STICKY+GPIO_106_PULLUP+GPIO_106_PULLDOWN, GPIO_106_SELECT}, + {GPIO_107_SELECT, GPIO_107_TYPE, GPO_107_LEVEL+GPIO_107_STICKY+GPIO_107_PULLUP+GPIO_107_PULLDOWN, GPIO_107_SELECT}, + {GPIO_108_SELECT, GPIO_108_TYPE, GPO_108_LEVEL+GPIO_108_STICKY+GPIO_108_PULLUP+GPIO_108_PULLDOWN, GPIO_108_SELECT}, + {GPIO_109_SELECT, GPIO_109_TYPE, GPO_109_LEVEL+GPIO_109_STICKY+GPIO_109_PULLUP+GPIO_109_PULLDOWN, GPIO_109_SELECT}, + {GPIO_110_SELECT, GPIO_110_TYPE, GPO_110_LEVEL+GPIO_110_STICKY+GPIO_110_PULLUP+GPIO_110_PULLDOWN, GPIO_110_SELECT}, + {GPIO_111_SELECT, GPIO_111_TYPE, GPO_111_LEVEL+GPIO_111_STICKY+GPIO_111_PULLUP+GPIO_111_PULLDOWN, GPIO_111_SELECT}, + {GPIO_112_SELECT, GPIO_112_TYPE, GPO_112_LEVEL+GPIO_112_STICKY+GPIO_112_PULLUP+GPIO_112_PULLDOWN, GPIO_112_SELECT}, + {GPIO_113_SELECT, GPIO_113_TYPE, GPO_113_LEVEL+GPIO_113_STICKY+GPIO_113_PULLUP+GPIO_113_PULLDOWN, GPIO_113_SELECT}, + {GPIO_114_SELECT, GPIO_114_TYPE, GPO_114_LEVEL+GPIO_114_STICKY+GPIO_114_PULLUP+GPIO_114_PULLDOWN, GPIO_114_SELECT}, + {GPIO_115_SELECT, GPIO_115_TYPE, GPO_115_LEVEL+GPIO_115_STICKY+GPIO_115_PULLUP+GPIO_115_PULLDOWN, GPIO_115_SELECT}, + {GPIO_116_SELECT, GPIO_116_TYPE, GPO_116_LEVEL+GPIO_116_STICKY+GPIO_116_PULLUP+GPIO_116_PULLDOWN, GPIO_116_SELECT}, + {GPIO_117_SELECT, GPIO_117_TYPE, GPO_117_LEVEL+GPIO_117_STICKY+GPIO_117_PULLUP+GPIO_117_PULLDOWN, GPIO_117_SELECT}, + {GPIO_118_SELECT, GPIO_118_TYPE, GPO_118_LEVEL+GPIO_118_STICKY+GPIO_118_PULLUP+GPIO_118_PULLDOWN, GPIO_118_SELECT}, + {GPIO_119_SELECT, GPIO_119_TYPE, GPO_119_LEVEL+GPIO_119_STICKY+GPIO_119_PULLUP+GPIO_119_PULLDOWN, GPIO_119_SELECT}, + {GPIO_120_SELECT, GPIO_120_TYPE, GPO_120_LEVEL+GPIO_120_STICKY+GPIO_120_PULLUP+GPIO_120_PULLDOWN, GPIO_120_SELECT}, + {GPIO_121_SELECT, GPIO_121_TYPE, GPO_121_LEVEL+GPIO_121_STICKY+GPIO_121_PULLUP+GPIO_121_PULLDOWN, GPIO_121_SELECT}, + {GPIO_122_SELECT, GPIO_122_TYPE, GPO_122_LEVEL+GPIO_122_STICKY+GPIO_122_PULLUP+GPIO_122_PULLDOWN, GPIO_122_SELECT}, + {GPIO_123_SELECT, GPIO_123_TYPE, GPO_123_LEVEL+GPIO_123_STICKY+GPIO_123_PULLUP+GPIO_123_PULLDOWN, GPIO_123_SELECT}, + {GPIO_124_SELECT, GPIO_124_TYPE, GPO_124_LEVEL+GPIO_124_STICKY+GPIO_124_PULLUP+GPIO_124_PULLDOWN, GPIO_124_SELECT}, + {GPIO_125_SELECT, GPIO_125_TYPE, GPO_125_LEVEL+GPIO_125_STICKY+GPIO_125_PULLUP+GPIO_125_PULLDOWN, GPIO_125_SELECT}, + {GPIO_126_SELECT, GPIO_126_TYPE, GPO_126_LEVEL+GPIO_126_STICKY+GPIO_126_PULLUP+GPIO_126_PULLDOWN, GPIO_126_SELECT}, + {GPIO_127_SELECT, GPIO_127_TYPE, GPO_127_LEVEL+GPIO_127_STICKY+GPIO_127_PULLUP+GPIO_127_PULLDOWN, GPIO_127_SELECT}, + {GPIO_128_SELECT, GPIO_128_TYPE, GPO_128_LEVEL+GPIO_128_STICKY+GPIO_128_PULLUP+GPIO_128_PULLDOWN, GPIO_128_SELECT}, + {GPIO_129_SELECT, GPIO_129_TYPE, GPO_129_LEVEL+GPIO_129_STICKY+GPIO_129_PULLUP+GPIO_129_PULLDOWN, GPIO_129_SELECT}, + {GPIO_130_SELECT, GPIO_130_TYPE, GPO_130_LEVEL+GPIO_130_STICKY+GPIO_130_PULLUP+GPIO_130_PULLDOWN, GPIO_130_SELECT}, + {GPIO_131_SELECT, GPIO_131_TYPE, GPO_131_LEVEL+GPIO_131_STICKY+GPIO_131_PULLUP+GPIO_131_PULLDOWN, GPIO_131_SELECT}, + {GPIO_132_SELECT, GPIO_132_TYPE, GPO_132_LEVEL+GPIO_132_STICKY+GPIO_132_PULLUP+GPIO_132_PULLDOWN, GPIO_132_SELECT}, + {GPIO_133_SELECT, GPIO_133_TYPE, GPO_133_LEVEL+GPIO_133_STICKY+GPIO_133_PULLUP+GPIO_133_PULLDOWN, GPIO_133_SELECT}, + {GPIO_134_SELECT, GPIO_134_TYPE, GPO_134_LEVEL+GPIO_134_STICKY+GPIO_134_PULLUP+GPIO_134_PULLDOWN, GPIO_134_SELECT}, + {GPIO_135_SELECT, GPIO_135_TYPE, GPO_135_LEVEL+GPIO_135_STICKY+GPIO_135_PULLUP+GPIO_135_PULLDOWN, GPIO_135_SELECT}, + {GPIO_136_SELECT, GPIO_136_TYPE, GPO_136_LEVEL+GPIO_136_STICKY+GPIO_136_PULLUP+GPIO_136_PULLDOWN, GPIO_136_SELECT}, + {GPIO_137_SELECT, GPIO_137_TYPE, GPO_137_LEVEL+GPIO_137_STICKY+GPIO_137_PULLUP+GPIO_137_PULLDOWN, GPIO_137_SELECT}, + {GPIO_138_SELECT, GPIO_138_TYPE, GPO_138_LEVEL+GPIO_138_STICKY+GPIO_138_PULLUP+GPIO_138_PULLDOWN, GPIO_138_SELECT}, + {GPIO_139_SELECT, GPIO_139_TYPE, GPO_139_LEVEL+GPIO_139_STICKY+GPIO_139_PULLUP+GPIO_139_PULLDOWN, GPIO_139_SELECT}, + {GPIO_140_SELECT, GPIO_140_TYPE, GPO_140_LEVEL+GPIO_140_STICKY+GPIO_140_PULLUP+GPIO_140_PULLDOWN, GPIO_140_SELECT}, + {GPIO_141_SELECT, GPIO_141_TYPE, GPO_141_LEVEL+GPIO_141_STICKY+GPIO_141_PULLUP+GPIO_141_PULLDOWN, GPIO_141_SELECT}, + {GPIO_142_SELECT, GPIO_142_TYPE, GPO_142_LEVEL+GPIO_142_STICKY+GPIO_142_PULLUP+GPIO_142_PULLDOWN, GPIO_142_SELECT}, + {GPIO_143_SELECT, GPIO_143_TYPE, GPO_143_LEVEL+GPIO_143_STICKY+GPIO_143_PULLUP+GPIO_143_PULLDOWN, GPIO_143_SELECT}, + {GPIO_144_SELECT, GPIO_144_TYPE, GPO_144_LEVEL+GPIO_144_STICKY+GPIO_144_PULLUP+GPIO_144_PULLDOWN, GPIO_144_SELECT}, + {GPIO_145_SELECT, GPIO_145_TYPE, GPO_145_LEVEL+GPIO_145_STICKY+GPIO_145_PULLUP+GPIO_145_PULLDOWN, GPIO_145_SELECT}, + {GPIO_146_SELECT, GPIO_146_TYPE, GPO_146_LEVEL+GPIO_146_STICKY+GPIO_146_PULLUP+GPIO_146_PULLDOWN, GPIO_146_SELECT}, + {GPIO_147_SELECT, GPIO_147_TYPE, GPO_147_LEVEL+GPIO_147_STICKY+GPIO_147_PULLUP+GPIO_147_PULLDOWN, GPIO_147_SELECT}, + {GPIO_148_SELECT, GPIO_148_TYPE, GPO_148_LEVEL+GPIO_148_STICKY+GPIO_148_PULLUP+GPIO_148_PULLDOWN, GPIO_148_SELECT}, + {GPIO_149_SELECT, GPIO_149_TYPE, GPO_149_LEVEL+GPIO_149_STICKY+GPIO_149_PULLUP+GPIO_149_PULLDOWN, GPIO_149_SELECT}, + {GPIO_150_SELECT, GPIO_150_TYPE, GPO_150_LEVEL+GPIO_150_STICKY+GPIO_150_PULLUP+GPIO_150_PULLDOWN, GPIO_150_SELECT}, + {GPIO_151_SELECT, GPIO_151_TYPE, GPO_151_LEVEL+GPIO_151_STICKY+GPIO_151_PULLUP+GPIO_151_PULLDOWN, GPIO_151_SELECT}, + {GPIO_152_SELECT, GPIO_152_TYPE, GPO_152_LEVEL+GPIO_152_STICKY+GPIO_152_PULLUP+GPIO_152_PULLDOWN, GPIO_152_SELECT}, + {GPIO_153_SELECT, GPIO_153_TYPE, GPO_153_LEVEL+GPIO_153_STICKY+GPIO_153_PULLUP+GPIO_153_PULLDOWN, GPIO_153_SELECT}, + {GPIO_154_SELECT, GPIO_154_TYPE, GPO_154_LEVEL+GPIO_154_STICKY+GPIO_154_PULLUP+GPIO_154_PULLDOWN, GPIO_154_SELECT}, + {GPIO_155_SELECT, GPIO_155_TYPE, GPO_155_LEVEL+GPIO_155_STICKY+GPIO_155_PULLUP+GPIO_155_PULLDOWN, GPIO_155_SELECT}, + {GPIO_156_SELECT, GPIO_156_TYPE, GPO_156_LEVEL+GPIO_156_STICKY+GPIO_156_PULLUP+GPIO_156_PULLDOWN, GPIO_156_SELECT}, + {GPIO_157_SELECT, GPIO_157_TYPE, GPO_157_LEVEL+GPIO_157_STICKY+GPIO_157_PULLUP+GPIO_157_PULLDOWN, GPIO_157_SELECT}, + {GPIO_158_SELECT, GPIO_158_TYPE, GPO_158_LEVEL+GPIO_158_STICKY+GPIO_158_PULLUP+GPIO_158_PULLDOWN, GPIO_158_SELECT}, + {GPIO_159_SELECT, GPIO_159_TYPE, GPO_159_LEVEL+GPIO_159_STICKY+GPIO_159_PULLUP+GPIO_159_PULLDOWN, GPIO_159_SELECT}, + {GPIO_160_SELECT, GPIO_160_TYPE, GPO_160_LEVEL+GPIO_160_STICKY+GPIO_160_PULLUP+GPIO_160_PULLDOWN, GPIO_160_SELECT}, + {GPIO_161_SELECT, GPIO_161_TYPE, GPO_161_LEVEL+GPIO_161_STICKY+GPIO_161_PULLUP+GPIO_161_PULLDOWN, GPIO_161_SELECT}, + {GPIO_162_SELECT, GPIO_162_TYPE, GPO_162_LEVEL+GPIO_162_STICKY+GPIO_162_PULLUP+GPIO_162_PULLDOWN, GPIO_162_SELECT}, + {GPIO_163_SELECT, GPIO_163_TYPE, GPO_163_LEVEL+GPIO_163_STICKY+GPIO_163_PULLUP+GPIO_163_PULLDOWN, GPIO_163_SELECT}, + {GPIO_164_SELECT, GPIO_164_TYPE, GPO_164_LEVEL+GPIO_164_STICKY+GPIO_164_PULLUP+GPIO_164_PULLDOWN, GPIO_164_SELECT}, + {GPIO_165_SELECT, GPIO_165_TYPE, GPO_165_LEVEL+GPIO_165_STICKY+GPIO_165_PULLUP+GPIO_165_PULLDOWN, GPIO_165_SELECT}, + {GPIO_166_SELECT, GPIO_166_TYPE, GPO_166_LEVEL+GPIO_166_STICKY+GPIO_166_PULLUP+GPIO_166_PULLDOWN, GPIO_166_SELECT}, + {GPIO_167_SELECT, GPIO_167_TYPE, GPO_167_LEVEL+GPIO_167_STICKY+GPIO_167_PULLUP+GPIO_167_PULLDOWN, GPIO_167_SELECT}, + {GPIO_168_SELECT, GPIO_168_TYPE, GPO_168_LEVEL+GPIO_168_STICKY+GPIO_168_PULLUP+GPIO_168_PULLDOWN, GPIO_168_SELECT}, + {GPIO_169_SELECT, GPIO_169_TYPE, GPO_169_LEVEL+GPIO_169_STICKY+GPIO_169_PULLUP+GPIO_169_PULLDOWN, GPIO_169_SELECT}, + {GPIO_170_SELECT, GPIO_170_TYPE, GPO_170_LEVEL+GPIO_170_STICKY+GPIO_170_PULLUP+GPIO_170_PULLDOWN, GPIO_170_SELECT}, + {GPIO_171_SELECT, GPIO_171_TYPE, GPO_171_LEVEL+GPIO_171_STICKY+GPIO_171_PULLUP+GPIO_171_PULLDOWN, GPIO_171_SELECT}, + {GPIO_172_SELECT, GPIO_172_TYPE, GPO_172_LEVEL+GPIO_172_STICKY+GPIO_172_PULLUP+GPIO_172_PULLDOWN, GPIO_172_SELECT}, + {GPIO_173_SELECT, GPIO_173_TYPE, GPO_173_LEVEL+GPIO_173_STICKY+GPIO_173_PULLUP+GPIO_173_PULLDOWN, GPIO_173_SELECT}, + {GPIO_174_SELECT, GPIO_174_TYPE, GPO_174_LEVEL+GPIO_174_STICKY+GPIO_174_PULLUP+GPIO_174_PULLDOWN, GPIO_174_SELECT}, + {GPIO_175_SELECT, GPIO_175_TYPE, GPO_175_LEVEL+GPIO_175_STICKY+GPIO_175_PULLUP+GPIO_175_PULLDOWN, GPIO_175_SELECT}, + {GPIO_176_SELECT, GPIO_176_TYPE, GPO_176_LEVEL+GPIO_176_STICKY+GPIO_176_PULLUP+GPIO_176_PULLDOWN, GPIO_176_SELECT}, + {GPIO_177_SELECT, GPIO_177_TYPE, GPO_177_LEVEL+GPIO_177_STICKY+GPIO_177_PULLUP+GPIO_177_PULLDOWN, GPIO_177_SELECT}, + {GPIO_178_SELECT, GPIO_178_TYPE, GPO_178_LEVEL+GPIO_178_STICKY+GPIO_178_PULLUP+GPIO_178_PULLDOWN, GPIO_178_SELECT}, + {GPIO_179_SELECT, GPIO_179_TYPE, GPO_179_LEVEL+GPIO_179_STICKY+GPIO_179_PULLUP+GPIO_179_PULLDOWN, GPIO_179_SELECT}, + {GPIO_180_SELECT, GPIO_180_TYPE, GPO_180_LEVEL+GPIO_180_STICKY+GPIO_180_PULLUP+GPIO_180_PULLDOWN, GPIO_180_SELECT}, + {GPIO_181_SELECT, GPIO_181_TYPE, GPO_181_LEVEL+GPIO_181_STICKY+GPIO_181_PULLUP+GPIO_181_PULLDOWN, GPIO_181_SELECT}, + {GPIO_182_SELECT, GPIO_182_TYPE, GPO_182_LEVEL+GPIO_182_STICKY+GPIO_182_PULLUP+GPIO_182_PULLDOWN, GPIO_182_SELECT}, + {GPIO_183_SELECT, GPIO_183_TYPE, GPO_183_LEVEL+GPIO_183_STICKY+GPIO_183_PULLUP+GPIO_183_PULLDOWN, GPIO_183_SELECT}, + {GPIO_184_SELECT, GPIO_184_TYPE, GPO_184_LEVEL+GPIO_184_STICKY+GPIO_184_PULLUP+GPIO_184_PULLDOWN, GPIO_184_SELECT}, + {GPIO_185_SELECT, GPIO_185_TYPE, GPO_185_LEVEL+GPIO_185_STICKY+GPIO_185_PULLUP+GPIO_185_PULLDOWN, GPIO_185_SELECT}, + {GPIO_186_SELECT, GPIO_186_TYPE, GPO_186_LEVEL+GPIO_186_STICKY+GPIO_186_PULLUP+GPIO_186_PULLDOWN, GPIO_186_SELECT}, + {GPIO_187_SELECT, GPIO_187_TYPE, GPO_187_LEVEL+GPIO_187_STICKY+GPIO_187_PULLUP+GPIO_187_PULLDOWN, GPIO_187_SELECT}, + {GPIO_188_SELECT, GPIO_188_TYPE, GPO_188_LEVEL+GPIO_188_STICKY+GPIO_188_PULLUP+GPIO_188_PULLDOWN, GPIO_188_SELECT}, + {GPIO_189_SELECT, GPIO_189_TYPE, GPO_189_LEVEL+GPIO_189_STICKY+GPIO_189_PULLUP+GPIO_189_PULLDOWN, GPIO_189_SELECT}, + {GPIO_190_SELECT, GPIO_190_TYPE, GPO_190_LEVEL+GPIO_190_STICKY+GPIO_190_PULLUP+GPIO_190_PULLDOWN, GPIO_190_SELECT}, + {GPIO_191_SELECT, GPIO_191_TYPE, GPO_191_LEVEL+GPIO_191_STICKY+GPIO_191_PULLUP+GPIO_191_PULLDOWN, GPIO_191_SELECT}, + {GPIO_192_SELECT, GPIO_192_TYPE, GPO_192_LEVEL+GPIO_192_STICKY+GPIO_192_PULLUP+GPIO_192_PULLDOWN, GPIO_192_SELECT}, + {GPIO_193_SELECT, GPIO_193_TYPE, GPO_193_LEVEL+GPIO_193_STICKY+GPIO_193_PULLUP+GPIO_193_PULLDOWN, GPIO_193_SELECT}, + {GPIO_194_SELECT, GPIO_194_TYPE, GPO_194_LEVEL+GPIO_194_STICKY+GPIO_194_PULLUP+GPIO_194_PULLDOWN, GPIO_194_SELECT}, + {GPIO_195_SELECT, GPIO_195_TYPE, GPO_195_LEVEL+GPIO_195_STICKY+GPIO_195_PULLUP+GPIO_195_PULLDOWN, GPIO_195_SELECT}, + {GPIO_196_SELECT, GPIO_196_TYPE, GPO_196_LEVEL+GPIO_196_STICKY+GPIO_196_PULLUP+GPIO_196_PULLDOWN, GPIO_196_SELECT}, + {GPIO_197_SELECT, GPIO_197_TYPE, GPO_197_LEVEL+GPIO_197_STICKY+GPIO_197_PULLUP+GPIO_197_PULLDOWN, GPIO_197_SELECT}, + {GPIO_198_SELECT, GPIO_198_TYPE, GPO_198_LEVEL+GPIO_198_STICKY+GPIO_198_PULLUP+GPIO_198_PULLDOWN, GPIO_198_SELECT}, + {GPIO_199_SELECT, GPIO_199_TYPE, GPO_199_LEVEL+GPIO_199_STICKY+GPIO_199_PULLUP+GPIO_199_PULLDOWN, GPIO_199_SELECT}, + {GPIO_200_SELECT, GPIO_200_TYPE, GPO_200_LEVEL+GPIO_200_STICKY+GPIO_200_PULLUP+GPIO_200_PULLDOWN, GPIO_200_SELECT}, + {GPIO_201_SELECT, GPIO_201_TYPE, GPO_201_LEVEL+GPIO_201_STICKY+GPIO_201_PULLUP+GPIO_201_PULLDOWN, GPIO_201_SELECT}, + {GPIO_202_SELECT, GPIO_202_TYPE, GPO_202_LEVEL+GPIO_202_STICKY+GPIO_202_PULLUP+GPIO_202_PULLDOWN, GPIO_202_SELECT}, + {GPIO_203_SELECT, GPIO_203_TYPE, GPO_203_LEVEL+GPIO_203_STICKY+GPIO_203_PULLUP+GPIO_203_PULLDOWN, GPIO_203_SELECT}, + {GPIO_204_SELECT, GPIO_204_TYPE, GPO_204_LEVEL+GPIO_204_STICKY+GPIO_204_PULLUP+GPIO_204_PULLDOWN, GPIO_204_SELECT}, + {GPIO_205_SELECT, GPIO_205_TYPE, GPO_205_LEVEL+GPIO_205_STICKY+GPIO_205_PULLUP+GPIO_205_PULLDOWN, GPIO_205_SELECT}, + {GPIO_206_SELECT, GPIO_206_TYPE, GPO_206_LEVEL+GPIO_206_STICKY+GPIO_206_PULLUP+GPIO_206_PULLDOWN, GPIO_206_SELECT}, + {GPIO_207_SELECT, GPIO_207_TYPE, GPO_207_LEVEL+GPIO_207_STICKY+GPIO_207_PULLUP+GPIO_207_PULLDOWN, GPIO_207_SELECT}, + {GPIO_208_SELECT, GPIO_208_TYPE, GPO_208_LEVEL+GPIO_208_STICKY+GPIO_208_PULLUP+GPIO_208_PULLDOWN, GPIO_208_SELECT}, + {GPIO_209_SELECT, GPIO_209_TYPE, GPO_209_LEVEL+GPIO_209_STICKY+GPIO_209_PULLUP+GPIO_209_PULLDOWN, GPIO_209_SELECT}, + {GPIO_210_SELECT, GPIO_210_TYPE, GPO_210_LEVEL+GPIO_210_STICKY+GPIO_210_PULLUP+GPIO_210_PULLDOWN, GPIO_210_SELECT}, + {GPIO_211_SELECT, GPIO_211_TYPE, GPO_211_LEVEL+GPIO_211_STICKY+GPIO_211_PULLUP+GPIO_211_PULLDOWN, GPIO_211_SELECT}, + {GPIO_212_SELECT, GPIO_212_TYPE, GPO_212_LEVEL+GPIO_212_STICKY+GPIO_212_PULLUP+GPIO_212_PULLDOWN, GPIO_212_SELECT}, + {GPIO_213_SELECT, GPIO_213_TYPE, GPO_213_LEVEL+GPIO_213_STICKY+GPIO_213_PULLUP+GPIO_213_PULLDOWN, GPIO_213_SELECT}, + {GPIO_214_SELECT, GPIO_214_TYPE, GPO_214_LEVEL+GPIO_214_STICKY+GPIO_214_PULLUP+GPIO_214_PULLDOWN, GPIO_214_SELECT}, + {GPIO_215_SELECT, GPIO_215_TYPE, GPO_215_LEVEL+GPIO_215_STICKY+GPIO_215_PULLUP+GPIO_215_PULLDOWN, GPIO_215_SELECT}, + {GPIO_216_SELECT, GPIO_216_TYPE, GPO_216_LEVEL+GPIO_216_STICKY+GPIO_216_PULLUP+GPIO_216_PULLDOWN, GPIO_216_SELECT}, + {GPIO_217_SELECT, GPIO_217_TYPE, GPO_217_LEVEL+GPIO_217_STICKY+GPIO_217_PULLUP+GPIO_217_PULLDOWN, GPIO_217_SELECT}, + {GPIO_218_SELECT, GPIO_218_TYPE, GPO_218_LEVEL+GPIO_218_STICKY+GPIO_218_PULLUP+GPIO_218_PULLDOWN, GPIO_218_SELECT}, + {GPIO_219_SELECT, GPIO_219_TYPE, GPO_219_LEVEL+GPIO_219_STICKY+GPIO_219_PULLUP+GPIO_219_PULLDOWN, GPIO_219_SELECT}, + {GPIO_220_SELECT, GPIO_220_TYPE, GPO_220_LEVEL+GPIO_220_STICKY+GPIO_220_PULLUP+GPIO_220_PULLDOWN, GPIO_220_SELECT}, + {GPIO_221_SELECT, GPIO_221_TYPE, GPO_221_LEVEL+GPIO_221_STICKY+GPIO_221_PULLUP+GPIO_221_PULLDOWN, GPIO_221_SELECT}, + {GPIO_222_SELECT, GPIO_222_TYPE, GPO_222_LEVEL+GPIO_222_STICKY+GPIO_222_PULLUP+GPIO_222_PULLDOWN, GPIO_222_SELECT}, + {GPIO_223_SELECT, GPIO_223_TYPE, GPO_223_LEVEL+GPIO_223_STICKY+GPIO_223_PULLUP+GPIO_223_PULLDOWN, GPIO_223_SELECT}, + {GPIO_224_SELECT, GPIO_224_TYPE, GPO_224_LEVEL+GPIO_224_STICKY+GPIO_224_PULLUP+GPIO_224_PULLDOWN, GPIO_224_SELECT}, + {GPIO_225_SELECT, GPIO_225_TYPE, GPO_225_LEVEL+GPIO_225_STICKY+GPIO_225_PULLUP+GPIO_225_PULLDOWN, GPIO_225_SELECT}, + {GPIO_226_SELECT, GPIO_226_TYPE, GPO_226_LEVEL+GPIO_226_STICKY+GPIO_226_PULLUP+GPIO_226_PULLDOWN, GPIO_226_SELECT}, + {GPIO_227_SELECT, GPIO_227_TYPE, GPO_227_LEVEL+GPIO_227_STICKY+GPIO_227_PULLUP+GPIO_227_PULLDOWN, GPIO_227_SELECT}, + {GPIO_228_SELECT, GPIO_228_TYPE, GPO_228_LEVEL+GPIO_228_STICKY+GPIO_228_PULLUP+GPIO_228_PULLDOWN, GPIO_228_SELECT}, + {GPIO_229_SELECT, GPIO_229_TYPE, GPO_229_LEVEL+GPIO_229_STICKY+GPIO_229_PULLUP+GPIO_229_PULLDOWN, GPIO_229_SELECT}, +}; + +typedef enum _GEVENT_COUNT +{ + GEVENT_00=0x60, + GEVENT_01, + GEVENT_02, + GEVENT_03, + GEVENT_04, + GEVENT_05, + GEVENT_06, + GEVENT_07, + GEVENT_08, + GEVENT_09, + GEVENT_10, + GEVENT_11, + GEVENT_12, + GEVENT_13, + GEVENT_14, + GEVENT_15, + GEVENT_16, + GEVENT_17, + GEVENT_18, + GEVENT_19, + GEVENT_20, + GEVENT_21, + GEVENT_22, + GEVENT_23 +} GEVENT_COUNT; + +typedef struct _GEVENT_SETTINGS +{ + u8 EventEnable; // 0: Disable, 1: Enable + u8 SciTrig; // 0: Falling Edge, 1: Rising Edge + u8 SciLevl; // 0: Edge trigger, 1: Level Trigger + u8 SmiSciEn; // 0: Not send SMI, 1: Send SMI + u8 SciS0En; // 0: Disable, 1: Enable + u8 SciMap; // 0000b->1111b + u8 SmiTrig; // 0: Active Low, 1: Active High + u8 SmiControl; // 0: Disable, 1: SMI 2: NMI 3: IRQ13 +} GEVENT_SETTINGS; + +GEVENT_SETTINGS gevent_table[] = +{ + {GEVENT_00_EVENTENABLE, GEVENT_00_SCITRIG, GEVENT_00_SCILEVEL, GEVENT_00_SMISCIEN, GEVENT_00_SCIS0EN, GEVENT_00_SCIMAP, GEVENT_00_SMITRIG, GEVENT_00_SMICONTROL}, + {GEVENT_01_EVENTENABLE, GEVENT_01_SCITRIG, GEVENT_01_SCILEVEL, GEVENT_01_SMISCIEN, GEVENT_01_SCIS0EN, GEVENT_01_SCIMAP, GEVENT_01_SMITRIG, GEVENT_01_SMICONTROL}, + {GEVENT_02_EVENTENABLE, GEVENT_02_SCITRIG, GEVENT_02_SCILEVEL, GEVENT_02_SMISCIEN, GEVENT_02_SCIS0EN, GEVENT_02_SCIMAP, GEVENT_02_SMITRIG, GEVENT_02_SMICONTROL}, + {GEVENT_03_EVENTENABLE, GEVENT_03_SCITRIG, GEVENT_03_SCILEVEL, GEVENT_03_SMISCIEN, GEVENT_03_SCIS0EN, GEVENT_03_SCIMAP, GEVENT_03_SMITRIG, GEVENT_03_SMICONTROL}, + {GEVENT_04_EVENTENABLE, GEVENT_04_SCITRIG, GEVENT_04_SCILEVEL, GEVENT_04_SMISCIEN, GEVENT_04_SCIS0EN, GEVENT_04_SCIMAP, GEVENT_04_SMITRIG, GEVENT_04_SMICONTROL}, + {GEVENT_05_EVENTENABLE, GEVENT_05_SCITRIG, GEVENT_05_SCILEVEL, GEVENT_05_SMISCIEN, GEVENT_05_SCIS0EN, GEVENT_05_SCIMAP, GEVENT_05_SMITRIG, GEVENT_05_SMICONTROL}, + {GEVENT_06_EVENTENABLE, GEVENT_06_SCITRIG, GEVENT_06_SCILEVEL, GEVENT_06_SMISCIEN, GEVENT_06_SCIS0EN, GEVENT_06_SCIMAP, GEVENT_06_SMITRIG, GEVENT_06_SMICONTROL}, + {GEVENT_07_EVENTENABLE, GEVENT_07_SCITRIG, GEVENT_07_SCILEVEL, GEVENT_07_SMISCIEN, GEVENT_07_SCIS0EN, GEVENT_07_SCIMAP, GEVENT_07_SMITRIG, GEVENT_07_SMICONTROL}, + {GEVENT_08_EVENTENABLE, GEVENT_08_SCITRIG, GEVENT_08_SCILEVEL, GEVENT_08_SMISCIEN, GEVENT_08_SCIS0EN, GEVENT_08_SCIMAP, GEVENT_08_SMITRIG, GEVENT_08_SMICONTROL}, + {GEVENT_09_EVENTENABLE, GEVENT_09_SCITRIG, GEVENT_09_SCILEVEL, GEVENT_09_SMISCIEN, GEVENT_09_SCIS0EN, GEVENT_09_SCIMAP, GEVENT_09_SMITRIG, GEVENT_09_SMICONTROL}, + {GEVENT_10_EVENTENABLE, GEVENT_10_SCITRIG, GEVENT_10_SCILEVEL, GEVENT_10_SMISCIEN, GEVENT_10_SCIS0EN, GEVENT_10_SCIMAP, GEVENT_10_SMITRIG, GEVENT_10_SMICONTROL}, + {GEVENT_11_EVENTENABLE, GEVENT_11_SCITRIG, GEVENT_11_SCILEVEL, GEVENT_11_SMISCIEN, GEVENT_11_SCIS0EN, GEVENT_11_SCIMAP, GEVENT_11_SMITRIG, GEVENT_11_SMICONTROL}, + {GEVENT_12_EVENTENABLE, GEVENT_12_SCITRIG, GEVENT_12_SCILEVEL, GEVENT_12_SMISCIEN, GEVENT_12_SCIS0EN, GEVENT_12_SCIMAP, GEVENT_12_SMITRIG, GEVENT_12_SMICONTROL}, + {GEVENT_13_EVENTENABLE, GEVENT_13_SCITRIG, GEVENT_13_SCILEVEL, GEVENT_13_SMISCIEN, GEVENT_13_SCIS0EN, GEVENT_13_SCIMAP, GEVENT_13_SMITRIG, GEVENT_13_SMICONTROL}, + {GEVENT_14_EVENTENABLE, GEVENT_14_SCITRIG, GEVENT_14_SCILEVEL, GEVENT_14_SMISCIEN, GEVENT_14_SCIS0EN, GEVENT_14_SCIMAP, GEVENT_14_SMITRIG, GEVENT_14_SMICONTROL}, + {GEVENT_15_EVENTENABLE, GEVENT_15_SCITRIG, GEVENT_15_SCILEVEL, GEVENT_15_SMISCIEN, GEVENT_15_SCIS0EN, GEVENT_15_SCIMAP, GEVENT_15_SMITRIG, GEVENT_15_SMICONTROL}, + {GEVENT_16_EVENTENABLE, GEVENT_16_SCITRIG, GEVENT_16_SCILEVEL, GEVENT_16_SMISCIEN, GEVENT_16_SCIS0EN, GEVENT_16_SCIMAP, GEVENT_16_SMITRIG, GEVENT_16_SMICONTROL}, + {GEVENT_17_EVENTENABLE, GEVENT_17_SCITRIG, GEVENT_17_SCILEVEL, GEVENT_17_SMISCIEN, GEVENT_17_SCIS0EN, GEVENT_17_SCIMAP, GEVENT_17_SMITRIG, GEVENT_17_SMICONTROL}, + {GEVENT_18_EVENTENABLE, GEVENT_18_SCITRIG, GEVENT_18_SCILEVEL, GEVENT_18_SMISCIEN, GEVENT_18_SCIS0EN, GEVENT_18_SCIMAP, GEVENT_18_SMITRIG, GEVENT_18_SMICONTROL}, + {GEVENT_19_EVENTENABLE, GEVENT_19_SCITRIG, GEVENT_19_SCILEVEL, GEVENT_19_SMISCIEN, GEVENT_19_SCIS0EN, GEVENT_19_SCIMAP, GEVENT_19_SMITRIG, GEVENT_19_SMICONTROL}, + {GEVENT_20_EVENTENABLE, GEVENT_20_SCITRIG, GEVENT_20_SCILEVEL, GEVENT_20_SMISCIEN, GEVENT_20_SCIS0EN, GEVENT_20_SCIMAP, GEVENT_20_SMITRIG, GEVENT_20_SMICONTROL}, + {GEVENT_21_EVENTENABLE, GEVENT_21_SCITRIG, GEVENT_21_SCILEVEL, GEVENT_21_SMISCIEN, GEVENT_21_SCIS0EN, GEVENT_21_SCIMAP, GEVENT_21_SMITRIG, GEVENT_21_SMICONTROL}, + {GEVENT_22_EVENTENABLE, GEVENT_22_SCITRIG, GEVENT_22_SCILEVEL, GEVENT_22_SMISCIEN, GEVENT_22_SCIS0EN, GEVENT_22_SCIMAP, GEVENT_22_SMITRIG, GEVENT_22_SMICONTROL}, + {GEVENT_23_EVENTENABLE, GEVENT_23_SCITRIG, GEVENT_23_SCILEVEL, GEVENT_23_SMISCIEN, GEVENT_23_SCIS0EN, GEVENT_23_SCIMAP, GEVENT_23_SMITRIG, GEVENT_23_SMICONTROL}, +}; + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*--------------------------------------------------------------------------------------- + * L O C A L F U N C T I O N S + *--------------------------------------------------------------------------------------- + */ + +#endif diff --git a/src/mainboard/amd/dinar/irq_tables.c b/src/mainboard/amd/dinar/irq_tables.c new file mode 100644 index 0000000..afd8c67 --- /dev/null +++ b/src/mainboard/amd/dinar/irq_tables.c @@ -0,0 +1,122 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include <console/console.h> +#include <device/pci.h> +#include <string.h> +#include <stdint.h> +#include <arch/pirq_routing.h> + + + +static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, + u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, + u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, + u8 slot, u8 rfu) +{ + pirq_info->bus = bus; + pirq_info->devfn = devfn; + pirq_info->irq[0].link = link0; + pirq_info->irq[0].bitmap = bitmap0; + pirq_info->irq[1].link = link1; + pirq_info->irq[1].bitmap = bitmap1; + pirq_info->irq[2].link = link2; + pirq_info->irq[2].bitmap = bitmap2; + pirq_info->irq[3].link = link3; + pirq_info->irq[3].bitmap = bitmap3; + pirq_info->slot = slot; + pirq_info->rfu = rfu; +} +extern u8 bus_isa; +extern u8 bus_sb700[2]; +extern unsigned long sbdn_sb700; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + + struct irq_routing_table *pirq; + struct irq_info *pirq_info; + u32 slot_num; + u8 *v; + + u8 sum = 0; + int i; + + + get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */ + + + /* Align the table to be 16 byte aligned. */ + addr += 15; + addr &= ~15; + + /* This table must be betweeen 0xf0000 & 0x100000 */ + printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); + + pirq = (void *)(addr); + v = (u8 *) (addr); + + pirq->signature = PIRQ_SIGNATURE; + pirq->version = PIRQ_VERSION; + + pirq->rtr_bus = bus_sb700[0]; + pirq->rtr_devfn = ((sbdn_sb700 + 0x14) << 3) | 4; + + pirq->exclusive_irqs = 0; + + pirq->rtr_vendor = 0x1002; + pirq->rtr_device = 0x4384; + + pirq->miniport_data = 0; + + memset(pirq->rfu, 0, sizeof(pirq->rfu)); + + pirq_info = (void *)(&pirq->checksum + 1); + slot_num = 0; + + + /* pci bridge */ + write_pirq_info(pirq_info, bus_sb700[0], ((sbdn_sb700 + 0x14) << 3) | 4, + 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, + 0); + pirq_info++; + + + + slot_num++; + + + + pirq->size = 32 + 16 * slot_num; + + for (i = 0; i < pirq->size; i++) + sum += v[i]; + + sum = pirq->checksum - sum; + + if (sum != pirq->checksum) { + pirq->checksum = sum; + } + + printk(BIOS_INFO, "write_pirq_routing_table done.\n"); + + return (unsigned long)pirq_info; + +} diff --git a/src/mainboard/amd/dinar/mainboard.c b/src/mainboard/amd/dinar/mainboard.c new file mode 100644 index 0000000..9d10390 --- /dev/null +++ b/src/mainboard/amd/dinar/mainboard.c @@ -0,0 +1,138 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <arch/io.h> +#include <boot/tables.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/mtrr.h> +#include <device/pci_def.h> +#include <NbPlatform.h> +#include "chip.h" + +#define ONE_MB 0x100000 +//#define SMBUS_IO_BASE 0x6000 + +void set_pcie_reset(void *nbconfig); +void set_pcie_dereset(void *nbconfig); + +/** + * TODO + * SB CIMx callback + */ +void set_pcie_reset(void *nbconfig) +{ +} + +/** + * Mainboard specific RD890 CIMx callback + * Release Resets to PCIe Links + * SR5690 PCIE_RESET_GPIO1,2,3,4 to reset pcie + */ +void set_pcie_dereset(void *nbconfig) +{ + //u32 nb_dev = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0); + u32 i; + u32 val; + u32 nb_addr; + + val = 0x00000007UL; + AMD_NB_CONFIG_BLOCK *pConfig = (AMD_NB_CONFIG_BLOCK*)nbconfig; + for (i = 0; i < MAX_NB_COUNT; i ++) { + nb_addr = pConfig->Northbridges[i].NbPciAddress.AddressValue | NB_HTIU_INDEX; + LibNbPciIndexRMW(nb_addr, + NB_HTIU_REGA8, + AccessS3SaveWidth32, + ~val, + val, + &(pConfig->Northbridges[i])); + } +} + +uint64_t uma_memory_base, uma_memory_size; + +/************************************************* + * enable the dedicated function in dinar board. + *************************************************/ +static void dinar_enable(device_t dev) +{ + printk(BIOS_INFO, "Mainboard Dinar Enable. dev=0x%p\n", dev); +#if (CONFIG_GFXUMA == 1) + msr_t msr, msr2; + uint32_t sys_mem; + + /* TOP_MEM: the top of DRAM below 4G */ + msr = rdmsr(TOP_MEM); + printk + (BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n", + __func__, msr.lo, msr.hi); + + /* TOP_MEM2: the top of DRAM above 4G */ + msr2 = rdmsr(TOP_MEM2); + printk (BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n", + __func__, msr2.lo, msr2.hi); + + /* refer to UMA Size Consideration in Family15h BKDG. */ + /* Please reference MemNGetUmaSizeOR () */ + /* + * Total system memory UMASize + * >= 2G 512M + * >=1G 256M + * <1G 64M + */ + sys_mem = msr.lo + 16 * ONE_MB; // Ignore 16MB allocated for C6 when finding UMA size + if ((msr2.hi & 0x0000000F) || (sys_mem >= 2048 * ONE_MB)) { + uma_memory_size = 512 * ONE_MB; + } else if (sys_mem >= 1024 * ONE_MB) { + uma_memory_size = 256 * ONE_MB; + } else { + uma_memory_size = 64 * ONE_MB; + } + uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */ + + printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n", + __func__, uma_memory_size, uma_memory_base); + + /* TODO: TOP_MEM2 */ +#else + uma_memory_size = 256 * ONE_MB; /* 256M recommended UMA */ + uma_memory_base = 768 * ONE_MB; /* 1GB system memory supported */ +#endif + +} + +int add_mainboard_resources(struct lb_memory *mem) +{ + /* UMA is removed from system memory in the northbridge code, but + * in some circumstances we want the memory mentioned as reserved. + */ +#if (CONFIG_GFXUMA == 1) + printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n", + uma_memory_base, uma_memory_size); + lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base, + uma_memory_size); +#endif + return 0; +} +struct chip_operations mainboard_ops = { + CHIP_NAME("AMD DINAR Mainboard") + .enable_dev = dinar_enable, +}; diff --git a/src/mainboard/amd/dinar/mptable.c b/src/mainboard/amd/dinar/mptable.c new file mode 100644 index 0000000..d988eb1 --- /dev/null +++ b/src/mainboard/amd/dinar/mptable.c @@ -0,0 +1,196 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include <console/console.h> +#include <arch/smp/mpspec.h> +#include <device/pci.h> +#include <arch/io.h> +#include <string.h> +#include <stdint.h> +#include <arch/cpu.h> +#include <cpu/x86/lapic.h> + +extern u8 bus_rd890[14]; +extern u8 bus_sb700[2]; +extern u32 bus_type[256]; +extern u32 sbdn_rd890; +extern u32 sbdn_sb700; + + +static void *smp_write_config_table(void *v) +{ + struct mp_config_table *mc; + int bus_isa; + u32 apicid_sb700; + u32 apicid_rd890; + device_t dev; + u32 dword; + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + mptable_init(mc, LAPIC_ADDR); + + smp_write_processors(mc); + get_bus_conf(); + mptable_write_buses(mc, NULL, &bus_isa); + + /* + * AGESA v5 Apply apic enumeration rules + * For systems with >= 16 APICs, put the IO-APICs at 0..n and + * put the local-APICs at m..z + * For systems with < 16 APICs, put the Local-APICs at 0..n and + * put the IO-APICs at (n + 1)..z + */ +#if CONFIG_MAX_CPUS >= 16 + apicid_sb700 = 0x0; +#else + apicid_sb700 = CONFIG_MAX_CPUS + 1 +#endif + apicid_rd890 = apicid_sb700 + 1; + + //bus_sb700[0], TODO: why bus_sb700[0] use same value of bus_rd890[0] assigned by get_pci1234(), instead of 0. + dev = dev_find_slot(0, PCI_DEVFN(sbdn_sb700 + 0x14, 0)); + if (dev) { + /* Set sb700 IOAPIC ID */ + dword = pci_read_config32(dev, 0x74) & 0xfffffff0; + smp_write_ioapic(mc, apicid_sb700, 0x20, dword); + +#ifdef UNUSED_CODE + u8 byte; + /* Initialize interrupt mapping */ + /* aza */ + byte = pci_read_config8(dev, 0x63); + byte &= 0xf8; + byte |= 0; /* 0: INTA, ...., 7: INTH */ + pci_write_config8(dev, 0x63, byte); + /* SATA */ + dword = pci_read_config32(dev, 0xAC); + dword &= ~(7 << 26); + dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */ + /* dword |= 1<<22; PIC and APIC co exists */ + pci_write_config32(dev, 0xAC, dword); +#endif + + /* + * 00:12.0: PROG SATA : INT F + * 00:13.0: INTA USB_0 + * 00:13.1: INTB USB_1 + * 00:13.2: INTC USB_2 + * 00:13.3: INTD USB_3 + * 00:13.4: INTC USB_4 + * 00:13.5: INTD USB2 + * 00:14.1: INTA IDE + * 00:14.2: Prog HDA : INT E + * 00:14.5: INTB ACI + * 00:14.6: INTB MCI + */ + + /* Set RS5650 IOAPIC ID */ + dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + if (dev) { + pci_write_config32(dev, 0xF8, 0x1); + dword = pci_read_config32(dev, 0xFC) & 0xfffffff0; + smp_write_ioapic(mc, apicid_rd890, 0x20, dword); + } + + } + + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ +#define IO_LOCAL_INT(type, intr, apicid, pin) \ + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + + mptable_add_isa_interrupts(mc, bus_isa, apicid_sb700, 0); + + /* PCI interrupts are level triggered, and are + * associated with a specific bus/device/function tuple. + */ +#define PCI_INT(bus, dev, int_sign, pin) \ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_sb700, (pin)) + + /* SMBUS */ + //PCI_INT(0x0, 0x14, 0x0, 0x10); //not generate interrupt, 3Ch hardcoded to 0 + + /* HD Audio */ + PCI_INT(0x0, 0x14, 0x2, 0x10); + + /* USB */ + /* OHCI0, OHCI1 hard-wired to 01h, corresponding to using INTA# */ + /* EHCI hard-wired to 02h, corresponding to using INTB# */ + /* USB1 */ + PCI_INT(0x0, 0x12, 0x0, 0x10); /* OHCI0 Port 0~2 */ + PCI_INT(0x0, 0x12, 0x1, 0x10); /* OHCI1 Port 3~5 */ + PCI_INT(0x0, 0x12, 0x2, 0x11); /* EHCI Port 0~5 */ + + /* USB2 */ + PCI_INT(0x0, 0x13, 0x0, 0x10); /* OHCI0 Port 6~8 */ + PCI_INT(0x0, 0x13, 0x1, 0x10); /* OHCI1 Port 9~11 */ + PCI_INT(0x0, 0x13, 0x2, 0x11); /* EHCI Port 6~11 */ + + /* USB3 EHCI hard-wired to 03h, corresponding to using INTC# */ + PCI_INT(0x0, 0x14, 0x5, 0x12); /* OHCI0 Port 12~13 */ + + /* SATA */ + PCI_INT(0x0, 0x11, 0x0, 0x16); //6, INTG + + /* on board NIC & Slot PCIE. */ + /* configuration B doesnt need dev 5,6,7 */ + /* + * PCI_INT(bus_rd890[0x5], 0x0, 0x0, 0x11); + * PCI_INT(bus_rd890[0x6], 0x0, 0x0, 0x12); + * PCI_INT(bus_rd890[0x7], 0x0, 0x0, 0x13); + */ + + //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((13)<<2)|(0)), apicid_rd890, 28); /* dev d */ + //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_rd890[13], (((0)<<2)|(1)), apicid_rd890, 0); /* card behind dev13 */ + + /* PCI slots */ + /* PCI_SLOT 0. */ + PCI_INT(bus_sb700[1], 0x5, 0x0, 0x14); + PCI_INT(bus_sb700[1], 0x5, 0x1, 0x15); + PCI_INT(bus_sb700[1], 0x5, 0x2, 0x16); + PCI_INT(bus_sb700[1], 0x5, 0x3, 0x17); + + /* PCI_SLOT 1. */ + PCI_INT(bus_sb700[1], 0x6, 0x0, 0x15); + PCI_INT(bus_sb700[1], 0x6, 0x1, 0x16); + PCI_INT(bus_sb700[1], 0x6, 0x2, 0x17); + PCI_INT(bus_sb700[1], 0x6, 0x3, 0x14); + + /* PCI_SLOT 2. */ + PCI_INT(bus_sb700[1], 0x7, 0x0, 0x16); + PCI_INT(bus_sb700[1], 0x7, 0x1, 0x17); + PCI_INT(bus_sb700[1], 0x7, 0x2, 0x14); + PCI_INT(bus_sb700[1], 0x7, 0x3, 0x15); + + + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); + IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); + /* There is no extension information... */ + + /* Compute the checksums */ + return mptable_finalize(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr, 0); + return (unsigned long)smp_write_config_table(v); +} diff --git a/src/mainboard/amd/dinar/platform_cfg.h b/src/mainboard/amd/dinar/platform_cfg.h new file mode 100644 index 0000000..8265f87 --- /dev/null +++ b/src/mainboard/amd/dinar/platform_cfg.h @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _PLATFORM_CFG_H_ +#define _PLATFORM_CFG_H_ + + +/* northbridge customize options */ +/** + * Max number of northbridges in the system + */ +#define MAX_NB_COUNT 1 //TODO: only 1 NB tested + +/** + * Enable check for PCIe endpoint to be ready for PCI enumeration. + * + */ +//#define EPREADY_WORKAROUND_DISABLED + +/** + * Enable IOMMU support. Initialize IOMMU subsystem, generate IVRS ACPI table. + * + */ +#define IOMMU_SUPPORT_DISABLE //TODO: enable it + +/** + * Disable server PCIe hotplug support. + */ + +//#define HOTPLUG_SUPPORT_DISABLED + +/** + * Disable support for device number remapping for PCIe portsserver PCIe hotplug support. + */ + +//#define DEVICE_REMAP_DISABLE + +#endif //_PLATFORM_CFG_H_ diff --git a/src/mainboard/amd/dinar/rd890_cfg.c b/src/mainboard/amd/dinar/rd890_cfg.c new file mode 100644 index 0000000..9518691 --- /dev/null +++ b/src/mainboard/amd/dinar/rd890_cfg.c @@ -0,0 +1,274 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "NbPlatform.h" +#include "rd890_cfg.h" +#include "northbridge/amd/cimx/rd890/chip.h" +#include "nbInitializer.h" +#include <string.h> +#include <arch/ioapic.h> + +#ifndef __PRE_RAM__ +#include <device/device.h> +extern void set_pcie_reset(void *config); +extern void set_pcie_dereset(void *config); + +/** + * Platform dependent configuration at ramstage + */ +static void nb_platform_config(device_t nb_dev, AMD_NB_CONFIG *NbConfigPtr) +{ + u16 i; + PCIE_CONFIG *pPcieConfig = NbConfigPtr->pPcieConfig; + //AMD_NB_CONFIG_BLOCK *ConfigPtr = GET_BLOCK_CONFIG_PTR(NbConfigPtr); + struct northbridge_amd_cimx_rd890_config *rd890_info = NULL; + DEFAULT_PLATFORM_CONFIG(platform_config); + + /* update the platform depentent configuration by devicetree */ + rd890_info = nb_dev->chip_info; + platform_config.PortEnableMap = rd890_info->port_enable; + if (rd890_info->gpp1_configuration == 0) { + platform_config.Gpp1Config = GFX_CONFIG_AAAA; + } else if (rd890_info->gpp1_configuration == 1) { + platform_config.Gpp1Config = GFX_CONFIG_AABB; + } + if (rd890_info->gpp2_configuration == 0) { + platform_config.Gpp2Config = GFX_CONFIG_AAAA; + } else if (rd890_info->gpp2_configuration == 1) { + platform_config.Gpp2Config = GFX_CONFIG_AABB; + } + platform_config.Gpp3aConfig = rd890_info->gpp3a_configuration; + + if (platform_config.Gpp1Config != 0) { + pPcieConfig->CoreConfiguration[0] = platform_config.Gpp1Config; + } + if (platform_config.Gpp2Config != 0) { + pPcieConfig->CoreConfiguration[1] = platform_config.Gpp2Config; + } + if (platform_config.Gpp3aConfig != 0) { + pPcieConfig->CoreConfiguration[2] = platform_config.Gpp3aConfig; + } + + pPcieConfig->TempMmioBaseAddress = (UINT16)(platform_config.TemporaryMmio >> 20); + for (i = 0; i <= MAX_CORE_ID; i++) { + NbConfigPtr->pPcieConfig->CoreSetting[i].SkipConfiguration = OFF; + NbConfigPtr->pPcieConfig->CoreSetting[i].PerformanceMode = OFF; + } + for (i = MIN_PORT_ID; i <= MAX_PORT_ID; i++) { + NbConfigPtr->pPcieConfig->PortConfiguration[i].PortLinkMode = PcieLinkModeGen2; + } + + for (i = MIN_PORT_ID; i <= MAX_PORT_ID; i++) { + if ((platform_config.PortEnableMap & (1 << i)) != 0) { + pPcieConfig->PortConfiguration[i].PortPresent = ON; + if ((platform_config.PortGen1Map & (1 << i)) != 0) { + pPcieConfig->PortConfiguration[i].PortLinkMode = PcieLinkModeGen1; + } + if ((platform_config.PortHotplugMap & (1 << i)) != 0) { + u16 j; + pPcieConfig->PortConfiguration[j].PortHotplug = ON; /* Enable Hotplug */ + /* Set Hotplug descriptor info */ + for (j = 0; j < 8; j++) { + u32 PortDescriptor; + PortDescriptor = platform_config.PortHotplugDescriptors[j]; + if ((PortDescriptor & 0xF) == j) { + pPcieConfig->ExtPortConfiguration[j].PortHotplugDevMap = (PortDescriptor >> 4) & 3; + pPcieConfig->ExtPortConfiguration[j].PortHotplugByteMap = (PortDescriptor >> 6) & 1; + break; + } + } + } + } + } +} +#endif // __PRE_RAM__ + +/** + * @brief Entry point of Northbridge CIMx callout/CallBack + * + * prototype AGESA_STATUS (*CALLOUT_ENTRY) (UINT32 Param1, UINTN Param2, VOID* ConfigPtr); + * + * @param[in] u32 func Northbridge CIMx CallBackId + * @param[in] u32 data Northbridge Input Data. + * @param[in] AMD_NB_CONFIG *config Northbridge configuration structure pointer. + * + */ +static u32 rd890_callout_entry(u32 func, u32 data, void *config) +{ + u32 ret = 0; +#ifndef __PRE_RAM__ + device_t nb_dev = (device_t)data; +#endif + AMD_NB_CONFIG *nbConfigPtr = (AMD_NB_CONFIG*)config; + + switch (func) { + case PHCB_AmdPortTrainingCompleted: + break; + + case PHCB_AmdPortResetDeassert: +#ifndef __PRE_RAM__ + set_pcie_dereset(config); +#endif + break; + + case PHCB_AmdPortResetAssert: +#ifndef __PRE_RAM__ + set_pcie_reset(config); +#endif + break; + + case PHCB_AmdPortResetSupported: + break; + case PHCB_AmdGeneratePciReset: + break; + case PHCB_AmdGetExclusionTable: + break; + case PHCB_AmdAllocateBuffer: + break; + case PHCB_AmdUpdateApicInterruptMapping: + break; + case PHCB_AmdFreeBuffer: + break; + case PHCB_AmdLocateBuffer: + break; + case PHCB_AmdReportEvent: + break; + case PHCB_AmdPcieAsmpInfo: + break; + + case CB_AmdSetNbPorConfig: + break; + case CB_AmdSetHtConfig: + /*TODO: different HT path and deempasis for each NB */ + nbConfigPtr->pHtConfig->NbTransmitterDeemphasis = DEFAULT_HT_DEEMPASIES; + + break; + case CB_AmdSetPcieEarlyConfig: +#ifndef __PRE_RAM__ + nb_platform_config(nb_dev, nbConfigPtr); +#endif + break; + + case CB_AmdSetEarlyPostConfig: + break; + + case CB_AmdSetMidPostConfig: + nbConfigPtr->pNbConfig->IoApicBaseAddress = RD890_IOAPIC_ADDR; +#ifndef IOMMU_SUPPORT_DISABLE //TODO enable iommu + /* SBIOS must alloc 16K memory for IOMMU MMIO */ + UINT32 MmcfgBarAddress; //using default IOmmuBaseAddress + LibNbPciRead(nbConfigPtr->NbPciAddress.AddressValue | 0x1C, + AccessWidth32, + &MmcfgBarAddress, + nbConfigPtr); + MmcfgBarAddress &= ~0xf; + if (MmcfgBarAddress != 0) { + nbConfigPtr->IommuBaseAddress = MmcfgBarAddress; + } + nbConfigPtr->IommuBaseAddress = 0; //disable iommu +#endif + break; + + case CB_AmdSetLatePostConfig: + break; + + case CB_AmdSetRecoveryConfig: + break; + } + + return ret; +} + + +/** + * @brief North Bridge CIMx configuration + * + * should be called before exeucte CIMx function. + * this function will be called in romstage and ramstage. + */ +void rd890_cimx_config(AMD_NB_CONFIG_BLOCK *pConfig, NB_CONFIG *nbConfig, HT_CONFIG *htConfig, PCIE_CONFIG *pcieConfig) +{ + u16 i = 0; + PCI_ADDR PciAddress; + u32 val, sbNode, sbLink; + + if (!pConfig) { + return; + } + + memset(pConfig, 0, sizeof(AMD_NB_CONFIG_BLOCK)); + for (i = 0; i < MAX_NB_COUNT; i++) { + pConfig->Northbridges[i].pNbConfig = &nbConfig[i]; + pConfig->Northbridges[i].pHtConfig = &htConfig[i]; + pConfig->Northbridges[i].pPcieConfig = &pcieConfig[i]; + pConfig->Northbridges[i].ConfigPtr = &pConfig; + } + + /* Initialize all NB structures */ + AmdInitializer(pConfig); + + pConfig->NumberOfNorthbridges = MAX_NB_COUNT - 1; /* Support limited to primary NB only located at 0:0:0 */ + //pConfig->StandardHeader.ImageBasePtr = CIMX_B2_IMAGE_BASE_ADDRESS; + pConfig->StandardHeader.PcieBasePtr = (VOID *)PCIEX_BASE_ADDRESS; + pConfig->StandardHeader.CalloutPtr = &rd890_callout_entry; + + /* + * PCI Address to Access NB. Depends on HT topology and configuration for multi NB platform. + * Always 0:0:0 on single NB platform. + */ + pConfig->Northbridges[0].NbPciAddress.AddressValue = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0); + + /* Set HT path to NB by SbNode and SbLink */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x60); + LibNbPciRead(PciAddress.AddressValue, AccessWidth32, &val, &(pConfig->Northbridges[0])); + sbNode = (val >> 8) & 0x07; + PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x64); + LibNbPciRead(PciAddress.AddressValue, AccessWidth32, &val, &(pConfig->Northbridges[0])); + sbLink = (val >> 8) & 0x07; //assum ganged + pConfig->Northbridges[0].NbHtPath.NodeID = sbNode; + pConfig->Northbridges[0].NbHtPath.LinkID = sbLink; + //TODO: other NBs + +#ifndef __PRE_RAM__ + /* If temporrary MMIO enable set up CPU MMIO */ + for (i = 0; i <= pConfig->NumberOfNorthbridges; i++) { + UINT32 MmioBase; + UINT32 LinkId; + UINT32 SubLinkId; + MmioBase = pConfig->Northbridges[i].pPcieConfig->TempMmioBaseAddress; + if (MmioBase != 0) { + LinkId = pConfig->Northbridges[i].NbHtPath.LinkID & 0xf; + SubLinkId = ((pConfig->Northbridges[i].NbHtPath.LinkID & 0xF0) == 0x20) ? 1 : 0; + /* Set Limit */ + LibNbPciRMW(MAKE_SBDFO (0, 0, 0x18, 0x1, (i * 4) + 0x84), + AccessWidth32, + 0x0, + ((MmioBase << 12) + 0xF00) | (LinkId << 4) | (SubLinkId << 6), + &(pConfig->Northbridges[i])); + /* Set Base */ + LibNbPciRMW(MAKE_SBDFO (0, 0, 0x18, 0x1, (i * 4) + 0x80), + AccessWidth32, + 0x0, + (MmioBase << 12) | 0x3, + &(pConfig->Northbridges[i])); + } + } +#endif +} + diff --git a/src/mainboard/amd/dinar/rd890_cfg.h b/src/mainboard/amd/dinar/rd890_cfg.h new file mode 100644 index 0000000..a4f4e1a --- /dev/null +++ b/src/mainboard/amd/dinar/rd890_cfg.h @@ -0,0 +1,175 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _RD890_CFG_H_ +#define _RD890_CFG_H_ + +#include "NbPlatform.h" + +#define RD890_IOAPIC_ADDR 0xC8000000 +/* platform dependent configuration default value */ + +/** + * Path from CPU to NB + * [0..7] - Node (0..8) + * [8..11] - Link (0..3) + * [12..15] - Sublink (1..2), If NB connected to full link than Sublink should be set to 0. + */ +#ifndef DEFAULT_HT_PATH +#if CONFIG_CPU_AMD_AGESA_FAMILY10 == 1 +#define DEFAULT_HT_PATH {0x0, 0x3} +#endif +#if CONFIG_CPU_AMD_AGESA_FAMILY15 == 1 +#define DEFAULT_HT_PATH {0x0, 0x1} +#endif +#endif + +/** + * Bitmap of enabled ports on NB #0/1/2/3 + * Bit[0] - Reserved + * Bit[1] - Reserved + * Bit[2] - Enable PCIe port 2 + * Bit[3] - Enable PCIe port 3 + * Bit[4] - Enable PCIe port 4 + * Bit[5] - Enable PCIe port 5 + * Bit[6] - Enable PCIe port 2 + * Bit[7] - Enable PCIe port 7 + * Bit[8] - Reserved + * Bit[9] - Enable PCIe port 9 + * Bit[10]- Enable PCIe port 10 + * Bit[11]- Enable PCIe port 11 + * Bit[12]- Enable PCIe port 12 + * Bit[13]- Enable PCIe port 13 + * Example: + * port_enable = 0x14 + * Port 2 and 4 enabled for training/initialization + */ +#ifndef DEFAULT_PORT_ENABLE_MAP +#define DEFAULT_PORT_ENABLE_MAP 0x0014 +#endif + +/** + * Bitmap of ports that have slot or onboard device connected. + * Example force PCIe Gen1 supporton port 2 and 4 (DEFAULT_PORT_ENABLE_MAP = BIT2 | BIT4) + * #define DEFAULT_PORT_FORCE_GEN1 0x604 + */ +#ifndef DEFAULT_PORT_FORCE_GEN1 +#define DEFAULT_PORT_FORCE_GEN1 0x0 +#endif + +/** + * Bitmap of ports that have server hotplug support + */ +#ifndef DEFAULT_HOTPLUG_SUPPORT +#define DEFAULT_HOTPLUG_SUPPORT 0x0 +#endif + +#ifndef DEFAULT_HOTPLUG_DESCRIPTOR +#define DEFAULT_HOTPLUG_DESCRIPTOR {0, 0, 0, 0, 0, 0, 0, 0} +#endif + +#ifndef DEFAULT_TEMPMMIO_BASE_ADDRESS +#define DEFAULT_TEMPMMIO_BASE_ADDRESS 0xD0000000 +#endif + +/** + * Default GPP1 core configuraton on NB #0/1/2/3. + * 2 x8 slot, GFX_CONFIG_AABB + * 1 x16 slot, GFX_CONFIG_AAAA + */ +#ifndef DEFAULT_GPP1_CONFIG +#define DEFAULT_GPP1_CONFIG GFX_CONFIG_AABB +#endif + +/** + * Default GPP2 core configuraton on NB #0/1/2/3. + * 2 x8 slot, GFX_CONFIG_AABB + * 1 x16 slot, GFX_CONFIG_AAAA + */ +#ifndef DEFAULT_GPP2_CONFIG +#define DEFAULT_GPP2_CONFIG GFX_CONFIG_AABB +#endif + +/** + * Default GPP3a core configuraton on NB #0/1/2/3. + * 4:2:0:0:0:0 - GPP_CONFIG_GPP420000, 0x1 + * 4:1:1:0:0:0 - GPP_CONFIG_GPP411000, 0x2 + * 2:2:2:0:0:0 - GPP_CONFIG_GPP222000, 0x3 + * 2:2:1:1:0:0 - GPP_CONFIG_GPP221100, 0x4 + * 2:1:1:1:1:0 - GPP_CONFIG_GPP211110, 0x5 + * 1:1:1:1:1:1 - GPP_CONFIG_GPP111111, 0x6 + */ +#ifndef DEFAULT_GPP3A_CONFIG +#define DEFAULT_GPP3A_CONFIG GPP_CONFIG_GPP111111 +#endif + + +/** + * Default HT Transmitter de-emphasis setting + */ +#ifndef DEFAULT_HT_DEEMPASIES +#define DEFAULT_HT_DEEMPASIES 0x3 +#endif + +/** + * Default APIC nterrupt base for IOAPIC + */ +#ifndef DEFAULT_APIC_INTERRUPT_BASE +#define DEFAULT_APIC_INTERRUPT_BASE 24 +#endif + + +#define DEFAULT_PLATFORM_CONFIG(name) \ + NB_PLATFORM_CONFIG name = { \ + DEFAULT_PORT_ENABLE_MAP, \ + DEFAULT_PORT_FORCE_GEN1, \ + DEFAULT_HOTPLUG_SUPPORT, \ + DEFAULT_HOTPLUG_DESCRIPTOR, \ + DEFAULT_TEMPMMIO_BASE_ADDRESS, \ + DEFAULT_GPP1_CONFIG, \ + DEFAULT_GPP2_CONFIG, \ + DEFAULT_GPP3A_CONFIG, \ + DEFAULT_HT_DEEMPASIES, \ + /*DEFAULT_HT_PATH,*/ \ + DEFAULT_APIC_INTERRUPT_BASE, \ + } + +/** + * Platform configuration + */ +typedef struct { + UINT16 PortEnableMap; ///< Bitmap of enabled ports + UINT16 PortGen1Map; ///< Bitmap of ports to disable Gen2 + UINT16 PortHotplugMap; ///< Bitmap of ports support hotplug + UINT8 PortHotplugDescriptors[8];///< Ports Hotplug descriptors + UINT32 TemporaryMmio; ///< Temporary MMIO + UINT32 Gpp1Config; ///< Default PCIe GFX core configuration + UINT32 Gpp2Config; ///< Default PCIe GPP2 core configuration + UINT32 Gpp3aConfig; ///< Default PCIe GPP3a core configuration + UINT8 NbTransmitterDeemphasis; ///< HT transmitter de-emphasis level + // HT_PATH NbHtPath; ///< HT path to NB + UINT8 GlobalApicInterruptBase; ///< Global APIC interrupt base that is used in MADT table for IO APIC. +} NB_PLATFORM_CONFIG; + +/** + * Bridge CIMx configuration + */ +void rd890_cimx_config(AMD_NB_CONFIG_BLOCK *pConfig, NB_CONFIG *nbConfig, HT_CONFIG *htConfig, PCIE_CONFIG *pcieConfig); + +#endif //_RD890_CFG_H_ diff --git a/src/mainboard/amd/dinar/reset.c b/src/mainboard/amd/dinar/reset.c new file mode 100644 index 0000000..4cc1efd --- /dev/null +++ b/src/mainboard/amd/dinar/reset.c @@ -0,0 +1,66 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include <reset.h> +#include <arch/io.h> /*inb, outb*/ +#include <arch/romcc_io.h> /*pci_read_config32, device_t, PCI_DEV*/ + +#define HT_INIT_CONTROL 0x6C +#define HTIC_BIOSR_Detect (1<<5) + +#if CONFIG_MAX_PHYSICAL_CPUS > 32 +#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) +#else +#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) +#endif + +static inline void set_bios_reset(void) +{ + u32 nodes; + u32 htic; + device_t dev; + int i; + + nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; + for(i = 0; i < nodes; i++) { + dev = NODE_PCI(i, 0); + htic = pci_read_config32(dev, HT_INIT_CONTROL); + htic &= ~HTIC_BIOSR_Detect; + pci_write_config32(dev, HT_INIT_CONTROL, htic); + } +} + +void hard_reset(void) +{ + set_bios_reset(); + /* Try rebooting through port 0xcf9 */ + /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ + outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); + outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); +} + +//SbReset(); +void soft_reset(void) +{ + set_bios_reset(); + /* link reset */ + outb(0x06, 0x0cf9); +} + diff --git a/src/mainboard/amd/dinar/romstage.c b/src/mainboard/amd/dinar/romstage.c new file mode 100644 index 0000000..39d8b45 --- /dev/null +++ b/src/mainboard/amd/dinar/romstage.c @@ -0,0 +1,157 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <string.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <arch/io.h> +#include <arch/stages.h> +#include <device/pnp_def.h> +#include <arch/romcc_io.h> +#include <cpu/x86/lapic.h> +#include <console/console.h> +#include <console/loglevel.h> +#include "cpu/x86/bist.h" +#include "superio/smsc/sch4037/sch4037_early_init.c" +#include "superio/smsc/sio1036/sio1036_early_init.c" +#include "cpu/x86/lapic/boot_cpu.c" +#include "pc80/i8254.c" +#include "pc80/i8259.c" +#include "nb_cimx.h" +#include "sb_cimx.h" +#include "Platform.h" +#include <arch/cpu.h> + +#define SERIAL_DEV PNP_DEV(CONFIG_SIO_PORT, SMSCSUPERIO_SP1) + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); +u32 agesawrapper_amdinitmmio (void); +u32 agesawrapper_amdinitreset (void); +u32 agesawrapper_amdinitearly (void); +u32 agesawrapper_amdinitenv (void); +u32 agesawrapper_amdinitlate (void); +u32 agesawrapper_amdinitpost (void); +u32 agesawrapper_amdinitmid (void); + + + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + u32 val; + + if (!cpu_init_detectedx && boot_cpu()) { + + post_code(0x30); + + sch4037_early_init (CONFIG_SIO_PORT); + + /* Detect SMSC SIO1036 LPC Debug Card status */ + if (detect_sio1036_chip(0x4E)) { + /* Found SMSC SIO1036 LPC Debug Card */ + sio1036_early_init(0x4E); + } + + post_code(0x31); + uart_init(); + console_init(); + + /* + * SR5650/5670/5690 RD890 chipset, read pci config space hang at POR, + * Disable all Pcie Bridges to work around It. + */ + sr56x0_rd890_disable_pcie_bridge(); + + } + + post_code(0x32); + val = agesawrapper_amdinitmmio(); + if(val) { + printk(BIOS_DEBUG, "agesawrapper_amdinitmmio failed: %x \n", val); + } + printk(BIOS_DEBUG, "Got past agesawrapper_amdinitmmio\n"); + + /* Halt if there was a built in self test failure */ + post_code(0x33); + report_bist_failure(bist); + + // Load MPB + val = cpuid_eax(1); + printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); + + if(boot_cpu()) { + post_code(0x34); + sb_Poweron_Init(); + } + + post_code(0x35); + val = agesawrapper_amdinitreset(); + if(val) { + printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val); + } + printk(BIOS_DEBUG, "Got past agesawrapper_amdinitreset\n"); + + post_code(0x36); + val = agesawrapper_amdinitearly (); + if(val) { + printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val); + } + printk(BIOS_DEBUG, "Got past agesawrapper_amdinitearly\n"); + + post_code(0x37); + nb_Poweron_Init(); + post_code(0x38); + nb_Ht_Init(); + + + post_code(0x39); + val = agesawrapper_amdinitpost (); + if(val) { + printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val); + } + printk(BIOS_DEBUG, "Got past agesawrapper_amdinitpost\n"); + + post_code(0x40); + val = agesawrapper_amdinitenv (); + if(val) { + printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", val); + } + printk(BIOS_DEBUG, "Got past agesawrapper_amdinitenv\n"); + + + /* Initialize i8259 pic */ + post_code(0x41); + setup_i8259 (); + + /* Initialize i8254 timers */ + post_code(0x42); + setup_i8254 (); + + post_code(0x43); + print_debug("Disabling cache as ram "); + disable_cache_as_ram(); + print_debug("done\n"); + + post_code(0x44); + copy_and_run(0); + + post_code(0x45); // Should never see this post code. +} + diff --git a/src/mainboard/amd/dinar/sb700_cfg.c b/src/mainboard/amd/dinar/sb700_cfg.c new file mode 100644 index 0000000..36a453b --- /dev/null +++ b/src/mainboard/amd/dinar/sb700_cfg.c @@ -0,0 +1,142 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include <string.h> +#include <console/console.h> /* printk */ +#include "Platform.h" +#include "sb700_cfg.h" + + +/** + * @brief South Bridge CIMx configuration + * + * should be called before exeucte CIMx function. + * this function will be called in romstage and ramstage. + */ +void sb700_cimx_config(AMDSBCFG *sb_config) +{ + if (!sb_config) { + printk(BIOS_DEBUG, "SB700 - Cfg.c - sb700_cimx_config - No sb_config.\n"); + return; + } + printk(BIOS_DEBUG, "SB700 - Cfg.c - sb700_cimx_config - Start.\n"); + memset(sb_config, 0, sizeof(AMDSBCFG)); + + /* SB_POWERON_INIT */ + sb_config->StdHeader.Func = SB_POWERON_INIT; + + /* header */ + sb_config->StdHeader.pPcieBase = PCIEX_BASE_ADDRESS; + + /* static Build Parameters */ + sb_config->BuildParameters.BiosSize = BIOS_SIZE; + sb_config->BuildParameters.LegacyFree = LEGACY_FREE; + sb_config->BuildParameters.EcKbd = 0; + sb_config->BuildParameters.EcChannel0 = 0; + sb_config->BuildParameters.Smbus0BaseAddress = SMBUS0_BASE_ADDRESS; + sb_config->BuildParameters.Smbus1BaseAddress = SMBUS1_BASE_ADDRESS; + sb_config->BuildParameters.SioPmeBaseAddress = SIO_PME_BASE_ADDRESS; + sb_config->BuildParameters.WatchDogTimerBase = WATCHDOG_TIMER_BASE_ADDRESS; + sb_config->BuildParameters.SpiRomBaseAddress = SPI_BASE_ADDRESS; + + sb_config->BuildParameters.AcpiPm1EvtBlkAddr = PM1_EVT_BLK_ADDRESS; + sb_config->BuildParameters.AcpiPm1CntBlkAddr = PM1_CNT_BLK_ADDRESS; + sb_config->BuildParameters.AcpiPmTmrBlkAddr = PM1_TMR_BLK_ADDRESS; + sb_config->BuildParameters.CpuControlBlkAddr = CPU_CNT_BLK_ADDRESS; + sb_config->BuildParameters.AcpiGpe0BlkAddr = GPE0_BLK_ADDRESS; + sb_config->BuildParameters.SmiCmdPortAddr = SMI_CMD_PORT; + sb_config->BuildParameters.AcpiPmaCntBlkAddr = ACPI_PMA_CNT_BLK_ADDRESS; + + sb_config->BuildParameters.SataIDESsid = SATA_IDE_MODE_SSID; + sb_config->BuildParameters.SataRAIDSsid = SATA_RAID_MODE_SSID; + sb_config->BuildParameters.SataRAID5Ssid = SATA_RAID5_MODE_SSID; + sb_config->BuildParameters.SataAHCISsid = SATA_AHCI_SSID; + sb_config->BuildParameters.Ohci0Ssid = OHCI0_SSID; + sb_config->BuildParameters.Ohci1Ssid = OHCI1_SSID; + sb_config->BuildParameters.Ohci2Ssid = OHCI2_SSID; + sb_config->BuildParameters.Ohci3Ssid = OHCI3_SSID; + sb_config->BuildParameters.Ohci4Ssid = OHCI4_SSID; + sb_config->BuildParameters.Ehci0Ssid = EHCI0_SSID; + sb_config->BuildParameters.Ehci1Ssid = EHCI1_SSID; + sb_config->BuildParameters.SmbusSsid = SMBUS_SSID; + sb_config->BuildParameters.IdeSsid = IDE_SSID; + sb_config->BuildParameters.AzaliaSsid = AZALIA_SSID; + sb_config->BuildParameters.LpcSsid = LPC_SSID; + + sb_config->BuildParameters.HpetBase = HPET_BASE_ADDRESS; + + /* General */ + sb_config->Spi33Mhz = 1; + sb_config->SpreadSpectrum = 0; + sb_config->PciClk5 = 0; + sb_config->PciClks = 0x1F; + sb_config->ResetCpuOnSyncFlood = 1; // Do not reset CPU on sync flood + sb_config->TimerClockSource = 2; // Auto + sb_config->S3Resume = 0; + sb_config->RebootRequired = 0; + + /* HPET */ + sb_config->HpetTimer = HPET_TIMER; + + /* USB */ + sb_config->UsbIntClock = 0; // Use external clock + sb_config->Usb1Ohci0 = 1; //0:disable 1:enable Bus 0 Dev 18 Func0 + sb_config->Usb1Ohci1 = 1; //0:disable 1:enable Bus 0 Dev 18 Func1 + sb_config->Usb1Ehci = 1; //0:disable 1:enable Bus 0 Dev 18 Func2 + sb_config->Usb2Ohci0 = 1; //0:disable 1:enable Bus 0 Dev 19 Func0 + sb_config->Usb2Ohci1 = 1; //0:disable 1:enable Bus 0 Dev 19 Func1 + sb_config->Usb2Ehci = 1; //0:disable 1:enable Bus 0 Dev 19 Func2 + sb_config->Usb3Ohci = 1; //0:disable 1:enable Bus 0 Dev 20 Func5 + sb_config->UsbOhciLegacyEmulation = 1; //0:Enable 1:Disable + + sb_config->AcpiS1Supported = 1; + + /* SATA */ + sb_config->SataController = 1; + sb_config->SataClass = CONFIG_SATA_CONTROLLER_MODE; //0 native, 1 raid, 2 ahci + sb_config->SataSmbus = 0; + sb_config->SataAggrLinkPmCap = 1; + sb_config->SataPortMultCap = 1; + sb_config->SataClkAutoOff = 1; + sb_config->SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary, 1 -IDE as secondary. + //TODO: set to secondary not take effect. + sb_config->SataIdeCombinedMode = 0; //1 IDE controlor exposed and combined mode enabled, 0 disabled + sb_config->SataEspPort = 0; + sb_config->SataClkAutoOffAhciMode = 1; + sb_config->SataHpcpButNonESP = 0; + sb_config->SataHideUnusedPort = 0; + + /* Azalia HDA */ + sb_config->AzaliaController = AZALIA_CONTROLLER; + sb_config->AzaliaPinCfg = AZALIA_PIN_CONFIG; + sb_config->AzaliaSdin0 = AZALIA_SDIN_PIN; + sb_config->pAzaliaOemCodecTablePtr = NULL; + +#ifndef __PRE_RAM__ + /* ramstage cimx config here */ + if (!sb_config->StdHeader.pCallBack) { + sb_config->StdHeader.pCallBack = sb700_callout_entry; + } + + //sb_config-> +#endif //!__PRE_RAM__ + printk(BIOS_DEBUG, "SB700 - Cfg.c - sb700_cimx_config - End.\n"); +} + diff --git a/src/mainboard/amd/dinar/sb700_cfg.h b/src/mainboard/amd/dinar/sb700_cfg.h new file mode 100644 index 0000000..b405f0e --- /dev/null +++ b/src/mainboard/amd/dinar/sb700_cfg.h @@ -0,0 +1,237 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#ifndef _SB700_CFG_H_ +#define _SB700_CFG_H_ + +#include <stdint.h> + + +/** + * @def BIOS_SIZE_1M + * @def BIOS_SIZE_2M + * @def BIOS_SIZE_4M + * @def BIOS_SIZE_8M + */ +#define BIOS_SIZE_1M 0 +#define BIOS_SIZE_2M 1 +#define BIOS_SIZE_4M 3 +#define BIOS_SIZE_8M 7 + +/* In SB700, default ROM size is 1M Bytes, if your platform ROM + * bigger than 1M you have to set the ROM size outside CIMx module and + * before AGESA module get call. + */ +#ifndef BIOS_SIZE +#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1 +#define BIOS_SIZE BIOS_SIZE_1M +#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1 +#define BIOS_SIZE BIOS_SIZE_2M +#elif CONFIG_COREBOOT_ROMSIZE_KB_4096 == 1 +#define BIOS_SIZE BIOS_SIZE_4M +#elif CONFIG_COREBOOT_ROMSIZE_KB_8192 == 1 +#define BIOS_SIZE BIOS_SIZE_8M +#endif +#endif + +/** + * @def SPREAD_SPECTRUM + * @brief + * 0 - Disable Spread Spectrum function + * 1 - Enable Spread Spectrum function + */ +#define SPREAD_SPECTRUM 0 + +/** + * @def SB_HPET_TIMER + * @breif + * 0 - Disable hpet + * 1 - Enable hpet + */ +#define HPET_TIMER 1 + +/** + * @def USB_CONFIG + * @brief bit[0-6] used to control USB + * 0 - Disable + * 1 - Enable + * Usb Ohci1 Contoller (Bus 0 Dev 18 Func0) is define at BIT0 + * Usb Ehci1 Contoller (Bus 0 Dev 18 Func2) is define at BIT1 + * Usb Ohci2 Contoller (Bus 0 Dev 19 Func0) is define at BIT2 + * Usb Ehci2 Contoller (Bus 0 Dev 19 Func2) is define at BIT3 + * Usb Ohci3 Contoller (Bus 0 Dev 22 Func0) is define at BIT4 + * Usb Ehci3 Contoller (Bus 0 Dev 22 Func2) is define at BIT5 + * Usb Ohci4 Contoller (Bus 0 Dev 20 Func5) is define at BIT6 + */ +#define USB_CINFIG 0x7F + +/** + * @def PCI_CLOCK_CTRL + * @breif bit[0-4] used for PCI Slots Clock Control, + * 0 - disable + * 1 - enable + * PCI SLOT 0 define at BIT0 + * PCI SLOT 1 define at BIT1 + * PCI SLOT 2 define at BIT2 + * PCI SLOT 3 define at BIT3 + * PCI SLOT 4 define at BIT4 + */ +#define PCI_CLOCK_CTRL 0x1F + +/** + * @def SATA_CONTROLLER + * @breif INCHIP Sata Controller + */ +#ifndef SATA_CONTROLLER +#define SATA_CONTROLLER 1 +#endif + +/** + * @def SATA_MODE + * @breif INCHIP Sata Controller Mode + * NOTE: DO NOT ALLOW SATA & IDE use same mode + */ +#ifndef SATA_MODE +#define SATA_MODE NATIVE_IDE_MODE +#endif + +/** + * @breif INCHIP Sata IDE Controller Mode + */ +#define IDE_LEGACY_MODE 0 +#define IDE_NATIVE_MODE 1 + +/** + * @def SATA_IDE_MODE + * @breif INCHIP Sata IDE Controller Mode + * NOTE: DO NOT ALLOW SATA & IDE use same mode + */ +#ifndef SATA_IDE_MODE +#define SATA_IDE_MODE IDE_LEGACY_MODE +#endif + +/** + * @def EXTERNAL_CLOCK + * @brief 00/10: Reference clock from crystal oscillator via + * PAD_XTALI and PAD_XTALO + * + * @def INTERNAL_CLOCK + * @brief 01/11: Reference clock from internal clock through + * CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL + */ +#define EXTERNAL_CLOCK 0x00 +#define INTERNAL_CLOCK 0x01 + +#define SATA_CLOCK_SOURCE EXTERNAL_CLOCK + +/** + * @def SATA_PORT_MULT_CAP_RESERVED + * @brief 1 ON, 0 0FF + */ +#define SATA_PORT_MULT_CAP_RESERVED 1 + + +/** + * @def AZALIA_AUTO + * @brief Detect Azalia controller automatically. + * + * @def AZALIA_DISABLE + * @brief Disable Azalia controller. + + * @def AZALIA_ENABLE + * @brief Enable Azalia controller. + */ +#define AZALIA_AUTO 0 +#define AZALIA_DISABLE 1 +#define AZALIA_ENABLE 2 + +/** + * @breif INCHIP HDA controller + */ +#ifndef AZALIA_CONTROLLER +#define AZALIA_CONTROLLER AZALIA_AUTO +#endif + +/** + * @def AZALIA_PIN_CONFIG + * @brief + * 0 - disable + * 1 - enable + */ +#ifndef AZALIA_PIN_CONFIG +#define AZALIA_PIN_CONFIG 1 +#endif + +/** + * @def AZALIA_SDIN_PIN + * @brief + * SDIN0 is define at BIT0 & BIT1 + * 00 - GPIO PIN + * 01 - Reserved + * 10 - As a Azalia SDIN pin + * SDIN1 is define at BIT2 & BIT3 + * SDIN2 is define at BIT4 & BIT5 + * SDIN3 is define at BIT6 & BIT7 + */ +#ifndef AZALIA_SDIN_PIN +//#define AZALIA_SDIN_PIN 0xAA +#define AZALIA_SDIN_PIN 0x2A +#endif + +/** + * @def GPP_CONTROLLER + */ +#ifndef GPP_CONTROLLER +#define GPP_CONTROLLER 1 +#endif + +/** + * @def GPP_CFGMODE + * @brief GPP Link Configuration + * four possible configuration: + * GPP_CFGMODE_X4000 + * GPP_CFGMODE_X2200 + * GPP_CFGMODE_X2110 + * GPP_CFGMODE_X1111 + */ +#ifndef GPP_CFGMODE +#define GPP_CFGMODE GPP_CFGMODE_X1111 +#endif + + +/** + * @brief South Bridge CIMx configuration + * + */ +void sb700_cimx_config(AMDSBCFG *sb_cfg); + +/** + * @brief Entry point of Southbridge CIMx callout + * + * prototype UINT32 (*SBCIM_HOOK_ENTRY)(UINT32 Param1, UINT32 Param2, void* pConfig) + * + * @param[in] func Southbridge CIMx Function ID. + * @param[in] data Southbridge Input Data. + * @param[in] sb_cfg Southbridge configuration structure pointer. + * + */ +u32 sb700_callout_entry(u32 func, u32 data, void* sb_cfg); + +#endif //_SB700_CFG_H_

1 0

Patch set updated for coreboot: 0303640 SIO: Winbond w83627dhg update
by Kerry Sheh Jan. 31, 2012

Jan. 31, 2012

Kerry Sheh (shekairui(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/565 -gerrit commit 03036400344cb59079c47ed0d9949e5b89e6e904 Author: Kerry Sheh <shekairui(a)gmail.com> Date: Tue Jan 31 20:42:27 2012 +0800 SIO: Winbond w83627dhg update 1. Stop include c file. 2. W83627dhg Pin 89, Pin 90 are multi function pins, add support to select them to I2C function. Change-Id: I42eaaf7d70aa48d7edf2710349b51e401526c1a6 Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> --- src/mainboard/asrock/939a785gmh/romstage.c | 2 +- src/mainboard/kontron/kt690/romstage.c | 2 +- src/superio/winbond/w83627dhg/Makefile.inc | 2 + src/superio/winbond/w83627dhg/early_serial.c | 29 +++++++++++++++++++++++-- src/superio/winbond/w83627dhg/superio.c | 4 +- src/superio/winbond/w83627dhg/w83627dhg.h | 6 +++++ 6 files changed, 38 insertions(+), 7 deletions(-) diff --git a/src/mainboard/asrock/939a785gmh/romstage.c b/src/mainboard/asrock/939a785gmh/romstage.c index 3183c1c..4a1b1c3 100644 --- a/src/mainboard/asrock/939a785gmh/romstage.c +++ b/src/mainboard/asrock/939a785gmh/romstage.c @@ -39,7 +39,7 @@ #include <spd.h> #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" -#include "superio/winbond/w83627dhg/early_serial.c" +#include "superio/winbond/w83627dhg/w83627dhg.h" #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" diff --git a/src/mainboard/kontron/kt690/romstage.c b/src/mainboard/kontron/kt690/romstage.c index f2525e3..621c27f 100644 --- a/src/mainboard/kontron/kt690/romstage.c +++ b/src/mainboard/kontron/kt690/romstage.c @@ -40,7 +40,7 @@ #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/winbond/w83627dhg/early_serial.c" +#include "superio/winbond/w83627dhg/w83627dhg.h" #include <cpu/amd/mtrr.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" diff --git a/src/superio/winbond/w83627dhg/Makefile.inc b/src/superio/winbond/w83627dhg/Makefile.inc index 0b0bb8b..09df47e 100644 --- a/src/superio/winbond/w83627dhg/Makefile.inc +++ b/src/superio/winbond/w83627dhg/Makefile.inc @@ -2,6 +2,7 @@ ## This file is part of the coreboot project. ## ## Copyright (C) 2008 Uwe Hermann <uwe(a)hermann-uwe.de> +## Copyright (C) 2012 Advanced Micro Devices, Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -18,5 +19,6 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +romstage-$(CONFIG_SUPERIO_WINBOND_W83627DHG) += early_serial.c ramstage-$(CONFIG_SUPERIO_WINBOND_W83627DHG) += superio.c diff --git a/src/superio/winbond/w83627dhg/early_serial.c b/src/superio/winbond/w83627dhg/early_serial.c index f530dc6..e0be8de 100644 --- a/src/superio/winbond/w83627dhg/early_serial.c +++ b/src/superio/winbond/w83627dhg/early_serial.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2008 Uwe Hermann <uwe(a)hermann-uwe.de> + * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,24 +19,26 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <arch/io.h> #include <arch/romcc_io.h> +#include <device/pnp_def.h> #include <stdint.h> #include "w83627dhg.h" -static void pnp_enter_ext_func_mode(device_t dev) +void pnp_enter_ext_func_mode(device_t dev) { u16 port = dev >> 8; outb(0x87, port); outb(0x87, port); } -static void pnp_exit_ext_func_mode(device_t dev) +void pnp_exit_ext_func_mode(device_t dev) { u16 port = dev >> 8; outb(0xaa, port); } -static void w83627dhg_enable_serial(device_t dev, u16 iobase) +void w83627dhg_enable_serial(device_t dev, u16 iobase) { pnp_enter_ext_func_mode(dev); pnp_set_logical_device(dev); @@ -44,3 +47,23 @@ static void w83627dhg_enable_serial(device_t dev, u16 iobase) pnp_set_enable(dev, 1); pnp_exit_ext_func_mode(dev); } + +/** + * Select Pin 89, Pin 90 function as I2C interface SDA, SCL. + * {Pin 89, Pin 90} function can be selected as {GP33, GP32}, or + * {RSTOUT3#, RSTOUT2#} or {SDA, SCL} + */ +void w83627dhg_enable_i2c(device_t dev) +{ + u8 val; + + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(dev); + + val = pnp_read_config(dev, 0x2A); + val |= 1 << 1; + pnp_write_config(dev, 0x2A, val); + + pnp_exit_ext_func_mode(dev); +} + diff --git a/src/superio/winbond/w83627dhg/superio.c b/src/superio/winbond/w83627dhg/superio.c index 1771c26..a936ce1 100644 --- a/src/superio/winbond/w83627dhg/superio.c +++ b/src/superio/winbond/w83627dhg/superio.c @@ -26,13 +26,13 @@ #include "chip.h" #include "w83627dhg.h" -static void pnp_enter_ext_func_mode(device_t dev) +void pnp_enter_ext_func_mode(device_t dev) { outb(0x87, dev->path.pnp.port); outb(0x87, dev->path.pnp.port); } -static void pnp_exit_ext_func_mode(device_t dev) +void pnp_exit_ext_func_mode(device_t dev) { outb(0xaa, dev->path.pnp.port); } diff --git a/src/superio/winbond/w83627dhg/w83627dhg.h b/src/superio/winbond/w83627dhg/w83627dhg.h index 74761e9..158e60b 100644 --- a/src/superio/winbond/w83627dhg/w83627dhg.h +++ b/src/superio/winbond/w83627dhg/w83627dhg.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2008 Uwe Hermann <uwe(a)hermann-uwe.de> + * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -51,4 +52,9 @@ /* Note: There is no GPIO1 on the W83627DHG as per datasheet. */ +void pnp_enter_ext_func_mode(device_t dev); +void pnp_exit_ext_func_mode(device_t dev); +void w83627dhg_enable_serial(device_t dev, u16 iobase); +void w83627dhg_enable_i2c(device_t dev); + #endif

1 0