coreboot January 2012

coreboot@coreboot.org

40 participants
302 discussions

Re: [coreboot] Trying to port abit A-S78H
by Prakash Punnoor 03 Feb '12

03 Feb '12

On Monday 23 January 2012 22:35:22 Scott Duplichan wrote: > Prakash Punnoor wrote: > ]So, I cannot make coreboot boot. On cold start it seems to hang in > ] > ]src/southbridge/amd/sb700/reset.c > ] > ]in soft_reset. set_bios_reset seems sucessful, but I get no post code after > > ]outb(0x06, 0x0cf9). Any idea, what I can try? > > Maybe the reset is just causing your port 80 routing to be lost. You need > to execute some port 80 enable and routing code as early as possible. > Is your port 80 card PCI or LPC? For the LPC type, I believe you only > have to set 'Port enable for IO port 80h' (bit 5 of pci config register 4Ah > on device 14h, function 3). To route port 80 to PCI, I think you have to set > 'IO Enable' (bit 0 of PCI config register 4 on device 14h, function 4). Sounds reasonable. It is a PCI port 80 card. I'll try that when I find time. BTW, could you explain what happens after soft_reset? Will coreboot run again from start? At least the following "die(...)" statement (romstage.c cache_as_ram_main) suggests that program flow should NOT get there. So, if coreboots runs again from start, why doesn't it enable port 80 again like it did initially? Thanks, Prakash

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Patch merged into coreboot/master: cb54abe i3100: add sata_ports_implemented option
by gerrit＠coreboot.org 31 Jan '12

31 Jan '12

the following patch was just integrated into master: commit cb54abee3ffa57e67f2803a79ed2ce8a612fa2b9 Author: Sven Schnelle <svens(a)stackframe.org> Date: Tue Jan 31 22:44:53 2012 +0100 i3100: add sata_ports_implemented option BIOS needs to set the bit mask which ports are iplemented on the board. Without setting this option, seabios fails to boot from SATA. Change-Id: I21de3fde3a9cff7c590226f70fa549274f36e2a8 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> Build-Tested: build bot (Jenkins) at Tue Jan 31 23:16:37 2012, giving +1 Reviewed-By: Sven Schnelle <svens(a)stackframe.org> at Tue Jan 31 23:31:28 2012, giving +2 See http://review.coreboot.org/601 for details. -gerrit

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Patch merged into coreboot/master: 00d2638 i3100: Add init sequence
by gerrit＠coreboot.org 31 Jan '12

31 Jan '12

the following patch was just integrated into master: commit 00d263825b8deaddd8a6bf573bc97fb625f22bdf Author: Sven Schnelle <svens(a)stackframe.org> Date: Tue Jan 31 22:40:50 2012 +0100 i3100: Add init sequence i3100 misses the magic SATA init sequence, which makes all requests fail. Captured from the vendor BIOS, which writes those bits on all configurations. Change-Id: I293b7d9cd681181311ecaced6d7df9b2706c711f Signed-off-by: Sven Schnelle <svens(a)stackframe.org> Build-Tested: build bot (Jenkins) at Tue Jan 31 22:53:26 2012, giving +1 Reviewed-By: Sven Schnelle <svens(a)stackframe.org> at Tue Jan 31 23:31:41 2012, giving +2 See http://review.coreboot.org/600 for details. -gerrit

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Patch merged into coreboot/master: 9f73df7 X86: fix cpu_phys_address_size()
by gerrit＠coreboot.org 31 Jan '12

31 Jan '12

the following patch was just integrated into master: commit 9f73df7837c00d07a4f29527c2d10308d708209b Author: Sven Schnelle <svens(a)stackframe.org> Date: Tue Jan 31 22:10:28 2012 +0100 X86: fix cpu_phys_address_size() CPUs with CPUID level >= 0x80000008 can return the number of physical address bits. Change-Id: I1c0523b6a091c476af838d173ed9030280360d7f Signed-off-by: Sven Schnelle <svens(a)stackframe.org> Build-Tested: build bot (Jenkins) at Tue Jan 31 22:35:54 2012, giving +1 Reviewed-By: Sven Schnelle <svens(a)stackframe.org> at Tue Jan 31 22:47:39 2012, giving +2 See http://review.coreboot.org/599 for details. -gerrit

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New patch to review for coreboot: cb54abe i3100: add sata_ports_implemented option
by Sven Schnelle 31 Jan '12

31 Jan '12

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/601 -gerrit commit cb54abee3ffa57e67f2803a79ed2ce8a612fa2b9 Author: Sven Schnelle <svens(a)stackframe.org> Date: Tue Jan 31 22:44:53 2012 +0100 i3100: add sata_ports_implemented option BIOS needs to set the bit mask which ports are iplemented on the board. Without setting this option, seabios fails to boot from SATA. Change-Id: I21de3fde3a9cff7c590226f70fa549274f36e2a8 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/southbridge/intel/i3100/chip.h | 1 + src/southbridge/intel/i3100/sata.c | 11 ++++++++++- 2 files changed, 11 insertions(+), 1 deletions(-) diff --git a/src/southbridge/intel/i3100/chip.h b/src/southbridge/intel/i3100/chip.h index f35e4a8..7e58674 100644 --- a/src/southbridge/intel/i3100/chip.h +++ b/src/southbridge/intel/i3100/chip.h @@ -43,6 +43,7 @@ struct southbridge_intel_i3100_config /* GPIO use select */ u8 gpio[64]; + int sata_ports_implemented; u32 pirq_a_d; u32 pirq_e_h; }; diff --git a/src/southbridge/intel/i3100/sata.c b/src/southbridge/intel/i3100/sata.c index 1925f88..2341ca1 100644 --- a/src/southbridge/intel/i3100/sata.c +++ b/src/southbridge/intel/i3100/sata.c @@ -31,7 +31,14 @@ typedef struct southbridge_intel_i3100_config config_t; static void sata_init(struct device *dev) { - u8 ahci; + u8 ahci; + u32 *ahci_bar; + config_t *config = dev->chip_info; + + if (config == NULL) { + printk(BIOS_ERR, "i3100_sata: error: device not in devicetree.cb!\n"); + return; + } /* Get the chip configuration */ ahci = (pci_read_config8(dev, SATA_MAP) >> 6) & 0x03; @@ -58,6 +65,8 @@ static void sata_init(struct device *dev) /* IDE I/O configuration */ pci_write_config32(dev, SATA_IIOC, 0); + ahci_bar = (u32 *)(pci_read_config32(dev, 0x27) & ~0x3ff); + ahci_bar[3] = config->sata_ports_implemented; } else { /* SATA configuration */ pci_write_config8(dev, SATA_CMD, 0x07);

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New patch to review for coreboot: 00d2638 i3100: Add init sequence
by Sven Schnelle 31 Jan '12

31 Jan '12

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/600 -gerrit commit 00d263825b8deaddd8a6bf573bc97fb625f22bdf Author: Sven Schnelle <svens(a)stackframe.org> Date: Tue Jan 31 22:40:50 2012 +0100 i3100: Add init sequence i3100 misses the magic SATA init sequence, which makes all requests fail. Captured from the vendor BIOS, which writes those bits on all configurations. Change-Id: I293b7d9cd681181311ecaced6d7df9b2706c711f Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/southbridge/intel/i3100/sata.c | 18 ++++++++++++++++++ 1 files changed, 18 insertions(+), 0 deletions(-) diff --git a/src/southbridge/intel/i3100/sata.c b/src/southbridge/intel/i3100/sata.c index af22600..1925f88 100644 --- a/src/southbridge/intel/i3100/sata.c +++ b/src/southbridge/intel/i3100/sata.c @@ -81,6 +81,24 @@ static void sata_init(struct device *dev) pci_write_config8(dev, SATA_PCS + 1, 0x0f); } + + /* secret init sequence, required */ + pci_write_config32(dev, 0x94, 0x00400180); + pci_write_config32(dev, 0xa0, 0x18); + pci_write_config32(dev, 0xa4, 0x224); + pci_write_config32(dev, 0xa0, 0x42); + pci_write_config32(dev, 0xa4, 0x22006d); + pci_write_config32(dev, 0xa0, 0x84); + pci_write_config32(dev, 0xa4, 0x24); + pci_write_config32(dev, 0xa0, 0x7a); + pci_write_config32(dev, 0xa4, 0x220000); + pci_write_config32(dev, 0xa0, 0x9c); + pci_write_config32(dev, 0xa4, 0x24); + pci_write_config32(dev, 0xa0, 0x90); + pci_write_config32(dev, 0xa4, 0x220000); + pci_write_config32(dev, 0xa0, 0xa0); + pci_write_config32(dev, 0xa4, 0x12492aa); + printk(BIOS_DEBUG, "SATA Enabled\n"); }

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New patch to review for coreboot: 9f73df7 X86: fix cpu_phys_address_size()
by Sven Schnelle 31 Jan '12

31 Jan '12

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/599 -gerrit commit 9f73df7837c00d07a4f29527c2d10308d708209b Author: Sven Schnelle <svens(a)stackframe.org> Date: Tue Jan 31 22:10:28 2012 +0100 X86: fix cpu_phys_address_size() CPUs with CPUID level >= 0x80000008 can return the number of physical address bits. Change-Id: I1c0523b6a091c476af838d173ed9030280360d7f Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/arch/x86/lib/cpu.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/arch/x86/lib/cpu.c b/src/arch/x86/lib/cpu.c index aaa0a16..ada57e2 100644 --- a/src/arch/x86/lib/cpu.c +++ b/src/arch/x86/lib/cpu.c @@ -144,7 +144,7 @@ int cpu_phys_address_size(void) if (!(have_cpuid_p())) return 32; - if (cpu_cpuid_extended_level() > 0x80000008) + if (cpu_cpuid_extended_level() >= 0x80000008) return cpuid_eax(0x80000008) & 0xff; if (cpuid_eax(1) & (CPUID_FEATURE_PAE | CPUID_FEATURE_PSE36))

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Re: [coreboot] Asus M2V-MX problems
by Gregg Levine 31 Jan '12

31 Jan '12

On Tue, Jan 31, 2012 at 11:56 AM, David Hillman <hillmands(a)gmail.com> wrote: > I was hoping to use the board above to experiment with Coreboot. The board > has the same northbridge as the Asus M2V-MX SE (VIA K8M890) and the same > southbridge as the Asus M2V (VIA 8237A). Both of those chipsets are fully > supported. Thinking that maybe I can at least get the board to boot ASAP, I > built Coreboot for the Asus M2V board to get the southbridge functionality. > I also didn't use the M2V-MX SE profile because it has the SPI chip, while > the M2V-MX board has a PLCC-32 chip. > > The board booted fine, except I have no video, serial port or ability to > write to the BIOS chip. I know the board booted fine because I was able to > SSH into the box using a PCI network card. Considering that both the M2V > and M2V-MX have the same southbridge chip, I don't understand why there was > not serial port or write access to the BIOS chip. Can someone shed some > light on that for me, please. > > My other problem is I would like to create a build profile for the M2V-MX > using the code from the M2V for the southbridge and the code from the M2V-MX > SE for the northbridge. Is that a good idea or would I have to do some > other things? I learned C programming in 1993 and used it only until 1998; > I am a little rusty. My ability to make sense of low-level chipset stuff is > also very narrow. However, I am a fast learner and I am desperate to get > something accomplished for a homebrew thin client project that I have spent > way too much time working on. > > My goal is to extend the life of boards that people send in for recycling by > turning them into more reliable diskless information terminals. Thanks. > > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot Hello! Interesting. I freely admit that I'm not very familiar with the way Coreboot does it thing because its evolved past its humble beginnings. That being said can you make use of your SSH connection to retrieve the log for its boot sequence? We'd need to know what was launched, what was not, and why your board is ignoring video and serial. ----- Gregg C Levine gregg.drwho8(a)gmail.com "This signature fought the Time Wars, time and again."

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Patch merged into coreboot/master: 6e8ae90 X60/T60: Add option to enable/disable bluetooth
by gerrit＠coreboot.org 31 Jan '12

31 Jan '12

the following patch was just integrated into master: commit 6e8ae90bbb68e1caa9e0c55e30bc66c5e2fe2007 Author: Sven Schnelle <svens(a)stackframe.org> Date: Tue Jan 31 17:41:12 2012 +0100 X60/T60: Add option to enable/disable bluetooth Change-Id: I9761a8a9a7cc708fe95169cb8b79b413b97ee523 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> Build-Tested: build bot (Jenkins) at Tue Jan 31 18:03:15 2012, giving +1 Reviewed-By: Sven Schnelle <svens(a)stackframe.org> at Tue Jan 31 17:52:19 2012, giving +2 See http://review.coreboot.org/598 for details. -gerrit

1 0

Asus M2V-MX problems
by David Hillman 31 Jan '12

31 Jan '12

I was hoping to use the board above to experiment with Coreboot. The board has the same northbridge as the Asus M2V-MX SE (VIA K8M890) and the same southbridge as the Asus M2V (VIA 8237A). Both of those chipsets are fully supported. Thinking that maybe I can at least get the board to boot ASAP, I built Coreboot for the Asus M2V board to get the southbridge functionality. I also didn't use the M2V-MX SE profile because it has the SPI chip, while the M2V-MX board has a PLCC-32 chip. The board booted fine, except I have no video, serial port or ability to write to the BIOS chip. I know the board booted fine because I was able to SSH into the box using a PCI network card. Considering that both the M2V and M2V-MX have the same southbridge chip, I don't understand why there was not serial port or write access to the BIOS chip. Can someone shed some light on that for me, please. My other problem is I would like to create a build profile for the M2V-MX using the code from the M2V for the southbridge and the code from the M2V-MX SE for the northbridge. Is that a good idea or would I have to do some other things? I learned C programming in 1993 and used it only until 1998; I am a little rusty. My ability to make sense of low-level chipset stuff is also very narrow. However, I am a fast learner and I am desperate to get something accomplished for a homebrew thin client project that I have spent way too much time working on. My goal is to extend the life of boards that people send in for recycling by turning them into more reliable diskless information terminals. Thanks.

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coreboot January 2012