coreboot January 2012

coreboot@coreboot.org

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302 discussions

Patch merged into coreboot/master: 53fe1f9 X60: fix docking
by gerrit＠coreboot.org 31 Jan '12

31 Jan '12

the following patch was just integrated into master: commit 53fe1f939c9f1b5ac8787c61f7c2fb285c3933fc Author: Sven Schnelle <svens(a)stackframe.org> Date: Tue Jan 10 14:44:12 2012 +0100 X60: fix docking Fix ordering of power/reset/undock procedure to prevent crashes seen with the old code. Also call dlpc_init() only once. Change-Id: I27d1f42e845fcccde40e6ca5af4a7762edab5d36 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> Build-Tested: build bot (Jenkins) at Tue Jan 31 17:51:59 2012, giving +1 Reviewed-By: Sven Schnelle <svens(a)stackframe.org> at Tue Jan 31 17:53:29 2012, giving +2 See http://review.coreboot.org/597 for details. -gerrit

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New patch to review for coreboot: 6e8ae90 X60/T60: Add option to enable/disable bluetooth
by Sven Schnelle 31 Jan '12

31 Jan '12

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/598 -gerrit commit 6e8ae90bbb68e1caa9e0c55e30bc66c5e2fe2007 Author: Sven Schnelle <svens(a)stackframe.org> Date: Tue Jan 31 17:41:12 2012 +0100 X60/T60: Add option to enable/disable bluetooth Change-Id: I9761a8a9a7cc708fe95169cb8b79b413b97ee523 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/ec/lenovo/h8/h8.c | 11 +++++++++++ src/mainboard/lenovo/t60/cmos.layout | 1 + src/mainboard/lenovo/x60/cmos.layout | 1 + 3 files changed, 13 insertions(+), 0 deletions(-) diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c index f20cd38..ecd34b2 100644 --- a/src/ec/lenovo/h8/h8.c +++ b/src/ec/lenovo/h8/h8.c @@ -27,6 +27,14 @@ #include "chip.h" #include <pc80/mc146818rtc.h> +static void h8_bluetooth_enable(int on) +{ + if (on) + ec_set_bit(0x3a, 4); + else + ec_clr_bit(0x3a, 4); +} + void h8_trackpoint_enable(int on) { ec_write(H8_TRACKPOINT_CTRL, @@ -143,6 +151,9 @@ static void h8_enable(device_t dev) ec_write(H8_VOLUME_CONTROL, val); + if (!get_option(&val, "bluetooth")) + h8_bluetooth_enable(val); + if (!get_option(&val, "first_battery")) { tmp = ec_read(H8_CONFIG3); tmp &= ~(1 << 4); diff --git a/src/mainboard/lenovo/t60/cmos.layout b/src/mainboard/lenovo/t60/cmos.layout index 8d9dce4..7539b60 100644 --- a/src/mainboard/lenovo/t60/cmos.layout +++ b/src/mainboard/lenovo/t60/cmos.layout @@ -108,6 +108,7 @@ entries 1052 4 r 0 C1DRT1 1060 1 e 1 touchpad +1061 1 e 1 bluetooth 1064 8 h 0 volume 1072 1 e 9 first_battery # ----------------------------------------------------------------- diff --git a/src/mainboard/lenovo/x60/cmos.layout b/src/mainboard/lenovo/x60/cmos.layout index cae70cb..ab51a84 100644 --- a/src/mainboard/lenovo/x60/cmos.layout +++ b/src/mainboard/lenovo/x60/cmos.layout @@ -110,6 +110,7 @@ entries 1064 8 h 0 volume 1072 8 h 0 tft_brightness 1080 1 e 9 first_battery +1081 1 e 1 bluetooth # ----------------------------------------------------------------- enumerations

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Re: [coreboot] Asus m2n-e mcp55 won't boot
by Marc Jones 31 Jan '12

31 Jan '12

On Mon, Jan 30, 2012 at 6:17 AM, Julian Shulika <hercares(a)gmail.com> wrote: > Hi. I compiled coreboot image for Asus m2n-e (mcp55,ite 8716f). This board > turns off after few seconds > The log from serial > > Welcome to minicom 2.5 > > OPTIONS: > Compiled on Dec 4 2011, 11:23:38. > Port /dev/ttyS0 > > Press CTRL-A Z for help on special keys > > > > coreboot-4.0-1980-gcc16cca-dirty Sat Jan 28 15:06:08 EST 2012 starting... > *sysinfo range: [000cf000,000cf730] > bsp_apicid=0x00 > Enabling routing table for node 00 done. > Enabling UP settings > Disabling read/write/fill probes for UP... done. > coherent_ht_finalize > done > core0 started: > started ap apicid: > SBLink=00 > NC node|link=00 > entering > optimize_link_incoherent_ht > sysinfo->link_pair_num=0x1 > entering > ht_optimize_link > pos=0x8a, unfiltered > freq_cap=0x8075 > pos=0x8a, filtered > freq_cap=0x75 > pos=0x52, unfiltered > freq_cap=0x807f > pos=0x52, filtered > freq_cap=0x7f > freq_cap1=0x75, > freq_cap2=0x7f > dev1 old_freq=0x0, freq=0x6, > needs_reset=0x1 > dev2 old_freq=0x0, freq=0x6, > needs_reset=0x1 > width_cap1=0x11, > width_cap2=0x11 > dev1 input ln_width1=0x4, > ln_width2=0x4 > dev1 input > width=0x1 > dev1 output ln_width1=0x4, > ln_width2=0x4 > dev1 input|output > width=0x11 > old dev1 input|output > width=0x11 > dev2 input|output > width=0x11 > old dev2 input|output > width=0x11 > after ht_optimize_link for link pair 0, > reset_needed=0x1 > after optimize_link_read_pointers_chain, > reset_needed=0x1 > mcp55_num:01 > ht reset > - > > > coreboot-4.0-1980-gcc16cca-dirty Sat Jan 28 15:06:08 EST 2012 > starting... > *sysinfo range: > [000cf000,000cf730] > bsp_apicid=0x00 > Enabling routing table for node 00 > done. > Enabling UP > settings > Disabling read/write/fill probes for UP... > done. > coherent_ht_finalize > done > core0 > started: > started ap > apicid: > SBLink=00 > NC > node|link=00 > entering > optimize_link_incoherent_ht > sysinfo->link_pair_num=0x1 > entering > ht_optimize_link > pos=0x8a, unfiltered > freq_cap=0x8075 > pos=0x8a, filtered > freq_cap=0x75 > pos=0x52, unfiltered > freq_cap=0x7f > pos=0x52, filtered > freq_cap=0x7f > freq_cap1=0x75, > freq_cap2=0x7f > dev1 old_freq=0x6, freq=0x6, > needs_reset=0x0 > dev2 old_freq=0x6, freq=0x6, > needs_reset=0x0 > width_cap1=0x11, > width_cap2=0x11 > dev1 input ln_width1=0x4, > ln_width2=0x4 > dev1 input > width=0x1 > dev1 output ln_width1=0x4, > ln_width2=0x4 > dev1 input|output > width=0x11 > old dev1 input|output > width=0x11 > dev2 input|output > width=0x11 > old dev2 input|output > width=0x11 > after ht_optimize_link for link pair 0, > reset_needed=0x0 > after optimize_link_read_pointers_chain, > reset_needed=0x0 > mcp55_num:01 > Ram1.00 > setting up CPU 00 northbridge > registers > done. > Ram2.00 > sdram_set_spd_registers: paramx > :000cef20 > Enable 64MuxMode & > BurstLength32 > Unbuffered > 333MHz > 333MHz > set_ecc spd_device: > 0x51 > Interleaving > disabled > RAM end at 0x00080000 > kB > Ram3 > ECC > enabled > Initializing memory: > done > Setting variable MTRR 2, base: 0MB, range: 512MB, type > WB > set DQS timing:RcvrEn:Pass1: > 00 > CTLRMaxDelay=03 > done > set DQS timing:DQSPos: > 00 > TrainDQSRdWrPos: > buf_a:000ce9f0 > TrainDQSPos: MutualCSPassW[48] > :000ce8c8 > TrainDQSPos: MutualCSPassW[48] > :000ce8c8 > TrainDQSPos: MutualCSPassW[48] > :000ce8c8 > TrainDQSPos: MutualCSPassW[48] > :000ce8d8 > done > set DQS timing:RcvrEn:Pass2: > 00 > CTLRMaxDelay=58 > done > Total DQS Training : tsc > [00]=0000000012e40bef > Total DQS Training : tsc > [01]=000000001358f446 > Total DQS Training : tsc > [02]=0000000018d60c82 > Total DQS Training : tsc > [03]=0000000019771d46 > Ram4 > v_esp=000cef68 > testx = > 5a5a5a5a > > > > INIT detected from --- { APICID = 00 NODEID = 00 COREID = 00} > --- > > Issuing > SOFT_RESET... > > > coreboot-4.0-1980-gcc16cca-dirty Sat Jan 28 15:06:08 EST 2012 > starting... > *sysinfo range: > [000cf000,000cf730] > bsp_apicid=0x00 > Enabling routing table for node 00 > done. > Enabling UP > settings > Disabling read/write/fill probes for UP... > done. > coherent_ht_finalize > done > core0 > started: > started ap > apicid: > SBLink=00 > NC > node|link=00 > entering > optimize_link_incoherent_ht > sysinfo->link_pair_num=0x1 > entering > ht_optimize_link > pos=0x8a, unfiltered > freq_cap=0x8075 > pos=0x8a, filtered > freq_cap=0x75 > pos=0x52, unfiltered > freq_cap=0x7f > pos=0x52, filtered > freq_cap=0x7f > freq_cap1=0x75, > freq_cap2=0x7f > dev1 old_freq=0x6, freq=0x6, > needs_reset=0x0 > dev2 old_freq=0x6, freq=0x6, > needs_reset=0x0 > width_cap1=0x11, > width_cap2=0x11 > dev1 input ln_width1=0x4, > ln_width2=0x4 > dev1 input > width=0x1 > dev1 output ln_width1=0x4, > ln_width2=0x4 > dev1 input|output > width=0x11 > old dev1 input|output > width=0x11 > dev2 input|output > width=0x11 > old dev2 input|output > width=0x11 > after ht_optimize_link for link pair 0, > reset_needed=0x0 > after optimize_link_read_pointers_chain, > reset_needed=0x0 > mcp55_num:01 > Ram1.00 > setting up CPU 00 northbridge > registers > done. > Ram2.00 > sdram_set_spd_registers: paramx > :000cef20 > Enable 64MuxMode & > BurstLength32 > Unbuffered > 333MHz > 333MHz > set_ecc spd_device: > 0x51 > Interleaving > disabled > RAM end at 0x00080000 > kB > Ram3 > ECC > enabled > Initializing memory: > done > Setting variable MTRR 2, base: 0MB, range: 512MB, type > WB > set DQS timing:RcvrEn:Pass1: > 00 > CTLRMaxDelay=03 > done > set DQS timing:DQSPos: > 00 > TrainDQSRdWrPos: > buf_a:000ce9f0 > TrainDQSPos: MutualCSPassW[48] > :000ce8c8 > TrainDQSPos: MutualCSPassW[48] > :000ce8c8 > TrainDQSPos: MutualCSPassW[48] > :000ce8c8 > TrainDQSPos: MutualCSPassW[48] > :000ce8d8 > done > set DQS timing:RcvrEn:Pass2: > 00 > CTLRMaxDelay=58 > done > Total DQS Training : tsc > [00]=0000000012e3eacf > Total DQS Training : tsc > [01]=000000001358d326 > Total DQS Training : tsc > [02]=0000000018d97cfa > Total DQS Training : tsc > [03]=00000000197a8c56 > Ram4 > v_esp=000cef68 > testx = > 5a5a5a5a > Copying data from cache to RAM -- switching to use RAM as stack... > D > > > INIT detected from --- { APICID = 00 NODEID = 00 COREID = 00} > --- > > Issuing > SOFT_RESET... > > > coreboot-4.0-1980-gcc16cca-dirty Sat Jan 28 15:06:08 EST 2012 > starting... > *sysinfo range: > [000cf000,000cf730] > bsp_apicid=0x00 > Enabling routing table for node 00 > done. > Enabling UP > settings > Disabling read/write/fill probes for UP... > done. > coherent_ht_finalize > done > core0 > started: > started ap > apicid: > SBLink=00 > NC > node|link=00 > entering > optimize_link_incoherent_ht > sysinfo->link_pair_num=0x1 > entering > ht_optimize_link > pos=0x8a, unfiltered > freq_cap=0x8075 > pos=0x8a, filtered > freq_cap=0x75 > pos=0x52, unfiltered > freq_cap=0x7f > pos=0x52, filtered > freq_cap=0x7f > freq_cap1=0x75, > freq_cap2=0x7f > dev1 old_freq=0x6, freq=0x6, > needs_reset=0x0 > dev2 old_freq=0x6, freq=0x6, > needs_reset=0x0 > width_cap1=0x11, > width_cap2=0x11 > dev1 input ln_width1=0x4, > ln_width2=0x4 > dev1 input > width=0x1 > dev1 output ln_width1=0x4, > ln_width2=0x4 > dev1 input|output > width=0x11 > old dev1 input|output > width=0x11 > dev2 input|output > width=0x11 > old dev2 input|output > width=0x11 > after ht_optimize_link for link pair 0, > reset_needed=0x0 > after optimize_link_read_pointers_chain, > reset_needed=0x0 > mcp55_num:01 > Ram1.00 > setting up CPU 00 northbridge > registers > done. > Ram2.00 > sdram_set_spd_registers: paramx > :000cef20 > Enable 64MuxMode & > BurstLength32 > Unbuffered > 333MHz > 333MHz > set_ecc spd_device: > 0x51 > Interleaving > disabled > RAM end at 0x00080000 > kB > Ram3 > ECC > enabled > Initializing memory: > done > Setting variable MTRR 2, base: 0MB, range: 512MB, type > WB > set DQS timing:RcvrEn:Pass1: > 00 > CTLRMaxDelay=03 > done > set DQS timing:DQSPos: > 00 > TrainDQSRdWrPos: > buf_a:000ce9f0 > TrainDQSPos: MutualCSPassW[48] > :000ce8c8 > TrainDQSPos: MutualCSPassW[48] > :000ce8c8 > TrainDQSPos: MutualCSPassW[48] > :000ce8c8 > TrainDQSPos: MutualCSPassW[48] > :000ce8d8 > done > set DQS timing:RcvrEn:Pass2: > 00 > CTLRMaxDelay=58 > done > Total DQS Training : tsc > [00]=0000000012e3ed63 > Total DQS Training : tsc > [01]=000000001358f68a > Total DQS Training : tsc > [02]=0000000018d73a6a > Total DQS Training : tsc > [03]=0000000019784e5a > Ram4 > v_esp=000cef68 > testx = > 5a5a5a5a > Copying data from cache to RAM -- switching to use RAM as stack... > m > > > INIT detected from --- { APICID = 00 NODEID = 00 COREID = 00} > --- > > Issuing > SOFT_RESET... > > > coreboot-4.0-1980-gcc16cca-dirty Sat Jan 28 15:06:08 EST 2012 > starting... > *sysinfo range: > [000cf000,000cf730] > bsp_apicid=0x00 > Enabling routing table for node 00 > done. > Enabling UP > settings > Disabling read/write/fill probes for UP... > done. > coherent_ht_finalize > done > core0 > started: > started ap > apicid: > SBLink=00 > NC > node|link=00 > entering > optimize_link_incoherent_ht > sysinfo->link_pair_num=0x1 > entering > ht_optimize_link > pos=0x8a, unfiltered > freq_cap=0x8075 > pos=0x8a, filtered > freq_cap=0x75 > pos=0x52, unfiltered > freq_cap=0x7f > pos=0x52, filtered > freq_cap=0x7f > freq_cap1=0x75, > freq_cap2=0x7f > dev1 old_freq=0x6, freq=0x6, > needs_reset=0x0 > dev2 old_freq=0x6, freq=0x6, > needs_reset=0x0 > width_cap1=0x11, > width_cap2=0x11 > dev1 input ln_width1=0x4, > ln_width2=0x4 > dev1 input > width=0x1 > dev1 output ln_width1=0x4, > ln_width2=0x4 > dev1 input|output > width=0x11 > old dev1 input|output > width=0x11 > dev2 input|output > width=0x11 > old dev2 input|output > width=0x11 > after ht_optimize_link for link pair 0, > reset_needed=0x0 > after optimize_link_read_pointers_chain, > reset_needed=0x0 > mcp55_num:01 > Ram1.00 > setting up CPU 00 northbridge > registers > done. > Ram2.00 > sdram_set_spd_registers: paramx > :000cef20 > Enable 64MuxMode & > BurstLength32 > Unbuffered > 333MHz > 333MHz > set_ecc spd_device: > 0x51 > Interleaving > disabled > RAM end at 0x00080000 > kB > Ram3 > ECC > enabled > Initializing memory: > done > Setting variable MTRR 2, base: 0MB, range: 512MB, type > WB > set DQS timing:RcvrEn:Pass1: > 00 > CTLRMaxDelay=03 > done > set DQS timing:DQSPos: > 00 > TrainDQSRdWrPos: > buf_a:000ce9f0 > TrainDQSPos: MutualCSPassW[48] > :000ce8c8 > TrainDQSPos: MutualCSPassW[48] > :000ce8c8 > TrainDQSPos: MutualCSPassW[48] > :000ce8c8 > TrainDQSPos: MutualCSPassW[48] > :000ce8d8 > done > set DQS timing:RcvrEn:Pass2: > 00 > CTLRMaxDelay=58 > done > Total DQS Training : tsc > [00]=0000000012e4504b > Total DQS Training : tsc > [01]=0000000013593c4a > Total DQS Training : tsc > [02]=0000000018d6d4b2 > Total DQS Training : tsc > [03]=000000001977e9ce > Ram4 > v_esp=000cef68 > testx = > 5a5a5a5a > Copying data from cache to RAM -- switching to use RAM as stack... Hi Julian, Looks like a memory issue of some type. Try a single dimm or a different slot. You might also try adding in a memory test at the end of romstage.c. Marc -- http://se-eng.com

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New patch to review for coreboot: 53fe1f9 X60: fix docking
by Sven Schnelle 31 Jan '12

31 Jan '12

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/597 -gerrit commit 53fe1f939c9f1b5ac8787c61f7c2fb285c3933fc Author: Sven Schnelle <svens(a)stackframe.org> Date: Tue Jan 10 14:44:12 2012 +0100 X60: fix docking Fix ordering of power/reset/undock procedure to prevent crashes seen with the old code. Also call dlpc_init() only once. Change-Id: I27d1f42e845fcccde40e6ca5af4a7762edab5d36 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/mainboard/lenovo/x60/dock.c | 33 +++++++++++++++++++---------- src/mainboard/lenovo/x60/mainboard_smi.c | 5 ++- src/mainboard/lenovo/x60/romstage.c | 4 +- 3 files changed, 26 insertions(+), 16 deletions(-) diff --git a/src/mainboard/lenovo/x60/dock.c b/src/mainboard/lenovo/x60/dock.c index eed00a1..37d5b76 100644 --- a/src/mainboard/lenovo/x60/dock.c +++ b/src/mainboard/lenovo/x60/dock.c @@ -107,6 +107,15 @@ int dlpc_init(void) /* Activate DLPC */ dlpc_write_register(0x30, 0x01); + dlpc_gpio_init(); + + return 0; +} + +int dock_connect(void) +{ + int timeout = 1000; + outb(0x07, 0x164c); timeout = 1000; @@ -121,26 +130,18 @@ int dlpc_init(void) return 1; } - dlpc_gpio_init(); - - return 0; -} - -int dock_connect(void) -{ - int timeout = 1000; - /* Assert D_PLTRST# */ outb(0xfe, 0x1680); udelay(100000); /* Deassert D_PLTRST# */ outb(0xff, 0x1680); - udelay(1000); + udelay(100000); /* startup 14.318MHz Clock */ dock_write_register(0x29, 0x06); /* wait until clock is settled */ + timeout = 1000; while(!(dock_read_register(0x29) & 0x08) && timeout--) udelay(1000); @@ -243,12 +244,20 @@ int dock_connect(void) void dock_disconnect(void) { - /* disable Ultrabay and USB Power */ - outb(0x00, 0x1628); + printk(BIOS_DEBUG, "%s enter\n", __func__); /* disconnect LPC bus */ outb(0x00, 0x164c); + udelay(10000); + /* Assert PLTRST and DLPCPD */ outb(0xfc, 0x1680); + udelay(10000); + + /* disable Ultrabay and USB Power */ + outb(0x00, 0x1628); + udelay(10000); + + printk(BIOS_DEBUG, "%s finish\n", __func__); } int dock_present(void) diff --git a/src/mainboard/lenovo/x60/mainboard_smi.c b/src/mainboard/lenovo/x60/mainboard_smi.c index 34f1d36..bd1333a 100644 --- a/src/mainboard/lenovo/x60/mainboard_smi.c +++ b/src/mainboard/lenovo/x60/mainboard_smi.c @@ -28,6 +28,7 @@ #include <ec/acpi/ec.h> #include <pc80/mc146818rtc.h> #include <ec/lenovo/h8/h8.h> +#include <delay.h> #include "dock.h" #include "smi.h" @@ -72,8 +73,8 @@ int mainboard_io_trap_handler(int smif) switch (smif) { case SMI_DOCK_CONNECT: ec_clr_bit(0x03, 2); - dlpc_init(); - if (!dlpc_init() && !dock_connect()) { + udelay(250000); + if (!dock_connect()) { ec_set_bit(0x03, 2); /* set dock LED to indicate status */ ec_write(0x0c, 0x09); diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index 44cde72..ee080ea 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -229,12 +229,12 @@ void main(unsigned long bist) ich7_enable_lpc(); - + dlpc_init(); /* dock_init initializes the DLPC switch on * thinpad side, so this is required even * if we're undocked. */ - if (!dlpc_init() && dock_present()) { + if (dock_present()) { dock_connect(); early_superio_config(); /* Set up the console */

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Patch merged into coreboot/master: 9829e42 mainboard/lenovo/t60, x60: Disable CHECK_SLFRCS_ON_RESUME
by gerrit＠coreboot.org 31 Jan '12

31 Jan '12

the following patch was just integrated into master: commit 9829e42122d2453ae176254d0b00bcfa0f7020db Author: Peter Stuge <peter(a)stuge.se> Date: Fri Jan 27 22:56:25 2012 +0100 mainboard/lenovo/t60, x60: Disable CHECK_SLFRCS_ON_RESUME This makes resume from S3 work. Change-Id: I472baf2fbde46bfac223ce39fc81b8e09849fb7f Signed-off-by: Peter Stuge <peter(a)stuge.se> Build-Tested: build bot (Jenkins) at Fri Jan 27 23:19:14 2012, giving +1 Reviewed-By: Sven Schnelle <svens(a)stackframe.org> at Tue Jan 31 16:59:36 2012, giving +2 See http://review.coreboot.org/591 for details. -gerrit

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New patch to review for coreboot: d2086a2 X60/T60: Disable Self refresh check
by Sven Schnelle 31 Jan '12

31 Jan '12

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/596 -gerrit commit d2086a2879a16b23a726bf361e8a160b5d5495e8 Author: Sven Schnelle <svens(a)stackframe.org> Date: Tue Jan 31 14:54:13 2012 +0100 X60/T60: Disable Self refresh check commit faa6bebeaa2dbdacb9333d20e5a2f6f52b21a3f0 introduced CHECK_SLFRCS_ON_RESUME to explicit tell coreboot on what Boards to check for self refresh status. This check is not working on X60/T60, so remove those Kconfig options. Change-Id: I9e5d918d6dd1f88737b09252ed3a3d8e44357823 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/mainboard/lenovo/t60/Kconfig | 1 - src/mainboard/lenovo/x60/Kconfig | 1 - 2 files changed, 0 insertions(+), 2 deletions(-) diff --git a/src/mainboard/lenovo/t60/Kconfig b/src/mainboard/lenovo/t60/Kconfig index 1e4afd1..d1abcf6 100644 --- a/src/mainboard/lenovo/t60/Kconfig +++ b/src/mainboard/lenovo/t60/Kconfig @@ -5,7 +5,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ARCH_X86 select CPU_INTEL_SOCKET_MFCPGA478 select NORTHBRIDGE_INTEL_I945GM - select CHECK_SLFRCS_ON_RESUME select SOUTHBRIDGE_INTEL_I82801GX select SUPERIO_NSC_PC87382 select SUPERIO_NSC_PC87384 diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig index 64a3761..69f83a8 100644 --- a/src/mainboard/lenovo/x60/Kconfig +++ b/src/mainboard/lenovo/x60/Kconfig @@ -5,7 +5,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ARCH_X86 select CPU_INTEL_SOCKET_MFCPGA478 select NORTHBRIDGE_INTEL_I945GM - select CHECK_SLFRCS_ON_RESUME select SOUTHBRIDGE_INTEL_I82801GX select SOUTHBRIDGE_RICOH_RL5C476 select SUPERIO_NSC_PC87382

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Patch merged into coreboot/master: faa6beb northbridge/intel/i945: CHECK_SLFRCS_ON_RESUME Kconfig option
by gerrit＠coreboot.org 31 Jan '12

31 Jan '12

the following patch was just integrated into master: commit faa6bebeaa2dbdacb9333d20e5a2f6f52b21a3f0 Author: Peter Stuge <peter(a)stuge.se> Date: Fri Jan 27 22:17:09 2012 +0100 northbridge/intel/i945: CHECK_SLFRCS_ON_RESUME Kconfig option Originally brought up by Sven Schnelle in March 2011 http://patchwork.coreboot.org/patch/2801/ http://www.coreboot.org/pipermail/coreboot/2011-March/064277.html On some mainboards it may be neccessary to reset early during resume from S3 if the SLFRCS register indicates that a memory channel is not guaranteed to be in self-refresh. On other mainboards, such as Lenovo X60 and T60, the check always creates false positives, effectively making it impossible to resume. The SLFRCS register is documented on page 197 of Mobile Intel® 945 Express Chipset Family Datasheet Document Number: 309219-006 which is publically available, and the register indicates if a memory channel is guaranteed to be in self-refresh mode (if bit = 1), or that a memory channel *may or may not be* in self-refresh mode (if bit = 0). The register can thus only be used to positively learn that memory is in self-refresh. It is not known for sure that memory is *not* in self-refresh. The register is reset by the PWROK signal, which *should* go low during S3, and go high again when resuming, so it is unsurprising that SLFRCS has already been cleared when we read the register. Sven's measurements of the CKE signal on a ThinkPad shows that memory remains in self-refresh indefinitely, until coreboot re-initializes the memory controller, even when SLFRCS bits were = 0. Boards which require a warm reset when SLFRCS bits are cleared must now explicitly enable the check in the mainboard Kconfig file. This commit selects the new option in all existing i945 mainboards. A follow-up commit will remove the option for ThinkPads. Change-Id: I02320675efb8fde05c371ef243ba5093a4da6d11 Signed-off-by: Peter Stuge <peter(a)stuge.se> Build-Tested: build bot (Jenkins) at Fri Jan 27 23:33:41 2012, giving +1 Reviewed-By: Sven Schnelle <svens(a)stackframe.org> at Tue Jan 31 14:52:14 2012, giving +2 See http://review.coreboot.org/590 for details. -gerrit

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New patch to review for coreboot: aa4428b libpayload: Remove workaround for bitfield management in EHCI driver
by Patrick Georgi 31 Jan '12

31 Jan '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/595 -gerrit commit aa4428b722849dc772004d4d0ab10c035b00cf3c Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Tue Jan 31 14:48:05 2012 +0100 libpayload: Remove workaround for bitfield management in EHCI driver We don't use bitfields anymore. Change-Id: I25ceec2024f659612871bcfe5f98df3a10789055 Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> --- payloads/libpayload/drivers/usb/ehci_rh.c | 28 +++++++++++----------------- 1 files changed, 11 insertions(+), 17 deletions(-) diff --git a/payloads/libpayload/drivers/usb/ehci_rh.c b/payloads/libpayload/drivers/usb/ehci_rh.c index 1d41f3f..dd073a3 100644 --- a/payloads/libpayload/drivers/usb/ehci_rh.c +++ b/payloads/libpayload/drivers/usb/ehci_rh.c @@ -53,31 +53,28 @@ ehci_rh_destroy (usbdev_t *dev) static void ehci_rh_hand_over_port (usbdev_t *dev, int port) { - volatile portsc_t *p = &(RH_INST(dev)->ports[port]); - debug("giving up port %x, it's USB1\n", port+1); /* Lowspeed device. Hand over to companion */ - *p |= P_PORT_OWNER; - do {} while (!(*p & P_CONN_STATUS_CHANGE)); + RH_INST(dev)->ports[port] |= P_PORT_OWNER; + do {} while (!(RH_INST(dev)->ports[port] & P_CONN_STATUS_CHANGE)); /* RW/C register, so clear it by writing 1 */ - *p |= P_CONN_STATUS_CHANGE; + RH_INST(dev)->ports[port] |= P_CONN_STATUS_CHANGE; return; } static void ehci_rh_scanport (usbdev_t *dev, int port) { - volatile portsc_t *p = &(RH_INST(dev)->ports[port]); if (RH_INST(dev)->devices[port]!=-1) { debug("Unregister device at port %x\n", port+1); usb_detach_device(dev->controller, RH_INST(dev)->devices[port]); RH_INST(dev)->devices[port]=-1; } /* device connected, handle */ - if (*p & P_CURR_CONN_STATUS) { + if (RH_INST(dev)->ports[port] & P_CURR_CONN_STATUS) { mdelay(100); - if ((*p & P_LINE_STATUS) == P_LINE_STATUS_LOWSPEED) { + if ((RH_INST(dev)->ports[port] & P_LINE_STATUS) == P_LINE_STATUS_LOWSPEED) { ehci_rh_hand_over_port(dev, port); return; } @@ -85,17 +82,17 @@ ehci_rh_scanport (usbdev_t *dev, int port) /* Deassert enable, assert reset. These must change * atomically. */ - *p = (*p & ~P_PORT_ENABLE) | P_PORT_RESET; + RH_INST(dev)->ports[port] = (RH_INST(dev)->ports[port] & ~P_PORT_ENABLE) | P_PORT_RESET; /* Wait a bit while reset is active. */ mdelay(50); /* Deassert reset. */ - *p &= ~P_PORT_RESET; + RH_INST(dev)->ports[port] &= ~P_PORT_RESET; /* Wait for flag change to finish. The controller might take a while */ - while (*p & P_PORT_RESET) ; - if (!(*p & P_PORT_ENABLE)) { + while (RH_INST(dev)->ports[port] & P_PORT_RESET) ; + if (!(RH_INST(dev)->ports[port] & P_PORT_ENABLE)) { ehci_rh_hand_over_port(dev, port); return; } @@ -103,7 +100,7 @@ ehci_rh_scanport (usbdev_t *dev, int port) RH_INST(dev)->devices[port] = usb_attach_device(dev->controller, dev->address, port, 2); } /* RW/C register, so clear it by writing 1 */ - *p |= P_CONN_STATUS_CHANGE; + RH_INST(dev)->ports[port] |= P_CONN_STATUS_CHANGE; } static int @@ -130,8 +127,6 @@ void ehci_rh_init (usbdev_t *dev) { int i; - volatile portsc_t *p; - dev->destroy = ehci_rh_destroy; dev->poll = ehci_rh_poll; @@ -144,9 +139,8 @@ ehci_rh_init (usbdev_t *dev) RH_INST(dev)->devices = malloc(RH_INST(dev)->n_ports * sizeof(int)); for (i=0; i < RH_INST(dev)->n_ports; i++) { - p = &(RH_INST(dev)->ports[i]); RH_INST(dev)->devices[i] = -1; - *p |= P_PP; + RH_INST(dev)->ports[i] |= P_PP; ehci_rh_scanport(dev, i); }

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New patch to review for coreboot: 595df77 libpayload: Force checking all EHCI ports on power-on
by Patrick Georgi 31 Jan '12

31 Jan '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/594 -gerrit commit 595df777bfaf2fc07a394233a6e770737b78806e Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Tue Jan 31 14:42:47 2012 +0100 libpayload: Force checking all EHCI ports on power-on EHCI port status reporting isn't very consistent on power-on, so just looking for devices on all ports is the safest way to find everything. Change-Id: I26b4305016f0bed1d2c1b5cffc59d5813fa1cbbb Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> --- payloads/libpayload/drivers/usb/ehci_rh.c | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/payloads/libpayload/drivers/usb/ehci_rh.c b/payloads/libpayload/drivers/usb/ehci_rh.c index d9ba8e4..1d41f3f 100644 --- a/payloads/libpayload/drivers/usb/ehci_rh.c +++ b/payloads/libpayload/drivers/usb/ehci_rh.c @@ -147,6 +147,7 @@ ehci_rh_init (usbdev_t *dev) p = &(RH_INST(dev)->ports[i]); RH_INST(dev)->devices[i] = -1; *p |= P_PP; + ehci_rh_scanport(dev, i); } dev->address = 0;

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New patch to review for coreboot: d9c56fa libpayload: Fix EHCI driver
by Patrick Georgi 31 Jan '12

31 Jan '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/593 -gerrit commit d9c56faebed52ad5c583c6337d5b01d2c09ed9bd Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Tue Jan 31 14:37:59 2012 +0100 libpayload: Fix EHCI driver When converting EHCI to not use bitfields, two offsets were converted incorrectly. Change-Id: I0bb4bad0eee42e54ad4fd53d6c35b107e227c41a Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> --- payloads/libpayload/drivers/usb/ehci_private.h | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/payloads/libpayload/drivers/usb/ehci_private.h b/payloads/libpayload/drivers/usb/ehci_private.h index 22fd7b2..6fa5f03 100644 --- a/payloads/libpayload/drivers/usb/ehci_private.h +++ b/payloads/libpayload/drivers/usb/ehci_private.h @@ -81,8 +81,8 @@ typedef volatile struct { u32 alt_next_qtd; u32 token; #define QTD_STATUS_MASK 0xff -#define QTD_HALTED (1 << 14) -#define QTD_ACTIVE (1 << 15) +#define QTD_HALTED (1 << 6) +#define QTD_ACTIVE (1 << 7) #define QTD_PID_SHIFT 8 #define QTD_PID_MASK (3 << QTD_PID_SHIFT) #define QTD_CERR_SHIFT 10

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coreboot January 2012