coreboot July 2011

coreboot@coreboot.org

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244 discussions

Patch merged into master: 0cda4b8 libpayload: Provide atol(), malloc.h
by gerrit＠coreboot.org 07 Jul '11

07 Jul '11

the following patch was just integrated into master: commit 0cda4b86f6b9aa1dd8acdd733bca92d801627717 Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Fri May 27 15:31:52 2011 +0200 libpayload: Provide atol(), malloc.h Change-Id: I807ca061115146a6851eef481eb881b279fba8e1 Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> See http://review.coreboot.org/86 for details. -gerrit

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Patch merged into master: 8f68886 libpayload: Implement strlcpy
by gerrit＠coreboot.org 07 Jul '11

07 Jul '11

the following patch was just integrated into master: commit 8f688867d3237a6aa78cb1afa4d9ab4747b49275 Author: Patrick Georgi <Patrick.Georgi(a)secunet.com> Date: Fri Mar 11 09:34:23 2011 +0100 libpayload: Implement strlcpy Change-Id: Ibd339957690afe2cded46895c3088eba87f0ffd1 Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> See http://review.coreboot.org/85 for details. -gerrit

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Patch merged into master: f3a72e8 libpayload: fix wborder()
by gerrit＠coreboot.org 07 Jul '11

07 Jul '11

the following patch was just integrated into master: commit f3a72e8244185a3d9226febac68739e11bb3a350 Author: Patrick Georgi <Patrick.Georgi(a)secunet.com> Date: Tue Mar 15 12:34:04 2011 +0100 libpayload: fix wborder() wborder didn't provide default characters to draw a border. Change-Id: Ib746ed16be341598fd9fa1f1b7577606d1abd9e5 Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> See http://review.coreboot.org/84 for details. -gerrit

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SPI flashing
by Andreas Galauner 07 Jul '11

07 Jul '11

Hello again, as you may have read yesterday, I'm currently trying to play with some in-system SPI flashing and I need some additional advice. I just soldered a Pinheader to an Intel D525MW Motherboard (http://www.dont.ru/i/img_1orig/129310882576.jpg - lower right corner) I'm currently not using, but I'm not sure if I should really connect some hardware to it and pull/push on the SPI lines. I suppose it's generally a bad idea to do this, when the Board is currently operating. If it is completely off, I can supply external power and just flash, right? And what about the reset state? I don't have any schematics of my motherboards, so I don't know if there are pull-up or pull-down resistors, I don't know if the chipset really switches its SPI lines into a Z-state, if it is held in reset and so on. I don't want to let the magic smoke escape from my motherboard ;) The only thing I found out is, that the HOLD# ("pauses" the flash chip) and WP# are connected to VCC over a 150 Ohm resistor, each. 150 Ohm is too low for a pull-up, so these two seem to be for limiting the current. Also the pinout is kind of "weird": 1 #CS 2 #CS 3 SI 4 NC 5 SO 6 VCC 7 SCK 8 GND Why is CS# connected to two pins? The resistance between those two pins is 1 Ohm, so they are connected directly. Interestingly the are connected through a 0 Ohm resistor. Any ideas on that? Are there some kind of "best practices" the vendors have when designing those in-system-SPI-flashing-headers? I mean they have to flash these boards in some way by themselves without sending them to heaven, if there is an SPI header. Any advice is greatly appreciated. Thanks, Andreas

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Re: [coreboot] SPI flashing
by Andreas Galauner 07 Jul '11

07 Jul '11

On 7/7/11 2:53 PM, Corey Osgood wrote: > On my NM10 board, I looked into in-system programming, but Carl-Daniel > convinced me that there was too much that could go wrong. Well, I just read the Chip identification in-system with my bus pirate: SPI> [0x9f,r,r,r] /CS ENABLED WRITE: 0x9F READ: 0xFF READ: 0xC2 READ: 0x20 /CS DISABLED Looks good so far and the board isn't fried ;) It works while the board is in standby. I'm driving the pins directly with 3,3V and GND. No open-drain or something. I saw on the oscilloscope that, when using open-drain mode, the SCK line floats. So, there doesn't seem to be an external pull-down/-up resistor and the internal seems to be deactivated. The only weird thing is that I need to read 3 Bytes and not 2 as stated in the datasheet of the SPI flash, but I don't care about that right now. Also flashrom doesn't work with the buspirate. I'll have to look into this. > BTW, just curious, have you had any luck getting the datasheets from > Intel that cover memory init? Or did you even bother trying? No, the flashing is the first thing I'm doing with this board, sorry. -Andreas

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Patch merged into master: fc9dd35 Fix lint-002-build-dir-handling
by gerrit＠coreboot.org 07 Jul '11

07 Jul '11

the following patch was just integrated into master: commit fc9dd354ea48dfe132326f0b9d6ebece3c021bb8 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sat Jul 2 16:21:31 2011 +0200 Fix lint-002-build-dir-handling That lint test requires some Kconfig defaults and uses allyesconfig for that. Unfortunately that also draws in ccache and scanbuild support, which significantly change the behaviour of the toplevel Makefile. Notably, the ccache support breaks if no ccache is installed. Change-Id: I17cbb7974be33fc077e5cbd5fb616a5b00a47d97 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/80 for details. -gerrit

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Patch merged into master: 87c40a8 T60: handle EC events in SMM if ACPI is disabled
by gerrit＠coreboot.org 07 Jul '11

07 Jul '11

the following patch was just integrated into master: commit 87c40a816d41d4953c093decd8ac137235919226 Author: Sven Schnelle <svens(a)stackframe.org> Date: Thu Jun 23 19:12:25 2011 +0200 T60: handle EC events in SMM if ACPI is disabled Change-Id: I6f9e90015cafef3da896453ef8e3588434ae3554 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> See http://review.coreboot.org/89 for details. -gerrit

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New patch to review: 87c40a8 T60: handle EC events in SMM if ACPI is disabled
by Sven Schnelle 07 Jul '11

07 Jul '11

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/89 -gerrit commit 87c40a816d41d4953c093decd8ac137235919226 Author: Sven Schnelle <svens(a)stackframe.org> Date: Thu Jun 23 19:12:25 2011 +0200 T60: handle EC events in SMM if ACPI is disabled Change-Id: I6f9e90015cafef3da896453ef8e3588434ae3554 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/mainboard/lenovo/t60/acpi/video.asl | 4 + src/mainboard/lenovo/t60/devicetree.cb | 1 + src/mainboard/lenovo/t60/mainboard.c | 3 +- src/mainboard/lenovo/t60/mainboard_smi.c | 119 +++++++++++++++++++++++++++++- src/mainboard/lenovo/t60/smi.h | 2 + 5 files changed, 126 insertions(+), 3 deletions(-) diff --git a/src/mainboard/lenovo/t60/acpi/video.asl b/src/mainboard/lenovo/t60/acpi/video.asl index c2f9dfb..9a458e9 100644 --- a/src/mainboard/lenovo/t60/acpi/video.asl +++ b/src/mainboard/lenovo/t60/acpi/video.asl @@ -19,6 +19,8 @@ * MA 02110-1301 USA */ +#include "smi.h" + Device (DSPC) { Name (_ADR, 0x00020001) @@ -31,6 +33,7 @@ Device (DSPC) Method(BRTD, 0, NotSerialized) { + Trap(SMI_BRIGHTNESS_DOWN) Store(BRTC, Local0) if (LGreater (Local0, 15)) { @@ -41,6 +44,7 @@ Device (DSPC) Method(BRTU, 0, NotSerialized) { + Trap(SMI_BRIGHTNESS_UP) Store (BRTC, Local0) if (LLess(Local0, 0xff)) { diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb index 9d7a414..3615e59 100644 --- a/src/mainboard/lenovo/t60/devicetree.cb +++ b/src/mainboard/lenovo/t60/devicetree.cb @@ -66,6 +66,7 @@ chip northbridge/intel/i945 register "sata_ahci" = "0x0" register "gpe0_en" = "0x11000006" + register "alt_gp_smi_en" = "0x1000" device pci 1b.0 on # Audio Cnotroller subsystemid 0x17aa 0x2010 diff --git a/src/mainboard/lenovo/t60/mainboard.c b/src/mainboard/lenovo/t60/mainboard.c index 371085b..2b8c5fe 100644 --- a/src/mainboard/lenovo/t60/mainboard.c +++ b/src/mainboard/lenovo/t60/mainboard.c @@ -61,7 +61,8 @@ static void mainboard_enable(device_t dev) } /* set dock status led */ - ec_write(0x0c, inb(0x164c) & 8 ? 0x88 : 0x08); + ec_write(0x0c, 0x08); + ec_write(0x0c, inb(0x164c) & 8 ? 0x89 : 0x09); if (get_option(&defaults_loaded, "cmos_defaults_loaded") < 0) { printk(BIOS_INFO, "failed to get cmos_defaults_loaded"); diff --git a/src/mainboard/lenovo/t60/mainboard_smi.c b/src/mainboard/lenovo/t60/mainboard_smi.c index 30c2420..4a0b506 100644 --- a/src/mainboard/lenovo/t60/mainboard_smi.c +++ b/src/mainboard/lenovo/t60/mainboard_smi.c @@ -24,10 +24,12 @@ #include <console/console.h> #include <cpu/x86/smm.h> #include "southbridge/intel/i82801gx/nvs.h" +#include "southbridge/intel/i82801gx/i82801gx.h" #include <ec/acpi/ec.h> #include "dock.h" #include "smi.h" +#define LVTMA_BL_MOD_LEVEL 0x7af9 /* ATI Radeon backlight level */ /* The southbridge SMI handler checks whether gnvs has a * valid pointer before calling the trap handler */ @@ -38,7 +40,28 @@ static void mainboard_smm_init(void) printk(BIOS_DEBUG, "initializing SMI\n"); /* Enable 0x1600/0x1600 register pair */ ec_set_bit(0x00, 0x05); - ec_set_ports(0x1604, 0x1600); +} + +static void mainboard_smi_brightness_down(void) +{ + u8 *bar; + if ((bar = (u8 *)pci_read_config32(PCI_DEV(1, 0, 0), 0x18))) { + printk(BIOS_DEBUG, "bar: %08X, level %02X\n", (unsigned int)bar, *(bar+LVTMA_BL_MOD_LEVEL)); + *(bar+LVTMA_BL_MOD_LEVEL) &= 0xf0; + if (*(bar+LVTMA_BL_MOD_LEVEL) > 0x10) + *(bar+LVTMA_BL_MOD_LEVEL) -= 0x10; + } +} + +static void mainboard_smi_brightness_up(void) +{ + u8 *bar; + if ((bar = (u8 *)pci_read_config32(PCI_DEV(1, 0, 0), 0x18))) { + printk(BIOS_DEBUG, "bar: %08X, level %02X\n", (unsigned int )bar, *(bar+LVTMA_BL_MOD_LEVEL)); + *(bar+LVTMA_BL_MOD_LEVEL) |= 0x0f; + if (*(bar+LVTMA_BL_MOD_LEVEL) < 0xf0) + *(bar+LVTMA_BL_MOD_LEVEL) += 0x10; + } } int mainboard_io_trap_handler(int smif) @@ -55,18 +78,29 @@ int mainboard_io_trap_handler(int smif) dlpc_init(); if (!dock_connect()) { /* set dock LED to indicate status */ - ec_write(0x0c, 0x88); + ec_write(0x0c, 0x08); + ec_write(0x0c, 0x89); } else { /* blink dock LED to indicate failure */ ec_write(0x0c, 0xc8); + ec_write(0x0c, 0x09); } break; case SMI_DOCK_DISCONNECT: dock_disconnect(); + ec_write(0x0c, 0x09); ec_write(0x0c, 0x08); break; + case SMI_BRIGHTNESS_UP: + mainboard_smi_brightness_up(); + break; + + case SMI_BRIGHTNESS_DOWN: + mainboard_smi_brightness_down(); + break; + default: return 0; } @@ -76,3 +110,84 @@ int mainboard_io_trap_handler(int smif) return 1; } +static void mainboard_smi_handle_ec_sci(void) +{ + u8 status = inb(EC_SC); + u8 event; + + if (!(status & EC_SCI_EVT)) + return; + + event = ec_query(); + printk(BIOS_DEBUG, "EC event %02x\n", event); + + switch(event) { + /* brightness up */ + case 0x14: + mainboard_smi_brightness_up(); + break; + /* brightness down */ + case 0x15: + mainboard_smi_brightness_down(); + break; + /* Fn-F9 Key */ + case 0x18: + /* power loss */ + case 0x27: + /* undock event */ + case 0x50: + mainboard_io_trap_handler(SMI_DOCK_DISCONNECT); + break; + /* dock event */ + case 0x37: + mainboard_io_trap_handler(SMI_DOCK_CONNECT); + break; + default: + break; + } +} + +void mainboard_smi_gpi(u16 gpi) +{ + if (gpi & (1 << 12)) + mainboard_smi_handle_ec_sci(); +} + +int mainboard_apm_cnt(u8 data) +{ + u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; + u8 tmp; + + printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase, data); + + if (!pmbase) + return 0; + + switch(data) { + case APM_CNT_ACPI_ENABLE: + /* use 0x1600/0x1604 to prevent races with userspace */ + ec_set_ports(0x1604, 0x1600); + /* route H8SCI to SCI */ + outw(inw(ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN); + tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); + tmp &= ~0x03; + tmp |= 0x02; + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + break; + case APM_CNT_ACPI_DISABLE: + /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't + provide a EC query function */ + ec_set_ports(0x66, 0x62); + /* route H8SCI# to SMI */ + outw(inw(pmbase + ALT_GP_SMI_EN) | 0x1000, pmbase + ALT_GP_SMI_EN); + tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); + tmp &= ~0x03; + tmp |= 0x01; + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + break; + default: + break; + } + return 0; +} + diff --git a/src/mainboard/lenovo/t60/smi.h b/src/mainboard/lenovo/t60/smi.h index f89b6bd..f8e8a7c 100644 --- a/src/mainboard/lenovo/t60/smi.h +++ b/src/mainboard/lenovo/t60/smi.h @@ -22,5 +22,7 @@ #define SMI_DOCK_CONNECT 0x01 #define SMI_DOCK_DISCONNECT 0x02 +#define SMI_BRIGHTNESS_UP 0x03 +#define SMI_BRIGHTNESS_DOWN 0x04 #endif

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Patch merged into master: 1bab8b9 Run 'git fetch' in SeaBIOS only when really needed
by gerrit＠coreboot.org 07 Jul '11

07 Jul '11

the following patch was just integrated into master: commit 1bab8b961b845ea1c6a3d9074bc5474675579101 Author: Cristian Măgherușan-Stanciu <cristi.magherusan(a)gmail.com> Date: Tue Jun 7 15:03:14 2011 +0200 Run 'git fetch' in SeaBIOS only when really needed This allows coreboot to compile without Internet connectivity Change-Id: I969471e44e417f127fdc8744e868211500acee3e Signed-off-by: Cristian Măgherușan-Stanciu <cristi.magherusan(a)gmail.com> See http://review.coreboot.org/11 for details. -gerrit

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New patch to review: f530383 libpayload: Add qsort()
by Patrick Georgi 07 Jul '11

07 Jul '11

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/88 -gerrit commit f53038334f203008b625669404794bbaa4dd9d8e Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Thu Jul 7 12:02:10 2011 +0200 libpayload: Add qsort() It's taken from OpenBSD and thus appropriately licensed (and reasonably tested). Change-Id: I5767600c9865d39e56c220b52e045f3501875b98 Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> --- payloads/libpayload/include/stdlib.h | 2 + payloads/libpayload/libc/Makefile.inc | 1 + payloads/libpayload/libc/qsort.c | 162 +++++++++++++++++++++++++++++++++ 3 files changed, 165 insertions(+), 0 deletions(-) diff --git a/payloads/libpayload/include/stdlib.h b/payloads/libpayload/include/stdlib.h index 6fb73ad..52162fe 100644 --- a/payloads/libpayload/include/stdlib.h +++ b/payloads/libpayload/include/stdlib.h @@ -142,4 +142,6 @@ void exit(int status) __attribute__ ((noreturn)); /** @} */ +void qsort(void *aa, size_t n, size_t es, int (*cmp)(const void *, const void *)); + #endif diff --git a/payloads/libpayload/libc/Makefile.inc b/payloads/libpayload/libc/Makefile.inc index e5c626f..0dab8c1 100644 --- a/payloads/libpayload/libc/Makefile.inc +++ b/payloads/libpayload/libc/Makefile.inc @@ -34,6 +34,7 @@ libc-$(CONFIG_LIBC) += rand.c time.c exec.c libc-$(CONFIG_LIBC) += readline.c getopt_long.c sysinfo.c libc-$(CONFIG_LIBC) += args.c strings.c libc-$(CONFIG_LIBC) += strlcpy.c +libc-$(CONFIG_LIBC) += qsort.c # should be moved to coreboot directory libc-$(CONFIG_LAR) += lar.c diff --git a/payloads/libpayload/libc/qsort.c b/payloads/libpayload/libc/qsort.c new file mode 100644 index 0000000..f28449f --- /dev/null +++ b/payloads/libpayload/libc/qsort.c @@ -0,0 +1,162 @@ +/* $OpenBSD: qsort.c,v 1.11 2010/02/08 11:04:07 otto Exp $ */ +/*- + * Copyright (c) 1992, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <sys/types.h> +#include <stdlib.h> + +static __inline char *med3(char *, char *, char *, int (*)(const void *, const void *)); +static __inline void swapfunc(char *, char *, size_t, int); + +#define min(a, b) (a) < (b) ? a : b + +/* + * Qsort routine from Bentley & McIlroy's "Engineering a Sort Function". + */ +#define swapcode(TYPE, parmi, parmj, n) { \ + size_t i = (n) / sizeof (TYPE); \ + TYPE *pi = (TYPE *) (parmi); \ + TYPE *pj = (TYPE *) (parmj); \ + do { \ + TYPE t = *pi; \ + *pi++ = *pj; \ + *pj++ = t; \ + } while (--i > 0); \ +} + +#define SWAPINIT(a, es) swaptype = ((char *)a - (char *)0) % sizeof(long) || \ + es % sizeof(long) ? 2 : es == sizeof(long)? 0 : 1; + +static __inline void +swapfunc(char *a, char *b, size_t n, int swaptype) +{ + if (swaptype <= 1) + swapcode(long, a, b, n) + else + swapcode(char, a, b, n) +} + +#define swap(a, b) \ + if (swaptype == 0) { \ + long t = *(long *)(a); \ + *(long *)(a) = *(long *)(b); \ + *(long *)(b) = t; \ + } else \ + swapfunc(a, b, es, swaptype) + +#define vecswap(a, b, n) if ((n) > 0) swapfunc(a, b, n, swaptype) + +static __inline char * +med3(char *a, char *b, char *c, int (*cmp)(const void *, const void *)) +{ + return cmp(a, b) < 0 ? + (cmp(b, c) < 0 ? b : (cmp(a, c) < 0 ? c : a )) + :(cmp(b, c) > 0 ? b : (cmp(a, c) < 0 ? a : c )); +} + +void +qsort(void *aa, size_t n, size_t es, int (*cmp)(const void *, const void *)) +{ + char *pa, *pb, *pc, *pd, *pl, *pm, *pn; + int cmp_result, swaptype, swap_cnt; + size_t d, r; + char *a = aa; + +loop: SWAPINIT(a, es); + swap_cnt = 0; + if (n < 7) { + for (pm = (char *)a + es; pm < (char *) a + n * es; pm += es) + for (pl = pm; pl > (char *) a && cmp(pl - es, pl) > 0; + pl -= es) + swap(pl, pl - es); + return; + } + pm = (char *)a + (n / 2) * es; + if (n > 7) { + pl = (char *)a; + pn = (char *)a + (n - 1) * es; + if (n > 40) { + d = (n / 8) * es; + pl = med3(pl, pl + d, pl + 2 * d, cmp); + pm = med3(pm - d, pm, pm + d, cmp); + pn = med3(pn - 2 * d, pn - d, pn, cmp); + } + pm = med3(pl, pm, pn, cmp); + } + swap(a, pm); + pa = pb = (char *)a + es; + + pc = pd = (char *)a + (n - 1) * es; + for (;;) { + while (pb <= pc && (cmp_result = cmp(pb, a)) <= 0) { + if (cmp_result == 0) { + swap_cnt = 1; + swap(pa, pb); + pa += es; + } + pb += es; + } + while (pb <= pc && (cmp_result = cmp(pc, a)) >= 0) { + if (cmp_result == 0) { + swap_cnt = 1; + swap(pc, pd); + pd -= es; + } + pc -= es; + } + if (pb > pc) + break; + swap(pb, pc); + swap_cnt = 1; + pb += es; + pc -= es; + } + if (swap_cnt == 0) { /* Switch to insertion sort */ + for (pm = (char *) a + es; pm < (char *) a + n * es; pm += es) + for (pl = pm; pl > (char *) a && cmp(pl - es, pl) > 0; + pl -= es) + swap(pl, pl - es); + return; + } + + pn = (char *)a + n * es; + r = min(pa - (char *)a, pb - pa); + vecswap(a, pb - r, r); + r = min(pd - pc, pn - pd - es); + vecswap(pb, pn - r, r); + if ((r = pb - pa) > es) + qsort(a, r / es, es, cmp); + if ((r = pd - pc) > es) { + /* Iterate rather than recurse to save stack space */ + a = pn - r; + n = r / es; + goto loop; + } +/* qsort(pn - r, r / es, es, cmp);*/ +}

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coreboot July 2011