the following patch was just integrated into master:
Author: Patrick Georgi <patrick(a)georgi-clan.de>
Date: Thu Jun 30 15:48:57 2011 +0200
Relicense Makefile to match libpayload
libpayload's license is more liberal than coreboot's. If we are to
use the coreboot build system for libpayload (bringing a couple of
new features to libpayload), we should adopt it for this shared part
even if not strictly necessary.
Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de>
See http://review.coreboot.org/70 for details.
Cristian Măgherușan-Stanciu (cristi.magherusan(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/69
Author: Rudolf Marek <r.marek(a)assembler.cz>
Date: Wed Jun 29 23:59:13 2011 +0200
Workaround the errata #181.
We use LDTSTOP# to trigger the FID/VID change on K8M890, because the
FID/VID SMAF is blocked by not yet configured internal VGA.
The memory controller is enabled later, nor the workaround makes any
harm to non-affected CPUs.
This update unbreaks compilation by declaring the tmp variable.
Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz>
Signed-off-by: Cristian Măgherușan-Stanciu <cristi.magherusan(a)gmail.com>
src/mainboard/asus/m2v-mx_se/romstage.c | 7 ++++++-
1 files changed, 6 insertions(+), 1 deletions(-)
diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c
index 580d8fa..9825e2b 100644
@@ -74,10 +74,15 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#define SB_VFSMAF 0
-/* this function might fail on some K8 CPUs with errata #181 */
static void ldtstop_sb(void)
+ /* fix errata #181, disable DRAM controller it will get enabled later */
+ u8 tmp = pci_read_config8(PCI_DEV(0, 0x18, 2), 0x94);
+ tmp |= (( 1 << 14) | (1 << 3));
+ pci_write_config8(PCI_DEV(0, 0x18, 2), 0x94, tmp);
u8 reg = inb (VT8237R_ACPI_IO_BASE + 0x5c);
reg = reg ^ (1 << 0);
outb(reg, VT8237R_ACPI_IO_BASE + 0x5c);
Since it is too hard to get the detail information of Marvell CPU (
most of the information is covered under an NDA) , I decided to work
on porting coreboot to Armltd Versatile PB. Most of its information is
on the web of ARM ltd. and QEMU can emulate it so it is easy for me to
test and use it.
After applying those patches, we can now create a rom file only with
bootblock. There is one problem when we add romstage to this rom file,
I am trying to resolve this problem with the help of Patrick. Since no
romstage and ramstage is in this rom file, no information will print
to the screen. You can use the built-in gdb server in QEMU to trace
the work of bootblock and walkcbfs.
It is under vendor "Armltd" and mainboard "Versatile PB". Please test
it and any comments are welcome.
Thanks to you all for your kindly help.