This patch series enables SeaBIOS to pull common config settings from
CBFS (on coreboot) or fw_cfg (on QEmu). The series also converts
several compile-time settings to this new dynamic system.
I choose to place the file names in the "etc/" directory so that it is
clear they are configuration settings.
On coreboot, a user would do the following to enable a setting:
/path/to/seabios/tools/encodeint.py boot-menu-wait 5500
./build/cbfstool coreboot.rom add boot-menu-wait etc/boot-menu-wait raw
./build/cbfstool coreboot.rom print
See the patch descriptions below for the six compile-time settings
that are converted.
Kevin O'Connor (8):
Add "romfile" code to assist with extract integer config settings.
Replace CONFIG_BOOTMENU_WAIT with dynamic "etc/boot-menu-wait" file.
Replace CONFIG_EXTRA_PCI_ROOTS with dynamic "etc/extra-pci-roots"
Replace CONFIG_PS2_KEYBOARD_SPINUP with "etc/ps2-keyboard-spinup"
Replace "CONFIG_OPTIONROMS_CHECKSUM" with "etc/optionroms-checksum"
Replace CONFIG_S3_RESUME_VGA_INIT with "etc/s3-resume-vga-init" file.
Replace CONFIG_SCREEN_AND_DEBUG with "etc/screen-and-debug" file.
Add utility "tools/encodeint.py" for CBFS config file creation.
src/Kconfig | 50 --------------------------------------------------
src/boot.c | 5 ++++-
src/optionroms.c | 14 ++++++++++++--
src/output.c | 4 ++--
src/paravirt.c | 19 +++++++++++++++++++
src/paravirt.h | 2 ++
src/pci.c | 8 ++++----
src/ps2port.c | 6 ++++--
src/util.h | 1 +
tools/encodeint.py | 21 +++++++++++++++++++++
10 files changed, 69 insertions(+), 61 deletions(-)
create mode 100755 tools/encodeint.py
Here is a PoC of NULL pointer dereference checking in coreboot x86. It is
surprisingly easy to implement.
It uses strange expand down segments, making a data segment from 4KB-4GB (with
base 0). It should catch most NULL derefence symbols. Unfortunately we access
0x500 while placing the coreboot tables. The hack in the patch just swaps the ds
selector work arounding that.
More advanced method would use paging and PAE, first 4MB with 4KB pages rest
with 4MB pages identity mapped. We could even mark other than coreboot RAM range
as "missing" allowing more fine grained tests what is where accessed.
Even the segment hack above could be used to check the stack overflows, but I
think we will need in IDT instead of interrupt gate a task gate and set there a
exception stack, otherwise it will end very badly while CPU is trying to safe
stack yet again during the exception.
PS: Qemu does not implement segment limit checking, so just try on real HW. Dont
forget to switch off GDB debugging otherwise you wont get human readable
exception notice, on the other hand you can try to debug that ;)
I recently started to discover this great project you have here.
I want to play with it a bit and port it to an AMD E-350 Motherboard
(Sapphire Pure Fusion Mini E-350 - what a name...) I have at home in my
Now I don't think that the development work is much fun, when you have
to take the SPI chip off the motherboard, program it, put it back into
the board, see the code failing and repeat the whole process ;)
So, I had the idea of developing a small Board which contains a USB port
and an SPI flash.
I first thought about emulating the SPI flash completely by an AVR, but
I think the clock rates of the SPI bus are too high to do this. My new
approach is a SPI flash which resides on the AVR board which can be
multiplexed between the AVR to program it and the motherboard.
If I want to test a new BIOS, the AVR puts the motherboard into reset,
detaches the flash chip with a multiplexer from the motherboard,
programs it, switches it back to the motherboard and let off the reset.
Rapid BIOS development :)
As an added bonus, I'm thinking about using a USB 2.0 port of an
USB-capable AVR as a USB debug interface (those USB debugging cables are
expensive for a poor student ;) ) and add a second USB 1.1 port with a
MAX3420 for host-communication, but that's step 2.
I know that I won't get the full 480MBit/s with this, but I think I can
live with that.
As I am currently looking for suitable parts, I need to know some basic
parameters of the SPI communication.
Does anybody of you know what the typical clock rates between the
chipset and the flash are?
Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/86
Author: Patrick Georgi <patrick.georgi(a)secunet.com>
Date: Fri May 27 15:31:52 2011 +0200
libpayload: Provide atol(), malloc.h
Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com>
payloads/libpayload/include/malloc.h | 1 +
payloads/libpayload/include/stdlib.h | 1 +
payloads/libpayload/libc/string.c | 5 +++++
3 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/payloads/libpayload/include/malloc.h b/payloads/libpayload/include/malloc.h
new file mode 100644
@@ -0,0 +1 @@
diff --git a/payloads/libpayload/include/stdlib.h b/payloads/libpayload/include/stdlib.h
index a106607..6fb73ad 100644
@@ -120,6 +120,7 @@ void *memalign(size_t align, size_t size);
long int strtol(const char *s, char **nptr, int base);
unsigned long int strtoul(const char *s, char **nptr, int base);
+long atol(const char *nptr);
/** @} */
diff --git a/payloads/libpayload/libc/string.c b/payloads/libpayload/libc/string.c
index 2e0a558..8c6ea99 100644
@@ -473,6 +473,11 @@ long int strtol(const char *ptr, char **endptr, int base)
return ret * negative;
+long atol(const char *nptr)
+ return strtol(nptr, NULL, 10);
* Convert the initial portion of a string into an unsigned int
* @param ptr A pointer to the string to convert
This is for testing/developing purpose, not for merging.
SerialICE in coreboot would be great for developing at least CPUs cache init code.
This strategy makes use of early serial functions directly from coreboot tree.
This is with example for one board (copy from romstage early serial code for your board).
Comments are welcome!
SerialICE files, receive function for romcc_console, bootblock_simple example
src/arch/x86/SerialICE/io.h | 195 ++++++++++++++++++++++++
src/arch/x86/SerialICE/serial.c | 190 ++++++++++++++++++++++++
src/arch/x86/SerialICE/serialice.c | 272 ++++++++++++++++++++++++++++++++++
src/arch/x86/init/bootblock_simple.c | 2 +
src/arch/x86/lib/romcc_console.c | 7 +
5 files changed, 666 insertions(+), 0 deletions(-)
create mode 100644 src/arch/x86/SerialICE/io.h
create mode 100644 src/arch/x86/SerialICE/serial.c
create mode 100644 src/arch/x86/SerialICE/serialice.c