coreboot July 2011

coreboot@coreboot.org

52 participants
244 discussions

New patch to review: 67576b4 ASRock E350M1: ACPI-related BSOD fix
by Marshall Buschman 10 Jul '11

10 Jul '11

Marshall Buschman (mbuschman(a)lucidmachines.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/91 -gerrit commit 67576b4126a4c5be0df8236601ad0728fc1b24fd Author: Scott Duplichan <scott(a)notabs.org> Date: Sat Jul 9 20:14:20 2011 -0500 ASRock E350M1: ACPI-related BSOD fix On installing/starting Windows (tested with Win7 Ultimate) the system crashes with a Blue Screen of Death, reporting an ACPI BIOS error. From Scott Duplichan: To avoid the Windows BSOD, the uninitialized value TOM1 in the SSDT must be corrected. The attached patch does this. It uses the older patching method, and not the (possibly preferred) AML generation method. To simplify the patching operation, I moved the AML item 'TOM1' to the start of the SSDT. The patch also includes code to confirm the AML variable TOM1 is at the expected offset before patching. Also tested & working with Linux. Change-Id: I59cedc366e09d98f690b093d6a21fc0c864559c3 Signed-off-by: Scott Duplichan <scott(a)notabs.org> Acked-by: Marshall Buschman <mbuschman(a)lucidmachines.com> --- src/mainboard/asrock/e350m1/acpi_tables.c | 5 +++++ src/northbridge/amd/agesa/family14/ssdt.asl | 2 +- 2 files changed, 6 insertions(+), 1 deletions(-) diff --git a/src/mainboard/asrock/e350m1/acpi_tables.c b/src/mainboard/asrock/e350m1/acpi_tables.c index 20b0dc2..cd0a996 100644 --- a/src/mainboard/asrock/e350m1/acpi_tables.c +++ b/src/mainboard/asrock/e350m1/acpi_tables.c @@ -185,6 +185,11 @@ unsigned long write_acpi_tables(unsigned long start) memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t)); current += ssdt->length; memcpy(ssdt, &AmlCode_ssdt, ssdt->length); + + char *position = ssdt; + if (memcmp (position + 50, "TOM1", 4) == 0) + *(u32 *) (position + 55) = __readmsr (0xc001001a); + /* recalculate checksum */ ssdt->checksum = 0; ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length); diff --git a/src/northbridge/amd/agesa/family14/ssdt.asl b/src/northbridge/amd/agesa/family14/ssdt.asl index e69012b..1e694db 100644 --- a/src/northbridge/amd/agesa/family14/ssdt.asl +++ b/src/northbridge/amd/agesa/family14/ssdt.asl @@ -30,6 +30,7 @@ DefinitionBlock ("SSDT.aml", "SSDT", 1, "AMD-FAM14H", "AMD-ACPI", 0x1000) Scope (\_SB.PCI0) { + Name (TOM1, 0xaaaaaaaa) Name (BUSN, Package (0x20) /* HC_NUMS */ { 0x11111111, @@ -264,7 +265,6 @@ DefinitionBlock ("SSDT.aml", "SSDT", 1, "AMD-FAM14H", "AMD-ACPI", 0x1000) 0x44444444 }) Name (SBLK, 0x11) - Name (TOM1, 0xaaaaaaaa) Name (SBDN, 0xbbbbbbbb) Name (HCLK, Package (0x20) /* HC_POSSIBLE_NUM */ {

1 0

New patch to review: 5176106 Do full flush on uart8250 only at end of printk.
by Anonymous Coward 10 Jul '11

10 Jul '11

Anonymous Coward (kevin(a)koconnor.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/90 -gerrit commit 51761067ec0ded3b8fa73efffc1462f262a94759 Author: Kevin O'Connor <kevin(a)koconnor.net> Date: Sat Jul 9 20:22:21 2011 -0400 Do full flush on uart8250 only at end of printk. The previous code does a full flush of the uart after every character. Unfortunately, this can cause transmission delays on some serial ports. This patch changes the code so that it does a flush at the end of every printk instead of at the end of every character. This reduces the time it takes to transmit serial messages (up to 9% on my Asrock e350m1 board). It also makes the transmission time more consistent which is important when performing timing tests via serial transmissions. Change-Id: I6b28488b905da68c6d68d7c517cc743cde567d70 Signed-off-by: Kevin O'Connor <kevin(a)koconnor.net> --- src/arch/x86/lib/romstage_console.c | 16 +++++++++++++--- src/console/uart8250_console.c | 6 ++++++ src/include/uart8250.h | 1 + src/lib/uart8250.c | 5 ++++- 4 files changed, 24 insertions(+), 4 deletions(-) diff --git a/src/arch/x86/lib/romstage_console.c b/src/arch/x86/lib/romstage_console.c index a5f2e2b..faa8afb 100644 --- a/src/arch/x86/lib/romstage_console.c +++ b/src/arch/x86/lib/romstage_console.c @@ -48,6 +48,16 @@ static void console_tx_byte(unsigned char byte) #endif } +static void console_tx_flush(void) +{ +#if CONFIG_CONSOLE_SERIAL8250 + uart8250_tx_flush(CONFIG_TTYS0_BASE); +#endif +#if CONFIG_CONSOLE_NE2K + ne2k_transmit(CONFIG_CONSOLE_NE2K_IO_PORT); +#endif +} + int do_printk(int msg_level, const char *fmt, ...) { va_list args; @@ -60,8 +70,8 @@ int do_printk(int msg_level, const char *fmt, ...) va_start(args, fmt); i = vtxprintf(console_tx_byte, fmt, args); va_end(args); -#if CONFIG_CONSOLE_NE2K - ne2k_transmit(CONFIG_CONSOLE_NE2K_IO_PORT); -#endif + + console_tx_flush(); + return i; } diff --git a/src/console/uart8250_console.c b/src/console/uart8250_console.c index 4799ca6..330ed68 100644 --- a/src/console/uart8250_console.c +++ b/src/console/uart8250_console.c @@ -31,6 +31,11 @@ static void ttyS0_tx_byte(unsigned char data) uart8250_tx_byte(CONFIG_TTYS0_BASE, data); } +static void ttyS0_tx_flush(void) +{ + uart8250_tx_flush(CONFIG_TTYS0_BASE); +} + static unsigned char ttyS0_rx_byte(void) { return uart8250_rx_byte(CONFIG_TTYS0_BASE); @@ -44,6 +49,7 @@ static int ttyS0_tst_byte(void) static const struct console_driver uart8250_console __console = { .init = ttyS0_init, .tx_byte = ttyS0_tx_byte, + .tx_flush = ttyS0_tx_flush, .rx_byte = ttyS0_rx_byte, .tst_byte = ttyS0_tst_byte, }; diff --git a/src/include/uart8250.h b/src/include/uart8250.h index bbf2d8c..ee0cd39 100644 --- a/src/include/uart8250.h +++ b/src/include/uart8250.h @@ -131,6 +131,7 @@ unsigned char uart8250_rx_byte(unsigned base_port); int uart8250_can_rx_byte(unsigned base_port); void uart8250_tx_byte(unsigned base_port, unsigned char data); +void uart8250_tx_flush(unsigned base_port); /* Yes it is silly to have three different uart init functions. But we used to * have three different sets of uart code, so it's an improvement. diff --git a/src/lib/uart8250.c b/src/lib/uart8250.c index 64e8854..e7ddd0b 100644 --- a/src/lib/uart8250.c +++ b/src/lib/uart8250.c @@ -48,7 +48,10 @@ void uart8250_tx_byte(unsigned base_port, unsigned char data) { uart8250_wait_to_tx_byte(base_port); outb(data, base_port + UART_TBR); - /* Make certain the data clears the fifos */ +} + +void uart8250_tx_flush(unsigned base_port) +{ uart8250_wait_until_sent(base_port); }

1 0

PATCH: Missing bus address assignment
by Steven A. Falco 09 Jul '11

09 Jul '11

The EHCI controller does not set the bus_address field of the controller structure. Other controllers have this assignment, so let's be consistent. Signed-off-by: Steven A. Falco <sfalco(a)coincident.com> --- diff --git a/payloads/libpayload/drivers/usb/ehci.c b/payloads/libpayload/drivers/usb/ehci.c index 3df0477..d979121 100644 --- a/payloads/libpayload/drivers/usb/ehci.c +++ b/payloads/libpayload/drivers/usb/ehci.c @@ -336,6 +336,7 @@ ehci_init (pcidev_t addr) controller->create_intr_queue = ehci_create_intr_queue; controller->destroy_intr_queue = ehci_destroy_intr_queue; controller->poll_intr_queue = ehci_poll_intr_queue; + controller->bus_address = addr; for (i = 0; i < 128; i++) { controller->devices[i] = 0; }

1 0

PATCH: Warn about unknown USB devices
by Steven A. Falco 09 Jul '11

09 Jul '11

Print a warning regarding unknown USB controller devices. Signed-off-by: Steven A. Falco <sfalco(a)coincident.com> --- I have observed a device that claims a USB controller programming interface of 0xfe. I don't know what the device is, but it is helpful to see a warning. So I've changed the individual if() statements to a switch() and added a default case to spit out the warning. diff --git a/payloads/libpayload/drivers/usb/usbinit.c b/payloads/libpayload/drivers/usb/usbinit.c index f0d5a60..5c2eae6 100644 --- a/payloads/libpayload/drivers/usb/usbinit.c +++ b/payloads/libpayload/drivers/usb/usbinit.c @@ -70,40 +70,47 @@ usb_controller_initialize (int bus, int dev, int func) printf ("%02x:%02x.%x %04x:%04x.%d ", bus, dev, func, pciid >> 16, pciid & 0xFFFF, func); - if (prog_if == 0) { - printf ("UHCI controller\n"); + switch(prog_if) { + case 0x00: + printf ("UHCI controller\n"); #ifdef CONFIG_USB_UHCI - uhci_init (addr); + uhci_init (addr); #else - printf ("Not supported.\n"); + printf ("Not supported.\n"); #endif - } - if (prog_if == 0x10) { - printf ("OHCI controller\n"); + break; + + case 0x10: + printf ("OHCI controller\n"); #ifdef CONFIG_USB_OHCI - ohci_init(addr); + ohci_init(addr); #else - printf ("Not supported.\n"); + printf ("Not supported.\n"); #endif + break; - } - if (prog_if == 0x20) { - printf ("EHCI controller\n"); + case 0x20: + printf ("EHCI controller\n"); #ifdef CONFIG_USB_EHCI - ehci_init(addr); + ehci_init(addr); #else - printf ("Not supported.\n"); + printf ("Not supported.\n"); #endif + break; - } - if (prog_if == 0x30) { - printf ("xHCI controller\n"); + case 0x30: + printf ("xHCI controller\n"); #ifdef CONFIG_USB_XHCI - xhci_init(addr); + xhci_init(addr); #else - printf ("Not supported.\n"); + printf ("Not supported.\n"); #endif + break; + default: + printf ("unknown controller %x not supported\n", + prog_if); + break; } }

1 0

PATCH: Make EHCI root host accesses atomic
by Steven A. Falco 09 Jul '11

09 Jul '11

Some EHCI controllers misbehave if bits in the portsc register do not change atomically. Thus we use a temporary variable to do a single read-modify-write when changing related bits in the register. The symptom is an incorrect handoff from EHCI to OHCI. Signed-off-by: Steven A. Falco <sfalco(a)coincident.com> --- I've observed the problem with several EHCI controllers: an Intel Topcliff IOH and a Pericom PI7C9X440SL. With the changes below, both these controllers work properly. Note that several other registers in ehci_private.h are described in terms of separate bits too. I have not changed them because I have not observed any problems with them. diff --git a/payloads/libpayload/drivers/usb/ehci_private.h b/payloads/libpayload/drivers/usb/ehci_private.h index e63a81d..07c1a2f 100644 --- a/payloads/libpayload/drivers/usb/ehci_private.h +++ b/payloads/libpayload/drivers/usb/ehci_private.h @@ -37,8 +37,34 @@ #define FLADJ 0x61 #define FLADJ_framelength(x) (((x)-59488)/16) +#define PORT_WKOC_E (1<<22) +#define PORT_WKDISC_E (1<<21) +#define PORT_WKCONN_E (1<<20) +#define PORT_TEST_PKT (0x4<<16) +#define PORT_LED_OFF (0<<14) +#define PORT_LED_AMBER (1<<14) +#define PORT_LED_GREEN (2<<14) +#define PORT_LED_MASK (3<<14) +#define PORT_OWNER (1<<13) +#define PORT_POWER (1<<12) +#define PORT_LINESTATUS_MASK (3<<10) +#define PORT_LINESTATUS_KSTATE (1<<10) +#define PORT_RESET (1<<8) +#define PORT_SUSPEND (1<<7) +#define PORT_RESUME (1<<6) +#define PORT_OCC (1<<5) +#define PORT_OC (1<<4) +#define PORT_PEC (1<<3) +#define PORT_PE (1<<2) +#define PORT_CSC (1<<1) +#define PORT_CONNECT (1<<0) + typedef union { - u32 val; + volatile u32 val; + // WARNING - some controllers require port_enable and port_reset to + // change atomically. Therefore, using these separate bits is not + // recommended. +#if 0 volatile struct { unsigned long current_conn_status:1; unsigned long conn_status_change:1; @@ -60,6 +86,7 @@ typedef union { unsigned long wake_on_overcurrent_en:1; unsigned long:9; } __attribute__ ((packed)); +#endif } __attribute__ ((packed)) portsc_t; typedef struct { diff --git a/payloads/libpayload/drivers/usb/ehci_rh.c b/payloads/libpayload/drivers/usb/ehci_rh.c index 5eaeeb6..c588a3d 100644 --- a/payloads/libpayload/drivers/usb/ehci_rh.c +++ b/payloads/libpayload/drivers/usb/ehci_rh.c @@ -54,14 +54,19 @@ static void ehci_rh_hand_over_port (usbdev_t *dev, int port) { volatile portsc_t *p = &(RH_INST(dev)->ports[port]); + volatile u32 tmp; printf("giving up port %x, it's USB1\n", port+1); /* Lowspeed device. Hand over to companion */ - p->port_owner = 1; - do {} while (!p->conn_status_change); + tmp = p->val; + tmp |= PORT_OWNER; + p->val = tmp; + while (!(p->val & PORT_CSC)); /* RW/C register, so clear it by writing 1 */ - p->conn_status_change = 1; + tmp = p->val; + tmp |= PORT_CSC; + p->val = tmp; return; } @@ -69,41 +74,54 @@ static void ehci_rh_scanport (usbdev_t *dev, int port) { volatile portsc_t *p = &(RH_INST(dev)->ports[port]); + volatile u32 tmp; if (RH_INST(dev)->devices[port]!=-1) { printf("Unregister device at port %x\n", port+1); usb_detach_device(dev->controller, RH_INST(dev)->devices[port]); RH_INST(dev)->devices[port]=-1; } /* device connected, handle */ - if (p->current_conn_status) { + if (p->val & PORT_CONNECT) { mdelay(100); - if (p->line_status == 0x1) { + if ((p->val & PORT_LINESTATUS_MASK) == PORT_LINESTATUS_KSTATE) { ehci_rh_hand_over_port(dev, port); return; } - p->port_enable = 0; - p->port_reset = 1; + + /* Remove port_enable, set port_reset. This must be atomic. */ + tmp = p->val; + tmp &= ~PORT_PE; + tmp |= PORT_RESET; + p->val = tmp; + mdelay(50); - p->port_reset = 0; + tmp &= ~PORT_RESET; + p->val = tmp; + /* Wait for flag change to finish. The controller might take a while */ - while (p->port_reset) ; - if (!p->port_enable) { + while(p->val & PORT_RESET) ; + if (!(p->val & PORT_PE)) { ehci_rh_hand_over_port(dev, port); return; } printf("port %x hosts a USB2 device\n", port+1); RH_INST(dev)->devices[port] = usb_attach_device(dev->controller, dev->address, port, 2); } + /* RW/C register, so clear it by writing 1 */ - p->conn_status_change = 1; + tmp = p->val; + tmp |= PORT_CSC; + p->val = tmp; } static int ehci_rh_report_port_changes (usbdev_t *dev) { + volatile portsc_t *p; int i; for (i=0; i<RH_INST(dev)->n_ports; i++) { - if (RH_INST(dev)->ports[i].conn_status_change) + p = &(RH_INST(dev)->ports[i]); + if (p->val & PORT_CSC) return i; } return -1; @@ -121,6 +139,8 @@ ehci_rh_poll (usbdev_t *dev) void ehci_rh_init (usbdev_t *dev) { + volatile portsc_t *p; + volatile u32 tmp; int i; dev->destroy = ehci_rh_destroy; @@ -135,8 +155,11 @@ ehci_rh_init (usbdev_t *dev) RH_INST(dev)->devices = malloc(RH_INST(dev)->n_ports * sizeof(int)); for (i=0; i < RH_INST(dev)->n_ports; i++) { + p = &(RH_INST(dev)->ports[i]); + tmp = p->val; + tmp |= PORT_POWER; + p->val = tmp; RH_INST(dev)->devices[i] = -1; - RH_INST(dev)->ports[i].pp = 1; } dev->address = 0;

1 0

Question about USB support in libpayload / FILO
by Steven A. Falco 09 Jul '11

09 Jul '11

I am attempting to use FILO and libpayload with an Intel Atom E6XX processor; specifically, the Intel Tunnel Creek development kit. This is a SOC-type processor that has four integrated PCIe links, one of which goes to an Intel IOH (sort of a southbridge). The IOH in turn contains a USB host controller (EHCI/OHCI). Another of the PCIe links goes through a PCIe <-> PCI bridge to a standard PCI slot. Finally, the other two PCIe links go to standard PCIe slots. I want to boot Linux from a Sandisk USB stick, so I first tried inserting the stick into one of the IOH USB ports. When I do that, I get a message: giving up port 1, it's USB1 and FILO appears to hang. The next thing I tried was connecting a NEC USB host controller card to the PCI slot. That one works properly. The Sandisk stick is correctly recognized, and I get: port 2 hosts a USB2 device highspeed device device 0x0781:0x5530 is USB 2.0 (MSC) it uses SCSI transparent command set it uses Bulk-Only Transport protocol using endpoint 81 as in, 2 as out has 1 luns Waiting for device to become ready... ok. spin up. OK. Reading capacity of mass storage device. has 15625216 blocks sized 512b I've also tried connecting a Pericom USB host controller to one of the PCIe slots. It contains a Pericom PI7C9X440SL chip. It gives the same error behavior as does the IOH. So the FILO / libpayload tally at this point is: NEC host bridge works, IOH and Pericom don't. I've also tried an experiment where I boot Linux using the NEC controller, then plug a second Sandisk stick into the IOH controller. Linux has no problem using the IOH USB ports. Linux also has no problem using the Pericom USB ports. I'm trying to instrument the code in ehci_rh_scanport(). I added a number of printf messages. So far, I don't see the problem. Reading some of the port status bits gives me: port power 1, port enable 0, port reset 0, line status 2 The line status of 2 means this is an EHCI device and that an EHCI reset should be done. The code does that, but port_enable apparently stays at 0, which causes a call to ehci_rh_hand_over_port(). That routine prints the "giving up" message, and then the world ends. The one thing I noticed in the code that might be a problem is that bit-fields are used for things like port_enable and port_reset. So to reset the port, the code does: p->port_enable = 0; p->port_reset = 1; mdelay(50); p->port_reset = 0; That means that port_enable and port_reset won't change at the same moment, even though they are in the same register. In contrast, the Linux driver uses temporary variables, such that both bits will change in the same register access. I don't know if that is the problem, but it is one difference I noticed. The Linux code looks like this: } else { ehci_vdbg (ehci, "port %d reset\n", wIndex + 1); temp |= PORT_RESET; temp &= ~PORT_PE; /* * caller must wait, then call GetPortStatus * usb 2.0 spec says 50 ms resets on root */ ehci->reset_done [wIndex] = jiffies + msecs_to_jiffies (50); } ehci_writel(ehci, temp, status_reg); What have other folks experiences been with the EHCI driver in libpayload? Steve

2 1

Patch merged into master: ad3e986 Fix memory size reporting on AMD family 14h systems for >= 4GB
by gerrit＠coreboot.org 09 Jul '11

09 Jul '11

the following patch was just integrated into master: commit ad3e9864d761f3b4ab95447d3fbc313cec19306d Author: Cristian Măgherușan-Stanciu <cristi.magherusan(a)gmail.com> Date: Fri Jul 8 22:41:12 2011 +0000 Fix memory size reporting on AMD family 14h systems for >= 4GB Applying Scott Duplichan's fix for memory >=4GB Adjusted it to the new directory structure (agesa_wrapper was renamed to just agesa). Boot-tested and confirmed to work, on my board Linux can now access the whole RAM. Change-Id: I31d66a488a7811d214d84653860b3e0116f67d19 Signed-off-by: Scott Duplichan <scott(a)notabs.org> Acked-by: Marshall Buschman <mbuschman(a)lucidmachines.com> Signed-off-by: Cristian Măgherușan-Stanciu <cristi.magherusan(a)gmail.com> See http://review.coreboot.org/48 for details. -gerrit

1 0

Patch set updated: ad3e986 Fix memory size reporting on AMD family 14h systems for >= 4GB
by Cristian Măgherușan-Stanciu 09 Jul '11

09 Jul '11

Cristian Măgherușan-Stanciu (cristi.magherusan(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/48 -gerrit commit ad3e9864d761f3b4ab95447d3fbc313cec19306d Author: Cristian Măgherușan-Stanciu <cristi.magherusan(a)gmail.com> Date: Fri Jul 8 22:41:12 2011 +0000 Fix memory size reporting on AMD family 14h systems for >= 4GB Applying Scott Duplichan's fix for memory >=4GB Adjusted it to the new directory structure (agesa_wrapper was renamed to just agesa). Boot-tested and confirmed to work, on my board Linux can now access the whole RAM. Change-Id: I31d66a488a7811d214d84653860b3e0116f67d19 Signed-off-by: Scott Duplichan <scott(a)notabs.org> Acked-by: Marshall Buschman <mbuschman(a)lucidmachines.com> Signed-off-by: Cristian Măgherușan-Stanciu <cristi.magherusan(a)gmail.com> --- src/northbridge/amd/agesa/family14/northbridge.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index 78ba2da..e38500d 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -652,8 +652,8 @@ printk(BIOS_DEBUG, "adsr - CONFIG_PCI_64BIT_PREF_MEM is true.\n"); d = get_dram_base_mask(0); if (d.mask & 1) { - basek = ((resource_t)(d.base)) << 8; - limitk = (resource_t)((d.mask << 8) | 0xFFFFFF); + basek = ((resource_t)((u64)d.base)) << 8; + limitk = (resource_t)(((u64)d.mask << 8) | 0xFFFFFF); printk(BIOS_DEBUG, "adsr: (before) basek = %llx, limitk = %llx.\n",basek,limitk); /* Convert these values to multiples of 1K for ease of math. */

1 0

ASRock e350m1 problems
by Tadas Slotkus 08 Jul '11

08 Jul '11

Hi, just compiled coreboot for e350m1, flashed original flashchip and got this (log attached) everytime I power on or reset my system. Any hints? Thanks, Tadas

4 4

Patch merged into master: 6b83829 libpayload: Don't declare mouse support in tinycurses
by gerrit＠coreboot.org 07 Jul '11

07 Jul '11

the following patch was just integrated into master: commit 6b8382926be735a0c14c7ff516f0a390df4f1708 Author: Patrick Georgi <Patrick.Georgi(a)secunet.com> Date: Thu Mar 10 14:53:54 2011 +0100 libpayload: Don't declare mouse support in tinycurses Change-Id: Id1ff3d85617e3ec063ce332cf13920dfbbb7cf26 Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> See http://review.coreboot.org/87 for details. -gerrit

1 0

← Newer
1
...
17
18
19
20
21
22
23
24
25
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot July 2011