coreboot April 2011

coreboot@coreboot.org

66 participants
229 discussions

romcc segfault
by Stefan Reinauer 13 Apr '11

13 Apr '11

Hi, just a heads up, I got romcc to segfault with the following sample program: --------------------- 8< snip 8< -------------------------------------- typedef unsigned int u32; #define DEFAULT_RCBA 0xfed1c000 #define GCS 0x3410 #define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x)) void test(void) { RCBA32(GCS) &= (~0x04); } --------------------- >8 snip >8 -------------------------------------- I tried to simplify this further and this construct is still crashing romcc: --------------------- 8< snip 8< -------------------------------------- u32 *gcs = (u32 *)(DEFAULT_RCBA + GCS); *gcs &= (~0x04); --------------------- >8 snip >8 -------------------------------------- while this one is working --------------------- 8< snip 8< -------------------------------------- u32 *gcs = (u32 *)(DEFAULT_RCBA + GCS); u32 temp = *gcs; temp &= (~0x04); *gcs = temp; --------------------- >8 snip >8 -------------------------------------- Is that a construct that we just can't/don't want to support in romcc? Or is there a chance we can fix that? Stefan gdb back trace: $ gdb build/util/romcc/romcc GNU gdb (GDB) 7.2-gg8 Copyright (C) 2010 Free Software Foundation, Inc. License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html> Type "show copying" and "show warranty" for licensing/warranty details. This GDB was configured as "x86_64-linux". <http://wiki/Main/GnuDebugger FAQ: http://go/gdb Email: gdb-team> Hey, I'm GDB 7.x. Check me out! http://wiki/Main/Gdb7x Reading symbols from /Users/stepan/svn/coreboot/build/util/romcc/romcc...done. (gdb) run test.c Starting program: /Users/stepan/svn/coreboot/build/util/romcc/romcc test.c Program received signal SIGSEGV, Segmentation fault. 0x0000000000402baa in use_triple (used=0x676860, user=0x676a50) at /Users/stepan/svn/coreboot/util/romcc/romcc.c:1901 1901 if ((*ptr)->member == user) { (gdb) bt #0 0x0000000000402baa in use_triple (used=0x676860, user=0x676a50) at /Users/stepan/svn/coreboot/util/romcc/romcc.c:1901 #1 0x00000000004120df in flatten_generic (state=0x7fffffff9c60, first=0x675d40, ptr=0x676a50, ignored=0) at /Users/stepan/svn/coreboot/util/romcc/romcc.c:7847 #2 0x00000000004131a0 in flatten (state=0x7fffffff9c60, first=0x675d40, ptr=0x676a50) at /Users/stepan/svn/coreboot/util/romcc/romcc.c:8042 #3 0x000000000041e1fb in expr_statement (state=0x7fffffff9c60, first=0x675d40) at /Users/stepan/svn/coreboot/util/romcc/romcc.c:11662 #4 0x0000000000420479 in statement (state=0x7fffffff9c60, first=0x675d40) at /Users/stepan/svn/coreboot/util/romcc/romcc.c:12361 #5 0x0000000000420248 in compound_statement (state=0x7fffffff9c60, first=0x675d40) at /Users/stepan/svn/coreboot/util/romcc/romcc.c:12304 #6 0x0000000000422bb1 in function_definition (state=0x7fffffff9c60, type=0x675c60) at /Users/stepan/svn/coreboot/util/romcc/romcc.c:13415 #7 0x0000000000422fa5 in decl (state=0x7fffffff9c60, first=0x675960) at /Users/stepan/svn/coreboot/util/romcc/romcc.c:13507 #8 0x00000000004231b8 in decls (state=0x7fffffff9c60) at /Users/stepan/svn/coreboot/util/romcc/romcc.c:13553 #9 0x000000000043f263 in compile (filename=0x7fffffffe389 "test.c", compiler=0x7fffffffdea0, arch=0x7fffffffdf00) at /Users/stepan/svn/coreboot/util/romcc/romcc.c:25045 #10 0x000000000043f98b in main (argc=1, argv=0x7fffffffe020) at /Users/stepan/svn/coreboot/util/romcc/romcc.c:25190

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SB850 SERR# routing (almost off-topic)
by Jonathan A. Kollasch 12 Apr '11

12 Apr '11

Hi, My AM3/870/sb850 board doesn't seem to route SERR# on the conventional PCI bus to a NMI. I've adjusted the registers at port 61h and 70h, and ensured that the Core 0 LAPIC LINT1 is not masked and is routed to NMI. I've also enabled SERR handling in various parts of the chipset. I managed to get this to work on a 785/sb7xx board after adjusting port C14h, but that's not where I need to trigger a NMI. The sb850 board does not appear to have a decoded register at port C14h I don't know if this is because it's been hidden, or because it's moved somewhere else or where it may have moved to. Could anyone tell how I could make this work on the SB850 board? Jonathan Kollasch

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[commit] r6490 - trunk/src/ec/lenovo/h8
by repository service 12 Apr '11

12 Apr '11

Author: svens Date: Tue Apr 12 20:18:24 2011 New Revision: 6490 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6490 Log: Lenovo H8 EC: Set fancontrol to Automatic management My Notebook gets far to hot without fan, so just enable automatic fan control by default. Signed-off-by: Sven Schnelle <svens(a)stackframe.org> Acked-by: Sven Schnelle <svens(a)stackframe.org> Modified: trunk/src/ec/lenovo/h8/h8.c trunk/src/ec/lenovo/h8/h8.h Modified: trunk/src/ec/lenovo/h8/h8.c ============================================================================== --- trunk/src/ec/lenovo/h8/h8.c Tue Apr 12 20:18:12 2011 (r6489) +++ trunk/src/ec/lenovo/h8/h8.c Tue Apr 12 20:18:24 2011 (r6490) @@ -118,6 +118,7 @@ ec_write(0x1e, conf->evente_enable); ec_write(0x1f, conf->eventf_enable); + ec_write(H8_FAN_CONTROL, H8_FAN_CONTROL_AUTO); h8_wlan_enable(conf->wlan_enable); h8_trackpoint_enable(conf->trackpoint_enable); Modified: trunk/src/ec/lenovo/h8/h8.h ============================================================================== --- trunk/src/ec/lenovo/h8/h8.h Tue Apr 12 20:18:12 2011 (r6489) +++ trunk/src/ec/lenovo/h8/h8.h Tue Apr 12 20:18:24 2011 (r6490) @@ -67,6 +67,8 @@ #define H8_LED_CONTROL_DOCK_LED1 0x08 #define H8_LED_CONTROL_DOCK_LED2 0x09 +#define H8_FAN_CONTROL 0x2f +#define H8_FAN_CONTROL_AUTO 0x80 /* Embedded controller events */ #define H8_EVENT_FN_F1 0x10 #define H8_EVENT_FN_F2 0x11

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[commit] r6489 - trunk/src/superio/nsc/pc87384
by repository service 12 Apr '11

12 Apr '11

Author: svens Date: Tue Apr 12 20:18:12 2011 New Revision: 6489 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6489 Log: PC87384: add GPIO defines Signed-off-by: Sven Schnelle <svens(a)stackframe.org> Acked-by: Sven Schnelle <svens(a)stackframe.org> Modified: trunk/src/superio/nsc/pc87384/pc87384.h Modified: trunk/src/superio/nsc/pc87384/pc87384.h ============================================================================== --- trunk/src/superio/nsc/pc87384/pc87384.h Tue Apr 12 03:12:46 2011 (r6488) +++ trunk/src/superio/nsc/pc87384/pc87384.h Tue Apr 12 20:18:12 2011 (r6489) @@ -25,4 +25,15 @@ #define PC87384_SP2 0x02 #define PC87384_SP1 0x03 #define PC87384_GPIO 0x07 + +#define PC87384_GPIO_PIN_OE 0x01 +#define PC87384_GPIO_PIN_TYPE_PUSH_PULL 0x02 +#define PC87384_GPIO_PIN_PULLUP 0x04 +#define PC87384_GPIO_PIN_LOCK 0x08 +#define PC87384_GPIO_PIN_TRIG_LEVEL 0x10 +#define PC87384_GPIO_PIN_TRIG_LOW 0x20 +#define PC87384_GPIO_PIN_DEBOUNCE 0x40 + +#define PC87384_GPIO_PIN_TRIGGERS_IRQ 0x01 + #endif

1 0

Coreboot on Atom N550
by Joesph Czerniak 12 Apr '11

12 Apr '11

Hi, I bought the HP 5103 netbook. I was wondering if coreboot would run on it. It has the following specs: Here are the quick specs (the more detailed specs are at the bottom): CPU: Intel Atom N550 with an integrated northbridge Southbridge: Intel N10/ICH 7 SuperIO: SMSC FDC37B72x So on your motherboard page, the closest motherboard I could find is the Intel D945GCLF. So I found the Kconfig file and thought a good way to start would be to modify it. It has: select CPU_INTEL_SOCKET_441 select NORTHBRIDGE_INTEL_I945GC select SOUTHBRIDGE_INTEL_I82801GX select SUPERIO_SMSC_LPC47M15X Should I start by modifying these four lines? Then compile and flash? The socket for the N550 is the Intel Socket 437. Does coreboot support that? The other question I had was about the northbridge. Since its integrated into the CPU, should I remove that line? Or can I keep it in? Thanks for your help! Joseph Per the FAQ, here's lspci -tvnn: -[0000:00]-+-00.0 Intel Corporation N10 Family DMI Bridge [8086:a010] +-02.0 Intel Corporation N10 Family Integrated Graphics Controller [8086:a011] +-02.1 Intel Corporation N10 Family Integrated Graphics Controller [8086:a012] +-1b.0 Intel Corporation N10/ICH 7 Family High Definition Audio Controller [8086:27d8] +-1c.0-[0000:01]----00.0 Broadcom Corporation Device [14e4:4727] +-1c.3-[0000:02]----00.0 Marvell Technology Group Ltd. Device [11ab:4381] +-1d.0 Intel Corporation N10/ICH7 Family USB UHCI Controller #1 [8086:27c8] +-1d.1 Intel Corporation N10/ICH 7 Family USB UHCI Controller #2 [8086:27c9] +-1d.2 Intel Corporation N10/ICH 7 Family USB UHCI Controller #3 [8086:27ca] +-1d.3 Intel Corporation N10/ICH 7 Family USB UHCI Controller #4 [8086:27cb] +-1d.7 Intel Corporation N10/ICH 7 Family USB2 EHCI Controller [8086:27cc] +-1e.0-[0000:03]-- +-1f.0 Intel Corporation NM10 Family LPC Controller [8086:27bc] \-1f.2 Intel Corporation N10/ICH7 Family SATA AHCI Controller [8086:27c1] Here's superiotool -dV: Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e... Found SMSC FDC37B72x (id=0x4c, rev=0x01) at 0x2e Register dump: idx 03 20 21 22 23 24 26 27 28 2b 2c 2d 2e 2f val 00 4c 01 10 00 04 2e 00 00 00 00 00 00 00 def 03 4c 00 00 00 04 MM MM 00 NA NA NA NA NA LDN 0x00 (Floppy) idx 30 60 61 70 74 f0 f1 f2 f4 f5 val 00 00 00 00 00 00 00 00 00 00 def 00 03 f0 06 02 0e 00 ff 00 00 LDN 0x03 (Parallel port) idx 30 60 61 70 74 f0 f1 val 00 00 00 00 00 00 00 def 00 00 00 00 04 3c 00 LDN 0x04 (COM1) idx 30 60 61 70 f0 val 01 02 80 06 00 def 00 00 00 00 00 LDN 0x05 (COM2) idx 30 60 61 70 f0 f1 f2 val 00 00 00 00 00 00 00 def NA 00 00 00 00 02 03 LDN 0x07 (Keyboard) idx 30 70 72 f0 val 01 01 0c 00 def 00 00 00 00 LDN 0x08 (Aux I/O) idx 30 b0 b1 b2 b3 b8 c0 c1 c2 c3 c4 c5 c6 c8 ca cb cc d0 d1 d2 d3 d4 d5 d6 d7 e0 e1 e2 e3 e4 e5 e6 e7 ef f0 f1 f2 f3 f4 f6 f9 fa val 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 def 00 NA NA NA NA NA 00 01 NA NA NA 00 NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA 00 00 00 MM NA NA NA LDN 0x0a (ACPI) idx 30 60 61 70 f0 val 00 00 00 00 00 def 00 00 00 NA NA Here's flashrom -V: flashrom v0.9.1-r946 No coreboot table found. DMI string system-manufacturer: "Hewlett-Packard" DMI string system-product-name: "HP Mini 5103" DMI string system-version: " " DMI string baseboard-manufacturer: "Hewlett-Packard" DMI string baseboard-product-name: "1608" DMI string baseboard-version: "KBC Version 92.04" DMI string chassis-type: "Notebook" Laptop detected via DMI ======================================================================== WARNING! You seem to be running flashrom on a laptop. Laptops, notebooks and netbooks are difficult to support and we recommend to use the vendor flashing utility. The embedded controller (EC) in these machines often interacts badly with flashing. See http://www.flashrom.org/Laptops for details. ======================================================================== Found chipset "Intel NM10", enabling flash write... 0xfff80000/0xffb80000 FWH IDSEL: 0x0 0xfff00000/0xffb00000 FWH IDSEL: 0x0 0xffe80000/0xffa80000 FWH IDSEL: 0x1 0xffe00000/0xffa00000 FWH IDSEL: 0x1 0xffd80000/0xff980000 FWH IDSEL: 0x2 0xffd00000/0xff900000 FWH IDSEL: 0x2 0xffc80000/0xff880000 FWH IDSEL: 0x3 0xffc00000/0xff800000 FWH IDSEL: 0x3 0xff700000/0xff300000 FWH IDSEL: 0x4 0xff600000/0xff200000 FWH IDSEL: 0x5 0xff500000/0xff100000 FWH IDSEL: 0x6 0xff400000/0xff000000 FWH IDSEL: 0x7 0xfff80000/0xffb80000 FWH decode enabled 0xfff00000/0xffb00000 FWH decode enabled 0xffe80000/0xffa80000 FWH decode enabled 0xffe00000/0xffa00000 FWH decode enabled 0xffd80000/0xff980000 FWH decode enabled 0xffd00000/0xff900000 FWH decode enabled 0xffc80000/0xff880000 FWH decode enabled 0xffc00000/0xff800000 FWH decode enabled 0xff700000/0xff300000 FWH decode disabled 0xff600000/0xff200000 FWH decode disabled 0xff500000/0xff100000 FWH decode disabled 0xff400000/0xff000000 FWH decode disabled Maximum FWH chip size: 0x100000 bytes BIOS Lock Enable: disabled, BIOS Write Enable: disabled, BIOS_CNTL is 0x0 Root Complex Register Block address = 0xfed1c000 GCS = 0x460: BIOS Interface Lock-Down: disabled, BOOT BIOS Straps: 0x1 (SPI) Top Swap : not enabled SPIBAR = 0xfed1c000 + 0x3020 0x00: 0x8004 (SPIS) 0x02: 0x4020 (SPIC) 0x04: 0x00000000 (SPIA) 0x08: 0x00412500 (SPID0) 0x0c: 0x00000000 (SPID0+4) 0x10: 0x00000000 (SPID1) 0x14: 0x00000000 (SPID1+4) 0x18: 0x00000000 (SPID2) 0x1c: 0x00000000 (SPID2+4) 0x20: 0x00000000 (SPID3) 0x24: 0x00000000 (SPID3+4) 0x28: 0x00000000 (SPID4) 0x2c: 0x00000000 (SPID4+4) 0x30: 0x00000000 (SPID5) 0x34: 0x00000000 (SPID5+4) 0x38: 0x00000000 (SPID6) 0x3c: 0x00000000 (SPID6+4) 0x40: 0x00000000 (SPID7) 0x44: 0x00000000 (SPID7+4) 0x50: 0x00000000 (BBAR) 0x54: 0x0606 (PREOP) 0x56: 0x7f48 (OPTYPE) 0x58: 0x0405039f (OPMENU) 0x5c: 0x0102d820 (OPMENU+4) 0x60: 0x80ff01c0 (PBR0) 0x64: 0x00000000 (PBR1) 0x68: 0x00000000 (PBR2) 0x6c: 0x00000000 (PBR3) WARNING: SPI Configuration Lockdown activated. Generating OPCODES... done SPI Read Configuration: prefetching disabled, caching enabled, OK. This chipset supports the following protocols: SPI. Calibrating delay loop... 738M loops per second, 100 myus = 211 us. OK. Probing for AMD Am29F010A/B, 128 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for AMD Am29F002(N)BB, 256 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for AMD Am29F002(N)BT, 256 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for AMD Am29F016D, 2048 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for AMD Am29F040B, 512 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for AMD Am29F080B, 1024 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for AMD Am29LV040B, 512 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for AMD Am29LV081B, 1024 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for ASD AE49F2008, 256 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for Atmel AT25DF021, 256 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Atmel AT25DF041A, 512 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Atmel AT25DF081, 1024 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Atmel AT25DF161, 2048 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Atmel AT25DF321, 4096 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Atmel AT25DF321A, 4096 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Atmel AT25DF641, 8192 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Atmel AT25F512B, 64 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Atmel AT25FS010, 128 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Atmel AT25FS040, 512 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Atmel AT26DF041, 512 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Atmel AT26DF081A, 1024 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Atmel AT26DF161, 2048 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Atmel AT26DF161A, 2048 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Atmel AT26F004, 512 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Atmel AT29C512, 64 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for Atmel AT29C010A, 128 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for Atmel AT29C020, 256 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for Atmel AT29C040A, 512 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for Atmel AT45CS1282, 16896 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Atmel AT45DB011D, 128 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Atmel AT45DB021D, 256 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Atmel AT45DB041D, 512 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Atmel AT45DB081D, 1024 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Atmel AT45DB161D, 2048 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Atmel AT45DB321C, 4224 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Atmel AT45DB321D, 4096 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Atmel AT45DB642D, 8192 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Atmel AT49BV512, 64 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for Atmel AT49F002(N), 256 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for Atmel AT49F002(N)T, 256 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for AMIC A25L40PT, 512 KB: RDID returned 0xbf 0x25 0x41 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for AMIC A25L40PU, 512 KB: RDID returned 0xbf 0x25 0x41 0xbf. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for AMIC A29002B, 256 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for AMIC A29002T, 256 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for AMIC A29040B, 512 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for AMIC A49LF040A, 512 KB: skipped. Host bus type SPI and chip bus type LPC are incompatible. Probing for EMST F49B002UA, 256 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for Eon EN25B05, 64 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Eon EN25B05T, 64 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Eon EN25B10, 128 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Eon EN25B10T, 128 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Eon EN25B20, 256 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Eon EN25B20T, 256 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Eon EN25B40, 512 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Eon EN25B40T, 512 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Eon EN25B80, 1024 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Eon EN25B80T, 1024 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Eon EN25B16, 2048 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Eon EN25B16T, 2048 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Eon EN25B32, 4096 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Eon EN25B32T, 4096 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Eon EN25B64, 8192 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Eon EN25B64T, 8192 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Eon EN25D16, 2048 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Eon EN25F05, 64 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Eon EN25F10, 128 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Eon EN25F20, 256 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Eon EN25F40, 512 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Eon EN25F80, 1024 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Eon EN25F16, 2048 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Eon EN25F32, 4096 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Eon EN29F010, 128 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for EON EN29F002(A)(N)B, 256 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for EON EN29F002(A)(N)T, 256 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F004BC, 512 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F004TC, 512 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F400BC, 512 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F400TC, 512 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for Intel 28F001BX-B, 128 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for Intel 28F001BX-T, 128 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for Intel 28F004S5, 512 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for Intel 82802AB, 512 KB: skipped. Host bus type SPI and chip bus type FWH are incompatible. Probing for Intel 82802AC, 1024 KB: skipped. Host bus type SPI and chip bus type FWH are incompatible. Probing for Macronix MX25L512, 64 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Macronix MX25L1005, 128 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Macronix MX25L2005, 256 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Macronix MX25L4005, 512 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Macronix MX25L8005, 1024 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Macronix MX25L1605, 2048 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Macronix MX25L1635D, 2048 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Macronix MX25L3205, 4096 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Macronix MX25L3235D, 4096 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Macronix MX25L6405, 8192 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Macronix MX25L12805, 16384 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Macronix MX29F001B, 128 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for Macronix MX29F001T, 128 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for Macronix MX29F002B, 256 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for Macronix MX29F002T, 256 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for Macronix MX29LV040, 512 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for Numonyx M25PE10, 128 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Numonyx M25PE20, 256 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Numonyx M25PE40, 512 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Numonyx M25PE80, 1024 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Numonyx M25PE16, 2048 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for PMC Pm25LV010, 128 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for PMC Pm25LV016B, 2048 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for PMC Pm25LV020, 256 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for PMC Pm25LV040, 512 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for PMC Pm25LV080B, 1024 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for PMC Pm25LV512, 64 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for PMC Pm29F002T, 256 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for PMC Pm29F002B, 256 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for PMC Pm39LV010, 128 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for PMC Pm49FL002, 256 KB: skipped. Host bus type SPI and chip bus type LPC,FWH are incompatible. Probing for PMC Pm49FL004, 512 KB: skipped. Host bus type SPI and chip bus type LPC,FWH are incompatible. Probing for Sanyo LF25FW203A, 2048 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Sharp LHF00L04, 1024 KB: skipped. Host bus type SPI and chip bus type FWH are incompatible. Probing for Spansion S25FL008A, 1024 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Spansion S25FL016A, 2048 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for SST SST25VF016B, 2048 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Chip status register is 00 Chip status register: Block Protect Write Disable (BPL) is not set Chip status register: Auto Address Increment Programming (AAI) is not set Chip status register: Bit 5 / Block Protect 3 (BP3) is not set Chip status register: Bit 4 / Block Protect 2 (BP2) is not set Chip status register: Bit 3 / Block Protect 1 (BP1) is not set Chip status register: Bit 2 / Block Protect 0 (BP0) is not set Chip status register: Write Enable Latch (WEL) is not set Chip status register: Write In Progress (WIP/BUSY) is not set Resulting block protection : none Found chip "SST SST25VF016B" (2048 KB, SPI) at physical address 0xffe00000. Probing for SST SST25VF032B, 4096 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for SST SST25VF040.REMS, 512 KB: Invalid OPCODE 0x90 Probing for SST SST25VF040B, 512 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for SST SST25VF040B.REMS, 512 KB: Invalid OPCODE 0x90 Probing for SST SST25VF080B, 1024 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for SST SST28SF040A, 512 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for SST SST29EE010, 128 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for SST SST29LE010, 128 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for SST SST29EE020A, 256 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for SST SST29LE020, 256 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for SST SST39SF512, 64 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for SST SST39SF010A, 128 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for SST SST39SF020A, 256 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for SST SST39SF040, 512 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for SST SST39VF512, 64 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for SST SST39VF010, 128 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for SST SST39VF020, 256 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for SST SST39VF040, 512 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for SST SST39VF080, 1024 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for SST SST49LF002A/B, 256 KB: skipped. Host bus type SPI and chip bus type FWH are incompatible. Probing for SST SST49LF003A/B, 384 KB: skipped. Host bus type SPI and chip bus type FWH are incompatible. Probing for SST SST49LF004A/B, 512 KB: skipped. Host bus type SPI and chip bus type FWH are incompatible. Probing for SST SST49LF004C, 512 KB: skipped. Host bus type SPI and chip bus type FWH are incompatible. Probing for SST SST49LF008A, 1024 KB: skipped. Host bus type SPI and chip bus type FWH are incompatible. Probing for SST SST49LF008C, 1024 KB: skipped. Host bus type SPI and chip bus type FWH are incompatible. Probing for SST SST49LF016C, 2048 KB: skipped. Host bus type SPI and chip bus type FWH are incompatible. Probing for SST SST49LF020, 256 KB: skipped. Host bus type SPI and chip bus type LPC are incompatible. Probing for SST SST49LF020A, 256 KB: skipped. Host bus type SPI and chip bus type LPC are incompatible. Probing for SST SST49LF040, 512 KB: skipped. Host bus type SPI and chip bus type LPC are incompatible. Probing for SST SST49LF040B, 512 KB: skipped. Host bus type SPI and chip bus type LPC are incompatible. Probing for SST SST49LF080A, 1024 KB: skipped. Host bus type SPI and chip bus type LPC are incompatible. Probing for SST SST49LF160C, 2048 KB: skipped. Host bus type SPI and chip bus type LPC are incompatible. Probing for ST M25P05-A, 64 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for ST M25P05.RES, 64 KB: RDID returned 0xbf 0x25 0x41. Ignoring RES in favour of RDID. Probing for ST M25P10-A, 128 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for ST M25P10.RES, 128 KB: RDID returned 0xbf 0x25 0x41. Ignoring RES in favour of RDID. Probing for ST M25P20, 256 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for ST M25P40, 512 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for ST M25P40-old, 512 KB: RDID returned 0xbf 0x25 0x41. Ignoring RES in favour of RDID. Probing for ST M25P80, 1024 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for ST M25P16, 2048 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for ST M25P32, 4096 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for ST M25P64, 8192 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for ST M25P128, 16384 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for ST M29F002B, 256 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for ST M29F002T/NT, 256 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for ST M29F040B, 512 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for ST M29F400BT, 512 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for ST M29W010B, 128 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for ST M29W040B, 512 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for ST M29W512B, 64 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for ST M50FLW040A, 512 KB: skipped. Host bus type SPI and chip bus type LPC,FWH are incompatible. Probing for ST M50FLW040B, 512 KB: skipped. Host bus type SPI and chip bus type LPC,FWH are incompatible. Probing for ST M50FLW080A, 1024 KB: skipped. Host bus type SPI and chip bus type LPC,FWH are incompatible. Probing for ST M50FLW080B, 1024 KB: skipped. Host bus type SPI and chip bus type LPC,FWH are incompatible. Probing for ST M50FW002, 256 KB: skipped. Host bus type SPI and chip bus type FWH are incompatible. Probing for ST M50FW016, 2048 KB: skipped. Host bus type SPI and chip bus type FWH are incompatible. Probing for ST M50FW040, 512 KB: skipped. Host bus type SPI and chip bus type FWH are incompatible. Probing for ST M50FW080, 1024 KB: skipped. Host bus type SPI and chip bus type FWH are incompatible. Probing for ST M50LPW116, 2048 KB: skipped. Host bus type SPI and chip bus type LPC are incompatible. Probing for SyncMOS S29C31004T, 512 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for SyncMOS S29C51001T, 128 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for SyncMOS S29C51002T, 256 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for SyncMOS S29C51004T, 512 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for TI TMS29F002RB, 256 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for TI TMS29F002RT, 256 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for Winbond W25x10, 128 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Winbond W25x20, 256 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Winbond W25x40, 512 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Winbond W25x80, 1024 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Winbond W25x16, 2048 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Winbond W25x32, 4096 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Winbond W25x64, 8192 KB: RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Probing for Winbond W29C011, 128 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for Winbond W29C020C, 256 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for Winbond W29C040P, 512 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for Winbond W29EE011, 128 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for Winbond W39V040A, 512 KB: skipped. Host bus type SPI and chip bus type LPC are incompatible. Probing for Winbond W39V040B, 512 KB: skipped. Host bus type SPI and chip bus type LPC are incompatible. Probing for Winbond W39V040C, 512 KB: skipped. Host bus type SPI and chip bus type LPC are incompatible. Probing for Winbond W39V040FA, 512 KB: skipped. Host bus type SPI and chip bus type FWH are incompatible. Probing for Winbond W39V080A, 1024 KB: skipped. Host bus type SPI and chip bus type LPC are incompatible. Probing for Winbond W49F002U, 256 KB: skipped. Host bus type SPI and chip bus type Parallel are incompatible. Probing for Winbond W49V002A, 256 KB: skipped. Host bus type SPI and chip bus type LPC are incompatible. Probing for Winbond W49V002FA, 256 KB: skipped. Host bus type SPI and chip bus type FWH are incompatible. Probing for Winbond W39V080FA, 1024 KB: skipped. Host bus type SPI and chip bus type FWH are incompatible. Probing for Winbond W39V080FA (dual mode), 512 KB: skipped. Host bus type SPI and chip bus type FWH are incompatible. Probing for Atmel unknown Atmel SPI chip, 0 KB: Not mapping flash chip, zero size at 0x00000000. RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Not unmapping zero size at (nil) Probing for EON unknown EON SPI chip, 0 KB: Not mapping flash chip, zero size at 0x00000000. RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Not unmapping zero size at (nil) Probing for Macronix unknown Macronix SPI chip, 0 KB: Not mapping flash chip, zero size at 0x00000000. RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Not unmapping zero size at (nil) Probing for PMC unknown PMC SPI chip, 0 KB: Not mapping flash chip, zero size at 0x00000000. RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Not unmapping zero size at (nil) Probing for SST unknown SST SPI chip, 0 KB: Not mapping flash chip, zero size at 0x00000000. RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Not unmapping zero size at (nil) Probing for ST unknown ST SPI chip, 0 KB: Not mapping flash chip, zero size at 0x00000000. RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Not unmapping zero size at (nil) Probing for Sanyo unknown Sanyo SPI chip, 0 KB: Not mapping flash chip, zero size at 0x00000000. RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Not unmapping zero size at (nil) Probing for Generic unknown SPI chip (RDID), 0 KB: Not mapping flash chip, zero size at 0x00000000. RDID returned 0xbf 0x25 0x41. probe_spi_rdid_generic: id1 0xbf, id2 0x2541 Not unmapping zero size at (nil) Probing for Generic unknown SPI chip (REMS), 0 KB: Not mapping flash chip, zero size at 0x00000000. Invalid OPCODE 0x90 Not unmapping zero size at (nil) === This flash part has status UNTESTED for operations: ERASE Please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -rV, -wV, -EV), and mention which mainboard or programmer you tested. Thanks for your help! === No operations were specified.

3 2

[commit] r6488 - trunk/src/southbridge/amd/rs780
by repository service 12 Apr '11

12 Apr '11

Author: kerry Date: Tue Apr 12 03:12:46 2011 New Revision: 6488 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6488 Log: Use TOM2 for highest sysmem setting for northbound memory routing (DMA). This fixes 4GB memory issues. Signed-off-by: Marc Jones <marcj303(a)gmail.com> Acked-by: Kerry she <kerry.she(a)amd.com> Modified: trunk/src/southbridge/amd/rs780/gfx.c Modified: trunk/src/southbridge/amd/rs780/gfx.c ============================================================================== --- trunk/src/southbridge/amd/rs780/gfx.c Mon Apr 11 22:17:22 2011 (r6487) +++ trunk/src/southbridge/amd/rs780/gfx.c Tue Apr 12 03:12:46 2011 (r6488) @@ -661,13 +661,15 @@ printk(BIOS_DEBUG, "rs780_internal_gfx_enable dev = 0x%p, nb_dev = 0x%p.\n", dev, nb_dev); - sysmem = rdmsr(0xc001001a); - printk(BIOS_DEBUG, "sysmem = %x_%x\n", sysmem.hi, sysmem.lo); - /* The system top memory in 780. */ + sysmem = rdmsr(0xc001001a); + printk(BIOS_DEBUG, "Sysmem TOM = %x_%x\n", sysmem.hi, sysmem.lo); pci_write_config32(nb_dev, 0x90, sysmem.lo); - htiu_write_index(nb_dev, 0x30, 0); - htiu_write_index(nb_dev, 0x31, 0); + + sysmem = rdmsr(0xc001001D); + printk(BIOS_DEBUG, "Sysmem TOM2 = %x_%x\n", sysmem.hi, sysmem.lo); + htiu_write_index(nb_dev, 0x31, sysmem.hi); + htiu_write_index(nb_dev, 0x30, sysmem.lo | 1); /* Disable external GFX and enable internal GFX. */ l_dword = pci_read_config32(nb_dev, 0x8c);

1 0

[patch] rs780 4GB memory issues
by Marc Jones 12 Apr '11

12 Apr '11

Use TOM2 for highest sysmem setting for northbound memory routing (DMA). This fixes 4GB memory issues. Signed-off-by: Marc Jones <marcj303(a)gmail.com> -- http://se-eng.com

4 5

[commit] r6487 - in trunk/src: arch/x86/init arch/x86/lib boot cpu/amd/model_gx2 cpu/amd/model_lx cpu/amd/sc520 cpu/intel/car cpu/intel/model_106cx cpu/intel/model_6ex cpu/intel/model_6fx cpu/via/c...
by repository service 11 Apr '11

11 Apr '11

Author: stepan Date: Mon Apr 11 22:17:22 2011 New Revision: 6487 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6487 Log: Unify use of post_code Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Acked-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Added: trunk/src/include/console/post_codes.h Modified: trunk/src/arch/x86/init/crt0_romcc_epilogue.inc trunk/src/arch/x86/init/prologue.inc trunk/src/arch/x86/lib/c_start.S trunk/src/boot/hardwaremain.c trunk/src/boot/selfboot.c trunk/src/cpu/amd/model_gx2/cache_as_ram.inc trunk/src/cpu/amd/model_lx/cache_as_ram.inc trunk/src/cpu/amd/sc520/raminit.c trunk/src/cpu/intel/car/cache_as_ram.inc trunk/src/cpu/intel/model_106cx/cache_as_ram.inc trunk/src/cpu/intel/model_6ex/cache_as_ram.inc trunk/src/cpu/intel/model_6fx/cache_as_ram.inc trunk/src/cpu/via/car/cache_as_ram.inc trunk/src/cpu/x86/32bit/entry32.inc trunk/src/include/console/console.h trunk/src/include/cpu/amd/geode_post_code.h trunk/src/include/cpu/x86/post_code.h trunk/src/mainboard/amd/db800/romstage.c trunk/src/mainboard/amd/norwich/romstage.c trunk/src/mainboard/amd/rumba/romstage.c trunk/src/mainboard/artecgroup/dbe61/romstage.c trunk/src/mainboard/digitallogic/msm800sev/romstage.c trunk/src/mainboard/iei/pcisa-lx-800-r10/romstage.c trunk/src/mainboard/lippert/frontrunner/romstage.c trunk/src/mainboard/lippert/hurricane-lx/romstage.c trunk/src/mainboard/lippert/literunner-lx/romstage.c trunk/src/mainboard/lippert/roadrunner-lx/romstage.c trunk/src/mainboard/lippert/spacerunner-lx/romstage.c trunk/src/mainboard/pcengines/alix1c/romstage.c trunk/src/mainboard/pcengines/alix2d/romstage.c trunk/src/mainboard/traverse/geos/romstage.c trunk/src/mainboard/winent/pl6064/romstage.c trunk/src/mainboard/wyse/s50/romstage.c trunk/src/northbridge/amd/gx1/raminit.c trunk/src/northbridge/via/cx700/early_serial.c trunk/src/northbridge/via/vx800/early_serial.c trunk/src/southbridge/amd/cs5535/chipsetinit.c trunk/src/southbridge/amd/cs5536/cs5536.c trunk/src/southbridge/via/vt8231/early_serial.c Modified: trunk/src/arch/x86/init/crt0_romcc_epilogue.inc ============================================================================== --- trunk/src/arch/x86/init/crt0_romcc_epilogue.inc Mon Apr 11 21:43:50 2011 (r6486) +++ trunk/src/arch/x86/init/crt0_romcc_epilogue.inc Mon Apr 11 22:17:22 2011 (r6487) @@ -5,11 +5,12 @@ * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; version 2 of the License. */ +#include <cpu/x86/post_code.h> /* clear boot_complete flag */ xorl %ebp, %ebp __main: - post_code(0x11) + post_code(POST_PREPARE_RAMSTAGE) cld /* clear direction flag */ movl %ebp, %esi @@ -20,7 +21,7 @@ call copy_and_run .Lhlt: - post_code(0xee) + post_code(POST_DEAD_CODE) hlt jmp .Lhlt Modified: trunk/src/arch/x86/init/prologue.inc ============================================================================== --- trunk/src/arch/x86/init/prologue.inc Mon Apr 11 21:43:50 2011 (r6486) +++ trunk/src/arch/x86/init/prologue.inc Mon Apr 11 22:17:22 2011 (r6487) @@ -25,5 +25,5 @@ /* This is the entry code. The code in the .reset section jumps here. */ - post_code(0x01) + post_code(POST_RESET_VECTOR_CORRECT) Modified: trunk/src/arch/x86/lib/c_start.S ============================================================================== --- trunk/src/arch/x86/lib/c_start.S Mon Apr 11 21:43:50 2011 (r6486) +++ trunk/src/arch/x86/lib/c_start.S Mon Apr 11 22:17:22 2011 (r6487) @@ -14,7 +14,7 @@ movl %eax, %fs movl %eax, %gs - post_code(0x13) /* post 13 */ + post_code(POST_ENTRY_C_START) /* post 13 */ /** clear stack */ cld @@ -73,7 +73,7 @@ * bss is cleared. Now we call the main routine and * let it do the rest. */ - post_code(0xfe) /* post fe */ + post_code(POST_PRE_HARDWAREMAIN) /* post fe */ /* Restore the stack location */ movl %ebp, %esp @@ -82,7 +82,7 @@ call hardwaremain /* NOTREACHED */ .Lhlt: - post_code(0xee) /* post ee */ + post_code(POST_DEAD_CODE) /* post ee */ hlt jmp .Lhlt Modified: trunk/src/boot/hardwaremain.c ============================================================================== --- trunk/src/boot/hardwaremain.c Mon Apr 11 21:43:50 2011 (r6486) +++ trunk/src/boot/hardwaremain.c Mon Apr 11 22:17:22 2011 (r6487) @@ -57,18 +57,18 @@ { struct lb_memory *lb_mem; - post_code(0x80); + post_code(POST_ENTRY_RAMSTAGE); /* console_init() MUST PRECEDE ALL printk()! */ console_init(); - post_code(0x39); + post_code(POST_CONSOLE_READY); printk(BIOS_NOTICE, "coreboot-%s%s %s %s...\n", coreboot_version, coreboot_extra_version, coreboot_build, (boot_complete)?"rebooting":"booting"); - post_code(0x40); + post_code(POST_CONSOLE_BOOT_MSG); /* If we have already booted attempt a hard reboot */ if (boot_complete) { @@ -80,15 +80,15 @@ /* Find the devices we don't have hard coded knowledge about. */ dev_enumerate(); - post_code(0x66); + post_code(POST_DEVICE_ENUMERATION_COMPLETE); /* Now compute and assign the bus resources. */ dev_configure(); - post_code(0x88); + post_code(POST_DEVICE_CONFIGURATION_COMPLETE); /* Now actually enable devices on the bus */ dev_enable(); /* And of course initialize devices on the bus */ dev_initialize(); - post_code(0x89); + post_code(POST_DEVICES_ENABLED); #if CONFIG_WRITE_HIGH_TABLES == 1 cbmem_initialize(); Modified: trunk/src/boot/selfboot.c ============================================================================== --- trunk/src/boot/selfboot.c Mon Apr 11 21:43:50 2011 (r6486) +++ trunk/src/boot/selfboot.c Mon Apr 11 22:17:22 2011 (r6487) @@ -553,7 +553,7 @@ boot_successful(); printk(BIOS_DEBUG, "Jumping to boot code at %x\n", entry); - post_code(0xfe); + post_code(POST_ENTER_ELF_BOOT); /* Jump to kernel */ jmp_to_elf_entry((void*)entry, bounce_buffer, bounce_size); Modified: trunk/src/cpu/amd/model_gx2/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/amd/model_gx2/cache_as_ram.inc Mon Apr 11 21:43:50 2011 (r6486) +++ trunk/src/cpu/amd/model_gx2/cache_as_ram.inc Mon Apr 11 22:17:22 2011 (r6487) @@ -27,6 +27,7 @@ #define CR0_CD 0x40000000 /* bit 30 = Cache Disable */ #define CR0_NW 0x20000000 /* bit 29 = Not Write Through */ #include <cpu/amd/gx2def.h> +#include <cpu/x86/post_code.h> /*************************************************************************** /** /** DCacheSetup @@ -184,7 +185,7 @@ /* clear boot_complete flag */ xorl %ebp, %ebp __main: - post_code(0x11) + post_code(POST_PREPARE_RAMSTAGE) /* TODO For suspend/resume the cache will have to live between * CONFIG_RAMBASE and CONFIG_RAMTOP @@ -201,7 +202,7 @@ call copy_and_run .Lhlt: - post_code(0xee) + post_code(POST_DEAD_CODE) hlt jmp .Lhlt Modified: trunk/src/cpu/amd/model_lx/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/amd/model_lx/cache_as_ram.inc Mon Apr 11 21:43:50 2011 (r6486) +++ trunk/src/cpu/amd/model_lx/cache_as_ram.inc Mon Apr 11 22:17:22 2011 (r6487) @@ -26,6 +26,7 @@ #define CR0_CD 0x40000000 /* bit 30 = Cache Disable */ #define CR0_NW 0x20000000 /* bit 29 = Not Write Through */ #include <cpu/amd/lxdef.h> +#include <cpu/x86/post_code.h> /*************************************************************************** /** /** DCacheSetup @@ -210,7 +211,7 @@ /* clear boot_complete flag */ xorl %ebp, %ebp __main: - post_code(0x11) + post_code(POST_PREPARE_RAMSTAGE) /* TODO For suspend/resume the cache will have to live between * CONFIG_RAMBASE and CONFIG_RAMTOP @@ -227,7 +228,7 @@ call copy_and_run .Lhlt: - post_code(0xee) + post_code(POST_DEAD_CODE) hlt jmp .Lhlt Modified: trunk/src/cpu/amd/sc520/raminit.c ============================================================================== --- trunk/src/cpu/amd/sc520/raminit.c Mon Apr 11 21:43:50 2011 (r6486) +++ trunk/src/cpu/amd/sc520/raminit.c Mon Apr 11 22:17:22 2011 (r6487) @@ -144,13 +144,13 @@ /* the 0x80 led should now be working*/ - outb(0xaa, 0x80); + post_code(0xaa); #if 0 - /* wtf are 680 leds ... */ + /* wtf are 680 leds ... *//* <-- WTF is this comment? */ par = (unsigned long *) 0xfffef0c4; *par = 0x28000680; /* well? */ - outb(0x55, 0x80); + post_code(0x55); #endif /* set the uart baud rate clocks to the normal 1.8432 MHz.*/ Modified: trunk/src/cpu/intel/car/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/intel/car/cache_as_ram.inc Mon Apr 11 21:43:50 2011 (r6486) +++ trunk/src/cpu/intel/car/cache_as_ram.inc Mon Apr 11 22:17:22 2011 (r6487) @@ -24,6 +24,7 @@ #include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/lapic_def.h> +#include <cpu/x86/post_code.h> #define CacheSize CONFIG_DCACHE_RAM_SIZE #define CacheBase (0xd0000 - CacheSize) @@ -364,7 +365,7 @@ /* Clear boot_complete flag. */ xorl %ebp, %ebp __main: - post_code(0x11) + post_code(POST_PREPARE_RAMSTAGE) cld /* Clear direction flag. */ movl %ebp, %esi @@ -375,7 +376,7 @@ call copy_and_run .Lhlt: - post_code(0xee) + post_code(POST_DEAD_CODE) hlt jmp .Lhlt Modified: trunk/src/cpu/intel/model_106cx/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/intel/model_106cx/cache_as_ram.inc Mon Apr 11 21:43:50 2011 (r6486) +++ trunk/src/cpu/intel/model_106cx/cache_as_ram.inc Mon Apr 11 22:17:22 2011 (r6487) @@ -20,6 +20,7 @@ #include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> +#include <cpu/x86/post_code.h> #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE @@ -229,7 +230,7 @@ /* Clear boot_complete flag. */ xorl %ebp, %ebp __main: - post_code(0x11) + post_code(POST_PREPARE_RAMSTAGE) cld /* Clear direction flag. */ movl %ebp, %esi @@ -240,7 +241,7 @@ call copy_and_run .Lhlt: - post_code(0xee) + post_code(POST_DEAD_CODE) hlt jmp .Lhlt Modified: trunk/src/cpu/intel/model_6ex/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/intel/model_6ex/cache_as_ram.inc Mon Apr 11 21:43:50 2011 (r6486) +++ trunk/src/cpu/intel/model_6ex/cache_as_ram.inc Mon Apr 11 22:17:22 2011 (r6487) @@ -20,6 +20,7 @@ #include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> +#include <cpu/x86/post_code.h> #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE @@ -229,7 +230,7 @@ /* Clear boot_complete flag. */ xorl %ebp, %ebp __main: - post_code(0x11) + post_code(POST_PREPARE_RAMSTAGE) cld /* Clear direction flag. */ movl %ebp, %esi @@ -240,7 +241,7 @@ call copy_and_run .Lhlt: - post_code(0xee) + post_code(POST_DEAD_CODE) hlt jmp .Lhlt Modified: trunk/src/cpu/intel/model_6fx/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/intel/model_6fx/cache_as_ram.inc Mon Apr 11 21:43:50 2011 (r6486) +++ trunk/src/cpu/intel/model_6fx/cache_as_ram.inc Mon Apr 11 22:17:22 2011 (r6487) @@ -20,6 +20,7 @@ #include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> +#include <cpu/x86/post_code.h> #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE @@ -243,7 +244,7 @@ /* Clear boot_complete flag. */ xorl %ebp, %ebp __main: - post_code(0x11) + post_code(POST_PREPARE_RAMSTAGE) cld /* Clear direction flag. */ movl %ebp, %esi @@ -254,7 +255,7 @@ call copy_and_run .Lhlt: - post_code(0xee) + post_code(POST_DEAD_CODE) hlt jmp .Lhlt Modified: trunk/src/cpu/via/car/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/via/car/cache_as_ram.inc Mon Apr 11 21:43:50 2011 (r6486) +++ trunk/src/cpu/via/car/cache_as_ram.inc Mon Apr 11 22:17:22 2011 (r6487) @@ -27,6 +27,7 @@ #include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> +#include <console/post_codes.h> #define CacheSize CONFIG_DCACHE_RAM_SIZE #define CacheBase CONFIG_DCACHE_RAM_BASE @@ -261,7 +262,7 @@ /* Clear boot_complete flag. */ xorl %ebp, %ebp __main: - post_code(0x11) + post_code(POST_PREPARE_RAMSTAGE) cld /* Clear direction flag. */ movl %ebp, %esi @@ -272,7 +273,7 @@ call copy_and_run .Lhlt: - post_code(0xee) + post_code(POST_DEAD_CODE) hlt jmp .Lhlt Modified: trunk/src/cpu/x86/32bit/entry32.inc ============================================================================== --- trunk/src/cpu/x86/32bit/entry32.inc Mon Apr 11 21:43:50 2011 (r6486) +++ trunk/src/cpu/x86/32bit/entry32.inc Mon Apr 11 22:17:22 2011 (r6487) @@ -1,6 +1,7 @@ /* For starting coreboot in protected mode */ #include <arch/rom_segs.h> +#include <cpu/x86/post_code.h> .code32 @@ -51,7 +52,7 @@ /* Save the BIST value */ movl %eax, %ebp - post_code(0x10) + post_code(POST_ENTER_PROTECTED_MODE) movw $ROM_DATA_SEG, %ax movw %ax, %ds Modified: trunk/src/include/console/console.h ============================================================================== --- trunk/src/include/console/console.h Mon Apr 11 21:43:50 2011 (r6486) +++ trunk/src/include/console/console.h Mon Apr 11 22:17:22 2011 (r6487) @@ -22,6 +22,7 @@ #include <stdint.h> #include <console/loglevel.h> +#include <console/post_codes.h> #ifndef __PRE_RAM__ void console_tx_byte(unsigned char byte); Added: trunk/src/include/console/post_codes.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/include/console/post_codes.h Mon Apr 11 22:17:22 2011 (r6487) @@ -0,0 +1,351 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/** + * @file post_codes.h + * + * This aims to be a central point for POST codes used throughout coreboot. + * All POST codes should be declared here as macros, and post_code() should + * be used with the macros instead of hardcoded values. This allows us to + * quicly reference POST codes when nothing is working + * + * The format for a POST code macro is + * #define POST_WHAT_WE_COMMUNICATE_IS_HAPPENING_WHEN_THIS_CODE_IS_POSTED + * Lets's keep it at POST_* instead of POST_CODE_* + * + * This file is also included by early assembly files. Only use #define s; + * no function prototypes allowed here + * + * DOCUMENTATION: + * Please document any and all post codes using Doxygen style comments. We + * want to be able to generate a verbose enough documentation that is useful + * during debugging. Failure to do so will result in your patch being rejected + * without any explanation or effort on part of the maintainers. + * + */ +#ifndef POST_CODES_H +#define POST_CODES_H + +/** + * \brief Entry into 'crt0.s'. reset code jumps to here + * + * First instruction that gets executed after the reset vector jumps. + * This indicates that the reset vector points to the correct code segment. + */ +#define POST_RESET_VECTOR_CORRECT 0x01 + +/** + * \brief Entry into protected mode + * + * Preparing to enter protected mode. This is POSTed right before changing to + * protected mode. + */ +#define POST_ENTER_PROTECTED_MODE 0x10 + +/** + * \brief Start copying coreboot to RAM with decompression if compressed + * + * POSTed before ramstage is about to be loaded into memory + */ +#define POST_PREPARE_RAMSTAGE 0x11 + +/** + * \brief Copy/decompression finished; jumping to RAM + * + * This is called after ramstage is loaded in memory, and before + * the code jumps there. This represents the end of romstage. + */ +#define POST_RAMSTAGE_IS_PREPARED 0x12 + + +/** + * \brief Entry into c_start + * + * c_start.S is the first code executing in ramstage. + */ +#define POST_ENTRY_C_START 0x13 + +/** + * \brief Entry into coreboot in hardwaremain (RAM) + * + * This is the first call in hardwaremain.c. If this code is POSTed, then + * ramstage has succesfully loaded and started executing. + */ +#define POST_ENTRY_RAMSTAGE 0x80 + +/** + * \brief Console is initialized + * + * The console is initialized and is ready for usage + */ +#define POST_CONSOLE_READY 0x39 + +/** + * \brief Console boot message succeeded + * + * First console message has been succesfully sent through the console backend + * driver. + */ +#define POST_CONSOLE_BOOT_MSG 0x40 + +/** + * \brief Devices have been enumerated + * + * Bus scan, and device enumeration has completed. + */ +#define POST_DEVICE_ENUMERATION_COMPLETE 0x66 + +/** + * \brief Devices have been configured + * + * Device confgration has completed. + */ +#define POST_DEVICE_CONFIGURATION_COMPLETE 0x88 + +/** + * \brief Devices have been enabled + * + * Devices have been enabled. + */ +#define POST_DEVICES_ENABLED 0x89 + +/** + * \brief Entry into elf boot + * + * This POST code is called right before invoking jmp_to_elf_entry() + * jmp_to_elf_entry() invokes the payload, and should never return + */ +#define POST_ENTER_ELF_BOOT 0xf8 + +/** + * \brief Jumping to payload + * + * Called right before jumping to a payload. If the boot sequence stops with + * this code, chances are the payload freezes. + */ +#define POST_JUMPING_TO_PAYLOAD 0xf3 + +/** + * \brief Not supposed to get here + * + * A function that should not have returned, returned + * + * Check the console output for details. + */ +#define POST_DEAD_CODE 0xee + +/** + * \brief Pre call to hardwaremain() + * + * POSTed right before hardwaremain is called from c_start.S + * TODO: Change this code to a lower number + */ +#define POST_PRE_HARDWAREMAIN 0xfe + +/** + * \brief Elfload fail or die() called + * + * Coreboot was not able to load the payload, no payload was detected + * or die() was called. + * \n + * If this code appears before entering ramstage, then most likely + * ramstage is corrupted, and reflashing of the ROM chip is needed. + * \n + * If this code appears after ramstage, there is a problem with the payload + * If the payload was built out-of-tree, check that it was compiled as + * a coreboot payload + * \n + * Check the console output to see exactly where the failure occured. + */ +#define POST_DIE 0xff + + +/* + * The following POST codes are taken from src/include/cpu/amd/geode_post_code.h + * They overlap with previous codes, and most are not even used + * Some maiboards still require them, but they are deprecated. We want to consolidate + * our own POST code structure with the codes above. + * + * standard AMD post definitions for the AMD Geode + */ +#define POST_Output_Port (0x080) /* port to write post codes to*/ + +#define POST_preSioInit (0x000) +#define POST_clockInit (0x001) +#define POST_CPURegInit (0x002) +#define POST_UNREAL (0x003) +#define POST_CPUMemRegInit (0x004) +#define POST_CPUTest (0x005) +#define POST_memSetup (0x006) +#define POST_memSetUpStack (0x007) +#define POST_memTest (0x008) +#define POST_shadowRom (0x009) +#define POST_memRAMoptimize (0x00A) +#define POST_cacheInit (0x00B) +#define POST_northBridgeInit (0x00C) +#define POST_chipsetInit (0x00D) +#define POST_sioTest (0x00E) +#define POST_pcATjunk (0x00F) + +#define POST_intTable (0x010) +#define POST_memInfo (0x011) +#define POST_romCopy (0x012) +#define POST_PLLCheck (0x013) +#define POST_keyboardInit (0x014) +#define POST_cpuCacheOff (0x015) +#define POST_BDAInit (0x016) +#define POST_pciScan (0x017) +#define POST_optionRomInit (0x018) +#define POST_ResetLimits (0x019) +#define POST_summary_screen (0x01A) +#define POST_Boot (0x01B) +#define POST_SystemPreInit (0x01C) +#define POST_ClearRebootFlag (0x01D) +#define POST_GLIUInit (0x01E) +#define POST_BootFailed (0x01F) + +#define POST_CPU_ID (0x020) +#define POST_COUNTERBROKEN (0x021) +#define POST_DIFF_DIMMS (0x022) +#define POST_WIGGLE_MEM_LINES (0x023) +#define POST_NO_GLIU_DESC (0x024) +#define POST_CPU_LCD_CHECK (0x025) +#define POST_CPU_LCD_PASS (0x026) +#define POST_CPU_LCD_FAIL (0x027) +#define POST_CPU_STEPPING (0x028) +#define POST_CPU_DM_BIST_FAILURE (0x029) +#define POST_CPU_FLAGS (0x02A) +#define POST_CHIPSET_ID (0x02B) +#define POST_CHIPSET_ID_PASS (0x02C) +#define POST_CHIPSET_ID_FAIL (0x02D) +#define POST_CPU_ID_GOOD (0x02E) +#define POST_CPU_ID_FAIL (0x02F) + +/* PCI config*/ +#define P80_PCICFG (0x030) + +/* PCI io*/ +#define P80_PCIIO (0x040) + +/* PCI memory*/ +#define P80_PCIMEM (0x050) + +/* SIO*/ +#define P80_SIO (0x060) + +/* Memory Setp*/ +#define P80_MEM_SETUP (0x070) +#define POST_MEM_SETUP (0x070) +#define ERROR_32BIT_DIMMS (0x071) +#define POST_MEM_SETUP2 (0x072) +#define POST_MEM_SETUP3 (0x073) +#define POST_MEM_SETUP4 (0x074) +#define POST_MEM_SETUP5 (0x075) +#define POST_MEM_ENABLE (0x076) +#define ERROR_NO_DIMMS (0x077) +#define ERROR_DIFF_DIMMS (0x078) +#define ERROR_BAD_LATENCY (0x079) +#define ERROR_SET_PAGE (0x07A) +#define ERROR_DENSITY_DIMM (0x07B) +#define ERROR_UNSUPPORTED_DIMM (0x07C) +#define ERROR_BANK_SET (0x07D) +#define POST_MEM_SETUP_GOOD (0x07E) +#define POST_MEM_SETUP_FAIL (0x07F) + +#define POST_UserPreInit (0x080) +#define POST_UserPostInit (0x081) +#define POST_Equipment_check (0x082) +#define POST_InitNVRAMBX (0x083) +#define POST_NoPIRTable (0x084) +#define POST_ChipsetFingerPrintPass (0x085) +#define POST_ChipsetFingerPrintFail (0x086) +#define POST_CPU_IM_TAG_BIST_FAILURE (0x087) +#define POST_CPU_IM_DATA_BIST_FAILURE (0x088) +#define POST_CPU_FPU_BIST_FAILURE (0x089) +#define POST_CPU_BTB_BIST_FAILURE (0x08A) +#define POST_CPU_EX_BIST_FAILURE (0x08B) +#define POST_Chipset_PI_Test_Fail (0x08C) +#define POST_Chipset_SMBus_SDA_Test_Fail (0x08D) +#define POST_BIT_CLK_Fail (0x08E) + +#define POST_STACK_SETUP (0x090) +#define POST_CPU_PF_BIST_FAILURE (0x091) +#define POST_CPU_L2_BIST_FAILURE (0x092) +#define POST_CPU_GLCP_BIST_FAILURE (0x093) +#define POST_CPU_DF_BIST_FAILURE (0x094) +#define POST_CPU_VG_BIST_FAILURE (0x095) +#define POST_CPU_VIP_BIST_FAILURE (0x096) +#define POST_STACK_SETUP_PASS (0x09E) +#define POST_STACK_SETUP_FAIL (0x09F) + +#define POST_PLL_INIT (0x0A0) +#define POST_PLL_MANUAL (0x0A1) +#define POST_PLL_STRAP (0x0A2) +#define POST_PLL_RESET_FAIL (0x0A3) +#define POST_PLL_PCI_FAIL (0x0A4) +#define POST_PLL_MEM_FAIL (0x0A5) +#define POST_PLL_CPU_VER_FAIL (0x0A6) + +#define POST_MEM_TESTMEM (0x0B0) +#define POST_MEM_TESTMEM1 (0x0B1) +#define POST_MEM_TESTMEM2 (0x0B2) +#define POST_MEM_TESTMEM3 (0x0B3) +#define POST_MEM_TESTMEM4 (0x0B4) +#define POST_MEM_TESTMEM_PASS (0x0BE) +#define POST_MEM_TESTMEM_FAIL (0x0BF) + +#define POST_SECUROM_SECBOOT_START (0x0C0) +#define POST_SECUROM_BOOTSRCSETUP (0x0C1) +#define POST_SECUROM_REMAP_FAIL (0x0C2) +#define POST_SECUROM_BOOTSRCSETUP_FAIL (0x0C3) +#define POST_SECUROM_DCACHESETUP (0x0C4) +#define POST_SECUROM_DCACHESETUP_FAIL (0x0C5) +#define POST_SECUROM_ICACHESETUP (0x0C6) +#define POST_SECUROM_DESCRIPTORSETUP (0x0C7) +#define POST_SECUROM_DCACHESETUPBIOS (0x0C8) +#define POST_SECUROM_PLATFORMSETUP (0x0C9) +#define POST_SECUROM_SIGCHECKBIOS (0x0CA) +#define POST_SECUROM_ICACHESETUPBIOS (0x0CB) +#define POST_SECUROM_PASS (0x0CC) +#define POST_SECUROM_FAIL (0x0CD) + +#define POST_RCONFInitError (0x0CE) +#define POST_CacheInitError (0x0CF) + +#define POST_ROM_PREUNCOMPRESS (0x0D0) +#define POST_ROM_UNCOMPRESS (0x0D1) +#define POST_ROM_SMM_INIT (0x0D2) +#define POST_ROM_VID_BIOS (0x0D3) +#define POST_ROM_LCDINIT (0x0D4) +#define POST_ROM_SPLASH (0x0D5) +#define POST_ROM_HDDINIT (0x0D6) +#define POST_ROM_SYS_INIT (0x0D7) +#define POST_ROM_DMM_INIT (0x0D8) +#define POST_ROM_TVINIT (0x0D9) +#define POST_ROM_POSTUNCOMPRESS (0x0DE) + +#define P80_CHIPSET_INIT (0x0E0) +#define POST_PreChipsetInit (0x0E1) +#define POST_LateChipsetInit (0x0E2) +#define POST_NORTHB_INIT (0x0E8) + +#define POST_INTR_SEG_JUMP (0x0F0) + +#endif /* THE_ALMIGHTY_POST_CODES_H */ Modified: trunk/src/include/cpu/amd/geode_post_code.h ============================================================================== --- trunk/src/include/cpu/amd/geode_post_code.h Mon Apr 11 21:43:50 2011 (r6486) +++ trunk/src/include/cpu/amd/geode_post_code.h Mon Apr 11 22:17:22 2011 (r6487) @@ -1,182 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* standard AMD post definitions -- might as well use them. */ -#define POST_Output_Port (0x080) /* port to write post codes to*/ - -#define POST_preSioInit (0x000) -#define POST_clockInit (0x001) -#define POST_CPURegInit (0x002) -#define POST_UNREAL (0x003) -#define POST_CPUMemRegInit (0x004) -#define POST_CPUTest (0x005) -#define POST_memSetup (0x006) -#define POST_memSetUpStack (0x007) -#define POST_memTest (0x008) -#define POST_shadowRom (0x009) -#define POST_memRAMoptimize (0x00A) -#define POST_cacheInit (0x00B) -#define POST_northBridgeInit (0x00C) -#define POST_chipsetInit (0x00D) -#define POST_sioTest (0x00E) -#define POST_pcATjunk (0x00F) - -#define POST_intTable (0x010) -#define POST_memInfo (0x011) -#define POST_romCopy (0x012) -#define POST_PLLCheck (0x013) -#define POST_keyboardInit (0x014) -#define POST_cpuCacheOff (0x015) -#define POST_BDAInit (0x016) -#define POST_pciScan (0x017) -#define POST_optionRomInit (0x018) -#define POST_ResetLimits (0x019) -#define POST_summary_screen (0x01A) -#define POST_Boot (0x01B) -#define POST_SystemPreInit (0x01C) -#define POST_ClearRebootFlag (0x01D) -#define POST_GLIUInit (0x01E) -#define POST_BootFailed (0x01F) - -#define POST_CPU_ID (0x020) -#define POST_COUNTERBROKEN (0x021) -#define POST_DIFF_DIMMS (0x022) -#define POST_WIGGLE_MEM_LINES (0x023) -#define POST_NO_GLIU_DESC (0x024) -#define POST_CPU_LCD_CHECK (0x025) -#define POST_CPU_LCD_PASS (0x026) -#define POST_CPU_LCD_FAIL (0x027) -#define POST_CPU_STEPPING (0x028) -#define POST_CPU_DM_BIST_FAILURE (0x029) -#define POST_CPU_FLAGS (0x02A) -#define POST_CHIPSET_ID (0x02B) -#define POST_CHIPSET_ID_PASS (0x02C) -#define POST_CHIPSET_ID_FAIL (0x02D) -#define POST_CPU_ID_GOOD (0x02E) -#define POST_CPU_ID_FAIL (0x02F) - -/* PCI config*/ -#define P80_PCICFG (0x030) - -/* PCI io*/ -#define P80_PCIIO (0x040) - -/* PCI memory*/ -#define P80_PCIMEM (0x050) - -/* SIO*/ -#define P80_SIO (0x060) - -/* Memory Setp*/ -#define P80_MEM_SETUP (0x070) -#define POST_MEM_SETUP (0x070) -#define ERROR_32BIT_DIMMS (0x071) -#define POST_MEM_SETUP2 (0x072) -#define POST_MEM_SETUP3 (0x073) -#define POST_MEM_SETUP4 (0x074) -#define POST_MEM_SETUP5 (0x075) -#define POST_MEM_ENABLE (0x076) -#define ERROR_NO_DIMMS (0x077) -#define ERROR_DIFF_DIMMS (0x078) -#define ERROR_BAD_LATENCY (0x079) -#define ERROR_SET_PAGE (0x07A) -#define ERROR_DENSITY_DIMM (0x07B) -#define ERROR_UNSUPPORTED_DIMM (0x07C) -#define ERROR_BANK_SET (0x07D) -#define POST_MEM_SETUP_GOOD (0x07E) -#define POST_MEM_SETUP_FAIL (0x07F) - -#define POST_UserPreInit (0x080) -#define POST_UserPostInit (0x081) -#define POST_Equipment_check (0x082) -#define POST_InitNVRAMBX (0x083) -#define POST_NoPIRTable (0x084) -#define POST_ChipsetFingerPrintPass (0x085) -#define POST_ChipsetFingerPrintFail (0x086) -#define POST_CPU_IM_TAG_BIST_FAILURE (0x087) -#define POST_CPU_IM_DATA_BIST_FAILURE (0x088) -#define POST_CPU_FPU_BIST_FAILURE (0x089) -#define POST_CPU_BTB_BIST_FAILURE (0x08A) -#define POST_CPU_EX_BIST_FAILURE (0x08B) -#define POST_Chipset_PI_Test_Fail (0x08C) -#define POST_Chipset_SMBus_SDA_Test_Fail (0x08D) -#define POST_BIT_CLK_Fail (0x08E) - -#define POST_STACK_SETUP (0x090) -#define POST_CPU_PF_BIST_FAILURE (0x091) -#define POST_CPU_L2_BIST_FAILURE (0x092) -#define POST_CPU_GLCP_BIST_FAILURE (0x093) -#define POST_CPU_DF_BIST_FAILURE (0x094) -#define POST_CPU_VG_BIST_FAILURE (0x095) -#define POST_CPU_VIP_BIST_FAILURE (0x096) -#define POST_STACK_SETUP_PASS (0x09E) -#define POST_STACK_SETUP_FAIL (0x09F) - -#define POST_PLL_INIT (0x0A0) -#define POST_PLL_MANUAL (0x0A1) -#define POST_PLL_STRAP (0x0A2) -#define POST_PLL_RESET_FAIL (0x0A3) -#define POST_PLL_PCI_FAIL (0x0A4) -#define POST_PLL_MEM_FAIL (0x0A5) -#define POST_PLL_CPU_VER_FAIL (0x0A6) - -#define POST_MEM_TESTMEM (0x0B0) -#define POST_MEM_TESTMEM1 (0x0B1) -#define POST_MEM_TESTMEM2 (0x0B2) -#define POST_MEM_TESTMEM3 (0x0B3) -#define POST_MEM_TESTMEM4 (0x0B4) -#define POST_MEM_TESTMEM_PASS (0x0BE) -#define POST_MEM_TESTMEM_FAIL (0x0BF) - -#define POST_SECUROM_SECBOOT_START (0x0C0) -#define POST_SECUROM_BOOTSRCSETUP (0x0C1) -#define POST_SECUROM_REMAP_FAIL (0x0C2) -#define POST_SECUROM_BOOTSRCSETUP_FAIL (0x0C3) -#define POST_SECUROM_DCACHESETUP (0x0C4) -#define POST_SECUROM_DCACHESETUP_FAIL (0x0C5) -#define POST_SECUROM_ICACHESETUP (0x0C6) -#define POST_SECUROM_DESCRIPTORSETUP (0x0C7) -#define POST_SECUROM_DCACHESETUPBIOS (0x0C8) -#define POST_SECUROM_PLATFORMSETUP (0x0C9) -#define POST_SECUROM_SIGCHECKBIOS (0x0CA) -#define POST_SECUROM_ICACHESETUPBIOS (0x0CB) -#define POST_SECUROM_PASS (0x0CC) -#define POST_SECUROM_FAIL (0x0CD) - -#define POST_RCONFInitError (0x0CE) -#define POST_CacheInitError (0x0CF) - -#define POST_ROM_PREUNCOMPRESS (0x0D0) -#define POST_ROM_UNCOMPRESS (0x0D1) -#define POST_ROM_SMM_INIT (0x0D2) -#define POST_ROM_VID_BIOS (0x0D3) -#define POST_ROM_LCDINIT (0x0D4) -#define POST_ROM_SPLASH (0x0D5) -#define POST_ROM_HDDINIT (0x0D6) -#define POST_ROM_SYS_INIT (0x0D7) -#define POST_ROM_DMM_INIT (0x0D8) -#define POST_ROM_TVINIT (0x0D9) -#define POST_ROM_POSTUNCOMPRESS (0x0DE) - -#define P80_CHIPSET_INIT (0x0E0) -#define POST_PreChipsetInit (0x0E1) -#define POST_LateChipsetInit (0x0E2) -#define POST_NORTHB_INIT (0x0E8) - -#define POST_INTR_SEG_JUMP (0x0F0) Modified: trunk/src/include/cpu/x86/post_code.h ============================================================================== --- trunk/src/include/cpu/x86/post_code.h Mon Apr 11 21:43:50 2011 (r6486) +++ trunk/src/include/cpu/x86/post_code.h Mon Apr 11 22:17:22 2011 (r6487) @@ -1,4 +1,5 @@ +#include <console/post_codes.h> #define post_code(value) \ movb $value, %al; \ Modified: trunk/src/mainboard/amd/db800/romstage.c ============================================================================== --- trunk/src/mainboard/amd/db800/romstage.c Mon Apr 11 21:43:50 2011 (r6486) +++ trunk/src/mainboard/amd/db800/romstage.c Mon Apr 11 22:17:22 2011 (r6487) @@ -28,7 +28,6 @@ #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h> -#include <cpu/amd/geode_post_code.h> #include "southbridge/amd/cs5536/cs5536.h" #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" @@ -56,7 +55,6 @@ void main(unsigned long bist) { - post_code(0x01); static const struct mem_controller memctrl[] = { {.channel0 = {DIMM0, DIMM1}} Modified: trunk/src/mainboard/amd/norwich/romstage.c ============================================================================== --- trunk/src/mainboard/amd/norwich/romstage.c Mon Apr 11 21:43:50 2011 (r6486) +++ trunk/src/mainboard/amd/norwich/romstage.c Mon Apr 11 22:17:22 2011 (r6487) @@ -28,7 +28,6 @@ #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h> -#include <cpu/amd/geode_post_code.h> #include "southbridge/amd/cs5536/cs5536.h" #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" @@ -53,7 +52,6 @@ void main(unsigned long bist) { - post_code(0x01); static const struct mem_controller memctrl[] = { {.channel0 = {DIMM0, DIMM1}} Modified: trunk/src/mainboard/amd/rumba/romstage.c ============================================================================== --- trunk/src/mainboard/amd/rumba/romstage.c Mon Apr 11 21:43:50 2011 (r6486) +++ trunk/src/mainboard/amd/rumba/romstage.c Mon Apr 11 22:17:22 2011 (r6487) @@ -8,7 +8,6 @@ #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/gx2def.h> -#include <cpu/amd/geode_post_code.h> #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" #include "southbridge/amd/cs5536/early_setup.c" Modified: trunk/src/mainboard/artecgroup/dbe61/romstage.c ============================================================================== --- trunk/src/mainboard/artecgroup/dbe61/romstage.c Mon Apr 11 21:43:50 2011 (r6486) +++ trunk/src/mainboard/artecgroup/dbe61/romstage.c Mon Apr 11 22:17:22 2011 (r6487) @@ -29,7 +29,6 @@ #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h> -#include <cpu/amd/geode_post_code.h> #include "southbridge/amd/cs5536/cs5536.h" #include "spd_table.h" #include <spd.h> @@ -68,7 +67,6 @@ void main(unsigned long bist) { - post_code(0x01); msr_t msr; static const struct mem_controller memctrl[] = { Modified: trunk/src/mainboard/digitallogic/msm800sev/romstage.c ============================================================================== --- trunk/src/mainboard/digitallogic/msm800sev/romstage.c Mon Apr 11 21:43:50 2011 (r6486) +++ trunk/src/mainboard/digitallogic/msm800sev/romstage.c Mon Apr 11 22:17:22 2011 (r6487) @@ -9,7 +9,6 @@ #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h> -#include <cpu/amd/geode_post_code.h> #include "southbridge/amd/cs5536/cs5536.h" #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" @@ -37,7 +36,6 @@ void main(unsigned long bist) { - post_code(0x01); static const struct mem_controller memctrl [] = { {.channel0 = {DIMM0, DIMM1}} @@ -79,7 +77,6 @@ We use method 1 on Norwich. */ post_code(0x02); - print_err("POST 02\n"); __asm__("wbinvd\n"); print_err("Past wbinvd\n"); /* we are finding the return does not work on this board. Explicitly call the label that is Modified: trunk/src/mainboard/iei/pcisa-lx-800-r10/romstage.c ============================================================================== --- trunk/src/mainboard/iei/pcisa-lx-800-r10/romstage.c Mon Apr 11 21:43:50 2011 (r6486) +++ trunk/src/mainboard/iei/pcisa-lx-800-r10/romstage.c Mon Apr 11 22:17:22 2011 (r6487) @@ -28,7 +28,6 @@ #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h> -#include <cpu/amd/geode_post_code.h> #include "southbridge/amd/cs5536/cs5536.h" #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" @@ -60,7 +59,6 @@ void main(unsigned long bist) { - post_code(0x01); static const struct mem_controller memctrl[] = { {.channel0 = {DIMM0, DIMM1}} Modified: trunk/src/mainboard/lippert/frontrunner/romstage.c ============================================================================== --- trunk/src/mainboard/lippert/frontrunner/romstage.c Mon Apr 11 21:43:50 2011 (r6486) +++ trunk/src/mainboard/lippert/frontrunner/romstage.c Mon Apr 11 22:17:22 2011 (r6487) @@ -9,7 +9,6 @@ #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/gx2def.h> -#include <cpu/amd/geode_post_code.h> #include "southbridge/amd/cs5535/cs5535.h" #include "southbridge/amd/cs5535/early_smbus.c" #include "southbridge/amd/cs5535/early_setup.c" Modified: trunk/src/mainboard/lippert/hurricane-lx/romstage.c ============================================================================== --- trunk/src/mainboard/lippert/hurricane-lx/romstage.c Mon Apr 11 21:43:50 2011 (r6486) +++ trunk/src/mainboard/lippert/hurricane-lx/romstage.c Mon Apr 11 22:17:22 2011 (r6487) @@ -31,7 +31,6 @@ #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h> -#include <cpu/amd/geode_post_code.h> #include "southbridge/amd/cs5536/cs5536.h" #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" @@ -118,7 +117,6 @@ void main(unsigned long bist) { - post_code(0x01); static const struct mem_controller memctrl[] = { {.channel0 = {DIMM0, DIMM1}} Modified: trunk/src/mainboard/lippert/literunner-lx/romstage.c ============================================================================== --- trunk/src/mainboard/lippert/literunner-lx/romstage.c Mon Apr 11 21:43:50 2011 (r6486) +++ trunk/src/mainboard/lippert/literunner-lx/romstage.c Mon Apr 11 22:17:22 2011 (r6487) @@ -32,7 +32,6 @@ #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h> -#include <cpu/amd/geode_post_code.h> #include "southbridge/amd/cs5536/cs5536.h" #include "southbridge/amd/cs5536/early_smbus.c" #include "southbridge/amd/cs5536/early_setup.c" @@ -161,7 +160,6 @@ void main(unsigned long bist) { int err; - post_code(0x01); static const struct mem_controller memctrl[] = { {.channel0 = {DIMM0, DIMM1}} Modified: trunk/src/mainboard/lippert/roadrunner-lx/romstage.c ============================================================================== --- trunk/src/mainboard/lippert/roadrunner-lx/romstage.c Mon Apr 11 21:43:50 2011 (r6486) +++ trunk/src/mainboard/lippert/roadrunner-lx/romstage.c Mon Apr 11 22:17:22 2011 (r6487) @@ -31,7 +31,6 @@ #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h> -#include <cpu/amd/geode_post_code.h> #include "southbridge/amd/cs5536/cs5536.h" #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" @@ -93,7 +92,6 @@ void main(unsigned long bist) { - post_code(0x01); static const struct mem_controller memctrl[] = { {.channel0 = {DIMM0, DIMM1}} Modified: trunk/src/mainboard/lippert/spacerunner-lx/romstage.c ============================================================================== --- trunk/src/mainboard/lippert/spacerunner-lx/romstage.c Mon Apr 11 21:43:50 2011 (r6486) +++ trunk/src/mainboard/lippert/spacerunner-lx/romstage.c Mon Apr 11 22:17:22 2011 (r6487) @@ -32,7 +32,6 @@ #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h> -#include <cpu/amd/geode_post_code.h> #include "southbridge/amd/cs5536/cs5536.h" #include "southbridge/amd/cs5536/early_smbus.c" #include "southbridge/amd/cs5536/early_setup.c" @@ -158,7 +157,6 @@ void main(unsigned long bist) { int err; - post_code(0x01); static const struct mem_controller memctrl[] = { {.channel0 = {DIMM0, DIMM1}} Modified: trunk/src/mainboard/pcengines/alix1c/romstage.c ============================================================================== --- trunk/src/mainboard/pcengines/alix1c/romstage.c Mon Apr 11 21:43:50 2011 (r6486) +++ trunk/src/mainboard/pcengines/alix1c/romstage.c Mon Apr 11 22:17:22 2011 (r6487) @@ -30,7 +30,6 @@ #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h> -#include <cpu/amd/geode_post_code.h> #include "southbridge/amd/cs5536/cs5536.h" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) @@ -118,8 +117,6 @@ {.channel0 = {DIMM0}}, }; - post_code(0x01); - SystemPreInit(); msr_init(); Modified: trunk/src/mainboard/pcengines/alix2d/romstage.c ============================================================================== --- trunk/src/mainboard/pcengines/alix2d/romstage.c Mon Apr 11 21:43:50 2011 (r6486) +++ trunk/src/mainboard/pcengines/alix2d/romstage.c Mon Apr 11 22:17:22 2011 (r6487) @@ -30,7 +30,6 @@ #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h> -#include <cpu/amd/geode_post_code.h> #include "southbridge/amd/cs5536/cs5536.h" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) @@ -142,8 +141,6 @@ {.channel0 = {DIMM0}}, }; - post_code(0x01); - SystemPreInit(); msr_init(); Modified: trunk/src/mainboard/traverse/geos/romstage.c ============================================================================== --- trunk/src/mainboard/traverse/geos/romstage.c Mon Apr 11 21:43:50 2011 (r6486) +++ trunk/src/mainboard/traverse/geos/romstage.c Mon Apr 11 22:17:22 2011 (r6487) @@ -29,7 +29,6 @@ #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h> -#include <cpu/amd/geode_post_code.h> #include "southbridge/amd/cs5536/cs5536.h" #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" @@ -54,8 +53,6 @@ void main(unsigned long bist) { - post_code(0x01); - static const struct mem_controller memctrl[] = { {.channel0 = {DIMM0, DIMM1}} }; Modified: trunk/src/mainboard/winent/pl6064/romstage.c ============================================================================== --- trunk/src/mainboard/winent/pl6064/romstage.c Mon Apr 11 21:43:50 2011 (r6486) +++ trunk/src/mainboard/winent/pl6064/romstage.c Mon Apr 11 22:17:22 2011 (r6487) @@ -30,7 +30,6 @@ #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h> -#include <cpu/amd/geode_post_code.h> #include "southbridge/amd/cs5536/cs5536.h" #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" @@ -58,7 +57,6 @@ void main(unsigned long bist) { - post_code(0x01); static const struct mem_controller memctrl[] = { {.channel0 = {DIMM0, DIMM1}} Modified: trunk/src/mainboard/wyse/s50/romstage.c ============================================================================== --- trunk/src/mainboard/wyse/s50/romstage.c Mon Apr 11 21:43:50 2011 (r6486) +++ trunk/src/mainboard/wyse/s50/romstage.c Mon Apr 11 22:17:22 2011 (r6487) @@ -29,7 +29,6 @@ #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/gx2def.h> -#include <cpu/amd/geode_post_code.h> #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" #include "southbridge/amd/cs5536/early_setup.c" Modified: trunk/src/northbridge/amd/gx1/raminit.c ============================================================================== --- trunk/src/northbridge/amd/gx1/raminit.c Mon Apr 11 21:43:50 2011 (r6486) +++ trunk/src/northbridge/amd/gx1/raminit.c Mon Apr 11 22:17:22 2011 (r6487) @@ -46,12 +46,12 @@ { unsigned int tval, i; - outb(0x71, 0x80); + post_code(0x71); tval = getGX1Mem(GX_BASE + MC_MEM_CNTRL1); tval |= RFSHTST; for(i=0; i>NUM_REFRESH; i++) setGX1Mem(GX_BASE + MC_MEM_CNTRL1, tval); - outb(0x72, 0x80); + post_code(0x72); } @@ -59,7 +59,7 @@ { unsigned int tval, i; - outb(0x73, 0x80); + post_code(0x73); /* start SDCLCK's */ tval = getGX1Mem(GX_BASE + MC_MEM_CNTRL1); @@ -101,7 +101,7 @@ for(i=0; i<2000; i++) outb(0, 0xed); - outb(0x74, 0x80); + post_code(0x74); } static unsigned int size_dimm(int dimm_shift) @@ -321,7 +321,7 @@ unsigned int mem_config = 0x00700070; print_debug("Setting up default parameters for memory\n"); - outb(0x70, 0x80); + post_code(0x70); setGX1Mem(GX_BASE + MC_MEM_CNTRL2, 0x000007d8); /* Disable all CLKS, Shift = 3 */ setGX1Mem(GX_BASE + MC_MEM_CNTRL1, 0x92140000); /* MD_DS=2, MA_DS=2, CNTL_DS=2 SDCLKRATE=4 */ @@ -350,5 +350,5 @@ setGX1Mem(GX_BASE + MC_BANK_CFG, mem_config); enable_dimm(); - outb(0x7e, 0x80); + post_code(0x7e); } Modified: trunk/src/northbridge/via/cx700/early_serial.c ============================================================================== --- trunk/src/northbridge/via/cx700/early_serial.c Mon Apr 11 21:43:50 2011 (r6486) +++ trunk/src/northbridge/via/cx700/early_serial.c Mon Apr 11 22:17:22 2011 (r6487) @@ -47,7 +47,7 @@ static void enable_cx700_serial(void) { - outb(6, 0x80); + post_code(0x06); // WTH? outb(0x03, 0x22); @@ -98,5 +98,5 @@ // should be done. Dump a char for fun. cx700_writesiobyte(0x3f8, 48); - outb(7, 0x80); + post_code(0x07); } Modified: trunk/src/northbridge/via/vx800/early_serial.c ============================================================================== --- trunk/src/northbridge/via/vx800/early_serial.c Mon Apr 11 21:43:50 2011 (r6486) +++ trunk/src/northbridge/via/vx800/early_serial.c Mon Apr 11 22:17:22 2011 (r6487) @@ -55,7 +55,7 @@ void enable_vx800_serial(void) { - outb(6, 0x80); + post_code(0x06); outb(0x03, 0x22); //pci_write_config8(PCI_DEV(0,17,0),0xb4,0x7e); @@ -97,5 +97,5 @@ vx800_writesiobyte(0x3f9, 0xf); // should be done. Dump a char for fun. vx800_writesiobyte(0x3f8, 48); - outb(7, 0x80); + post_code(0x07); } Modified: trunk/src/southbridge/amd/cs5535/chipsetinit.c ============================================================================== --- trunk/src/southbridge/amd/cs5535/chipsetinit.c Mon Apr 11 21:43:50 2011 (r6486) +++ trunk/src/southbridge/amd/cs5535/chipsetinit.c Mon Apr 11 22:17:22 2011 (r6487) @@ -10,7 +10,6 @@ #include "chip.h" #include "northbridge/amd/gx2/northbridge.h" #include <cpu/amd/gx2def.h> -#include <cpu/amd/geode_post_code.h> #include <cpu/x86/msr.h> #include <cpu/x86/cache.h> #include "southbridge/amd/cs5535/cs5535.h" @@ -277,7 +276,7 @@ return; } - outb( P80_CHIPSET_INIT, 0x80); + post_code(P80_CHIPSET_INIT); ChipsetGeodeLinkInit(); #ifdef UNUSED_CODE Modified: trunk/src/southbridge/amd/cs5536/cs5536.c ============================================================================== --- trunk/src/southbridge/amd/cs5536/cs5536.c Mon Apr 11 21:43:50 2011 (r6486) +++ trunk/src/southbridge/amd/cs5536/cs5536.c Mon Apr 11 22:17:22 2011 (r6487) @@ -30,7 +30,6 @@ #include <pc80/i8259.h> #include <cpu/x86/msr.h> #include <cpu/amd/vr.h> -#include <cpu/amd/geode_post_code.h> #include <stdlib.h> #include "chip.h" #include "cs5536.h" Modified: trunk/src/southbridge/via/vt8231/early_serial.c ============================================================================== --- trunk/src/southbridge/via/vt8231/early_serial.c Mon Apr 11 21:43:50 2011 (r6486) +++ trunk/src/southbridge/via/vt8231/early_serial.c Mon Apr 11 22:17:22 2011 (r6487) @@ -1,3 +1,4 @@ +#include <console/console.h> /* * Enable the serial evices on the VIA */ @@ -33,11 +34,11 @@ { uint8_t c; device_t dev; - outb(6, 0x80); + post_code(0x06); dev = pci_locate_device(PCI_ID(0x1106,0x8231), 0); if (dev == PCI_DEV_INVALID) { - outb(7, 0x80); + post_code(0x07); die("Serial controller not found\n"); } @@ -47,7 +48,7 @@ c = pci_read_config8(dev, 0x50); c |= 6; pci_write_config8(dev, 0x50, c); - outb(2, 0x80); + post_code(0x02); // now go ahead and set up com1. // set address vt8231_writesuper(0xf4, 0xfe);

1 0

[commit] r6486 - in trunk/src: ec/lenovo/pmh7 mainboard/lenovo/x60
by repository service 11 Apr '11

11 Apr '11

Author: svens Date: Mon Apr 11 21:43:50 2011 New Revision: 6486 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6486 Log: PMH7: Add chip config Signed-off-by: Sven Schnelle <svens(a)stackframe.org> Acked-by: Peter Stuge <peter(a)stuge.se> Added: trunk/src/ec/lenovo/pmh7/chip.h Modified: trunk/src/ec/lenovo/pmh7/pmh7.c trunk/src/ec/lenovo/pmh7/pmh7.h trunk/src/mainboard/lenovo/x60/devicetree.cb trunk/src/mainboard/lenovo/x60/mainboard.c Added: trunk/src/ec/lenovo/pmh7/chip.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/ec/lenovo/pmh7/chip.h Mon Apr 11 21:43:50 2011 (r6486) @@ -0,0 +1,9 @@ +#ifndef EC_LENOVO_PMH7_CHIP_H +#define EC_LENOVO_PMH7_CHIP_H + +extern struct chip_operations ec_lenovo_pmh7_ops; + +struct ec_lenovo_pmh7_config { + int backlight_enable:1; +}; +#endif Modified: trunk/src/ec/lenovo/pmh7/pmh7.c ============================================================================== --- trunk/src/ec/lenovo/pmh7/pmh7.c Mon Apr 11 21:43:32 2011 (r6485) +++ trunk/src/ec/lenovo/pmh7/pmh7.c Mon Apr 11 21:43:50 2011 (r6486) @@ -23,6 +23,15 @@ #include <device/pnp.h> #include <stdlib.h> #include "pmh7.h" +#include "chip.h" + +void pmh7_backlight_enable(int onoff) +{ + if (onoff) + pmh7_register_set_bit(0x50, 5); + else + pmh7_register_clear_bit(0x50, 5); +} void pmh7_register_set_bit(int reg, int bit) { @@ -58,6 +67,7 @@ static void enable_dev(device_t dev) { + struct ec_lenovo_pmh7_config *conf = dev->chip_info; struct resource *resource; resource = new_resource(dev, EC_LENOVO_PMH7_INDEX); @@ -66,6 +76,8 @@ resource->size = 16; resource->align = 5; resource->gran = 5; + + pmh7_backlight_enable(conf->backlight_enable); } struct chip_operations ec_lenovo_pmh7_ops = { Modified: trunk/src/ec/lenovo/pmh7/pmh7.h ============================================================================== --- trunk/src/ec/lenovo/pmh7/pmh7.h Mon Apr 11 21:43:32 2011 (r6485) +++ trunk/src/ec/lenovo/pmh7/pmh7.h Mon Apr 11 21:43:50 2011 (r6486) @@ -31,4 +31,5 @@ char pmh7_register_read(int reg); void pmh7_register_write(int reg, int val); +void pmh7_backlight_enable(int onoff); #endif Modified: trunk/src/mainboard/lenovo/x60/devicetree.cb ============================================================================== --- trunk/src/mainboard/lenovo/x60/devicetree.cb Mon Apr 11 21:43:32 2011 (r6485) +++ trunk/src/mainboard/lenovo/x60/devicetree.cb Mon Apr 11 21:43:50 2011 (r6486) @@ -85,6 +85,7 @@ chip ec/lenovo/pmh7 device pnp ff.1 on # dummy end + register "backlight_enable" = "0x01" end chip ec/lenovo/h8 device pnp ff.2 on # dummy Modified: trunk/src/mainboard/lenovo/x60/mainboard.c ============================================================================== --- trunk/src/mainboard/lenovo/x60/mainboard.c Mon Apr 11 21:43:32 2011 (r6485) +++ trunk/src/mainboard/lenovo/x60/mainboard.c Mon Apr 11 21:43:50 2011 (r6486) @@ -35,17 +35,10 @@ #include <ec/lenovo/h8/h8.h> #include <northbridge/intel/i945/i945.h> -static void backlight_enable(void) -{ - pmh7_register_set_bit(0x50, 5); -} - static void mainboard_enable(device_t dev) { device_t dev0; - backlight_enable(); - /* enable Audio */ h8_set_audio_mute(0);

1 0

[commit] r6485 - in trunk/src: ec/lenovo ec/lenovo/h8 ec/lenovo/h8/acpi mainboard/lenovo/x60 mainboard/lenovo/x60/acpi
by repository service 11 Apr '11

11 Apr '11

Author: svens Date: Mon Apr 11 21:43:32 2011 New Revision: 6485 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6485 Log: EC: Add Lenovo H8 Move the EC support code from the X60 mainboard to a generic driver, as this EC is used in many thinkpads. Also move the ACPI code to this directory for this reason. This patch also adds a chip config, so that the initial setting for basic register can be specified in devicetree.cb Signed-off-by: Sven Schnelle <svens(a)stackframe.org> Acked-by: Peter Stuge <peter(a)stuge.se> Added: trunk/src/ec/lenovo/h8/ trunk/src/ec/lenovo/h8/Kconfig trunk/src/ec/lenovo/h8/Makefile.inc trunk/src/ec/lenovo/h8/acpi/ trunk/src/ec/lenovo/h8/acpi/ac.asl - copied, changed from r6483, trunk/src/mainboard/lenovo/x60/acpi/ac.asl trunk/src/ec/lenovo/h8/acpi/battery.asl - copied, changed from r6483, trunk/src/mainboard/lenovo/x60/acpi/battery.asl trunk/src/ec/lenovo/h8/acpi/beep.asl - copied, changed from r6483, trunk/src/mainboard/lenovo/x60/acpi/beep.asl trunk/src/ec/lenovo/h8/acpi/ec.asl - copied, changed from r6483, trunk/src/mainboard/lenovo/x60/acpi/ec.asl trunk/src/ec/lenovo/h8/acpi/lid.asl - copied, changed from r6483, trunk/src/mainboard/lenovo/x60/acpi/lid.asl trunk/src/ec/lenovo/h8/acpi/sleepbutton.asl - copied, changed from r6483, trunk/src/mainboard/lenovo/x60/acpi/sleepbutton.asl trunk/src/ec/lenovo/h8/acpi/systemstatus.asl - copied, changed from r6483, trunk/src/mainboard/lenovo/x60/acpi/systemstatus.asl trunk/src/ec/lenovo/h8/acpi/thermal.asl - copied, changed from r6483, trunk/src/mainboard/lenovo/x60/acpi/thermal.asl trunk/src/ec/lenovo/h8/chip.h trunk/src/ec/lenovo/h8/h8.c trunk/src/ec/lenovo/h8/h8.h Deleted: trunk/src/mainboard/lenovo/x60/acpi/ac.asl trunk/src/mainboard/lenovo/x60/acpi/battery.asl trunk/src/mainboard/lenovo/x60/acpi/beep.asl trunk/src/mainboard/lenovo/x60/acpi/lid.asl trunk/src/mainboard/lenovo/x60/acpi/sleepbutton.asl trunk/src/mainboard/lenovo/x60/acpi/systemstatus.asl trunk/src/mainboard/lenovo/x60/acpi/thermal.asl Modified: trunk/src/ec/lenovo/Kconfig trunk/src/ec/lenovo/Makefile.inc trunk/src/mainboard/lenovo/x60/Kconfig trunk/src/mainboard/lenovo/x60/acpi/dock.asl trunk/src/mainboard/lenovo/x60/acpi/ec.asl trunk/src/mainboard/lenovo/x60/acpi/gpe.asl trunk/src/mainboard/lenovo/x60/devicetree.cb trunk/src/mainboard/lenovo/x60/dsdt.asl trunk/src/mainboard/lenovo/x60/mainboard.c Modified: trunk/src/ec/lenovo/Kconfig ============================================================================== --- trunk/src/ec/lenovo/Kconfig Mon Apr 11 09:46:27 2011 (r6484) +++ trunk/src/ec/lenovo/Kconfig Mon Apr 11 21:43:32 2011 (r6485) @@ -1 +1,2 @@ +source src/ec/lenovo/h8/Kconfig source src/ec/lenovo/pmh7/Kconfig Modified: trunk/src/ec/lenovo/Makefile.inc ============================================================================== --- trunk/src/ec/lenovo/Makefile.inc Mon Apr 11 09:46:27 2011 (r6484) +++ trunk/src/ec/lenovo/Makefile.inc Mon Apr 11 21:43:32 2011 (r6485) @@ -1 +1,2 @@ +subdirs-$(CONFIG_EC_LENOVO_H8) += h8 subdirs-$(CONFIG_EC_LENOVO_PMH7) += pmh7 Added: trunk/src/ec/lenovo/h8/Kconfig ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/ec/lenovo/h8/Kconfig Mon Apr 11 21:43:32 2011 (r6485) @@ -0,0 +1,3 @@ +config EC_LENOVO_H8 + select EC_ACPI + bool Added: trunk/src/ec/lenovo/h8/Makefile.inc ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/ec/lenovo/h8/Makefile.inc Mon Apr 11 21:43:32 2011 (r6485) @@ -0,0 +1 @@ +driver-y += h8.c Copied and modified: trunk/src/ec/lenovo/h8/acpi/ac.asl (from r6483, trunk/src/mainboard/lenovo/x60/acpi/ac.asl) ============================================================================== Copied and modified: trunk/src/ec/lenovo/h8/acpi/battery.asl (from r6483, trunk/src/mainboard/lenovo/x60/acpi/battery.asl) ============================================================================== Copied and modified: trunk/src/ec/lenovo/h8/acpi/beep.asl (from r6483, trunk/src/mainboard/lenovo/x60/acpi/beep.asl) ============================================================================== Copied and modified: trunk/src/ec/lenovo/h8/acpi/ec.asl (from r6483, trunk/src/mainboard/lenovo/x60/acpi/ec.asl) ============================================================================== --- trunk/src/mainboard/lenovo/x60/acpi/ec.asl Sun Apr 10 09:41:56 2011 (r6483, copy source) +++ trunk/src/ec/lenovo/h8/acpi/ec.asl Mon Apr 11 21:43:32 2011 (r6485) @@ -54,7 +54,7 @@ Name (ECMD, ResourceTemplate() { IO (Decode16, 0x62, 0x62, 1, 1) - IO (Decode16, 0x66, 0x66, 1, 1) + IO (Decode16, 0x66, 0x66, 1, 1) }) Return (ECMD) } @@ -91,11 +91,6 @@ \DSPC.BRTD() } - Method(_Q18, 0, NotSerialized) - { - Notify(\_SB.PCI0.LPCB.EC.DOCK, 3) - } - /* AC status change: present */ Method(_Q26, 0, NotSerialized) { @@ -124,5 +119,4 @@ #include "sleepbutton.asl" #include "lid.asl" #include "beep.asl" -#include "dock.asl" } Copied and modified: trunk/src/ec/lenovo/h8/acpi/lid.asl (from r6483, trunk/src/mainboard/lenovo/x60/acpi/lid.asl) ============================================================================== Copied and modified: trunk/src/ec/lenovo/h8/acpi/sleepbutton.asl (from r6483, trunk/src/mainboard/lenovo/x60/acpi/sleepbutton.asl) ============================================================================== Copied and modified: trunk/src/ec/lenovo/h8/acpi/systemstatus.asl (from r6483, trunk/src/mainboard/lenovo/x60/acpi/systemstatus.asl) ============================================================================== --- trunk/src/mainboard/lenovo/x60/acpi/systemstatus.asl Sun Apr 10 09:41:56 2011 (r6483, copy source) +++ trunk/src/ec/lenovo/h8/acpi/systemstatus.asl Mon Apr 11 21:43:32 2011 (r6485) @@ -59,8 +59,5 @@ /* suspend LED on */ \_SB.PCI0.LPCB.EC.LED(0x87) } - - - } } Copied and modified: trunk/src/ec/lenovo/h8/acpi/thermal.asl (from r6483, trunk/src/mainboard/lenovo/x60/acpi/thermal.asl) ============================================================================== Added: trunk/src/ec/lenovo/h8/chip.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/ec/lenovo/h8/chip.h Mon Apr 11 21:43:32 2011 (r6485) @@ -0,0 +1,36 @@ +#ifndef EC_LENOVO_H8EC_CHIP_H +#define EC_LENOVO_H8EC_CHIP_H + +extern struct chip_operations ec_lenovo_h8_ops; +struct ec_lenovo_h8_config { + + u8 config0; + u8 config1; + u8 config2; + u8 config3; + + u8 beepmask0; + u8 beepmask1; + + u8 event0_enable; + u8 event1_enable; + u8 event2_enable; + u8 event3_enable; + u8 event4_enable; + u8 event5_enable; + u8 event6_enable; + u8 event7_enable; + u8 event8_enable; + u8 event9_enable; + u8 eventa_enable; + u8 eventb_enable; + u8 eventc_enable; + u8 eventd_enable; + u8 evente_enable; + u8 eventf_enable; + + u8 trackpoint_enable; + u8 wlan_enable; + u8 wwan_enable; +}; +#endif Added: trunk/src/ec/lenovo/h8/h8.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/ec/lenovo/h8/h8.c Mon Apr 11 21:43:32 2011 (r6485) @@ -0,0 +1,129 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <device/device.h> +#include <ec/acpi/ec.h> +#include <device/pnp.h> +#include <stdlib.h> +#include "h8.h" +#include "chip.h" + +void h8_trackpoint_enable(int on) +{ + ec_write(H8_TRACKPOINT_CTRL, + on ? H8_TRACKPOINT_ON : H8_TRACKPOINT_OFF); + +} + +void h8_wlan_enable(int on) +{ + if (on) + ec_set_bit(0x3a, 5); + else + ec_clr_bit(0x3a, 5); +} + +static void h8_log_ec_version(void) +{ + unsigned char ecfw[9], c; + u16 fwvh, fwvl; + int i; + + for(i = 0; i < 8; i++) { + c = ec_read(0xf0 + i); + if (c < 0x20 || c > 0x7f) + break; + ecfw[i] = c; + } + ecfw[i] = '\0'; + + fwvh = ec_read(0xe9); + fwvl = ec_read(0xe8); + + printk(BIOS_INFO, "EC Firmware ID %s, Version %d.%d%d%c\n", ecfw, + fwvh >> 4, fwvh & 0x0f, fwvl >> 4, 0x41 + (fwvl & 0xf)); +} + +void h8_set_audio_mute(int on) +{ + if (on) + ec_clr_bit(0x3a, 0); + else + ec_set_bit(0x3a, 1); +} + +void h8_enable_event(int event) +{ + if (event < 0 || event > 127) + return; + + ec_set_bit(0x10 + (event >> 3), event & 7); +} + +void h8_disable_event(int event) +{ + if (event < 0 || event > 127) + return; + + ec_clr_bit(0x10 + (event >> 3), event & 7); + +} + +static void h8_enable(device_t dev) +{ + struct ec_lenovo_h8_config *conf = dev->chip_info; + h8_log_ec_version(); + + ec_write(H8_CONFIG0, conf->config0); + ec_write(H8_CONFIG1, conf->config1); + ec_write(H8_CONFIG2, conf->config2); + ec_write(H8_CONFIG3, conf->config3); + + ec_write(H8_SOUND_ENABLE0, conf->beepmask0); + ec_write(H8_SOUND_ENABLE1, conf->beepmask1); + ec_write(H8_SOUND_REPEAT, 0x00); + + ec_write(0x10, conf->event0_enable); + ec_write(0x11, conf->event1_enable); + ec_write(0x12, conf->event2_enable); + ec_write(0x13, conf->event3_enable); + ec_write(0x14, conf->event4_enable); + ec_write(0x15, conf->event5_enable); + ec_write(0x16, conf->event6_enable); + ec_write(0x17, conf->event7_enable); + ec_write(0x18, conf->event8_enable); + ec_write(0x19, conf->event9_enable); + ec_write(0x1a, conf->eventa_enable); + ec_write(0x1b, conf->eventb_enable); + ec_write(0x1c, conf->eventc_enable); + ec_write(0x1d, conf->eventd_enable); + ec_write(0x1e, conf->evente_enable); + ec_write(0x1f, conf->eventf_enable); + + h8_wlan_enable(conf->wlan_enable); + h8_trackpoint_enable(conf->trackpoint_enable); + +} + +struct chip_operations ec_lenovo_h8_ops = { + CHIP_NAME("Lenovo H8 EC") + .enable_dev = h8_enable +}; Added: trunk/src/ec/lenovo/h8/h8.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/ec/lenovo/h8/h8.h Mon Apr 11 21:43:32 2011 (r6485) @@ -0,0 +1,111 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef EC_LENOVO_H8_H +#define EC_LENOVO_H8_H + +void h8_trackpoint_enable(int on); +void h8_wlan_enable(int on); +void h8_set_audio_mute(int on); +void h8_enable_event(int event); +void h8_disable_event(int event); + +/* EC registers */ +#define H8_CONFIG0 0x00 +#define H8_CONFIG0_EVENTS_ENABLE 0x02 +#define H8_CONFIG0_HOTKEY_ENABLE 0x04 +#define H8_CONFIG0_SMM_H8_ENABLE 0x20 +#define H8_CONFIG0_TC_ENABLE 0x80 + +#define H8_CONFIG1 0x01 +#define H8_CONFIG1_BKLT_LID 0x01 +#define H8_CONFIG1_UBAY_PWR 0x20 + +#define H8_CONFIG2 0x02 +#define H8_CONFIG2_USB_DOCK 0x01 +#define H8_CONFIG2_DOCK_SPEAKER_MUTE 0x02 +#define H8_CONFIG2_DOCK_SPEAKER_MUTE_POL 0x04 + +#define H8_CONFIG3 0x03 + +#define H8_SOUND_ENABLE0 0x04 +#define H8_SOUND_ENABLE1 0x05 +#define H8_SOUND_REG 0x06 +#define H8_SOUND_REPEAT 0x07 + +#define H8_TRACKPOINT_CTRL 0x0B +#define H8_TRACKPOINT_AUTO 0x01 +#define H8_TRACKPOINT_OFF 0x02 +#define H8_TRACKPOINT_ON 0x03 + +#define H8_LED_CONTROL 0x0c +#define H8_LED_CONTROL_OFF 0x00 +#define H8_LED_CONTROL_ON 0x80 +#define H8_LED_CONTROL_BLINK 0xc0 + +#define H8_LED_CONTROL_POWER_LED 0x00 +#define H8_LED_CONTROL_BAT0_LED 0x01 +#define H8_LED_CONTROL_BAT1_LED 0x02 +#define H8_LED_CONTROL_UBAY_LED 0x04 +#define H8_LED_CONTROL_SUSPEND_LED 0x07 +#define H8_LED_CONTROL_DOCK_LED1 0x08 +#define H8_LED_CONTROL_DOCK_LED2 0x09 + +/* Embedded controller events */ +#define H8_EVENT_FN_F1 0x10 +#define H8_EVENT_FN_F2 0x11 +#define H8_EVENT_FN_F3 0x12 +#define H8_EVENT_FN_F4 0x13 +#define H8_EVENT_FN_HOME 0x14 +#define H8_EVENT_FN_END 0x15 +#define H8_EVENT_FN_F7 0x16 +#define H8_EVENT_FN_F8 0x17 +#define H8_EVENT_FN_F9 0x18 +#define H8_EVENT_FN_THINKVANTAGE 0x19 +#define H8_EVENT_FN_F11 0x1a +#define H8_EVENT_FN_F12 0x1b +#define H8_EVENT_FN_1 0x1c +#define H8_EVENT_FN_2 0x1d +#define H8_EVENT_FN_PGUP 0x1f + +#define H8_EVENT_AC_ON 0x26 +#define H8_EVENT_AC_OFF 0x27 + +#define H8_EVENT_PWRSW_PRESS 0x28 +#define H8_EVENT_PWRSW_RELEASE 0x29 + +#define H8_EVENT_LIDSW_CLOSE 0x2a +#define H8_EVENT_LIDSW_PUSH 0x2b + +#define H8_EVENT_UBAY_UNLOCK 0x2c +#define H8_EVENT_UBAY_LOCK 0x2d + +#define H8_EVENT_KEYPRESS 0x33 + +#define H8_EVENT_FN_PRESS 0x39 + +#define H8_EVENT_BAT0 0x4a +#define H8_EVENT_BAT0_STATE 0x4b + +#define H8_EVENT_BAT1 0x4c +#define H8_EVENT_BAT1_STATE 0x4d + +#define H8_EVENT_FN_F5 0x64 +#define H8_EVENT_FN_F6 0x65 +#endif Modified: trunk/src/mainboard/lenovo/x60/Kconfig ============================================================================== --- trunk/src/mainboard/lenovo/x60/Kconfig Mon Apr 11 09:46:27 2011 (r6484) +++ trunk/src/mainboard/lenovo/x60/Kconfig Mon Apr 11 21:43:32 2011 (r6485) @@ -11,7 +11,7 @@ select SUPERIO_NSC_PC87382 select SUPERIO_NSC_PC87392 select EC_LENOVO_PMH7 - select EC_ACPI + select EC_LENOVO_H8 select BOARD_HAS_FADT select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE Modified: trunk/src/mainboard/lenovo/x60/acpi/dock.asl ============================================================================== --- trunk/src/mainboard/lenovo/x60/acpi/dock.asl Mon Apr 11 09:46:27 2011 (r6484) +++ trunk/src/mainboard/lenovo/x60/acpi/dock.asl Mon Apr 11 21:43:32 2011 (r6485) @@ -21,35 +21,47 @@ #include "smi.h" -OperationRegion (DLPC, SystemIO, 0x164c, 1) -Field(DLPC, ByteAcc, NoLock, Preserve) +Scope (\_SB) { - , 3, - DSTA, 1, -} -Device(DOCK) -{ - Name(_HID, "ACPI0003") - Name(_UID, 0x00) - Name(_PCL, Package() { \_SB } ) + OperationRegion (DLPC, SystemIO, 0x164c, 1) + Field(DLPC, ByteAcc, NoLock, Preserve) + { + , 3, + DSTA, 1, + } - Method(_DCK, 1, NotSerialized) + Device(DOCK) { - if (Arg0) { - Sleep(250) - /* connect dock */ - TRAP(SMI_DOCK_CONNECT) - } else { - /* disconnect dock */ - TRAP(SMI_DOCK_DISCONNECT) + Name(_HID, "ACPI0003") + Name(_UID, 0x00) + Name(_PCL, Package() { \_SB } ) + + Method(_DCK, 1, NotSerialized) + { + if (Arg0) { + Sleep(250) + /* connect dock */ + TRAP(SMI_DOCK_CONNECT) + } else { + /* disconnect dock */ + TRAP(SMI_DOCK_DISCONNECT) + } + + Xor(Arg0, DSTA, Local0) + Return (Local0) } - Xor(Arg0, DSTA, Local0) - Return (Local0) + Method(_STA, 0, NotSerialized) + { + Return (DSTA) + } } +} - Method(_STA, 0, NotSerialized) +Scope(\_SB.PCI0.LPCB.EC) +{ + Method(_Q18, 0, NotSerialized) { - Return (DSTA) + Notify(\_SB.DOCK, 3) } } Modified: trunk/src/mainboard/lenovo/x60/acpi/ec.asl ============================================================================== --- trunk/src/mainboard/lenovo/x60/acpi/ec.asl Mon Apr 11 09:46:27 2011 (r6484) +++ trunk/src/mainboard/lenovo/x60/acpi/ec.asl Mon Apr 11 21:43:32 2011 (r6485) @@ -1,128 +1 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#include "smi.h" -Device(EC) -{ - Name (_HID, EISAID("PNP0C09")) - Name (_UID, 0) - - Name (_GPE, 28) - Mutex (ECLK, 0) - - OperationRegion(ERAM, EmbeddedControl, 0x00, 0x100) - Field (ERAM, ByteAcc, NoLock, Preserve) - { - Offset (0x05), - HSPA, 1, - Offset (0x0C), - LEDS, 8, /* LED state */ - Offset (0x3a), - AMUT, 1, /* Audio Mute */ - Offset (0x3B), - , 1, - KBLT, 1, /* Keyboard Light */ - Offset (0x4e), - WAKE, 16, - Offset (0x78), - TMP0, 8, /* Thermal Zone 0 temperature */ - TMP1, 8, /* Thermal Zone 1 temperature */ - Offset (0x81), - PAGE, 8 /* Information Page Selector */ - } - - Method (_CRS, 0) - { - Name (ECMD, ResourceTemplate() - { - IO (Decode16, 0x62, 0x62, 1, 1) - IO (Decode16, 0x66, 0x66, 1, 1) - }) - Return (ECMD) - } - - Method (LED, 1, NotSerialized) - { - Store(Arg0, LEDS) - } - - Method (_INI, 0, NotSerialized) - { - } - - Method (MUTE, 1, NotSerialized) - { - Store(Arg0, AMUT) - } - - /* Sleep Button pressed */ - Method(_Q13, 0, NotSerialized) - { - Notify(\_SB.PCI0.LPCB.EC.SLPB, 0x80) - } - - /* Brightness up GPE */ - Method(_Q14, 0, NotSerialized) - { - \DSPC.BRTU () - } - - /* Brightness down GPE */ - Method(_Q15, 0, NotSerialized) - { - \DSPC.BRTD() - } - - Method(_Q18, 0, NotSerialized) - { - Notify(\_SB.PCI0.LPCB.EC.DOCK, 3) - } - - /* AC status change: present */ - Method(_Q26, 0, NotSerialized) - { - Notify (AC, 0x80) - } - - /* AC status change: not present */ - Method(_Q27, 0, NotSerialized) - { - Notify (AC, 0x80) - } - - Method(_Q2A, 0, NotSerialized) - { - Notify(\_SB.PCI0.LPCB.EC.LID, 0x80) - } - - Method(_Q2B, 0, NotSerialized) - { - Notify(\_SB.PCI0.LPCB.EC.LID, 0x80) - } - - -#include "ac.asl" -#include "battery.asl" -#include "sleepbutton.asl" -#include "lid.asl" -#include "beep.asl" -#include "dock.asl" -} +#include <ec/lenovo/h8/acpi/ec.asl> Modified: trunk/src/mainboard/lenovo/x60/acpi/gpe.asl ============================================================================== --- trunk/src/mainboard/lenovo/x60/acpi/gpe.asl Mon Apr 11 09:46:27 2011 (r6484) +++ trunk/src/mainboard/lenovo/x60/acpi/gpe.asl Mon Apr 11 21:43:32 2011 (r6485) @@ -12,10 +12,10 @@ { if (GP13) { Or(GIV1, 0x20, GIV1) - Notify(\_SB.PCI0.LPCB.EC.DOCK, 3) + Notify(\_SB.DOCK, 3) } else { And(GIV1, 0xdf, GIV1) - Notify(\_SB.PCI0.LPCB.EC.DOCK, 0) + Notify(\_SB.DOCK, 0) } } } Modified: trunk/src/mainboard/lenovo/x60/devicetree.cb ============================================================================== --- trunk/src/mainboard/lenovo/x60/devicetree.cb Mon Apr 11 09:46:27 2011 (r6484) +++ trunk/src/mainboard/lenovo/x60/devicetree.cb Mon Apr 11 21:43:32 2011 (r6485) @@ -86,13 +86,29 @@ device pnp ff.1 on # dummy end end - chip ec/acpi + chip ec/lenovo/h8 device pnp ff.2 on # dummy io 0x60 = 0x62 io 0x62 = 0x66 io 0x64 = 0x1600 io 0x66 = 0x1604 end + + register "config0" = "0xa6" + register "config1" = "0x05" + register "config2" = "0xa0" + register "config3" = "0x05" + + register "beepmask0" = "0xfe" + register "beepmask1" = "0x96" + + register "event2_enable" = "0xff" + register "event3_enable" = "0xff" + register "event4_enable" = "0xf4" + register "event5_enable" = "0x3c" + + register "wlan_enable" = "0x01" + register "trackpoint_enable" = "0x03" end chip superio/nsc/pc87382 device pnp 164e.2 on # IR Modified: trunk/src/mainboard/lenovo/x60/dsdt.asl ============================================================================== --- trunk/src/mainboard/lenovo/x60/dsdt.asl Mon Apr 11 09:46:27 2011 (r6484) +++ trunk/src/mainboard/lenovo/x60/dsdt.asl Mon Apr 11 21:43:32 2011 (r6485) @@ -40,10 +40,6 @@ // mainboard specific devices #include "acpi/mainboard.asl" - // Thermal Zone - #include "acpi/thermal.asl" - // System status indicators - #include "acpi/systemstatus.asl" Scope (\_SB) { Device (PCI0) { @@ -54,4 +50,7 @@ /* Chipset specific sleep states */ #include "../../../southbridge/intel/i82801gx/acpi/sleepstates.asl" + + // Dock support code + #include "acpi/dock.asl" } Modified: trunk/src/mainboard/lenovo/x60/mainboard.c ============================================================================== --- trunk/src/mainboard/lenovo/x60/mainboard.c Mon Apr 11 09:46:27 2011 (r6484) +++ trunk/src/mainboard/lenovo/x60/mainboard.c Mon Apr 11 21:43:32 2011 (r6485) @@ -32,78 +32,22 @@ #include <arch/io.h> #include <ec/lenovo/pmh7/pmh7.h> #include <ec/acpi/ec.h> +#include <ec/lenovo/h8/h8.h> #include <northbridge/intel/i945/i945.h> static void backlight_enable(void) { - pmh7_register_set_bit(0x50, 5); -} - -static void trackpoint_enable(void) -{ - ec_write(0x0b, 0x03); -} - -static void wlan_enable(void) -{ - ec_write(0x3a, 0x20); -} - -static void log_ec_version(void) -{ - unsigned char ecfw[9], c; - u16 fwvh, fwvl; - int i; - - for(i = 0; i < 8; i++) { - c = ec_read(0xf0 + i); - if (c < 0x20 || c > 0x7f) - break; - ecfw[i] = c; - } - ecfw[i] = '\0'; - - fwvh = ec_read(0xe9); - fwvl = ec_read(0xe8); - - printk(BIOS_INFO, "EC Firmware ID %s, Version %d.%d%d%c\n", ecfw, - fwvh >> 4, fwvh & 0x0f, fwvl >> 4, 0x41 + (fwvl & 0xf)); + pmh7_register_set_bit(0x50, 5); } static void mainboard_enable(device_t dev) { device_t dev0; - log_ec_version(); - backlight_enable(); - trackpoint_enable(); - - /* FIXME: this should be ACPI's task - * but for now, enable it here */ - wlan_enable(); - - /* enable ACPI events */ - ec_write(0x00, 0xa6); - ec_write(0x01, 0x05); - - ec_write(0x02, 0xa0); - ec_write(0x03, 0x05); - - /* set mask of enabled beeps */ - ec_write(0x04, 0xfe); - ec_write(0x05, 0x96); - - /* Unknown, but required for hotkeys - Maybe a mask for enabled keys? */ - - ec_write(0x12, 0xff); - ec_write(0x13, 0xff); - ec_write(0x14, 0xf4); - ec_write(0x15, 0x3c); /* enable Audio */ - ec_clr_bit(0x3a, 0); + h8_set_audio_mute(0); /* If we're resuming from suspend, blink suspend LED */ dev0 = dev_find_slot(0, PCI_DEVFN(0,0));

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coreboot April 2011