coreboot April 2011

coreboot@coreboot.org

66 participants
229 discussions

[commit] r6483 - trunk/src/northbridge/intel/i945
by repository service 10 Apr '11

10 Apr '11

Author: svens Date: Sun Apr 10 09:41:56 2011 New Revision: 6483 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6483 Log: i945: improve get_top_of_ram() The current version doesn't honor TSEG, and fails to report the correct top of RAM if IGD is disabled. This is because it uses the BSM (base of stolen RAM) register. In that case, we should use the TOLUD register. Signed-off-by: Sven Schnelle <svens(a)stackframe.org> Acked-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Modified: trunk/src/northbridge/intel/i945/raminit.c Modified: trunk/src/northbridge/intel/i945/raminit.c ============================================================================== --- trunk/src/northbridge/intel/i945/raminit.c Sun Apr 10 06:15:23 2011 (r6482) +++ trunk/src/northbridge/intel/i945/raminit.c Sun Apr 10 09:41:56 2011 (r6483) @@ -3192,9 +3192,33 @@ unsigned long get_top_of_ram(void) { - /* This will not work if TSEG is in place! */ - u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c); + u32 tom; + if (pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) & ((1 << 4) | (1 << 3))) { + /* IGD enabled, get top of Memory from BSM register */ + tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c); + } else { + tom = (pci_read_config8(PCI_DEV(0,0,0), TOLUD) & 0xf7) << 24; + } + + /* if TSEG enabled subtract size */ + switch(pci_read_config8(PCI_DEV(0, 0, 0), ESMRAM)) { + case 0x01: + /* 1MB TSEG */ + tom -= 0x10000; + break; + case 0x03: + /* 2MB TSEG */ + tom -= 0x20000; + break; + case 0x05: + /* 8MB TSEG */ + tom -= 0x80000; + break; + default: + /* TSEG either disabled or invalid */ + break; + } return (unsigned long) tom; }

1 0

a question about hardware and PCI
by ali hagigat 09 Apr '11

09 Apr '11

I have a general question about a PCI-to-PCI bridge. If the device has a positive decoder and receives an address in the range of the addresses it should respond. Then it claims the address and forwards it to the secondary interface. Now suppose no target on the secondary interface claims the transaction and master-abort happens for the second interface. What will happen to the primary interface then? Why PCI specifications do not explain the connection between the state machines of the primary and secondary interfaces?

2 1

Help for motherboard
by sh4r4d＠gmail.com 09 Apr '11

09 Apr '11

Hi All, I wanted to build a new Desktop workstation with currently available CPU and motherboard that is supported by Coreboot bios, I have searched few links for it e.g. Ubuntu-certified hardware http://www.ubuntu.com/certification/ Zareason http://zareason.com/shop/home.php AMD Processors - Recommended Motherboards http://products.amd.com/pages/recommendedmbfilter.aspx?AspxAutoDetectCookie… But these site mention hardware where gnu/linux could run easily, but they do not inform about coreboot bios compatibility. And checked http://www.coreboot.org/Supported_Motherboards for searching suitable motherboard, seen coreboot related video in youtube. But I did not found here new Intel and AMD cpu for motherboards in Desktop/Workstation section (except Laptop) mentioned for e.g. Intel Core 7i Intel Core 3i and similar AMD's latest. So finally I like to know do these newer CPU's any motherboard going to be supported in near future, So I will purchase that motherboard. I want to find it out as it will be difficult to change hardware than software later. Please suggest which CPU/motherboard combination is good with coreboot. -- Regards, -sharad

5 9

[commit] r6482 - in trunk: . src/arch/x86 src/include src/include/cpu/amd src/include/cpu/x86 src/mainboard/amd/serengeti_cheetah src/mainboard/gigabyte/ga_2761gxdk src/mainboard/gigabyte/m57sli sr...
by repository service 09 Apr '11

09 Apr '11

Author: stepan Date: Sun Apr 10 06:15:23 2011 New Revision: 6482 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6482 Log: In 2007 Adrian Reber suggested that we drop ASSEMBLY in favor of __ASSEMBLER__. http://www.coreboot.org/pipermail/coreboot/2007-September/024665.html It's about time we follow this advice. Also move some manually set __PRE_RAM__ defines (ap_romstage.c) to the Makefile and drop unused CPP define Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Acked-by: Patrick Georgi <patrick(a)georgi-clan.de> Modified: trunk/Makefile trunk/Makefile.inc trunk/src/arch/x86/Makefile.bigbootblock.inc trunk/src/arch/x86/Makefile.bootblock.inc trunk/src/arch/x86/Makefile.inc trunk/src/include/cpu/amd/gx2def.h trunk/src/include/cpu/amd/lxdef.h trunk/src/include/cpu/amd/mtrr.h trunk/src/include/cpu/x86/mtrr.h trunk/src/include/fallback.h trunk/src/mainboard/amd/serengeti_cheetah/ap_romstage.c trunk/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c trunk/src/mainboard/gigabyte/m57sli/ap_romstage.c trunk/src/mainboard/msi/ms7260/ap_romstage.c trunk/src/mainboard/nvidia/l1_2pvv/ap_romstage.c trunk/src/mainboard/supermicro/h8dme/ap_romstage.c trunk/src/mainboard/supermicro/h8dmr/ap_romstage.c trunk/src/mainboard/tyan/s2912/ap_romstage.c trunk/src/southbridge/amd/cs5535/cs5535.h trunk/src/southbridge/amd/cs5536/cs5536.h trunk/src/southbridge/intel/i82371eb/i82371eb.h trunk/src/southbridge/intel/i82801gx/i82801gx.h trunk/util/xcompile/xcompile Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Tue Apr 5 15:00:33 2011 (r6481) +++ trunk/Makefile Sun Apr 10 06:15:23 2011 (r6482) @@ -64,7 +64,6 @@ endif endif -CPP:= $(CC) -x assembler-with-cpp -DASSEMBLY -E HOSTCC = gcc HOSTCXX = g++ HOSTCFLAGS := -I$(srck) -I$(objk) -g Modified: trunk/Makefile.inc ============================================================================== --- trunk/Makefile.inc Tue Apr 5 15:00:33 2011 (r6481) +++ trunk/Makefile.inc Sun Apr 10 06:15:23 2011 (r6482) @@ -50,10 +50,8 @@ # Add source classes and their build options classes-y := ramstage romstage driver smm -ramstage-S-ccopts:=-DASSEMBLY romstage-c-ccopts:=-D__PRE_RAM__ -romstage-S-ccopts:=-DASSEMBLY -D__PRE_RAM__ -driver-S-ccopts:=-DASSEMBLY +romstage-S-ccopts:=-D__PRE_RAM__ ramstage-c-deps:=$$(OPTION_TABLE_H) romstage-c-deps:=$$(OPTION_TABLE_H) @@ -63,7 +61,7 @@ define ramstage-objs_asl_template $(obj)/$(1).ramstage.o: src/$(1).asl $(obj)/config.h @printf " IASL $$(subst $(top)/,,$$(@))\n" - $(CPP) -MMD -MT $$(@) -D__ACPI__ -P -include $(abspath $(obj)/config.h) -I$(src) -I$(src)/mainboard/$(MAINBOARDDIR) $$< -o $$(basename $$(a)).asl + $(CC) -x assembler-with-cpp -E -MMD -MT $$(@) -D__ACPI__ -P -include $(abspath $(obj)/config.h) -I$(src) -I$(src)/mainboard/$(MAINBOARDDIR) $$< -o $$(basename $$(a)).asl iasl -p $$(obj)/$(1) -tc $$(basename $$(a)).asl mv $$(obj)/$(1).hex $$(basename $$(a)).c $(CC) $$(CFLAGS) $$(if $$(subst dsdt,,$$(basename $$(notdir $(1)))), -DAmlCode=AmlCode_$$(basename $$(notdir $(1)))) -c -o $$@ $$(basename $$(a)).c Modified: trunk/src/arch/x86/Makefile.bigbootblock.inc ============================================================================== --- trunk/src/arch/x86/Makefile.bigbootblock.inc Tue Apr 5 15:00:33 2011 (r6481) +++ trunk/src/arch/x86/Makefile.bigbootblock.inc Sun Apr 10 06:15:23 2011 (r6482) @@ -26,7 +26,7 @@ $(obj)/mainboard/$(MAINBOARDDIR)/crt0.s: $(obj)/crt0.S @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -MMD -x assembler-with-cpp -DASSEMBLY -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -include $(obj)/config.h -I. -I$(src) $< -o $@ + $(CC) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -include $(obj)/config.h -I. -I$(src) $< -o $@ $(obj)/coreboot: $$(romstage-objs) $(obj)/ldscript.ld @printf " LINK $(subst $(obj)/,,$(@))\n" Modified: trunk/src/arch/x86/Makefile.bootblock.inc ============================================================================== --- trunk/src/arch/x86/Makefile.bootblock.inc Tue Apr 5 15:00:33 2011 (r6481) +++ trunk/src/arch/x86/Makefile.bootblock.inc Sun Apr 10 06:15:23 2011 (r6482) @@ -55,7 +55,7 @@ $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.s: $(obj)/bootblock/bootblock.S @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -MMD -DASSEMBLY -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -I$(obj)/bootblock -include $(obj)/config.h -I. -I$(src) $< -o $@ + $(CC) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -I$(obj)/bootblock -include $(obj)/config.h -I. -I$(src) $< -o $@ $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.inc: $(src)/arch/x86/init/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(objutil)/romcc/romcc $(OPTION_TABLE_H) @printf " ROMCC $(subst $(obj)/,,$(@))\n" @@ -105,5 +105,5 @@ $(obj)/mainboard/$(MAINBOARDDIR)/crt0.s: $(obj)/romstage/crt0.S @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -MMD -x assembler-with-cpp -DASSEMBLY -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -I$(obj)/romstage -include $(obj)/config.h -I. -I$(src) $< -o $@ + $(CC) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -I$(obj)/romstage -include $(obj)/config.h -I. -I$(src) $< -o $@ Modified: trunk/src/arch/x86/Makefile.inc ============================================================================== --- trunk/src/arch/x86/Makefile.inc Tue Apr 5 15:00:33 2011 (r6481) +++ trunk/src/arch/x86/Makefile.inc Sun Apr 10 06:15:23 2011 (r6482) @@ -225,7 +225,7 @@ $(obj)/mainboard/$(MAINBOARDDIR)/ap_romstage.o: $(src)/mainboard/$(MAINBOARDDIR)/ap_romstage.c $(OPTION_TABLE_H) @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -MMD $(CFLAGS) -I$(src) -I. -I$(obj) -c $(src)/mainboard/$(MAINBOARDDIR)/ap_romstage.c -o $@ + $(CC) -MMD $(CFLAGS) -I$(src) -D__PRE_RAM__ -I. -I$(obj) -c $< -o $@ $(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(OPTION_TABLE_H) $(obj)/build.h $(obj)/config.h @printf " CC romstage.inc\n" Modified: trunk/src/include/cpu/amd/gx2def.h ============================================================================== --- trunk/src/include/cpu/amd/gx2def.h Tue Apr 5 15:00:33 2011 (r6481) +++ trunk/src/include/cpu/amd/gx2def.h Sun Apr 10 06:15:23 2011 (r6482) @@ -511,7 +511,7 @@ #define PMLogic_BASE (0x9D00) -#if !defined(__ROMCC__) && !defined(ASSEMBLY) +#if !defined(__ROMCC__) && !defined(__ASSEMBLER__) #if defined(__PRE_RAM__) void cpuRegInit(void); void SystemPreInit(void); Modified: trunk/src/include/cpu/amd/lxdef.h ============================================================================== --- trunk/src/include/cpu/amd/lxdef.h Tue Apr 5 15:00:33 2011 (r6481) +++ trunk/src/include/cpu/amd/lxdef.h Sun Apr 10 06:15:23 2011 (r6482) @@ -630,7 +630,7 @@ #define DELAY_UPPER_DISABLE_CLK135 (1 << 23) #define DELAY_LOWER_STATUS_MASK 0x7C0 -#if !defined(__ROMCC__) && !defined(ASSEMBLY) +#if !defined(__ROMCC__) && !defined(__ASSEMBLER__) #if defined(__PRE_RAM__) void cpuRegInit(int debug_clock_disable, u8 dimm0, u8 dimm1, int terminated); void SystemPreInit(void); Modified: trunk/src/include/cpu/amd/mtrr.h ============================================================================== --- trunk/src/include/cpu/amd/mtrr.h Tue Apr 5 15:00:33 2011 (r6481) +++ trunk/src/include/cpu/amd/mtrr.h Sun Apr 10 06:15:23 2011 (r6482) @@ -33,7 +33,7 @@ #define TOP_MEM_MASK 0x007fffff #define TOP_MEM_MASK_KB (TOP_MEM_MASK >> 10) -#if !defined(__PRE_RAM__) && !defined(ASSEMBLY) +#if !defined(__PRE_RAM__) && !defined(__ASSEMBLER__) void amd_setup_mtrrs(void); #endif Modified: trunk/src/include/cpu/x86/mtrr.h ============================================================================== --- trunk/src/include/cpu/x86/mtrr.h Tue Apr 5 15:00:33 2011 (r6481) +++ trunk/src/include/cpu/x86/mtrr.h Sun Apr 10 06:15:23 2011 (r6482) @@ -36,7 +36,7 @@ #define MTRRfix4K_F0000_MSR 0x26e #define MTRRfix4K_F8000_MSR 0x26f -#if !defined (ASSEMBLY) && !defined(__PRE_RAM__) +#if !defined (__ASSEMBLER__) && !defined(__PRE_RAM__) #include <device/device.h> void enable_fixed_mtrr(void); void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb); @@ -69,7 +69,7 @@ #endif -#if !defined (ASSEMBLY) +#if !defined (__ASSEMBLER__) #if defined(CONFIG_XIP_ROM_SIZE) # if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK extern unsigned long AUTO_XIP_ROM_BASE; Modified: trunk/src/include/fallback.h ============================================================================== --- trunk/src/include/fallback.h Tue Apr 5 15:00:33 2011 (r6481) +++ trunk/src/include/fallback.h Sun Apr 10 06:15:23 2011 (r6482) @@ -1,12 +1,12 @@ #ifndef FALLBACK_H #define FALLBACK_H -#if !defined(ASSEMBLY) && !defined(__PRE_RAM__) +#if !defined(__ASSEMBLER__) && !defined(__PRE_RAM__) void set_boot_successful(void); void boot_successful(void); -#endif /* ASSEMBLY */ +#endif /* __ASSEMBLER__ */ #define RTC_BOOT_BYTE 48 Modified: trunk/src/mainboard/amd/serengeti_cheetah/ap_romstage.c ============================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah/ap_romstage.c Tue Apr 5 15:00:33 2011 (r6481) +++ trunk/src/mainboard/amd/serengeti_cheetah/ap_romstage.c Sun Apr 10 06:15:23 2011 (r6482) @@ -1,6 +1,3 @@ -#define ASSEMBLY 1 -#define __PRE_RAM__ - #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #include <stdint.h> Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c Tue Apr 5 15:00:33 2011 (r6481) +++ trunk/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c Sun Apr 10 06:15:23 2011 (r6482) @@ -21,9 +21,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 -#define __PRE_RAM__ - #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #include <stdint.h> Modified: trunk/src/mainboard/gigabyte/m57sli/ap_romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/m57sli/ap_romstage.c Tue Apr 5 15:00:33 2011 (r6481) +++ trunk/src/mainboard/gigabyte/m57sli/ap_romstage.c Sun Apr 10 06:15:23 2011 (r6482) @@ -19,9 +19,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 -#define __PRE_RAM__ - #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #include <stdint.h> Modified: trunk/src/mainboard/msi/ms7260/ap_romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms7260/ap_romstage.c Tue Apr 5 15:00:33 2011 (r6481) +++ trunk/src/mainboard/msi/ms7260/ap_romstage.c Sun Apr 10 06:15:23 2011 (r6482) @@ -19,10 +19,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 - -#define __PRE_RAM__ - #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #include <stdint.h> Modified: trunk/src/mainboard/nvidia/l1_2pvv/ap_romstage.c ============================================================================== --- trunk/src/mainboard/nvidia/l1_2pvv/ap_romstage.c Tue Apr 5 15:00:33 2011 (r6481) +++ trunk/src/mainboard/nvidia/l1_2pvv/ap_romstage.c Sun Apr 10 06:15:23 2011 (r6482) @@ -19,9 +19,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 -#define __PRE_RAM__ - #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #include <stdint.h> Modified: trunk/src/mainboard/supermicro/h8dme/ap_romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dme/ap_romstage.c Tue Apr 5 15:00:33 2011 (r6481) +++ trunk/src/mainboard/supermicro/h8dme/ap_romstage.c Sun Apr 10 06:15:23 2011 (r6482) @@ -19,9 +19,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 -#define __PRE_RAM__ - #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #include <stdint.h> Modified: trunk/src/mainboard/supermicro/h8dmr/ap_romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr/ap_romstage.c Tue Apr 5 15:00:33 2011 (r6481) +++ trunk/src/mainboard/supermicro/h8dmr/ap_romstage.c Sun Apr 10 06:15:23 2011 (r6482) @@ -19,9 +19,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 -#define __PRE_RAM__ - #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #include <stdint.h> Modified: trunk/src/mainboard/tyan/s2912/ap_romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2912/ap_romstage.c Tue Apr 5 15:00:33 2011 (r6481) +++ trunk/src/mainboard/tyan/s2912/ap_romstage.c Sun Apr 10 06:15:23 2011 (r6482) @@ -19,9 +19,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 -#define __PRE_RAM__ - #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #include <stdint.h> Modified: trunk/src/southbridge/amd/cs5535/cs5535.h ============================================================================== --- trunk/src/southbridge/amd/cs5535/cs5535.h Tue Apr 5 15:00:33 2011 (r6481) +++ trunk/src/southbridge/amd/cs5535/cs5535.h Sun Apr 10 06:15:23 2011 (r6482) @@ -115,7 +115,7 @@ /* Flash Memory Mask values */ #define FLASH_MEM_4K 0xFFFFF000 -#if !defined(ASSEMBLY) && !defined(__ROMCC__) +#if !defined(__ASSEMBLER__) && !defined(__ROMCC__) #if defined(__PRE_RAM__) void cs5535_disable_internal_uart(void); #else Modified: trunk/src/southbridge/amd/cs5536/cs5536.h ============================================================================== --- trunk/src/southbridge/amd/cs5536/cs5536.h Tue Apr 5 15:00:33 2011 (r6481) +++ trunk/src/southbridge/amd/cs5536/cs5536.h Sun Apr 10 06:15:23 2011 (r6482) @@ -442,7 +442,7 @@ #define FLASH_IO_128B 0x0000FF80 #define FLASH_IO_256B 0x0000FF00 -#if !defined(ASSEMBLY) && !defined(__ROMCC__) +#if !defined(__ASSEMBLER__) && !defined(__ROMCC__) #if defined(__PRE_RAM__) void cs5536_setup_onchipuart(int uart); void cs5536_disable_internal_uart(void); Modified: trunk/src/southbridge/intel/i82371eb/i82371eb.h ============================================================================== --- trunk/src/southbridge/intel/i82371eb/i82371eb.h Tue Apr 5 15:00:33 2011 (r6481) +++ trunk/src/southbridge/intel/i82371eb/i82371eb.h Sun Apr 10 06:15:23 2011 (r6482) @@ -21,7 +21,7 @@ #ifndef SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H #define SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H -#if !defined(ASSEMBLY) +#if !defined(__ASSEMBLER__) #if !defined(__PRE_RAM__) #if !defined(__ACPI__) /* dsdt include */ Modified: trunk/src/southbridge/intel/i82801gx/i82801gx.h ============================================================================== --- trunk/src/southbridge/intel/i82801gx/i82801gx.h Tue Apr 5 15:00:33 2011 (r6481) +++ trunk/src/southbridge/intel/i82801gx/i82801gx.h Sun Apr 10 06:15:23 2011 (r6482) @@ -38,7 +38,7 @@ #ifndef __ACPI__ #define DEBUG_PERIODIC_SMIS 0 -#if !defined(ASSEMBLY) && !defined(__ROMCC__) +#if !defined(__ASSEMBLER__) && !defined(__ROMCC__) #if !defined(__PRE_RAM__) #include "chip.h" extern void i82801gx_enable(device_t dev); Modified: trunk/util/xcompile/xcompile ============================================================================== --- trunk/util/xcompile/xcompile Tue Apr 5 15:00:33 2011 (r6481) +++ trunk/util/xcompile/xcompile Sun Apr 10 06:15:23 2011 (r6482) @@ -89,7 +89,6 @@ # elf${TWIDTH}-${TARCH} toolchain AS:=${GCCPREFIX}as ${ASFLAGS} CC:=${GCCPREFIX}gcc ${CFLAGS} -CPP:=${GCCPREFIX}cpp AR:=${GCCPREFIX}ar LD:=${GCCPREFIX}ld ${LDFLAGS} STRIP:=${GCCPREFIX}strip

1 0

[PATCH] i945: improve get_top_of_ram()
by Sven Schnelle 09 Apr '11

09 Apr '11

The current version doesn't honor TSEG, and fails to report the correct top of RAM if IGD is disabled. This is because it uses the BSM (base of stolen RAM) register. In that case, we should use the TOLUD register. Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/northbridge/intel/i945/raminit.c | 30 +++++++++++++++++++++++++++--- 1 files changed, 27 insertions(+), 3 deletions(-) diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 8b7ffa1..c8bef11 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -3192,9 +3192,33 @@ void sdram_initialize(int boot_path, const u8 *spd_addresses) unsigned long get_top_of_ram(void) { - /* This will not work if TSEG is in place! */ - u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c); + u32 tom; - return (unsigned long) tom; + if (pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) & ((1 << 4) | (1 << 3))) { + /* IGD enabled, get top of Memory from BSM register */ + tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c); + } else { + tom = (pci_read_config8(PCI_DEV(0,0,0), TOLUD) & 0xf7) << 24; + } + + /* if TSEG enabled subtract size */ + switch(pci_read_config8(PCI_DEV(0, 0, 0), ESMRAM)) { + case 0x01: + /* 1MB TSEG */ + tom -= 0x10000; + break; + case 0x03: + /* 2MB TSEG */ + tom -= 0x20000; + break; + case 0x05: + /* 8MB TSEG */ + tom -= 0x80000; + break; + default: + /* TSEG either disabled or invalid */ + break; + } + return (unsigned long)tom; } -- 1.7.4.1

1 0

[PATCH] drop ASSEMBLY define
by Stefan Reinauer 08 Apr '11

08 Apr '11

see patch

2 1

e-vectra flash
by Devel 08 Apr '11

08 Apr '11

Hello, (Murphy's Law in action!) Well, I tried to use Coreboot + Seabios in old hp e-vectra. - Download coreboot. - Compile coreboot. - Flash with flashrom. Seems to be that is not easy, because old e-vectra do not boot. Any page that explains how to add devices like onboard vga, and onboard ethernet to image? Any pre-builded rom for this device? I will try to re-flash using eeprom programmer. Regards, -- Ordenadores, componentes y software: http://www.1pc.es/ Sistemas IT: http://www.precioventa.com/

2 1

[PATCH][RESEND] Print what mainboard coreboot is being built for during build
by Nickolas Lloyd 07 Apr '11

07 Apr '11

Sorry about the mangling, I've attached the patch this time. Nickolas

4 4

Dell Adamo XPS
by Marek 07 Apr '11

07 Apr '11

Hi, I'd like to ask whether someone would be so kind to take a look at Dell Adamo XPS logs and give me some advice as to whether there is any chance to flashrom & coreboot this device: http://ul.to/fiyfu9so I'd be glad if anyone could give me further instructions on how to find out more information. thanks, Marek

2 2

QingPei Wang wants to stay in touch on LinkedIn
by QingPei Wang via LinkedIn 06 Apr '11

06 Apr '11

LinkedIn ------------QingPei Wang requested to add you as a connection on LinkedIn: ------------------------------------------ Jerome, I'd like to add you to my professional network on LinkedIn. - QingPei Wang Accept invitation from QingPei Wang http://www.linkedin.com/e/onyp92-gm7bw79r-4t/u6SZGvvJ_mvgyxl93y5eAqkCVLuNNc… View invitation from QingPei Wang http://www.linkedin.com/e/onyp92-gm7bw79r-4t/u6SZGvvJ_mvgyxl93y5eAqkCVLuNNc… ------------------------------------------ Why might connecting with QingPei Wang be a good idea? QingPei Wang's connections could be useful to you: After accepting QingPei Wang's invitation, check QingPei Wang's connections to see who else you may know and who you might want an introduction to. Building these connections can create opportunities in the future. -- (c) 2011, LinkedIn Corporation

2 1

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coreboot April 2011