coreboot April 2011

coreboot@coreboot.org

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229 discussions

#176: inteltool: added PCI_DEVICE_ID_INTEL_X44 0x29e0
by coreboot 04 Apr '11

04 Apr '11

#176: inteltool: added PCI_DEVICE_ID_INTEL_X44 0x29e0 ---------------------------+----------------------------------------------- Reporter: schramp@… | Owner: stepan@… Type: | Status: new enhancement | Milestone: Priority: major | Keywords: Component: misc | Patch Status: patch is ready to be committed Dependencies: | ---------------------------+----------------------------------------------- The inteltool didn't recognize my MCH lspci did. looked up the intel documentation and made a patch. As its trivial i think it can be added straight away. Best regards, Ruud Schramp -- Ticket URL: <https://tracker.coreboot.org/trac/coreboot/ticket/176> coreboot <http://www.coreboot.org/>

2 4

Is my laptop supported? (gateway 450SX4)
by X 04 Apr '11

04 Apr '11

I am having a hard time figuring out if my laptop is supported...it is a gateway 450SX4 NS PC87391 LPC super I/O controller Intel® 845MZ chipset (MCH-M+ICH3-M) lspci -tvnn output: lspci -tvnn -[0000:00]-+-00.0 Intel Corporation 82845 845 [Brookdale] Chipset Host Bridge [8086:1a30] +-01.0-[01]----00.0 ATI Technologies Inc Radeon Mobility M6 LY [1002:4c59] +-1d.0 Intel Corporation 82801CA/CAM USB Controller #1 [8086:2482] +-1d.1 Intel Corporation 82801CA/CAM USB Controller #2 [8086:2484] +-1e.0-[02-0a]--+-[0000:03]---00.0 Atheros Communications Inc. AR2413 802.11bg NIC [168c:001a] | \-[0000:02]-+-02.0 Texas Instruments PCI1520 PC card Cardbus Controller [104c:ac55] | +-02.1 Texas Instruments PCI1520 PC card Cardbus Controller [104c:ac55] | +-03.0 ESS Technology ES1988 Allegro-1 [125d:1988] | \-05.0 Texas Instruments TSB43AB21 IEEE-1394a-2000 Controller (PHY/Link) [104c:8026] +-1f.0 Intel Corporation 82801CAM ISA Bridge (LPC) [8086:248c] +-1f.1 Intel Corporation 82801CAM IDE U100 Controller [8086:248a] \-1f.3 Intel Corporation 82801CA/CAM SMBus Controller [8086:2483] Flashrom-v reports this: flashrom v0.9.2-r1141 on Linux 2.6.32-5-686 (i686), built with libpci 3.1.7, GCC 4.4.5 20100728 (prerelease), little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 1223M loops per second, 10 myus = 10 us, 100 myus = 94 us, 1000 myus = 1076 us, 10000 myus = 9857 us, 4 myus = 5 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "Gateway " DMI string system-product-name: "Gateway 450 " DMI string system-version: "Rev 1 " DMI string baseboard-manufacturer: "Gateway " DMI string baseboard-product-name: "Gateway 450 " DMI string baseboard-version: "Rev 1.0 " DMI string chassis-type: "Notebook" Laptop detected via DMI ======================================================================== WARNING! You seem to be running flashrom on a laptop. Laptops, notebooks and netbooks are difficult to support and we recommend to use the vendor flashing utility. The embedded controller (EC) in these machines often interacts badly with flashing. See http://www.flashrom.org/Laptops for details. If flash is shared with the EC, erase is guaranteed to brick your laptop and write may brick your laptop. Read and probe may irritate your EC and cause fan failure, backlight failure and sudden poweroff. You have been warned. ======================================================================== Aborting. BIOS info reported by gateway: BIOS Phoenix BIOS 512-KB Flash ROM SMBIOS 2.3 support ACPI 1.0b support APM 1.2 Wired for Management 2.0 (WfM 2.0) my CPU info: Packaging: Intel socketable micro-FCPGA Model name: Mobile Intel(R) Pentium(R) 4 - M CPU 2.00GHz Frequency: 2000Mhz L2 Cache: 512kb Bogomips: 3989.06 Numbering: family(15) model(2) stepping(7) flags: fpu vme de pse tsc msr pae mce cx8 sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe up pebs bts cid Front Side Bus: 400 MHz front side bus any help is appreciated...and i will help in any way I can.

2 1

[PATCH] FILO: Utility for generating an Artecboot image
by Nathan Williams 04 Apr '11

04 Apr '11

This program outputs a binary file with artecboot header and Linux kernel that can be used with the FILO Artecboot loader. Signed-off-by: Nathan Williams <nathan(a)traverse.com.au> --- /dev/null +++ util/artecimage.c @@ -0,0 +1,200 @@ +#include <stdio.h> +#include <string.h> +#include <unistd.h> + +#define PROG_NAME "artecimage" +#define VERSION "1.1" + +#define BUFSIZE 512 + +// Artecboot header, gives information to loader + +#define ARTECBOOT_HEADER_MAGIC 0x10ADFACE +#define CURRENT_VERSION 0x0102 + +#define OS_UNKNOWN 0x00 +#define OS_LINUX 0x01 +#define OS_WINCE 0x02 + +#define FLAG_INITRD 0x0001 // if set, the loader will provide initrd to kernel +#define FLAG_FILESYSTEM 0x0002 // if set, the loader will use specified file names +#define FLAG_CMDLINE 0x0004 // if set, the loader will pass the new command line + +#define ABOOT_FILE_KERNEL "/kernel" +#define ABOOT_FILE_INITRD "/initrd" +#define ABOOT_FILE_HEADER "/header" + +#define DEV_SECTOR_SIZE 512 +#define DEV_SECTOR_BITS 9 + +typedef struct __attribute__ ((packed)) +{ + unsigned long magicHeader; + unsigned short bootVersion; + unsigned short headerSize; // also kernel image start + unsigned long imageSize; // NB! since 1.02 is the total image/partition size + unsigned long bitFlags; + unsigned short osType; + char cmdLine[256]; + unsigned long kernelStart; // used with Artecboot VFS / NULLFS + unsigned long kernelSize; // used with Artecboot VFS / NULLFS + unsigned long initrdStart; // used with Artecboot VFS / NULLFS + unsigned long initrdSize; // used with Artecboot VFS / NULLFS + char kernelFile[100]; // valid only with FLAG_FILESYSTEM + char initrdFile[100]; // valid only with FLAG_FILESYSTEM + +} ARTECBOOT_HEADER; + +void usage(void); + +int main(int argc, char **argv){ + ARTECBOOT_HEADER bootHdr; + FILE *BINFILE = 0; + FILE *KERNFILE = 0; + FILE *INITRDFILE = 0; + char buf[BUFSIZE]; + int c; + int i; + int verbose = 0; + + /* clear header */ + memset(&bootHdr, 0, sizeof(ARTECBOOT_HEADER)); + + while ((c = getopt(argc, argv, "c:hi:k:o:v")) != -1) { + switch(c) { + case 'c': + if (strlen(optarg) < sizeof(bootHdr.cmdLine)) { + strcpy(bootHdr.cmdLine, optarg); + bootHdr.bitFlags |= FLAG_CMDLINE; + } else { + usage(); + printf("\nCommand line exceeds %d char limit\n", (sizeof(bootHdr.cmdLine) - 1)); + return 1; + } + break; + case 'h': + usage(); + return 0; + break; + case 'i': + INITRDFILE = fopen(optarg,"r"); + if(INITRDFILE == NULL){ + usage(); + printf("\nError: Failed to open file '%s'\n\n", optarg); + return 1; + } + break; + case 'k': + KERNFILE = fopen(optarg,"r"); + if(KERNFILE == NULL){ + usage(); + printf("\nError: Failed to open file '%s'\n\n", optarg); + return 1; + } + break; + case 'o': + BINFILE = fopen(optarg,"w"); + if(BINFILE == NULL){ + usage(); + printf("\nError: Failed to open file '%s'\n\n", optarg); + return 1; + } + break; + case 'v': + verbose = 1; + break; + } + } + if(!BINFILE){ + usage(); + printf("\nError: No output file specified\n\n"); + return 1; + } + + if(!KERNFILE){ + usage(); + printf("\nError: No kernel image specified\n\n"); + return 1; + } + + bootHdr.magicHeader = ARTECBOOT_HEADER_MAGIC; + bootHdr.bootVersion = CURRENT_VERSION; + bootHdr.headerSize = sizeof(ARTECBOOT_HEADER); + + /* Get kernel image size */ + fseek(KERNFILE, 0L, SEEK_END); + bootHdr.imageSize = ftell(KERNFILE); + + bootHdr.kernelSize = bootHdr.imageSize; + bootHdr.kernelStart = DEV_SECTOR_SIZE; + + bootHdr.osType = OS_LINUX; + + if(INITRDFILE){ + /* Get initrd image size */ + fseek(INITRDFILE, 0L, SEEK_END); + bootHdr.initrdSize = ftell(INITRDFILE); + + /* Set INITRD flag */ + bootHdr.bitFlags |= FLAG_INITRD; + + /* Calculate start address (512 boundary) */ + bootHdr.initrdStart = (bootHdr.kernelStart + bootHdr.imageSize); + bootHdr.initrdStart = (bootHdr.initrdStart >> DEV_SECTOR_BITS) + 1; + bootHdr.initrdStart <<= DEV_SECTOR_BITS; + } + + fwrite(&bootHdr, 1, sizeof(ARTECBOOT_HEADER), BINFILE); + fseek(BINFILE, bootHdr.kernelStart, SEEK_SET); + + /* Copy kernel into output file */ + fseek(KERNFILE, 0, SEEK_SET); + while((i = fread(&buf, 1, BUFSIZE, KERNFILE)) != 0){ + fwrite(&buf, 1, i, BINFILE); + } + fclose(KERNFILE); + + if(INITRDFILE){ + fseek(BINFILE, bootHdr.initrdStart, SEEK_SET); + + /* Copy initrd into output file */ + fseek(INITRDFILE, 0, SEEK_SET); + while((i = fread(&buf, 1, BUFSIZE, INITRDFILE)) != 0){ + fwrite(&buf, 1, i, BINFILE); + } + fclose(INITRDFILE); + } + + fclose(BINFILE); + + if(verbose){ + printf("magicHeader: 0x%04lx\n", bootHdr.magicHeader); + printf("bootVersion: 0x%04x\n", bootHdr.bootVersion); + printf("headerSize: 0x%08x\n", bootHdr.headerSize); + printf("imageSize: 0x%08lx\n", bootHdr.imageSize); + printf("bitFlags: 0x%08lx\n", bootHdr.bitFlags); + printf("osType: 0x%04x\n", bootHdr.osType); + printf("cmdLine: %s\n", bootHdr.cmdLine); + printf("kernelStart: 0x%08lx\n", bootHdr.kernelStart); + printf("kernelSize: 0x%08lx\n", bootHdr.imageSize); + printf("initrdStart: 0x%08lx\n", bootHdr.initrdStart); + printf("initrdSize: 0x%08lx\n", bootHdr.initrdSize); + printf("kernelFile: %s\n", bootHdr.kernelFile); + printf("initrdFile: %s\n", bootHdr.initrdFile); + } + return 0; +} + +void usage(void) { + printf(PROG_NAME " v" VERSION "\n" + "Usage: " PROG_NAME " [-hv] [-c cmdline] [-i initrd] -k kernel -o outfile\n\n" + "Options:\n" + " -c cmdline Kernel command line (max 255 chars).\n" + " -h Display this help.\n" + " -i initrd initrd filename.\n" + " -k kernel Linux kernel filename.\n" + " -o outfile Write image to outfile.\n" + " -v Verbose.\n" + ); + return; +}

1 0

Support for Jasper Forest and Sandy bridge on coreboot
by sharib khan 03 Apr '11

03 Apr '11

Hi, I am doing a feasibility study to port coreboot on our new generation data processing boards. We are evaluating on Sandy bridge and Jasper Forest (Intel Processor's). Could someone explain if it is possible to support these processors on coreboot. If yes, what could be the steps required. Kind Regards, Sharib

4 6

Where is the source code of Coreboot for PPC?
by Hamo 03 Apr '11

03 Apr '11

Hi lists, As I want to port Coreboot to ARM, I need to study the structure of Coreboot. Since Coreboot supported PPC once, I want to study the structure of the source code. But I can't find it. Can someone help me? Thanks.

5 8

mingw build problem with seabios/tools/kconfig
by Scott Duplichan 02 Apr '11

02 Apr '11

Hello, I am trying to overcome problems building seabios/tools/kconfig from the windows/mingw environment. Here are the failures: 1) Link step for tools/kconfig/conf fails to find regcomp/regexec/regfree. In the mingw environment these functions are available in libregex, but libregex is not included in the standard library search. I have not found a way to add '-lregex' to the link command line: $(Q)$(HOSTCC) $(HOSTLDFLAGS) -o $@ $(addprefix $(obj)/,$($(@F)-objs)) $(HOST_LOADLIBES) $(HOSTLOADLIBES_$(@F)) HOSTLDFLAGS occurs too early in the file list for this use. 2) Link step for tools/kconfig/conf fails to find function uname(). I can come up with a library to provide this function but need help passing it to the linker, same as with item 1. 3) Function mkdir() takes only one argument in the mingw environment, yet takes 2 arguments otherwise. I have not found a good way to overcome this difference. Thanks, Scott

5 12

Re: [coreboot] Asus B202 port
by Stefan Reinauer 02 Apr '11

02 Apr '11

* yuen(a)klacno.sk <yuen(a)klacno.sk> [110402 00:13]: > > >> Setting Graphics Frequency... > >> FSB: 533 MHz Voltage: 1.05V Render: 166Mhz Display: 200MHz > > Hm.. FSB supports up to 667 > > Atom N270 supports just 533Mhz And that's apparently what it is trying to use, too. > >> Setting Memory Frequency... CLKCFG=0x00010021, CLKCFG=0x00010031, ok > >> Setting mode of operation for memory channels...Single Channel 0 only. > >> DCC=0x00000400 > >> Programming Clock Crossing...MEM=667 FSB=533... ok > > > > This looks suspicious. It MEM=667 is not supported. > > Just idea ... maybe I should try it with debuggind messages off, if there > is something with CAR ... Unlikely, but worth a shot. See my other mail for suggestions.

1 0

[PATCH] better chipset reporting on i945
by Stefan Reinauer 02 Apr '11

02 Apr '11

See patch

1 0

Asus B202 port
by yuen＠klacno.sk 02 Apr '11

02 Apr '11

Hi, I'm working on port coreboot to Asus Eee Box B202 (http://www.asus.com/product.aspx?P_ID=QUObl5lSRQQ3lSqJ). Code is based on Intel d945gclf target. So far I have console running. Boot halts on sdram initialization before "Extended Mode Register Set(2)", sometime goes one or two steps ahead. Any idea how to move on? Cheers Marek Becka

2 2

XP is very slow on coreboot with SeaBIOS
by Jiang Wang 02 Apr '11

02 Apr '11

Hi there, My colleagues and me tested Windows XP SP3 on coreboot and SeaBIOS on ASUS M2V MX-SE motherboard. The XP is very slow when opening a new window (such as Visual Studio) and when suspending and waking up. We tried original AMI bios, which is much faster. Also, we noticed that on coreboot and SeaBIOS, interrupts some times consume about 20-60% CPU usage, which is very strange. We tried two coreboot version: 6179 and 6460. Both are slow. The SeaBIOS version is 0.6.1 I am not sure whether it is coreboot or SeaBIOS problem. Any suggestions? Regards, Jiang

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coreboot April 2011