coreboot April 2011

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[patch] fix compilation of all i82371eb boards when ACPI tables aren't generated
by Idwer Vollering 01 Apr '11

01 Apr '11

When CONFIG_GENERATE_ACPI_TABLES is not used/set, this error appears: CC southbridge/intel/i82371eb/fadt.driver.o src/southbridge/intel/i82371eb/fadt.c:35:35: error: expected ')' before '*' token make: *** [build/southbridge/intel/i82371eb/fadt.driver.o] Error 1 These boards are affected (shell command): for f in $(find src/mainboard/ -name Kconfig); do grep -Hi i82371eb $f ; done | awk -F \/ '{ print $3 "/" $4 }'| sort abit/be6-ii_v2_0 asus/p2b asus/p2b-d asus/p2b-ds asus/p2b-f asus/p2b-ls asus/p3b-f a-trend/atc-6220 a-trend/atc-6240 azza/pt-6ibd biostar/m6tba compaq/deskpro_en_sff_p600 emulation/qemu-x86 gigabyte/ga-6bxc gigabyte/ga-6bxe msi/ms6119 msi/ms6147 msi/ms6156 nokia/ip530 soyo/sy-6ba-plus-iii tyan/s1846 Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> --- Index: src/southbridge/intel/i82371eb/Makefile.inc =================================================================== --- src/southbridge/intel/i82371eb/Makefile.inc (revision 6474) +++ src/southbridge/intel/i82371eb/Makefile.inc (working copy) @@ -24,8 +24,10 @@ driver-y += usb.c driver-y += smbus.c driver-y += reset.c +ifeq ($(CONFIG_GENERATE_ACPI_TABLES),y) driver-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c driver-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.c +endif romstage-y += early_pm.c romstage-y += early_smbus.c

2 4

[commit] r6474 - trunk/src/mainboard/lenovo/x60/acpi
by repository service 01 Apr '11

01 Apr '11

Author: svens Date: Fri Apr 1 09:41:47 2011 New Revision: 6474 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6474 Log: remove swp files accidently added Signed-off-by: Sven Schnelle <svens(a)stackframe.org> Acked-by: Sven Schnelle <svens(a)stackframe.org> Deleted: trunk/src/mainboard/lenovo/x60/acpi/.ec.asl.swp trunk/src/mainboard/lenovo/x60/acpi/.gpe.asl.swp

1 0

[commit] r6473 - in trunk/src/mainboard/lenovo/x60: . acpi
by repository service 01 Apr '11

01 Apr '11

Author: svens Date: Fri Apr 1 09:28:56 2011 New Revision: 6473 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6473 Log: X60: add dock code for Ultrabase X6 Move the old docking code from romstage.c to dock.c, and use that code both in romstage and SMM code. Signed-off-by: Sven Schnelle <svens(a)stackframe.org> Acked-by: Peter Stuge <peter(a)stuge.se> Added: trunk/src/mainboard/lenovo/x60/acpi/.ec.asl.swp trunk/src/mainboard/lenovo/x60/acpi/.gpe.asl.swp trunk/src/mainboard/lenovo/x60/acpi/dock.asl - copied, changed from r6472, trunk/src/mainboard/lenovo/x60/mainboard_smi.c trunk/src/mainboard/lenovo/x60/dock.c trunk/src/mainboard/lenovo/x60/dock.h trunk/src/mainboard/lenovo/x60/smi.h Modified: trunk/src/mainboard/lenovo/x60/Makefile.inc trunk/src/mainboard/lenovo/x60/acpi/ec.asl trunk/src/mainboard/lenovo/x60/acpi/gpe.asl trunk/src/mainboard/lenovo/x60/mainboard_smi.c trunk/src/mainboard/lenovo/x60/romstage.c Modified: trunk/src/mainboard/lenovo/x60/Makefile.inc ============================================================================== --- trunk/src/mainboard/lenovo/x60/Makefile.inc Fri Apr 1 09:28:50 2011 (r6472) +++ trunk/src/mainboard/lenovo/x60/Makefile.inc Fri Apr 1 09:28:56 2011 (r6473) @@ -17,4 +17,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c dock.c +romstage-y += dock.c Added: trunk/src/mainboard/lenovo/x60/acpi/.ec.asl.swp ============================================================================== Files /dev/null 00:00:00 1970 (empty, because file is newly added) and trunk/src/mainboard/lenovo/x60/acpi/.ec.asl.swp Fri Apr 1 09:28:56 2011 (r6473) differ Added: trunk/src/mainboard/lenovo/x60/acpi/.gpe.asl.swp ============================================================================== Files /dev/null 00:00:00 1970 (empty, because file is newly added) and trunk/src/mainboard/lenovo/x60/acpi/.gpe.asl.swp Fri Apr 1 09:28:56 2011 (r6473) differ Copied and modified: trunk/src/mainboard/lenovo/x60/acpi/dock.asl (from r6472, trunk/src/mainboard/lenovo/x60/mainboard_smi.c) ============================================================================== --- trunk/src/mainboard/lenovo/x60/mainboard_smi.c Fri Apr 1 09:28:50 2011 (r6472, copy source) +++ trunk/src/mainboard/lenovo/x60/acpi/dock.asl Fri Apr 1 09:28:56 2011 (r6473) @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org> * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -19,35 +19,37 @@ * MA 02110-1301 USA */ -#include <arch/io.h> -#include <arch/romcc_io.h> -#include <console/console.h> -#include <cpu/x86/smm.h> -#include "southbridge/intel/i82801gx/nvs.h" +#include "smi.h" -/* The southbridge SMI handler checks whether gnvs has a - * valid pointer before calling the trap handler - */ -extern global_nvs_t *gnvs; - -int mainboard_io_trap_handler(int smif) +OperationRegion (DLPC, SystemIO, 0x164c, 1) +Field(DLPC, ByteAcc, NoLock, Preserve) +{ + , 3, + DSTA, 1, +} +Device(DOCK) { - switch (smif) { - case 0x99: - printk(BIOS_DEBUG, "Sample\n"); - //gnvs->smif = 0; - break; - default: - return 0; + Name(_HID, "ACPI0003") + Name(_UID, 0x00) + Name(_PCL, Package() { \_SB } ) + + Method(_DCK, 1, NotSerialized) + { + if (Arg0) { + Sleep(250) + /* connect dock */ + TRAP(SMI_DOCK_CONNECT) + } else { + /* disconnect dock */ + TRAP(SMI_DOCK_DISCONNECT) + } + + Xor(Arg0, DSTA, Local0) + Return (Local0) } - /* On success, the IO Trap Handler returns 0 - * On failure, the IO Trap Handler returns a value != 0 - * - * For now, we force the return value to 0 and log all traps to - * see what's going on. - */ - //gnvs->smif = 0; - return 1; + Method(_STA, 0, NotSerialized) + { + Return (DSTA) + } } - Modified: trunk/src/mainboard/lenovo/x60/acpi/ec.asl ============================================================================== --- trunk/src/mainboard/lenovo/x60/acpi/ec.asl Fri Apr 1 09:28:50 2011 (r6472) +++ trunk/src/mainboard/lenovo/x60/acpi/ec.asl Fri Apr 1 09:28:56 2011 (r6473) @@ -19,6 +19,7 @@ * MA 02110-1301 USA */ +#include "smi.h" Device(EC) { Name (_HID, EISAID("PNP0C09")) @@ -83,6 +84,11 @@ \DSPC.BRTD() } + Method(_Q18, 0, NotSerialized) + { + Notify(\_SB.PCI0.LPCB.EC.DOCK, 3) + } + /* AC status change: present */ Method(_Q26, 0, NotSerialized) { @@ -111,4 +117,5 @@ #include "sleepbutton.asl" #include "lid.asl" #include "beep.asl" +#include "dock.asl" } Modified: trunk/src/mainboard/lenovo/x60/acpi/gpe.asl ============================================================================== --- trunk/src/mainboard/lenovo/x60/acpi/gpe.asl Fri Apr 1 09:28:50 2011 (r6472) +++ trunk/src/mainboard/lenovo/x60/acpi/gpe.asl Fri Apr 1 09:28:56 2011 (r6473) @@ -1,3 +1,4 @@ +#include "smi.h" Scope (\_GPE) { Method(_L18, 0, NotSerialized) @@ -5,4 +6,16 @@ /* Read EC register to clear wake status */ Store(\_SB.PCI0.LPCB.EC.WAKE, Local0) } + + /* SLICE_ON_3M GPE (Dock status) */ + Method(_L1D, 0, NotSerialized) + { + if (GP13) { + Or(GIV1, 0x20, GIV1) + Notify(\_SB.PCI0.LPCB.EC.DOCK, 3) + } else { + And(GIV1, 0xdf, GIV1) + Notify(\_SB.PCI0.LPCB.EC.DOCK, 0) + } + } } Added: trunk/src/mainboard/lenovo/x60/dock.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/lenovo/x60/dock.c Fri Apr 1 09:28:56 2011 (r6473) @@ -0,0 +1,249 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <arch/io.h> +#include <boot/tables.h> +#include <delay.h> +#include <arch/io.h> +#include "dock.h" +#include "southbridge/intel/i82801gx/i82801gx.h" +#include "superio/nsc/pc87392/pc87392.h" + +static void dlpc_write_register(int reg, int value) +{ + outb(reg, 0x164e); + outb(value, 0x164f); +} + +static u8 dlpc_read_register(int reg) +{ + outb(reg, 0x164e); + return inb(0x164f); +} + +static void dock_write_register(int reg, int value) +{ + outb(reg, 0x2e); + outb(value, 0x2f); +} + +static u8 dock_read_register(int reg) +{ + outb(reg, 0x2e); + return inb(0x2f); +} + +static void dlpc_gpio_set_mode(int port, int mode) +{ + dlpc_write_register(0xf0, port); + dlpc_write_register(0xf1, mode); +} + +static void dock_gpio_set_mode(int port, int mode, int irq) +{ + dock_write_register(0xf0, port); + dock_write_register(0xf1, mode); + dock_write_register(0xf2, irq); +} + +static void dlpc_gpio_init(void) +{ + /* Select GPIO module */ + dlpc_write_register(0x07, 0x07); + /* GPIO Base Address 0x1680 */ + dlpc_write_register(0x60, 0x16); + dlpc_write_register(0x61, 0x80); + + /* Activate GPIO */ + dlpc_write_register(0x30, 0x01); + + dlpc_gpio_set_mode(0x00, 3); + dlpc_gpio_set_mode(0x01, 3); + dlpc_gpio_set_mode(0x02, 0); + dlpc_gpio_set_mode(0x03, 3); + dlpc_gpio_set_mode(0x04, 4); + dlpc_gpio_set_mode(0x20, 4); + dlpc_gpio_set_mode(0x21, 4); + dlpc_gpio_set_mode(0x23, 4); +} + +int dlpc_init(void) +{ + int timeout = 1000; + + /* Enable 14.318MHz CLK on CLKIN */ + dlpc_write_register(0x29, 0xa0); + while(!(dlpc_read_register(0x29) & 0x10) && timeout--) + udelay(1000); + + if (!timeout) + return 1; + + /* Select DLPC module */ + dlpc_write_register(0x07, 0x19); + /* DLPC Base Address 0x164c */ + dlpc_write_register(0x60, 0x16); + dlpc_write_register(0x61, 0x4c); + /* Activate DLPC */ + dlpc_write_register(0x30, 0x01); + + outb(0x07, 0x164c); + + timeout = 1000; + + while(!(inb(0x164c) & 8) && timeout--) + udelay(1000); + + if (!timeout) { + /* docking failed, disable DLPC switch */ + outb(0x00, 0x164c); + dlpc_write_register(0x30, 0x00); + return 1; + } + + dlpc_gpio_init(); + + return 0; +} + +int dock_connect(void) +{ + int timeout = 1000; + + /* Assert D_PLTRST# */ + outb(0xfe, 0x1680); + udelay(1000); + /* Deassert D_PLTRST# */ + outb(0xff, 0x1680); + + /* startup 14.318MHz Clock */ + dock_write_register(0x29, 0x06); + /* wait until clock is settled */ + while(!(dock_read_register(0x29) & 0x08) && timeout--) + udelay(1000); + + if (!timeout) + return 1; + + /* Pin 6: CLKRUN + * Pin 72: #DR1 + * Pin 19: #SMI + * Pin 73: #MTR + */ + dock_write_register(0x24, 0x37); + + /* PNF active HIGH */ + dock_write_register(0x25, 0xa0); + + /* disable FDC */ + dock_write_register(0x26, 0x01); + + /* Enable GPIO IRQ to #SMI */ + dock_write_register(0x28, 0x02); + + /* select GPIO */ + dock_write_register(0x07, 0x07); + + /* set base address */ + dock_write_register(0x60, 0x16); + dock_write_register(0x61, 0x20); + + /* init GPIO pins */ + dock_gpio_set_mode(0x00, PC87392_GPIO_PIN_DEBOUNCE | + PC87392_GPIO_PIN_PULLUP, 0x00); + + dock_gpio_set_mode(0x01, PC87392_GPIO_PIN_DEBOUNCE | + PC87392_GPIO_PIN_PULLUP, + PC87392_GPIO_PIN_TRIGGERS_SMI); + + dock_gpio_set_mode(0x02, PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x03, PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x04, PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x05, PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x06, PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x07, PC87392_GPIO_PIN_PULLUP, 0x02); + + dock_gpio_set_mode(0x10, PC87392_GPIO_PIN_DEBOUNCE | + PC87392_GPIO_PIN_PULLUP, + PC87392_GPIO_PIN_TRIGGERS_SMI); + + dock_gpio_set_mode(0x11, PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x12, PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x13, PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x14, PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x15, PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x16, PC87392_GPIO_PIN_PULLUP | + PC87392_GPIO_PIN_OE , 0x00); + + dock_gpio_set_mode(0x17, PC87392_GPIO_PIN_PULLUP, 0x00); + + dock_gpio_set_mode(0x20, PC87392_GPIO_PIN_TYPE_PUSH_PULL | + PC87392_GPIO_PIN_OE, 0x00); + + dock_gpio_set_mode(0x21, PC87392_GPIO_PIN_TYPE_PUSH_PULL | + PC87392_GPIO_PIN_OE, 0x00); + + dock_gpio_set_mode(0x22, PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x23, PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x24, PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x25, PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x26, PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x27, PC87392_GPIO_PIN_PULLUP, 0x00); + + dock_gpio_set_mode(0x30, PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x31, PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x32, PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x33, PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x34, PC87392_GPIO_PIN_PULLUP, 0x00); + + dock_gpio_set_mode(0x35, PC87392_GPIO_PIN_PULLUP | + PC87392_GPIO_PIN_OE, 0x00); + + dock_gpio_set_mode(0x36, PC87392_GPIO_PIN_PULLUP, 0x00); + dock_gpio_set_mode(0x37, PC87392_GPIO_PIN_PULLUP, 0x00); + + /* enable GPIO */ + dock_write_register(0x30, 0x01); + + outb(0x00, 0x1628); + outb(0x00, 0x1623); + outb(0x82, 0x1622); + outb(0xff, 0x1624); + + /* Enable USB and Ultrabay power */ + outb(0x03, 0x1628); + return 0; +} + +void dock_disconnect(void) +{ + /* disconnect LPC bus */ + outb(0x00, 0x164c); + /* Assert PLTRST and DLPCPD */ + outb(0xfc, 0x1680); +} + +int dock_present(void) +{ + return !((inb(DEFAULT_GPIOBASE + 0x0c) >> 13) & 1); +} Added: trunk/src/mainboard/lenovo/x60/dock.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/lenovo/x60/dock.h Fri Apr 1 09:28:56 2011 (r6473) @@ -0,0 +1,8 @@ +#ifndef THINKPAD_X60_DOCK_H +#define THINKPAD_X60_DOCK_H + +extern int dock_connect(void); +extern void dock_disconnect(void); +extern int dock_present(void); +extern int dlpc_init(void); +#endif Modified: trunk/src/mainboard/lenovo/x60/mainboard_smi.c ============================================================================== --- trunk/src/mainboard/lenovo/x60/mainboard_smi.c Fri Apr 1 09:28:50 2011 (r6472) +++ trunk/src/mainboard/lenovo/x60/mainboard_smi.c Fri Apr 1 09:28:56 2011 (r6473) @@ -24,30 +24,55 @@ #include <console/console.h> #include <cpu/x86/smm.h> #include "southbridge/intel/i82801gx/nvs.h" +#include <ec/acpi/ec.h> +#include "dock.h" +#include "smi.h" /* The southbridge SMI handler checks whether gnvs has a * valid pointer before calling the trap handler */ extern global_nvs_t *gnvs; +static void mainboard_smm_init(void) +{ + printk(BIOS_DEBUG, "initializing SMI\n"); + /* Enable 0x1600/0x1600 register pair */ + ec_set_bit(0x00, 0x05); + ec_set_ports(0x1604, 0x1600); +} + int mainboard_io_trap_handler(int smif) { + static int smm_initialized; + + if (!smm_initialized) { + mainboard_smm_init(); + smm_initialized = 1; + } + switch (smif) { - case 0x99: - printk(BIOS_DEBUG, "Sample\n"); - //gnvs->smif = 0; + case SMI_DOCK_CONNECT: + dlpc_init(); + if (!dock_connect()) { + /* set dock LED to indicate status */ + ec_write(0x0c, 0x88); + } else { + /* blink dock LED to indicate failure */ + ec_write(0x0c, 0xc8); + } + break; + + case SMI_DOCK_DISCONNECT: + dock_disconnect(); + ec_write(0x0c, 0x08); break; + default: - return 0; + return 1; } /* On success, the IO Trap Handler returns 0 - * On failure, the IO Trap Handler returns a value != 0 - * - * For now, we force the return value to 0 and log all traps to - * see what's going on. - */ - //gnvs->smif = 0; - return 1; + * On failure, the IO Trap Handler returns a value != 0 */ + return 0; } Modified: trunk/src/mainboard/lenovo/x60/romstage.c ============================================================================== --- trunk/src/mainboard/lenovo/x60/romstage.c Fri Apr 1 09:28:50 2011 (r6472) +++ trunk/src/mainboard/lenovo/x60/romstage.c Fri Apr 1 09:28:56 2011 (r6473) @@ -37,6 +37,7 @@ #include "northbridge/intel/i945/i945.h" #include "northbridge/intel/i945/raminit.h" #include "southbridge/intel/i82801gx/i82801gx.h" +#include "dock.h" void setup_ich7_gpios(void) { @@ -107,78 +108,6 @@ outb(val, port+1); } -static void dock_write_register(int reg, int value) -{ - outb(reg, 0x164e); - outb(value, 0x164f); - /* original software reads the chip id after every - I/O operation. Not sure if they are doing it for - some code switching depending on hardware or just - to have a delay after every operation. - - Do it the same way for now, we may remove it later - if it isn't needed - */ - outb(0x20, 0x164e); - inb(0x164f); -} - -static void dock_dlpc_init(void) -{ - /* Select DLPC module */ - dock_write_register(0x07, 0x19); - /* DLPC Base Address 0x164c */ - dock_write_register(0x60, 0x16); - dock_write_register(0x61, 0x4c); - /* Activate DLPC */ - dock_write_register(0x30, 0x01); - outb(0x07, 0x164c); - - while(!(inb(0x164c) & 8)) - udelay(100 * 100); -} - -static void dock_gpio_set_mode(int port, int mode) -{ - dock_write_register(0xf0, port); - dock_write_register(0xf1, mode); - -} - -static void dock_gpio_init(void) -{ - /* Select GPIO module */ - dock_write_register(0x07, 0x07); - /* GPIO Base Address 0x1680 */ - dock_write_register(0x60, 0x16); - dock_write_register(0x61, 0x80); - - /* Activate GPIO */ - dock_write_register(0x30, 0x01); - - dock_gpio_set_mode(0x00, 3); - dock_gpio_set_mode(0x01, 3); - dock_gpio_set_mode(0x02, 0); - dock_gpio_set_mode(0x03, 3); - dock_gpio_set_mode(0x04, 4); - dock_gpio_set_mode(0x20, 4); - dock_gpio_set_mode(0x21, 4); - dock_gpio_set_mode(0x23, 4); -} - -static void connect_dock(void) -{ - /* Enable 14.318MHz CLK on CLKIN */ - dock_write_register(0x29, 0x00); - dock_write_register(0x29, 0xa0); - dock_gpio_init(); - /* Assert D_PLTRST# */ - outb(0xfe, 0x1680); - dock_dlpc_init(); - /* Deassert D_PLTRST# */ - outb(0xff, 0x1680); -} - static void early_superio_config(void) { device_t dev; @@ -306,12 +235,17 @@ ich7_enable_lpc(); - connect_dock(); - - early_superio_config(); - /* Set up the console */ - uart_init(); + /* dock_init initializes the DLPC switch on + * thinpad side, so this is required even + * if we're undocked. + */ + if (!dlpc_init() && dock_present()) { + dock_connect(); + early_superio_config(); + /* Set up the console */ + uart_init(); + } #if CONFIG_USBDEBUG i82801gx_enable_usbdebug(1); Added: trunk/src/mainboard/lenovo/x60/smi.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/lenovo/x60/smi.h Fri Apr 1 09:28:56 2011 (r6473) @@ -0,0 +1,7 @@ +#ifndef MAINBOARD_LENOVO_X60_SMI_H +#define MAINBOARD_LENOVO_X60_SMI_H + +#define SMI_DOCK_CONNECT 0x01 +#define SMI_DOCK_DISCONNECT 0x02 + +#endif

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[commit] r6472 - trunk/src/superio/nsc/pc87392
by repository service 01 Apr '11

01 Apr '11

Author: svens Date: Fri Apr 1 09:28:50 2011 New Revision: 6472 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6472 Log: Add GPIO definitions to PC87392 superio Signed-off-by: Sven Schnelle <svens(a)stackframe.org> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/src/superio/nsc/pc87392/pc87392.h Modified: trunk/src/superio/nsc/pc87392/pc87392.h ============================================================================== --- trunk/src/superio/nsc/pc87392/pc87392.h Fri Apr 1 09:28:35 2011 (r6471) +++ trunk/src/superio/nsc/pc87392/pc87392.h Fri Apr 1 09:28:50 2011 (r6472) @@ -28,4 +28,15 @@ #define PC87392_GPIO 0x07 #define PC87392_WDT 0x0A +#define PC87392_GPIO_PIN_OE 0x01 +#define PC87392_GPIO_PIN_TYPE_PUSH_PULL 0x02 +#define PC87392_GPIO_PIN_PULLUP 0x04 +#define PC87392_GPIO_PIN_LOCK 0x08 +#define PC87392_GPIO_PIN_TRIG_LEVEL 0x10 +#define PC87392_GPIO_PIN_TRIG_LOW 0x20 +#define PC87392_GPIO_PIN_DEBOUNCE 0x40 + +#define PC87392_GPIO_PIN_TRIGGERS_IRQ 0x01 +#define PC87392_GPIO_PIN_TRIGGERS_SMI 0x02 + #endif

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[commit] r6471 - in trunk/src: mainboard/getac/p470/acpi southbridge/intel/i82801gx/acpi
by repository service 01 Apr '11

01 Apr '11

Author: svens Date: Fri Apr 1 09:28:35 2011 New Revision: 6471 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6471 Log: ICH7: Fix register naming error There's an off-by-one error in the ACPI GP_LVL declaration: it declares GL00 with a bit count of 6, and continues with GP07 afterwards. This should be GP06, as the first bitfield covers GP00-GP05. While at it, change it to GP00-GP05, as right now GL00 isn't used, and single bitfield are more usable here. Also adjust the Getac P470, as this is the only user of those defintions right now. Signed-off-by: Sven Schnelle <svens(a)stackframe.org> Acked-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Modified: trunk/src/mainboard/getac/p470/acpi/ec.asl trunk/src/southbridge/intel/i82801gx/acpi/ich7.asl Modified: trunk/src/mainboard/getac/p470/acpi/ec.asl ============================================================================== --- trunk/src/mainboard/getac/p470/acpi/ec.asl Fri Apr 1 02:39:07 2011 (r6470) +++ trunk/src/mainboard/getac/p470/acpi/ec.asl Fri Apr 1 09:28:35 2011 (r6471) @@ -491,16 +491,16 @@ If(And(RFDV, 0x08)) { Or(Local0, 0x08, Local0) } - If(And(GP16, 0x01)) { // GDIS + If(And(GP15, 0x01)) { // GDIS Or(Local0, 0x10, Local0) } - If(And(GP13, 0x01)) { // WIFI Led (WLED) + If(And(GP12, 0x01)) { // WIFI Led (WLED) Or(Local0, 0x20, Local0) } If(And(BTEN, 0x01)) { // BlueTooth Enable Or(Local0, 0x40, Local0) } - If(And(GP11, 0x01)) { // GPS Enable + If(And(GP10, 0x01)) { // GPS Enable Or(Local0, 0x80, Local0) } @@ -511,28 +511,28 @@ Method(SRFD, 1, Serialized) { If (And(Arg0, 0x01)) { - Store (1, GP15) // GLED - Store (1, GP16) // GDIS + Store (1, GP14) // GLED + Store (1, GP15) // GDIS } Else { + Store (0, GP14) Store (0, GP15) - Store (0, GP16) } /* WIFI */ If (And(Arg0, 0x02)) { - Store (1, GP13) // WLED - Store (1, GP26) // WLAN + Store (1, GP12) // WLED + Store (1, GP25) // WLAN } Else { - Store (0, GP13) - Store (0, GP26) + Store (0, GP12) + Store (0, GP25) } /* Bluetooth */ If (And(Arg0, 0x04)) { - Store (1, GP14) // BLED + Store (1, GP13) // BLED Store (1, BTEN) } Else { - Store (0, GP14) // BLED + Store (0, GP13) // BLED Store (0, BTEN) } Return (0) @@ -577,7 +577,7 @@ /* ??? */ Method(GTSD, 0, Serialized) { - Return (GP20) // TSDT + Return (GP19) // TSDT } /* Not even decent function names anymore? */ Modified: trunk/src/southbridge/intel/i82801gx/acpi/ich7.asl ============================================================================== --- trunk/src/southbridge/intel/i82801gx/acpi/ich7.asl Fri Apr 1 02:39:07 2011 (r6470) +++ trunk/src/southbridge/intel/i82801gx/acpi/ich7.asl Fri Apr 1 09:28:35 2011 (r6471) @@ -59,29 +59,35 @@ GIO2, 8, GIO3, 8, Offset(0x0c), // GPIO Level - GL00, 6, - GP07, 1, // GDET + GP00, 1, + GP01, 1, + GP02, 1, + GP03, 1, + GP04, 1, + GP05, 1, + GP06, 1, // GDET + GP07, 1, GP08, 1, - GP09, 1, - GP10, 1, // HPMU - GP11, 1, // GPSE - GP12, 1, - GP13, 1, // WLED - GP14, 1, // BLED - GP15, 1, // GLED - GP16, 1, // GDIS + GP09, 1, // HPMU + GP10, 1, // GPSE + GP11, 1, + GP12, 1, // WLED + GP13, 1, // BLED + GP14, 1, // GLED + GP15, 1, // GDIS + GP16, 1, GP17, 1, - GP18, 1, - GP19, 1, // SPCI - GP20, 1, // TSDT - GP21, 1, // SCPU + GP18, 1, // SPCI + GP19, 1, // TSDT + GP20, 1, // SCPU + GP21, 1, GP22, 1, - GP23, 1, - GP24, 1, // LANP - GP25, 1, // DKLR - GP26, 1, // WLAN - GP27, 1, // SATA_PWR_EN #0 / SPOF - GP28, 1, // SATA_PWR_EN #1 / SPMU + GP23, 1, // LANP + GP24, 1, // DKLR + GP25, 1, // WLAN + GP26, 1, // SATA_PWR_EN #0 / SPOF + GP27, 1, // SATA_PWR_EN #1 / SPMU + GP28, 1, GP29, 1, GP30, 1, GP31, 1,

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[PATCH] FILO: Add fallback autoboot option
by Nathan Williams 01 Apr '11

01 Apr '11

This patch adds a fallback command line in case the autoboot command line fails. This could be used on an AMD Geode board to try booting a kernel off IDE, before falling back to NAND flash. Signed-off-by: Nathan Williams <nathan(a)traverse.com.au> Index: main/filo.c =================================================================== --- main/filo.c (revision 143) +++ main/filo.c (working copy) @@ -37,11 +37,11 @@ #define ESCAPE '\x1b' #if !defined(CONFIG_AUTOBOOT_FILE) -#define autoboot() ((void) 0) /* nop */ +#define autoboot() ((int) 0) /* nop */ #endif #ifndef CONFIG_AUTOBOOT_DELAY -#define autoboot_delay() 0 /* success */ +#define autoboot_delay(boot_type) 0 /* success */ #endif struct sys_info sys_info; @@ -156,7 +156,7 @@ #ifdef CONFIG_AUTOBOOT_FILE #ifdef CONFIG_AUTOBOOT_DELAY -static inline int autoboot_delay(void) +static inline int autoboot_delay(const char *boot_type) { u64 timeout; int sec, tmp; @@ -164,7 +164,7 @@ key = 0; - printf("Press <Enter> for default boot, or <Esc> for boot prompt... "); + printf("Press <Enter> for %s boot, or <Esc> for boot prompt... ", boot_type); for (sec = CONFIG_AUTOBOOT_DELAY; sec>0 && key==0; sec--) { printf("%d", sec); timeout = currticks() + TICKS_PER_SEC; @@ -191,17 +191,33 @@ } #endif /* CONFIG_AUTOBOOT_DELAY */ -static void autoboot(void) +static int autoboot(void) { /* If Escape key is pressed already, skip autoboot */ if (havechar() && getchar()==ESCAPE) - return; + return 0; - if (autoboot_delay()==0) { + if (autoboot_delay("default")==0) { printf("boot: %s\n", CONFIG_AUTOBOOT_FILE); boot(CONFIG_AUTOBOOT_FILE); + return 1; } + return 0; } + +#ifdef CONFIG_FALLBACKBOOT_FILE +static void fallbackboot(void) +{ + /* If Escape key is pressed already, skip autoboot */ + if (havechar() && getchar()==ESCAPE) + return; + + if (autoboot_delay("fallback")==0) { + printf("boot: %s\n", CONFIG_FALLBACKBOOT_FILE); + boot(CONFIG_FALLBACKBOOT_FILE); + } +} +#endif /* FALLBACKBOOT_FILE */ #endif /* AUTOBOOT_FILE */ /* The main routine */ @@ -213,17 +229,30 @@ init(); /* Try default image */ - autoboot(); + if (autoboot()) { + /* Default boot has failed */ +#ifdef CONFIG_AUTOBOOT_FILE +#ifdef CONFIG_FALLBACKBOOT_FILE + fallbackboot(); + strncpy(line, CONFIG_FALLBACKBOOT_FILE, sizeof(line)-1); +#else + strncpy(line, CONFIG_AUTOBOOT_FILE, sizeof(line)-1); +#endif +#endif + line[sizeof(line)-1] = '\0'; + } else { + /* Either CONFIG_AUTOBOOT_FILE not defined, or delay escaped by user */ +#ifdef CONFIG_AUTOBOOT_FILE + strncpy(line, CONFIG_AUTOBOOT_FILE, sizeof(line)-1); + line[sizeof(line)-1] = '\0'; +#else + line[0] = '\0'; +#endif + } /* The above didn't work, ask user */ while (havechar()) getchar(); -#ifdef CONFIG_AUTOBOOT_FILE - strncpy(line, CONFIG_AUTOBOOT_FILE, sizeof(line)-1); - line[sizeof(line)-1] = '\0'; -#else - line[0] = '\0'; -#endif for (;;) { printf("boot: "); getline(line, sizeof line); Index: Config.in =================================================================== --- Config.in (revision 143) +++ Config.in (working copy) @@ -75,6 +75,23 @@ help Time in second before booting AUTOBOOT_FILE +config USE_FALLBACKBOOT + bool "Use a fallback command line" + default n + depends on USE_AUTOBOOT + help + If autoboot fails, try a fallback command line. + +config FALLBACKBOOT_FILE + string "Fallback kernel filename and parameters" + default "" + depends on USE_FALLBACKBOOT + help + #FALLBACKBOOT_FILE = "mem@0xfff80000" + #FALLBACKBOOT_FILE = "hde1@0" + #FALLBACKBOOT_FILE = "uda1:/vmlinuz.elf" + #FALLBACKBOOT_FILE = "flashb@0x00400000,0x154a00 console=tty0 console=ttyS0,115200" + config ISOLINUX_PARSER bool "Support for parsing isolinux.cfg config files" default n

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[PATCH] FILO: Kconfig option for forcing NAND flash mode
by Nathan Williams 01 Apr '11

01 Apr '11

This patch adds support for enabling NAND flash even if it hasn't been set up by coreboot. Since DIVIL_LBAR_FLSH[x], NANDF_DATA and NANDF_CTL are likely to be incorrect, they can be specified in Kconfig as well. Signed-off-by: Nathan Williams <nathan(a)traverse.com.au> Index: Config.in =================================================================== --- Config.in (revision 143) +++ Config.in (working copy) @@ -141,6 +141,46 @@ help Driver for Geode NAND flash storage +config FORCE_NAND_FLASH + bool "Enable NAND flash automatically" + default n + depends on FLASH_DISK + help + If Geode is currently set to IDE mode, change + to NAND flash mode. + +config DIVIL_LBAR_FLSH_HI + hex "LBAR_FLSH[x] (hi)" + default "0xfffff007" + depends on FORCE_NAND_FLASH + help + Local BAR Flash Chip Select. See AMD Geode CS5536 Companion + Device Data Book section 6.6.2.8 for details. + +config DIVIL_LBAR_FLSH_LO + hex "LBAR_FLSH[x] (lo)" + default "0x20000000" + depends on FORCE_NAND_FLASH + help + Local BAR Flash Chip Select. See AMD Geode CS5536 Companion + Device Data Book section 6.6.2.8 for details. + +config NANDF_DATA + hex "Initial NANDF_DATA" + default "0x00100010" + depends on FORCE_NAND_FLASH + help + Specify NAND Flash Data Timing MSR value. See AMD Geode + CS5536 Companion Device Data Book section 6.19.1.3 for details. + +config NANDF_CTL + hex "Initial NANDF_CTL" + default "0x00000010" + depends on FORCE_NAND_FLASH + help + Specify NAND Flash Control Timing MSR value. See AMD Geode + CS5536 Companion Device Data Book section 6.19.1.4 for details. + config SUPPORT_PCI bool "PCI support" default y Index: drivers/flash/lxflash.c =================================================================== --- drivers/flash/lxflash.c (revision 143) +++ drivers/flash/lxflash.c (working copy) @@ -523,8 +523,21 @@ int NAND_close(void) { - if (g_chipID >= 0) + if (g_chipID >= 0) { wrmsr(MSR_DIVIL_LBAR_FLSH0 + g_chipID, g_orig_flsh); +#ifdef CONFIG_FORCE_NAND_FLASH + // Set up NAND data and control timing for OS + msr_t tmp; + + tmp = rdmsr(MSR_NANDF_DATA); + tmp.lo = CONFIG_NANDF_DATA; + wrmsr(MSR_NANDF_DATA, tmp); + + tmp = rdmsr(MSR_NANDF_CTL); + tmp.lo = CONFIG_NANDF_CTL; + wrmsr(MSR_NANDF_CTL, tmp); +#endif + } } //////////////////////////////////////////////////////////////////////////////// @@ -547,19 +560,31 @@ msr = rdmsr(MSR_DIVIL_BALL_OPTS); if (msr.lo & PIN_OPT_IDE) { +#ifndef CONFIG_FORCE_NAND_FLASH printf("NAND controller not enabled!\n"); return -1; +#else + printf("Enabling NAND controller\n"); + msr.lo &= ~PIN_OPT_IDE; + wrmsr(MSR_DIVIL_BALL_OPTS, msr); +#endif } /////////////////////////////////////////////////////////////////////////////////// // init the MSR_DIVIL_LBAR_FLSHx register, I/O mapped mode, set a hardcoded base address // Later we restore initial state +#ifdef CONFIG_FORCE_NAND_FLASH + // When we NAND_close() restore to these values instead + g_orig_flsh.hi = CONFIG_DIVIL_LBAR_FLSH_HI; + g_orig_flsh.lo = CONFIG_DIVIL_LBAR_FLSH_LO; +#else g_orig_flsh = rdmsr(MSR_DIVIL_LBAR_FLSH0 + chipNum); if (!(g_orig_flsh.hi & NOR_NAND)) { printf("CS%d set up for NOR, aborting!\n", chipNum); return -1; } +#endif msr.hi = SET_FLSH_HIGH; msr.lo = SET_FLSH_LOW;

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[PATCH] Add build instructions for coreinfo in readme
by Hamo 01 Apr '11

01 Apr '11

Add build instructions for coreinfo, specially pointing out installing gcc-multilib on a 64bit system. Signed-off-by: Yang Hamo Bai <hamo.by(a)gmail.com> This is the very first time I send a patch to coreboot, any comment is welcome. Thanks.

2 2

[commit] r6470 - trunk/payloads/coreinfo
by repository service 01 Apr '11

01 Apr '11

Author: stepan Date: Fri Apr 1 02:39:07 2011 New Revision: 6470 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6470 Log: Add build instructions for coreinfo, specially pointing out installing gcc-multilib on a 64bit system. Signed-off-by: Yang Hamo Bai <hamo.by(a)gmail.com> Acked-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Modified: trunk/payloads/coreinfo/README Modified: trunk/payloads/coreinfo/README ============================================================================== --- trunk/payloads/coreinfo/README Tue Mar 29 21:29:01 2011 (r6469) +++ trunk/payloads/coreinfo/README Fri Apr 1 02:39:07 2011 (r6470) @@ -1,3 +1,27 @@ This is a silly little program that demonstrates how cool libpayload is and also serves a purpose. Its fun and educational! +Requirements +------------ + +You should use the coreboot reference cross compiler. If you insist on using +your system compiler, some Linux distributions might require you to install +a package called gcc-multilib if you are on a 64bit system. + +Build +----- + +You need libpayload to build coreinfo. So, first, you need follow the README of +libpayload to build it but install libpayload into its own directory by doing +this: + + $ make DESTDIR=/path/to/libpayload/install install + +Then you can build coreinfo now: + + $ cd coreinfo + + $ make menuconfig + + $ make +

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coreboot April 2011