coreboot April 2011

coreboot@coreboot.org

66 participants
229 discussions

GSoC application deadline 4/8
by Marc Jones 07 Apr '11

07 Apr '11

Hello Students, As you probably know, the deadline for GSoC is just a day away. Please make sure to get your application submitted before the deadline. The mentors will start to review the applications, ask questions, and allow students to make adjustments early next week. Please make sure that you answer the standard coreboot part of the application. Feel free to stop in IRC or send email if you have any questions. http://www.coreboot.org/GSoC Regards, Marc -- http://se-eng.com

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Re: [coreboot] [PATCH] 440BX registered SDRAM support
by Keith Hui 07 Apr '11

07 Apr '11

>> + if ((edosd & 0x84) == 0x84) { >> + edosd = 0x10; // Registered SDRAM >> + } else { >> + // Clear [4:3] in case it's EDO. >> + edosd &= 0x07; >> +// } else if (edosd & 0x02) { > Besides being commented out, this piece of code would never be executed, > as there already is an else case. > Also, modifying edosd in place is semi nice. So is this good, not so good, or bad? I want to know if I should split up edosd. > > Please clean this up before committing. Maybe consider using switch/case? > > Looks good otherwise. >> +// edosd |= 0x00; >> + if (edosd & 0x04) { >> + edosd |= 0x08; // SDRAM >> + } >> } >> + // Keep only [4:3]. >> edosd &= 0x18; >> Thanks Keith

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[RFC][PATCHv2]add WIP_ARM config entry
by Hamo 07 Apr '11

07 Apr '11

Add WIP_ARM config entry so that we can make all ARM-related entries depend on this now. We need to make all the ARM-related code available to ALL so that we can attract those interested in ARM to join us. During this process, some of the code may not be usable, so we need this to ensure that those normal users will not be upset with it. Signed-off-by: Yang Bai <hamo.by(a)gmail.com> P.S. Can I use git diff to generate the patch? Index: src/Kconfig =================================================================== --- src/Kconfig (revision 6481) +++ src/Kconfig (working copy) @@ -21,6 +21,16 @@ menu "General setup" +config WIP_ARM + bool "Prompt for unfinished ARM options" + default n + help + This will show you the configuration options about Coreboot ARM + support. + + Warning: Since ARM porting is now working in process, the code + for ARM may be not usable. + config EXPERT bool "Expert mode" help

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where can i ask detailed technical questions about hardware?
by ali hagigat 06 Apr '11

06 Apr '11

I wonder if any one knows about some forums or sites for asking questions about the data sheets contents of mother board ICs. I am investing about Intel ICs. Though Intel has some forums but they are inactive and questions remain unanswered. Is there any active site to discuss Intel data sheets? Regards

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VIA EPIA V5000 Problems
by Andreas Franz 06 Apr '11

06 Apr '11

Hello, I am trying to use Coreboot + Filo + Debian Linux on the VIA EPIA V5000 board. I had no problems compiling and flashing coreboot, but running into trouble when booting. The serial console states the following and than simply stops: vt8601 init starting 00000000 is the north 1106 0601 0120d4 is the computed timing NOP PRECHARGE DUMMY READS CBR MRS NORMAL set ref. rate enable multi-page open Slot 00 is SDRAM 08000000 bytes x2 000c is the MA type Slot 01 is empty Slot 02 is empty Slot 03 is empty vt8601 done Loading image. Check CBFS header at fffeffe0 magic is 4f524243 Found CBFS header at fffeffe0 Check cmos_layout.bin CBFS: follow chain: fffc0000 + 28 + 487 + align -> fffc04c0 Check pci1106,3230.rom CBFS: follow chain: fffc04c0 + 38 + 10000 + align -> fffd0500 Check fallback/coreboot_ram Stage: loading fallback/coreboot_ram @ 0x100000 (114688 bytes), entry @ 0x100000 I guess ist has something to do with RAM-init? Any help/hint is appreciated. Thanks Andreas Franz

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[PATCH] Print what mainboard coreboot is being built for during build
by Nickolas Lloyd 06 Apr '11

06 Apr '11

>From 404e7bd11e3dadf912b45057000e053db5ed7e90 Mon Sep 17 00:00:00 2001 From: Nickolas Lloyd <ntlloyd(a)uncg.edu> Date: Tue, 5 Apr 2011 19:18:07 -0400 Subject: [PATCH] Print what mainboard coreboot is being built for during build Print a message before and after build saying what mainboard coreboot is being built for. Only print after build if build was successful Signed-off-by: Nickolas Lloyd <ntlloyd(a)uncg.edu> --- Makefile | 1 + Makefile.inc | 4 +++- 2 files changed, 4 insertions(+), 1 deletions(-) diff --git a/Makefile b/Makefile index 06847b6..ddc12a6 100644 --- a/Makefile +++ b/Makefile @@ -145,6 +145,7 @@ real-all: else real-all: real-target endif + @echo "Built coreboot for $(CONFIG_MAINBOARD_VENDOR) $(CONFIG_MAINBOARD_PART_NUMBER)" # must come rather early .SECONDEXPANSION: diff --git a/Makefile.inc b/Makefile.inc index 3f553c6..74b4455 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -31,7 +31,9 @@ export MAINBOARDDIR ####################################################################### # root rule to resolve if in build mode (ie. configuration exists) real-target: $(obj)/config.h coreboot -coreboot: $(obj)/coreboot.rom +coreboot: building-msg $(obj)/coreboot.rom +building-msg: + @echo "Building coreboot for $(CONFIG_MAINBOARD_VENDOR) $(CONFIG_MAINBOARD_PART_NUMBER)" ####################################################################### # our phony targets -- 1.7.4.1

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[commit] r6478 - trunk/src/mainboard/lenovo/x60
by repository service 05 Apr '11

05 Apr '11

Author: svens Date: Mon Apr 4 14:33:54 2011 New Revision: 6478 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6478 Log: X60: log firmware version Signed-off-by: Sven Schnelle <svens(a)stackframe.org> Acked-by: Sven Schnelle <svens(a)stackframe.org> Modified: trunk/src/mainboard/lenovo/x60/mainboard.c Modified: trunk/src/mainboard/lenovo/x60/mainboard.c ============================================================================== --- trunk/src/mainboard/lenovo/x60/mainboard.c Mon Apr 4 12:57:17 2011 (r6477) +++ trunk/src/mainboard/lenovo/x60/mainboard.c Mon Apr 4 14:33:54 2011 (r6478) @@ -51,7 +51,24 @@ static void mainboard_enable(device_t dev) { + unsigned char ecfw[9], c; + u16 fwvh, fwvl; device_t dev0; + int i; + + for(i = 0; i < 8; i++) { + c = ec_read(0xf0 + i); + if (c < 0x20 || c > 0x7f) + break; + ecfw[i] = c; + } + ecfw[i] = '\0'; + + fwvh = ec_read(0xe9); + fwvl = ec_read(0xe8); + + printk(BIOS_INFO, "EC Firmware ID %s, Version %d.%d%d%c\n", ecfw, + fwvh >> 4, fwvh & 0x0f, fwvl >> 4, 0x41 + (fwvl & 0xf)); backlight_enable(); trackpoint_enable();

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[commit] r6481 - trunk/src/mainboard/lenovo/x60
by repository service 05 Apr '11

05 Apr '11

Author: svens Date: Tue Apr 5 15:00:33 2011 New Revision: 6481 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6481 Log: X60: use pnp_write_config() instead of custom function Signed-off-by: Sven Schnelle <svens(a)stackframe.org> Acked-by: Sven Schnelle <svens(a)stackframe.org> Modified: trunk/src/mainboard/lenovo/x60/romstage.c Modified: trunk/src/mainboard/lenovo/x60/romstage.c ============================================================================== --- trunk/src/mainboard/lenovo/x60/romstage.c Tue Apr 5 15:00:14 2011 (r6480) +++ trunk/src/mainboard/lenovo/x60/romstage.c Tue Apr 5 15:00:33 2011 (r6481) @@ -101,25 +101,20 @@ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8e, 0x001c); } -static void pnp_write_register(device_t dev, int reg, int val) -{ - unsigned int port = dev >> 8; - outb(reg, port); - outb(val, port+1); -} - static void early_superio_config(void) { - device_t dev; + int timeout = 100000; + device_t dev = PNP_DEV(0x2e, 3); + + pnp_write_config(dev, 0x29, 0x06); - dev=PNP_DEV(0x2e, 0x00); - pnp_write_register(dev, 0x29, 0x06); + while(!(pnp_read_config(dev, 0x29) & 0x08) && timeout--) + udelay(1000); /* Enable COM1 */ - pnp_write_register(dev, 0x07, 0x03); - pnp_write_register(dev, 0x60, 0x03); - pnp_write_register(dev, 0x61, 0xf8); - pnp_write_register(dev, 0x30, 0x01); + pnp_set_logical_device(dev); + pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8); + pnp_set_enable(dev, 1); } static void rcba_config(void)

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[commit] r6480 - trunk/src/mainboard/lenovo/x60
by repository service 05 Apr '11

05 Apr '11

Author: svens Date: Tue Apr 5 15:00:14 2011 New Revision: 6480 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6480 Log: X60: move ec version info code to log_ec_version() Signed-off-by: Sven Schnelle <svens(a)stackframe.org> Acked-by: Sven Schnelle <svens(a)stackframe.org> Modified: trunk/src/mainboard/lenovo/x60/mainboard.c Modified: trunk/src/mainboard/lenovo/x60/mainboard.c ============================================================================== --- trunk/src/mainboard/lenovo/x60/mainboard.c Mon Apr 4 17:19:59 2011 (r6479) +++ trunk/src/mainboard/lenovo/x60/mainboard.c Tue Apr 5 15:00:14 2011 (r6480) @@ -49,11 +49,10 @@ ec_write(0x3a, 0x20); } -static void mainboard_enable(device_t dev) +static void log_ec_version(void) { unsigned char ecfw[9], c; u16 fwvh, fwvl; - device_t dev0; int i; for(i = 0; i < 8; i++) { @@ -69,9 +68,17 @@ printk(BIOS_INFO, "EC Firmware ID %s, Version %d.%d%d%c\n", ecfw, fwvh >> 4, fwvh & 0x0f, fwvl >> 4, 0x41 + (fwvl & 0xf)); +} + +static void mainboard_enable(device_t dev) +{ + device_t dev0; + + log_ec_version(); backlight_enable(); trackpoint_enable(); + /* FIXME: this should be ACPI's task * but for now, enable it here */ wlan_enable();

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[RFC][PATCH]add EXPERIMENTAL config entry
by Hamo 05 Apr '11

05 Apr '11

Add EXPERIMENTAL config entry so that we can make all ARM-related entries depend on this now. We need to make all the ARM-related code available to ALL so that we can attract those interested in ARM to join us. During this process, some of the code may not be usable, so we need this to ensure that those normal users will not be upset with it. Signed-off-by: Yang Hamo Bai <hamo.by(a)gmail.com> Index: src/Kconfig =================================================================== --- src/Kconfig (revision 6479) +++ src/Kconfig (working copy) @@ -21,6 +21,12 @@ menu "General setup" +config EXPERIMENTAL + bool "Prompt for developement and/or incomplete code" + default n + help + Some of the various things that Coreboot supports can be in a state of development where the functionality, stability, or the level of testing is not yet high enough fro general use. + config EXPERT bool "Expert mode" help

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coreboot April 2011