coreboot April 2011

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[commit] r6499 - trunk/src/cpu/x86/mtrr
by repository service 14 Apr '11

14 Apr '11

Author: stepan Date: Thu Apr 14 22:39:49 2011 New Revision: 6499 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6499 Log: earlymtrr.c: wipe some dead code, use names instead of numbers and some cosmetics. Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Modified: trunk/src/cpu/x86/mtrr/earlymtrr.c Modified: trunk/src/cpu/x86/mtrr/earlymtrr.c ============================================================================== --- trunk/src/cpu/x86/mtrr/earlymtrr.c Thu Apr 14 22:33:53 2011 (r6498) +++ trunk/src/cpu/x86/mtrr/earlymtrr.c Thu Apr 14 22:39:49 2011 (r6499) @@ -5,19 +5,6 @@ #include <cpu/amd/mtrr.h> #include <cpu/x86/msr.h> -#if 0 -static void disable_var_mtrr(unsigned reg) -{ - /* The invalid bit is kept in the mask so we simply - * clear the relevent mask register to disable a - * range. - */ - msr_t zero; - zero.lo = zero.hi = 0; - wrmsr(MTRRphysMask_MSR(reg), zero); -} -#endif - static void set_var_mtrr( unsigned reg, unsigned base, unsigned size, unsigned type) @@ -28,33 +15,13 @@ basem.lo = base | type; basem.hi = 0; wrmsr(MTRRphysBase_MSR(reg), basem); - maskm.lo = ~(size - 1) | 0x800; - maskm.hi = (1<<(CONFIG_CPU_ADDR_BITS-32))-1; + maskm.lo = ~(size - 1) | MTRRphysMaskValid; + maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1; wrmsr(MTRRphysMask_MSR(reg), maskm); } -#if 0 -static void set_var_mtrr_x( - unsigned reg, uint32_t base_lo, uint32_t base_hi, uint32_t size_lo, uint32_t size_hi, unsigned type) - -{ - /* Bit Bit 32-35 of MTRRphysMask should be set to 1 */ - msr_t basem, maskm; - basem.lo = (base_lo & 0xfffff000) | type; - basem.hi = base_hi & ((1<<(CONFIG_CPU_ADDR_BITS-32))-1); - wrmsr(MTRRphysBase_MSR(reg), basem); - maskm.hi = (1<<(CONFIG_CPU_ADDR_BITS-32))-1; - if(size_lo) { - maskm.lo = ~(size_lo - 1) | 0x800; - } else { - maskm.lo = 0x800; - maskm.hi &= ~(size_hi - 1); - } - wrmsr(MTRRphysMask_MSR(reg), maskm); -} -#endif - -static inline void cache_lbmem(int type) +#if !defined(CONFIG_CACHE_AS_RAM) || (CONFIG_CACHE_AS_RAM == 0) +static void cache_lbmem(int type) { /* Enable caching for 0 - 1MB using variable mtrr */ disable_cache(); @@ -62,7 +29,6 @@ enable_cache(); } -#if !defined(CONFIG_CACHE_AS_RAM) || (CONFIG_CACHE_AS_RAM == 0) /* the fixed and variable MTTRs are power-up with random values, * clear them to MTRR_TYPE_UNCACHEABLE for safty. */ @@ -119,7 +85,6 @@ do_early_mtrr_init(mtrr_msrs); enable_cache(); } -#endif static inline int early_mtrr_init_detected(void) { @@ -131,7 +96,8 @@ * according to the documentation. */ msr = rdmsr(MTRRdefType_MSR); - return msr.lo & 0x00000800; + return msr.lo & MTRRdefTypeEn; } +#endif #endif /* EARLYMTRR_C */

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[commit] r6498 - trunk/src/arch/x86/lib
by repository service 14 Apr '11

14 Apr '11

Author: stepan Date: Thu Apr 14 22:33:53 2011 New Revision: 6498 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6498 Log: add some comments to walkcbfs.S Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Modified: trunk/src/arch/x86/lib/walkcbfs.S Modified: trunk/src/arch/x86/lib/walkcbfs.S ============================================================================== --- trunk/src/arch/x86/lib/walkcbfs.S Thu Apr 14 22:30:21 2011 (r6497) +++ trunk/src/arch/x86/lib/walkcbfs.S Thu Apr 14 22:33:53 2011 (r6498) @@ -16,11 +16,11 @@ #define CBFS_FILE_STRUCTSIZE (CBFS_FILE_OFFSET + 4) /* - input %esi: filename - input %esp: return address (not pointer to return address!) - output %eax: entry point - clobbers %ebx, %ecx, %edi -*/ + * input %esi: filename + * input %esp: return address (not pointer to return address!) + * output %eax: entry point + * clobbers %ebx, %ecx, %edi + */ walkcbfs_asm: cld @@ -28,10 +28,10 @@ mov CBFS_HEADER_ROMSIZE(%eax), %ecx bswap %ecx mov $0, %ebx - sub %ecx, %ebx + sub %ecx, %ebx /* rom base address in ebx */ mov CBFS_HEADER_OFFSET(%eax), %ecx bswap %ecx - add %ecx, %ebx + add %ecx, %ebx /* address where we start looking for LARCHIVEs */ /* determine filename length */ mov $0, %eax @@ -43,21 +43,22 @@ 2: add $1, %eax walker: - mov 0(%ebx), %edi + mov 0(%ebx), %edi /* Check for LARCHIVE header */ cmp %edi, filemagic jne searchfile mov 4(%ebx), %edi cmp %edi, filemagic+4 jne searchfile + /* LARCHIVE header found */ mov %ebx, %edi add $CBFS_FILE_STRUCTSIZE, %edi /* edi = address of first byte after struct cbfs_file */ mov %eax, %ecx repe cmpsb - # zero flag set if strings are equal + /* zero flag set if strings are equal */ jnz tryharder - # we found it! + /* we found it! */ mov CBFS_FILE_OFFSET(%ebx), %eax bswap %eax add %ebx, %eax

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[commit] r6496 - in trunk/src: arch/x86 arch/x86/lib cpu/x86/16bit northbridge/via/vx800 southbridge/nvidia/ck804 southbridge/nvidia/mcp55 southbridge/sis/sis966 southbridge/via/k8t890
by repository service 14 Apr '11

14 Apr '11

Author: stepan Date: Thu Apr 14 22:21:49 2011 New Revision: 6496 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6496 Log: drop incorrectly used CONFIG_ROM_IMAGE_SIZE and unused CONFIG_ARCH Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Modified: trunk/src/arch/x86/Kconfig trunk/src/arch/x86/lib/id.lds trunk/src/cpu/x86/16bit/reset16.lds trunk/src/northbridge/via/vx800/romstrap.lds trunk/src/southbridge/nvidia/ck804/romstrap.lds trunk/src/southbridge/nvidia/mcp55/romstrap.lds trunk/src/southbridge/sis/sis966/romstrap.lds trunk/src/southbridge/via/k8t890/romstrap.lds Modified: trunk/src/arch/x86/Kconfig ============================================================================== --- trunk/src/arch/x86/Kconfig Thu Apr 14 22:11:34 2011 (r6495) +++ trunk/src/arch/x86/Kconfig Thu Apr 14 22:21:49 2011 (r6496) @@ -8,20 +8,10 @@ default n depends on ARCH_X86 -# This is the name of the respective architecture subdirectory in arch/. -config ARCH - string - default i386 - depends on ARCH_X86 - config ROMBASE hex default 0xffff0000 -config ROM_IMAGE_SIZE - hex - default 0x10000 - config RAMBASE hex default 0x100000 Modified: trunk/src/arch/x86/lib/id.lds ============================================================================== --- trunk/src/arch/x86/lib/id.lds Thu Apr 14 22:11:34 2011 (r6495) +++ trunk/src/arch/x86/lib/id.lds Thu Apr 14 22:21:49 2011 (r6496) @@ -1,5 +1,5 @@ SECTIONS { - . = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - CONFIG_ID_SECTION_OFFSET) - (__id_end - __id_start); + . = (0x100000000 - CONFIG_ID_SECTION_OFFSET) - (__id_end - __id_start); .id (.): { *(.id) } Modified: trunk/src/cpu/x86/16bit/reset16.lds ============================================================================== --- trunk/src/cpu/x86/16bit/reset16.lds Thu Apr 14 22:11:34 2011 (r6495) +++ trunk/src/cpu/x86/16bit/reset16.lds Thu Apr 14 22:21:49 2011 (r6496) @@ -5,7 +5,7 @@ SECTIONS { /* Trigger an error if I have an unuseable start address */ - _bogus = ASSERT(_start >= 0xffff0000, "_start too low. Please decrease CONFIG_ROM_IMAGE_SIZE"); + _bogus = ASSERT(_start >= 0xffff0000, "_start too low. Please report."); _ROMTOP = 0xfffffff0; . = _ROMTOP; .reset . : { Modified: trunk/src/northbridge/via/vx800/romstrap.lds ============================================================================== --- trunk/src/northbridge/via/vx800/romstrap.lds Thu Apr 14 22:11:34 2011 (r6495) +++ trunk/src/northbridge/via/vx800/romstrap.lds Thu Apr 14 22:21:49 2011 (r6496) @@ -19,7 +19,7 @@ */ SECTIONS { - . = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - 0x2c) - (__romstrap_end - __romstrap_start); + . = (0x100000000 - 0x2c) - (__romstrap_end - __romstrap_start); .romstrap (.): { *(.romstrap) } Modified: trunk/src/southbridge/nvidia/ck804/romstrap.lds ============================================================================== --- trunk/src/southbridge/nvidia/ck804/romstrap.lds Thu Apr 14 22:11:34 2011 (r6495) +++ trunk/src/southbridge/nvidia/ck804/romstrap.lds Thu Apr 14 22:21:49 2011 (r6496) @@ -19,7 +19,7 @@ */ SECTIONS { - . = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - 0x10) - (__romstrap_end - __romstrap_start); + . = (0x100000000 - 0x10) - (__romstrap_end - __romstrap_start); .romstrap (.): { *(.romstrap) } Modified: trunk/src/southbridge/nvidia/mcp55/romstrap.lds ============================================================================== --- trunk/src/southbridge/nvidia/mcp55/romstrap.lds Thu Apr 14 22:11:34 2011 (r6495) +++ trunk/src/southbridge/nvidia/mcp55/romstrap.lds Thu Apr 14 22:21:49 2011 (r6496) @@ -20,7 +20,7 @@ */ SECTIONS { - . = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - 0x10) - (__romstrap_end - __romstrap_start); + . = (0x100000000 - 0x10) - (__romstrap_end - __romstrap_start); .romstrap (.): { *(.romstrap) } Modified: trunk/src/southbridge/sis/sis966/romstrap.lds ============================================================================== --- trunk/src/southbridge/sis/sis966/romstrap.lds Thu Apr 14 22:11:34 2011 (r6495) +++ trunk/src/southbridge/sis/sis966/romstrap.lds Thu Apr 14 22:21:49 2011 (r6496) @@ -20,7 +20,7 @@ */ SECTIONS { - . = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - 0x10) - (__romstrap_end - __romstrap_start); + . = (0x100000000 - 0x10) - (__romstrap_end - __romstrap_start); .romstrap (.): { *(.romstrap) } Modified: trunk/src/southbridge/via/k8t890/romstrap.lds ============================================================================== --- trunk/src/southbridge/via/k8t890/romstrap.lds Thu Apr 14 22:11:34 2011 (r6495) +++ trunk/src/southbridge/via/k8t890/romstrap.lds Thu Apr 14 22:21:49 2011 (r6496) @@ -22,7 +22,7 @@ /* Modified for K8T890 ROM strap by Rudolf Marek <r.marek(a)assembler.cz>. */ SECTIONS { - . = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - 0x2c) - (__romstrap_end - __romstrap_start); + . = (0x100000000 - 0x2c) - (__romstrap_end - __romstrap_start); .romstrap (.): { *(.romstrap) }

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[commit] r6495 - trunk/src/southbridge/nvidia/mcp55
by repository service 14 Apr '11

14 Apr '11

Author: stepan Date: Thu Apr 14 22:11:34 2011 New Revision: 6495 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6495 Log: nvidia mcp55: drop unused dbg_info Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Modified: trunk/src/southbridge/nvidia/mcp55/usb2.c Modified: trunk/src/southbridge/nvidia/mcp55/usb2.c ============================================================================== --- trunk/src/southbridge/nvidia/mcp55/usb2.c Thu Apr 14 22:10:27 2011 (r6494) +++ trunk/src/southbridge/nvidia/mcp55/usb2.c Thu Apr 14 22:11:34 2011 (r6495) @@ -29,8 +29,6 @@ #include "mcp55.h" #include <usbdebug.h> -extern struct ehci_debug_info dbg_info; - static void usb2_init(struct device *dev) { u32 dword;

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[commit] r6494 - trunk/src/southbridge/sis/sis966
by repository service 14 Apr '11

14 Apr '11

Author: stepan Date: Thu Apr 14 22:10:27 2011 New Revision: 6494 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6494 Log: cosmetic cleanup of sis966 usb2 code Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Modified: trunk/src/southbridge/sis/sis966/usb2.c Modified: trunk/src/southbridge/sis/sis966/usb2.c ============================================================================== --- trunk/src/southbridge/sis/sis966/usb2.c Thu Apr 14 22:06:30 2011 (r6493) +++ trunk/src/southbridge/sis/sis966/usb2.c Thu Apr 14 22:10:27 2011 (r6494) @@ -32,52 +32,50 @@ #include "sis966.h" #include <usbdebug.h> -extern struct ehci_debug_info dbg_info; +static const u8 SiS_SiS7002_init[22][3]={ + {0x04, 0x00, 0x06}, + {0x0D, 0x00, 0x00}, + + {0x2C, 0xFF, 0x39}, + {0x2D, 0xFF, 0x10}, + {0x2E, 0xFF, 0x02}, + {0x2F, 0xFF, 0x70}, + + {0x74, 0x00, 0x00}, + {0x75, 0x00, 0x00}, + {0x76, 0x00, 0x00}, + {0x77, 0x00, 0x00}, + + {0x7A, 0x00, 0x00}, + {0x7B, 0x00, 0x00}, + + {0x40, 0x00, 0x20}, + {0x41, 0x00, 0x00}, + {0x42, 0x00, 0x00}, + {0x43, 0x00, 0x08}, + + {0x44, 0x00, 0x04}, + + {0x48, 0x00, 0x10}, + {0x49, 0x00, 0x80}, + {0x4A, 0x00, 0x07}, + {0x4B, 0x00, 0x00}, -u8 SiS_SiS7002_init[22][3]={ -{0x04, 0x00, 0x06}, -{0x0D, 0x00, 0x00}, - -{0x2C, 0xFF, 0x39}, -{0x2D, 0xFF, 0x10}, -{0x2E, 0xFF, 0x02}, -{0x2F, 0xFF, 0x70}, - -{0x74, 0x00, 0x00}, -{0x75, 0x00, 0x00}, -{0x76, 0x00, 0x00}, -{0x77, 0x00, 0x00}, - -{0x7A, 0x00, 0x00}, -{0x7B, 0x00, 0x00}, - -{0x40, 0x00, 0x20}, -{0x41, 0x00, 0x00}, -{0x42, 0x00, 0x00}, -{0x43, 0x00, 0x08}, - -{0x44, 0x00, 0x04}, - -{0x48, 0x00, 0x10}, -{0x49, 0x00, 0x80}, -{0x4A, 0x00, 0x07}, -{0x4B, 0x00, 0x00}, - -{0x00, 0x00, 0x00} //End of table + {0x00, 0x00, 0x00} //End of table }; static void usb2_init(struct device *dev) { u32 base; struct resource *res; + int i; + u8 temp8; print_debug("USB 2.0 INIT:---------->\n"); -//-------------- enable USB2.0 (SiS7002) ------------------------- -{ - u8 temp8; - int i=0; + //-------------- enable USB2.0 (SiS7002) ---------------------- + i = 0; while(SiS_SiS7002_init[i][0] != 0) { temp8 = pci_read_config8(dev, SiS_SiS7002_init[i][0]); @@ -86,7 +84,6 @@ pci_write_config8(dev, SiS_SiS7002_init[i][0], temp8); i++; }; -} res = find_resource(dev, 0x10); if(!res) @@ -95,12 +92,9 @@ base = res->base; printk(BIOS_DEBUG, "base = 0x%08x\n", base); write32(base+0x20, 0x2); -//----------------------------------------------------------- + //------------------------------------------------------------- #if DEBUG_USB2 -{ - int i; - print_debug("****** USB 2.0 PCI config ******"); print_debug("\n 03020100 07060504 0B0A0908 0F0E0D0C"); @@ -114,7 +108,6 @@ print_debug(" "); } print_debug("\n"); -} #endif print_debug("USB 2.0 INIT:<----------\n"); } @@ -139,7 +132,6 @@ set_ehci_base(base); report_resource_stored(dev, res, ""); #endif - } static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) @@ -147,6 +139,7 @@ pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); } + static struct pci_operations lops_pci = { .set_subsystem = lpci_set_subsystem, };

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[commit] r6493 - in trunk/src/cpu: amd/car intel/car intel/model_6ex intel/model_6fx
by repository service 14 Apr '11

14 Apr '11

Author: stepan Date: Thu Apr 14 22:06:30 2011 New Revision: 6493 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6493 Log: Use symbolic names for some MTRR bits instead of numbers in CAR code Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Modified: trunk/src/cpu/amd/car/cache_as_ram.inc trunk/src/cpu/intel/car/cache_as_ram.inc trunk/src/cpu/intel/model_6ex/cache_as_ram.inc trunk/src/cpu/intel/model_6fx/cache_as_ram.inc Modified: trunk/src/cpu/amd/car/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/amd/car/cache_as_ram.inc Thu Apr 14 21:52:04 2011 (r6492) +++ trunk/src/cpu/amd/car/cache_as_ram.inc Thu Apr 14 22:06:30 2011 (r6493) @@ -77,7 +77,7 @@ /* Check if cpu_init_detected. */ movl $MTRRdefType_MSR, %ecx rdmsr - andl $(1 << 11), %eax + andl $MTRRdefTypeEn, %eax movl %eax, %ebx /* We store the status. */ jmp_if_k8(CAR_FAM10_out_post_errata) @@ -306,7 +306,7 @@ jmp_if_k8(wbcache_post_fam10_setup) movl $0xffff, %edx /* (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1 for FAM10 (CONFIG_CPU_ADDR_BITS = 48) */ wbcache_post_fam10_setup: - movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax + movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax wrmsr #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */ Modified: trunk/src/cpu/intel/car/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/intel/car/cache_as_ram.inc Thu Apr 14 21:52:04 2011 (r6492) +++ trunk/src/cpu/intel/car/cache_as_ram.inc Thu Apr 14 22:06:30 2011 (r6493) @@ -254,7 +254,7 @@ movl $MTRRphysMask_MSR(1), %ecx movl $0x0000000f, %edx - movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax + movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax wrmsr #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */ @@ -354,7 +354,7 @@ */ movl $MTRRdefType_MSR, %ecx xorl %edx, %edx - movl $0x00000800, %eax /* Enable variable and disable fixed MTRRs. */ + movl $MTRRdefTypeEn, %eax /* Enable variable and disable fixed MTRRs. */ wrmsr /* Enable cache. */ Modified: trunk/src/cpu/intel/model_6ex/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/intel/model_6ex/cache_as_ram.inc Thu Apr 14 21:52:04 2011 (r6492) +++ trunk/src/cpu/intel/model_6ex/cache_as_ram.inc Thu Apr 14 22:06:30 2011 (r6493) @@ -63,14 +63,14 @@ /* Set Cache-as-RAM mask. */ movl $(MTRRphysMask_MSR(0)), %ecx - movl $(~((CACHE_AS_RAM_SIZE - 1)) | (1 << 11)), %eax + movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax movl $0x0000000f, %edx wrmsr /* Enable MTRR. */ movl $MTRRdefType_MSR, %ecx rdmsr - orl $(1 << 11), %eax + orl $MTRRdefTypeEn, %eax wrmsr /* Enable L2 cache. */ @@ -118,7 +118,7 @@ movl $MTRRphysMask_MSR(1), %ecx movl $0x0000000f, %edx - movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax + movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax wrmsr #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */ @@ -160,7 +160,7 @@ /* Disable MTRR. */ movl $MTRRdefType_MSR, %ecx rdmsr - andl $(~(1 << 11)), %eax + andl $(~MTRRdefTypeEn), %eax wrmsr post_code(0x31) @@ -201,7 +201,7 @@ xorl %edx, %edx wrmsr movl $MTRRphysMask_MSR(0), %ecx - movl $(~(1024 * 1024 - 1) | (1 << 11)), %eax + movl $(~(1024 * 1024 - 1) | MTRRphysMaskValid), %eax movl $0x0000000f, %edx // 36bit address space wrmsr @@ -217,7 +217,7 @@ /* Enable MTRR. */ movl $MTRRdefType_MSR, %ecx rdmsr - orl $(1 << 11), %eax + orl $MTRRdefTypeEn, %eax wrmsr post_code(0x3b) Modified: trunk/src/cpu/intel/model_6fx/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/intel/model_6fx/cache_as_ram.inc Thu Apr 14 21:52:04 2011 (r6492) +++ trunk/src/cpu/intel/model_6fx/cache_as_ram.inc Thu Apr 14 22:06:30 2011 (r6493) @@ -70,14 +70,14 @@ /* Set Cache-as-RAM mask. */ movl $(MTRRphysMask_MSR(0)), %ecx - movl $(~((CACHE_AS_RAM_SIZE - 1)) | (1 << 11)), %eax + movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax movl $0x0000000f, %edx wrmsr /* Enable MTRR. */ movl $MTRRdefType_MSR, %ecx rdmsr - orl $(1 << 11), %eax + orl $MTRRdefTypeEn, %eax wrmsr /* Enable L2 cache. */ @@ -125,7 +125,7 @@ movl $MTRRphysMask_MSR(1), %ecx movl $0x0000000f, %edx - movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax + movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax wrmsr #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */ @@ -167,7 +167,7 @@ /* Disable MTRR. */ movl $MTRRdefType_MSR, %ecx rdmsr - andl $(~(1 << 11)), %eax + andl $(~MTRRdefTypeEn), %eax wrmsr post_code(0x31) @@ -208,7 +208,7 @@ xorl %edx, %edx wrmsr movl $MTRRphysMask_MSR(0), %ecx - movl $(~(1024 * 1024 - 1) | (1 << 11)), %eax + movl $(~(1024 * 1024 - 1) | MTRRphysMaskValid), %eax movl $0x0000000f, %edx // 36bit address space wrmsr @@ -224,7 +224,7 @@ /* Enable MTRR. */ movl $MTRRdefType_MSR, %ecx rdmsr - orl $(1 << 11), %eax + orl $MTRRdefTypeEn, %eax wrmsr post_code(0x3b)

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[commit] r6492 - trunk/payloads/libpayload/drivers/usb
by repository service 14 Apr '11

14 Apr '11

Author: stepan Date: Thu Apr 14 21:52:04 2011 New Revision: 6492 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6492 Log: coding style cosmetics. Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Modified: trunk/payloads/libpayload/drivers/usb/ehci.c Modified: trunk/payloads/libpayload/drivers/usb/ehci.c ============================================================================== --- trunk/payloads/libpayload/drivers/usb/ehci.c Wed Apr 13 11:23:45 2011 (r6491) +++ trunk/payloads/libpayload/drivers/usb/ehci.c Thu Apr 14 21:52:04 2011 (r6492) @@ -31,7 +31,8 @@ #include "ehci.h" #include "ehci_private.h" -static void dump_td(u32 addr) { +static void dump_td(u32 addr) +{ qtd_t *td = phys_to_virt(addr); printf("td at phys(%x): active: %x, halted: %x, data_buf_err: %x\n babble: %x, xact_err: %x, missed_mframe: %x\n splitxstate: %x, perr: %x\n\n", addr, td->active, td->halted, td->data_buf_err, td->babble, td->xact_err, td->missed_mframe, td->splitxstate, td->perr); @@ -61,7 +62,8 @@ enum { EHCI_OUT=0, EHCI_IN=1, EHCI_SETUP=2 }; /* returns handled bytes */ -int fill_td(qtd_t *td, void* data, int datalen) { +int fill_td(qtd_t *td, void* data, int datalen) +{ u32 total_len = 0; u32 page_minus_1 = 0; @@ -99,7 +101,8 @@ } /* free up data structures */ -void free_qh_and_tds(ehci_qh_t *qh, qtd_t *cur) { +void free_qh_and_tds(ehci_qh_t *qh, qtd_t *cur) +{ qtd_t *next; while (cur) { next = (qtd_t*)phys_to_virt(cur->next_qtd & ~31); @@ -109,7 +112,8 @@ free(qh); } -int wait_for_tds(qtd_t *head) { +int wait_for_tds(qtd_t *head) +{ int result = 0; qtd_t *cur = head; while (1) {

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ASUS M4A79XTD EVO
by christopher west 14 Apr '11

14 Apr '11

Hello all, I've finally decided to bite the bullet and seriously look into putting coreboot on my Asus M4A79XTD EVO as I've getting bored of waiting for the BIOS to load. Buy my initial reckoning it looks as if everything is supported except the superio device. Could someone please confirm this as the specifications are as follows: Processor: AMD Phenom(tm) II X4 965 Processor, northbridge: RD790X Southbridge: SB750 SuperIO: IT8720F Rom Chip: Winbond W25x80 If I'm missing anything or you need more raw output please let me know. If my initial assumption is true then what could I do to support the superio as I'm not adverse to getting my hands dirty as I'm trying to get into embedded software and hardware design. Many thanks, Chris

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Super I/O: Winbond LPC Super I/O WPCN381U
by Jeremy Moles 13 Apr '11

13 Apr '11

Hello everyone. I have my hands on a piece of hardware here using the Super I/O device listed in the subject; that is: Winbond LPC Super I/O WPCN381U - My first question is, has anyone else encountered this device? - SVN trunk of superiotool detects this device as: Found NSC PC87382 (sid=0xf4, srid=0x04) at 0x2e ...and I know from the manufacturer that the device is actually the one mentioned previously. However, I know from the specsheet that the hardware is pin-compatible with the Winbond PC87381, which has a very similar name to the device it "thinks" it is. http://www.winbond-usa.com/products/winbond_products/pdfs/APC/WPCN381U_pba.… Does this mean that superiotool is actually detecting it properly? - Finally, the device I want to use waits for input via the serial port, but before this can be initiated the device must be powered on via the Super I/O module. According to the manufacturer, I do this by activating the GPIO03 pin. I know superiotool is a read-only tool, given I know these pieces of data, is there an easy way to ping this particular bit? - My first approach to enable this device was to write a small kernel module that would call gpio_request(3); however, this always returns -ENOSYS or -EINVAL. This clearly isn't the right approach. :) I realize this is probably a question for LKML proper, but I figured I'd ask here first and see what the Fates have in store. :)

3 10

[commit] r6491 - trunk/src/ec/lenovo/h8/acpi
by repository service 13 Apr '11

13 Apr '11

Author: svens Date: Wed Apr 13 11:23:45 2011 New Revision: 6491 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6491 Log: Lenovo H8 EC: add missing include for thermal.asl Signed-off-by: Sven Schnelle <svens(a)stackframe.org> Acked-by: Sven Schnelle <svens(a)stackframe.org> Modified: trunk/src/ec/lenovo/h8/acpi/ec.asl Modified: trunk/src/ec/lenovo/h8/acpi/ec.asl ============================================================================== --- trunk/src/ec/lenovo/h8/acpi/ec.asl Tue Apr 12 20:18:24 2011 (r6490) +++ trunk/src/ec/lenovo/h8/acpi/ec.asl Wed Apr 13 11:23:45 2011 (r6491) @@ -119,4 +119,5 @@ #include "sleepbutton.asl" #include "lid.asl" #include "beep.asl" +#include "thermal.asl" }

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coreboot April 2011