coreboot April 2011

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build service results for r6509
by repository service 17 Apr '11

17 Apr '11

Dear coreboot readers! This is the automatic build system of coreboot. The developer "svens" checked in revision 6509 to the coreboot repository. This caused the following changes: Change Log: PMH7: Add dock event control Signed-off-by: Sven Schnelle <svens(a)stackframe.org> Acked-by: Sven Schnelle <svens(a)stackframe.org> Build Log: Compilation of amd:inagua is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6509&device=inagua&vendor=… Compilation of amd:persimmon is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6509&device=persimmon&vend… Compilation of asrock:e350m1 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6509&device=e350m1&vendor=… If something broke during this checkin please be a pain in svens's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[commit] r6509 - trunk/src/ec/lenovo/pmh7
by repository service 17 Apr '11

17 Apr '11

Author: svens Date: Sun Apr 17 14:54:32 2011 New Revision: 6509 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6509 Log: PMH7: Add dock event control Signed-off-by: Sven Schnelle <svens(a)stackframe.org> Acked-by: Sven Schnelle <svens(a)stackframe.org> Modified: trunk/src/ec/lenovo/pmh7/chip.h trunk/src/ec/lenovo/pmh7/pmh7.c trunk/src/ec/lenovo/pmh7/pmh7.h Modified: trunk/src/ec/lenovo/pmh7/chip.h ============================================================================== --- trunk/src/ec/lenovo/pmh7/chip.h Sat Apr 16 02:13:17 2011 (r6508) +++ trunk/src/ec/lenovo/pmh7/chip.h Sun Apr 17 14:54:32 2011 (r6509) @@ -5,5 +5,6 @@ struct ec_lenovo_pmh7_config { int backlight_enable:1; + int dock_event_enable:1; }; #endif Modified: trunk/src/ec/lenovo/pmh7/pmh7.c ============================================================================== --- trunk/src/ec/lenovo/pmh7/pmh7.c Sat Apr 16 02:13:17 2011 (r6508) +++ trunk/src/ec/lenovo/pmh7/pmh7.c Sun Apr 17 14:54:32 2011 (r6509) @@ -33,6 +33,14 @@ pmh7_register_clear_bit(0x50, 5); } +void pmh7_dock_event_enable(int onoff) +{ + if (onoff) + pmh7_register_set_bit(0x60, 3); + else + pmh7_register_clear_bit(0x60, 3); + +} void pmh7_register_set_bit(int reg, int bit) { char val; @@ -78,6 +86,7 @@ resource->gran = 5; pmh7_backlight_enable(conf->backlight_enable); + pmh7_dock_event_enable(conf->dock_event_enable); } struct chip_operations ec_lenovo_pmh7_ops = { Modified: trunk/src/ec/lenovo/pmh7/pmh7.h ============================================================================== --- trunk/src/ec/lenovo/pmh7/pmh7.h Sat Apr 16 02:13:17 2011 (r6508) +++ trunk/src/ec/lenovo/pmh7/pmh7.h Sun Apr 17 14:54:32 2011 (r6509) @@ -32,4 +32,5 @@ void pmh7_register_write(int reg, int val); void pmh7_backlight_enable(int onoff); +void pmh7_dock_event_enable(int onoff); #endif

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Recovering a bricked Alic1c with arduino+LPC?
by Benjamin Henrion 17 Apr '11

17 Apr '11

Hi, Does anybody has any experience with reflashing an Alix 1C with LPC? I am trying with an arduino in 3.3v and some LPC code written by Mike Stirling: http://www.zoobab.com/arduino-as-a-bios-lpc-flasher http://www.zoobab.com/alix-1c Any idea? Best, -- Benjamin Henrion <bhenrion at ffii.org> FFII Brussels - +32-484-566109 - +32-2-4148403 "In July 2005, after several failed attempts to legalise software patents in Europe, the patent establishment changed its strategy. Instead of explicitly seeking to sanction the patentability of software, they are now seeking to create a central European patent court, which would establish and enforce patentability rules in their favor, without any possibility of correction by competing courts or democratically elected legislators."

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Fwd: support for Asus L1N64
by Julian Shulika 16 Apr '11

16 Apr '11

Hi,everyone. I have Asus L1N64WS/B with pair quad opteron Barcelona. I want to upgrade it for working with Shanghai core (an other owners too),but Asus engineers don't support this board more (last update was on 2009). It was one of a kind for AMD 4x4 platform based on pair of MCP55. (Tyan,Supermicro and Asus (other servers products) released new bioses for their MBs based on MCP55 for Shanghai and Istanbul cores) I wrote via email to support several times,no answer until,tried to chat with online helpers - no result.The base problem is update AGESA code. What is needed to do to add support for this MB in your project? I sent three files to subproject flashrom mailing list - dmidecode, flashrom verbose and lspci information, but any news yet. Have a nice day. http://www.asus.com/Motherboards/AMD_Socket_L1/L1N64SLI_WSB/

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Re: [coreboot] Gigabyte GA AMD E350N USB3 Board
by Niklas Cholmkvist 16 Apr '11

16 Apr '11

Hi Marek, did you have any luck in finding any other AMD USB3 motherboard? Are you mostly interested that it supports USB3? -- Niklas Cholmkvist Public GPG/PGP key block ID: 1024D/C09E670B Fingerprint: 8487 ECE3 8ED9 870B BB56 95E7 9AD2 946A C09E 670B Key download: https://sites.google.com/site/towardsfloss/main-page/NiklasCholmkvist.asc [Please, do not send my key to any keyserver]

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build service results for r6508
by repository service 16 Apr '11

16 Apr '11

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 6508 to the coreboot repository. This caused the following changes: Change Log: Allow libpayload to use an OXPCIe 952 card on systems without onboard serial port Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Acked-by: Marc Jones <marcj303(a)gmail.com> Build Log: Compilation of amd:inagua is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6508&device=inagua&vendor=… Compilation of amd:persimmon is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6508&device=persimmon&vend… Compilation of asrock:e350m1 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6508&device=e350m1&vendor=… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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build service results for r6507
by repository service 16 Apr '11

16 Apr '11

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 6507 to the coreboot repository. This caused the following changes: Change Log: bootblock updates: - allow CPU to define bootblock code, too. - drop unneeded __PRE_RAM__ define - move CBFS specific code out of bootblock_common.h into cbfs.h Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Acked-by: Marc Jones <marcj303(a)gmail.com> Build Log: Compilation of amd:inagua is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6507&device=inagua&vendor=… Compilation of amd:persimmon is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6507&device=persimmon&vend… Compilation of asrock:e350m1 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6507&device=e350m1&vendor=… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[PATCH] libpayload OXPCIe 952 support
by Stefan Reinauer 16 Apr '11

16 Apr '11

See patch.

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[commit] r6508 - in trunk/payloads/libpayload: drivers include
by repository service 16 Apr '11

16 Apr '11

Author: stepan Date: Sat Apr 16 02:13:17 2011 New Revision: 6508 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6508 Log: Allow libpayload to use an OXPCIe 952 card on systems without onboard serial port Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Acked-by: Marc Jones <marcj303(a)gmail.com> Modified: trunk/payloads/libpayload/drivers/serial.c trunk/payloads/libpayload/include/libpayload.h trunk/payloads/libpayload/include/sysinfo.h Modified: trunk/payloads/libpayload/drivers/serial.c ============================================================================== --- trunk/payloads/libpayload/drivers/serial.c Sat Apr 16 02:09:53 2011 (r6507) +++ trunk/payloads/libpayload/drivers/serial.c Sat Apr 16 02:13:17 2011 (r6508) @@ -32,9 +32,11 @@ #include <libpayload.h> #define IOBASE lib_sysinfo.ser_ioport +#define MEMBASE (phys_to_virt(lib_sysinfo.ser_base)) #define DIVISOR(x) (115200 / x) -void serial_hardware_init(int port, int speed, int word_bits, int parity, int stop_bits) +#ifdef CONFIG_SERIAL_SET_SPEED +static void serial_io_hardware_init(int port, int speed, int word_bits, int parity, int stop_bits) { unsigned char reg; @@ -58,6 +60,31 @@ outb(reg & ~0x80, port + 0x03); } +static void serial_mem_hardware_init(int port, int speed, int word_bits, int parity, int stop_bits) +{ + unsigned char reg; + + /* We will assume 8n1 for now. Does anyone use anything else these days? */ + + /* Disable interrupts. */ + writeb(0, MEMBASE + 0x01); + + /* Assert RTS and DTR. */ + writeb(3, MEMBASE + 0x04); + + /* Set the divisor latch. */ + reg = readb(MEMBASE + 0x03); + writeb(reg | 0x80, MEMBASE + 0x03); + + /* Write the divisor. */ + writeb(DIVISOR(speed) & 0xFF, MEMBASE); + writeb(DIVISOR(speed) >> 8 & 0xFF, MEMBASE + 1); + + /* Restore the previous value of the divisor. */ + writeb(reg & ~0x80, MEMBASE + 0x03); +} +#endif + static struct console_input_driver consin = { .havekey = serial_havechar, .getchar = serial_getchar @@ -69,31 +96,84 @@ void serial_init(void) { + pcidev_t oxpcie_dev; + if (pci_find_device(0x1415, 0xc158, &oxpcie_dev)) { + lib_sysinfo.ser_base = pci_read_resource(oxpcie_dev, 0) + 0x1000; + } else { + lib_sysinfo.ser_base = 0; + } + #ifdef CONFIG_SERIAL_SET_SPEED - serial_hardware_init(IOBASE, CONFIG_SERIAL_BAUD_RATE, 8, 0, 1); + if (lib_sysinfo.ser_base) + serial_mem_hardware_init(IOBASE, CONFIG_SERIAL_BAUD_RATE, 8, 0, 1); + else + serial_io_hardware_init(IOBASE, CONFIG_SERIAL_BAUD_RATE, 8, 0, 1); #endif console_add_input_driver(&consin); console_add_output_driver(&consout); } -void serial_putchar(unsigned int c) +static void serial_io_putchar(unsigned int c) { c &= 0xff; while ((inb(IOBASE + 0x05) & 0x20) == 0) ; outb(c, IOBASE); } -int serial_havechar(void) +static int serial_io_havechar(void) { return inb(IOBASE + 0x05) & 0x01; } -int serial_getchar(void) +static int serial_io_getchar(void) { - while (!serial_havechar()) ; + while (!serial_io_havechar()) ; return (int)inb(IOBASE); } +static void serial_mem_putchar(unsigned int c) +{ + c &= 0xff; + while ((readb(MEMBASE + 0x05) & 0x20) == 0) ; + writeb(c, MEMBASE); +} + +static int serial_mem_havechar(void) +{ + return readb(MEMBASE + 0x05) & 0x01; +} + +static int serial_mem_getchar(void) +{ + while (!serial_mem_havechar()) ; + return (int)readb(MEMBASE); +} + + +void serial_putchar(unsigned int c) +{ + if (lib_sysinfo.ser_base) + serial_mem_putchar(c); + else + serial_io_putchar(c); +} + +int serial_havechar(void) +{ + if (lib_sysinfo.ser_base) + return serial_mem_havechar(); + else + return serial_io_havechar(); +} + +int serial_getchar(void) +{ + if (lib_sysinfo.ser_base) + return serial_mem_getchar(); + else + return serial_io_getchar(); +} + /* These are thinly veiled vt100 functions used by curses */ #define VT100_CLEAR "\e[H\e[J" Modified: trunk/payloads/libpayload/include/libpayload.h ============================================================================== --- trunk/payloads/libpayload/include/libpayload.h Sat Apr 16 02:09:53 2011 (r6507) +++ trunk/payloads/libpayload/include/libpayload.h Sat Apr 16 02:13:17 2011 (r6508) @@ -153,7 +153,6 @@ * @{ */ void serial_init(void); -void serial_hardware_init(int port, int speed, int word_bits, int parity, int stop_bits); void serial_putchar(unsigned int c); int serial_havechar(void); int serial_getchar(void); Modified: trunk/payloads/libpayload/include/sysinfo.h ============================================================================== --- trunk/payloads/libpayload/include/sysinfo.h Sat Apr 16 02:09:53 2011 (r6507) +++ trunk/payloads/libpayload/include/sysinfo.h Sat Apr 16 02:13:17 2011 (r6508) @@ -36,6 +36,7 @@ struct sysinfo_t { unsigned int cpu_khz; unsigned short ser_ioport; + unsigned long ser_base; // for mmapped serial int n_memranges;

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[commit] r6507 - in trunk/src/arch/x86: include include/arch init
by repository service 16 Apr '11

16 Apr '11

Author: stepan Date: Sat Apr 16 02:09:53 2011 New Revision: 6507 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6507 Log: bootblock updates: - allow CPU to define bootblock code, too. - drop unneeded __PRE_RAM__ define - move CBFS specific code out of bootblock_common.h into cbfs.h Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Acked-by: Marc Jones <marcj303(a)gmail.com> Added: trunk/src/arch/x86/include/arch/cbfs.h Modified: trunk/src/arch/x86/include/bootblock_common.h trunk/src/arch/x86/init/bootblock_normal.c trunk/src/arch/x86/init/bootblock_simple.c Added: trunk/src/arch/x86/include/arch/cbfs.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/arch/x86/include/arch/cbfs.h Sat Apr 16 02:09:53 2011 (r6507) @@ -0,0 +1,26 @@ +static void *walkcbfs(char *target) +{ + void *entry; + asm volatile ( + "mov $1f, %%esp\n\t" + "jmp walkcbfs_asm\n\t" + "1:\n\t" : "=a" (entry) : "S" (target) : "ebx", "ecx", "edi", "esp"); + return entry; +} + +/* just enough to support findstage. copied because the original version doesn't easily pass through romcc */ +struct cbfs_stage_restricted { + unsigned long compression; + unsigned long entry; // this is really 64bit, but properly endianized +}; + +static inline unsigned long findstage(char* target) +{ + return ((struct cbfs_stage_restricted *)walkcbfs(target))->entry; +} + +static inline void call(unsigned long addr, unsigned long bist) +{ + asm volatile ("jmp *%0\n\t" : : "r" (addr), "a" (bist)); +} + Modified: trunk/src/arch/x86/include/bootblock_common.h ============================================================================== --- trunk/src/arch/x86/include/bootblock_common.h Fri Apr 15 11:01:42 2011 (r6506) +++ trunk/src/arch/x86/include/bootblock_common.h Sat Apr 16 02:09:53 2011 (r6507) @@ -1,4 +1,3 @@ -#define __PRE_RAM__ #if CONFIG_LOGICAL_CPUS && \ (defined(CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT) || defined(CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT)) #include <cpu/x86/lapic/boot_cpu.c> @@ -6,6 +5,11 @@ #define boot_cpu(x) 1 #endif +#ifdef CONFIG_BOOTBLOCK_CPU_INIT +#include CONFIG_BOOTBLOCK_CPU_INIT +#else +static void bootblock_cpu_init(void) { } +#endif #ifdef CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT #include CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT #else @@ -17,31 +21,7 @@ static void bootblock_southbridge_init(void) { } #endif -static void *walkcbfs(char *target) -{ - void *entry; - asm volatile ( - "mov $1f, %%esp\n\t" - "jmp walkcbfs_asm\n\t" - "1:\n\t" : "=a" (entry) : "S" (target) : "ebx", "ecx", "edi", "esp"); - return entry; -} - -/* just enough to support findstage. copied because the original version doesn't easily pass through romcc */ -struct cbfs_stage { - unsigned long compression; - unsigned long entry; // this is really 64bit, but properly endianized -}; - -static unsigned long findstage(char* target) -{ - return ((struct cbfs_stage*)walkcbfs(target))->entry; -} - -static void call(unsigned long addr, unsigned long bist) -{ - asm volatile ("jmp *%0\n\t" : : "r" (addr), "a" (bist)); -} +#include <arch/cbfs.h> #if CONFIG_USE_OPTION_TABLE #include <pc80/mc146818rtc.h> Modified: trunk/src/arch/x86/init/bootblock_normal.c ============================================================================== --- trunk/src/arch/x86/init/bootblock_normal.c Fri Apr 15 11:01:42 2011 (r6506) +++ trunk/src/arch/x86/init/bootblock_normal.c Sat Apr 16 02:09:53 2011 (r6507) @@ -6,6 +6,7 @@ if (boot_cpu()) { bootblock_northbridge_init(); bootblock_southbridge_init(); + bootblock_cpu_init(); } #if CONFIG_USE_OPTION_TABLE Modified: trunk/src/arch/x86/init/bootblock_simple.c ============================================================================== --- trunk/src/arch/x86/init/bootblock_simple.c Fri Apr 15 11:01:42 2011 (r6506) +++ trunk/src/arch/x86/init/bootblock_simple.c Sat Apr 16 02:09:53 2011 (r6507) @@ -5,6 +5,7 @@ if (boot_cpu()) { bootblock_northbridge_init(); bootblock_southbridge_init(); + bootblock_cpu_init(); } #if CONFIG_USE_OPTION_TABLE

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coreboot April 2011