coreboot April 2011

coreboot@coreboot.org

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build service results for r6499
by repository service 14 Apr '11

14 Apr '11

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 6499 to the coreboot repository. This caused the following changes: Change Log: earlymtrr.c: wipe some dead code, use names instead of numbers and some cosmetics. Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build Log: Compilation of amd:inagua is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6499&device=inagua&vendor=… Compilation of amd:persimmon is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6499&device=persimmon&vend… Compilation of asrock:e350m1 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6499&device=e350m1&vendor=… Compilation of digitallogic:adl855pc has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6499&device=adl855pc&vendo… Compilation of intel:eagleheights has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6499&device=eagleheights&v… Compilation of intel:mtarvon has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6499&device=mtarvon&vendor… Compilation of lanner:em8510 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6499&device=em8510&vendor=… Compilation of tyan:s2735 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6499&device=s2735&vendor=t… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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build service results for r6502
by repository service 14 Apr '11

14 Apr '11

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 6502 to the coreboot repository. This caused the following changes: Change Log: fix mainboards that were including earlymtrr.c without actually using it. Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build Log: Compilation of amd:inagua is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6502&device=inagua&vendor=… Compilation of amd:persimmon is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6502&device=persimmon&vend… Compilation of asrock:e350m1 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6502&device=e350m1&vendor=… Compilation of digitallogic:adl855pc has been fixed Compilation of intel:eagleheights has been fixed Compilation of intel:mtarvon has been fixed Compilation of lanner:em8510 has been fixed Compilation of tyan:s2735 has been fixed If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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build service results for r6501
by repository service 14 Apr '11

14 Apr '11

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 6501 to the coreboot repository. This caused the following changes: Change Log: drop half an uart8250 implementation from smiutil and use the common code for that instead. This also allows using non-uart8250 consoles for smi debugging. Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build Log: Compilation of amd:inagua is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6501&device=inagua&vendor=… Compilation of amd:persimmon is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6501&device=persimmon&vend… Compilation of asrock:e350m1 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6501&device=e350m1&vendor=… Compilation of digitallogic:adl855pc is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6501&device=adl855pc&vendo… Compilation of intel:eagleheights is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6501&device=eagleheights&v… Compilation of intel:mtarvon is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6501&device=mtarvon&vendor… Compilation of lanner:em8510 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6501&device=em8510&vendor=… Compilation of tyan:s2735 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6501&device=s2735&vendor=t… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[commit] r6502 - in trunk/src/mainboard: digitallogic/adl855pc intel/eagleheights intel/mtarvon lanner/em8510 tyan/s2735
by repository service 14 Apr '11

14 Apr '11

Author: stepan Date: Fri Apr 15 02:19:27 2011 New Revision: 6502 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6502 Log: fix mainboards that were including earlymtrr.c without actually using it. Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Modified: trunk/src/mainboard/digitallogic/adl855pc/romstage.c trunk/src/mainboard/intel/eagleheights/romstage.c trunk/src/mainboard/intel/mtarvon/romstage.c trunk/src/mainboard/lanner/em8510/romstage.c trunk/src/mainboard/tyan/s2735/romstage.c Modified: trunk/src/mainboard/digitallogic/adl855pc/romstage.c ============================================================================== --- trunk/src/mainboard/digitallogic/adl855pc/romstage.c Fri Apr 15 00:28:00 2011 (r6501) +++ trunk/src/mainboard/digitallogic/adl855pc/romstage.c Fri Apr 15 02:19:27 2011 (r6502) @@ -14,7 +14,6 @@ #include "northbridge/intel/i855/raminit.h" #include "northbridge/intel/i855/debug.c" #include "superio/winbond/w83627hf/early_serial.c" -#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include <spd.h> Modified: trunk/src/mainboard/intel/eagleheights/romstage.c ============================================================================== --- trunk/src/mainboard/intel/eagleheights/romstage.c Fri Apr 15 00:28:00 2011 (r6501) +++ trunk/src/mainboard/intel/eagleheights/romstage.c Fri Apr 15 02:19:27 2011 (r6502) @@ -68,7 +68,6 @@ } #include "northbridge/intel/i3100/raminit.h" -#include "cpu/x86/mtrr/earlymtrr.c" #include "northbridge/intel/i3100/memory_initialized.c" #include "northbridge/intel/i3100/raminit.c" #include "lib/generic_sdram.c" Modified: trunk/src/mainboard/intel/mtarvon/romstage.c ============================================================================== --- trunk/src/mainboard/intel/mtarvon/romstage.c Fri Apr 15 00:28:00 2011 (r6501) +++ trunk/src/mainboard/intel/mtarvon/romstage.c Fri Apr 15 02:19:27 2011 (r6502) @@ -31,7 +31,6 @@ #include "southbridge/intel/i3100/early_lpc.c" #include "northbridge/intel/i3100/raminit.h" #include "superio/intel/i3100/i3100.h" -#include "cpu/x86/mtrr/earlymtrr.c" #include "superio/intel/i3100/early_serial.c" #include "northbridge/intel/i3100/memory_initialized.c" #include "cpu/x86/bist.h" Modified: trunk/src/mainboard/lanner/em8510/romstage.c ============================================================================== --- trunk/src/mainboard/lanner/em8510/romstage.c Fri Apr 15 00:28:00 2011 (r6501) +++ trunk/src/mainboard/lanner/em8510/romstage.c Fri Apr 15 02:19:27 2011 (r6502) @@ -37,7 +37,6 @@ #include "northbridge/intel/i855/raminit.h" #include "northbridge/intel/i855/debug.c" #include "superio/winbond/w83627thg/early_serial.c" -#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1) Modified: trunk/src/mainboard/tyan/s2735/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2735/romstage.c Fri Apr 15 00:28:00 2011 (r6501) +++ trunk/src/mainboard/tyan/s2735/romstage.c Fri Apr 15 02:19:27 2011 (r6502) @@ -13,7 +13,6 @@ #include "northbridge/intel/e7501/raminit.h" #include "northbridge/intel/e7501/debug.c" #include "superio/winbond/w83627hf/early_serial.c" -#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)

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SuperI/O Access (Kernelspace)
by Jeremy Moles 14 Apr '11

14 Apr '11

Hey guys, me again. :) So, my device is working great now that I can access the GPIO pins via userspace (using iotools w/ Tom Sylla's help) and can power on the device. However, I'd like to be able to toggle the power on via a kernel driver as well, but I'm having trouble accessing the same memory range from kernelspace. For example: iotools io_read8 0xA00 Will return the state of the first 5 GPIO pins. I see that iotools calls iopl() to be able to access this location from userspace. When I try to do the same thing in the kernel: unsigned short b; unsigned short* ptr = (unsigned short*)(0xA00); if(access_ok(VERIFY_READ, ptr, 8)) { get_user(b, ptr); ...I immediately get a segfault. From what I've read and seen in other example code, I believe I'm doing this right. However, I may be making some wrong assumptions. I was just curious if anyone would be able to shed some light on the subject--perhaps I'm missing some virtual memory offset functions or similar...

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ASUS M488t-m
by Dave Houston 14 Apr '11

14 Apr '11

Afternoon all, I have an ASUS M488t-m which is very close to m4a785-m. I am currently making sure that I have a method to reflash should my build is bad ( which it most likely will be ) and I have been doing some digging regarding my Flash chip. The data sheet suggests that the current chip is 16Mb http://www.alldatasheet.com/datasheet-pdf/pdf/272751/EON/EN25F16.html. High resolution of mainboard: http://media.ldlc.com/ld/products/00/00/77/92/LD0000779214_2.jpg I have included all relevant output below. Is there any gotchas I should be aware of and is there a good flashing solution (I'm not adverse to buying a hardware solution ) ? Flashrom output > flashrom v0.9.1-r946 > No coreboot table found. > Found ITE Super I/O, id 8712 > Found chipset "AMD SB700/SB710/SB750", enabling flash write... OK. > This chipset supports the following protocols: LPC,FWH,SPI. > Calibrating delay loop... OK. > Found chip "Eon EN25F16" (2048 KB, SPI) at physical address 0xffe00000. > === > This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE > Please email a report to flashrom(a)flashrom.org if any of the above operations > work correctly for you with this flash part. Please include the flashrom > output with the additional -V option for all operations you tested (-V, -rV, > -wV, -EV), and mention which mainboard or programmer you tested. > Thanks for your help! > === > No operations were specified. SuperIOTool -d output > Found ITE IT8712F (id=0x8712, rev=0x8) at 0x2e > Register dump: > idx 20 21 22 23 24 2b > val 87 12 08 00 00 00 > def 87 12 08 00 00 00 > LDN 0x00 (Floppy) > idx 30 60 61 70 74 f0 f1 > val 00 03 f0 06 02 00 00 > def 00 03 f0 06 02 00 00 > LDN 0x01 (COM1) > idx 30 60 61 70 f0 f1 f2 f3 > val 00 00 00 00 00 50 00 7f > def 00 03 f8 04 00 50 00 7f > LDN 0x02 (COM2) > idx 30 60 61 70 f0 f1 f2 f3 > val 00 02 f8 03 00 50 00 7f > def 00 02 f8 03 00 50 00 7f > LDN 0x03 (Parallel port) > idx 30 60 61 62 63 70 74 f0 > val 00 00 00 00 00 00 04 00 > def 00 03 78 07 78 07 03 03 > LDN 0x04 (Environment controller) > idx 30 60 61 62 63 70 f0 f1 f2 f3 f4 f5 f6 > val 01 02 90 02 30 00 00 00 00 00 20 00 ff > def 00 02 90 02 30 09 00 00 00 00 00 NA NA > LDN 0x05 (Keyboard) > idx 30 60 61 62 63 70 71 f0 > val 01 00 60 00 64 01 02 04 > def 01 00 60 00 64 01 02 08 > LDN 0x06 (Mouse) > idx 30 70 71 f0 > val 01 0c 02 00 > def 00 0c 02 00 > LDN 0x07 (GPIO) > idx 25 26 27 28 29 2a 2c 60 61 62 63 64 65 70 71 72 73 74 b0 b1 b2 b3 b4 b5 b8 b9 ba bb bc bd c0 c1 c2 c3 c4 c8 c9 ca cb cc e0 e1 e2 e3 e4 f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 fa fb fc fd > val c1 a0 00 00 80 01 1f 00 00 03 00 00 00 00 01 00 38 00 00 00 00 00 00 00 00 00 00 00 00 00 c0 a0 00 00 00 40 a0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 1a 00 00 00 00 01 00 00 > def 01 00 00 40 00 00 00 00 00 00 00 00 00 00 00 00 c0 00 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 40 00 01 00 00 40 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 NA 00 > LDN 0x08 (MIDI port) > idx 30 60 61 70 f0 > val 00 03 00 0a 00 > def 00 03 00 0a 00 > LDN 0x09 (Game port) > idx 30 60 61 > val 00 02 01 > def 00 02 01 > LDN 0x0a (Consumer IR) > idx 30 60 61 70 f0 > val 00 03 10 0b 06 > def 00 03 10 0b 00 > $ lspci -tvnn > -[0000:00]-+-00.0 Advanced Micro Devices [AMD] RS780 Host Bridge Alternate [1022:9601] > +-01.0-[0000:01]--+-05.0 ATI Technologies Inc Device [1002:9715] > | \-05.1 ATI Technologies Inc RS880 Audio Device [Radeon HD 4200] [1002:970f] > +-0a.0-[0000:02]----00.0 Realtek Semiconductor Co., Ltd. RTL8111/8168B PCI Express Gigabit Ethernet controller [10ec:8168] > +-11.0 ATI Technologies Inc SB700/SB800 SATA Controller [AHCI mode] [1002:4391] > +-12.0 ATI Technologies Inc SB700/SB800 USB OHCI0 Controller [1002:4397] > +-12.1 ATI Technologies Inc SB700 USB OHCI1 Controller [1002:4398] > +-12.2 ATI Technologies Inc SB700/SB800 USB EHCI Controller [1002:4396] > +-13.0 ATI Technologies Inc SB700/SB800 USB OHCI0 Controller [1002:4397] > +-13.1 ATI Technologies Inc SB700 USB OHCI1 Controller [1002:4398] > +-13.2 ATI Technologies Inc SB700/SB800 USB EHCI Controller [1002:4396] > +-14.0 ATI Technologies Inc SBx00 SMBus Controller [1002:4385] > +-14.1 ATI Technologies Inc SB700/SB800 IDE Controller [1002:439c] > +-14.2 ATI Technologies Inc SBx00 Azalia (Intel HDA) [1002:4383] > +-14.3 ATI Technologies Inc SB700/SB800 LPC host controller [1002:439d] > +-14.4-[0000:03]-- > +-14.5 ATI Technologies Inc SB700/SB800 USB OHCI2 Controller [1002:4399] > +-18.0 Advanced Micro Devices [AMD] K10 [Opteron, Athlon64, Sempron] HyperTransport Configuration [1022:1200] > +-18.1 Advanced Micro Devices [AMD] K10 [Opteron, Athlon64, Sempron] Address Map [1022:1201] > +-18.2 Advanced Micro Devices [AMD] K10 [Opteron, Athlon64, Sempron] DRAM Controller [1022:1202] > +-18.3 Advanced Micro Devices [AMD] K10 [Opteron, Athlon64, Sempron] Miscellaneous Control [1022:1203] > \-18.4 Advanced Micro Devices [AMD] K10 [Opteron, Athlon64, Sempron] Link Control [1022:1204] > Many thanks Dave

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[commit] r6501 - in trunk: . src/cpu/x86/smm src/lib
by repository service 14 Apr '11

14 Apr '11

Author: stepan Date: Fri Apr 15 00:28:00 2011 New Revision: 6501 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6501 Log: drop half an uart8250 implementation from smiutil and use the common code for that instead. This also allows using non-uart8250 consoles for smi debugging. Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Modified: trunk/Makefile.inc trunk/src/cpu/x86/smm/smiutil.c trunk/src/lib/Makefile.inc trunk/src/lib/uart8250.c Modified: trunk/Makefile.inc ============================================================================== --- trunk/Makefile.inc Thu Apr 14 23:05:41 2011 (r6500) +++ trunk/Makefile.inc Fri Apr 15 00:28:00 2011 (r6501) @@ -52,6 +52,8 @@ romstage-c-ccopts:=-D__PRE_RAM__ romstage-S-ccopts:=-D__PRE_RAM__ +smm-c-ccopts:=-D__SMM__ +smm-S-ccopts:=-D__SMM__ ramstage-c-deps:=$$(OPTION_TABLE_H) romstage-c-deps:=$$(OPTION_TABLE_H) Modified: trunk/src/cpu/x86/smm/smiutil.c ============================================================================== --- trunk/src/cpu/x86/smm/smiutil.c Thu Apr 14 23:05:41 2011 (r6500) +++ trunk/src/cpu/x86/smm/smiutil.c Fri Apr 15 00:28:00 2011 (r6501) @@ -21,110 +21,52 @@ #include <arch/io.h> #include <arch/romcc_io.h> -#include <console/console.h> #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> -/* ********************* smi_util ************************* */ - -/* Data */ -#define UART_RBR 0x00 -#define UART_TBR 0x00 - -/* Control */ -#define UART_IER 0x01 -#define UART_IIR 0x02 -#define UART_FCR 0x02 -#define UART_LCR 0x03 -#define UART_MCR 0x04 -#define UART_DLL 0x00 -#define UART_DLM 0x01 - -/* Status */ -#define UART_LSR 0x05 -#define UART_MSR 0x06 -#define UART_SCR 0x07 - -#ifndef CONFIG_TTYS0_BASE -#define CONFIG_TTYS0_BASE 0x3f8 -#endif - -#ifndef CONFIG_TTYS0_BAUD -#define CONFIG_TTYS0_BAUD 115200 +#include <console/console.h> +#include <console/vtxprintf.h> +#if CONFIG_CONSOLE_SERIAL8250 +#include <uart8250.h> #endif - -#ifndef CONFIG_TTYS0_DIV -#define CONFIG_TTYS0_DIV (115200/CONFIG_TTYS0_BAUD) +#if CONFIG_USBDEBUG +#include <usbdebug.h> #endif - -/* Line Control Settings */ -#ifndef CONFIG_TTYS0_LCS -/* Set 8bit, 1 stop bit, no parity */ -#define CONFIG_TTYS0_LCS 0x3 +#if CONFIG_CONSOLE_NE2K +#include <console/ne2k.h> #endif -#define UART_LCS CONFIG_TTYS0_LCS - -static int uart_can_tx_byte(void) -{ - return inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x20; -} - -static void uart_wait_to_tx_byte(void) -{ - while(!uart_can_tx_byte()) - ; -} - -static void uart_wait_until_sent(void) -{ - while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40)) - ; -} - -static void uart_tx_byte(unsigned char data) -{ - uart_wait_to_tx_byte(); - outb(data, CONFIG_TTYS0_BASE + UART_TBR); - /* Make certain the data clears the fifos */ - uart_wait_until_sent(); -} - void console_tx_flush(void) { - uart_wait_to_tx_byte(); + // the tx_byte functions take care of the flush. + // if not, this should be implemented. } void console_tx_byte(unsigned char byte) { if (byte == '\n') - uart_tx_byte('\r'); - uart_tx_byte(byte); -} + console_tx_byte('\r'); -#if CONFIG_DEBUG_SMI -static void uart_init(void) -{ - /* disable interrupts */ - outb(0x0, CONFIG_TTYS0_BASE + UART_IER); - /* enable fifo's */ - outb(0x01, CONFIG_TTYS0_BASE + UART_FCR); - /* Set Baud Rate Divisor to 12 ==> 115200 Baud */ - outb(0x80 | UART_LCS, CONFIG_TTYS0_BASE + UART_LCR); - outb(CONFIG_TTYS0_DIV & 0xFF, CONFIG_TTYS0_BASE + UART_DLL); - outb((CONFIG_TTYS0_DIV >> 8) & 0xFF, CONFIG_TTYS0_BASE + UART_DLM); - outb(UART_LCS, CONFIG_TTYS0_BASE + UART_LCR); -} +#if CONFIG_CONSOLE_SERIAL8250 + uart8250_tx_byte(CONFIG_TTYS0_BASE, byte); +#endif +#if CONFIG_USBDEBUG + usbdebug_tx_byte(byte); #endif +#if CONFIG_CONSOLE_NE2K + ne2k_append_data(&byte, 1, CONFIG_CONSOLE_NE2K_IO_PORT); +#endif +} void console_init(void) { #if CONFIG_DEBUG_SMI console_loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL; +#if CONFIG_CONSOLE_SERIAL8250 uart_init(); +#endif #else console_loglevel = 1; #endif } -/* ********************* smi_util ************************* */ Modified: trunk/src/lib/Makefile.inc ============================================================================== --- trunk/src/lib/Makefile.inc Thu Apr 14 23:05:41 2011 (r6500) +++ trunk/src/lib/Makefile.inc Fri Apr 15 00:28:00 2011 (r6501) @@ -1,5 +1,18 @@ -ramstage-y += clog2.c -ramstage-y += uart8250.c + + +romstage-y += memset.c +romstage-y += memcpy.c +romstage-y += memcmp.c +romstage-y += cbfs.c +romstage-y += lzma.c +#romstage-y += lzmadecode.c +romstage-$(CONFIG_CACHE_AS_RAM) += ramtest.c +romstage-$(CONFIG_HAVE_ACPI_RESUME) += cbmem.c +romstage-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c +romstage-$(CONFIG_CONSOLE_NE2K) += ne2k.c +romstage-$(CONFIG_CONSOLE_NE2K) += compute_ip_checksum.c +romstage-$(CONFIG_USBDEBUG) += usbdebug.c + ramstage-y += memset.c ramstage-y += memcpy.c ramstage-y += memcmp.c @@ -13,27 +26,15 @@ ramstage-y += lzma.c #ramstage-y += lzmadecode.c ramstage-y += gcc.c +ramstage-y += clog2.c ramstage-y += cbmem.c - -romstage-$(CONFIG_HAVE_ACPI_RESUME) += cbmem.c -romstage-y += uart8250.c -romstage-y += memset.c -romstage-y += memcpy.c -romstage-y += memcmp.c -romstage-y += cbfs.c -romstage-y += lzma.c -romstage-$(CONFIG_CACHE_AS_RAM) += ramtest.c -#romstage-y += lzmadecode.c -romstage-$(CONFIG_CONSOLE_NE2K) += ne2k.c -romstage-$(CONFIG_CONSOLE_NE2K) += compute_ip_checksum.c - -driver-$(CONFIG_CONSOLE_NE2K) += ne2k.c - -romstage-$(CONFIG_USBDEBUG) += usbdebug.c +ramstage-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c ramstage-$(CONFIG_USBDEBUG) += usbdebug.c - ramstage-$(CONFIG_BOOTSPLASH) += jpeg.c +driver-$(CONFIG_CONSOLE_NE2K) += ne2k.c + smm-y += memcpy.c +smm-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c $(obj)/lib/version.ramstage.o : $(obj)/build.h Modified: trunk/src/lib/uart8250.c ============================================================================== --- trunk/src/lib/uart8250.c Thu Apr 14 23:05:41 2011 (r6500) +++ trunk/src/lib/uart8250.c Fri Apr 15 00:28:00 2011 (r6501) @@ -103,10 +103,10 @@ } #endif -#ifdef __PRE_RAM__ +#if defined(__PRE_RAM__) || defined(__SMM__) void uart_init(void) { -#if CONFIG_USE_OPTION_TABLE +#if CONFIG_USE_OPTION_TABLE && !defined(__SMM__) static const unsigned char divisor[] = { 1, 2, 3, 6, 12, 24, 48, 96 }; unsigned ttys0_div, ttys0_index; ttys0_index = read_option(CMOS_VSTART_baud_rate, CMOS_VLEN_baud_rate, 0);

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build service results for r6496
by repository service 14 Apr '11

14 Apr '11

2 1

[commit] r6497 - in trunk/src/arch/x86: . init
by repository service 14 Apr '11

14 Apr '11

Author: stepan Date: Thu Apr 14 22:30:21 2011 New Revision: 6497 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6497 Log: - drop remaining CONFIG_ROM_IMAGE_SIZE - re-enable .data section check for bootblock. - rename ldscript_fallback_cbfs.lb to bootblock.ld Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Added: trunk/src/arch/x86/init/bootblock.ld - copied, changed from r6491, trunk/src/arch/x86/init/ldscript_fallback_cbfs.lb Deleted: trunk/src/arch/x86/init/ldscript_fallback_cbfs.lb Modified: trunk/src/arch/x86/Makefile.inc Modified: trunk/src/arch/x86/Makefile.inc ============================================================================== --- trunk/src/arch/x86/Makefile.inc Thu Apr 14 22:21:49 2011 (r6496) +++ trunk/src/arch/x86/Makefile.inc Thu Apr 14 22:30:21 2011 (r6497) @@ -165,7 +165,7 @@ crt0s = $(src)/arch/x86/init/prologue.inc ldscripts = -ldscripts += $(src)/arch/x86/init/ldscript_fallback_cbfs.lb +ldscripts += $(src)/arch/x86/init/bootblock.ld ifeq ($(CONFIG_BIG_BOOTBLOCK),y) crt0s += $(src)/cpu/x86/16bit/entry16.inc ldscripts += $(src)/cpu/x86/16bit/entry16.lds Copied and modified: trunk/src/arch/x86/init/bootblock.ld (from r6491, trunk/src/arch/x86/init/ldscript_fallback_cbfs.lb) ============================================================================== --- trunk/src/arch/x86/init/ldscript_fallback_cbfs.lb Wed Apr 13 11:23:45 2011 (r6491, copy source) +++ trunk/src/arch/x86/init/bootblock.ld Thu Apr 14 22:30:21 2011 (r6497) @@ -29,7 +29,7 @@ /* cut _start into last 64k*/ _x = .; - . = (_x < (CONFIG_ROMBASE - 0x10000 + CONFIG_ROM_IMAGE_SIZE)) ? (CONFIG_ROMBASE - 0x10000 + CONFIG_ROM_IMAGE_SIZE) : _x; + . = (_x < CONFIG_ROMBASE) ? (CONFIG_ROMBASE) : _x; /* This section might be better named .setup */ .rom . : { @@ -49,6 +49,5 @@ *(.comment.*) *(.note.*) } -/* _bogus = ASSERT((SIZEOF(.bss) + SIZEOF(.data)) == 0, "Do not use global variables in romstage"); */ - _bogus = ASSERT((SIZEOF(.bss)) == 0, "Do not use global variables in romstage"); + _bogus = ASSERT((SIZEOF(.bss) + SIZEOF(.data)) == 0, "Do not use global variables in romstage"); }

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[commit] r6500 - trunk/src/arch/x86/boot
by repository service 14 Apr '11

14 Apr '11

Author: stepan Date: Thu Apr 14 23:05:41 2011 New Revision: 6500 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6500 Log: fix coreboot compilation without serial console enabled. Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Modified: trunk/src/arch/x86/boot/coreboot_table.c Modified: trunk/src/arch/x86/boot/coreboot_table.c ============================================================================== --- trunk/src/arch/x86/boot/coreboot_table.c Thu Apr 14 22:39:49 2011 (r6499) +++ trunk/src/arch/x86/boot/coreboot_table.c Thu Apr 14 23:05:41 2011 (r6500) @@ -116,7 +116,7 @@ serial->baud = CONFIG_TTYS0_BAUD; return serial; #else - return header; + return NULL; #endif }

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coreboot April 2011