SB850 SERR# routing (almost off-topic) - coreboot

12 Apr 2011


      Hi,
My AM3/870/sb850 board doesn't seem to route SERR# on the conventional
PCI bus to a NMI.  I've adjusted the registers at port 61h and 70h,
and ensured that the Core 0 LAPIC LINT1 is not masked and is routed
to NMI. I've also enabled SERR handling in various parts of the chipset.
I managed to get this to work on a 785/sb7xx board after adjusting port
C14h, but that's not where I need to trigger a NMI.
The sb850 board does not appear to have a decoded register at port C14h
I don't know if this is because it's been hidden, or because it's
moved somewhere else or where it may have moved to.
Could anyone tell how I could make this work on the SB850 board?
Jonathan Kollasch