coreboot March 2011

coreboot@coreboot.org

71 participants
210 discussions

[commit] r6433 - trunk/util/superiotool
by repository service 06 Mar '11

06 Mar '11

Author: hailfinger Date: Sun Mar 6 18:58:31 2011 New Revision: 6433 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6433 Log: Add support for the NSC PC87364 Super I/O. superiotool -deV output: http://www.flashrom.org/pipermail/flashrom/2011-March/005878.html Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Acked-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Modified: trunk/util/superiotool/nsc.c Modified: trunk/util/superiotool/nsc.c ============================================================================== --- trunk/util/superiotool/nsc.c Fri Mar 4 21:01:15 2011 (r6432) +++ trunk/util/superiotool/nsc.c Sun Mar 6 18:58:31 2011 (r6433) @@ -242,6 +242,48 @@ {0x00,0x00,0x00,0x00,0x00,0x04,0x04,0x00,EOT}}, {EOT}}}, {0xe4, "PC87364", { + {NOLDN, NULL, + {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28,0x2a, + 0x2b,0x2c,0x2d,0x2e,EOT}, + {0xe4,0x11,0x00,0x03,0x00,0x00,0x00,NANA,0x00,MISC, + 0x00,0x00,NANA,RSVD,EOT}}, + {0x0, "Floppy", + {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,0xf1,EOT}, + {0x00,0x03,0xf2,0x06,0x03,0x02,0x04,0x24,0x00,EOT}}, + {0x1, "Parallel port", + {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT}, + {0x00,0x02,0x78,0x07,0x02,0x04,0x04,0xf2,EOT}}, + {0x2, "COM2", + {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT}, + {0x00,0x02,0xf8,0x03,0x03,0x04,0x04,0x02,EOT}}, + {0x3, "COM1", + {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT}, + {0x00,0x03,0xf8,0x04,0x03,0x04,0x04,0x02,EOT}}, + {0x4, "System wake-up control (SWC)", + {0x30,0x60,0x61,0x70,0x71,0x74,0x75,EOT}, + {0x00,0x00,0x00,0x00,0x03,0x04,0x04,EOT}}, + {0x5, "Mouse", + {0x30,0x70,0x71,0x74,0x75,EOT}, + {0x00,0x0c,0x02,0x04,0x04,EOT}}, + {0x6, "Keyboard", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,0x74,0x75,0xf0, + EOT}, + {0x01,0x00,0x60,0x00,0x64,0x01,0x02,0x04,0x04,0x40, + EOT}}, + {0x7, "GPIO", + {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,0xf1,0xf2, + EOT}, + {0x00,0x00,0x00,0x00,0x03,0x04,0x04,0x00,0x00,0x00, + EOT}}, + {0x8, "ACCESS.bus (ACB)", + {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT}, + {0x00,0x00,0x00,0x00,0x03,0x04,0x04,0x00,EOT}}, + {0x9, "Fan speed control and monitor (FSCM)", + {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,0xf1,EOT}, + {0x00,0x00,0x00,0x00,0x03,0x04,0x04,0x00,0x00,EOT}}, + {0xa, "Watchdog timer", + {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT}, + {0x00,0x00,0x00,0x00,0x03,0x04,0x04,0x02,EOT}}, {EOT}}}, {0xe5, "PC87365", { /* SRID[7..0] == chip revision */ {EOT}}},

1 0

[PATCH] X60: add thermal zone 0
by Sven Schnelle 06 Mar '11

06 Mar '11

Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/mainboard/lenovo/x60/acpi/ec.asl | 4 +++- src/mainboard/lenovo/x60/acpi/thermal.asl | 26 ++++++++++++++++++++++++++ 2 files changed, 29 insertions(+), 1 deletions(-) diff --git a/src/mainboard/lenovo/x60/acpi/ec.asl b/src/mainboard/lenovo/x60/acpi/ec.asl index 775fa58..f18b665 100644 --- a/src/mainboard/lenovo/x60/acpi/ec.asl +++ b/src/mainboard/lenovo/x60/acpi/ec.asl @@ -36,7 +36,9 @@ Device(EC) LEDS, 8, /* LED state */ Offset (0x3B), , 1, - KBLT, 1, /* Keyboard Light */ + KBLT, 1, /* Keyboard Light */ + Offset (0x78), + TMP0, 8, /* Thermal Zone 0 temperature */ Offset (0x81), PAGE, 8 /* Information Page Selector */ } diff --git a/src/mainboard/lenovo/x60/acpi/thermal.asl b/src/mainboard/lenovo/x60/acpi/thermal.asl index e69de29..b7256ce 100644 --- a/src/mainboard/lenovo/x60/acpi/thermal.asl +++ b/src/mainboard/lenovo/x60/acpi/thermal.asl @@ -0,0 +1,26 @@ +Scope(\_TZ) +{ + Method(C2K, 1, NotSerialized) + { + Multiply(Arg0, 10, Local0) + Add (Local0, 2732, Local0) + if (LLessEqual(Local0, 2732)) { + Return (3000) + } + + if (LGreater(Local0, 4012)) { + Return (3000) + } + Return (Local0) + } + + ThermalZone(THM0) + { + Method(_CRT, 0, NotSerialized) { + Return (C2K(127)) + } + Method(_TMP) { + Return (C2K(\_SB.PCI0.LPCB.EC.TMP0)) + } + } +} -- 1.7.4.1

1 0

ACPI breakage/questions and ramstage code question
by Keith Hui 06 Mar '11

06 Mar '11

--- First, Mysterious breakage on experimental i82371eb ACPI stuff Rudolf, Idwer, and anyone that tried doing ACPI for the ASUS P2B series of boards: I'm seeing mysterious compiler breakge after updating my local copy to r6424. I copied that from P2B to P2B-LS and both break. Make log says: CC southbridge/intel/i82371eb/fadt.driver.o src/southbridge/intel/i82371eb/fadt.c:35:35: error: expected ‘)’ before ‘*’ token make: *** [build/southbridge/intel/i82371eb/fadt.driver.o] Error 1 Which points to this in the file: /** * Create the Fixed ACPI Description Tables (FADT) for any board with this SB. * Reference: ACPIspec40a, 5.2.9, page 118 */ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void * dsdt) { acpi_header_t *header = &(fadt->header); device_t dev; [ Rest of function goes here] } Are any of you guys having the same problem? I ran abuild on a random target with ACPI and didn't have this problem. I will try to find out why but hoping that someone will beat me to an explanation. --- In code that create ACPI tables like the above, have anyone tried declaring the constant part of the tables statically, memcpy() it to a working buffer at runtime, fill in the dynamic parts, then pass it on? Currently all entries in these ACPI tables are written at runtime, producing a lot of code that may not be needed. --- I am finding these getting compiled into my ramstage: ... CC devices/device_util.ramstage.o CC devices/pci_device.ramstage.o > CC devices/pcix_device.ramstage.o > CC devices/pciexp_device.ramstage.o CC devices/agp_device.ramstage.o > CC devices/cardbus_device.ramstage.o CC devices/pnp_device.ramstage.o CC devices/pci_ops.ramstage.o CC devices/smbus_ops.ramstage.o CC devices/pci_rom.ramstage.o ... Why is code for every bus types getting compiled in anyway? The compile shown here is for ASUS P2B-LS, which has no PCIX, no PCI express (board predates this), and no cardbus. Can I attempt to leave these out and hopefully save some time and bytes?

3 2

not sure
by donnie hylton 06 Mar '11

06 Mar '11

i am not sure if you have received these emails or not because my email service never sent a copy to my sent folder so i am sending them again. sorry to bother you. 1st email i only have a 32 bit edition of windows installed and i know nothing about programming so i am not able to use the linux tools listed. so i have sent the hardware specs in the attachments that i created using some programs for windows i found. my laptop is a toshiba l35 s2151. in the hardware specs and the bios info the number of total memory slots says 4 even though there are only 2. i have taken the laptop apart more than once and have only seen 2 ram slots. here is a link to the processor. http://ark.intel.com/Product.aspx?id=27149&processor=420&spec-codes=SL8VZ in the hardware spec attachment that i sent it says that the package socket is 479 mPGA but on the intel webpage under Ordering / sSpecs / Steppings the processor is listed as Intel® Celeron® M Processor 420 (1M Cache, 1.60 GHz, 533 MHz FSB) uFCPGA, Tray and having a socket type of PPGA478. that is 3 different listings PPGA478,479 mPGA,uFCPGA from 2 different sources intel and speccy a program from piriform. 2nd email this is a reading from speedfan when you load the program. Linked ISA BUS at $0290 Scanning ISA BUS at $0290... SuperIO Chip=NS PC87591 Found ST9160310AS on AdvSMART and here is the device instance id for the ati smbus PCI\VEN_1002&DEV_4372&SUBSYS_FF311179&REV_82\3&13C0B0C5&0&A0 i found this within the details listed under the properties for the ati smbus within the windows xp device manager. __________________________________________ BreakThru.com - Pure email. Zero spam. http://friendfinder.com/go/f47930 - Dating Personals and Social Networking http://quizhappy.com/go/f301 - Ph.D certified tests and quizzes http://dine.com/go/f5554 - Restaurant Reviews in your area

1 0

email to flashrom
by donnie hylton 06 Mar '11

06 Mar '11

should i send the same info that i sent to you to the flashrom mailing list? __________________________________________ BreakThru.com - Pure email. Zero spam. http://friendfinder.com/go/f47930 - Dating Personals and Social Networking http://quizhappy.com/go/f301 - Ph.D certified tests and quizzes http://dine.com/go/f5554 - Restaurant Reviews in your area

1 0

Issue mainboard asus a8n-e
by ors 06 Mar '11

06 Mar '11

Author: raby71 Date: Mon Feb 28 22:00 2011 last Revision: 6380 hi all I try to work my board (asus a8n-e) with coreboot. I compiled coreboot with a debian 5.07 installation. After flashing the bios-chip with flashrom, the system starts, also the monitor until to boot-promt (or payload terminal) but is not possible to type anything with keyboard (usb or ps/2) to monitor, simply: i'm not able to take further actions. I compiled coreboot with payloads filo grub2 and seabios, but i have in all my tries the same effect. Can everyone help me? I have also the coreboot.log here. I got them with a serial-null-modem cable. Terminal ready coreboot-4.0-r- Sat Feb 26 16:25:25 CST 2011 starting... Enabling routing table for node 00 done. Enabling UP settings Disabling read/write/fill probes for UP... done. coherent_ht_finalize done core0 started: started ap apicid: SBLink=00 NC node|link=00 entering ht_optimize_link pos=0x8a, unfiltered freq_cap=0x8075 pos=0x8a, filtered freq_cap=0x35 pos=0x52, unfiltered freq_cap=0x807f pos=0x52, filtered freq_cap=0x7f freq_cap1=0x35, freq_cap2=0x7f dev1 old_freq=0x5, freq=0x5, needs_reset=0x0 dev2 old_freq=0x5, freq=0x5, needs_reset=0x0 width_cap1=0x11, width_cap2=0x11 dev1 input ln_width1=0x4, ln_width2=0x4 dev1 input width=0x1 dev1 output ln_width1=0x4, ln_width2=0x4 dev1 input|output width=0x11 old dev1 input|output width=0x11 dev2 input|output width=0x11 old dev2 input|output width=0x11 SMBus controller enabled Ram1.00 setting up CPU00 northbridge registers done. Ram2.00 Enabling dual channel memory Unbuffered 166Mhz Interleaved RAM end at 0x00100000 kB Lower RAM end at 0x00100000 kB Ram3 Initializing memory: done Handling memory hole at 0x00300000 (default) Ram4 v_esp=000cfdb8 testx = 5a5a5a5a Copying data from cache to RAM -- switching to use RAM as stack... Done testx = 5a5a5a5a Disabling cache as ram now Clearing initial memory region: Done Loading image. Check CBFS header at fffffcfe magic is 4f524243 Found CBFS header at fffffcfe Check cmos_layout.bin CBFS: follow chain: fff80000 + 28 + 6f3 + align -> fff80740 Check fallback/romstage CBFS: follow chain: fff80740 + 38 + 7eca + align -> fff88680 Check fallback/coreboot_ram Stage: loading fallback/coreboot_ram @ 0x100000 (245760 bytes), entry @ 0x100000 Stage: done loading. Jumping to image. coreboot-4.0-r- Sat Feb 26 16:25:25 CST 2011 booting... Enumerating buses... Show all devs...Before device enumeration. Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:01.0: enabled 1 PNP: 002e.0: enabled 1 PNP: 002e.1: enabled 1 PNP: 002e.2: enabled 0 PNP: 002e.3: enabled 1 PNP: 002e.4: enabled 1 PNP: 002e.5: enabled 1 PNP: 002e.6: enabled 1 PNP: 002e.7: enabled 1 PNP: 002e.8: enabled 1 PNP: 002e.9: enabled 1 PNP: 002e.a: enabled 0 PCI: 00:01.1: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:02.1: enabled 1 PCI: 00:04.0: enabled 1 PCI: 00:04.1: enabled 0 PCI: 00:06.0: enabled 1 PCI: 00:07.0: enabled 1 PCI: 00:08.0: enabled 1 PCI: 00:09.0: enabled 1 PCI: 00:0a.0: enabled 1 PCI: 00:0b.0: enabled 1 PCI: 00:0c.0: enabled 1 PCI: 00:0d.0: enabled 1 PCI: 00:0e.0: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 Compare with tree... Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:01.0: enabled 1 PNP: 002e.0: enabled 1 PNP: 002e.1: enabled 1 PNP: 002e.2: enabled 0 PNP: 002e.3: enabled 1 PNP: 002e.4: enabled 1 PNP: 002e.5: enabled 1 PNP: 002e.6: enabled 1 PNP: 002e.7: enabled 1 PNP: 002e.8: enabled 1 PNP: 002e.9: enabled 1 PNP: 002e.a: enabled 0 PCI: 00:01.1: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:02.1: enabled 1 PCI: 00:04.0: enabled 1 PCI: 00:04.1: enabled 0 PCI: 00:06.0: enabled 1 PCI: 00:07.0: enabled 1 PCI: 00:08.0: enabled 1 PCI: 00:09.0: enabled 1 PCI: 00:0a.0: enabled 1 PCI: 00:0b.0: enabled 1 PCI: 00:0c.0: enabled 1 PCI: 00:0d.0: enabled 1 PCI: 00:0e.0: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 scan_static_bus for Root Device APIC_CLUSTER: 0 enabled PCI_DOMAIN: 0000 enabled APIC_CLUSTER: 0 scanning... PCI: 00:18.3 siblings=0 Found Rev E or Rev F later single core CPU: APIC: 00 enabled PCI_DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 PCI: 00:18.0 [1022/1100] bus ops PCI: 00:18.0 [1022/1100] enabled PCI: 00:18.1 [1022/1101] enabled PCI: 00:18.2 [1022/1102] enabled PCI: 00:18.3 [1022/1103] ops PCI: 00:18.3 [1022/1103] enabled PCI: Using configuration type 1 PCI: 00:00.0 [10de/005e] ops PCI: 00:00.0 [10de/005e] enabled Capability: type 0x08 @ 0x44 flags: 0x01e0 PCI: 00:00.0 count: 000f static_count: 000f PCI: 00:00.0 [10de/005e] enabled next_unitid: 000f PCI: pci_scan_bus for bus 00 PCI: 00:00.0 [10de/005e] enabled PCI: 00:01.0 [10de/0050] bus ops PCI: 00:01.0 [10de/0050] enabled PCI: 00:01.1 [10de/0052] bus ops PCI: 00:01.1 [10de/0052] enabled PCI: 00:02.0 [10de/005a] ops PCI: 00:02.0 [10de/005a] enabled PCI: 00:02.1 [10de/005b] ops PCI: 00:02.1 [10de/005b] enabled PCI: 00:04.0 [10de/0059] ops PCI: 00:04.0 [10de/0059] enabled PCI: 00:04.1 [10de/0058] ops PCI: 00:04.1 [10de/0058] disabled PCI: 00:06.0 [10de/0053] ops PCI: 00:06.0 [10de/0053] enabled PCI: 00:07.0 [10de/0054] ops PCI: 00:07.0 [10de/0054] enabled PCI: 00:08.0 [10de/0055] ops PCI: 00:08.0 [10de/0055] enabled PCI: 00:09.0 [10de/005c] bus ops PCI: 00:09.0 [10de/005c] enabled PCI: 00:0a.0 [10de/0057] ops PCI: 00:0a.0 [10de/0057] enabled PCI: 00:0b.0 [10de/005d] bus ops PCI: 00:0b.0 [10de/005d] enabled PCI: 00:0c.0 [10de/005d] bus ops PCI: 00:0c.0 [10de/005d] enabled PCI: 00:0d.0 [10de/005d] bus ops PCI: 00:0d.0 [10de/005d] enabled PCI: 00:0e.0 [10de/005d] bus ops PCI: 00:0e.0 [10de/005d] enabled scan_static_bus for PCI: 00:01.0 PNP: 002e.0 enabled PNP: 002e.1 enabled PNP: 002e.2 disabled PNP: 002e.3 enabled PNP: 002e.4 enabled PNP: 002e.5 enabled PNP: 002e.6 enabled PNP: 002e.7 enabled PNP: 002e.8 enabled PNP: 002e.9 enabled PNP: 002e.a disabled scan_static_bus for PCI: 00:01.0 done scan_static_bus for PCI: 00:01.1 scan_static_bus for PCI: 00:01.1 done do_pci_scan_bridge for PCI: 00:09.0 PCI: pci_scan_bus for bus 01 PCI: 01:06.0 [10de/002c] enabled PCI: pci_scan_bus returning with max=001 do_pci_scan_bridge returns max 1 do_pci_scan_bridge for PCI: 00:0b.0 PCI: pci_scan_bus for bus 02 PCI: pci_scan_bus returning with max=002 do_pci_scan_bridge returns max 2 do_pci_scan_bridge for PCI: 00:0c.0 PCI: pci_scan_bus for bus 03 PCI: pci_scan_bus returning with max=003 do_pci_scan_bridge returns max 3 do_pci_scan_bridge for PCI: 00:0d.0 PCI: pci_scan_bus for bus 04 PCI: pci_scan_bus returning with max=004 do_pci_scan_bridge returns max 4 do_pci_scan_bridge for PCI: 00:0e.0 PCI: pci_scan_bus for bus 05 PCI: pci_scan_bus returning with max=005 do_pci_scan_bridge returns max 5 PCI: pci_scan_bus returning with max=005 PCI: pci_scan_bus returning with max=005 PCI_DOMAIN: 0000 passpw: enabled scan_static_bus for Root Device done done Setting up VGA for PCI: 01:06.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:09.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:18.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 APIC_CLUSTER: 0 read_resources bus 0 link: 0 APIC: 00 missing read_resources APIC_CLUSTER: 0 read_resources bus 0 link: 0 done PCI_DOMAIN: 0000 read_resources bus 0 link: 0 VGA: PCI: 00:18.0 (aka node 0) link 0 has VGA device PCI: 00:18.0 read_resources bus 0 link: 0 PCI: 00:01.0 read_resources bus 0 link: 0 PCI: 00:01.0 read_resources bus 0 link: 0 done PCI: 00:09.0 read_resources bus 1 link: 0 PCI: 00:09.0 read_resources bus 1 link: 0 done PCI: 00:0b.0 read_resources bus 2 link: 0 PCI: 00:0b.0 read_resources bus 2 link: 0 done PCI: 00:0c.0 read_resources bus 3 link: 0 PCI: 00:0c.0 read_resources bus 3 link: 0 done PCI: 00:0d.0 read_resources bus 4 link: 0 PCI: 00:0d.0 read_resources bus 4 link: 0 done PCI: 00:0e.0 read_resources bus 5 link: 0 PCI: 00:0e.0 read_resources bus 5 link: 0 done PCI: 00:18.0 read_resources bus 0 link: 0 done PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 APIC_CLUSTER: 0 APIC_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 PCI_DOMAIN: 0000 child on link 0 PCI: 00:18.0 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 PCI: 00:18.0 child on link 0 PCI: 00:00.0 PCI: 00:18.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80100 index 0 PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 81200 index 2 PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80200 index 1 PCI: 00:18.0 resource base a0000 size 20000 align 0 gran 0 limit ffffffff flags c0000200 index 4 PCI: 00:00.0 PCI: 00:01.0 child on link 0 PNP: 002e.0 PCI: 00:01.0 resource base 0 size 80 align 7 gran 7 limit ffff flags 100 index 10 PCI: 00:01.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14 PCI: 00:01.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 60 PCI: 00:01.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 64 PCI: 00:01.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 68 PCI: 00:01.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 PCI: 00:01.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100 PCI: 00:01.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 PNP: 002e.0 PNP: 002e.0 resource base 3f0 size 8 align 3 gran 3 limit fff flags c0000100 index 60 PNP: 002e.0 resource base 6 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.0 resource base 2 size 1 align 0 gran 0 limit 0 flags c0000800 index 74 PNP: 002e.1 PNP: 002e.1 resource base 3f8 size 8 align 3 gran 3 limit fff flags c0000100 index 60 PNP: 002e.1 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.2 PNP: 002e.2 resource base 2f8 size 8 align 3 gran 3 limit fff flags c0000100 index 60 PNP: 002e.2 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.3 PNP: 002e.3 resource base 378 size 4 align 2 gran 2 limit fff flags c0000100 index 60 PNP: 002e.3 resource base 7 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.3 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000800 index 74 PNP: 002e.4 PNP: 002e.4 resource base 290 size 8 align 3 gran 3 limit fff flags c0000100 index 60 PNP: 002e.4 resource base 0 size 8 align 3 gran 3 limit fff flags c0000100 index 62 PNP: 002e.4 resource base 0 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.5 PNP: 002e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 60 PNP: 002e.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 62 PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.5 resource base 2 size 0 align 0 gran 0 limit 0 flags c0000400 index 71 PNP: 002e.6 PNP: 002e.6 resource base c size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.6 resource base 2 size 0 align 0 gran 0 limit 0 flags c0000400 index 71 PNP: 002e.7 PNP: 002e.7 resource base 800 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 60 PNP: 002e.7 resource base 0 size 0 align 0 gran 0 limit 0 flags c0000100 index 25 PNP: 002e.7 resource base 2540 size 0 align 0 gran 0 limit 0 flags c0000100 index 27 PNP: 002e.7 resource base 2100 size 0 align 0 gran 0 limit 0 flags c0000100 index b2 PNP: 002e.7 resource base 100 size 0 align 0 gran 0 limit 0 flags c0000100 index ba PNP: 002e.7 resource base 0 size 0 align 0 gran 0 limit 0 flags c0000100 index c0 PNP: 002e.7 resource base 2540 size 0 align 0 gran 0 limit 0 flags c0000100 index c2 PNP: 002e.7 resource base 0 size 0 align 0 gran 0 limit 0 flags c0000100 index c8 PNP: 002e.7 resource base 500 size 0 align 0 gran 0 limit 0 flags c0000100 index ca PNP: 002e.7 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 62 PNP: 002e.7 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 64 PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.8 PNP: 002e.8 resource base 300 size 8 align 3 gran 3 limit fff flags c0000100 index 60 PNP: 002e.8 resource base a size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.9 PNP: 002e.9 resource base 201 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 60 PNP: 002e.a PNP: 002e.a resource base 310 size 8 align 3 gran 3 limit fff flags c0000100 index 60 PNP: 002e.a resource base b size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PCI: 00:01.1 PCI: 00:01.1 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 10 PCI: 00:01.1 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20 PCI: 00:01.1 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 24 PCI: 00:02.0 PCI: 00:02.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:02.1 PCI: 00:02.1 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10 PCI: 00:04.0 PCI: 00:04.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10 PCI: 00:04.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 14 PCI: 00:04.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 18 PCI: 00:04.1 PCI: 00:06.0 PCI: 00:06.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 PCI: 00:07.0 PCI: 00:07.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 PCI: 00:07.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 PCI: 00:07.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 PCI: 00:07.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c PCI: 00:07.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 PCI: 00:07.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 24 PCI: 00:08.0 PCI: 00:08.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 PCI: 00:08.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 PCI: 00:08.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 PCI: 00:08.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c PCI: 00:08.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 PCI: 00:08.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 24 PCI: 00:09.0 child on link 0 PCI: 01:06.0 PCI: 00:09.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c PCI: 00:09.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 81202 index 24 PCI: 00:09.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 01:06.0 PCI: 01:06.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffff flags 200 index 10 PCI: 01:06.0 resource base 0 size 2000000 align 25 gran 25 limit ffffffff flags 1200 index 14 PCI: 01:06.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 2200 index 30 PCI: 00:0a.0 PCI: 00:0a.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:0a.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 14 PCI: 00:0b.0 PCI: 00:0b.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c PCI: 00:0b.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:0b.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 00:0c.0 PCI: 00:0c.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c PCI: 00:0c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:0c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 00:0d.0 PCI: 00:0d.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c PCI: 00:0d.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:0d.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 00:0e.0 PCI: 00:0e.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c PCI: 00:0e.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:0e.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 00:18.1 PCI: 00:18.2 PCI: 00:18.3 PCI: 00:18.3 resource base 0 size 4000000 align 26 gran 26 limit ffffffff flags 200 index 94 PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff PCI: 00:18.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 00:09.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 00:09.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done PCI: 00:0b.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff PCI: 00:0b.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done PCI: 00:0c.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff PCI: 00:0c.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done PCI: 00:0d.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff PCI: 00:0d.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done PCI: 00:0e.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff PCI: 00:0e.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done PCI: 00:01.0 60 * [0x0 - 0xff] io PCI: 00:01.0 64 * [0x400 - 0x4ff] io PCI: 00:01.0 68 * [0x800 - 0x8ff] io PCI: 00:04.0 10 * [0xc00 - 0xcff] io PCI: 00:04.0 14 * [0x1000 - 0x10ff] io PCI: 00:01.0 10 * [0x1400 - 0x147f] io PCI: 00:01.1 20 * [0x1480 - 0x14bf] io PCI: 00:01.1 24 * [0x14c0 - 0x14ff] io PCI: 00:01.1 10 * [0x1800 - 0x181f] io PCI: 00:06.0 20 * [0x1820 - 0x182f] io PCI: 00:07.0 20 * [0x1830 - 0x183f] io PCI: 00:08.0 20 * [0x1840 - 0x184f] io PNP: 002e.7 62 * [0x1850 - 0x1857] io PNP: 002e.7 64 * [0x1858 - 0x185f] io PCI: 00:07.0 10 * [0x1860 - 0x1867] io PCI: 00:07.0 18 * [0x1868 - 0x186f] io PCI: 00:08.0 10 * [0x1870 - 0x1877] io PCI: 00:08.0 18 * [0x1878 - 0x187f] io PCI: 00:0a.0 14 * [0x1880 - 0x1887] io PCI: 00:07.0 14 * [0x1888 - 0x188b] io PCI: 00:07.0 1c * [0x188c - 0x188f] io PCI: 00:08.0 14 * [0x1890 - 0x1893] io PCI: 00:08.0 1c * [0x1894 - 0x1897] io PCI: 00:18.0 compute_resources_io: base: 1898 size: 2000 align: 12 gran: 12 limit: fff done PCI: 00:18.0 00 * [0x0 - 0x1fff] io PCI_DOMAIN: 0000 compute_resources_io: base: 2000 size: 2000 align: 12 gran: 0 limit: fff done PCI_DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff PCI: 00:18.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff PCI: 00:09.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 01:06.0 14 * [0x0 - 0x1ffffff] prefmem PCI: 00:09.0 compute_resources_prefmem: base: 2000000 size: 2000000 align: 25 gran: 20 limit: ffffffff done PCI: 00:0b.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:0b.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:0c.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:0c.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:0d.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:0d.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:0e.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:0e.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:09.0 24 * [0x0 - 0x1ffffff] prefmem PCI: 00:18.0 compute_resources_prefmem: base: 2000000 size: 2000000 align: 25 gran: 20 limit: ffffffff done PCI: 00:18.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:09.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 01:06.0 10 * [0x0 - 0xffffff] mem PCI: 01:06.0 30 * [0x1000000 - 0x100ffff] mem PCI: 00:09.0 compute_resources_mem: base: 1010000 size: 1100000 align: 24 gran: 20 limit: ffffffff done PCI: 00:0b.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:0b.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:0c.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:0c.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:0d.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:0d.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:0e.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:0e.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:09.0 20 * [0x0 - 0x10fffff] mem PCI: 00:01.0 14 * [0x1100000 - 0x1100fff] mem PCI: 00:02.0 10 * [0x1101000 - 0x1101fff] mem PCI: 00:04.0 18 * [0x1102000 - 0x1102fff] mem PCI: 00:07.0 24 * [0x1103000 - 0x1103fff] mem PCI: 00:08.0 24 * [0x1104000 - 0x1104fff] mem PCI: 00:0a.0 10 * [0x1105000 - 0x1105fff] mem PCI: 00:02.1 10 * [0x1106000 - 0x11060ff] mem PCI: 00:18.0 compute_resources_mem: base: 1106100 size: 1200000 align: 24 gran: 20 limit: ffffffff done PCI: 00:18.3 94 * [0x0 - 0x3ffffff] mem PCI: 00:18.0 02 * [0x4000000 - 0x5ffffff] prefmem PCI: 00:18.0 01 * [0x6000000 - 0x71fffff] mem PCI_DOMAIN: 0000 compute_resources_mem: base: 7200000 size: 7200000 align: 26 gran: 0 limit: ffffffff done avoid_fixed_resources: PCI_DOMAIN: 0000 avoid_fixed_resources:@PCI_DOMAIN: 0000 10000000 limit 00000fff avoid_fixed_resources:@PCI_DOMAIN: 0000 10000100 limit ffffffff constrain_resources: PCI_DOMAIN: 0000 constrain_resources: PCI: 00:18.0 constrain_resources: PCI: 00:00.0 constrain_resources: PCI: 00:01.0 constrain_resources: PNP: 002e.0 constrain_resources: PNP: 002e.1 constrain_resources: PNP: 002e.3 constrain_resources: PNP: 002e.4 constrain_resources: PNP: 002e.5 skipping PNP: 002e.5@71 fixed resource, size=0! constrain_resources: PNP: 002e.6 skipping PNP: 002e.6@71 fixed resource, size=0! constrain_resources: PNP: 002e.7 skipping PNP: 002e.7@25 fixed resource, size=0! skipping PNP: 002e.7@27 fixed resource, size=0! skipping PNP: 002e.7@b2 fixed resource, size=0! skipping PNP: 002e.7@ba fixed resource, size=0! skipping PNP: 002e.7@c0 fixed resource, size=0! skipping PNP: 002e.7@c2 fixed resource, size=0! skipping PNP: 002e.7@c8 fixed resource, size=0! skipping PNP: 002e.7@ca fixed resource, size=0! constrain_resources: PNP: 002e.8 constrain_resources: PNP: 002e.9 constrain_resources: PCI: 00:01.1 constrain_resources: PCI: 00:02.0 constrain_resources: PCI: 00:02.1 constrain_resources: PCI: 00:04.0 constrain_resources: PCI: 00:06.0 constrain_resources: PCI: 00:07.0 constrain_resources: PCI: 00:08.0 constrain_resources: PCI: 00:09.0 constrain_resources: PCI: 01:06.0 constrain_resources: PCI: 00:0a.0 constrain_resources: PCI: 00:0b.0 constrain_resources: PCI: 00:0c.0 constrain_resources: PCI: 00:0d.0 constrain_resources: PCI: 00:0e.0 constrain_resources: PCI: 00:18.1 constrain_resources: PCI: 00:18.2 constrain_resources: PCI: 00:18.3 avoid_fixed_resources2: PCI_DOMAIN: 0000@10000000 limit 00000fff lim->base 00000065 lim->limit 00000200 avoid_fixed_resources2: PCI_DOMAIN: 0000@10000100 limit ffffffff lim->base 000c0000 lim->limit febfffff Setting resources... PCI_DOMAIN: 0000 allocate_resources_io: base:65 size:2000 align:12 gran:0 limit:200 !! Resource didn't fit !! aligned base 1000 size 2000 limit 200 2fff needs to be <= 200 (limit) PCI: 00:18.0 00 * [0x0 - 0x1fff] io PCI: 00:18.0 00 * [0x0 - 0x1fff] io PCI_DOMAIN: 0000 allocate_resources_io: next_base: 65 size: 2000 align: 12 gran: 0 done PCI: 00:18.0 allocate_resources_io: base:0 size:2000 align:12 gran:12 limit:200 Assigned: PCI: 00:01.0 60 * [0x0 - 0xff] io !! Resource didn't fit !! aligned base 400 size 100 limit 200 4ff needs to be <= 200 (limit) PCI: 00:01.0 64 * [0x400 - 0x4ff] io PCI: 00:01.0 64 * [0x400 - 0x4ff] io !! Resource didn't fit !! aligned base 400 size 100 limit 200 4ff needs to be <= 200 (limit) PCI: 00:01.0 68 * [0x800 - 0x8ff] io PCI: 00:01.0 68 * [0x800 - 0x8ff] io !! Resource didn't fit !! aligned base 400 size 100 limit 200 4ff needs to be <= 200 (limit) PCI: 00:04.0 10 * [0xc00 - 0xcff] io PCI: 00:04.0 10 * [0xc00 - 0xcff] io !! Resource didn't fit !! aligned base 400 size 100 limit 200 4ff needs to be <= 200 (limit) PCI: 00:04.0 14 * [0x1000 - 0x10ff] io PCI: 00:04.0 14 * [0x1000 - 0x10ff] io !! Resource didn't fit !! aligned base 400 size 80 limit 200 47f needs to be <= 200 (limit) PCI: 00:01.0 10 * [0x1400 - 0x147f] io PCI: 00:01.0 10 * [0x1400 - 0x147f] io !! Resource didn't fit !! aligned base 400 size 40 limit 200 43f needs to be <= 200 (limit) PCI: 00:01.1 20 * [0x1480 - 0x14bf] io PCI: 00:01.1 20 * [0x1480 - 0x14bf] io !! Resource didn't fit !! aligned base 400 size 40 limit 200 43f needs to be <= 200 (limit) PCI: 00:01.1 24 * [0x14c0 - 0x14ff] io PCI: 00:01.1 24 * [0x14c0 - 0x14ff] io !! Resource didn't fit !! aligned base 400 size 20 limit 200 41f needs to be <= 200 (limit) PCI: 00:01.1 10 * [0x1800 - 0x181f] io PCI: 00:01.1 10 * [0x1800 - 0x181f] io !! Resource didn't fit !! aligned base 400 size 10 limit 200 40f needs to be <= 200 (limit) PCI: 00:06.0 20 * [0x1820 - 0x182f] io PCI: 00:06.0 20 * [0x1820 - 0x182f] io !! Resource didn't fit !! aligned base 400 size 10 limit 200 40f needs to be <= 200 (limit) PCI: 00:07.0 20 * [0x1830 - 0x183f] io PCI: 00:07.0 20 * [0x1830 - 0x183f] io !! Resource didn't fit !! aligned base 400 size 10 limit 200 40f needs to be <= 200 (limit) PCI: 00:08.0 20 * [0x1840 - 0x184f] io PCI: 00:08.0 20 * [0x1840 - 0x184f] io !! Resource didn't fit !! aligned base 400 size 8 limit 200 407 needs to be <= 200 (limit) PNP: 002e.7 62 * [0x1850 - 0x1857] io PNP: 002e.7 62 * [0x1850 - 0x1857] io !! Resource didn't fit !! aligned base 400 size 8 limit 200 407 needs to be <= 200 (limit) PNP: 002e.7 64 * [0x1858 - 0x185f] io PNP: 002e.7 64 * [0x1858 - 0x185f] io !! Resource didn't fit !! aligned base 400 size 8 limit 200 407 needs to be <= 200 (limit) PCI: 00:07.0 10 * [0x1860 - 0x1867] io PCI: 00:07.0 10 * [0x1860 - 0x1867] io !! Resource didn't fit !! aligned base 400 size 8 limit 200 407 needs to be <= 200 (limit) PCI: 00:07.0 18 * [0x1868 - 0x186f] io PCI: 00:07.0 18 * [0x1868 - 0x186f] io !! Resource didn't fit !! aligned base 400 size 8 limit 200 407 needs to be <= 200 (limit) PCI: 00:08.0 10 * [0x1870 - 0x1877] io PCI: 00:08.0 10 * [0x1870 - 0x1877] io !! Resource didn't fit !! aligned base 400 size 8 limit 200 407 needs to be <= 200 (limit) PCI: 00:08.0 18 * [0x1878 - 0x187f] io PCI: 00:08.0 18 * [0x1878 - 0x187f] io !! Resource didn't fit !! aligned base 400 size 8 limit 200 407 needs to be <= 200 (limit) PCI: 00:0a.0 14 * [0x1880 - 0x1887] io PCI: 00:0a.0 14 * [0x1880 - 0x1887] io !! Resource didn't fit !! aligned base 400 size 4 limit 200 403 needs to be <= 200 (limit) PCI: 00:07.0 14 * [0x1888 - 0x188b] io PCI: 00:07.0 14 * [0x1888 - 0x188b] io !! Resource didn't fit !! aligned base 400 size 4 limit 200 403 needs to be <= 200 (limit) PCI: 00:07.0 1c * [0x188c - 0x188f] io PCI: 00:07.0 1c * [0x188c - 0x188f] io !! Resource didn't fit !! aligned base 400 size 4 limit 200 403 needs to be <= 200 (limit) PCI: 00:08.0 14 * [0x1890 - 0x1893] io PCI: 00:08.0 14 * [0x1890 - 0x1893] io !! Resource didn't fit !! aligned base 400 size 4 limit 200 403 needs to be <= 200 (limit) PCI: 00:08.0 1c * [0x1894 - 0x1897] io PCI: 00:08.0 1c * [0x1894 - 0x1897] io PCI: 00:18.0 allocate_resources_io: next_base: 400 size: 2000 align: 12 gran: 12 done PCI: 00:09.0 allocate_resources_io: base:200 size:0 align:12 gran:12 limit:200 PCI: 00:09.0 allocate_resources_io: next_base: 200 size: 0 align: 12 gran: 12 done PCI: 00:0b.0 allocate_resources_io: base:200 size:0 align:12 gran:12 limit:200 PCI: 00:0b.0 allocate_resources_io: next_base: 200 size: 0 align: 12 gran: 12 done PCI: 00:0c.0 allocate_resources_io: base:200 size:0 align:12 gran:12 limit:200 PCI: 00:0c.0 allocate_resources_io: next_base: 200 size: 0 align: 12 gran: 12 done PCI: 00:0d.0 allocate_resources_io: base:200 size:0 align:12 gran:12 limit:200 PCI: 00:0d.0 allocate_resources_io: next_base: 200 size: 0 align: 12 gran: 12 done PCI: 00:0e.0 allocate_resources_io: base:200 size:0 align:12 gran:12 limit:200 PCI: 00:0e.0 allocate_resources_io: next_base: 200 size: 0 align: 12 gran: 12 done PCI_DOMAIN: 0000 allocate_resources_mem: base:f4000000 size:7200000 align:26 gran:0 limit:febfffff Assigned: PCI: 00:18.3 94 * [0xf4000000 - 0xf7ffffff] mem Assigned: PCI: 00:18.0 02 * [0xf8000000 - 0xf9ffffff] prefmem Assigned: PCI: 00:18.0 01 * [0xfa000000 - 0xfb1fffff] mem PCI_DOMAIN: 0000 allocate_resources_mem: next_base: fb200000 size: 7200000 align: 26 gran: 0 done PCI: 00:18.0 allocate_resources_prefmem: base:f8000000 size:2000000 align:25 gran:20 limit:febfffff Assigned: PCI: 00:09.0 24 * [0xf8000000 - 0xf9ffffff] prefmem PCI: 00:18.0 allocate_resources_prefmem: next_base: fa000000 size: 2000000 align: 25 gran: 20 done PCI: 00:09.0 allocate_resources_prefmem: base:f8000000 size:2000000 align:25 gran:20 limit:febfffff Assigned: PCI: 01:06.0 14 * [0xf8000000 - 0xf9ffffff] prefmem PCI: 00:09.0 allocate_resources_prefmem: next_base: fa000000 size: 2000000 align: 25 gran: 20 done PCI: 00:0b.0 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 limit:febfffff PCI: 00:0b.0 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 gran: 20 done PCI: 00:0c.0 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 limit:febfffff PCI: 00:0c.0 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 gran: 20 done PCI: 00:0d.0 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 limit:febfffff PCI: 00:0d.0 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 gran: 20 done PCI: 00:0e.0 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 limit:febfffff PCI: 00:0e.0 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 gran: 20 done PCI: 00:18.0 allocate_resources_mem: base:fa000000 size:1200000 align:24 gran:20 limit:febfffff Assigned: PCI: 00:09.0 20 * [0xfa000000 - 0xfb0fffff] mem Assigned: PCI: 00:01.0 14 * [0xfb100000 - 0xfb100fff] mem Assigned: PCI: 00:02.0 10 * [0xfb101000 - 0xfb101fff] mem Assigned: PCI: 00:04.0 18 * [0xfb102000 - 0xfb102fff] mem Assigned: PCI: 00:07.0 24 * [0xfb103000 - 0xfb103fff] mem Assigned: PCI: 00:08.0 24 * [0xfb104000 - 0xfb104fff] mem Assigned: PCI: 00:0a.0 10 * [0xfb105000 - 0xfb105fff] mem Assigned: PCI: 00:02.1 10 * [0xfb106000 - 0xfb1060ff] mem PCI: 00:18.0 allocate_resources_mem: next_base: fb106100 size: 1200000 align: 24 gran: 20 done PCI: 00:09.0 allocate_resources_mem: base:fa000000 size:1100000 align:24 gran:20 limit:febfffff Assigned: PCI: 01:06.0 10 * [0xfa000000 - 0xfaffffff] mem Assigned: PCI: 01:06.0 30 * [0xfb000000 - 0xfb00ffff] mem PCI: 00:09.0 allocate_resources_mem: next_base: fb010000 size: 1100000 align: 24 gran: 20 done PCI: 00:0b.0 allocate_resources_mem: base:febfffff size:0 align:20 gran:20 limit:febfffff PCI: 00:0b.0 allocate_resources_mem: next_base: febfffff size: 0 align: 20 gran: 20 done PCI: 00:0c.0 allocate_resources_mem: base:febfffff size:0 align:20 gran:20 limit:febfffff PCI: 00:0c.0 allocate_resources_mem: next_base: febfffff size: 0 align: 20 gran: 20 done PCI: 00:0d.0 allocate_resources_mem: base:febfffff size:0 align:20 gran:20 limit:febfffff PCI: 00:0d.0 allocate_resources_mem: next_base: febfffff size: 0 align: 20 gran: 20 done PCI: 00:0e.0 allocate_resources_mem: base:febfffff size:0 align:20 gran:20 limit:febfffff PCI: 00:0e.0 allocate_resources_mem: next_base: febfffff size: 0 align: 20 gran: 20 done Root Device assign_resources, bus 0 link: 0 0: mmio_basek=003d0000, basek=00000300, limitk=00100000 PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 amdk8_set_resource, enabling legacy VGA IO forwarding for PCI: 00:18.0 link 0x0 FATAL: stdin closed picocom v1.4 port is : /dev/ttyS0 flowcontrol : none baudrate is : 115200 parity is : none databits are : 8 escape is : C-a noinit is : no noreset is : no nolock is : no send_cmd is : ascii_xfr -s -v -l10 receive_cmd is : rz -vv

2 1

Here are the specs of my laptop:
by Brandon Dowdy 05 Mar '11

05 Mar '11

Name: Toshiba A135-S4437 CPU: Intel Core Duo Northbridge: Intel 945GM Southbridge: Intel ICH7-M EC: ENE KB910QF* Super I/O: I don't know Flash Chip: SST SST39VF080** Flash Chip Size: 1MB Flash Chip Supported: Yes Flash Chip Type: Parallel*** * This is from a schematic I looked at online. ** This flash chip is Parallel although the southbridge supports only FWH. This might be a flashrom bug or it might be that my laptop uses a special mechanism. *** That is explained on the Supported Hardware page of the flashrom wiki.

1 0

[PATCH] Move cmos.default handling to bootblock
by Patrick Georgi 04 Mar '11

04 Mar '11

The cmos.default code wasn't actually used so far, due to an oversight when forward-porting this feature from an old branch. - Extend walkcbfs' use by factoring out the stage handling into C code. - New sanitize_cmos() function that looks if CMOS data is invalid and cmos.default exists and if so overwrites CMOS with cmos.default data. - Use sanitize_cmos() in both bootblock implementations. - Drop the need to reboot after writing CMOS: CMOS wasn't used so far, so we can go on without a reboot. - Remove the restriction that cmos.default only works on CAR boards. - Always build in cmos.default support on boards that USE_OPTION_TABLE. Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> It's abuild tested and boot tested with emulation/qemu-x86. With this patch CMOS recovery only works on bootblock enabled boards/chipsets. Consider this an incentive to implement bootblock support where necessary :-) --- src/arch/x86/Kconfig | 6 ----- src/arch/x86/Makefile.bootblock.inc | 2 +- src/arch/x86/include/bootblock_common.h | 34 ++++++++++++++++++++++++++++-- src/arch/x86/init/bootblock_normal.c | 4 +++ src/arch/x86/init/bootblock_simple.c | 5 ++++ src/arch/x86/lib/walkcbfs.S | 10 +-------- src/pc80/mc146818rtc_early.c | 28 ------------------------- 7 files changed, 42 insertions(+), 47 deletions(-)

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[commit] r6432 - trunk/src/cpu/amd/model_fxx
by repository service 04 Mar '11

04 Mar '11

Author: jakllsch Date: Fri Mar 4 21:01:15 2011 New Revision: 6432 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6432 Log: Add P-states for select Socket 754 processors. States for AMA3000BEX5AR, SDA3100AIO3BX, and SDA3400AIO3BX are from AMD document 30430 3.51. States for ADA3200AIO4BX derived from SSDT of a MS-7135. States for TMDML34BKX5LD derived from legacy PowerNow! table of a MS-7135, and therefore lack accurate TDP information. Signed-off-by: Jonathan Kollasch <jakllsch(a)kollasch.net> Acked-by: Marc Jones <marcj303(a)gmail.com> Modified: trunk/src/cpu/amd/model_fxx/powernow_acpi.c Modified: trunk/src/cpu/amd/model_fxx/powernow_acpi.c ============================================================================== --- trunk/src/cpu/amd/model_fxx/powernow_acpi.c Fri Mar 4 18:09:21 2011 (r6431) +++ trunk/src/cpu/amd/model_fxx/powernow_acpi.c Fri Mar 4 21:01:15 2011 (r6432) @@ -563,6 +563,21 @@ {1800, 1200, 748}, {1000, 1100, 466}}}, {3000, 0x4, 0x10ff0, 0xa, 0xa, 670, {{1000, 1100, 210}}}, + /* AMA3000BEX5AR */ + {3000, 0x4, 0xf4a, 0xa, 0x0, 815, + {{1600, 1400, 570}, {800, 1100, 190}}}, + /* TMDML34BKX5LD, needs real TDP info */ + {34, 0xa, 0x20f42, 0xa, 0x0, 350, + {{1600, 1400, 340}, {800, 1000, 330}}}, + /* SDA3100AIO3BX */ + {3100, 0x26, 0x20fc2, 0xa, 0xa, 590, + {{1000, 1100, 217}}}, + /* SDA3400AIO3BX */ + {3400, 0x26, 0x20fc2, 0xc, 0xc, 590, + {{1800, 1350, 496}, {1000, 1100, 207}}}, + /* ADA3200AIO4BX */ + {3200, 0x4, 0x20fc2, 0xe, 0xe, 670, + {{2000, 1350, 647}, {1800, 1300, 548}, {1000, 1100, 275}}}, }; static int pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)

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[commit] r6431 - trunk/src/mainboard/amd/bimini_fam10
by repository service 04 Mar '11

04 Mar '11

Author: oxygene Date: Fri Mar 4 18:09:21 2011 New Revision: 6431 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6431 Log: Redo r6099 after copy&pasted code reintroduced DIMMx #defines Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Acked-by: Patrick Georgi <patrick(a)georgi-clan.de> Modified: trunk/src/mainboard/amd/bimini_fam10/romstage.c Modified: trunk/src/mainboard/amd/bimini_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/bimini_fam10/romstage.c Fri Mar 4 00:09:43 2011 (r6430) +++ trunk/src/mainboard/amd/bimini_fam10/romstage.c Fri Mar 4 18:09:21 2011 (r6431) @@ -49,6 +49,7 @@ #include "southbridge/amd/rs780/early_setup.c" #include "southbridge/amd/sb800/early_setup.c" #include "northbridge/amd/amdfam10/debug.c" +#include <spd.h> static void activate_spd_rom(const struct mem_controller *ctrl) { @@ -77,11 +78,6 @@ #define RC00 0 #define RC01 1 -#define DIMM0 0x50 -#define DIMM1 0x51 -#define DIMM2 0x52 -#define DIMM3 0x53 - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);

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coreboot March 2011