coreboot March 2011

coreboot@coreboot.org

71 participants
210 discussions

Microcode CPU writeup
by Rudolf Marek 13 Mar '11

13 Mar '11

Hi all, Would someone be interrested if I write something about microcoded CPUs controllers? Like the classic uCode ROM + ALU + Regs + IO unit? Thanks, Rudolf

4 3

Coreboot meeting @ Google, Sunday Mar. 13
by David Hendricks 12 Mar '11

12 Mar '11

Hey everyone, Stefan and I are going to be @ Google in Mountain View hacking on Coreboot this weekend, so we figured this would be a good time to host another users group meeting for those interested. This time we'll be hacking on our shiny new AMD Persimmons (Fam 14h / Fusion) dev boards which I have been assured by AMD are non-confidential so anyone curious can come in and poke at 'em. Or you can swing by Fry's before coming and pick up a generic E350 board, like the one Scott Duplichan recently ported: http://www.coreboot.org/pipermail/coreboot/2011-February/063737.html When: Sunday Mar. 13, noon to 8pm Where: 1950 Charleston Rd. in Mountain View [ Link<http://maps.google.com/maps?q=1950+charleston+rd+mountain+view+ca&ie=UTF8&h…> ], Alamitos conference room (1st floor, adjacent to lobby) Contact #: 408-512-3445 (last meeting's participants bcc'd since this is pretty short notice) -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc.

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Invite: Silicon Valley Coreboot Hackathon
by David Hendricks 12 Mar '11

12 Mar '11

Stefan mentioned that he knows several people who he has worked with in the area, and we're thinking it would be fun to get everyone together for a day of hacking on Coreboot and related projects such as Flashrom and SeaBIOS. So, I'd like to invite everyone to Google's beautiful campus in Mountain View for a day of Coreboot hacking, board porting, BIOS flashing, etc. We'll set a tentative date for Saturday the 29th of this month from noon 'till 8pm. We also have FlexyICE ROMulators and Dediprog SPI flash programmers so folks can worry less about bricking their system. Maybe Stefan can whip up a tutorial for newbies if there is particular interest in a specific area. If this sounds like something you'd like to participate in, please fill out the registration form at the URL below. It will help us to ensure we have adequate facilities reserved, equipment ready, visitor badges printed, and technically prepared for the topics of interest. We'll also send confirmation with detailed instructions on how to find the building / conference room to those who register. Registration form: https://spreadsheets.google.com/viewform?formkey=dGRab2s1VHRKNzRDX19pTVVrTj… -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc.

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Support for Core i3 and better
by Oleg Gvozdev 12 Mar '11

12 Mar '11

Hello Could you, please, advise what motherboard I should use with coreboot to support Core i3, i5 or i7 CPU ? And if any of these CPUs is not supported for now, where they will be supported? As an alternative: do you support Core 2 Duo and with what motheboard ? Thanks

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[The 604 CAR crusades][Master Yoda style] Preludium
by Alex G. 11 Mar '11

11 Mar '11

Hi everyone, The Tyan S2735 a Socket 604 (Intel) board it is which CAR it uses I found. "Why care I should?" yourself you ask. Because eight boards which socket 604 use, ROMCC they are. dell/s1850 intel/jarrell intel/xe7501devkit supermicro/x6dai_g supermicro/x6dhe_g supermicro/x6dhe_g2 supermicro/x6dhr_ig supermicro/x6dhr_ig2 This a bug to be considered is. Any 604 board as CAR work it should this means. Move them all to CAR we should. Alex

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Trying to port Intel Truxton to CAR
by Noé Rubinstein 10 Mar '11

10 Mar '11

NOT TO MERGE Signed-off-by: Noé Rubinstein <nrubinstein(a)proformatique.com> I'm trying to port Intel Truxton to CAR. So far, serial output works and Coreboot fails during SPD dump. If I remove the SPD dump, serial output doesn't work anymore (??). I have been told on the chan to post my current progress here. The patch is not meant to be used as-is, and contains a lot of unrelated code, as I was explicitly requested to leave things as they are. -- Noé Rubinstein Proformatique (groupe Avencall) - XiVO IPBX OpenHardware 10 bis, rue Lucien VOILIN - 92800 Puteaux Tél. : +33 (0)1 41 38 99 60 ext 123 Fax. : +33 (0)1 41 38 99 70

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Intel 855GM status?
by Peter James 10 Mar '11

10 Mar '11

Just wondering if any further progress has been made to the intel 82855 chipset which as far as I can tell is in a WIP status. Has anyone been able to get this working successfully? I see someone is working on a similar chipset 854gme. I own an Acer tm 291lci which has this chipset and would be willing to test.. Many thanks in advance, Peter

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Support fot UMC UM8670 Super IO
by Anup Rao 10 Mar '11

10 Mar '11

Hi Everyone, I want to install Coreboot on an old Cyrix 6x86 machine. It comes equipped with a M558 motherboard. The AMI BIOS string ID is 51-0830-001437-00111111-071595-UT801X-001_10_UTRON-F Further details can be found on this webpage: http://motherboards.mbarron.net/models/pcchips/m558.htm The Super IO chip on it is a UMC UM8670. The Superiotool currently does not detect/dump this chip (exactly as mentioned on the supported HW page). Also, It is currently not listed on the supported chipsets page for Coreboot. I am unable to find any further information on the web for this chip. I am hoping that this chip is in someway a clone or identical to other SuperIO chips. Can anyone confirm if it is supported by Coreboot? If not can anyone point me to a location where information on this chip could be available ? Regards, Anup

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[commit] r6440 - in trunk/util/nvramtool: . accessors
by repository service 09 Mar '11

09 Mar '11

Author: oxygene Date: Thu Mar 10 08:52:02 2011 New Revision: 6440 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6440 Log: nvramtool: Move code so it has access to the right data structures Signed-off-by: Mathias Krause <mathias.krause(a)secunet.com> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/util/nvramtool/accessors/layout-bin.c trunk/util/nvramtool/lbtable.c trunk/util/nvramtool/lbtable.h Modified: trunk/util/nvramtool/accessors/layout-bin.c ============================================================================== --- trunk/util/nvramtool/accessors/layout-bin.c Wed Mar 9 00:01:46 2011 (r6439) +++ trunk/util/nvramtool/accessors/layout-bin.c Thu Mar 10 08:52:02 2011 (r6440) @@ -84,6 +84,20 @@ } /**************************************************************************** + * get_layout_from_cmos_table + * + * Find the CMOS table which is stored within the coreboot table and set the + * global variable cmos_table to point to it. + ****************************************************************************/ +void get_layout_from_cmos_table(void) +{ + get_lbtable(); + cmos_table = (const struct cmos_option_table *) + find_lbrec(LB_TAG_CMOS_OPTION_TABLE); + process_layout(); +} + +/**************************************************************************** * process_cmos_table * * Extract layout information from the CMOS option table and store it in our Modified: trunk/util/nvramtool/lbtable.c ============================================================================== --- trunk/util/nvramtool/lbtable.c Wed Mar 9 00:01:46 2011 (r6439) +++ trunk/util/nvramtool/lbtable.c Thu Mar 10 08:52:02 2011 (r6440) @@ -63,7 +63,6 @@ unsigned long end, int *bad_header_count, int *bad_table_count); -static const struct lb_record *find_lbrec(uint32_t tag); static const char *lbrec_tag_to_str(uint32_t tag); static void memory_print_fn(const struct lb_record *rec); static void mainboard_print_fn(const struct lb_record *rec); @@ -215,11 +214,6 @@ /* Pointer to coreboot table. */ static const struct lb_header *lbtable = NULL; -/* The CMOS option table is located within the coreboot table. It tells us - * where the CMOS parameters are located in the nonvolatile RAM. - */ -static const struct cmos_option_table *cmos_table = NULL; - static const hexdump_format_t format = { 12, 4, " ", " | ", " ", " | ", '.' }; @@ -303,21 +297,6 @@ } /**************************************************************************** - * get_layout_from_cmos_table - * - * Find the CMOS table which is stored within the coreboot table and set the - * global variable cmos_table to point to it. - ****************************************************************************/ -void get_layout_from_cmos_table(void) -{ - - get_lbtable(); - cmos_table = (const struct cmos_option_table *) - find_lbrec(LB_TAG_CMOS_OPTION_TABLE); - process_layout(); -} - -/**************************************************************************** * dump_lbtable * * Do a low-level dump of the coreboot table. @@ -538,7 +517,7 @@ * Find the record in the coreboot table that matches 'tag'. Return pointer * to record on success or NULL if record not found. ****************************************************************************/ -static const struct lb_record *find_lbrec(uint32_t tag) +const struct lb_record *find_lbrec(uint32_t tag) { const char *p; uint32_t bytes_processed; Modified: trunk/util/nvramtool/lbtable.h ============================================================================== --- trunk/util/nvramtool/lbtable.h Wed Mar 9 00:01:46 2011 (r6439) +++ trunk/util/nvramtool/lbtable.h Thu Mar 10 08:52:02 2011 (r6440) @@ -39,6 +39,7 @@ void dump_lbtable(void); void list_lbtable_choices(void); void list_lbtable_item(const char item[]); +const struct lb_record *find_lbrec(uint32_t tag); void process_layout(void); #endif /* LBTABLE_H */

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[PATCH] nvramtool: Fix CMOS layout initialization using option table
by Mathias Krause 09 Mar '11

09 Mar '11

Move get_layout_from_cmos_table() to accessors/layout-bin.c so process_layout() will do its check against the right cmos_table. This bug was introduced with r6314.

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coreboot March 2011